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Fix divison by zero when the timing cost is zero #3194

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Merged
merged 2 commits into from
Jul 8, 2025
Merged

Fix divison by zero when the timing cost is zero #3194

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19885db
avoid a division by zero when the timing cost is zero
soheilshahrouz Jul 8, 2025
61539f2
update golden results for strong_clock_aliases_set_delay
soheilshahrouz Jul 8, 2025
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11 changes: 4 additions & 7 deletions vpr/src/place/placer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -118,18 +118,17 @@ Placer::Placer(const Netlist<>& net_list,

// Gets initial cost and loads bounding boxes.
costs_.bb_cost = net_cost_handler_.comp_bb_cost(e_cost_methods::NORMAL).first;
costs_.bb_cost_norm = 1 / costs_.bb_cost;

if (placer_opts.place_algorithm.is_timing_driven()) {
alloc_and_init_timing_objects_(net_list, analysis_opts);
} else {
VTR_ASSERT(placer_opts.place_algorithm == e_place_algorithm::BOUNDING_BOX_PLACE);
// Timing cost and normalization factors are not used
constexpr double INVALID_COST = std::numeric_limits<double>::quiet_NaN();
costs_.timing_cost = INVALID_COST;
costs_.timing_cost_norm = INVALID_COST;
// Timing cost is not used
costs_.timing_cost = std::numeric_limits<double>::quiet_NaN();
}

costs_.update_norm_factors();

if (noc_opts.noc) {
VTR_ASSERT(noc_cost_handler_.has_value());

Expand Down Expand Up @@ -215,8 +214,6 @@ void Placer::alloc_and_init_timing_objects_(const Netlist<>& net_list,
write_setup_timing_graph_dot(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH) + std::string(".dot"),
*timing_info_, debug_tnode);
}

costs_.timing_cost_norm = 1 / costs_.timing_cost;
}

void Placer::check_place_() {
Expand Down
4 changes: 2 additions & 2 deletions .../regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.31 vpr 58.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 59592 2 2 22 24 2 4 6 4 4 16 clb auto 19.5 MiB 0.00 8 8 15 5 7 3 58.2 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.01 3.4522e-05 2.8944e-05 0.000260301 0.000230358 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00183444 0.00168689 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00144073 0.00134886
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.23 vpr 58.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-13290-g19885dbb2 release VTR_ASSERT_LEVEL=3 debug_logging GNU 11.4.0 on Linux-4.15.0-213-generic x86_64 2025-07-08T18:21:59 pt-372-11 /home/soheil/vpr_repos/vtr_flow 59704 2 2 22 24 2 4 6 4 4 16 clb auto 18.6 MiB 0.00 8 7 15 8 4 3 58.3 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.01 2.0714e-05 1.3783e-05 0.00019331 0.000157289 -1 -1 -1 -1 6 8 3 72000 36000 4025.56 251.598 0.00 0.00075902 0.000638592 660 1032 -1 7 3 5 5 233 157 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.000441175 0.000384118
4 changes: 2 additions & 2 deletions ...ession_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.32 vpr 58.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 59756 2 2 22 24 2 4 6 4 4 16 clb auto 19.9 MiB 0.00 8 8 15 5 7 3 58.4 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.01 3.4498e-05 2.8622e-05 0.000252067 0.000222891 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.00 0.00172098 0.0015803 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00159955 0.00147715
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.22 vpr 58.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-13290-g19885dbb2 release VTR_ASSERT_LEVEL=3 debug_logging GNU 11.4.0 on Linux-4.15.0-213-generic x86_64 2025-07-08T18:21:59 pt-372-11 /home/soheil/vpr_repos/vtr_flow 60048 2 2 22 24 2 4 6 4 4 16 clb auto 19.1 MiB 0.00 8 7 15 8 4 3 58.6 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.01 3.4629e-05 2.3788e-05 0.000211272 0.000171138 -1 -1 -1 -1 6 8 3 72000 36000 4025.56 251.598 0.00 0.000731131 0.000609405 660 1032 -1 7 3 5 5 233 157 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.000462807 0.0004042