Skip to content

Fix divison by zero when the timing cost is zero #3194

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Jul 8, 2025

Conversation

soheilshahrouz
Copy link
Contributor

@soheilshahrouz soheilshahrouz commented Jul 8, 2025

Placer::alloc_and_init_timing_objects_ used to update timing_cost_norm without checking timing_cost is zero. Now, t_placer_costs::update_norm_factors() is called to set timing_cost_norm to a large number instead of infinity.

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Jul 8, 2025
@soheilshahrouz soheilshahrouz requested a review from amin1377 July 8, 2025 21:54
@soheilshahrouz soheilshahrouz changed the title [WIP] Fix divison by zero when the timing cost is zero Fix divison by zero when the timing cost is zero Jul 8, 2025
@soheilshahrouz soheilshahrouz merged commit 5bd2d04 into master Jul 8, 2025
30 checks passed
@soheilshahrouz soheilshahrouz deleted the fix_div_by_zero_timing_cost branch July 8, 2025 23:02
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
lang-cpp C/C++ code VPR VPR FPGA Placement & Routing Tool
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants