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[Coalesce]: Enhance the Intel coalescing pass to support while loops. #4290

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Merged
merged 16 commits into from
May 26, 2025
Merged

[Coalesce]: Enhance the Intel coalescing pass to support while loops. #4290

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4384ad1
Ensure block ptr is created with the same layout as the descriptor_lo…
etiotto May 9, 2025
f0ce91c
Remove naked print and unnecessary headers
etiotto May 9, 2025
04f1c1d
Merge remote-tracking branch 'origin/main' into etiotto.tensor_desc_t…
etiotto May 14, 2025
3543e6e
WIP: TensorDescToBlockPtr updates
etiotto May 14, 2025
38ef6c3
WIP: RemoveLAuoyutConversion improvement for tt.advance operation
etiotto May 15, 2025
e4d5d7d
Merge remote-tracking branch 'origin/main' into etiotto.tensor_desc_t…
etiotto May 15, 2025
9eb16ec
WIP: TensorDescToBlockPtr updates
etiotto May 15, 2025
7f9bbc9
WIP: TensorDescToBlockPtr updates
etiotto May 15, 2025
f6ed66a
WIP: TensorDescToBlockPtr updates
etiotto May 16, 2025
cb4bb2e
WIP: TensorDescToBlockPtr updates
etiotto May 20, 2025
f6ce50a
Merge branch 'main' into etiotto.tensor_desc_to_block_ptr.1
etiotto May 20, 2025
d1c3d0b
Enhance coalescing pass to support scf::While loop
etiotto May 23, 2025
1f4ec74
Merge branch 'main' into etiotto.coalesce.1
etiotto May 23, 2025
1cc7fd5
Merge branch 'main' into etiotto.coalesce.1
etiotto May 23, 2025
d4c2655
Remove unnecessary changes
etiotto May 23, 2025
65dc3c3
Address code review comments
etiotto May 26, 2025
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39 changes: 39 additions & 0 deletions test/TritonIntelGPU/coalesce.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -472,6 +472,7 @@ module attributes {ttig.target_arch = "spir64", "ttg.num-ctas" = 1 : i32, "ttg.n
}

// -----

#blocked = #ttg.blocked<{sizePerThread = [1, 1, 1], threadsPerWarp = [2, 4, 4], warpsPerCTA = [2, 1, 1], order = [2, 1, 0]}>
#blocked1 = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [8, 4], warpsPerCTA = [2, 1], order = [1, 0]}>
#blocked2 = #ttg.blocked<{sizePerThread = [1, 1, 1], threadsPerWarp = [8, 1, 4], warpsPerCTA = [2, 1, 1], order = [2, 1, 0]}>
Expand Down Expand Up @@ -522,3 +523,41 @@ module attributes {ttig.min_sg_size = 16 : i32, ttig.target_arch = "spir64", "tt
tt.return
}
}

// -----

// COM: Ensure layout propagation works for a while loop.
#blocked = #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 4], order = [1, 0]}>
module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32} {
// CHECK: [[BLOCKED_LAYOUT:#.*]] = #ttg.blocked<{sizePerThread = [1, 4], threadsPerWarp = [1, 32], warpsPerCTA = [4, 1], order = [1, 0]}>
// CHECK: kernel_make_tensor_descriptor_loop_carried
tt.func public @kernel_make_tensor_descriptor_loop_carried(%arg0: !tt.ptr<f32> {tt.divisibility = 16 : i32}, %arg1: i64 {tt.divisibility = 16 : i32}, %arg2: i64 {tt.divisibility = 16 : i32}) {
%c1_i64 = arith.constant 1 : i64
%c0_i32 = arith.constant 0 : i32
%c2_i32 = arith.constant 2 : i32
// CHECK: [[PTR:%.*]] = tt.make_tensor_ptr {{.*}} {order = array<i32: 1, 0>} : <tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>
// CHECK: [[ADV_PTR:%.*]] = tt.advance [[PTR]], {{.*}} : <tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>
%4 = tt.make_tensor_ptr %arg0, [%arg1, %arg2], [%arg2, %c1_i64], [%c0_i32, %c0_i32] {order = array<i32: 1, 0>} : <tensor<8x128xf32, #blocked>>
%5 = tt.advance %4, [%c2_i32, %c0_i32] : <tensor<8x128xf32, #blocked>>
%7 = arith.cmpi slt, %arg1, %arg2 : i64
// CHECK: scf.while ([[ARG3:%.*]] = [[PTR]], [[ARG4:%.*]] = [[ADV_PTR]]) : (!tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>, !tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>) -> (!tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>, !tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>) {
%6:2 = scf.while (%arg3 = %4, %arg4 = %5) : (!tt.ptr<tensor<8x128xf32, #blocked>>, !tt.ptr<tensor<8x128xf32, #blocked>>) -> (!tt.ptr<tensor<8x128xf32, #blocked>>, !tt.ptr<tensor<8x128xf32, #blocked>>) {
// CHECK: scf.condition({{.*}}) [[ARG3]], [[ARG4]] : !tt.ptr<tensor<8x128xf32, #blocked>>, !tt.ptr<tensor<8x128xf32, #blocked>>
scf.condition(%7) %arg3, %arg4 : !tt.ptr<tensor<8x128xf32, #blocked>>, !tt.ptr<tensor<8x128xf32, #blocked>>
} do {
// CHECK: ^bb0({{.*}}: !tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>, {{.*}}: !tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>):
^bb0(%arg3: !tt.ptr<tensor<8x128xf32, #blocked>>, %arg4: !tt.ptr<tensor<8x128xf32, #blocked>>):
// CHECK: [[PTR1:%.*]] = arith.select {{.*}} : !tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>
// CHECK: [[PTR2:%.*]] = tt.advance [[PTR1]], {{.*}} : <tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>
// CHECK: [[LOAD:%.*]] = tt.load [[PTR1]] : !tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>
// CHECK: tt.store [[PTR2]], {{.*}} : !tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>
// CHECK: scf.yield [[PTR1]], [[PTR2]] : !tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>, !tt.ptr<tensor<8x128xf32, [[BLOCKED_LAYOUT]]>>
%12 = arith.select %7, %arg4, %arg3 : !tt.ptr<tensor<8x128xf32, #blocked>>
%13 = tt.advance %12, [%c0_i32, %c2_i32] : <tensor<8x128xf32, #blocked>>
%15 = tt.load %12 : !tt.ptr<tensor<8x128xf32, #blocked>>
tt.store %13, %15 : !tt.ptr<tensor<8x128xf32, #blocked>>
scf.yield %12, %13 : !tt.ptr<tensor<8x128xf32, #blocked>>, !tt.ptr<tensor<8x128xf32, #blocked>>
}
tt.return
}
}
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