-
Notifications
You must be signed in to change notification settings - Fork 74
Pull requests: intel/intel-xpu-backend-for-triton
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
Fix clang error: add explicit braces to avoid dangling else
#5301
opened Oct 14, 2025 by
AndreyPavlenko
Loading…
[CI][benchmarks] Longer warmup for flash attention and
gemm_preop_exp
#5293
opened Oct 13, 2025 by
Egor-Krivov
Loading…
Integrate PTI callback interface and build it from sources
#5289
opened Oct 10, 2025 by
anmyachev
Loading…
[Draft] Add a new stage to generate
zebin
to align CUDA stages in triton.compile
#5189
opened Sep 25, 2025 by
chengjunlu
•
Draft
[Draft] Support the globaltimer and smid on Intel Arch
#4816
opened Jul 31, 2025 by
chengjunlu
•
Draft
A tracking utility for gathering the compile and/or runtime time, size, profiling and other statistics
#4777
opened Jul 25, 2025 by
AndreyPavlenko
Loading…
[LoadStoreToLLVM] Refactor the 2D block load lowering.
#4615
opened Jul 4, 2025 by
chengjunlu
Loading…
[BACKEND] Enhance the remove layout implementation to reduce the duplicated values with different layout in scf.for.
#4527
opened Jun 18, 2025 by
chengjunlu
Loading…
Clean up Intel specific code in the common TritonGPU dialect source file.
upstream: triton
#4469
opened Jun 10, 2025 by
chengjunlu
•
Draft
Previous Next
ProTip!
Follow long discussions with comments:>50.