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[WIP] Switching from Synlig to Yosys-Slang #3181

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@loglav03 loglav03 commented Jul 3, 2025

Description

Replaced Synlig with the Yosys-Slang plugin for Yosys for reading SystemVerilog.

Related Issue

  1. System Verilog support is broken due to compilation error in F4PGA plugin #2821
  2. Embed slang-yosys plugin as a SystemVerilog frontend for yosys #3108

Motivation and Context

Synlig has a lot of overhead when building with the vtr build system leading to issues when building in CI and sometimes locally. Synlig is also poorly maintained. Yosys-Slang has significantly less overhead, can easily be implemented as a plugin for yosys, and is regularly maintained.

How Has This Been Tested?

Has been tested with the vtr_reg_system_verilog tests [PASSED]
Going to test with extra tests from the Yosys-Slang repo: https://github.com/povik/yosys-slang/tree/master/tests

Types of changes

  • [ x] Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • [ x] My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

loglav03 and others added 5 commits June 26, 2025 17:38
…stall with vtr when enabled with the cmake parameter -DSLANG_SYSTEMVERILOG=ON
…ultiple .sv files instead of single flattened .sv files (with the exception of the f4pga_pulse_width_led test since it uses .v files instead of .sv)
@github-actions github-actions bot added lang-cpp C/C++ code build Build system lang-python Python code lang-make CMake/Make code external_libs labels Jul 3, 2025
@github-actions github-actions bot added the infra Project Infrastructure label Jul 3, 2025
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