Add Zilsd, Zclsd, Zcmp to Extension Bitmask #104
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Signed-off-by: Luke Wren <[email protected]>
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@Wren6991 , do you have the patch for LLVM or GCC toolchains? |
lenary
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As proposed in riscv-non-isa/riscv-c-api-doc#104 No real compiler-rt implementation, as these are not exposed by Linux.
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LLVM Implementation is here: llvm/llvm-project#135197 |
lenary
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As proposed in riscv-non-isa/riscv-c-api-doc#104 No real compiler-rt implementation, as these are not exposed by Linux.
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The LLVM change was approved, and I have merged it. |
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As proposed in riscv-non-isa/riscv-c-api-doc#104 No real compiler-rt implementation, as these are not exposed by Linux.
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As proposed in riscv-non-isa/riscv-c-api-doc#104 No real compiler-rt implementation, as these are not exposed by Linux.
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As proposed in riscv-non-isa/riscv-c-api-doc#104 No real compiler-rt implementation, as these are not exposed by Linux.
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As proposed in riscv-non-isa/riscv-c-api-doc#104 No real compiler-rt implementation, as these are not exposed by Linux.
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As proposed in riscv-non-isa/riscv-c-api-doc#104 No real compiler-rt implementation, as these are not exposed by Linux.
kito-cheng
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As proposed in riscv-non-isa/riscv-c-api-doc#104 No real compiler-rt implementation, as these are not exposed by Linux.
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Zilsd, Zclsd and Zcmp are ratified standard extensions which lack bit assignments. I've just appended them to the end.
Note that Zcmop, which is already listed next to the non-Zcmp Zce extensions, is its own extension, not a typo for Zcmp.
For context, I'm considering exposing this bit mask through a custom M-mode CSR on an embedded-class core to list hardware capabilities with finer granularity than
misa, but less complexity than the configuration struct or device tree. I implement the three extensions added by this PR.