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[RISCV] Allocate Feature Bits for Zilsd/Zclsd/Zcmp
As proposed in riscv-non-isa/riscv-c-api-doc#104 No real compiler-rt implementation, as these are not exposed by Linux.
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2 files changed

+12
-3
lines changed

2 files changed

+12
-3
lines changed

compiler-rt/lib/builtins/cpu_model/riscv.c

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Original file line numberDiff line numberDiff line change
@@ -128,6 +128,12 @@ struct {
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#define ZCMOP_BITMASK (1ULL << 6)
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#define ZAWRS_GROUPID 1
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#define ZAWRS_BITMASK (1ULL << 7)
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#define ZILSD_GROUPID 1
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#define ZILSD_BITMASK (1ULL << 8)
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#define ZCLSD_GROUPID 1
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#define ZCLSD_BITMASK (1ULL << 9)
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#define ZCMP_GROUPID 1
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#define ZCMP_BITMASK (1ULL << 10)
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#if defined(__linux__)
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llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -178,7 +178,8 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
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def FeatureStdExtZilsd
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: RISCVExtension<1, 0,
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"Load/Store Pair Instructions">;
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"Load/Store Pair Instructions">,
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RISCVExtensionBitmask<1, 8>;
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def HasStdExtZilsd : Predicate<"Subtarget->hasStdExtZilsd()">,
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AssemblerPredicate<(all_of FeatureStdExtZilsd),
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"'Zilsd' (Load/Store pair instructions)">;
@@ -411,15 +412,17 @@ def FeatureStdExtZcf
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def FeatureStdExtZclsd
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: RISCVExtension<1, 0,
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"Compressed Load/Store Pair Instructions",
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[FeatureStdExtZilsd, FeatureStdExtZca]>;
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[FeatureStdExtZilsd, FeatureStdExtZca]>,
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RISCVExtensionBitmask<1, 9>;
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def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd()">,
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AssemblerPredicate<(all_of FeatureStdExtZclsd),
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"'Zclsd' (Compressed Load/Store pair instructions)">;
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def FeatureStdExtZcmp
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: RISCVExtension<1, 0,
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"sequenced instructions for code-size reduction",
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[FeatureStdExtZca]>;
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[FeatureStdExtZca]>,
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RISCVExtensionBitmask<1, 10>;
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def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
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AssemblerPredicate<(all_of FeatureStdExtZcmp),
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"'Zcmp' (sequenced instructions for code-size reduction)">;

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