Add RVC GPR Pair Constraint - cR
#102
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This follows the notion of using `c` as a prefix to mean "RVC-compatible", and `R` to mean "GPR Pair". The Zclsd specification adds registers with this constraint, in particular the `c.ld` and `c.sd` instructions need it.
This denotes RVC-compatible GPR Pairs, which are used by the Zclsd extension. C API PR: riscv-non-isa/riscv-c-api-doc#102
This denotes RVC-compatible GPR Pairs, which are used by the Zclsd extension. C API PR: riscv-non-isa/riscv-c-api-doc#102
This denotes RVC-compatible GPR Pairs, which are used by the Zclsd extension. C API PR: riscv-non-isa/riscv-c-api-doc#102
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LGTM, it's reasonable and also trivial to implement, I saw you already implemented in LLVM and I believe it's also trivial to support on GCC side, although it's kinda late to GCC since it's become bug fix only development stage, so that may defer to GCC 16, but I think it's fine to moving forward here.
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Sorry for missing your release window :( I figured this would be uncontroversial enough that I could add it to LLVM for our release. |
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We discussed this briefly in today's SIG Toolchain call and agreed to land this. |
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The patch has been sent, and will land once CI pass: https://gcc.gnu.org/pipermail/gcc-patches/2025-May/683737.html |
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Thanks @kito-cheng! |
This commit introduces a new operand constraint `cR` for the RISC-V architecture, which allows the use of an even-odd RVC general purpose register (x8-x15) in inline asm. Ref: riscv-non-isa/riscv-c-api-doc#102 gcc/ChangeLog: * config/riscv/constraints.md (cR): New constraint. * doc/md.texi (Machine Constraints::RISC-V): Document the new cR constraint. gcc/testsuite/ChangeLog: * gcc.target/riscv/constraint-cR-pair.c: New test case.
This follows the notion of using
cas a prefix to mean "RVC-compatible", andRto mean "even-odd GPR Pair".The Zclsd specification adds registers with this constraint, in particular the
c.ldandc.sdinstructions need it.