RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose register
(x8-x15) in inline asm.

Ref: riscv-non-isa/riscv-c-api-doc#102

gcc/ChangeLog:

	* config/riscv/constraints.md (cR): New constraint.
	* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
	constraint.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/constraint-cR-pair.c: New test case.

Author: kito-cheng

gcc/config/riscv/constraints.md

@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : (TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"

gcc/doc/md.texi

@@ -3694,6 +3694,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 

gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c

@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+    __asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}