Repositories list

• sv-tests-results

  Public
  Output of the sv-tests runs.

  HTML

  •6•7•0•0•Updated Feb 1, 2026Feb 1, 2026

• caliptra-mcu-sw

  Public

  chipsalliance/caliptra-mcu-sw’s past year of commit activity
  Caliptra MCU Software

  Rust

  •

  Apache License 2.0

  •40•21•120•28•Updated Jan 31, 2026Jan 31, 2026

• verilator

  Public

  chipsalliance/verilator’s past year of commit activity
  Verilator open-source SystemVerilog simulator and lint system

  SystemVerilog

  •747•41•0•0•Updated Jan 31, 2026Jan 31, 2026

• t1

  Public
  Scala

  •

  Apache License 2.0

  •44•308•18•29•Updated Jan 31, 2026Jan 31, 2026

• chisel

  Public

  chipsalliance/chisel’s past year of commit activity
  Chisel: A Modern Hardware Design Language

  scalachip-generatorchisel+ 4rtlchisel3firrtlverilog

  Scala

  •

  Apache License 2.0

  •646•4.6k•351•142•Updated Jan 31, 2026Jan 31, 2026

• caliptra-dpe

  Public
  High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

  Rust

  •

  Apache License 2.0

  •29•20•19•8•Updated Jan 31, 2026Jan 31, 2026

• caliptra-rtl

  Public

  chipsalliance/caliptra-rtl’s past year of commit activity
  HW Design Collateral for Caliptra RoT IP

  SystemVerilog

  •

  Apache License 2.0

  •75•127•101•26•Updated Jan 31, 2026Jan 31, 2026

• caliptra-sw

  Public

  chipsalliance/caliptra-sw’s past year of commit activity
  Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

  Rust

  •

  Apache License 2.0

  •84•136•225•82•Updated Jan 31, 2026Jan 31, 2026

• sv-tests

  Public

  chipsalliance/sv-tests’s past year of commit activity
  Test suite designed to check compliance with the SystemVerilog standard.

  rtlverilogsystemverilog+ 3hdlcompliance-testingsymbiflow

  SystemVerilog

  •

  ISC License

  •86•357•47•29•Updated Jan 30, 2026Jan 30, 2026

• caliptra-infra

  Public
  Various tools used for Caliptra's Continuous Integration flows

  SystemVerilog

  •

  Apache License 2.0

  •2•1•5•2•Updated Jan 30, 2026Jan 30, 2026

• adams-bridge

  Public
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)

  cryptographydigital-signaturelattice+ 2pqcml-dsa-87

  SystemVerilog

  •

  Apache License 2.0

  •10•43•19•3•Updated Jan 30, 2026Jan 30, 2026

• chisel-template

  Public template
  A template project for beginning new Chisel work

  Shell

  •

  The Unlicense

  •197•690•15•3•Updated Jan 29, 2026Jan 29, 2026

• i3c-core

  Public
  SystemVerilog

  •

  Apache License 2.0

  •20•43•17•2•Updated Jan 29, 2026Jan 29, 2026

• OmnixtendEndpoint

  Public
  Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

  asicfpgabluespec+ 3coherencetilelinkomnixtend

  Bluespec

  •

  Apache License 2.0

  •5•19•0•0•Updated Jan 29, 2026Jan 29, 2026

• Caliptra

  Public
  Caliptra IP and firmware for integrated Root of Trust block

  Apache License 2.0

  •57•375•70•12•Updated Jan 27, 2026Jan 27, 2026

• caliptra-ss

  Public
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

  securityrotocp+ 3root-of-trustcaliptraopencomputeproject

  SystemVerilog

  •

  Apache License 2.0

  •34•36•68•9•Updated Jan 22, 2026Jan 22, 2026

• rvdecoderdb

  Public
  The Scala parser to parse riscv/riscv-opcodes generate

  Nix

  •11•22•1•1•Updated Jan 21, 2026Jan 21, 2026

• caliptra-web

  Public
  Astro

  •

  Apache License 2.0

  •6•0•0•0•Updated Jan 20, 2026Jan 20, 2026

• chips-alliance-website

  Public
  SCSS

  •

  MIT License

  •7•4•8•8•Updated Jan 16, 2026Jan 16, 2026

• tac

  Public
  CHIPS Alliance Technical Advisory Council

  Apache License 2.0

  •25•7•17•3•Updated Jan 15, 2026Jan 15, 2026

• rocket-pcblib

  Public
  Apache License 2.0

  •1•2•0•0•Updated Jan 10, 2026Jan 10, 2026

• firtool-resolver

  Public
  Shell

  •2•5•0•1•Updated Jan 9, 2026Jan 9, 2026

• rocket-chip

  Public
  Rocket Chip Generator

  scalarocket-chipchip-generator+ 3chiselriscvrtl

  Scala

  •

  Other

  •1.2k•3.7k•258•70•Updated Jan 9, 2026Jan 9, 2026

• firrtl-spec

  Public
  The specification for the FIRRTL language

  TeX

  •31•62•25•19•Updated Jan 9, 2026Jan 9, 2026

• Cores-VeeR-EL2

  Public
  VeeR EL2 Core

  fpgaprocessorriscv+ 11rtlrisc-vopen-source-hardwarefusesocverilatorriscv32western-digital+ 4

  SystemVerilog

  •

  Apache License 2.0

  •96•316•32•5•Updated Dec 29, 2025Dec 29, 2025

• verible

  Public
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  productivityparserformatter+ 14analysisstyle-linterlinterlanguage-server-protocolsyntax-treelexeryacc+ 7

  C++

  •

  Other

  •268•1.8k•556•29•Updated Dec 22, 2025Dec 22, 2025

• guineveer

  Public
  https://chipsalliance.github.io/guineveer/

  C

  •

  Apache License 2.0

  •3•4•0•0•Updated Dec 17, 2025Dec 17, 2025

• espresso

  Public
  C

  •19•41•7•0•Updated Dec 5, 2025Dec 5, 2025

• diplomacy

  Public
  Scala

  •

  Apache License 2.0

  •19•23•9•2•Updated Dec 4, 2025Dec 4, 2025

• riscv-vector-tests

  Public
  Unit tests generator for RVV 1.0

  generatorspikeriscv+ 2testsuitervv

  Go

  •

  Apache License 2.0

  •33•100•12•1•Updated Nov 11, 2025Nov 11, 2025