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Confusing bundle connection behavior with SRAM API

Status: Open.

#4945 In chipsalliance/chisel;

· tymcauley opened on Jun 2, 2025

Naming Prefix Preserved Across Failing Tests

bug

Status: Open.

#4941 In chipsalliance/chisel;

· seldridge opened on May 27, 2025

[chiselsim] Questasim Support

feature request

Status: Open.

#4935 In chipsalliance/chisel;

· seldridge opened on May 23, 2025

Proposal: Standardized Property Metadata API for Chisel Based on IP-XACT

Status: Open.

#4932 In chipsalliance/chisel;

· sequencer opened on May 21, 2025

Warning occurs when the decoder fields chiselType is chiselEnum

Status: Open.

#4930 In chipsalliance/chisel;

· yizishun opened on May 20, 2025

IntelliJ Errors with Chisel 7.0.0-RC1 Despite Successful Compilation

Status: Open.

#4929 In chipsalliance/chisel;

· Emin017 opened on May 19, 2025

How to parse firrtl file/string to Circuit instance?

Status: Open.

#4899 In chipsalliance/chisel;

· canxin121 opened on Apr 20, 2025

Inaccrate Infomation in the "Get me Verilog" section of FAQ

Status: Open.

#4877 In chipsalliance/chisel;

· scratch-er opened on Apr 9, 2025

Warnings occurs when using the VCS backend for simulation in SVSIM

Status: Open.

#4848 In chipsalliance/chisel;

· jcvclouds opened on Apr 1, 2025

[svsim][chiselsim] Support Questa

Status: Open.

#4846 In chipsalliance/chisel;

· seldridge opened on Mar 31, 2025

ChiselSim not allowing capturing of stdout/stderr

Status: Open.

#4819 In chipsalliance/chisel;

· seldridge opened on Mar 21, 2025

Chisel drops escaped % in printf if it is the last character in the format string and preceded by a space

Status: Open.

#4818 In chipsalliance/chisel;

· jackkoenig opened on Mar 21, 2025