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Feature request: more flexibility for IO naming

enhancementNew feature or requestNew feature or request

style-linterVerilog style-linter issuesVerilog style-linter issues

Status: Open.

#2490 In chipsalliance/verible;

· nexibard opened on Jan 28, 2026

column_limit affects the formatting even when we are under the limit

formatterVerilog code formatter issuesVerilog code formatter issues

Status: Open.

#2489 In chipsalliance/verible;

· furkanu-work opened on Jan 26, 2026

Missing language server in-line/in-lay hints

language-serverLanguage server related issuesLanguage server related issues

Status: Open.

#2486 In chipsalliance/verible;

· slolson1 opened on Jan 12, 2026

Verible verilog formatter crash with segfault

formatterVerilog code formatter issuesVerilog code formatter issues

Status: Open.

#2485 In chipsalliance/verible;

· JackySu opened on Dec 31, 2025

[feature quest] obfuscation should keep top level

Status: Open.

#2482 In chipsalliance/verible;

· facebreeze opened on Dec 19, 2025

assignment blocks exceeds the column limit,alignment will fail

formatterVerilog code formatter issuesVerilog code formatter issues

Status: Open.

#2481 In chipsalliance/verible;

· LinYu369 opened on Dec 18, 2025

Formatter fails to converge when `define is used.

formatterVerilog code formatter issuesVerilog code formatter issues

Status: Open.

#2479 In chipsalliance/verible;

· tornose opened on Dec 11, 2025

Support for parsing, preserving, and emitting comments in Verible (CST)

rejects-valid syntaxIf the parser wrongly rejects syntactically valid code (according to SV-2017).If the parser wrongly rejects syntactically valid code (according to SV-2017).

Status: Open.

#2476 In chipsalliance/verible;

· gmCAD opened on Dec 4, 2025

Verible Fails to Parse Non-ANSI Verilog Port Syntax

rejects-valid syntaxIf the parser wrongly rejects syntactically valid code (according to SV-2017).If the parser wrongly rejects syntactically valid code (according to SV-2017).

Status: Open.

#2475 In chipsalliance/verible;

· gmCAD opened on Dec 4, 2025

verible-verilog-format crash for special wire signed vectors

formatterVerilog code formatter issuesVerilog code formatter issues

Status: Open.

#2474 In chipsalliance/verible;

· frazezhang opened on Dec 1, 2025

Parsing code with interface ports results in an error

Status: Open.

#2473 In chipsalliance/verible;

· jszhanghit opened on Nov 26, 2025

Enum value rename does not work

language-serverLanguage server related issuesLanguage server related issues

Status: Open.

#2471 In chipsalliance/verible;

· fishBone000 opened on Nov 25, 2025