assignment blocks exceeds the column limit,alignment will fail

[LinYu369]

vscode parameter use

  "verible.arguments": [
    "--column_limit=400",
    "--rules=+line-length=length:600,-parameter-name-style,-explicit-parameter-storage-type,-always-comb,-case-missing-default,-unpacked-dimensions-range-ordering,-no-tabs,-no-trailing-spaces,-posix-eof",
    "--assignment_statement_alignment=align",
    "--class_member_variable_alignment=align",
    "--named_parameter_alignment=align",
    "--named_port_alignment=align",
    "--port_declarations_alignment=align",
    "--module_net_variable_alignment=align",
    "--try_wrap_long_lines=true",
    "--variables_in_outline=false"
  ],

Actual output

module eth_top (
    input wire clk,   // clk
    input wire rst_n  // rst
);
  wire [  7:0] rx_crc;  // crc checksum
  wire         ins_rx_crc_ok;  // crc checksum ok
  wire         ins_machine_code_ok;
  wire         data_machine_code_ok;
  wire         ins_initialize_ctrl;
  wire         ins_asyn_rest_ctrl;
  wire         ins_set_ip_ctrl;
  wire         ins_set_mac_ctrl;
  reg  [127:0] ins_rx_data_buff;
  reg          udp_get_ins_state;
  reg          udp_rx_ram_rd_data;

  //parameter define
  parameter FPGA_VERSION = 32'h01_00_00_02;  // fpga ver
  parameter INSTRUCTION_MESSAGE_LENGTH = 16;
  parameter DATA_MESSAGE_DATA_LENGTH = 1024;
  parameter MACHINE_CODE = 16'h01;

  parameter UDP_INS_INITIALIZE = 16'h0000;
  parameter UDP_INS_ASYN_REST = 16'h0001;
  parameter UDP_INS_SET_IP = 16'h0002;
  parameter UDP_INS_SET_MAC = 16'h0003;


  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      ins_rx_data_buff <= 128'd0;
    end else if (udp_get_ins_state == 1) begin
      ins_rx_data_buff <= {ins_rx_data_buff[119:0], udp_rx_ram_rd_data};
    end else begin
      ins_rx_data_buff <= ins_rx_data_buff;
    end
  end

  assign rx_crc = (ins_rx_data_buff[15:8] ^ ins_rx_data_buff[23:16] ^ ins_rx_data_buff[31:24] ^ ins_rx_data_buff[39:32] ^ ins_rx_data_buff[47:40] ^ ins_rx_data_buff[55:48] ^ ins_rx_data_buff[63:56] ^ ins_rx_data_buff[71:64] ^ ins_rx_data_buff[79:72] ^ ins_rx_data_buff[87:80] ^ ins_rx_data_buff[95:88] ^ ins_rx_data_buff[103:96] ^ ins_rx_data_buff[111:104] ^ ins_rx_data_buff[119:112] ^
                   ins_rx_data_buff[127:120]);
  assign ins_rx_crc_ok = (rx_crc == ins_rx_data_buff[7:0]) ? 1 : 0;
  assign ins_machine_code_ok = (ins_rx_data_buff[127:120] == MACHINE_CODE) ? 1 : 0;
  assign data_machine_code_ok = (ins_rx_data_buff[127:112] == MACHINE_CODE) ? 1 : 0;
  assign ins_initialize_ctrl = ins_rx_crc_ok ? (ins_machine_code_ok ? (ins_rx_data_buff[119:104] == UDP_INS_INITIALIZE ? 1 : 0) : 0) : 0;
  assign ins_asyn_rest_ctrl = ins_rx_crc_ok ? (ins_machine_code_ok ? (ins_rx_data_buff[119:104] == UDP_INS_ASYN_REST ? 1 : 0) : 0) : 0;
  assign ins_set_ip_ctrl = ins_rx_crc_ok ? (ins_machine_code_ok ? (ins_rx_data_buff[119:104] == UDP_INS_SET_IP ? 1 : 0) : 0) : 0;
  assign ins_set_mac_ctrl = ins_rx_crc_ok ? (ins_machine_code_ok ? (ins_rx_data_buff[119:104] == UDP_INS_SET_MAC ? 1 : 0) : 0) : 0;

endmodule

Expected or suggested output

module eth_top (
    input wire clk,   // clk
    input wire rst_n  // rst
);
  wire [  7:0] rx_crc;                // crc checksum
  wire         ins_rx_crc_ok;         // crc checksum ok
  wire         ins_machine_code_ok;
  wire         data_machine_code_ok;
  wire         ins_initialize_ctrl;
  wire         ins_asyn_rest_ctrl;
  wire         ins_set_ip_ctrl;
  wire         ins_set_mac_ctrl;
  reg  [127:0] ins_rx_data_buff;
  reg          udp_get_ins_state;
  reg          udp_rx_ram_rd_data;

  //parameter define
  parameter FPGA_VERSION               = 32'h01_00_00_02;  // fpga ver
  parameter INSTRUCTION_MESSAGE_LENGTH = 16;
  parameter DATA_MESSAGE_DATA_LENGTH   = 1024;
  parameter MACHINE_CODE               = 16'h01;

  parameter UDP_INS_INITIALIZE         = 16'h0000;
  parameter UDP_INS_ASYN_REST          = 16'h0001;
  parameter UDP_INS_SET_IP             = 16'h0002;
  parameter UDP_INS_SET_MAC            = 16'h0003;


  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      ins_rx_data_buff <= 128'd0;
    end else if (udp_get_ins_state == 1) begin
      ins_rx_data_buff <= {ins_rx_data_buff[119:0], udp_rx_ram_rd_data};
    end else begin
      ins_rx_data_buff <= ins_rx_data_buff;
    end
  end

  assign rx_crc               = (ins_rx_data_buff[15:8] ^ ins_rx_data_buff[23:16] ^ ins_rx_data_buff[31:24] ^ ins_rx_data_buff[39:32] ^ ins_rx_data_buff[47:40] ^ ins_rx_data_buff[55:48] ^ ins_rx_data_buff[63:56] ^ ins_rx_data_buff[71:64] ^ ins_rx_data_buff[79:72] ^ ins_rx_data_buff[87:80] ^ ins_rx_data_buff[95:88] ^ ins_rx_data_buff[103:96] ^ ins_rx_data_buff[111:104] ^ ins_rx_data_buff[119:112] ^
                                ins_rx_data_buff[127:120]);
  assign ins_rx_crc_ok        = (rx_crc == ins_rx_data_buff[7:0]) ? 1 : 0;
  assign ins_machine_code_ok  = (ins_rx_data_buff[127:120] == MACHINE_CODE) ? 1 : 0;
  assign data_machine_code_ok = (ins_rx_data_buff[127:112] == MACHINE_CODE) ? 1 : 0;
  assign ins_initialize_ctrl  = ins_rx_crc_ok ? (ins_machine_code_ok ? (ins_rx_data_buff[119:104] == UDP_INS_INITIALIZE ? 1 : 0) : 0) : 0;
  assign ins_asyn_rest_ctrl   = ins_rx_crc_ok ? (ins_machine_code_ok ? (ins_rx_data_buff[119:104] == UDP_INS_ASYN_REST ? 1 : 0) : 0) : 0;
  assign ins_set_ip_ctrl      = ins_rx_crc_ok ? (ins_machine_code_ok ? (ins_rx_data_buff[119:104] == UDP_INS_SET_IP ? 1 : 0) : 0) : 0;
  assign ins_set_mac_ctrl     = ins_rx_crc_ok ? (ins_machine_code_ok ? (ins_rx_data_buff[119:104] == UDP_INS_SET_MAC ? 1 : 0) : 0) : 0;

endmodule

1. If one of the assignment blocks exceeds the column limit, alignment will fail.
2. The parameters won't be aligned. I hope it can also be aligned like the assign key word.
3. The annotations also hope to be aligned like the input and output ports of the module.（ // crc checksum, // crc checksum ok like // clk , rst）