Chisel v7.0.0-RC1

Features

• Add AffectsChiselName (by @adkian-sifive in #4283)
  Adds new trait AffectsChiselName that adds support for naming user-defined types
• Add --remap-layers to ChiselStage (by @seldridge in #4322)
• Add common layers to Chisel (by @seldridge in #4326)
• Add skipIfAlreadyInBlock arg to layer.block (by @seldridge in #4327)
• Add skipIfLayersEnabled param to layer.block (by @seldridge in #4346)
• Add layer.elideBlocks API (by @seldridge in #4348)
• Make layer.addLayer API public (by @seldridge in #4349)
• Add Property expression for list concatenation. (by @mikeurbach in #4347)
  This adds a list concatenation operation for Property[Seq[T]], using the same typeclass approach used for other Property expressions.
• Add support for circt.OutputDirAnnotation. (by @dtzSiFive in #4352)
  Expose capability to request a Module be placed in a specific directory.
  Functions as with Layer output directories.
• Make '--module' support arguments (by @seldridge in #4358)
• Add DataMirror API for currentInstancePorts. (by @mikeurbach in #4362)
  This allows users to query an Instance without it being closed or forcing it to close, which can be useful in atModuleBodyEnd and other scenarios.
• Add experimental Select APIs for current instances in a BaseModule. (by @mikeurbach in #4363)
  This is useful in situations like atModuleBodyEnd to reflect on the current BaseModule before it is closed.
• Add Path.apply() to support HasTarget (by @debs-sifive in #4364)
  Adds Path.apply() function that support HasTargets, so that the paths of things that extend HasTarget, like SRAM, can be put into properties.
• feat: implement SerializableModuleElaborator (by @unlsycn in #4409)
  Add SerializableModuleElaborator
• Add SourceLocator for Sequence (by @unlsycn in #4436)
  Add source locator for Sequence
• Add Property expression for integer shift left (by @maerhart in #4440)
  This adds an API for integer Property shift left.
• Support creation of Paths from HasTargets (by @debs-sifive in #4455)
• Add --firtool-option arg to ChiselStage (by @seldridge in #4463)
• switch SRAMDescription to Class (by @sequencer in #4437)
• add additionalAnnotations for SerializableModuleElaborator (by @sequencer in #4477)
• Implement Lookupable for HasTarget (used by SRAM) (by @jackkoenig in #4481)
• Allow BoringUtils to use existing port in a closed module (by @tmckay-sifive in #4484)
  When trying to drill a port, it doesn't matter if the module is closed. We do not need to construct new hardware and can just use the existing port.
• Implement Lookupable for Unit (by @jackkoenig in #4497)
• [Module] Add afterModuleBuilt hook (by @fabianschuiki in #4479)
  The new afterModuleBuilt hook can be used to schedule code to be executed once a module has been fully generated and its definition is available. This allows further collateral such as unit tests to be generated alongside a module.
• Add withModulePrefix (by @mmaloney-sf in #4487)
• Add AutoBlackbox (by @unlsycn in #4495)
• Add new InlineInstanceAllowDedup trait (by @rwy7 in #4508)
• Add module prefixing to BaseModule definitions (by @jackkoenig in #4509)
  • BaseModule.localModulePrefix can be used to set a prefix for the module and its children.
  • BaseModule.localPrefixAppliesToSelf (defaults to true) allows the module to exclude itself from the prefix.
  • localModulePrefix composes with prefixes added via withModulePrefix.
• feat: add CIRCTSRAMInterface (by @unlsycn in #4494)
  Add CIRCTSRAMInterface
• Add APIs to omit module prefix separator (by @jackkoenig in #4532)
  • withModulePrefix now optionally takes a 2nd parameter includeSeparator (passing false will omit separator).
  • Overriding localModulePrefixUseSeparator in a Module to false will omit separator for local prefix applied by overriding localModulePrefix in that Module.
• feat: add SRAMBlackBox (by @unlsycn in #4544)
• Add partial cross-compilation for Scala 3 (by @adkian-sifive in #4549)
  Adds initial support for Scala 3 LTS version 3.3.3
• [util] Add a withShadowLayer Queue (by @seldridge in #4589)
• Add FormalTest marker (by @fabianschuiki in #4635)
• [core] Add layer block that returns colored wire (by @seldridge in #4623)
• Add UnitTest marker and test discovery utility (by @fabianschuiki in #4642)
• [chiselsim] Add Default (non-Ephemeral) Simulator (by @seldridge in #4665)
• [Chiselsim] Add WithTestingDirectory (by @seldridge in #4669)
• [chiselsim] Rewrite EphemeralSimulator in terms of DefaultSimulator (by @seldridge in #4675)
• [chiselsim] Add, use HasSimulator type class (by @seldridge in #4678)
• [firrtl] Add, use dramaticMessage (by @seldridge in #4684)
• [chiselsim] Add SimulatorAPI, reduce DefaultSimulator to nothing (by @seldridge in #4680)
• [chiselsim] Add ChiselSim APIs (by @seldridge in #4685)
• Add simple API for generating testharnesses inline (by @tmckay-sifive in #4629)
  Add an API to generate testharnesses inline that are emitted as additional public modules in the output.
• Dev/seldridge/switch to chisel settings (by @seldridge in #4708)
• Add RequireProperty and EnsureProperty (by @fabianschuiki in #4681)
• [chiselsim] Add FIRRTL macro control (by @seldridge in #4699)
• [Chiselsim] Replace Chiselspec w/ ChiselSim (by @seldridge in #4706)
• [testing] Add FileCheck API (by @seldridge in #4749)
• Add formal contracts (by @fabianschuiki in #4682)
• [testing] Add HasTestingDirectory subdir factory (by @seldridge in #4774)
• [chiselsim] Allow command line options to be passed to ChiselSim tests (by @seldridge in #4773)
• [scalatest] Add HasCliSimulator (by @seldridge in #4776)
• Change Data._fromUInt to protected (by @jackkoenig in #4782)
  This enables external libraries like FixedPoint to override it. This is not an ideal API, but it works until we have a better way to do this.
• [chiselsim] Add ControlAPI w/ Waveform Enable/Disable Support (by @seldridge in #4779)
• [ChiselSim] Factor reset procedure out of SimulatorAPI and into stimulus (by @seldridge in #4784)
• Add resetType to inline test TestParameters (by @tmckay-sifive in #4789)
  • Add resetType to chisel3.experimental.inlinetest.TestParameters. It will now be easier to properly handle DUTs with uninferred resets.
• [svsim] Add coverage collection to VCS backend (by @seldridge in #4793)
• [svsim][chiselsim] Add plusarg support (by @seldridge in #4796)
• [chiselsim] Add CLI FSDB, VPD support, enable waves (VCD, too) (by @seldridge in #4797)
• [chiselsim] Add waves at time zero to settings (by @seldridge in #4801)
• Provide custom error for Mem masked write wrong data type (by @jackkoenig in #4805)
  The old error was Cannot prove that chisel3.UInt <:< chisel3.Vec[_], the new error is Masked write requires that the data type is a Vec, got chisel3.UInt.
• [chiselsim] HasCliOptions, EmitVcd for ChiselSim (by @seldridge in #4807)
• [chiselsim] Chisel/firtool update type classes (by @seldridge in #4808)
• [svsim] Add Coverage Directory and Name to VCS Backend (by @seldridge in #4812)
• [chiselsim] Add subdirectory to SimulatorAPI fns (by @seldridge in #4815)
• [chiselsim] Add RunUntilSuccess stimulus (by @seldridge in #4825)
• Add support for printing hierarchical names in Verilog (%m) (by @jackkoenig in #4820)
• [chiselsim] Add randomization to settings (by @seldridge in #4835)
• Add dump file name for VCS backend (by @jcvclouds in #4844)
  Add filename argument for svsim.vcs.Backend.CompilationSettings.TraceSettings.FsdbSettings to specify the waveform file name, which is similar to the filename argument of svsim.verilator.Backend.CompilationSettings.TraceStyle.Vcd
• Add API to create layer-colored RWProbes (by @tmckay-sifive in #4857)
  • Add API for creating layer-colored writable probes
• Revert "Remove deprecated BoringUtils APIs (#4852)" (by @seldridge in #4873)
• Add command line options to control elaboration of inline tests (by @tmckay-sifive in #4826)
  • Provide control over when inline tests are elaborated
    • Add --include-tests-module command line argument to enable inline test elaboration for modules matching a glob
    • Add --include-tests-name command line argument to enable inline test elaboration for tests matching a glob
    • Add HasTests.elaborateTests to dynamically enable test elaboration for a module (dynamic per-test elaboration can be done by wrapping calls to test in a conditional block)
• Add SimulationTime (%T) format specifier (by @jackkoenig in #4875)
  Unlike %t in Verilog, SimulationTime (%T) does not take an argument.
• Add FixedIOModule (by @tmckay-sifive in #4874)
  • Add FixedIOModule, which behaves like FixedIORawModule but also has a clock and reset port.
• [chiselsim] Add a "flag" CLI option factory (by @seldridge in #4880)
• Add methods to inline module instances (by @jackkoenig in #4883)
  Add chisel3.experimental.inlineInstance and chisel3.experimental.inlineInstanceAllowDedup methods to control module inlining at run-time.
• Add SimLog for printing to files (by @jackkoenig in #4882)
  You can now print to files:

  val fd = SimLog.file("logfile.txt")
  fd.printf(cf"foo = $foo%0d\n")

• Support customizing output CHIRRTL file name (by @tymcauley in #4894)
  Users can use the --chisel-output-file argument to ChiselStage to customize the output file name.
• Support Printable SimLog filenames (by @jackkoenig in #4892)
  You can use Printables in SimLog filenames, e.g. val log = SimLog.file(cf"logfile_$idx%0d.log")
• Add Simlog.flush (by @jackkoenig in #4895)
  SimLog objects now support .flush(). You can flush stderr with SimLog.StdErr.flush().
• Support reset-initializing the lastGrant register in RRArbiter (by @tymcauley in #4903)
  Add the initLastGrant argument to the round-robin arbiter classes (RRArbiter and LockingRRArbiter) to support reset-initializing a register which might be in the control path of designs.

API Modification

• Create layer blocks on demand (by @seldridge in #4304)
• [simulator] Enable all layers for simulation (by @seldridge in #4307)
• Bundle elements ordering fix (by @adkian-sifive in #4226)
  All Bundle elements will be ordered by the order of their declaration, including by inheritance.
• Layers: Add support for inline convention. (by @dtzSiFive in #4300)
  Layer API has changed from convention as argument to constructing specific layer kind directly.
• Put Verification Operations into Layer Blocks (by @seldridge in #4323)
• Add property support to SRAMInterface-based SRAM (by @sequencer in #4298)
  add property to SRAMInterface
• Change Path to emit relative targets (by @jackkoenig in #4368)
• make SRAM description value optional in SRAMInterface (by @debs-sifive in #4370)
  Add a hasDescription argument to SRAMInterface that specifies whether or not it contains a SRAMDescription.
  Making description optional enables users to create SRAMInterfaces without having to hook up an SRAMDescription.
• Refactor Internals to use Scala 2 Veneers (by @jackkoenig in #4400)
  This is a massive refactoring of Chisel's internals in preparation for adding Scala 3 support. The public API should be generally unchanged but there are many new package private traits that should not affect Scala users but are messy at the binary compatibility level.
• Deprecate all Injecting Aspect Code (by @seldridge in #4415)
• Remove Injecting Aspects (by @seldridge in #4417)
• Remove aspects (by @seldridge in #4424)
• Support cross-compiling FIRRTL source files with Scala3 (by @adkian-sifive in #4403)
  Refactor FIRRTL sources to support cross-compilation with Scala3
• Add svsim -Xsource:3 for Scala3 cross compilation support (by @adkian-sifive in #4430)
  • svsim.Simulation.Port apply and copy methods are now private, these should never have been public.
  • svsim.CommonCompilationSettings.VerilogPreprocessorDefine apply and copy methods now private, use other public apply methods.
• [Scala3] Refactor Printf and VerificationStatement macros (by @adkian-sifive in #4449)
  Separate and move Printf and VerificationStatement macros in preparation of Scala3 support
• [Scala3] Add core -Xsource:3 for Scala3 cross compilation support (by @adkian-sifive in #4431)
  Adds -Xsource:3 to core in preparation of Scala3 migration. Add stricter type ascriptions for Scala3:
  • ResetType.litOption return type changed from None to Option[BigInt]
  • AsyncReset.litOption return type changed from None to Option[BigInt]
  • RequireAsyncReset.resetType type changed from ResetType.Type to Asynchronous.type
  • RequireAsyncReset.resetType type changed from ResetType.Type to Synchronous.type
  • CrossModuleBinding.location return type changed from None.type to Option[BaseModule]
• [Scala3] [Mill] Add Xsource:3 to core in Mill to match SBT (by @adkian-sifive in #4468)
  Add -Xsource:3 to Mill core compilation unit
• Elide metadata by default, add --include-util-metadata (by @jackkoenig in #4475)
• [Scala3] Scala2 compatibility changes (by @adkian-sifive in #4483)
  Minor refactoring for compatibility with Scala3. Factory objects from package.scala are moved to live with their defining classes for compatibility with Dotty. Macros and reflection moved to scala-2 API directory.
• Remove do-apply pattern from Definition and Instance (by @adkian-sifive in #4540)
  Do-apply pattern for Definition/Instance apply methods was removed
• [ChiselSim] Add Inline Layer Control (by @seldridge in #4555)
• Error rather than throw on scope violations (by @jackkoenig in #4586)
  • Errors are aggregated by default and all reported at the end whereas exceptions throw immediately. This allows users to fix multiple scope violations at the same time.
  • Printable.unpack now takes an implicit SourceInfo
  • PropertyType.convertUnderlying now takes an explicit SourceInfo
• Add input seq length check to Mux1H and PriorityMux (by @Emin017 in #4572)
• Aggregate PriorityMux and Mux1H Seq size errors (by @jackkoenig in #4609)
  • This requires adding source locators to PriorityMux and Mux1H which requires SourceInfoTransform macros in Scala 2 and thus splitting the Scala 2 / Scala 3 public interfaces.
  • Because macro applications do not support named arguments in Scala 2, this is an API change.
• [scala3] Remove names from context parameters (by @jackkoenig in #4639)
  Only affects Scala 3 APIs which are not yet published
• [chiselsim] General cleanup (by @seldridge in #4674)
• Remove deprecated annotation APIs (by @jackkoenig in #4717)
  • Remove ChiselAnnotation and ChiselMultiAnnotation
  • Remove annotate methods for ChiselAnnotations
  • Remove Circuit APIs from ChiselOptions and ChiselCircuitAnnotation
    • Use ElaboratedCircuit instead
  • Remove ChiselEnum related annotations
• Partial Migration from ChiselSpec to ChiselSim (by @seldridge in #4724)
• [testers] Delete chisel3.testers (by @seldridge in #4746)
• Dev/seldridge/firrtl delete backend compilation utilities (by @seldridge in #4755)
• [chiselsim] Chisel/firtool Options on SimulatorAPI (by @seldridge in #4794)
• Replace autoNameRecursively with chisel3.withName (by @jackkoenig in #4799)
  Also use varargs of String instead of List[Option[String]] for the
  Product version of withName.
• [chiselsim] Change chiselSettings to settings (by @seldridge in #4814)
• Remove deprecated BoringUtils APIs (by @seldridge in #4852)
• Add support for modifiers to format specifiers in printing (by @jackkoenig in #4821)
  This includes modifiers defined in the SystemVerilog spec like minimum width (e.g. %0d) and set width (e.g. %8d). It does not include non-standard extensions like left-justification and zero-padding for decimal.
• [firrtl] Remove unused target APIs (by @seldridge in #4860)
• [firrtl] Remove serialize and miscellaneous APIs (by @seldridge in #4861)
• [firrtl] Drop Circuit from Target/Named (by @seldridge in #4862)

API Deprecation

• Deprecate more Aspect parts (by @seldridge in #4420)
• Refactor Lookupable (by @jackkoenig in #4519)
  Historically, the Lookupable API is able to change the type of fields looked up from Definitions or Instances. This enabled Module fields to be looked up as Instances, as well as user-defined types to opt-in to this same Instance-boxing behavior.
  This path-dependent type changing behavior is now deprecated. Looking up Modules is also deprecated, instead, the user should cast them Instances (via .toInstance). It is also deprecated to mark user-defined types as @instantiable. Instead, users should define Lookupable for their types using the new Lookupable.product[1-5] factory methods. See the Chisel website for more details.
  • Deprecate user-extension of trait Lookupable.
  • Deprecate Lookupable.lookupModule. Users should use Instances instead
    of Modules.
  • Deprecate Lookupable.isInstantiable. User should use new factories to
    implement Lookupable for their user-defined types instead.
  • Deprecate Lookupable.SimpleLookupable.
  • Add Lookupable.isLookupable factory for "simple" Lookupables.
  • Add Lookupable.product1-5 factories for Lookupables for user-defined types.
  • Add Lookupable for Tuple3-5 (already existed for Tuple2).
  • Add private LookupableImpl which is simpler to implement.
• Add ElaboratedCircuit and deprecate use of internal ir Circuit (by @jackkoenig in #4683)
  Change ChiselCircuitAnnotation and CircuitSerializationAnnotation to no longer be case classes to help with the transition to ElaboratedCircuit.
• Add safer Chisel annotation API, deprecate old ones (by @jackkoenig in #4643)
  Creating annotations in Chisel now requires reporting what InstanceIds are going to be annotated so that Chisel can do some safety checks.
• [testers] Deprecate everything the testers package (by @seldridge in #4742)
• Mass deprecations, to be removed in Chisel 7 (by @seldridge in #4754)
• Warn on .asUInt|.asSInt(_: Int) (by @jackkoenig in #4764)
  The user probably forgot .W. Apply the same technique as used for .U|.S.
• Deprecate ChiselStage.convert, replace with elaborate (by @jackkoenig in #4816)
  Also add name to Definition[BaseModule].
• Fix UInt unary negation ScalaDoc (by @jackkoenig in #4829)
  Deprecate invalid unary operator unary_-%.
• Deprecate Printable.unpack and .unpackArgs, replace with new version (by @jackkoenig in #4858)
• Deprecate everything in package firrtl (by @jackkoenig in #4878)
  If there is anything you cannot do without accessing APIs in package firrtl directly, please open an issue on the Chisel Github repository to explain your use case so we can see about adding APIs to Chisel directly.

Backend Code Generation

• Add default layers that are always emitted (by @seldridge in #4350)
• Allow HasTarget paths to be IsMemberPath (by @debs-sifive in #4470)
• Wrap printfs in the Verification layerblock (by @seldridge in #4506)
• Change default layers to use lowercase directories (by @seldridge in #4505)
• Bump emitted FIRRTL to 4.1.0 (by @seldridge in #4513)
• Bump FIRRTL version to 4.2.0 (by @seldridge in #4585)
• Bump emitted FIRRTL to 5.1.0 (by @seldridge in #4841)
• [FIRRTL] Serialize Named as Target (by @seldridge in #4853)
• Add --split-verilog to emitSystemVerilogFile (by @seldridge in #4867)

Performance

• Block: close earlier, ArraySeq builder and store result, drop unused owner field (by @dtzSiFive in #4456)
• Speedup Computation for whether Aggregates containsProbe (by @mwachs5 in #4656)
  Add a private containsProbe var to Aggregate and use it to speed up containsProbe checks.
• Selective view renaming (by @jackkoenig in #4644)
• Add Serializer for ChiselIR (by @jackkoenig in #4748)
  This reduces peak memory use when serializing to .fir. It heavily depends on the design, but for designs with a single very large module, we have measured 20-25% reductions in peak memory use. For most cases, the reduction will likely be more modest.
• Enable inlining in Scalac options (by @jackkoenig in #4813)

Fixes

• Properly handle OpaqueTypes in SRAM mask (by @jackkoenig in #4284)
• Emit Layers when using D/I (by @seldridge in #4301)
• Remove unnecessary overrides of lref and ref in Property (by @jackkoenig in #4309)
  This fixes an issue with views of List of Property.
• Handle define on views of Probes (by @jackkoenig in #4308)
• Fix svsim DPI function template (by @uenoku in #4317)
• Support BoringUtils.bore on OpaqueType wrapping a Property. (by @mikeurbach in #4337)
  This ensures boring from an OpaqueType that wraps a Property uses the correct connection operator in the IR.
• Visit layerblocks in aop.Select methods (by @seldridge in #4341)
• Fix Arg.name and earlyLocalName for probes (by @tmckay-sifive in #4359)
• Fix ActualDirection calculation from SpecifiedDirection (by @jackkoenig in #4205)
  Fixes #4204.
  Unspecified direction maps to Output while Flip maps to Input. Previously, ActualDirection.fromSpecified would return Unspecified for either Unspecified or Flipped input. This in turn resulted in Bundles mixing Unspecified and Outputs as being "bidirectional" despite the fact that they are actually unidirectional (or passive).
• Improve error messages for empty Mux1H and PriorityMux (by @jackkoenig in #4391)
• Select.collectDeep and related: search into layers and whens (by @dtzSiFive in #4395)
  More Select methods support searching into whens and layers.
• Flush staged commands before/after enter/exit regions. (by @dtzSiFive in #4399)
  Fix BoringUtils with regions in some cases.
• Module: reset layerStack (by @dtzSiFive in #4407)
• fix: wrap all intrinsics in layerblocks (by @unlsycn in #4435)
  Fix LTL intrinsics are generated outside the verification layer block
• Save/restore when+layer stack w/D/I, fix crashes. (by @dtzSiFive in #4442)
  Fix crashing or incorrect behavior in some cases involving use of DI interacting with when's or layer's.
• Make it legal to extract zero bits from a zero-width UInt (by @jackkoenig in #4445)
• Fix Boring.rwTap on instance ports (by @azidar in #4451)
  BoringUtils.rwTap can now works on a port of an instance: Instance[..]
• Fix addAttribute and add AttributesAnnotationSpec (by @unlsycn in #4454)
  Fix addAttribute and add AttributesAnnotationSpec.
• Fix Select.attachedTo (by @jackkoenig in #4458)
• Layers: color check all not any and don't consider enabled layers. (by @dtzSiFive in #4434)
  Fix checking of layer-color probes to avoid rejecting valid uses and to detect actual problems that would otherwise be caught by CIRCT.
• Fix missing string interpolators, add -Xlint:missing-interpolator (by @jackkoenig in #4471)
• Add Probes to .toString Data methods (by @azidar in #4478)
  Probe chisel types now include the kind of probe and layer in their .toString method
• fix: remove source locator for IO in FixedIOModule (by @unlsycn in #4500)
• fix: fix wrong mill source layout (by @unlsycn in #4511)
• fix: fix wrong package name in HierarchyPackage (by @unlsycn in #4512)
• fix: fix while loop in ReverseImpl (by @unlsycn in #4525)
• fix: fix mask granularity in CIRCTSRAMInterface (by @unlsycn in #4535)
• Fix auto generated DedupGroups to be sensitive to module prefix (by @jackkoenig in #4545)
  Also fix logic for naming PseudoModules which should ignore the prefix.
• fix: evaluate target lazily in Path (by @unlsycn in #4543)
• Fix potential name collision caused by LTL properties (by @tmckay-sifive in #4551)
  Some nodes created by LTL properties had suggestName called on them, potentially leading to name collisions with user code.
• [svsim] Escape ' (by @seldridge in #4559) in defines for VCS only (by @seldridge in #4559)
• Escape special characters in Property String literals (by @jackkoenig in #4564)
  This technically breaks backwards compatibility for firrtl.ir.StringPropertyLiteral but firrtl.ir is considered an internal API.
• Fix ModuleChoice under D/I (by @davidbiancolin in #4569)
• Fix BoringUtils input probe creation (by @seldridge in #4577)
• fix up extra waveform dump behavior in svsim (by @Emin017 in #4592)
• Support boring on original Module after .toInstance call (by @jackkoenig in #4602)
• Fixes sendBits()'s handling of signed numbers in svsim's simulation-driver in #4593 (by @AptInit in #4599)
• [svsim] Fix initial ordering issue (by @seldridge in #4614)
• [svsim] Initialize ports to zero (by @seldridge in #4651)
• Deterministic FibonacciLFSR reductions (by @jerryz123 in #4688)
• [chiselsim] Improve error behavior (by @seldridge in #4694)
• [svsim] End Verilator simulation on $finish (by @seldridge in #4702)
• [svsim][chiselsim] Do not compile extract layery directories (by @seldridge in #4709)
• Re-land #4702 (by @seldridge in #4712)
• [svsim] Wait after destroying simulator process (by @seldridge in #4718)
• [chiselsim] Strip quotes, hash in Chiselsim directories (by @seldridge in #4722)
• [testers] Fix BasicTester finish, port to ChiselSim (by @seldridge in #4725)
• [svsim] Avoid EndOfMessages Exception (by @seldridge in #4769)
• Fix extmodule emission when instantiating an imported Definition multiple times (by @tmckay-sifive in #4759)
  Fix multiple instantiation of imported Definitions.
• Fix for #4780 (by @tobias1012 in #4783)
  Fix 'rm' executable dependency on windows.
• Fix SInt literals to reject too small of widths (by @jackkoenig in #4786)
  For users attempting to reinterpret raw 2s complement values as SInts, use .U.asSInt.
• [svsim] Error if waves enabled in unsupported sim (by @seldridge in #4787)
• [svsim] Use SNPS-specific license in VCS (by @seldridge in #4792)
• [testing] Fix testing dir date/time stability (by @seldridge in #4800)
• [svsim] Batched VCS fixes (by @seldridge in #4810)
• Make SVSim directory clearing more robust (by @jackkoenig in #4811)
  • Use custom FileVisitor for more optimal traversal
  • Suppress DirectoryNotEmptyExceptions from failing to delete directories due to systems like FUSE.
• Fix layer.enable applying to all later modules (by @seldridge in #4840)
• [svsim] Use -no_save instead of ASLR workarounds (by @seldridge in #4845)
• Restore NumObject trait and Num object (by @tymcauley in #4856)
• [firrtl] Bump serializer version to 5.1.0 (by @seldridge in #4879)
• Add error message for dynamic index in target (by @unlsycn in #4887)
• Error eagerly when attempting to annotate dynamic indices (by @jackkoenig in #4896)
  Fixes a longstanding wart by at least giving a more useful error message at the site of the problematic user code.

Documentation

• Update chiseltest uses version to 6.0 in documentation (by @Emin017 in #4287)
• Improve the error message for mismatched types in Mux (by @jackkoenig in #4331)
• [website] Update docusaurus 3.1.1 => 3.5.2 (by @jackkoenig in #4365)
• Add utility for pretty Verilog emission in mdoc (by @jackkoenig in #4369)
  This cleans up a lot of boilerplate and removes the default layer emission in all of the uses.
• Enable -Xsource:3 on the docs project. (by @mwachs5 in #4432)
  Set -Xsource:3 on documentation code examples
• chore: Updating JDK-related docs for macOS Homebrew (by @SYYANI in #4439)
  The original brew command for installing jdk has been deprecated, this pr now provides a command to adapt to the new version of brew
• Change link colors for aid in readability in dark mode. (by @mmaloney-sf in #4501)
• The linked PDF at UCB is now behind a login wall. So dropping it. (by @schoeberl in #4542)
• fix typo in SourceInfoTransform.scala (by @Emin017 in #4594)
  Fix typo in scaladoc for sourceInfoTransform macro
• [docs] Add Cookbook entry for Verilog case equality (IsX) (by @jackkoenig in #4605)
• [docs] Fix pipe rendering in markdown table (by @tymcauley in #4625)
• update DPI function call examples in chisel3.util.circt.dpi (by @Emin017 in #4646)
• Update CONTRIBUTING.md build and test instructions (by @jackkoenig in #4660)
• [website] Host latest and snapshot Scala CLI examples (by @jackkoenig in #4715)
  You can now download the latest release Scala CLI example with:

  curl -O -L https://chisel-lang.org/releases/latest/download/chisel-example.scala
  

  And download for the latest snapshot with:

  curl -O -L https://chisel-lang.org/releases/snapshot/download/chisel-example.scala
  

• [docs] Add ChiselSim, FileCheck documentation (by @seldridge in #4760)
• [docs] Fix wrong argument docs in SRAM object (by @CSharperMantle in #4827)
  This PR fixes the inconsistency of argument names in signatures and Scaladocs in two overloads of SRAM.apply. It is a pure documentation change and impacts no executable code.
• Create PROJECT_CHARTER.md (by @bensternthal in #4869)

Dependency Updates

• Update upickle to 3.3.1 (by @scala-steward in #4135)
• [cd] Bump CIRCT from firtool-1.77.0 to firtool-1.78.0 (by @chiselbot in #4296)
• [cd] Bump CIRCT from firtool-1.78.0 to firtool-1.78.1 (by @chiselbot in #4297)
• [cd] Bump CIRCT from firtool-1.78.1 to firtool-1.79.0 (by @chiselbot in #4314)
• [cd] Bump CIRCT from firtool-1.79.0 to firtool-1.80.0 (by @chiselbot in #4325)
• [cd] Bump CIRCT from firtool-1.80.0 to firtool-1.80.1 (by @chiselbot in #4334)
• [cd] Bump CIRCT from firtool-1.80.1 to firtool-1.81.0 (by @chiselbot in #4339)
• [cd] Bump CIRCT from firtool-1.81.0 to firtool-1.81.1 (by @chiselbot in #4342)
• [cd] Bump CIRCT from firtool-1.81.1 to firtool-1.82.0 (by @chiselbot in #4357)
• [cd] Bump CIRCT from firtool-1.82.0 to firtool-1.83.0 (by @chiselbot in #4366)
• [cd] Bump CIRCT from firtool-1.83.0 to firtool-1.84.0 (by @chiselbot in #4377)
• [cd] Bump CIRCT from firtool-1.84.0 to firtool-1.85.0 (by @chiselbot in #4385)
• [cd] Bump CIRCT from firtool-1.85.0 to firtool-1.86.0 (by @chiselbot in #4401)
• Add Scala 2.13.15 to compiler plugin cross-build (by @jackkoenig in #4410)
  Add support for Scala 2.13.15
• Bump to Scala 2.13.15 (by @jackkoenig in #4414)
• [cd] Bump CIRCT from firtool-1.86.0 to firtool-1.87.0 (by @chiselbot in #4450)
• [cd] Bump CIRCT from firtool-1.87.0 to firtool-1.88.0 (by @chiselbot in #4457)
• [cd] Bump CIRCT from firtool-1.88.0 to firtool-1.89.0 (by @chiselbot in #4474)
• [cd] Bump CIRCT from firtool-1.89.0 to firtool-1.90.1 (by @chiselbot in #4491)
• [cd] Bump CIRCT from firtool-1.90.1 to firtool-1.91.0 (by @chiselbot in #4493)
• [cd] Bump CIRCT from firtool-1.91.0 to firtool-1.92.0 (by @chiselbot in #4499)
• [cd] Bump CIRCT from firtool-1.92.0 to firtool-1.93.1 (by @chiselbot in #4514)
• [cd] Bump CIRCT from firtool-1.93.1 to firtool-1.94.0 (by @chiselbot in #4521)
• [cd] Bump CIRCT from firtool-1.94.0 to firtool-1.95.0 (by @chiselbot in #4523)
• [cd] Bump CIRCT from firtool-1.95.0 to firtool-1.95.1 (by @chiselbot in #4524)
• [cd] Bump CIRCT from firtool-1.95.1 to firtool-1.96.0 (by @chiselbot in #4546)
• [cd] Bump CIRCT from firtool-1.96.0 to firtool-1.97.1 (by @chiselbot in #4553)
• [cd] Bump CIRCT from firtool-1.97.1 to firtool-1.98.0 (by @chiselbot in #4561)
• [cd] Bump CIRCT from firtool-1.98.0 to firtool-1.99.0 (by @chiselbot in #4568)
• [cd] Bump CIRCT from firtool-1.99.0 to firtool-1.99.1 (by @chiselbot in #4571)
• [cd] Bump CIRCT from firtool-1.99.1 to firtool-1.99.2 (by @chiselbot in #4573)
• [cd] Bump CIRCT from firtool-1.99.1 to firtool-1.99.2 (by @chiselbot in #4574)
• [cd] Bump CIRCT from firtool-1.99.2 to firtool-1.100.0 (by @chiselbot in #4612)
• Migrate to mill 0.12.5 and refactor mill scripts (by @unlsycn in #4616)
• [cd] Bump CIRCT from firtool-1.100.0 to firtool-1.101.0 (by @chiselbot in #4630)
• [ci] Bump to JDK 21 (by @unlsycn in #4632)
• [cd] Bump CIRCT from firtool-1.101.0 to firtool-1.102.0 (by @chiselbot in #4637)
• [cd] Bump CIRCT from firtool-1.102.0 to firtool-1.103.0 (by @chiselbot in #4645)
• Bump firtool-resolver to 2.0.1 (by @jackkoenig in #4653)
  This improves firtool-resolver's thread-safety between different processes.
• [cd] Bump CIRCT from firtool-1.103.0 to firtool-1.104.0 (by @chiselbot in #4655)
• [cd] Bump CIRCT from firtool-1.104.0 to firtool-1.105.0 (by @chiselbot in #4671)
• [cd] Bump CIRCT from firtool-1.105.0 to firtool-1.106.0 (by @chiselbot in #4701)
• [cd] Bump CIRCT from firtool-1.106.0 to firtool-1.107.0 (by @chiselbot in #4719)
• [cd] Bump CIRCT from firtool-1.107.0 to firtool-1.108.0 (by @chiselbot in #4758)
• Bump to and cross-compile for Scala 2.13.16 (by @jackkoenig in #4691)
• Update commons-text to 1.13.0 (by @scala-steward in #4581)
• [cd] Bump CIRCT from firtool-1.108.0 to firtool-1.109.0 (by @chiselbot in #4781)
• Update data-class to 0.2.7 (by @scala-steward in #4658)
• [cd] Bump CIRCT from firtool-1.109.0 to firtool-1.110.0 (by @chiselbot in #4822)
• [cd] Bump CIRCT from firtool-1.110.0 to firtool-1.111.0 (by @chiselbot in #4843)
• [cd] Bump CIRCT from firtool-1.111.0 to firtool-1.111.1 (by @chiselbot in #4854)
• [cd] Bump CIRCT from firtool-1.111.1 to firtool-1.112.0 (by @chiselbot in #4863)
• [cd] Bump CIRCT from firtool-1.112.0 to firtool-1.113.0 (by @chiselbot in #4885)
• [cd] Bump CIRCT from firtool-1.113.0 to firtool-1.114.0 (by @chiselbot in #4897)
• [cd] Bump CIRCT from firtool-1.114.0 to firtool-1.114.1 (by @chiselbot in #4904)
• Update commons-text to 1.13.1 (by @scala-steward in #4905)

Build and Internal Changes

• Add permissions to website deployment job (by @jackkoenig in #4285)
• Represent SRAM Mask as Data (by @jackkoenig in #4321)
  This replaces a hack where we directly manipulated the IR to create the mask and necessary connections.
• [cd] Guard cd-circt PR on llvm-firtool publish to Maven (by @jackkoenig in #4330)
  Now CIRCT bumping CD will wait for the repackaging of firtool as a Maven dependency for use with firtool-resolver.
• [mill] Enhance Mill flow to download jextract and circt-full (by @sequencer in #4383)
• [mill] Get unit testing working (by @jackkoenig in #4384)
• Switch publishing to use Mill (by @jackkoenig in #4438)
• BoringUtilsTapSpec: remove debugging print (by @dtzSiFive in #4453)
• Introduce Blocks, track, use for improved scope checking and boring (by @dtzSiFive in #4443)
• [Scala3] Refactor Printf and VerificationStatement macros (by @adkian-sifive in #4449)
  Separate and move Printf and VerificationStatement macros in preparation of Scala3 support
• [mill] Copy scalacOptions over to mill, add instructions to CONTRIBUTING (by @jackkoenig in #4462)
  Normal development should use Mill instead of SBT from now on.
• [Scala3] Add core -Xsource:3 for Scala3 cross compilation support (by @adkian-sifive in #4431)
  Adds -Xsource:3 to core in preparation of Scala3 migration. Add stricter type ascriptions for Scala3:
  • ResetType.litOption return type changed from None to Option[BigInt]
  • AsyncReset.litOption return type changed from None to Option[BigInt]
  • RequireAsyncReset.resetType type changed from ResetType.Type to Asynchronous.type
  • RequireAsyncReset.resetType type changed from ResetType.Type to Synchronous.type
  • CrossModuleBinding.location return type changed from None.type to Option[BaseModule]
• [CI] Use Mill for testing (by @jackkoenig in #4466)
• [Scala3] [Mill] Add Xsource:3 to core in Mill to match SBT (by @adkian-sifive in #4468)
  Add -Xsource:3 to Mill core compilation unit
• [Scala3] Add cross build support to Mill (by @adkian-sifive in #4492)
  Mill build files were refactored to support differentiated module dependencies and compilation options between Scala versions
• [Scala3] Scala2 compatibility changes (by @adkian-sifive in #4483)
  Minor refactoring for compatibility with Scala3. Factory objects from package.scala are moved to live with their defining classes for compatibility with Dotty. Macros and reflection moved to scala-2 API directory.
• Restore common scalacOptions to project chisel (by @jackkoenig in #4507)
• [Scala3] Scala2 src compatibility changes for Scala3 (by @adkian-sifive in #4518)
  Sources were refactored and updated in preparation of upcoming Scala3 support
• Update CD permissions for uploading release artifacts (by @jackkoenig in #4529)
  Also bump softprops/action-gh-release to v2.1.0.
• [CI] Run tests in parallel (by @jackkoenig in #4533)
• Add partial cross-compilation for Scala 3 (by @adkian-sifive in #4549)
  Adds initial support for Scala 3 LTS version 3.3.3
• Move Scala runtime isSingleton to Java runtime (by @adkian-sifive in #4608)
  Replace Scala runtime isSingleton in firrtl subproject to with cross-compiling Java runtime equivalent
• Replace ??? with UnlocatableSourceInfo (by @adkian-sifive in #4624)
  Update Scala3 materialize with a temporary placeholder UnlocatableSourceInfo
• Fix typo in #4632: correct JVM version (by @unlsycn in #4633)
• Upgrade Scalafmt to 3.8.5 and reformat (by @jackkoenig in #4566)
• [mill] Guard scalaReflect under not Scala 3 in macros (by @jackkoenig in #4640)
• Fix chisel-plugin artifact publishing (by @jackkoenig in #4648)
• Add -release:8 to scalacOptions (by @jackkoenig in #4649)
  This ensures published Chisel artifacts work with Java 8--both in generated bytecode (which was previously true because default setting is -target:8), but also in disallowing APIs added in newer JDKs.
• [ci] Speed up tests with testForkGrouping (by @jackkoenig in #4650)
• Update mergify config generator and config (by @jackkoenig in #4654)
• Update mill-main to 0.12.7 (by @scala-steward in #4657)
• Add publish flow for panama modules (by @unlsycn in #4661)
• Revert "Add publish flow for panama modules" (by @jackkoenig in #4667)
• Add publish flow for panama modules (by @unlsycn in #4670)
• Fix misoverrided publish version (by @unlsycn in #4672)
• Move tests to src/test/scala-2 (by @adkian-sifive in #4607)
  Tests moved to scala-2 directory to facilitate smoother Scala 3 development
• [Scala3] Cross compile Simulator (by @adkian-sifive in #4679)
  Simulator API now cross compiles with Scala 3.
• Support mdoc from Mill and remove SBT (by @jackkoenig in #4727)
• Switch from veneers to private macro interfaces (by @jackkoenig in #4768)
• [Scala3] Update build files to support Scala3 plugins (by @adkian-sifive in #4888)
  Build files have been updated to support plugins in Scala 3.
• [Scala3] Add ChiselComponent plugin (by @adkian-sifive in #4889)
  Adds initial Scala3 naming plugin
• build: bump to mill 0.12.10 (by @unlsycn in #4876)
• [Scala3] Add test compilation to CI (by @adkian-sifive in #4900)
  Add compilation of all cross-version tests to CI; update or move tests failing with Scala 3
• Refactor publishing logic (by @jackkoenig in #4901)
  mill-ci-release is archived and we were accidentally publishing the compiler plugin for Scala 3.

Full Changelog: v7.0.0-M2...v7.0.0-RC1