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…g-to-routing/vtr-verilog-to-routing into eliminate_free_and_malloc
…rilog-to-routing into placement_search_range
When timing analysis was turned on for AP, we originally only used the pre-cluster timing analyzer which was very high-level and innacurate. It practically just counted the number of hops between launch and capture registers to approximate criticality. Improved this by using flat placement information provided by AP. During global placement, the criticality of all edges are recomputed using the upper bound solution from the prior iteration of GP. The place delay model from the placement flow was used to get an mostly-accurate delay estimation for distances between tiles. The slacks computed each GP iteration are used to update the net weights between iterations to better optimize CPD and sTNS. This improved estimation of setup slacks is then passed into the full legalizer, which it is then used by the packer to better pack critical atoms together. This change required some changes to the APNetlist. Notably, we need all atom nets to be located somewhere in the AP netlist such that their delays can be calculated properly. Instead of removing nets we do not care about for AP, marked them as ignored.
The Clang builds were warning that there were several forward declarations of structs which were supposed to be classes and vice-versa. This is not necessarily a problem since in C++ classes and structs end up being basically the same from the compiler's perspective, but its still incorrect. Fixed the cases I could see in the Clang builds.
…alloc Eliminate vtr_free and vtr_malloc/vtr_calloc/vtr_realloc
…ward-declarations [Infra] Fixed False Forward Declarations
[AP][Timing] Used Flat Placement Info to Compute Setup Criticalities
Bumps [libs/EXTERNAL/libcatch2](https://github.com/catchorg/Catch2) from `5abfc0a` to `74fcff6`. - [Release notes](https://github.com/catchorg/Catch2/releases) - [Commits](catchorg/Catch2@5abfc0a...74fcff6) --- updated-dependencies: - dependency-name: libs/EXTERNAL/libcatch2 dependency-version: 74fcff6e5b190fb833a231b7f7c1829e3c3ac54d dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
…s/libs/EXTERNAL/libcatch2-74fcff6 Bump libs/EXTERNAL/libcatch2 from `5abfc0a` to `74fcff6`
…rilog-to-routing into placement_search_range
Pin to Pin annotations were stored as C-style arrays which creates confusing pointers around VTR. Converted to a standard vector.
…ay-cleanup [Infra] Converted Pin to Pin Annotations into Vector
Improve comments in Makefile
While presenting my tutorial on post-implementation timing analysis, I found that the SDC file generated did not look quite right. It was functionally correct, but some of the new-line characters were missing. Added the missing new line characters.
The titanium benchmarks were not being tested by the CI. Added the Titanium benchmarks which could be run in under around 2 hours to NightlyTest7. 5 circuits in this benchmark set currently fail through VTR. The failures are mainly in the initial placer, which is struggling to create an initial placement when logical blocks can be placed into different physical block types which are constrained resources.
[Place] Expand search range for sparse blocks
…t-fix [STA] Updated Tutorial
…-task [CI] Added Quick Titanium S10 Tests
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