[pull] master from verilog-to-routing:master #565
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VPR
libarchfpga
lang-python
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Fixing documentation build
VPR is moving to a style that uses "#pragma once" instead of header gaurds. These are less error prone and may be slightly more performant. Converted all of the header gaurds in VPR into pragma once's. Also moved all pragma onces to the top of all header files to maintain a consistent style. It is a good idea to have them as the very first line in all header files. While going through all header files, cleaned up any extra header includes which were including things they did not need.
[Infra] The Great VPR Pragma PR
Add ezgl Doxygen api documentation to to the VTR docs
…g on verbosity to the developer guide.
Added basic information on building with debug information and verbose output to developer guide
A failing python formatting check got into Master. Fixing it.
[HotFix] Fix Failing Python Formatting Check
[LibArchFPGA] Added Library Model IDs as constexpr
[STA] Enabled Dedicated Routing SDC Generation
Different build variations of VTR were being run on different CI runners which was wasteful. Consolidated these build variations into a single job which will run on a single runner.
[CI] Consolidated Build Variation Tests
…not robust for stage except the route. add doxygen doc for is_net_routed and is_net_fully_absorbed
Vpr viewer and flat routing on
…upload-vprout Upload vpr.out in nightly_test_manual artifacts
Updated the header files in the non-external libraries of VTR such that they use pragma once instead of ifdefs and removed false include files.
Clean up the usage tracking in grid blocks.
[Infra] Cleaned Up Includes in Non-External Libs
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