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[WIP] Use compressed grid locations in windowed bimatching detailed placer - #3742

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[WIP] Use compressed grid locations in windowed bimatching detailed placer#3742
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@AthavanBalakumar

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Updating windowed bipartite matching detailed placer to generate candidate moves using VTR's compressed block grids instead of fixed physical-grid neighbor locations.

The placer now searches compatible locations in compressed-grid space based on each block's logical type. Currently the scope is conservative, skips placement macro members, restricts occupied swaps to blocks of the same logical type, allows moves into empty compatible locations, and keeps floorplan legality checks.

This is a step towards heterogeneous architecture support.

@github-actions github-actions Bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Aug 4, 2026
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Compared the compressed-grid windowed detailed placer against --ap_detailed_placer none on a hetero test (using k6_frac_N10_frac_chain_mem32K_40nm.xml). Routed wirelength improved on the three tested circuits, min channel width improved on or1200 and sha but worsened on ch_intrinsics.

Circuit None routed_wirelength Windowed routed_wirelength New/old ratio routed_wirelength None min_chan_width Windowed min_chan_width New/old ratio min_chan_width
ch_intrinsics.v 1954 1780 0.910952 32 34 1.062500
or1200.v 41221 39957 0.969336 82 80 0.975610
sha.v 13450 12135 0.902230 82 78 0.951220

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