Stratix 10 Quad Port Ram Support #3180
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soheilshahrouz
requested changes
Jul 2, 2025
| if (ram_info.port_a_output_clock && ram_info.port_b_output_clock) { | ||
| reg_outputs = true; //Sequential output | ||
| } else if (!ram_info.port_a_output_clock && !ram_info.port_b_output_clock) { | ||
| reg_outputs = false; //Comb output |
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Please edit the comments in your code to be consistent the coding style guide:
- Add a space after
// - Avoid using block comments for implementation-related commnets
| @@ -613,8 +625,9 @@ void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, st | |||
| } | |||
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| //A dual port memory, both port A and B params have been found | |||
| } else { | |||
| VTR_ASSERT(ram_info.mode == "dual_port" || ram_info.mode == "bidir_dual_port"); | |||
| } else if (ram_info.mode == "dual_port" || ram_info.mode == "bidir_dual_port"){ | |||
| } else { | ||
| //3b) Use the more detailed name, since it was found in the architecture | ||
| mode_hash = tmp_mode_hash; | ||
| } |
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re-write this if statement get rid of the branch where nothing is done
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This pull request adds support for quad-port RAM in the Stratix 10 architecture file. It also updates the vqm2blif tool to process quad-port RAMs from VQM files and generate the appropriate operation modes in the BLIF output. Additionally, it makes a small modification to the MLAB primitives in the architecture capture by adding the class=memory attribute, enabling VPR to correctly pack MLABs slices in to MLAB primitives.