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[NetlistWriter] Fixed Failing Nightly Test #3172

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AlexandreSinger
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The nightly test for the netlist writer was failing due to changes in the clock to Q delays. After some digging, I found that there was an oversight in the netlist writer code when it generates ram black boxes.

Someone hard-coded the name of the clock port to "clock", when in reality the port's name is "clk". This was a very simple fix.

This resolves the failures in NightlyTest2:

image

The nightly test for the netlist writer was failing due to changes in
the clock to Q delays. After some digging, I found that there was an
oversight in the netlist writer code when it generates ram black boxes.

Someone hard-coded the name of the clock port to "clock", when in
reality the port's name is "clk". This was a very simple fix.
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Jun 30, 2025
@AmirhosseinPoolad
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LGTM

@AmirhosseinPoolad AmirhosseinPoolad merged commit 29cc58d into verilog-to-routing:master Jul 2, 2025
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2 participants