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verilog-to-routing / vtr-verilog-to-routing Public

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Add tileable RR Graph#3134

Open

amin1377 wants to merge 62 commits intomasterverilog-to-routing/vtr-verilog-to-routing:masterfrom

add_tileable_rr_graphverilog-to-routing/vtr-verilog-to-routing:add_tileable_rr_graphCopy head branch name to clipboard

Conversation Commits62 (62)Checks Files changed

Open

Add tileable RR Graph#3134
amin1377 wants to merge 62 commits intomasterfrom
add_tileable_rr_graph

Commits

Commits on Jun 11, 2025

[vpr][rr_graph] add tileable rr graph dir
amin1377
committed
[vpr][rr_graph] move tileable rr graph dir uner rr_graph_generation
amin1377
committed
[vpr][route] update rr_graph generation with tileable rr graph
amin1377
committed
[vpr][util] add is_inter_cluster_node for vib arch
amin1377
committed
[vpr][route] update router lookahead with tileable rr graph
amin1377
committed
[vpr][blif] use regex to find param val
amin1377
committed
[vpr][base] update with tileable rr graph
amin1377
committed
[vpr][route] remove unused param
amin1377
committed
[lib][arch] add vib processing
amin1377
committed
[lib][arch] add vib_inf
amin1377
committed
[libs][rr_graph] update lib rr graph with tileable
amin1377
committed
[libs][rr graph][io] update read/write rr graph functions with tileable info
amin1377
committed
[libs][rr graph][io] update rr_grpah utils with tileable info
amin1377
committed
[lib][rr_graph] add vtr tokenizer
amin1377
committed
[lib][util] update capnp and util with open fpga
amin1377
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add openfpga doc
amin1377
committed
[vpr][base] add vib grid
amin1377
committed
add VIB doc
amin1377
committed
[vpr][route] fix alloc_and_load_rr_switch_inf definition
amin1377
committed
make format
amin1377
committed
[vtr_flow][test] add openfpga arch
amin1377
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[CI] add openfpga tests
amin1377
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fix formatting
amin1377
committed

Commits on Jun 12, 2025

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into add_tileable_rr_graph
amin1377
committed
[doc][arch] add tileable doc
amin1377
committed

Commits on Jun 16, 2025

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into add_tileable_rr_graph
amin1377
committed
[libs][arch] add function declarations
amin1377
committed
[rr_graph] change MEDIUM node type name and related function to MUX
amin1377
committed
[libs][arch] add process_bend
amin1377
committed
make format
amin1377
committed
[doc] fix a typo in .bib file
amin1377
committed
[vpr] remove redundant version of is_inter_cluster_node
amin1377
committed

Commits on Jun 18, 2025

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into add_tileable_rr_graph
amin1377
committed
[doc][arch] move openfpga doc to the end of the file
amin1377
committed
[doc][arch] add figures related to direct connection
amin1377
committed
[doc][arch] add doc related to tileable direct interconnect
amin1377
committed
[arch] change isbend to is_bend
amin1377
committed
[tileable_rr_graph] fix sub_fs formatting
amin1377
committed
[rr_graph] comment tileable rr_graph function under rr_graph_builder.h
amin1377
committed
[libs][rr_graph] mode bend_start/end out of t_rr_node_data
amin1377
committed
[base] fix function names formatting
amin1377
committed
make format
amin1377
committed
[libs][matrix] check for size before filling the matrix
amin1377
committed

Commits on Jun 19, 2025

[libs][rr_graph] fix node_bend_start/end size
amin1377
committed
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into add_tileable_rr_graph
amin1377
committed
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into add_tileable_rr_graph
amin1377
committed

Commits on Jun 23, 2025

[libs][arch] fix c-style code in read_xml_arch_file
amin1377
committed
[lib][arch] fix process_vib_block_type_locs style
amin1377
committed
[lib][arch] pass set funcitons params by reference
amin1377
committed
Apply code review comment
amin1377
committed
make format
amin1377
committed

Commits on Jun 24, 2025

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into add_tileable_rr_graph
amin1377
committed
fix a typo
amin1377
committed
[libs][arch] fix clang-17 warning
amin1377
committed
[vpr][route][tileable] replace VTR_LOG to VTR_LOG_DEBUG & fix c-style code
amin1377
committed
[libs][vtrutil] fix string_view error
amin1377
committed

Commits on Jun 25, 2025

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into add_tileable_rr_graph
amin1377
committed
[vpr][utils] move StringToken under vtr util
amin1377
committed
[vpr][base] remove unnecessary auto
amin1377
committed
[vpr] apply code format rules to tileable RR Graph files
amin1377
committed
[libs][arch] move vib arch functions to a separate file
amin1377
committed
make format
amin1377
committed

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