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Merged
vaughnbetz merged 18 commits into from
May 30, 2025
Merged

Eliminate vtr_free and vtr_malloc/vtr_calloc/vtr_realloc #3040

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efd922c
removed most mallocs
SamuelHo10 May 13, 2025
2f679a7
Merge branch 'eliminate_free_and_malloc' of https://github.com/verilo…
SamuelHo10 May 13, 2025
0bdb49f
replaced most of the callocs with news
SamuelHo10 May 14, 2025
7cb2095
formatted c++
SamuelHo10 May 14, 2025
2c12600
undid a couple changes to fix odin memory leak
SamuelHo10 May 14, 2025
c0bf94c
replaced t_clock_arch with std::shared_ptr<std::vector<t_clock_network>>
SamuelHo10 May 20, 2025
e7b470a
Repaced prop and value in t_pin_to_pin_annotation with std::pair
SamuelHo10 May 23, 2025
e8875c7
replaced char[level+1] with std::string
SamuelHo10 May 23, 2025
3256475
changed calloc to new
SamuelHo10 May 26, 2025
d04d41f
fixed memory leak
SamuelHo10 May 26, 2025
81eba83
added default constructors
SamuelHo10 May 27, 2025
700cc75
fixed build issues and improved pair for loops
SamuelHo10 May 27, 2025
ba39dae
Merge branch 'master' into eliminate_free_and_malloc
SamuelHo10 May 30, 2025
d0c4cb9
renamed pairs and replaced .first and .second with ={} notation
SamuelHo10 May 30, 2025
1193d3b
removed unecessary if statements to check for nullptr
SamuelHo10 May 30, 2025
6eb6a8f
moved loop variable definitions to loop
SamuelHo10 May 30, 2025
c658a87
Merge branch 'eliminate_free_and_malloc' of https://github.com/verilo…
SamuelHo10 May 30, 2025
faa099d
make format
SamuelHo10 May 30, 2025
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108 changes: 35 additions & 73 deletions libs/libarchfpga/src/arch_util.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -162,10 +162,6 @@ void free_arch(t_arch* arch) {

vtr::free(arch->architecture_id);

if (arch->clocks) {
vtr::free(arch->clocks->clock_inf);
}

delete (arch->noc);
}

Expand Down Expand Up @@ -332,30 +328,22 @@ static void free_pb_type(t_pb_type* pb_type) {
if (pb_type->modes[i].interconnect[j].annotations[k].output_pins) {
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].output_pins);
}
for (int m = 0; m < pb_type->modes[i].interconnect[j].annotations[k].num_value_prop_pairs; ++m) {
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]);
}
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].prop);
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value);

}
vtr::free(pb_type->modes[i].interconnect[j].annotations);
delete[] pb_type->modes[i].interconnect[j].annotations;
if (pb_type->modes[i].interconnect[j].interconnect_power)
vtr::free(pb_type->modes[i].interconnect[j].interconnect_power);
delete pb_type->modes[i].interconnect[j].interconnect_power;
}
if (pb_type->modes[i].interconnect)
delete[] pb_type->modes[i].interconnect;
if (pb_type->modes[i].mode_power)
vtr::free(pb_type->modes[i].mode_power);
delete (pb_type->modes[i].mode_power);
}
if (pb_type->modes)
delete[] pb_type->modes;

for (int i = 0; i < pb_type->num_annotations; ++i) {
for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) {
vtr::free(pb_type->annotations[i].value[j]);
}
vtr::free(pb_type->annotations[i].value);
vtr::free(pb_type->annotations[i].prop);

if (pb_type->annotations[i].input_pins) {
vtr::free(pb_type->annotations[i].input_pins);
}
Expand All @@ -371,7 +359,7 @@ static void free_pb_type(t_pb_type* pb_type) {
}

if (pb_type->pb_type_power) {
vtr::free(pb_type->pb_type_power);
delete pb_type->pb_type_power;
}

for (int i = 0; i < pb_type->num_ports; ++i) {
Expand All @@ -380,10 +368,10 @@ static void free_pb_type(t_pb_type* pb_type) {
vtr::free(pb_type->ports[i].port_class);
}
if (pb_type->ports[i].port_power) {
vtr::free(pb_type->ports[i].port_power);
delete pb_type->ports[i].port_power;
}
}
vtr::free(pb_type->ports);
delete[] pb_type->ports;
}

t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, int* low_index) {
Expand Down Expand Up @@ -476,7 +464,7 @@ std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical
void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
char* new_name,
t_pb_type* copy) {
int i, j;
int i;
char* dot;

VTR_ASSERT(pb_type->blif_model != nullptr);
Expand All @@ -495,13 +483,12 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
copy->num_pb = 1;

/* Power */
copy->pb_type_power = (t_pb_type_power*)vtr::calloc(1,
sizeof(t_pb_type_power));
copy->pb_type_power = new t_pb_type_power();
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copy->pb_type_power->estimation_method = power_method_inherited(pb_type->pb_type_power->estimation_method);

/* Ports */
copy->num_ports = pb_type->num_ports;
copy->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port));
copy->ports = new t_port[pb_type->num_ports]();
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for (i = 0; i < pb_type->num_ports; i++) {
copy->ports[i].is_clock = pb_type->ports[i].is_clock;
copy->ports[i].model_port = pb_type->ports[i].model_port;
Expand All @@ -514,8 +501,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
copy->ports[i].index = pb_type->ports[i].index;
copy->ports[i].absolute_first_pin_index = pb_type->ports[i].absolute_first_pin_index;

copy->ports[i].port_power = (t_port_power*)vtr::calloc(1,
sizeof(t_port_power));
copy->ports[i].port_power = new t_port_power();
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//Defaults
if (copy->pb_type_power->estimation_method == POWER_METHOD_AUTO_SIZES) {
copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_AUTO;
Expand Down Expand Up @@ -548,13 +534,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
copy->annotations[i].line_num = pb_type->annotations[i].line_num;
copy->annotations[i].format = pb_type->annotations[i].format;
copy->annotations[i].type = pb_type->annotations[i].type;
copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs;
copy->annotations[i].prop = (int*)vtr::malloc(sizeof(int) * pb_type->annotations[i].num_value_prop_pairs);
copy->annotations[i].value = (char**)vtr::malloc(sizeof(char*) * pb_type->annotations[i].num_value_prop_pairs);
for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) {
copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j];
copy->annotations[i].value[j] = vtr::strdup(pb_type->annotations[i].value[j]);
}
copy->annotations[i].pairs = pb_type->annotations[i].pairs;
}
}

Expand All @@ -563,7 +543,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
char* default_name;
t_port* in_port;
t_port* out_port;
int i, j;
int i;

if (strcmp(lut_pb_type->name, "lut") != 0) {
default_name = vtr::strdup("lut");
Expand All @@ -580,8 +560,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
lut_pb_type->modes[0].parent_pb_type = lut_pb_type;
lut_pb_type->modes[0].index = 0;
lut_pb_type->modes[0].num_pb_type_children = 0;
lut_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1,
sizeof(t_mode_power));
lut_pb_type->modes[0].mode_power = new t_mode_power();

/* Process interconnect */
/* TODO: add timing annotations to route-through */
Expand Down Expand Up @@ -613,10 +592,9 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {

lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0;
lut_pb_type->modes[0].interconnect[0].parent_mode = &lut_pb_type->modes[0];
lut_pb_type->modes[0].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power));
lut_pb_type->modes[0].interconnect[0].interconnect_power = new t_interconnect_power();
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lut_pb_type->modes[0].interconnect[0].annotations = (t_pin_to_pin_annotation*)vtr::calloc(lut_pb_type->num_annotations,
sizeof(t_pin_to_pin_annotation));
lut_pb_type->modes[0].interconnect[0].annotations = new t_pin_to_pin_annotation[lut_pb_type->num_annotations]();
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lut_pb_type->modes[0].interconnect[0].num_annotations = lut_pb_type->num_annotations;
for (i = 0; i < lut_pb_type->modes[0].interconnect[0].num_annotations;
i++) {
Expand All @@ -626,15 +604,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
lut_pb_type->modes[0].interconnect[0].annotations[i].line_num = lut_pb_type->annotations[i].line_num;
lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format;
lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type;
lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs;
lut_pb_type->modes[0].interconnect[0].annotations[i].prop = (int*)vtr::malloc(sizeof(int)
* lut_pb_type->annotations[i].num_value_prop_pairs);
lut_pb_type->modes[0].interconnect[0].annotations[i].value = (char**)vtr::malloc(sizeof(char*)
* lut_pb_type->annotations[i].num_value_prop_pairs);
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j];
lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]);
}

lut_pb_type->modes[0].interconnect[0].annotations[i].pairs = lut_pb_type->annotations[i].pairs;
}

/* Second mode, LUT */
Expand All @@ -643,30 +614,24 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
lut_pb_type->modes[1].parent_pb_type = lut_pb_type;
lut_pb_type->modes[1].index = 1;
lut_pb_type->modes[1].num_pb_type_children = 1;
lut_pb_type->modes[1].mode_power = (t_mode_power*)vtr::calloc(1,
sizeof(t_mode_power));
lut_pb_type->modes[1].mode_power = new t_mode_power();
lut_pb_type->modes[1].pb_type_children = new t_pb_type[1];
alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name,
lut_pb_type->modes[1].pb_type_children);
/* moved annotations to child so delete old annotations */
for (i = 0; i < lut_pb_type->num_annotations; i++) {
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
free(lut_pb_type->annotations[i].value[j]);
}
free(lut_pb_type->annotations[i].value);
free(lut_pb_type->annotations[i].prop);
if (lut_pb_type->annotations[i].input_pins) {
free(lut_pb_type->annotations[i].input_pins);
vtr::free(lut_pb_type->annotations[i].input_pins);
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@vaughnbetz vaughnbetz May 16, 2025

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Possibly we could convert these C-strings to std::string so we don't need free calls for them, but it depends on how many places they are used (how much code you have to go change to use C++ strings)

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@vaughnbetz vaughnbetz May 16, 2025

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Same for .output_pins and .clock

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@SamuelHo10 SamuelHo10 May 27, 2025

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Will do that in another PR

}
if (lut_pb_type->annotations[i].output_pins) {
free(lut_pb_type->annotations[i].output_pins);
vtr::free(lut_pb_type->annotations[i].output_pins);
}
if (lut_pb_type->annotations[i].clock) {
free(lut_pb_type->annotations[i].clock);
vtr::free(lut_pb_type->annotations[i].clock);
}
}
lut_pb_type->num_annotations = 0;
free(lut_pb_type->annotations);
vtr::free(lut_pb_type->annotations);
lut_pb_type->annotations = nullptr;
lut_pb_type->modes[1].pb_type_children[0].depth = lut_pb_type->depth + 1;
lut_pb_type->modes[1].pb_type_children[0].parent_mode = &lut_pb_type->modes[1];
Expand Down Expand Up @@ -694,7 +659,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {

lut_pb_type->modes[1].interconnect[0].parent_mode_index = 1;
lut_pb_type->modes[1].interconnect[0].parent_mode = &lut_pb_type->modes[1];
lut_pb_type->modes[1].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power));
lut_pb_type->modes[1].interconnect[0].interconnect_power = new t_interconnect_power();

lut_pb_type->modes[1].interconnect[1].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 11, sizeof(char));
sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s",
Expand All @@ -713,7 +678,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {

lut_pb_type->modes[1].interconnect[1].parent_mode_index = 1;
lut_pb_type->modes[1].interconnect[1].parent_mode = &lut_pb_type->modes[1];
lut_pb_type->modes[1].interconnect[1].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power));
lut_pb_type->modes[1].interconnect[1].interconnect_power = new t_interconnect_power();

free(default_name);

Expand All @@ -738,8 +703,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
mem_pb_type->modes[0].name = vtr::strdup(default_name);
mem_pb_type->modes[0].parent_pb_type = mem_pb_type;
mem_pb_type->modes[0].index = 0;
mem_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1,
sizeof(t_mode_power));
mem_pb_type->modes[0].mode_power = new t_mode_power();
num_pb = OPEN;
for (i = 0; i < mem_pb_type->num_ports; i++) {
if (mem_pb_type->ports[i].port_class != nullptr
Expand Down Expand Up @@ -835,8 +799,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
}

/* Allocate interconnect power structures */
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1,
sizeof(t_interconnect_power));
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power();
i_inter++;
} else {
for (j = 0; j < num_pb; j++) {
Expand Down Expand Up @@ -876,8 +839,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
}

/* Allocate interconnect power structures */
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1,
sizeof(t_interconnect_power));
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power();
i_inter++;
}
}
Expand Down Expand Up @@ -944,7 +906,7 @@ void SyncModelsPbTypes_rec(t_arch* arch,

pb_type->model_id = model_match_prim_id;
vtr::t_linked_vptr* old = model_match_prim.pb_types;
model_match_prim.pb_types = (vtr::t_linked_vptr*)vtr::malloc(sizeof(vtr::t_linked_vptr));
model_match_prim.pb_types = new vtr::t_linked_vptr;
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@vaughnbetz vaughnbetz May 16, 2025

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We could probably change this linked list (which currently stores pb_type* pointers) to a vector of pb_type* (or maybe even just to direct pb_type elements). Probably don't do that yet though ... we should refactor in stages.

model_match_prim.pb_types->next = old;
model_match_prim.pb_types->data_vptr = pb_type;

Expand Down Expand Up @@ -1109,8 +1071,8 @@ const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_ty
const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot];
InstPort annot_in(annot->input_pins);
if (annot_in.port_name() == port->name) {
for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) {
if (annot->prop[iprop] == annot_type) {
for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) {
if (annot->pairs[iprop].first == annot_type) {
return annot;
}
}
Expand All @@ -1128,9 +1090,9 @@ const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb
for (const auto& annot_out_str : vtr::split(annot->output_pins)) {
InstPort out_pins(annot_out_str);
if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) {
if (annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MAX
|| annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) {
if (annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MAX
|| annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
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Outdated
return annot;
}
}
Expand Down
28 changes: 14 additions & 14 deletions libs/libarchfpga/src/echo_arch.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -335,19 +335,19 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
fprintf(Echo, "*************************************************\n");
fprintf(Echo, "Clock:\n");
if (arch->clocks) {
for (int i = 0; i < arch->clocks->num_global_clocks; i++) {
if (arch->clocks->clock_inf[i].autosize_buffer) {
fprintf(Echo, "\tClock[%d]: buffer_size auto C_wire %e", i + 1,
arch->clocks->clock_inf->C_wire);
for (size_t i = 0; i < arch->clocks->size(); i++) {
if ((*arch->clocks)[i].autosize_buffer) {
fprintf(Echo, "\tClock[%zu]: buffer_size auto C_wire %e", i + 1,
(*arch->clocks)[i].C_wire);
} else {
fprintf(Echo, "\tClock[%d]: buffer_size %e C_wire %e", i + 1,
arch->clocks->clock_inf[i].buffer_size,
arch->clocks->clock_inf[i].C_wire);
fprintf(Echo, "\tClock[%zu]: buffer_size %e C_wire %e", i + 1,
(*arch->clocks)[i].buffer_size,
(*arch->clocks)[i].C_wire);
}
fprintf(Echo, "\t\t\t\tstat_prob %f switch_density %f period %e",
arch->clocks->clock_inf[i].prob,
arch->clocks->clock_inf[i].dens,
arch->clocks->clock_inf[i].period);
(*arch->clocks)[i].prob,
(*arch->clocks)[i].dens,
(*arch->clocks)[i].period);
}
}

Expand Down Expand Up @@ -383,7 +383,7 @@ static void print_model(FILE* echo, const t_model& model) {
static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models) {
char* tabs;

tabs = (char*)vtr::malloc((level + 1) * sizeof(char));
tabs = new char[level + 1];
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for (int i = 0; i < level; i++) {
tabs[i] = '\t';
}
Expand Down Expand Up @@ -419,7 +419,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
pb_type->modes[i].interconnect[j].annotations[k].input_pins,
pb_type->modes[i].interconnect[j].annotations[k].output_pins,
pb_type->modes[i].interconnect[j].annotations[k].format,
pb_type->modes[i].interconnect[j].annotations[k].value[0]);
pb_type->modes[i].interconnect[j].annotations[k].pairs[0].second.c_str());
}
//Print power info for interconnects
if (pb_type->modes[i].interconnect[j].interconnect_power) {
Expand Down Expand Up @@ -447,15 +447,15 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
pb_type->annotations[k].input_pins,
pb_type->annotations[k].output_pins,
pb_type->annotations[k].format,
pb_type->annotations[k].value[0]);
pb_type->annotations[k].pairs[0].second.c_str());
}
}
}

if (pb_type->pb_type_power) {
PrintPb_types_recPower(Echo, pb_type, tabs);
}
free(tabs);
delete[] tabs;
}

//Added May 2013 Daniel Chen, help dump arch info after loading from XML
Expand Down
2 changes: 1 addition & 1 deletion libs/libarchfpga/src/logic_types.cpp
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -144,7 +144,7 @@ void LogicalModels::free_model_data(t_model& model) {
while (vptr) {
vtr::t_linked_vptr* vptr_prev = vptr;
vptr = vptr->next;
vtr::free(vptr_prev);
delete vptr_prev;
}

if (model.instances)
Expand Down
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