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[RegTests] Fixed VTR Nightly Test Failures #2785

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Merged
merged 1 commit into from
Oct 22, 2024
Merged

[RegTests] Fixed VTR Nightly Test Failures #2785

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2 changes: 1 addition & 1 deletion vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_fixed_chan_width.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -13,4 +13,4 @@ crit_path_route_time;RangeAbs(0.10,10.0,2)
#We set a 100MiB minimum threshold since the memory
#alloctor (e.g. TBB vs glibc) can cause a difference
#particularly on small benchmarks
max_vpr_mem;RangeAbs(0.8,1.203,102400)
max_vpr_mem;RangeAbs(0.8,1.35,102400)
4 changes: 2 additions & 2 deletions vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width_small.txt
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@@ -1,8 +1,8 @@
#VPR metrics at minimum channel width

#Routing Metrics
min_chan_width;Range(0.25,1.50)
routed_wirelength;RangeAbs(0.50,1.50,5)
min_chan_width;Range(0.25,1.70)
routed_wirelength;RangeAbs(0.50,1.75,5)

#Area metrics
logic_block_area_total;Range(0.5,1.6)
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6 changes: 3 additions & 3 deletions ...w/parse/pass_requirements/timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt
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Expand Up @@ -2,11 +2,11 @@
%include "../common/pass_requirements.vpr_route_relaxed_chan_width_small.txt"

#Routing Metrics
crit_path_routed_wirelength;Range(0.40,1.60)
crit_path_routed_wirelength;Range(0.40,1.90)

#Area Metrics
crit_path_routing_area_total;Range(0.5,1.5)
crit_path_routing_area_per_tile;Range(0.5,1.5)
crit_path_routing_area_total;Range(0.5,1.6)
crit_path_routing_area_per_tile;Range(0.5,1.6)

#Run-time Metrics
crit_path_route_time;RangeAbs(0.10,10.0,2)
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2 changes: 1 addition & 1 deletion .../tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt
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Expand Up @@ -15,7 +15,7 @@ archs_dir=arch/timing/fixed_size

# circuit_list_add=adder_001bits.v
# circuit_list_add=adder_002bits.v
circuit_list_add=adder_003bits.v
# circuit_list_add=adder_003bits.v
circuit_list_add=adder_004bits.v
circuit_list_add=adder_005bits.v
circuit_list_add=adder_006bits.v
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2 changes: 1 addition & 1 deletion ...regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
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Expand Up @@ -16,7 +16,7 @@ k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 14.53 vpr 69.19 MiB -1 -1
k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 890.77 vpr 524.05 MiB -1 -1 78.18 357960 123 95.78 -1 -1 82924 -1 119388 1274 114 45 8 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 536628 114 102 21994 21904 1 11815 1543 50 50 2500 memory auto 156.8 MiB 392.30 160275 990775 347540 619346 23889 524.1 MiB 26.07 0.22 80.1549 -53164.4 -80.1549 80.1549 33.32 0.0423342 0.0355298 5.37863 4.33825 -1 -1 -1 -1 98 232320 21 1.47946e+08 9.64913e+07 1.74237e+07 6969.48 163.73 20.4838 17.0687 371232 3885440 -1 210203 21 37478 147018 9204142 1693783 80.8722 80.8722 -65514.2 -80.8722 -15.0342 -0.291039 2.19566e+07 8782.65 10.29 6.74 4.49 -1 -1 10.29 3.94346 3.51065 0.09047 0.4148 0.01154 0.5737
k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.40 vpr 66.00 MiB -1 -1 0.37 22200 3 0.10 -1 -1 37136 -1 55296 68 99 1 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 67580 99 130 344 474 1 224 298 12 12 144 clb auto 26.8 MiB 0.18 613 74923 25398 37402 12123 66.0 MiB 0.19 0.00 1.839 -119.464 -1.839 1.839 0.39 0.000514572 0.000455927 0.0437043 0.0387858 -1 -1 -1 -1 50 1260 9 5.66058e+06 4.21279e+06 440062. 3055.98 0.94 0.161352 0.14609 14436 87570 -1 1179 7 283 438 20001 6155 1.98899 1.98899 -130.914 -1.98899 -1.29567 -0.29768 564899. 3922.91 0.20 0.03 0.09 -1 -1 0.20 0.0195384 0.0184717 0.01164 0.2329 0.07048 0.6967
k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 14.66 vpr 69.21 MiB -1 -1 0.59 26916 15 0.55 -1 -1 37584 -1 56744 36 162 0 5 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 70868 162 96 1009 950 1 712 299 16 16 256 mult_36 auto 29.9 MiB 1.53 5534 82217 25497 50567 6153 69.2 MiB 0.49 0.01 20.7544 -1578.81 -20.7544 20.7544 0.76 0.00142384 0.00124845 0.151419 0.134241 -1 -1 -1 -1 46 13744 47 1.21132e+07 3.92018e+06 791147. 3090.42 5.85 0.608129 0.548534 26792 163197 -1 10259 16 3195 6538 948445 234905 22.2459 22.2459 -1811.67 -22.2459 0 0 1.01637e+06 3970.19 0.34 0.25 0.20 -1 -1 0.34 0.0873672 0.0816501 0.008381 0.3414 0.01568 0.6429
k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common -1 -1 -1 -1 -1 -1 80.88 358140 123 101.54 -1 -1 82396 -1 119068 1175 114 45 8 -1 v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 -1 -1 -1 114 102 21994 21904 1 10942 1444 50 50 2500 memory auto 158.5 MiB 362.92 148069 866192 300137 545963 20092 542.5 MiB 21.96 0.19 78.5025 -50951.2 -78.5025 78.5025 33.51 0.0404284 0.0340368 4.97524 4.01711 -1 -1 -1 -1 -1 -1 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 993.48 vpr 547.13 MiB -1 -1 83.24 334060 123 63.57 -1 -1 78812 -1 117364 1175 114 45 8 success f4f46d5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-18T19:47:15 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 560264 114 102 21994 21904 1 10942 1444 50 50 2500 memory auto 157.6 MiB 250.68 156087 882508 304445 556112 21951 547.1 MiB 24.41 0.21 78.6961 -51503 -78.6961 78.6961 25.37 0.0616413 0.0539201 7.31609 6.16636 -1 -1 -1 -1 94 238082 31 1.47946e+08 9.11556e+07 1.68500e+07 6739.98 460.08 33.4776 27.6421 363732 3705320 -1 206225 20 37261 151174 10004867 1942001 79.656 79.656 -66948.2 -79.656 -8.35135 -0.293253 2.11127e+07 8445.07 7.76 6.76 3.24 -1 -1 7.76 3.71522 3.20453 0.09072 0.3979 0.01164 0.5905
k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.17 vpr 65.53 MiB -1 -1 0.39 21940 3 0.11 -1 -1 37088 -1 55036 68 99 1 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 67100 99 130 344 474 1 226 298 12 12 144 clb auto 26.3 MiB 0.18 538 74923 23743 38186 12994 65.5 MiB 0.18 0.00 1.85836 -118.859 -1.85836 1.85836 0.36 0.000503885 0.000445889 0.0407703 0.0361818 -1 -1 -1 -1 48 1119 10 5.66058e+06 4.21279e+06 394078. 2736.65 0.83 0.162516 0.147335 13382 75762 -1 1111 9 407 640 31098 9571 1.90517 1.90517 -133.268 -1.90517 -1.14837 -0.298787 503207. 3494.49 0.15 0.03 0.08 -1 -1 0.15 0.0185307 0.0174172 0.01058 0.2539 0.08162 0.6644
k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 16.59 vpr 68.81 MiB -1 -1 0.62 27080 15 0.54 -1 -1 37336 -1 56880 37 162 0 5 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 70460 162 96 1009 950 1 705 300 16 16 256 mult_36 auto 29.7 MiB 1.15 5400 93579 30951 55136 7492 68.8 MiB 0.67 0.01 21.0211 -1608.2 -21.0211 21.0211 0.83 0.00218529 0.00196052 0.210179 0.186327 -1 -1 -1 -1 52 13668 48 1.21132e+07 3.97408e+06 805949. 3148.24 7.94 0.777988 0.700423 25992 162577 -1 10366 18 3716 7645 1206424 330743 21.9034 21.9034 -1762.54 -21.9034 0 0 1.06067e+06 4143.25 0.34 0.34 0.17 -1 -1 0.34 0.101027 0.0941108 0.008025 0.369 0.01742 0.6136
k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 751.47 vpr 459.29 MiB -1 -1 76.66 357260 123 104.03 -1 -1 82768 -1 119376 1312 114 45 8 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 470316 114 102 21994 21904 1 12069 1581 50 50 2500 memory auto 157.2 MiB 214.07 157114 995829 353535 622712 19582 459.3 MiB 25.72 0.22 78.8285 -48928.8 -78.8285 78.8285 26.55 0.0460181 0.0354716 5.31863 4.22673 -1 -1 -1 -1 98 235798 29 1.47946e+08 9.85393e+07 1.60641e+07 6425.63 199.17 21.3518 17.6013 348768 3430976 -1 213424 20 45932 171043 10114133 1799018 78.271 78.271 -60696.1 -78.271 -29.5608 -0.29436 2.03677e+07 8147.07 10.37 8.63 4.34 -1 -1 10.37 4.63837 4.03562 0.08425 0.4305 0.01165 0.5578
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