Code

Openfpga#2382

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behnam-rs wants to merge 3 commits intoverilog-to-routing:openfpgaverilog-to-routing/vtr-verilog-to-routing:openfpgafrom

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Commits

Commits on Aug 31, 2023

• Making Analytical Placer Timing-driven and faster

  miladeb8

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  15345da

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• Cascade Placer: Enables using Analytical Placer as initial Placer

  miladeb8

  committed
  982ef33

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• Using VPR's default configs for Analytical Placer

  miladeb8

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  b66f415

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