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[vpr][base] remove unnecessary auto
1 parent 5f1939c commit bd62d9f

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+32
-32
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1 file changed

+32
-32
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vpr/src/base/setup_vpr.cpp

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ void SetupVPR(const t_options* options,
119119
t_vpr_setup* vpr_setup) {
120120
using argparse::Provenance;
121121

122-
auto& device_ctx = g_vpr_ctx.mutable_device();
122+
DeviceContext& device_ctx = g_vpr_ctx.mutable_device();
123123

124124
device_ctx.arch = arch;
125125

@@ -190,7 +190,7 @@ void SetupVPR(const t_options* options,
190190
device_ctx.EMPTY_PHYSICAL_TILE_TYPE = nullptr;
191191
int num_inputs = 0;
192192
int num_outputs = 0;
193-
for (auto& type : device_ctx.physical_tile_types) {
193+
for (t_physical_tile_type& type : device_ctx.physical_tile_types) {
194194
if (type.is_empty()) {
195195
VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE == nullptr);
196196
VTR_ASSERT(type.num_pins == 0);
@@ -208,7 +208,7 @@ void SetupVPR(const t_options* options,
208208

209209
device_ctx.EMPTY_LOGICAL_BLOCK_TYPE = nullptr;
210210
int max_equivalent_tiles = 0;
211-
for (const auto& type : device_ctx.logical_block_types) {
211+
for (const t_logical_block_type& type : device_ctx.logical_block_types) {
212212
if (type.is_empty()) {
213213
VTR_ASSERT(device_ctx.EMPTY_LOGICAL_BLOCK_TYPE == nullptr);
214214
VTR_ASSERT(type.pb_type == nullptr);
@@ -249,7 +249,7 @@ void SetupVPR(const t_options* options,
249249
setup_vib_inf(device_ctx.physical_tile_types, arch->switches, arch->Segments, arch->vib_infs);
250250
}
251251

252-
for (auto has_global_routing : arch->layer_global_routing) {
252+
for (bool has_global_routing : arch->layer_global_routing) {
253253
device_ctx.inter_cluster_prog_routing_resources.emplace_back(has_global_routing);
254254
}
255255

@@ -371,7 +371,7 @@ static void setup_timing(const t_options& Options, const bool TimingEnabled, t_t
371371
static void setup_switches(const t_arch& Arch,
372372
t_det_routing_arch& RoutingArch,
373373
const std::vector<t_arch_switch_inf>& arch_switches) {
374-
auto& device_ctx = g_vpr_ctx.mutable_device();
374+
DeviceContext& device_ctx = g_vpr_ctx.mutable_device();
375375

376376
int switches_to_copy = (int)arch_switches.size();
377377
int num_arch_switches = (int)arch_switches.size();
@@ -756,7 +756,7 @@ static void setup_analysis_opts(const t_options& Options, t_analysis_opts& analy
756756
}
757757

758758
static void setup_power_opts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch) {
759-
auto& device_ctx = g_vpr_ctx.mutable_device();
759+
DeviceContext& device_ctx = g_vpr_ctx.mutable_device();
760760

761761
power_opts->do_power = Options.do_power;
762762

@@ -836,20 +836,20 @@ static void find_ipin_cblock_switch_index(const t_arch& Arch, int& wire_to_arch_
836836
}
837837

838838
static void alloc_and_load_intra_cluster_resources(bool reachability_analysis) {
839-
auto& device_ctx = g_vpr_ctx.mutable_device();
839+
DeviceContext& device_ctx = g_vpr_ctx.mutable_device();
840840

841-
for (auto& physical_type : device_ctx.physical_tile_types) {
841+
for (t_physical_tile_type& physical_type : device_ctx.physical_tile_types) {
842842
set_root_pin_to_pb_pin_map(&physical_type);
843843
// Physical number of pins and classes in the clusters start from the number of pins and classes on the cluster
844844
// to avoid collision between intra-cluster pins and classes with root-level ones
845845
int physical_pin_offset = physical_type.num_pins;
846846
int physical_class_offset = (int)physical_type.class_inf.size();
847847
physical_type.primitive_class_starting_idx = physical_class_offset;
848-
for (auto& sub_tile : physical_type.sub_tiles) {
848+
for (t_sub_tile& sub_tile : physical_type.sub_tiles) {
849849
sub_tile.primitive_class_range.resize(sub_tile.capacity.total());
850850
sub_tile.intra_pin_range.resize(sub_tile.capacity.total());
851851
for (int sub_tile_inst = 0; sub_tile_inst < sub_tile.capacity.total(); sub_tile_inst++) {
852-
for (auto logic_block_ptr : sub_tile.equivalent_sites) {
852+
for (t_logical_block_type_ptr logic_block_ptr : sub_tile.equivalent_sites) {
853853
int num_classes = (int)logic_block_ptr->primitive_logical_class_inf.size();
854854
int num_pins = (int)logic_block_ptr->pin_logical_num_to_pb_pin_mapping.size();
855855
int logical_block_idx = logic_block_ptr->index;
@@ -868,13 +868,13 @@ static void alloc_and_load_intra_cluster_resources(bool reachability_analysis) {
868868
// Change the pin numbers in a class pin list from logical number to physical number
869869
std::for_each(logical_classes.begin(), logical_classes.end(),
870870
[&physical_pin_offset](t_class& l_class) {
871-
for (auto& pin : l_class.pinlist) {
871+
for (int& pin : l_class.pinlist) {
872872
pin += physical_pin_offset;
873873
}
874874
});
875875

876876
int physical_class_num = physical_class_offset;
877-
for (auto& logic_class : logical_classes) {
877+
for (t_class& logic_class : logical_classes) {
878878
auto result = physical_type.primitive_class_inf.insert(std::make_pair(physical_class_num, logic_class));
879879
add_primitive_pin_to_physical_tile(logic_class.pinlist,
880880
physical_class_num,
@@ -900,13 +900,13 @@ static void alloc_and_load_intra_cluster_resources(bool reachability_analysis) {
900900

901901
static void set_root_pin_to_pb_pin_map(t_physical_tile_type* physical_type) {
902902
for (int sub_tile_idx = 0; sub_tile_idx < (int)physical_type->sub_tiles.size(); sub_tile_idx++) {
903-
auto& sub_tile = physical_type->sub_tiles[sub_tile_idx];
903+
t_sub_tile& sub_tile = physical_type->sub_tiles[sub_tile_idx];
904904
int inst_num_pin = sub_tile.num_phy_pins / sub_tile.capacity.total();
905905
// Later in the code, I've assumed that pins of a subtile are mapped in a continuous fashion to
906906
// the tile pins - Usage case: vpr_utils.cpp:get_pb_pins
907907
VTR_ASSERT(sub_tile.sub_tile_to_tile_pin_indices[0] + sub_tile.num_phy_pins - 1 == sub_tile.sub_tile_to_tile_pin_indices[sub_tile.num_phy_pins - 1]);
908908
for (int sub_tile_pin_num = 0; sub_tile_pin_num < sub_tile.num_phy_pins; sub_tile_pin_num++) {
909-
for (auto& eq_site : sub_tile.equivalent_sites) {
909+
for (t_logical_block_type_ptr eq_site : sub_tile.equivalent_sites) {
910910
t_physical_pin sub_tile_physical_pin = t_physical_pin(sub_tile_pin_num % inst_num_pin);
911911
int physical_pin_num = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_num];
912912
auto direct_map = physical_type->tile_block_pin_directs_map.at(eq_site->index).at(sub_tile.index);
@@ -942,19 +942,19 @@ static void add_logical_pin_to_physical_tile(int physical_pin_offset,
942942
static void add_primitive_pin_to_physical_tile(const std::vector<int>& pin_list,
943943
int physical_class_num,
944944
t_physical_tile_type* physical_tile) {
945-
for (auto pin_num : pin_list) {
945+
for (int pin_num : pin_list) {
946946
physical_tile->primitive_pin_class.insert(std::make_pair(pin_num, physical_class_num));
947947
}
948948
}
949949

950950
static void add_intra_tile_switches() {
951-
auto& device_ctx = g_vpr_ctx.mutable_device();
951+
DeviceContext& device_ctx = g_vpr_ctx.mutable_device();
952952

953953
std::unordered_map<float, int> pb_edge_delays;
954954

955955
VTR_ASSERT(device_ctx.all_sw_inf.size() == device_ctx.arch_switch_inf.size());
956956

957-
for (auto& logical_block : device_ctx.logical_block_types) {
957+
for (t_logical_block_type& logical_block : device_ctx.logical_block_types) {
958958
if (logical_block.is_empty()) {
959959
continue;
960960
}
@@ -968,7 +968,7 @@ static void add_intra_tile_switches() {
968968
while (!pb_graph_node_q.empty()) {
969969
pb_graph_node = pb_graph_node_q.front();
970970
pb_graph_node_q.pop_front();
971-
auto pb_pins = get_mutable_pb_graph_node_pb_pins(pb_graph_node);
971+
std::vector<t_pb_graph_pin*> pb_pins = get_mutable_pb_graph_node_pb_pins(pb_graph_node);
972972

973973
for (t_pb_graph_pin* pb_pin : pb_pins) {
974974
for (int out_edge_idx = 0; out_edge_idx < pb_pin->num_output_edges; out_edge_idx++) {
@@ -1032,10 +1032,10 @@ static void do_reachability_analysis(t_physical_tile_type* physical_tile,
10321032
// Make sure that we are visiting each pin once.
10331033
if (insert_res.second) {
10341034
curr_pb_graph_pin->connected_sinks_ptc.insert(physical_class_num);
1035-
auto driving_pins = get_physical_pin_src_pins(physical_tile,
1035+
std::vector<int> driving_pins = get_physical_pin_src_pins(physical_tile,
10361036
logical_block,
10371037
curr_pin_physical_num);
1038-
for (auto driving_pin_physical_num : driving_pins) {
1038+
for (int driving_pin_physical_num : driving_pins) {
10391039
// Since we define reachable class as a class which is connected to a pin through a series of IPINs, only IPINs are added to the list
10401040
if (get_pin_type_from_pin_physical_num(physical_tile, driving_pin_physical_num) == e_pin_type::RECEIVER) {
10411041
pin_list.push_back(driving_pin_physical_num);
@@ -1051,7 +1051,7 @@ static void setup_vib_inf(const std::vector<t_physical_tile_type>& PhysicalTileT
10511051
const std::vector<t_segment_inf>& Segments,
10521052
std::vector<VibInf>& vib_infs) {
10531053
VTR_ASSERT(!vib_infs.empty());
1054-
for (auto& vib_inf : vib_infs) {
1054+
for (VibInf& vib_inf : vib_infs) {
10551055
for (size_t i_switch = 0; i_switch < switches.size(); i_switch++) {
10561056
if (vib_inf.get_switch_name() == switches[i_switch].name) {
10571057
vib_inf.set_switch_idx(i_switch);
@@ -1060,7 +1060,7 @@ static void setup_vib_inf(const std::vector<t_physical_tile_type>& PhysicalTileT
10601060
}
10611061

10621062
std::vector<t_seg_group> seg_groups = vib_inf.get_seg_groups();
1063-
for (auto& seg_group : seg_groups) {
1063+
for (t_seg_group& seg_group : seg_groups) {
10641064
for (int i_seg = 0; i_seg < (int)Segments.size(); i_seg++) {
10651065
if (Segments[i_seg].name == seg_group.name) {
10661066
seg_group.seg_index = i_seg;
@@ -1071,27 +1071,27 @@ static void setup_vib_inf(const std::vector<t_physical_tile_type>& PhysicalTileT
10711071
vib_inf.set_seg_groups(seg_groups);
10721072

10731073
std::vector<t_first_stage_mux_inf> first_stages = vib_inf.get_first_stages();
1074-
for (auto& first_stage : first_stages) {
1075-
auto& from_tokens = first_stage.from_tokens;
1076-
for (const auto& from_token : from_tokens) {
1074+
for (t_first_stage_mux_inf& first_stage : first_stages) {
1075+
std::vector<std::vector<std::string>>& from_tokens = first_stage.from_tokens;
1076+
for (const std::vector<std::string>& from_token : from_tokens) {
10771077
process_from_or_to_tokens(from_token, PhysicalTileTypes, Segments, first_stage.froms);
10781078
}
10791079
}
10801080
vib_inf.set_first_stages(first_stages);
10811081

1082-
auto second_stages = vib_inf.get_second_stages();
1083-
for (auto& second_stage : second_stages) {
1082+
std::vector<t_second_stage_mux_inf> second_stages = vib_inf.get_second_stages();
1083+
for (t_second_stage_mux_inf& second_stage : second_stages) {
10841084
std::vector<t_from_or_to_inf> tos;
10851085

10861086
process_from_or_to_tokens(second_stage.to_tokens, PhysicalTileTypes, Segments, tos);
1087-
for (auto& to : tos) {
1087+
for (t_from_or_to_inf& to : tos) {
10881088
VTR_ASSERT(to.from_type == e_multistage_mux_from_or_to_type::SEGMENT
10891089
|| to.from_type == e_multistage_mux_from_or_to_type::PB);
10901090
second_stage.to.push_back(to);
10911091
}
10921092

1093-
auto from_tokens = second_stage.from_tokens;
1094-
for (const auto& from_token : from_tokens) {
1093+
std::vector<std::vector<std::string>> from_tokens = second_stage.from_tokens;
1094+
for (const std::vector<std::string>& from_token : from_tokens) {
10951095
process_from_or_to_tokens(from_token, PhysicalTileTypes, Segments, second_stage.froms);
10961096
}
10971097
}
@@ -1103,7 +1103,7 @@ static void process_from_or_to_tokens(const std::vector<std::string> Tokens, con
11031103
for (int i_token = 0; i_token < (int)Tokens.size(); i_token++) {
11041104
std::string Token = Tokens[i_token];
11051105
const char* Token_char = Token.c_str();
1106-
auto token = vtr::StringToken(Token).split(".");
1106+
std::vector<std::string> token = vtr::StringToken(Token).split(".");
11071107
if (token.size() == 1) {
11081108
t_from_or_to_inf from_inf;
11091109
from_inf.type_name = token[0];
@@ -1124,7 +1124,7 @@ static void process_from_or_to_tokens(const std::vector<std::string> Tokens, con
11241124
parse_pin_name(Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name);
11251125

11261126
std::vector<int> all_sub_tile_to_tile_pin_indices;
1127-
for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) {
1127+
for (t_sub_tile& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) {
11281128
int sub_tile_capacity = sub_tile.capacity.total();
11291129

11301130
int start = 0;

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