@@ -119,7 +119,7 @@ void SetupVPR(const t_options* options,
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t_vpr_setup* vpr_setup) {
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using argparse::Provenance;
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- auto & device_ctx = g_vpr_ctx.mutable_device ();
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+ DeviceContext & device_ctx = g_vpr_ctx.mutable_device ();
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device_ctx.arch = arch;
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@@ -190,7 +190,7 @@ void SetupVPR(const t_options* options,
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device_ctx.EMPTY_PHYSICAL_TILE_TYPE = nullptr ;
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int num_inputs = 0 ;
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int num_outputs = 0 ;
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- for (auto & type : device_ctx.physical_tile_types ) {
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+ for (t_physical_tile_type & type : device_ctx.physical_tile_types ) {
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if (type.is_empty ()) {
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VTR_ASSERT (device_ctx.EMPTY_PHYSICAL_TILE_TYPE == nullptr );
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VTR_ASSERT (type.num_pins == 0 );
@@ -208,7 +208,7 @@ void SetupVPR(const t_options* options,
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device_ctx.EMPTY_LOGICAL_BLOCK_TYPE = nullptr ;
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int max_equivalent_tiles = 0 ;
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- for (const auto & type : device_ctx.logical_block_types ) {
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+ for (const t_logical_block_type & type : device_ctx.logical_block_types ) {
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if (type.is_empty ()) {
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VTR_ASSERT (device_ctx.EMPTY_LOGICAL_BLOCK_TYPE == nullptr );
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VTR_ASSERT (type.pb_type == nullptr );
@@ -249,7 +249,7 @@ void SetupVPR(const t_options* options,
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setup_vib_inf (device_ctx.physical_tile_types , arch->switches , arch->Segments , arch->vib_infs );
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}
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- for (auto has_global_routing : arch->layer_global_routing ) {
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+ for (bool has_global_routing : arch->layer_global_routing ) {
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device_ctx.inter_cluster_prog_routing_resources .emplace_back (has_global_routing);
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}
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@@ -371,7 +371,7 @@ static void setup_timing(const t_options& Options, const bool TimingEnabled, t_t
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static void setup_switches (const t_arch& Arch,
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t_det_routing_arch& RoutingArch,
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const std::vector<t_arch_switch_inf>& arch_switches) {
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- auto & device_ctx = g_vpr_ctx.mutable_device ();
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+ DeviceContext & device_ctx = g_vpr_ctx.mutable_device ();
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int switches_to_copy = (int )arch_switches.size ();
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int num_arch_switches = (int )arch_switches.size ();
@@ -756,7 +756,7 @@ static void setup_analysis_opts(const t_options& Options, t_analysis_opts& analy
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}
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static void setup_power_opts (const t_options& Options, t_power_opts* power_opts, t_arch* Arch) {
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- auto & device_ctx = g_vpr_ctx.mutable_device ();
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+ DeviceContext & device_ctx = g_vpr_ctx.mutable_device ();
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power_opts->do_power = Options.do_power ;
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@@ -836,20 +836,20 @@ static void find_ipin_cblock_switch_index(const t_arch& Arch, int& wire_to_arch_
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}
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static void alloc_and_load_intra_cluster_resources (bool reachability_analysis) {
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- auto & device_ctx = g_vpr_ctx.mutable_device ();
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+ DeviceContext & device_ctx = g_vpr_ctx.mutable_device ();
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- for (auto & physical_type : device_ctx.physical_tile_types ) {
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+ for (t_physical_tile_type & physical_type : device_ctx.physical_tile_types ) {
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set_root_pin_to_pb_pin_map (&physical_type);
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// Physical number of pins and classes in the clusters start from the number of pins and classes on the cluster
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// to avoid collision between intra-cluster pins and classes with root-level ones
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int physical_pin_offset = physical_type.num_pins ;
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int physical_class_offset = (int )physical_type.class_inf .size ();
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physical_type.primitive_class_starting_idx = physical_class_offset;
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- for (auto & sub_tile : physical_type.sub_tiles ) {
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+ for (t_sub_tile & sub_tile : physical_type.sub_tiles ) {
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sub_tile.primitive_class_range .resize (sub_tile.capacity .total ());
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sub_tile.intra_pin_range .resize (sub_tile.capacity .total ());
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for (int sub_tile_inst = 0 ; sub_tile_inst < sub_tile.capacity .total (); sub_tile_inst++) {
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- for (auto logic_block_ptr : sub_tile.equivalent_sites ) {
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+ for (t_logical_block_type_ptr logic_block_ptr : sub_tile.equivalent_sites ) {
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int num_classes = (int )logic_block_ptr->primitive_logical_class_inf .size ();
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int num_pins = (int )logic_block_ptr->pin_logical_num_to_pb_pin_mapping .size ();
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int logical_block_idx = logic_block_ptr->index ;
@@ -868,13 +868,13 @@ static void alloc_and_load_intra_cluster_resources(bool reachability_analysis) {
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// Change the pin numbers in a class pin list from logical number to physical number
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std::for_each (logical_classes.begin (), logical_classes.end (),
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[&physical_pin_offset](t_class& l_class) {
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- for (auto & pin : l_class.pinlist ) {
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+ for (int & pin : l_class.pinlist ) {
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pin += physical_pin_offset;
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}
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});
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int physical_class_num = physical_class_offset;
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- for (auto & logic_class : logical_classes) {
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+ for (t_class & logic_class : logical_classes) {
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auto result = physical_type.primitive_class_inf .insert (std::make_pair (physical_class_num, logic_class));
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add_primitive_pin_to_physical_tile (logic_class.pinlist ,
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physical_class_num,
@@ -900,13 +900,13 @@ static void alloc_and_load_intra_cluster_resources(bool reachability_analysis) {
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static void set_root_pin_to_pb_pin_map (t_physical_tile_type* physical_type) {
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for (int sub_tile_idx = 0 ; sub_tile_idx < (int )physical_type->sub_tiles .size (); sub_tile_idx++) {
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- auto & sub_tile = physical_type->sub_tiles [sub_tile_idx];
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+ t_sub_tile & sub_tile = physical_type->sub_tiles [sub_tile_idx];
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int inst_num_pin = sub_tile.num_phy_pins / sub_tile.capacity .total ();
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// Later in the code, I've assumed that pins of a subtile are mapped in a continuous fashion to
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// the tile pins - Usage case: vpr_utils.cpp:get_pb_pins
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VTR_ASSERT (sub_tile.sub_tile_to_tile_pin_indices [0 ] + sub_tile.num_phy_pins - 1 == sub_tile.sub_tile_to_tile_pin_indices [sub_tile.num_phy_pins - 1 ]);
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for (int sub_tile_pin_num = 0 ; sub_tile_pin_num < sub_tile.num_phy_pins ; sub_tile_pin_num++) {
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- for (auto & eq_site : sub_tile.equivalent_sites ) {
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+ for (t_logical_block_type_ptr eq_site : sub_tile.equivalent_sites ) {
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t_physical_pin sub_tile_physical_pin = t_physical_pin (sub_tile_pin_num % inst_num_pin);
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int physical_pin_num = sub_tile.sub_tile_to_tile_pin_indices [sub_tile_pin_num];
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auto direct_map = physical_type->tile_block_pin_directs_map .at (eq_site->index ).at (sub_tile.index );
@@ -942,19 +942,19 @@ static void add_logical_pin_to_physical_tile(int physical_pin_offset,
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static void add_primitive_pin_to_physical_tile (const std::vector<int >& pin_list,
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int physical_class_num,
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t_physical_tile_type* physical_tile) {
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- for (auto pin_num : pin_list) {
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+ for (int pin_num : pin_list) {
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physical_tile->primitive_pin_class .insert (std::make_pair (pin_num, physical_class_num));
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}
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}
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static void add_intra_tile_switches () {
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- auto & device_ctx = g_vpr_ctx.mutable_device ();
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+ DeviceContext & device_ctx = g_vpr_ctx.mutable_device ();
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std::unordered_map<float , int > pb_edge_delays;
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VTR_ASSERT (device_ctx.all_sw_inf .size () == device_ctx.arch_switch_inf .size ());
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- for (auto & logical_block : device_ctx.logical_block_types ) {
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+ for (t_logical_block_type & logical_block : device_ctx.logical_block_types ) {
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if (logical_block.is_empty ()) {
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continue ;
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}
@@ -968,7 +968,7 @@ static void add_intra_tile_switches() {
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while (!pb_graph_node_q.empty ()) {
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pb_graph_node = pb_graph_node_q.front ();
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pb_graph_node_q.pop_front ();
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- auto pb_pins = get_mutable_pb_graph_node_pb_pins (pb_graph_node);
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+ std::vector<t_pb_graph_pin*> pb_pins = get_mutable_pb_graph_node_pb_pins (pb_graph_node);
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for (t_pb_graph_pin* pb_pin : pb_pins) {
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for (int out_edge_idx = 0 ; out_edge_idx < pb_pin->num_output_edges ; out_edge_idx++) {
@@ -1032,10 +1032,10 @@ static void do_reachability_analysis(t_physical_tile_type* physical_tile,
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// Make sure that we are visiting each pin once.
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if (insert_res.second ) {
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curr_pb_graph_pin->connected_sinks_ptc .insert (physical_class_num);
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- auto driving_pins = get_physical_pin_src_pins (physical_tile,
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+ std::vector< int > driving_pins = get_physical_pin_src_pins (physical_tile,
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logical_block,
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curr_pin_physical_num);
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- for (auto driving_pin_physical_num : driving_pins) {
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+ for (int driving_pin_physical_num : driving_pins) {
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// Since we define reachable class as a class which is connected to a pin through a series of IPINs, only IPINs are added to the list
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if (get_pin_type_from_pin_physical_num (physical_tile, driving_pin_physical_num) == e_pin_type::RECEIVER) {
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pin_list.push_back (driving_pin_physical_num);
@@ -1051,7 +1051,7 @@ static void setup_vib_inf(const std::vector<t_physical_tile_type>& PhysicalTileT
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const std::vector<t_segment_inf>& Segments,
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std::vector<VibInf>& vib_infs) {
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VTR_ASSERT (!vib_infs.empty ());
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- for (auto & vib_inf : vib_infs) {
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+ for (VibInf & vib_inf : vib_infs) {
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for (size_t i_switch = 0 ; i_switch < switches.size (); i_switch++) {
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if (vib_inf.get_switch_name () == switches[i_switch].name ) {
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vib_inf.set_switch_idx (i_switch);
@@ -1060,7 +1060,7 @@ static void setup_vib_inf(const std::vector<t_physical_tile_type>& PhysicalTileT
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}
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std::vector<t_seg_group> seg_groups = vib_inf.get_seg_groups ();
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- for (auto & seg_group : seg_groups) {
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+ for (t_seg_group & seg_group : seg_groups) {
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for (int i_seg = 0 ; i_seg < (int )Segments.size (); i_seg++) {
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if (Segments[i_seg].name == seg_group.name ) {
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seg_group.seg_index = i_seg;
@@ -1071,27 +1071,27 @@ static void setup_vib_inf(const std::vector<t_physical_tile_type>& PhysicalTileT
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vib_inf.set_seg_groups (seg_groups);
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std::vector<t_first_stage_mux_inf> first_stages = vib_inf.get_first_stages ();
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- for (auto & first_stage : first_stages) {
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- auto & from_tokens = first_stage.from_tokens ;
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- for (const auto & from_token : from_tokens) {
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+ for (t_first_stage_mux_inf & first_stage : first_stages) {
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+ std::vector<std::vector<std::string>> & from_tokens = first_stage.from_tokens ;
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+ for (const std::vector<std::string> & from_token : from_tokens) {
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process_from_or_to_tokens (from_token, PhysicalTileTypes, Segments, first_stage.froms );
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}
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}
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vib_inf.set_first_stages (first_stages);
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- auto second_stages = vib_inf.get_second_stages ();
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- for (auto & second_stage : second_stages) {
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+ std::vector<t_second_stage_mux_inf> second_stages = vib_inf.get_second_stages ();
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+ for (t_second_stage_mux_inf & second_stage : second_stages) {
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std::vector<t_from_or_to_inf> tos;
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process_from_or_to_tokens (second_stage.to_tokens , PhysicalTileTypes, Segments, tos);
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- for (auto & to : tos) {
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+ for (t_from_or_to_inf & to : tos) {
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VTR_ASSERT (to.from_type == e_multistage_mux_from_or_to_type::SEGMENT
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|| to.from_type == e_multistage_mux_from_or_to_type::PB);
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second_stage.to .push_back (to);
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}
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- auto from_tokens = second_stage.from_tokens ;
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- for (const auto & from_token : from_tokens) {
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+ std::vector<std::vector<std::string>> from_tokens = second_stage.from_tokens ;
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+ for (const std::vector<std::string> & from_token : from_tokens) {
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process_from_or_to_tokens (from_token, PhysicalTileTypes, Segments, second_stage.froms );
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}
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}
@@ -1103,7 +1103,7 @@ static void process_from_or_to_tokens(const std::vector<std::string> Tokens, con
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for (int i_token = 0 ; i_token < (int )Tokens.size (); i_token++) {
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std::string Token = Tokens[i_token];
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const char * Token_char = Token.c_str ();
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- auto token = vtr::StringToken (Token).split (" ." );
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+ std::vector<std::string> token = vtr::StringToken (Token).split (" ." );
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if (token.size () == 1 ) {
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t_from_or_to_inf from_inf;
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from_inf.type_name = token[0 ];
@@ -1124,7 +1124,7 @@ static void process_from_or_to_tokens(const std::vector<std::string> Tokens, con
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parse_pin_name (Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name);
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std::vector<int > all_sub_tile_to_tile_pin_indices;
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- for (auto & sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles ) {
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+ for (t_sub_tile & sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles ) {
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int sub_tile_capacity = sub_tile.capacity .total ();
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int start = 0 ;
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