[vpr][utils] move StringToken under vtr util

Author: amin1377

libs/libarchfpga/src/arch_check.cpp

@@ -168,9 +168,9 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
 
                 //Annotations always put the pin in the input_pins field
                 VTR_ASSERT(annotation.input_pins);
-                for (const std::string& input_pin : vtr::split(annotation.input_pins)) {
+                for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
                     InstPort annot_port(input_pin);
-                    for (const std::string& clock : vtr::split(annotation.clock)) {
+                    for (const std::string& clock : vtr::StringToken(annotation.clock).split(" \t\n")) {
                         InstPort annot_clock(clock);
 
                         //Find the model port
@@ -210,9 +210,9 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
             } else if (annotation.input_pins && annotation.output_pins) {
                 //Combinational annotation
                 VTR_ASSERT_MSG(!annotation.clock, "Combinational annotations should have no clock");
-                for (const std::string& input_pin : vtr::split(annotation.input_pins)) {
+                for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
                     InstPort annot_in(input_pin);
-                    for (const std::string& output_pin : vtr::split(annotation.output_pins)) {
+                    for (const std::string& output_pin : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
                         InstPort annot_out(output_pin);
 
                         //Find the input model port

libs/libarchfpga/src/arch_util.cpp

@@ -39,7 +39,7 @@ const char* get_arch_file_name() {
 }
 
 InstPort::InstPort(const std::string& str) {
-    std::vector<std::string> inst_port = vtr::split(str, ".");
+    std::vector<std::string> inst_port = vtr::StringToken(str).split(".");
 
     if (inst_port.size() == 1) {
         instance_ = name_index();
@@ -701,9 +701,8 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
 
     mem_pb_type->modes[0].num_interconnect = mem_pb_type->num_ports * num_pb;
 
-    std::stringstream ss;
-    ss << "Memory pb_type " << mem_pb_type->name << " has no interconnect";
-    VTR_ASSERT_MSG(mem_pb_type->modes[0].num_interconnect > 0, ss.str().c_str());
+    std::string error_msg = (std::stringstream() << "Memory pb_type " << mem_pb_type->name << " has no interconnect").str();
+    VTR_ASSERT_MSG(mem_pb_type->modes[0].num_interconnect > 0, error_msg.c_str());
     mem_pb_type->modes[0].interconnect = new t_interconnect[mem_pb_type->modes[0].num_interconnect];
 
     for (i = 0; i < mem_pb_type->modes[0].num_interconnect; i++) {
@@ -1052,9 +1051,9 @@ bool has_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* po
 
 bool has_combinational_annotation(const t_pb_type* pb_type, std::string_view in_port, std::string_view out_port) {
     for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
-        for (const auto& annot_in_str : vtr::split(annotation.input_pins)) {
+        for (const auto& annot_in_str : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
             InstPort in_pins(annot_in_str);
-            for (const auto& annot_out_str : vtr::split(annotation.output_pins)) {
+            for (const auto& annot_out_str : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
                 InstPort out_pins(annot_out_str);
                 if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
                     for (const auto& [key, val] : annotation.annotation_entries) {

libs/libarchfpga/src/parse_switchblocks.cpp

@@ -201,7 +201,7 @@ t_wire_switchpoints parse_wireconn_from_to_node(pugi::xml_node node, const pugiu
     wire_switchpoints.segment_name = get_attribute(node, "type", loc_data).value();
 
     auto points_str = get_attribute(node, "switchpoint", loc_data).value();
-    for (const auto& point_str : vtr::split(points_str, ",")) {
+    for (const auto& point_str : vtr::StringToken(points_str).split(",")) {
         int switchpoint = vtr::atoi(point_str);
         wire_switchpoints.switchpoints.push_back(switchpoint);
     }
@@ -229,7 +229,7 @@ static void parse_switchpoint_order(const char* order, SwitchPointOrder& switchp
 /* parses the wire types specified in the comma-separated 'ch' char array into the vector wire_points_vec.
  * Spaces are trimmed off */
 static void parse_comma_separated_wire_types(const char* ch, std::vector<t_wire_switchpoints>& wire_switchpoints) {
-    auto types = vtr::split(ch, ",");
+    auto types = vtr::StringToken(ch).split(",");
 
     if (types.empty()) {
         archfpga_throw(__FILE__, __LINE__, "parse_comma_separated_wire_types: found empty wireconn wire type entry\n");
@@ -245,7 +245,7 @@ static void parse_comma_separated_wire_types(const char* ch, std::vector<t_wire_
 
 /* parses the wirepoints specified in the comma-separated 'ch' char array into the vector wire_points_vec */
 static void parse_comma_separated_wire_points(const char* ch, std::vector<t_wire_switchpoints>& wire_switchpoints) {
-    auto points = vtr::split(ch, ",");
+    auto points = vtr::StringToken(ch).split(",");
     if (points.empty()) {
         archfpga_throw(__FILE__, __LINE__, "parse_comma_separated_wire_points: found empty wireconn wire point entry\n");
     }

libs/libarchfpga/src/physical_types.h

@@ -2374,19 +2374,20 @@ struct t_arch {
     std::vector<t_lut_cell> lut_cells;
     std::unordered_map<std::string, std::vector<t_lut_element>> lut_elements;
 
-    //The name of the switch used for the input connection block (i.e. to
-    //connect routing tracks to block pins). tracks can be connected to
+    // The name of the switch used for the input connection block (i.e. to
+    // connect routing tracks to block pins). tracks can be connected to
     // ipins through the same die or from other dice, each of these
-    //types of connections requires a different switch, all names should correspond to a switch in Switches.
+    // types of connections requires a different switch, all names should correspond to a switch in Switches.
     std::vector<std::string> ipin_cblock_switch_name;
 
     std::vector<t_grid_def> grid_layouts; //Set of potential device layouts
 
-    //the layout that is chosen to be used with command line options
-    //It is used to generate custom SB for a specific locations within the device
-    //If the layout is not specified in the command line options, this variable will be set to "auto"
+    // the layout that is chosen to be used with command line options
+    // It is used to generate custom SB for a specific locations within the device
+    // If the layout is not specified in the command line options, this variable will be set to "auto"
     std::string device_layout;
 
+    /// VIB grid layouts
     std::vector<t_vib_grid_def> vib_grid_layouts;
 
     t_clock_arch_spec clock_arch; // Clock related data types

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -1845,14 +1845,14 @@ struct ArchReader {
         auto site_pins = site.getBelPins();
 
         std::string endpoint = direction == BACKWARD ? ic->input_string : ic->output_string;
-        auto ic_endpoints = vtr::split(endpoint, " ");
+        auto ic_endpoints = vtr::StringToken(endpoint).split(" ");
 
         std::unordered_map<t_interconnect*, std::set<std::string>> pps_map;
 
         bool is_backward = direction == BACKWARD;
 
         for (auto ep : ic_endpoints) {
-            auto parts = vtr::split(ep, ".");
+            auto parts = vtr::StringToken(ep).split(".");
             auto bel = parts[0];
             auto pin = parts[1];
 
@@ -1889,7 +1889,7 @@ struct ArchReader {
                         std::string ic_to_find = bel + "." + pin_name;
 
                         bool found = false;
-                        for (auto out : vtr::split(is_backward ? other_ic->output_string : other_ic->input_string, " "))
+                        for (auto out : vtr::StringToken(is_backward ? other_ic->output_string : other_ic->input_string).split(" "))
                             found |= out == ic_to_find;
 
                         if (found) {
@@ -1911,7 +1911,7 @@ struct ArchReader {
                         t_interconnect* other_ic = &mode->interconnect[iic];
 
                         bool found = false;
-                        for (auto other_ep : vtr::split(is_backward ? other_ic->output_string : other_ic->input_string, " ")) {
+                        for (auto other_ep : vtr::StringToken(is_backward ? other_ic->output_string : other_ic->input_string).split(" ")) {
                             found |= other_ep == ep;
                         }
 

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -2531,7 +2531,7 @@ static void process_model_ports(pugi::xml_node port_group, t_model& model, std::
                 model_port->clock = std::string(attr.value());
 
             } else if (attr.name() == std::string("combinational_sink_ports")) {
-                model_port->combinational_sink_ports = vtr::split(attr.value());
+                model_port->combinational_sink_ports = vtr::StringToken(attr.value()).split(" \t\n");
 
             } else {
                 bad_attribute(attr, port, loc_data);
@@ -3579,7 +3579,7 @@ static void process_pin_locations(pugi::xml_node Locations,
             seen_sides.insert(side_offset);
 
             /* Go through lists of pins */
-            const std::vector<std::string> Tokens = vtr::split(Cur.child_value());
+            const std::vector<std::string> Tokens = vtr::StringToken(Cur.child_value()).split(" \t\n");
             int Count = (int)Tokens.size();
             if (Count > 0) {
                 for (int pin = 0; pin < Count; ++pin) {
@@ -5257,7 +5257,7 @@ static void process_first_stage(pugi::xml_node Stage_node, std::vector<t_physica
         pugi::xml_node SubElem = get_first_child(Node, "from", loc_data);
         int from_num = count_children(Node, "from", loc_data);
         for (int i_from = 0; i_from < from_num; i_from++) {
-            std::vector<std::string> from_tokens = vtr::split(SubElem.child_value());
+            std::vector<std::string> from_tokens = vtr::StringToken(SubElem.child_value()).split(" \t\n");
             first_stage_mux.from_tokens.push_back(from_tokens);
             SubElem = SubElem.next_sibling(SubElem.name());
         }
@@ -5281,14 +5281,14 @@ static void process_second_stage(pugi::xml_node Stage_node, std::vector<t_physic
         pugi::xml_node SubElem = get_first_child(Node, "to", loc_data);
         int to_num = count_children(Node, "to", loc_data);
         VTR_ASSERT(to_num == 1);
-        std::vector<std::string> to_tokens = vtr::split(SubElem.child_value());
+        std::vector<std::string> to_tokens = vtr::StringToken(SubElem.child_value()).split(" \t\n");
         VTR_ASSERT(to_tokens.size() == 1);
         second_stage_mux.to_tokens = to_tokens;
 
         SubElem = get_first_child(Node, "from", loc_data);
         int from_num = count_children(Node, "from", loc_data);
         for (int i_from = 0; i_from < from_num; i_from++) {
-            std::vector<std::string> from_tokens = vtr::split(SubElem.child_value());
+            std::vector<std::string> from_tokens = vtr::StringToken(SubElem.child_value()).split(" \t\n");
             second_stage_mux.from_tokens.push_back(from_tokens);
             SubElem = SubElem.next_sibling(SubElem.name());
         }

libs/librrgraph/src/base/get_parallel_segs.cpp

@@ -3,13 +3,13 @@
 std::vector<t_segment_inf> get_parallel_segs(const std::vector<t_segment_inf>& segment_inf,
                                              t_unified_to_parallel_seg_index& seg_index_map,
                                              enum e_parallel_axis parallel_axis,
-                                             bool keep_original_index) {
+                                             bool keep_original_index /* = false */) {
     std::vector<t_segment_inf> result;
     for (size_t i = 0; i < segment_inf.size(); ++i) {
         if (segment_inf[i].parallel_axis == parallel_axis || segment_inf[i].parallel_axis == BOTH_AXIS) {
             result.push_back(segment_inf[i]);
             if (!keep_original_index) {
-                result[result.size() - 1].seg_index = i;
+                result.back().seg_index = i;
             }
             seg_index_map.insert(std::make_pair(i, std::make_pair(result.size() - 1, parallel_axis)));
         }

libs/librrgraph/src/base/get_parallel_segs.h

@@ -14,7 +14,7 @@
  * @param seg_index_map  Map from unified to axis-specific segment indices.
  * @param parallel_axis  Axis to filter segments by.
  * @param keep_original_index  Whether to keep the original index of the segment. Currently,
- * it is only set to true when building the tileable rr_graph.
+ *                             it is only set to true when building the tileable rr_graph.
  * @return Filtered list of segments for the given axis.
  */
 std::vector<t_segment_inf> get_parallel_segs(const std::vector<t_segment_inf>& segment_inf,

libs/librrgraph/src/base/rr_graph_builder.cpp

@@ -2,7 +2,7 @@
 #include "vtr_log.h"
 #include "rr_graph_builder.h"
 #include "vtr_time.h"
-#include "vtr_tokenizer.h"
+#include "vtr_util.h"
 #include <queue>
 #include <random>
 

libs/librrgraph/src/base/rr_graph_view.cpp

@@ -62,7 +62,7 @@ std::vector<RREdgeId> RRGraphView::node_non_configurable_in_edges(RRNodeId node)
     return ret_edges;
 }
 
-std::vector<RREdgeId> RRGraphView::find_edges(const RRNodeId& src_node, const RRNodeId& des_node) const {
+std::vector<RREdgeId> RRGraphView::find_edges(RRNodeId src_node, RRNodeId des_node) const {
     std::vector<RREdgeId> edge_list;
     for (auto iedge : node_out_edges(src_node)) {
         if (edge_sink_node(RREdgeId(iedge)) == des_node) {