[H7] Update the system source file

Base on system_stm32h7xx_singlecore.c

Signed-off-by: Frederic Pillon <[email protected]>

Author: fpistm

system/STM32H7xx/system_stm32h7xx.c

@@ -48,6 +48,7 @@
   */
 
 #include "stm32h7xx.h"
+#include <math.h>
 
 #if !defined  (HSE_VALUE)
 #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
@@ -79,11 +80,14 @@
   */
 
 /************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM  */
+/* #define DATA_IN_D2_SRAM */
+
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
 /* #define VECT_TAB_SRAM */
 #ifndef VECT_TAB_OFFSET
-#define VECT_TAB_OFFSET  0x00       /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
                                       This value must be a multiple of 0x200. */
 #endif
 /******************************************************************************/
@@ -140,9 +144,13 @@
   */
 void SystemInit (void)
 {
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
   /* FPU settings ------------------------------------------------------------*/
   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
   #endif
   /* Reset the RCC clock configuration to the default reset state ------------*/
   /* Set HSION bit */
@@ -152,7 +160,7 @@ void SystemInit (void)
   RCC->CFGR = 0x00000000;
 
   /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEAF6ED7F;
+  RCC->CR &= 0xEAF6ED7FU;
 
   /* Reset D1CFGR register */
   RCC->D1CFGR = 0x00000000;
@@ -186,15 +194,24 @@ void SystemInit (void)
   RCC->PLL3FRACR = 0x00000000;
 
   /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
+  RCC->CR &= 0xFFFBFFFFU;
 
   /* Disable all interrupts */
   RCC->CIER = 0x00000000;
 
+  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+  {
+    /* if stm32h7 revY*/
+    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+    *((__IO uint32_t*)0x51008108) = 0x000000001U;
+  }
 
-  /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
-  *((__IO uint32_t*)0x51008108) = 0x000000001;
-
+#if defined (DATA_IN_D2_SRAM)
+  /* in case of initialized data in D2 SRAM , enable the D2 SRAM clock */
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+  tmpreg = RCC->AHB2ENR;
+  (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
 
   /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
@@ -245,70 +262,80 @@ void SystemInit (void)
   */
 void SystemCoreClockUpdate (void)
 {
-uint32_t pllp = 2, pllsource = 0, pllm = 2 ,tmp, pllfracen  =0 , hsivalue = 0;
-float fracn1, pllvco = 0 ;
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  float_t fracn1, pllvco;
 
   /* Get SYSCLK source -------------------------------------------------------*/
 
   switch (RCC->CFGR & RCC_CFGR_SWS)
   {
-  case 0x00:  /* HSI used as system clock source */
-
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
    SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
-
     break;
 
-  case 0x08:  /* CSI used as system clock  source */
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
     SystemCoreClock = CSI_VALUE;
     break;
 
-  case 0x10:  /* HSE used as system clock  source */
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
     SystemCoreClock = HSE_VALUE;
     break;
 
-  case 0x18:  /* PLL1 used as system clock  source */
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
 
     /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
     SYSCLK = PLL_VCO / PLLR
     */
     pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
     pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
-    pllfracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
-    fracn1 = (pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
     switch (pllsource)
     {
+        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
 
-    case 0x00:  /* HSI used as PLL clock source */
       hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
-      pllvco = (hsivalue/ pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
+        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
       break;
 
-    case 0x01:  /* CSI used as PLL clock source */
-      pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
+        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
       break;
 
-    case 0x02:  /* HSE used as PLL clock source */
-      pllvco = (HSE_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
+        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
+          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
       break;
 
     default:
-      pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
       break;
     }
-    pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 ) ;
-    SystemCoreClock = (uint32_t) (pllvco/pllp);
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      SystemCoreClock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      SystemCoreClock = 0U;
+    }
     break;
 
   default:
     SystemCoreClock = CSI_VALUE;
     break;
   }
 
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
-  /* HCLK frequency */
+  /* Compute SystemClock frequency --------------------------------------------------*/
+  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+  /* SystemCoreClock frequency : CM7 CPU frequency  */
   SystemCoreClock >>= tmp;
+
+  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
+  SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 }
 
 /**