VLSI Design Project: Huffman to table Asymmetric Numeral System Re-Encoder

## Overview

These are the source files and reports for the ASIC hardware implementation of a Huffman to table Asymmetric Numeral System Re-Encoder.
The Re-Encoder is a minimal proof on concept considering three abritrary symbols {A, B, C} with known probabilties.

## Dependecies

Modelsim 10.5b (local)
Synopsys Design Compiler (server based)
Cadence Innovus (server based)

Note: Verdi can and has been used to verify both pre and post synth files however info on system functions for Verdi was not found.
In Modelsim I have access to system functions for getting sizes, file control, and run control which is neccesary for any level of automation.
Thus the test_bench files are meant for ModelSim as they call several system functions.

## Basic Usage

1) Run Re-Encoder_Verification.py and get the reverse encoding and size.
2) Open either the rtl or post_synth files in ModelSim
3) In the test bench (_tb) file replace  reversed_huffman_data with you values and adjust sizes EX: [size-1:0] ... size'b...
4) Compile the files (typically to the work dir)
5) Simulate the compiled test bench
6) Press the Run -All button or use the "run -all" command
7) Locate the new output.txt file (See Note0)
8) Replace the old output.txt file with new one
9) Continue the Re-Encoder_Verification.py program and check results :thumbs-up:

## Files and Directories

## rtl
  
  * HF_tANS_recoder.sv -- This is a system verilog module that performs tANS on an input stream and generates output data for parsing.
  The entire encoding process was condensed to this module and for the minimal case considered is not that long but code isnt a product its a liability.

  *  HF_tANS_recoder_tb.sv -- This is the testbench used for generating output files for either the rtl or post_synth modules.
  It will iterate through the data specified by reversed_huffman_data and write outputs to a file "output.txt".
  
  Note0: ModelSim pathing is strange and instead of "./output.txt" being the current directory it is relative to a root.
  This root is likely an enviroment variable specified back when I was using Modelsim for actual FPGA work with Altera Quartus.
  I do not want to mess with these enviroment variables and could not find anything way to change this within ModelSim settings.

## post_synth
  
  * HF_tANS_recoder.sv -- Netlist result of synthesis of rtl HF_tANS_recoder.sv with a timescale

  * HF_tANS_recoder_tb.sv -- Same as rtl HF_tANS_recoder_tb.sv

  * slow_vdd1v0_basicCells.sv -- System verilog version of cell library so we can compile the netlist result of synthesis
  
## synth
  
  * setup_synth_HF.tcl -- Setup script based on lab4 setup_synth.tcl, reads module, sets cell library and reports directory

  * constraints_synth.tcl -- Constraints script based on lab4 constraints_synth.tcl, sets timing and area constraints

  * reporting_synth.tcl -- Reports script based on lab4 reporting_synth.tcl, writes timing, area and power reports.
  Writes netlist.v file which contains netlist version of module used to make ## post_synth * HF_tANS_recoder.sv

  Note1: This is not directly usable even if we match the file names and paths because the slow_vdd1v0_basicCells.sv has timescales.

  * run_synth.tcl -- Calls other tcl files and compile command to automate entire synthesis.

  * gpdk045_fast.db / gpdk045_slow.db -- Cell libraries for synthesis, currently design uses slow as specified in setup_synth_HF.tcl.

  ## rpt -- contains reports and netlist generated by synthesis specified by reporting_synth.tcl

## pnr

  * netlist.v -- Netlist module generated by synthesis.

  * setup_pnr.tcl -- Setup script based on lab4 setup_pnr.tcl, reads module, sets up power and ground rails, process node, and reports directory.

  * mmmc.tcl -- Script for setting up libraries and constraints. Direct copy from lab4 mmmc.tcl.

  * pnr.tcl -- Script for setting up layout. Direct copy on lab4 pnr.tcl.

  * reporting_pnr.tcl -- Reports script based on lab4 reporting_pnr.tcl, writes timing, drc, power and route reports.

  * run_pnr.tcl -- Calls other tcl files and init_design command to automate entire layout.

  ## rpt -- contains reports generated by layout specified by reporting_pnr.tcl

* Re-Encoder_POC.py --  This is a python file that was the original proof of concept for the idea.
It was originally written with synthesizable system verilog in mind so avoiding constructs such as while loops, dictionaries etc...
It has since been updated to simply act as a way of testing comphression improvements on user or randomly generated data.

* Re-Encoder_Verification.py -- This is a python script for generating data from user input to be passed into the testbench and validating testbench outputs.
It will parse "output.txt" to get the enoding generated from the testbench and compare it to an expected encoded.
If the the encodings and final states match it is a succes otherwise it will notify of a mismatch.

* output.txt -- This is the output file the rtl test_bench will generate, remember that the location of new output.txt files is not entirely known.