Add bitmask for Q

[el-ev]

Q is the standard extension for Quad-precision floating point.
llvm/llvm-project#139369 is going to add assembly support for the Q extension.

https://github.com/riscv/riscv-isa-manual/blob/main/src/machine.adoc

[topperc]

binutils already has assembler support. Why does LLVM adding it require a new feature bit if binutils didn't?

[el-ev]

binutils already has assembler support. Why does LLVM adding it require a new feature bit if binutils didn't?

The Q extension is a ratified standard extension and is assigned to the 17th bit. As it is getting supported by both projects I think it's a good time to add the bitmask.

[lenary]

@topperc We've stated the single letter extensions will match their bits in misa so we should just go ahead and add definitions here for all of the single letter extensions that exist. It's not clear to me why they weren't in the first place, or why we wouldn't do that anyway.

Yes not all of these are exposed through hwcaps on linux yet, and we do not have full compiler support, but surely the single-letter stuff we can proceed with?

[topperc]

LGTM