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Added Willow Cove #301

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Merged
merged 5 commits into from
Jun 10, 2025
Merged

Added Willow Cove #301

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bf719af
Added Willow Cove
rrwinterton Jun 4, 2025
5202af1
Update uarch.c
rrwinterton Jun 5, 2025
a7e060e
Update cpu-info.c
rrwinterton Jun 5, 2025
7ef5671
Update cpuinfo.h
rrwinterton Jun 5, 2025
f9f50aa
Update cpuinfo.h
rrwinterton Jun 5, 2025
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2 changes: 2 additions & 0 deletions include/cpuinfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -353,6 +353,8 @@ enum cpuinfo_uarch {
cpuinfo_uarch_palm_cove = 0x0010020B,
/** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */
cpuinfo_uarch_sunny_cove = 0x0010020C,
/** Intel Willow Cove microarchitecture (10 nm, Tiger Lake). */
cpuinfo_uarch_willow_cove = 0x0010020D,

/** Pentium 4 with Willamette, Northwood, or Foster cores. */
cpuinfo_uarch_willamette = 0x00100300,
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3 changes: 3 additions & 0 deletions src/x86/uarch.c
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Expand Up @@ -168,6 +168,9 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
case 0x7E: // Ice Lake-U
return cpuinfo_uarch_sunny_cove;

case 0x8C: // Tiger U
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note 8c = 140 is the one that sde -tgl exposes but https://en.wikichip.org/wiki/intel/cpuid confirms 141

case 0x8D: // Tiger H
return cpuinfo_uarch_willow_cove;
/* Low-power cores */
case 0x1C: // Diamondville,
// Silverthorne,
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2 changes: 2 additions & 0 deletions tools/cpu-info.c
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Expand Up @@ -80,6 +80,8 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) {
return "Palm Cove";
case cpuinfo_uarch_sunny_cove:
return "Sunny Cove";
case cpuinfo_uarch_willow_cove:
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move up 2 lines because willow cove is the successor to sunny cove (icelake)

return "Willow Cove";
case cpuinfo_uarch_willamette:
return "Willamette";
case cpuinfo_uarch_prescott:
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