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RISCV] Select NDS_BFOZ for and with trailing ones mask #141398

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RISCV] Select NDS_BFOZ for and with trailing ones mask #141398

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[RISCV] Pre-commit
tclin914 May 25, 2025
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[RISCV] Select NDS_BFOZ for and with trailing ones mask
tclin914 May 25, 2025
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5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -564,6 +564,11 @@ def XLenSubTrailingOnes : SDNodeXForm<imm, [{
def GIXLenSubTrailingOnes : GICustomOperandRenderer<"renderXLenSubTrailingOnes">,
GISDNodeXFormEquiv<XLenSubTrailingOnes>;

def TrailingOnesSubOne : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(llvm::countr_one(N->getZExtValue()) - 1,
SDLoc(N), N->getValueType(0));
}]>;

// Checks if this mask is a non-empty sequence of ones starting at the
// most/least significant bit with the remainder zero and exceeds simm32/simm12.
def LeadingOnesMask : ImmLeaf<XLenVT, [{
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3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
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Expand Up @@ -466,6 +466,9 @@ def NDS_VD4DOTSU_VV : NDSRVInstVD4DOT<0b000101, "nds.vd4dotsu">;

let Predicates = [HasVendorXAndesPerf] in {

def : Pat<(XLenVT (and GPR:$rs, TrailingOnesMask:$mask)),
(NDS_BFOZ $rs, (TrailingOnesSubOne imm:$mask), 0)>;

def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (NDS_BFOS GPR:$rs1, 15, 0)>;
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (NDS_BFOS GPR:$rs1, 7, 0)>;
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i1), (NDS_BFOS GPR:$rs1, 0, 0)>;
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20 changes: 20 additions & 0 deletions llvm/test/CodeGen/RISCV/rv32xandesperf.ll
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Expand Up @@ -2,6 +2,26 @@
; RUN: llc -O0 -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define i32 @and32_0xfff(i32 %x) {
; CHECK-LABEL: and32_0xfff:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 11, 0
; CHECK-NEXT: ret
%a = and i32 %x, 4095
ret i32 %a
}

define i64 @and64_0xfff(i64 %x) {
; CHECK-LABEL: and64_0xfff:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $x11 killed $x10
; CHECK-NEXT: nds.bfoz a0, a0, 11, 0
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: ret
%a = and i64 %x, 4095
ret i64 %a
}

define i32 @sexti1_i32(i32 %a) {
; CHECK-LABEL: sexti1_i32:
; CHECK: # %bb.0:
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18 changes: 18 additions & 0 deletions llvm/test/CodeGen/RISCV/rv64xandesperf.ll
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Expand Up @@ -2,6 +2,24 @@
; RUN: llc -mtriple=riscv64 -mattr=+xandesperf -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define i32 @and32_0xfff(i32 %x) {
; CHECK-LABEL: and32_0xfff:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 11, 0
; CHECK-NEXT: ret
%a = and i32 %x, 4095
ret i32 %a
}

define i64 @and64_0xfff(i64 %x) {
; CHECK-LABEL: and64_0xfff:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 11, 0
; CHECK-NEXT: ret
%a = and i64 %x, 4095
ret i64 %a
}

define signext i32 @sexti1_i32(i32 signext %a) {
; CHECK-LABEL: sexti1_i32:
; CHECK: # %bb.0:
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