[RISCV] Select NDS_BFOZ for and with trailing ones mask

Select NDS_BFOS for and operation with trailing ones mask. The msb
operand is calculated as the number of trailing ones minus one.

Author: tclin914

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -564,6 +564,11 @@ def XLenSubTrailingOnes : SDNodeXForm<imm, [{
 def GIXLenSubTrailingOnes : GICustomOperandRenderer<"renderXLenSubTrailingOnes">,
   GISDNodeXFormEquiv<XLenSubTrailingOnes>;
 
+def TrailingOnesSubOne : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(llvm::countr_one(N->getZExtValue()) - 1,
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
 // Checks if this mask is a non-empty sequence of ones starting at the
 // most/least significant bit with the remainder zero and exceeds simm32/simm12.
 def LeadingOnesMask : ImmLeaf<XLenVT, [{

llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td

@@ -466,6 +466,9 @@ def NDS_VD4DOTSU_VV : NDSRVInstVD4DOT<0b000101, "nds.vd4dotsu">;
 
 let Predicates = [HasVendorXAndesPerf] in {
 
+def : Pat<(XLenVT (and GPR:$rs, TrailingOnesMask:$mask)),
+          (NDS_BFOZ $rs, (TrailingOnesSubOne imm:$mask), 0)>;
+
 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (NDS_BFOS GPR:$rs1, 15, 0)>;
 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (NDS_BFOS GPR:$rs1, 7, 0)>;
 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i1), (NDS_BFOS GPR:$rs1, 0, 0)>;

llvm/test/CodeGen/RISCV/rv32xandesperf.ll

@@ -5,8 +5,7 @@
 define i32 @and32_0xfff(i32 %x) {
 ; CHECK-LABEL: and32_0xfff:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 20
-; CHECK-NEXT:    srli a0, a0, 20
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
 ; CHECK-NEXT:    ret
   %a = and i32 %x, 4095
   ret i32 %a
@@ -16,8 +15,7 @@ define i64 @and64_0xfff(i64 %x) {
 ; CHECK-LABEL: and64_0xfff:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $x11 killed $x10
-; CHECK-NEXT:    slli a0, a0, 20
-; CHECK-NEXT:    srli a0, a0, 20
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:    ret
   %a = and i64 %x, 4095

llvm/test/CodeGen/RISCV/rv64xandesperf.ll

@@ -5,8 +5,7 @@
 define i32 @and32_0xfff(i32 %x) {
 ; CHECK-LABEL: and32_0xfff:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 52
-; CHECK-NEXT:    srli a0, a0, 52
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
 ; CHECK-NEXT:    ret
   %a = and i32 %x, 4095
   ret i32 %a
@@ -15,8 +14,7 @@ define i32 @and32_0xfff(i32 %x) {
 define i64 @and64_0xfff(i64 %x) {
 ; CHECK-LABEL: and64_0xfff:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 52
-; CHECK-NEXT:    srli a0, a0, 52
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
 ; CHECK-NEXT:    ret
   %a = and i64 %x, 4095
   ret i64 %a