[RISCV] Pre-commit

Author: tclin914

llvm/test/CodeGen/RISCV/rv32xandesperf.ll

@@ -2,6 +2,28 @@
 ; RUN: llc -O0 -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
+define i32 @and32_0xfff(i32 %x) {
+; CHECK-LABEL: and32_0xfff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 20
+; CHECK-NEXT:    srli a0, a0, 20
+; CHECK-NEXT:    ret
+  %a = and i32 %x, 4095
+  ret i32 %a
+}
+
+define i64 @and64_0xfff(i64 %x) {
+; CHECK-LABEL: and64_0xfff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $x11 killed $x10
+; CHECK-NEXT:    slli a0, a0, 20
+; CHECK-NEXT:    srli a0, a0, 20
+; CHECK-NEXT:    li a1, 0
+; CHECK-NEXT:    ret
+  %a = and i64 %x, 4095
+  ret i64 %a
+}
+
 define i32 @sexti1_i32(i32 %a) {
 ; CHECK-LABEL: sexti1_i32:
 ; CHECK:       # %bb.0:

llvm/test/CodeGen/RISCV/rv64xandesperf.ll

@@ -2,6 +2,26 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+xandesperf -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
+define i32 @and32_0xfff(i32 %x) {
+; CHECK-LABEL: and32_0xfff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 52
+; CHECK-NEXT:    srli a0, a0, 52
+; CHECK-NEXT:    ret
+  %a = and i32 %x, 4095
+  ret i32 %a
+}
+
+define i64 @and64_0xfff(i64 %x) {
+; CHECK-LABEL: and64_0xfff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 52
+; CHECK-NEXT:    srli a0, a0, 52
+; CHECK-NEXT:    ret
+  %a = and i64 %x, 4095
+  ret i64 %a
+}
+
 define signext i32 @sexti1_i32(i32 signext %a) {
 ; CHECK-LABEL: sexti1_i32:
 ; CHECK:       # %bb.0: