[arch][arm] Use conditional l/r register constraint in MMIO macros to fix Thumb-1 assembly#514
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[arch][arm] Use conditional l/r register constraint in MMIO macros to fix Thumb-1 assembly#514Copilot wants to merge 3 commits into
l/r register constraint in MMIO macros to fix Thumb-1 assembly#514Copilot wants to merge 3 commits into
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[WIP] Fix _ARCH_MMIO_WRITE32 to prevent assembling errors on Cortex-M0+
[arch][arm] Use Jun 17, 2026
l register constraint in MMIO macros to fix Thumb-1 assembly
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Pull request overview
This PR updates ARM MMIO accessor inline-asm constraints to avoid Thumb-1 assembler failures when GCC allocates high registers (R8–R15) for ldr*/str* operands, which are not encodable in Thumb-1’s 3-bit register fields.
Changes:
- Switch MMIO read/write inline-asm register constraints from
"r"/"=r"to"l"/"=l"inarch/arm/include/arch/reg.hto force low registers (R0–R7) in Thumb mode. - Apply the constraint change consistently across 8/16/32-bit load and store macros.
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| #define _ARCH_MMIO_READ8(addr) ({ \ | |||
| uint8_t val; \ | |||
| __asm__ volatile("ldrb %0, %1" : "=r"(val) : "m"(*(addr)) : "memory"); \ | |||
| __asm__ volatile("ldrb %0, %1" : "=l"(val) : "m"(*(addr)) : "memory"); \ | |||
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this is a fair request.
@copilot can you make this change?
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Done in accc632. _ARCH_MMIO_REG_CONSTRAINT now expands to "l" only when defined(__thumb__) && !defined(__thumb2__), and falls back to "r" for ARM state and Thumb-2 builds.
…513 Use the 'l' constraint (lo registers, R0-R7) only when building for Thumb-1 Thumb-1 16-bit str/ldr encodings only have a 3-bit register field. Fall back to 'r' for ARM state and Thumb-2 builds where the full register file is available, avoiding unnecessary register pressure in those cases.
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[arch][arm] Use
[arch][arm] Use conditional Jun 17, 2026
l register constraint in MMIO macros to fix Thumb-1 assemblyl/r register constraint in MMIO macros to fix Thumb-1 assembly
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On ARMv6-M (Cortex-M0+) and ARMv8-M Baseline, Thumb-1 16-bit encodings of
str/strh/strb/ldr/ldrh/ldrbonly have a 3-bit register field — restricting operands to R0–R7. The"r"constraint allows GCC to allocate R8–R15 (e.g. R12/ip), causing:Changes
arch/arm/include/arch/reg.h: Introduce_ARCH_MMIO_REG_CONSTRAINTwhich expands to"l"when building for Thumb-1 (defined(__thumb__) && !defined(__thumb2__)) and to"r"otherwise. Use this in all six_ARCH_MMIO_READ8/16/32and_ARCH_MMIO_WRITE8/16/32macros.The
"l"constraint is applied only where required (Thumb-1), while ARM state and Thumb-2 builds use the unrestricted"r"constraint to avoid unnecessary register pressure.