riscv: add init support #1516

Jvlegod · 2025-12-12T10:49:21Z

Hello maintainers. This PR initially supports RISC-V64 instructions.

After further improvements, it will support RISC-V32. RISC-V32 and RISC-V64 are similar in many ways, so I am referencing x86 and plan to put them in the same directory. In subsequent PRs, I will focus on participating in the development of the RISC-V module.

I wiil put a example here.

# I compiled it locally, so I inserted these two lines.
# you can fix the <PROJECT_PATH> with your path.
# then run `python3 setup.py build`.
import sys
sys.path.insert(0, "<PROJECT_PATH>/miasm/build/lib.linux-x86_64-cpython-311")


from miasm.core.locationdb import LocationDB

def code_sentinelle_riscv(jit):
    print("Hit sentinel!")
    print("X0 =", hex(jit.cpu.X1))
    jit.run = False

from miasm.arch.riscv.arch import mn_riscv

loc_db = LocationDB()
l = mn_riscv.fromstring("ADD X1, X3, X2", loc_db, 64)
# l = mn_riscv.fromstring("SLTIU X1, X5, 5", loc_db, 64)

print(l)
a = mn_riscv.asm(l)
print(a)
b = mn_riscv.dis(a[0], 64)
print(b)
from miasm.analysis.machine import Machine
mn = Machine('riscv').mn
instr = mn.dis(b'\x00\x21\x80\xb3', 64)
# instr = mn.dis(b'\x00\x52\xb0\x93', 64)
print(instr)

machine = Machine('riscv')
lifter = machine.lifter_model_call(loc_db)
ircfg = lifter.new_ircfg()
lifter.add_instr_to_ircfg(instr, ircfg)
for lbl, irblock in ircfg.blocks.items():
    print(irblock)
print("working with IR ---")
for lbl, irblock in ircfg.blocks.items():
    for assignblk in irblock:
        rw = assignblk.get_rw()
        for dst, reads in rw.items():
            print('read:   ', [str(x) for x in reads])
            print('written:', dst)
            print()
print("Emulate:")
from miasm.analysis.binary import Container
s = (
    b'\x00\x45\x05\x13'  # addi a0, a0, 4
    b'\x00\x15\x85\x93'  # addi a1, a1, 1
    b'\x0f\xf5\x72\x93'  # andi t0, a0, 0xff
    b'\xff\xf2\x82\x93'  # addi t0, t0, -1
    b'\x00\x02\x86\x63'  # beq  t0, x0, 1f
    b'\xff\xf5\x85\x93'  # addi a1, a1, -1
    b'\x00\x00\x04\x63'  # beq  x0, x0, 2f
    b'\x00\x15\x85\x93'  # 1: addi a1, a1, 1
    b'\x00\x05\x85\x13'  # 2: addi a0, a1, 0
    b'\x00\x00\x80\x67'  # jalr x0, ra, 0
)
# s = b'\x00\x21\x80\xb3'

loc_db = LocationDB()
c = Container.from_string(s, loc_db)
print(c)

mdis = machine.dis_engine(c.bin_stream, loc_db=loc_db)
asmcfg = mdis.dis_multiblock(0)
for block in asmcfg.blocks:
    print(block)

jitter = machine.jitter(loc_db, jit_type='python')
jitter.init_stack()
run_addr = 0x40000000
from miasm.jitter.csts import PAGE_READ, PAGE_WRITE
jitter.vm.add_memory_page(run_addr, PAGE_READ | PAGE_WRITE, s)

SENTINEL = 0x1337beef
jitter.cpu.X1 = SENTINEL

jitter.add_breakpoint(0x1337beef, code_sentinelle_riscv)
jitter.push_uint64_t(0x1337beef)
jitter.set_trace_log()
jitter.init_run(run_addr)
jitter.continue_run()

print("Symbolic execution:")
lifter = machine.lifter_model_call(loc_db)
ircfg = lifter.new_ircfg_from_asmcfg(asmcfg)
from miasm.ir.symbexec import SymbolicExecutionEngine
sb = SymbolicExecutionEngine(lifter)
symbolic_pc = sb.run_at(ircfg, 0)
print(symbolic_pc)
sb = SymbolicExecutionEngine(lifter, machine.mn.regs.regs_init)
symbolic_pc = sb.run_at(ircfg, 0, step=True)
from miasm.expression.expression import ExprInt
sb.symbols[machine.mn.regs.X1] = ExprInt(-3, 64)
symbolic_pc = sb.run_at(ircfg, 0, step=True)

Signed-off-by: Jvle <[email protected]>

Jvlegod · 2025-12-12T10:56:05Z

result

ADD        X1, X3, X2
[b'\x00!\x80\xb3']
ADD        X1, X3, X2
ADD        X1, X3, X2
loc_0:
X1 = X3 + X2

IRDst = loc_4

working with IR ---
read:    ['X3', 'X2']
written: X1

read:    []
written: IRDst

Emulate:
<miasm.analysis.binary.ContainerUnknown object at 0x7ac61046f550>
loc_0
ADDI       X10, X10, 0x4
ADDI       X11, X11, 0x1
ANDI       X5, X10, 0xFF
ADDI       X5, X5, 0xFFFFFFFFFFFFFFFF
BEQ        X5, X0, loc_1c
->	c_next:loc_14 	c_to:loc_1c 
loc_1c
ADDI       X11, X11, 0x1
->	c_next:loc_20 
loc_14
ADDI       X11, X11, 0xFFFFFFFFFFFFFFFF
BEQ        X0, X0, loc_20
->	c_next:loc_1c 	c_to:loc_20 
loc_20
ADDI       X10, X11, 0x0
JALR       X0, X1, 0x0
40000000 ADDI       X10, X10, 0x4
X0  0000000000000000 X1  000000001337BEEF X2  000000000123FFF8 X3  0000000000000000
X4  0000000000000000 X5  0000000000000000 X6  0000000000000000 X7  0000000000000000
X8  0000000000000000 X9  0000000000000000 X10 0000000000000004 X11 0000000000000000
X12 0000000000000000 X13 0000000000000000 X14 0000000000000000 X15 0000000000000000
X16 0000000000000000 X17 0000000000000000 X18 0000000000000000 X19 0000000000000000
X20 0000000000000000 X21 0000000000000000 X22 0000000000000000 X23 0000000000000000
X24 0000000000000000 X25 0000000000000000 X26 0000000000000000 X27 0000000000000000
X28 0000000000000000 X29 0000000000000000 X30 0000000000000000 X31 0000000000000000
PC  0000000040000004 exception_flags 00000000 interrupt_num 00000000
40000004 ADDI       X11, X11, 0x1
X0  0000000000000000 X1  000000001337BEEF X2  000000000123FFF8 X3  0000000000000000
X4  0000000000000000 X5  0000000000000000 X6  0000000000000000 X7  0000000000000000
X8  0000000000000000 X9  0000000000000000 X10 0000000000000004 X11 0000000000000001
X12 0000000000000000 X13 0000000000000000 X14 0000000000000000 X15 0000000000000000
X16 0000000000000000 X17 0000000000000000 X18 0000000000000000 X19 0000000000000000
X20 0000000000000000 X21 0000000000000000 X22 0000000000000000 X23 0000000000000000
X24 0000000000000000 X25 0000000000000000 X26 0000000000000000 X27 0000000000000000
X28 0000000000000000 X29 0000000000000000 X30 0000000000000000 X31 0000000000000000
PC  0000000040000008 exception_flags 00000000 interrupt_num 00000000
40000008 ANDI       X5, X10, 0xFF
X0  0000000000000000 X1  000000001337BEEF X2  000000000123FFF8 X3  0000000000000000
X4  0000000000000000 X5  0000000000000004 X6  0000000000000000 X7  0000000000000000
X8  0000000000000000 X9  0000000000000000 X10 0000000000000004 X11 0000000000000001
X12 0000000000000000 X13 0000000000000000 X14 0000000000000000 X15 0000000000000000
X16 0000000000000000 X17 0000000000000000 X18 0000000000000000 X19 0000000000000000
X20 0000000000000000 X21 0000000000000000 X22 0000000000000000 X23 0000000000000000
X24 0000000000000000 X25 0000000000000000 X26 0000000000000000 X27 0000000000000000
X28 0000000000000000 X29 0000000000000000 X30 0000000000000000 X31 0000000000000000
PC  000000004000000C exception_flags 00000000 interrupt_num 00000000
4000000C ADDI       X5, X5, 0xFFFFFFFFFFFFFFFF
X0  0000000000000000 X1  000000001337BEEF X2  000000000123FFF8 X3  0000000000000000
X4  0000000000000000 X5  0000000000000003 X6  0000000000000000 X7  0000000000000000
X8  0000000000000000 X9  0000000000000000 X10 0000000000000004 X11 0000000000000001
X12 0000000000000000 X13 0000000000000000 X14 0000000000000000 X15 0000000000000000
X16 0000000000000000 X17 0000000000000000 X18 0000000000000000 X19 0000000000000000
X20 0000000000000000 X21 0000000000000000 X22 0000000000000000 X23 0000000000000000
X24 0000000000000000 X25 0000000000000000 X26 0000000000000000 X27 0000000000000000
X28 0000000000000000 X29 0000000000000000 X30 0000000000000000 X31 0000000000000000
PC  0000000040000010 exception_flags 00000000 interrupt_num 00000000
40000010 BEQ        X5, X0, loc_4000001c
X0  0000000000000000 X1  000000001337BEEF X2  000000000123FFF8 X3  0000000000000000
X4  0000000000000000 X5  0000000000000003 X6  0000000000000000 X7  0000000000000000
X8  0000000000000000 X9  0000000000000000 X10 0000000000000004 X11 0000000000000001
X12 0000000000000000 X13 0000000000000000 X14 0000000000000000 X15 0000000000000000
X16 0000000000000000 X17 0000000000000000 X18 0000000000000000 X19 0000000000000000
X20 0000000000000000 X21 0000000000000000 X22 0000000000000000 X23 0000000000000000
X24 0000000000000000 X25 0000000000000000 X26 0000000000000000 X27 0000000000000000
X28 0000000000000000 X29 0000000000000000 X30 0000000000000000 X31 0000000000000000
PC  0000000040000014 exception_flags 00000000 interrupt_num 00000000
40000014 ADDI       X11, X11, 0xFFFFFFFFFFFFFFFF
X0  0000000000000000 X1  000000001337BEEF X2  000000000123FFF8 X3  0000000000000000
X4  0000000000000000 X5  0000000000000003 X6  0000000000000000 X7  0000000000000000
X8  0000000000000000 X9  0000000000000000 X10 0000000000000004 X11 0000000000000000
X12 0000000000000000 X13 0000000000000000 X14 0000000000000000 X15 0000000000000000
X16 0000000000000000 X17 0000000000000000 X18 0000000000000000 X19 0000000000000000
X20 0000000000000000 X21 0000000000000000 X22 0000000000000000 X23 0000000000000000
X24 0000000000000000 X25 0000000000000000 X26 0000000000000000 X27 0000000000000000
X28 0000000000000000 X29 0000000000000000 X30 0000000000000000 X31 0000000000000000
PC  0000000040000018 exception_flags 00000000 interrupt_num 00000000
40000018 BEQ        X0, X0, loc_40000020
X0  0000000000000000 X1  000000001337BEEF X2  000000000123FFF8 X3  0000000000000000
X4  0000000000000000 X5  0000000000000003 X6  0000000000000000 X7  0000000000000000
X8  0000000000000000 X9  0000000000000000 X10 0000000000000004 X11 0000000000000000
X12 0000000000000000 X13 0000000000000000 X14 0000000000000000 X15 0000000000000000
X16 0000000000000000 X17 0000000000000000 X18 0000000000000000 X19 0000000000000000
X20 0000000000000000 X21 0000000000000000 X22 0000000000000000 X23 0000000000000000
X24 0000000000000000 X25 0000000000000000 X26 0000000000000000 X27 0000000000000000
X28 0000000000000000 X29 0000000000000000 X30 0000000000000000 X31 0000000000000000
PC  0000000040000020 exception_flags 00000000 interrupt_num 00000000
40000020 ADDI       X10, X11, 0x0
X0  0000000000000000 X1  000000001337BEEF X2  000000000123FFF8 X3  0000000000000000
X4  0000000000000000 X5  0000000000000003 X6  0000000000000000 X7  0000000000000000
X8  0000000000000000 X9  0000000000000000 X10 0000000000000000 X11 0000000000000000
X12 0000000000000000 X13 0000000000000000 X14 0000000000000000 X15 0000000000000000
X16 0000000000000000 X17 0000000000000000 X18 0000000000000000 X19 0000000000000000
X20 0000000000000000 X21 0000000000000000 X22 0000000000000000 X23 0000000000000000
X24 0000000000000000 X25 0000000000000000 X26 0000000000000000 X27 0000000000000000
X28 0000000000000000 X29 0000000000000000 X30 0000000000000000 X31 0000000000000000
PC  0000000040000024 exception_flags 00000000 interrupt_num 00000000
40000024 JALR       X0, X1, 0x0
X0  0000000000000000 X1  000000001337BEEF X2  000000000123FFF8 X3  0000000000000000
X4  0000000000000000 X5  0000000000000003 X6  0000000000000000 X7  0000000000000000
X8  0000000000000000 X9  0000000000000000 X10 0000000000000000 X11 0000000000000000
X12 0000000000000000 X13 0000000000000000 X14 0000000000000000 X15 0000000000000000
X16 0000000000000000 X17 0000000000000000 X18 0000000000000000 X19 0000000000000000
X20 0000000000000000 X21 0000000000000000 X22 0000000000000000 X23 0000000000000000
X24 0000000000000000 X25 0000000000000000 X26 0000000000000000 X27 0000000000000000
X28 0000000000000000 X29 0000000000000000 X30 0000000000000000 X31 0000000000000000
PC  000000001337BEEF exception_flags 00000000 interrupt_num 00000000
Hit sentinel!
X0 = 0x1337beef
Symbolic execution:
((((X10 + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0)?(0x1C,0x14)
Instr ADDI       X10, X10, 0x4
Assignblk:
X10 = X10 + 0x4
________________________________________________________________________________
X0                 = X0_init
X1                 = X1_init
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = X5_init
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x4
X11                = X11_init
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = PC_init
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
________________________________________________________________________________
Instr ADDI       X11, X11, 0x1
Assignblk:
X11 = X11 + 0x1
________________________________________________________________________________
X0                 = X0_init
X1                 = X1_init
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = X5_init
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x4
X11                = X11_init + 0x1
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = PC_init
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
________________________________________________________________________________
Instr ANDI       X5, X10, 0xFF
Assignblk:
X5 = X10 & 0xFF
________________________________________________________________________________
X0                 = X0_init
X1                 = X1_init
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = (X10_init + 0x4) & 0xFF
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x4
X11                = X11_init + 0x1
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = PC_init
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
________________________________________________________________________________
Instr ADDI       X5, X5, 0xFFFFFFFFFFFFFFFF
Assignblk:
X5 = X5 + 0xFFFFFFFFFFFFFFFF
________________________________________________________________________________
X0                 = X0_init
X1                 = X1_init
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = ((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x4
X11                = X11_init + 0x1
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = PC_init
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
________________________________________________________________________________
Instr BEQ        X5, X0, loc_key_1
Assignblk:
PC = (X5 == X0)?(loc_key_1,loc_key_2)
IRDst = (X5 == X0)?(loc_key_1,loc_key_2)
________________________________________________________________________________
X0                 = X0_init
X1                 = X1_init
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = ((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x4
X11                = X11_init + 0x1
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
IRDst              = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
________________________________________________________________________________
Instr ADDI       X10, X10, 0x4
Assignblk:
X10 = X10 + 0x4
________________________________________________________________________________
X0                 = X0_init
X1                 = 0xFFFFFFFFFFFFFFFD
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = ((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x8
X11                = X11_init + 0x1
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
IRDst              = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
________________________________________________________________________________
Instr ADDI       X11, X11, 0x1
Assignblk:
X11 = X11 + 0x1
________________________________________________________________________________
X0                 = X0_init
X1                 = 0xFFFFFFFFFFFFFFFD
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = ((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x8
X11                = X11_init + 0x2
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
IRDst              = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
________________________________________________________________________________
Instr ANDI       X5, X10, 0xFF
Assignblk:
X5 = X10 & 0xFF
________________________________________________________________________________
X0                 = X0_init
X1                 = 0xFFFFFFFFFFFFFFFD
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = (X10_init + 0x8) & 0xFF
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x8
X11                = X11_init + 0x2
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
IRDst              = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
________________________________________________________________________________
Instr ADDI       X5, X5, 0xFFFFFFFFFFFFFFFF
Assignblk:
X5 = X5 + 0xFFFFFFFFFFFFFFFF
________________________________________________________________________________
X0                 = X0_init
X1                 = 0xFFFFFFFFFFFFFFFD
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = ((X10_init + 0x8) & 0xFF) + 0xFFFFFFFFFFFFFFFF
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x8
X11                = X11_init + 0x2
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
IRDst              = ((((X10_init + 0x4) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
________________________________________________________________________________
Instr BEQ        X5, X0, loc_key_1
Assignblk:
PC = (X5 == X0)?(loc_key_1,loc_key_2)
IRDst = (X5 == X0)?(loc_key_1,loc_key_2)
________________________________________________________________________________
X0                 = X0_init
X1                 = 0xFFFFFFFFFFFFFFFD
X2                 = X2_init
X3                 = X3_init
X4                 = X4_init
X5                 = ((X10_init + 0x8) & 0xFF) + 0xFFFFFFFFFFFFFFFF
X6                 = X6_init
X7                 = X7_init
X8                 = X8_init
X9                 = X9_init
X10                = X10_init + 0x8
X11                = X11_init + 0x2
X12                = X12_init
X13                = X13_init
X14                = X14_init
X15                = X15_init
X16                = X16_init
X17                = X17_init
X18                = X18_init
X19                = X19_init
X20                = X20_init
X21                = X21_init
X22                = X22_init
X23                = X23_init
X24                = X24_init
X25                = X25_init
X26                = X26_init
X27                = X27_init
X28                = X28_init
X29                = X29_init
X30                = X30_init
X31                = X31_init
PC                 = ((((X10_init + 0x8) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
USTATUS            = USTATUS_init
UIE                = UIE_init
UTVEC              = UTVEC_init
USCRATCH           = USCRATCH_init
UEPC               = UEPC_init
UCAUSE             = UCAUSE_init
UTVAL              = UTVAL_init
UIP                = UIP_init
SSTATUS            = SSTATUS_init
SIE                = SIE_init
STVEC              = STVEC_init
SSCRATCH           = SSCRATCH_init
SEPC               = SEPC_init
SCAUSE             = SCAUSE_init
STVAL              = STVAL_init
SIP                = SIP_init
SATP               = SATP_init
MSTATUS            = MSTATUS_init
MISA               = MISA_init
MIE                = MIE_init
MTVEC              = MTVEC_init
MSCRATCH           = MSCRATCH_init
MEPC               = MEPC_init
MCAUSE             = MCAUSE_init
MTVAL              = MTVAL_init
MIP                = MIP_init
MVENDORID          = MVENDORID_init
MARCHID            = MARCHID_init
MIMPID             = MIMPID_init
MHARTID            = MHARTID_init
IRDst              = ((((X10_init + 0x8) & 0xFF) + 0xFFFFFFFFFFFFFFFF) == X0_init)?(0x1C,0x14)
________________________________________________________________________________

serpilliere · 2025-12-13T13:17:27Z

Hi @Jvlegod !
Thanks a lot for the PR: That's really cool!
I will take time to review it in 15 or 20 days.

Thanks again!

Jvlegod · 2025-12-15T01:44:08Z

Okay, I'm happy to resolve any issues you may have.

Jvlegod added 8 commits December 12, 2025 16:48

test: add riscv init support

9a017e5

Signed-off-by: Jvle <[email protected]>

riscv: add init jitter support

a49e00c

Signed-off-by: Jvle <[email protected]>

riscv: add register definitions

34ad671

Signed-off-by: Jvle <[email protected]>

riscv: add RV64I init encode/decode

1db11a9

Signed-off-by: Jvle <[email protected]>

riscv: add RV64I init IR semantics

e88f288

Signed-off-by: Jvle <[email protected]>

riscv: add jit and lifter_model_call

bc55081

Signed-off-by: Jvle <[email protected]>

riscv: add machine support

b29a70f

Signed-off-by: Jvle <[email protected]>

riscv: add setup option

14f1f07

Signed-off-by: Jvle <[email protected]>

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riscv: add init support #1516

riscv: add init support #1516

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Jvlegod commented Dec 12, 2025 •

edited

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Jvlegod commented Dec 12, 2025

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serpilliere commented Dec 13, 2025

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Jvlegod commented Dec 15, 2025

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Jvlegod commented Dec 12, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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Jvlegod commented Dec 12, 2025

result

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serpilliere commented Dec 13, 2025

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Jvlegod commented Dec 15, 2025

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Jvlegod commented Dec 12, 2025 •

edited

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