Add SparkFun Thing Plus RA6M5.

boards.txt

@@ -206,3 +206,51 @@ muxto.upload.maximum_size=262144
 muxto.upload.maximum_data_size=32768
 
 ##############################################################
+
+thingplus_ra6m5.name=SparkFun Thing Plus RA6M5
+thingplus_ra6m5.build.core=arduino
+thingplus_ra6m5.build.crossprefix=arm-none-eabi-
+thingplus_ra6m5.build.compiler_path={runtime.tools.arm-none-eabi-gcc-7-2017q4.path}/bin/
+
+thingplus_ra6m5.build.variant=THINGPLUS_RA6M5
+thingplus_ra6m5.build.mcu=cortex-m33
+thingplus_ra6m5.build.architecture=cortex-m33
+thingplus_ra6m5.build.fpu=-mfpu=fpv5-sp-d16
+thingplus_ra6m5.build.float-abi=-mfloat-abi=hard
+
+thingplus_ra6m5.build.board=THINGPLUS_RA6M5
+thingplus_ra6m5.build.defines=-DF_CPU=200000000
+thingplus_ra6m5.vid.0=0x1b4f
+thingplus_ra6m5.pid.0=0x0037
+thingplus_ra6m5.vid.1=0x1b4f
+thingplus_ra6m5.pid.1=0x0036
+thingplus_ra6m5.upload_port.0.vid=0x1b4f
+thingplus_ra6m5.upload_port.0.pid=0x0037
+thingplus_ra6m5.upload_port.1.vid=0x1b4f
+thingplus_ra6m5.upload_port.1.pid=0x0036
+
+thingplus_ra6m5.compiler.fsp.defines={build.variant.path}/defines.txt
+thingplus_ra6m5.compiler.fsp.ldflags={build.variant.path}/ldflags.txt
+thingplus_ra6m5.compiler.fsp.cflags=-mthumb "@{compiler.fsp.defines}"
+thingplus_ra6m5.compiler.fsp.cxxflags=-mthumb "@{compiler.fsp.defines}"
+thingplus_ra6m5.compiler.tinyusb.cflags=-DCFG_TUSB_MCU=OPT_MCU_RAXXX
+thingplus_ra6m5.compiler.tinyusb.cxxflags=-DCFG_TUSB_MCU=OPT_MCU_RAXXX
+thingplus_ra6m5.compiler.fsp.includes={build.variant.path}/includes.txt
+thingplus_ra6m5.compiler.fsp.extra_ldflags=-lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
+thingplus_ra6m5.compiler.fsp="{build.variant.path}/libs/libfsp.a"
+
+thingplus_ra6m5.upload.tool=dfu-util
+thingplus_ra6m5.upload.tool.default=dfu-util
+thingplus_ra6m5.upload.protocol=
+thingplus_ra6m5.upload.transport=
+thingplus_ra6m5.upload.vid=0x1b4f
+thingplus_ra6m5.upload.pid=0x0036
+thingplus_ra6m5.upload.address=0x00010000
+thingplus_ra6m5.upload.interface=0
+thingplus_ra6m5.upload.use_1200bps_touch=false
+thingplus_ra6m5.upload.wait_for_upload_port=false
+thingplus_ra6m5.upload.native_usb=true
+thingplus_ra6m5.upload.maximum_size=2097152
+thingplus_ra6m5.upload.maximum_data_size=523624
+
+##############################################################

bootloaders/THINGPLUS_RA6M5/README.md

@@ -0,0 +1,30 @@
+:floppy_disk: `bootloaders/THINGPLUS_RA6M5`
+====================================
+Compiled with
+```bash
+git clone https://github.com/arduino/arduino-renesas-bootloader
+git clone https://github.com/hathach/tinyusb
+cd tinyusb
+# This step is temporary
+patch -p1 < ../arduino-renesas-bootloader/0001-fix-arduino-bootloaders.patch
+python tools/get_deps.py ra
+cd ..
+cd arduino-renesas-bootloader
+TINYUSB_ROOT=$PWD/../tinyusb make -f Makefile.thingplus
+```
+
+:rocket: `How to load bootloader`
+====================================
+
+Pull the boot test point low and plug in the Thing Plus RA6M5.
+The board will enumerate as Renesas RA USB Boot.
+
+Then flash the bootloader with [`rfp-cli`](https://www.renesas.com/us/en/software-tool/renesas-flash-programmer-programming-gui#download)
+```
+rfp-cli -device ra -port COM# -p dfu.hex
+```
+
+Otherwise, the same hex file can be loaded through the SWD port (using a Jlink or E2 Emulator for example)
+```
+rfp-cli -device ra -tool e2 -if swd -p dfu.hex
+```

drivers/sferenesas.inf

@@ -0,0 +1,63 @@
+;
+;
+; Installs WinUsb
+;
+
+[Strings]
+ManufacturerName="SparkFun Electronics"
+ClassName="Universal Serial Bus devices"
+REG_MULTI_SZ = 0x00010000
+DeviceNameThingPlusRA6M5 = "Thing Plus RA6M5 Firmware Upgrade"
+DeviceNameThingPlusRA6M5DFU = "Thing Plus RA6M5 (Upgrade)"
+VendorName = "SparkFun Electronics"
+SourceName = "SparkFun Renesas Firmware Upgrade Install Disk"
+DeviceIDThingPlusRA6M5   = "VID_1B4F&PID_0037&Rev_0100&MI_02"
+DeviceIDThingPlusRA6M5DFU= "VID_1B4F&PID_0036&Rev_0100"
+
+[Version]
+Signature   = "$Windows NT$"
+Class       = USBDevice
+ClassGUID   = {88BAE032-5A81-49f0-BC3D-A4FF138216D6}
+Provider    = %ManufacturerName%
+CatalogFile = sferenesas.cat
+DriverVer = 04/06/2024,16.32.52.384
+
+; ========== Manufacturer/Models sections ===========
+
+[Manufacturer]
+%ManufacturerName% = Standard,NTamd64
+
+[Standard.NTamd64]
+%DeviceNameThingPlusRA6M5% =USB_Install, USB\%DeviceIDThingPlusRA6M5%
+%DeviceNameThingPlusRA6M5DFU% =USB_Install, USB\%DeviceIDThingPlusRA6M5DFU%
+
+; ========== Class definition ===========
+
+[ClassInstall32]
+AddReg = ClassInstall_AddReg
+
+[ClassInstall_AddReg]
+HKR,,,,%ClassName%
+HKR,,NoInstallClass,,1
+HKR,,IconPath,%REG_MULTI_SZ%,"%systemroot%\system32\setupapi.dll,-20"
+HKR,,LowerLogoVersion,,5.2
+
+; =================== Installation ===================
+
+[USB_Install]
+Include = winusb.inf
+Needs   = WINUSB.NT
+
+[USB_Install.Services]
+Include = winusb.inf
+Needs   = WINUSB.NT.Services
+
+[USB_Install.HW]
+AddReg=Dev_AddReg
+
+[Dev_AddReg]
+HKR,,DeviceInterfaceGUIDs,0x10000,"{51de5bfa-d59d-4f3e-9b36-0b4b210dd53f}"
+
+; [DestinationDirs]
+; If your INF needs to copy files, you must not use the DefaultDestDir directive here.  
+; You must explicitly reference all file-list-section names in this section.

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.api_xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<ddscApi/>

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.gitignore

@@ -0,0 +1,8 @@
+src
+script
+ra_gen
+ra_cfg
+ra
+Debug
+*.d
+*.o

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.project

@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>SparkFun_ThingPlus_RA6M5</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.renesas.cdt.ddsc.contentgen.ddscBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>com.renesas.cdt.ddsc.contentgen.ddscInterlockBundleBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>com.renesas.cdt.ddsc.contentgen.ddscNature</nature>
+		<nature>com.renesas.cdt.ra.contentgen.raNature</nature>
+	</natures>
+</projectDescription>

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_azone

@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<azone>
+    <rzone name="R7FA6M5AH3CFP.rzone"/>
+    <partition>
+        <peripheral name="PORT0" group="PORT">
+            <slot name="P014" secure="true"/>
+            <slot name="P015" secure="true"/>
+        </peripheral>
+        <peripheral name="PORT1" group="PORT">
+            <slot name="P100" secure="true"/>
+            <slot name="P101" secure="true"/>
+            <slot name="P102" secure="true"/>
+            <slot name="P103" secure="true"/>
+            <slot name="P104" secure="true"/>
+            <slot name="P108" secure="true"/>
+            <slot name="P109" secure="true"/>
+            <slot name="P110" secure="true"/>
+            <slot name="P111" secure="true"/>
+            <slot name="P112" secure="true"/>
+        </peripheral>
+        <peripheral name="PORT2" group="PORT">
+            <slot name="P200" secure="true"/>
+            <slot name="P201" secure="true"/>
+            <slot name="P205" secure="true"/>
+            <slot name="P206" secure="true"/>
+            <slot name="P208" secure="true"/>
+            <slot name="P210" secure="true"/>
+            <slot name="P211" secure="true"/>
+            <slot name="P212" secure="true"/>
+            <slot name="P213" secure="true"/>
+            <slot name="P214" secure="true"/>
+        </peripheral>
+        <peripheral name="PORT3" group="PORT">
+            <slot name="P300" secure="true"/>
+            <slot name="P301" secure="true"/>
+            <slot name="P303" secure="true"/>
+        </peripheral>
+        <peripheral name="PORT4" group="PORT">
+            <slot name="P400" secure="true"/>
+            <slot name="P401" secure="true"/>
+            <slot name="P402" secure="true"/>
+            <slot name="P403" secure="true"/>
+            <slot name="P404" secure="true"/>
+            <slot name="P405" secure="true"/>
+            <slot name="P406" secure="true"/>
+            <slot name="P407" secure="true"/>
+            <slot name="P408" secure="true"/>
+            <slot name="P409" secure="true"/>
+            <slot name="P410" secure="true"/>
+            <slot name="P414" secure="true"/>
+        </peripheral>
+        <peripheral name="PORT5" group="PORT">
+            <slot name="P501" secure="true"/>
+            <slot name="P502" secure="true"/>
+            <slot name="P503" secure="true"/>
+            <slot name="P504" secure="true"/>
+            <slot name="P505" secure="true"/>
+        </peripheral>
+        <peripheral name="PORT6" group="PORT">
+            <slot name="P601" secure="true"/>
+            <slot name="P602" secure="true"/>
+        </peripheral>
+        <peripheral name="SCI0" group="SCI" security=""/>
+        <peripheral name="IIC0" group="IIC" security=""/>
+        <peripheral name="ADC0" group="ADC" security=""/>
+        <peripheral name="DAC0" group="DAC" security=""/>
+        <peripheral name="DAC120" group="DAC12" security=""/>
+        <peripheral name="SSIE0" group="SSIE" security=""/>
+        <peripheral name="SCI3" group="SCI" security=""/>
+        <peripheral name="ICU_EXT_IRQ">
+            <slot name="ICU_EXT_IRQ0" secure="true"/>
+        </peripheral>
+        <peripheral name="QSPI" security=""/>
+        <peripheral name="SDHI0" group="SDHI" security=""/>
+        <peripheral name="RTC" security=""/>
+        <peripheral name="SCI9" group="SCI" security=""/>
+        <peripheral name="SPI0" group="SPI" security=""/>
+        <peripheral name="DMA_DMAC0" group="DMA_DMAC" security=""/>
+        <peripheral name="AGT0" group="AGT" security=""/>
+        <peripheral name="ICU">
+            <slot name="IRQ0" secure="true"/>
+            <slot name="IRQ1" secure="true"/>
+            <slot name="IRQ2" secure="true"/>
+            <slot name="IRQ3" secure="true"/>
+            <slot name="IRQ4" secure="true"/>
+            <slot name="IRQ5" secure="true"/>
+            <slot name="IRQ6" secure="true"/>
+            <slot name="IRQ7" secure="true"/>
+            <slot name="IRQ8" secure="true"/>
+            <slot name="IRQ9" secure="true"/>
+            <slot name="IRQ10" secure="true"/>
+            <slot name="IRQ11" secure="true"/>
+            <slot name="IRQ12" secure="true"/>
+            <slot name="IRQ13" secure="true"/>
+            <slot name="IRQ14" secure="true"/>
+            <slot name="IRQ15" secure="true"/>
+            <slot name="IRQ16" secure="true"/>
+            <slot name="IRQ17" secure="true"/>
+            <slot name="IRQ18" secure="true"/>
+            <slot name="IRQ19" secure="true"/>
+            <slot name="IRQ20" secure="true"/>
+            <slot name="IRQ21" secure="true"/>
+            <slot name="IRQ22" secure="true"/>
+            <slot name="IRQ23" secure="true"/>
+            <slot name="IRQ24" secure="true"/>
+            <slot name="IRQ25" secure="true"/>
+            <slot name="IRQ26" secure="true"/>
+            <slot name="IRQ27" secure="true"/>
+            <slot name="IRQ28" secure="true"/>
+            <slot name="IRQ29" secure="true"/>
+            <slot name="IRQ30" secure="true"/>
+            <slot name="IRQ31" secure="true"/>
+            <slot name="IRQ32" secure="true"/>
+        </peripheral>
+    </partition>
+</azone>

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml

@@ -0,0 +1,109 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="9">
+  <generalSettings>
+    <option key="#Board#" value="board.custom"/>
+    <option key="CPU" value="RA6M5"/>
+    <option key="Core" value="CM33"/>
+    <option key="#TargetName#" value="R7FA6M5AH3CFP"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m33"/>
+    <option key="#DeviceCommand#" value="R7FA6M5AH"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA6M5AH3CFP.pincfg"/>
+    <option key="#FSPVersion#" value="4.0.0"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="gcc-arm-embedded"/>
+    <option key="#ToolchainVersion#" value="10.3.1.20210824"/>
+  </generalSettings>
+  <raBspConfiguration/>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
+    <node id="board.clock.pll.div" option="board.clock.pll.div.3"/>
+    <node id="board.clock.pll.mul" option="board.clock.pll.mul.250"/>
+    <node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
+    <node id="board.clock.pll2.source" option="board.clock.pll2.source.xtal"/>
+    <node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
+    <node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/>
+    <node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.uclk.source" option="board.clock.uclk.source.pll2"/>
+    <node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
+    <node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
+    <node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
+    <node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
+    <node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/>
+    <node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
+    <node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.1"/>
+    <node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.6"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
+    <node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+    <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
+    <node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
+    <node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
+  </raClockConfiguration>
+  <raPinConfiguration>
+    <pincfg active="true" name="" symbol="">
+      <configSetting altId="adc1.an18.p502" configurationId="adc1.an18"/>
+      <configSetting altId="adc1.an19.p503" configurationId="adc1.an19"/>
+      <configSetting altId="adc1.an20.p504" configurationId="adc1.an20"/>
+      <configSetting altId="adc1.an21.p505" configurationId="adc1.an21"/>
+      <configSetting altId="cgc0.extal.p212" configurationId="cgc0.extal" isUsedByDriver="true"/>
+      <configSetting altId="cgc0.xtal.p213" configurationId="cgc0.xtal" isUsedByDriver="true"/>
+      <configSetting altId="dac0.da.p014" configurationId="dac0.da" isUsedByDriver="true"/>
+      <configSetting altId="dac1.da.p015" configurationId="dac1.da"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk" isUsedByDriver="true"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio" isUsedByDriver="true"/>
+      <configSetting altId="debug0.traceswo.p109" configurationId="debug0.traceswo" isUsedByDriver="true"/>
+      <configSetting altId="iic0.scl.p400" configurationId="iic0.scl" isUsedByDriver="true"/>
+      <configSetting altId="iic0.sda.p401" configurationId="iic0.sda" isUsedByDriver="true"/>
+      <configSetting altId="irq0.nmi.p200" configurationId="irq0.nmi"/>
+      <configSetting altId="qspi0.qio0.p102" configurationId="qspi0.qio0" isUsedByDriver="true"/>
+      <configSetting altId="qspi0.qio1.p101" configurationId="qspi0.qio1" isUsedByDriver="true"/>
+      <configSetting altId="qspi0.qio2.p104" configurationId="qspi0.qio2" isUsedByDriver="true"/>
+      <configSetting altId="qspi0.qio3.p103" configurationId="qspi0.qio3" isUsedByDriver="true"/>
+      <configSetting altId="qspi0.qspclk.p100" configurationId="qspi0.qspclk" isUsedByDriver="true"/>
+      <configSetting altId="qspi0.qssl.p501" configurationId="qspi0.qssl" isUsedByDriver="true"/>
+      <configSetting altId="sci3.rxd.p408" configurationId="sci3.rxd" isUsedByDriver="true"/>
+      <configSetting altId="sci3.txd.p409" configurationId="sci3.txd" isUsedByDriver="true"/>
+      <configSetting altId="sci9.cts.p303" configurationId="sci9.cts" isUsedByDriver="true"/>
+      <configSetting altId="sci9.ctsrts.p301" configurationId="sci9.ctsrts" isUsedByDriver="true"/>
+      <configSetting altId="sci9.rxd.p601" configurationId="sci9.rxd" isUsedByDriver="true"/>
+      <configSetting altId="sci9.txd.p602" configurationId="sci9.txd" isUsedByDriver="true"/>
+      <configSetting altId="sdhi0.cd.p210" configurationId="sdhi0.cd" isUsedByDriver="true"/>
+      <configSetting altId="sdhi0.clk.p214" configurationId="sdhi0.clk" isUsedByDriver="true"/>
+      <configSetting altId="sdhi0.cmd.p211" configurationId="sdhi0.cmd" isUsedByDriver="true"/>
+      <configSetting altId="sdhi0.dat0.p208" configurationId="sdhi0.dat0" isUsedByDriver="true"/>
+      <configSetting altId="sdhi0.dat1.p410" configurationId="sdhi0.dat1" isUsedByDriver="true"/>
+      <configSetting altId="sdhi0.dat2.p206" configurationId="sdhi0.dat2" isUsedByDriver="true"/>
+      <configSetting altId="sdhi0.dat3.p205" configurationId="sdhi0.dat3" isUsedByDriver="true"/>
+      <configSetting altId="sdhi0.wp.p414" configurationId="sdhi0.wp" isUsedByDriver="true"/>
+      <configSetting altId="spi0.miso.p110" configurationId="spi0.miso" isUsedByDriver="true"/>
+      <configSetting altId="spi0.rspck.p111" configurationId="spi0.rspck" isUsedByDriver="true"/>
+      <configSetting altId="spi0.ssl0.p112" configurationId="spi0.ssl0" isUsedByDriver="true"/>
+      <configSetting altId="ssi0.ssirxd.p406" configurationId="ssi0.ssirxd" isUsedByDriver="true"/>
+      <configSetting altId="ssi0.ssisck.p403" configurationId="ssi0.ssisck" isUsedByDriver="true"/>
+      <configSetting altId="ssi0.ssitxd.p405" configurationId="ssi0.ssitxd" isUsedByDriver="true"/>
+      <configSetting altId="ssi0.ssiws.p404" configurationId="ssi0.ssiws" isUsedByDriver="true"/>
+      <configSetting altId="ssi_common0.audio_clk.p402" configurationId="ssi_common0.audio_clk"/>
+      <configSetting altId="system0.md.p201" configurationId="system0.md"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/.gitignore

@@ -0,0 +1 @@
+/e2studio_project.prefs

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.content.prefs

@@ -0,0 +1,2 @@
+com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.ld
+eclipse.preferences.version=1

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.contentgen.options.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+options/suppresswarningspaths=ra/arm,ra/renesas

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.settingseditor.prefs

@@ -0,0 +1,2 @@
+com.renesas.cdt.ddsc.settingseditor.active_page=ModuleSelection
+eclipse.preferences.version=1

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.threads.configurator.prefs

@@ -0,0 +1,12 @@
+collapse/module.driver.basic_on_usb.283002553=false
+collapse/module.driver.i2c_on_iic_master.857983463=false
+collapse/module.driver.i2c_on_sci_i2c.66231608=false
+collapse/module.driver.i2s_on_ssi.803618372=false
+collapse/module.driver.pcdc_on_usb.592586967=false
+collapse/module.driver.sdmmc_on_sdmmc.61359805=false
+collapse/module.driver.spi_on_sci_spi.786111052=false
+collapse/module.driver.spi_on_spi.1145449710=false
+collapse/module.driver.uart_on_sci_uart.1673971705=false
+collapse/module.driver.uart_on_sci_uart.623240377=false
+collapse/module.driver.usb_composite.845210554=false
+eclipse.preferences.version=1

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs

@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+is.toolchain.version=true
+store.version=2
+toolchain.version=10.3.1.20210824

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/language.settings.xml

@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1249346433081015176" id="org.eclipse.embedcdt.managedbuild.cross.arm.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Arm Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+	<configuration id="com.renesas.cdt.managedbuild.gnuarm.config.elf.release.942781880" name="Release">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1333764289719086120" id="org.eclipse.embedcdt.managedbuild.cross.arm.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Arm Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.cdt.managedbuilder.core.prefs

@@ -0,0 +1,13 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/CPLUS_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/CPLUS_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/append=true
+environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/appendContributed=true
+environment/buildEnvironmentLibrary/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/append=true
+environment/buildEnvironmentLibrary/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/appendContributed=true

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.core.resources.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding/<project>=UTF-8

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/SparkFun_ThingPlus_RA6M5 Debug_Flat.launch

@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.renesas.cdt.launch.dsf.gdbremote.launchConfigurationType">
+    <booleanAttribute key=".setStepMode" value="false"/>
+    <stringAttribute key="com.renesas.cdt.core.additionalServerArgs" value=""/>
+    <intAttribute key="com.renesas.cdt.core.connectionTimeout" value="30"/>
+    <stringAttribute key="com.renesas.cdt.core.initCommands" value=""/>
+    <stringAttribute key="com.renesas.cdt.core.ipAddress" value="localhost"/>
+    <stringAttribute key="com.renesas.cdt.core.jtagDeviceId" value="com.renesas.hardwaredebug.arm.e2"/>
+    <listAttribute key="com.renesas.cdt.core.listGDBExe">
+        <listEntry value="arm-none-eabi-gdb"/>
+    </listAttribute>
+    <listAttribute key="com.renesas.cdt.core.listGDBLaunchName">
+        <listEntry value="main"/>
+    </listAttribute>
+    <listAttribute key="com.renesas.cdt.core.listGDBPort">
+        <listEntry value="61234"/>
+    </listAttribute>
+    <stringAttribute key="com.renesas.cdt.core.optionInitCommands" value="monitor force_rtos_off&#10;&#10;"/>
+    <intAttribute key="com.renesas.cdt.core.portNumber" value="61234"/>
+    <stringAttribute key="com.renesas.cdt.core.runCommands" value=""/>
+    <stringAttribute key="com.renesas.cdt.core.secondGDBExe" value="green_dsp-elf-gdb"/>
+    <booleanAttribute key="com.renesas.cdt.core.secondGDBSupport" value="false"/>
+    <intAttribute key="com.renesas.cdt.core.secondGdbPortNumber" value="61237"/>
+    <stringAttribute key="com.renesas.cdt.core.serverParam" value="-g E2 -t R7FA6M5AH -uConnectionTimeout= 30 -uClockSrc= &quot;0&quot; -uAllowClockSourceInternal= 1 -uInteface= &quot;SWD&quot; -uIfSpeed= &quot;auto&quot; -w &quot;1&quot; -z &quot;33&quot; -uResetCon= 1 -uLowPower= 1 -uEnableSciBoot=  1 -uSWOclockDiv= &quot;4&quot; -uresetOnReload= 1 -n &quot;0&quot; -uFlashBp= 0 -uhookWorkRamSize= &quot;0x400&quot; -ueraseRomOnDownload= 0 -ueraseDataRomOnDownload= 0 -uTraceMTB=  0 -uTraceSizeMTB=  &quot;1024&quot; -uProgReWriteIRom= 0 -uProgReWriteDFlash= 0 -uOSRestriction= 0 -uTimeMeasurementEnable= 1 -uDWTEnable= 0"/>
+    <booleanAttribute key="com.renesas.cdt.core.setResume" value="true"/>
+    <booleanAttribute key="com.renesas.cdt.core.startServer" value="true"/>
+    <stringAttribute key="com.renesas.cdt.core.targetDevice" value="R7FA6M5AH"/>
+    <booleanAttribute key="com.renesas.cdt.core.useRemoteTarget" value="true"/>
+    <stringAttribute key="com.renesas.cdt.launch.dsf.IO_MAP" value="${support_area_loc}"/>
+    <booleanAttribute key="com.renesas.cdt.launch.dsf.USE_DEFAULT_IO_MAP" value="true"/>
+    <listAttribute key="com.renesas.cdt.launch.dsf.downloadImages">
+        <listEntry value="|true|true|true||true|No core|INTERNAL_MEMORY||false"/>
+    </listAttribute>
+    <booleanAttribute key="com.renesas.cdt.launch.dsf.downloadImagesUpgradedV30" value="true"/>
+    <listAttribute key="com.renesas.cdt.launch.dsf.externalFlashDestinationAddresses"/>
+    <listAttribute key="com.renesas.cdt.launch.dsf.externalFlashDownloadModules"/>
+    <stringAttribute key="com.renesas.cdt.launch.dsf.launchSeqType" value="com.renesas.cdt.launch.dsf.launchSequence.e2GdbServer"/>
+    <stringAttribute key="com.renesas.cdt.launch.dsf.serverPath" value="${renesas.support.targetLoc:com.renesas.ide.supportfiles.ra.debug.debugSupportFileTarget}\e2-server-gdb"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.allow.clock.source.internal" value="true"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.break.useFlashBreakpoints" value="false"/>
+    <intAttribute key="com.renesas.hardwaredebug.arm.e2.clock_source" value="0"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.connection.id_code.format.big_endian" value="false"/>
+    <intAttribute key="com.renesas.hardwaredebug.arm.e2.connection.id_code.input_type" value="0"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.connection.id_code2" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.connection.resetCon" value="true"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.connection.type" value="SWD"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.enable.hot.plug" value="false"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.enable_dwt" value="false"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.eraseDataRomOnDownload" value="false"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.eraseRomOnDownload" value="false"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.hook_Stop_func" value=""/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.hook_enable_Stop" value="false"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.hook_enable_start" value="false"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.hook_start_func" value=""/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.hook_work_ram_Addr" value=""/>
+    <intAttribute key="com.renesas.hardwaredebug.arm.e2.hook_work_ram_Size" value="1024"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.inputclock" value=""/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.interface.speed" value="auto"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.lowPowerHandling" value="true"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.memory.isLittleEndian" value="true"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.operating.freq" value=""/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.options.ArmE2DebugToolSettingsTree.resetAfterReload" value="true"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.prog_rewrite_dflash" value="false"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.prog_rewrite_irom" value="false"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.pwr" value="true"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.rtosIntegrationInDebugView" value="false"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.rtosintegrationthreadsrunning" value="false"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.serial_number" value=""/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.setTZBoundaries" value="true"/>
+    <intAttribute key="com.renesas.hardwaredebug.arm.e2.supply.power.via" value="1"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.supply.voltage" value="3.3"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.swvFrequencyDivision" value="16"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2.traceMTB" value="false"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2.traceSizeMTB" value="1024"/>
+    <booleanAttribute key="com.renesas.hardwaredebug.arm.e2com.renesas.hardwaredebug.timemeasurement" value="true"/>
+    <stringAttribute key="com.renesas.hardwaredebug.arm.e2workRam.startAddr" value=""/>
+    <booleanAttribute key="com.renesas.hardwaredebug.timemeasurement" value="true"/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="C:\Users\alex.brudner\Documents\GitHub\ArduinoCore-renesas\extras\e2studioProjects\SparkFun_ThingPlus_RA6M5\Debug\SparkFun_ThingPlus_RA6M5.elf"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="C:\Users\alex.brudner\Documents\GitHub\ArduinoCore-renesas\extras\e2studioProjects\SparkFun_ThingPlus_RA6M5\Debug\SparkFun_ThingPlus_RA6M5.elf"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/SparkFun_ThingPlus_RA6M5.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="SparkFun_ThingPlus_RA6M5"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+    <booleanAttribute key="org.eclipse.debug.core.ATTR_FORCE_SYSTEM_CONSOLE_ENCODING" value="false"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/SparkFun_ThingPlus_RA6M5"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>

extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/fsp_to_arduino.sh

@@ -0,0 +1,162 @@
+#!/bin/bash
+
+CORE_PATH=$(pwd -P)/../../../
+TARGET=THINGPLUS_RA6M5
+
+# this part changes the makefile generated by e2studio (removing ra_gen from the build)
+# then it cleans the build and re-build all again
+
+if ! grep -q "#\-include ra_gen\/subdir.mk" ./Debug/makefile; then
+    sed -i 's/-include ra_gen\/subdir.mk/#-include ra_gen\/subdir.mk/g' ./Debug/makefile
+    echo "not commented"
+else 
+    echo "already commented!"    
+fi
+
+mkdir -p fsp_patched
+cd fsp_patched
+ln -s ../../../fsp/ra/ .
+cd ..
+
+set +e
+find ra -type f | xargs -I{} cp fsp_patched/{} {}
+set -e
+
+cd Debug
+make clean
+make -j$(nproc)
+cd ..
+echo `pwd`
+
+
+LIBRARY=`find . | grep "\.a$"`
+
+echo Copying ${LIBRARY} to ${CORE_PATH}/variants/${TARGET}/libs/libfsp.a
+if [ ! -d ${CORE_PATH}/variants/${TARGET}/libs ]
+then
+    mkdir -p ${CORE_PATH}/variants/${TARGET}/libs
+fi
+cp ${LIBRARY} ${CORE_PATH}/variants/${TARGET}/libs/libfsp.a
+
+LINKER_SCRIPTS=`find . | grep "\.ld$"`
+# cp ${LINKER_SCRIPTS} ${CORE_PATH}/variants/${TARGET}/
+
+#-----------------------------------------------------------------------
+# TEMPORARY CHANGE - TO BE REMOVED - used to copy temporary some genrated files
+# those are the files that have been removed from the build at the beginning
+# and now are copied to a temporary path (so that we can continue to build)
+#------------------------------------------------------------------------
+if [ ! -d ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files ]
+then
+    mkdir -p ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files
+fi
+
+cp ./ra_gen/*.c ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/
+# no more need of the following file
+if test -f "${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/vector_data.c"; then
+    echo "removed"
+    rm ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/vector_data.c
+fi
+if test -f "${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/elc_data.c"; then
+    echo "removed"
+    rm ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/elc_data.c
+fi
+if test -f "${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/hal_data.c"; then
+    echo "removed"
+    rm ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/hal_data.c
+fi
+
+#-------------------------------------------------------------------------
+
+
+FILE_MK=`find . | grep all/subdir.mk`
+
+CCCOMMAND=`cat $FILE_MK | grep \$\(file | cut -f2 -d","`
+
+echo $CCCOMMAND
+
+DEFINES=()
+INCLUDES=()
+FLAGS=()
+
+OIFS=$IFS
+IFS=' '
+tokens=$CCCOMMAND
+for x in $tokens
+do
+    if [[ $x == -D* ]]; then DEFINES+=( $x ); fi
+    if [[ $x == -I* ]]; then INCLUDES+=( $x ); fi
+    if [[ $x == -m* ]]; then FLAGS+=( $x ); fi
+    if [[ $x == -f* ]]; then FLAGS+=( $x ); fi
+    if [[ $x == -W* ]]; then FLAGS+=( $x ); fi
+done
+IFS=$OIFS
+
+# Clean files
+rm ${CORE_PATH}/variants/${TARGET}/defines.txt
+rm ${CORE_PATH}/variants/${TARGET}/includes.txt
+rm ${CORE_PATH}/variants/${TARGET}/cflags.txt
+rm ${CORE_PATH}/variants/${TARGET}/cxxflags.txt
+
+for value in "${DEFINES[@]}"
+do
+    echo $value >> ${CORE_PATH}/variants/${TARGET}/defines.txt
+done
+
+echo ${INCLUDES[@]}
+
+if [ ! -d ${CORE_PATH}/variants/${TARGET}/includes/ ]
+then
+    mkdir -p ${CORE_PATH}/variants/${TARGET}/includes/
+else
+    rm -r ${CORE_PATH}/variants/${TARGET}/includes/*
+fi
+
+for value in "${INCLUDES[@]}"
+do
+    INCLUDE_PATH=`echo $value | cut -f2 -d"\"" | cut -f1 -d"\""`
+    echo $INCLUDE_PATH
+    PROJECT_FOLDER=$(pwd -P)
+    # temporarily, copy everything staring with "ra_" in variant/includes/ , everything with ra in core folder
+    if [[ $INCLUDE_PATH == */ra* ]]; then
+        INCLUDE_PATH_REL=`echo ${INCLUDE_PATH} | sed 's/.*ra//'`
+        INCLUDE_PATH_REL=ra${INCLUDE_PATH_REL}
+        #cp -r --parent $INCLUDE_PATH ${CORE_PATH}/variants/${TARGET}/includes/
+        echo "-iwithprefixbefore/variants/${TARGET}/includes/$INCLUDE_PATH_REL" >> ${CORE_PATH}/variants/${TARGET}/includes.txt
+    fi
+    #rel_path=`echo $value | sed -e "s#-I$PWD#-iwithprefixbefore/fsp#g"`
+    #echo $rel_path >> ${CORE_PATH}/variants/${TARGET}/includes.txt
+
+    # TODO: check how many include folders are generated and if it makes sense to track them manually
+done
+
+rm -rf ${CORE_PATH}/variants/${TARGET}/includes/ra/*
+rm -rf ${CORE_PATH}/variants/${TARGET}/includes/ra_gen/*
+
+RA_INCLUDES=`find ra/ -iname *.h`
+cp --parent $RA_INCLUDES ${CORE_PATH}/variants/${TARGET}/includes/
+
+RA_INCLUDES=`find ra_gen/ -iname *.h`
+cp --parent $RA_INCLUDES ${CORE_PATH}/variants/${TARGET}/includes/
+
+RA_INCLUDES=`find ra_cfg/ -iname *.h`
+cp --parent $RA_INCLUDES ${CORE_PATH}/variants/${TARGET}/includes/
+
+if test -f "${CORE_PATH}/variants/${TARGET}/elc_defines.h"; then
+    echo "${CORE_PATH}/variants/${TARGET}/elc_defines.h exists. -> deleting it"
+    rm "${CORE_PATH}/variants/${TARGET}/elc_defines.h"
+fi
+
+ELC_TABLE=`find ra/ | grep bsp_elc.h`
+ELC_ENTRIES=`cat ${ELC_TABLE} | grep "ELC_EVENT" | cut -f1 -d "="`
+for entry in $ELC_ENTRIES
+do
+    #echo "$entry"
+    echo "#define $entry $entry" >> ${CORE_PATH}/variants/${TARGET}/elc_defines.h
+done
+
+for value in "${FLAGS[@]}"
+do
+    echo $value >> ${CORE_PATH}/variants/${TARGET}/cflags.txt
+    echo $value >> ${CORE_PATH}/variants/${TARGET}/cxxflags.txt
+done

extras/package.sh

@@ -15,7 +15,7 @@ echo $VERSION
 #portenta
 
 VARIANT=portenta
-EXCLUDE_TAGS=--exclude-tag-all=.unor4_only
+EXCLUDE_TAGS="--exclude-tag-all=.unor4_only --exclude-tag-all=.exclude_portenta"
 
 FILENAME=ArduinoCore-renesas_$VARIANT-$VERSION.tar.bz2
 
@@ -25,6 +25,7 @@ git checkout platform.txt
 sed -i 's/minima./#minima./g' boards.txt
 sed -i 's/unor4wifi./#unor4wifi./g' boards.txt
 sed -i 's/muxto./#muxto./g' boards.txt
+sed -i 's/thingplus_ra6m5./#thingplus_ra6m5./g' boards.txt
 sed -i 's/Arduino Renesas fsp Boards/Arduino Renesas Portenta Boards/g' platform.txt
 
 CORE_BASE=`basename $PWD`
@@ -57,6 +58,7 @@ git checkout platform.txt
 
 sed -i 's/portenta_c33./#portenta_c33./g' boards.txt
 sed -i 's/muxto./#muxto./g' boards.txt
+sed -i 's/thingplus_ra6m5./#thingplus_ra6m5./g' boards.txt
 sed -i 's/Arduino Renesas fsp Boards/Arduino Renesas UNO R4 Boards/g' platform.txt
 
 CORE_BASE=`basename $PWD`
@@ -75,7 +77,41 @@ cat package_renesas_${VERSION}_index.json.tmp |
 sed "s/%%VERSION%%/${VERSION}/" |
 sed "s/%%FILENAME_UNO%%/${FILENAME}/" |
 sed "s/%%CHECKSUM_UNO%%/${CHKSUM}/" |
-sed "s/%%SIZE_UNO%%/${SIZE}/" > package_renesas_${VERSION}_index.json
+sed "s/%%SIZE_UNO%%/${SIZE}/" > package_renesas_${VERSION}_index.json.tmp
+
+# SparkFun Thing Plus RA6M5
+
+VARIANT=thingplus
+EXCLUDE_TAGS="--exclude-tag-all=.unor4_only --exclude-tag-all=.thingplus_exclude"
+
+FILENAME=ArduinoCore-renesas_$VARIANT-$VERSION.tar.bz2
+
+git checkout boards.txt
+git checkout platform.txt
+
+sed -i 's/minima./#minima./g' boards.txt
+sed -i 's/unor4wifi./#unor4wifi./g' boards.txt
+sed -i 's/muxto./#muxto./g' boards.txt
+sed -i 's/portenta_c33./#portenta_c33./g' boards.txt
+sed -i 's/Arduino Renesas fsp Boards/SparkFun Renesas Thing Plus Boards/g' platform.txt
+
+CORE_BASE=`basename $PWD`
+cd ..
+tar $EXCLUDE_TAGS --exclude='*.vscode*' --exclude='*.tar.*' --exclude='*.json*' --exclude '*.git*' --exclude='*e2studio*' --exclude='*extras*' -cjhvf $FILENAME $CORE_BASE
+cd -
+
+mv ../$FILENAME .
+
+CHKSUM=`sha256sum $FILENAME | awk '{ print $1 }'`
+SIZE=`wc -c $FILENAME | awk '{ print $1 }'`
+
+cat package_renesas_${VERSION}_index.json.tmp |
+# sed "s/%%BUILD_NUMBER%%/${BUILD_NUMBER}/" |
+# sed "s/%%BUILD_NUMBER%%/${CURR_TIME_SED}/" |
+sed "s/%%VERSION%%/${VERSION}/" |
+sed "s/%%FILENAME_THINGPLUS%%/${FILENAME}/" |
+sed "s/%%CHECKSUM_THINGPLUS%%/${CHKSUM}/" |
+sed "s/%%SIZE_THINGPLUS%%/${SIZE}/" > package_renesas_${VERSION}_index.json
 
 cat package_renesas_${VERSION}_index.json
 

extras/package_index.json.template

@@ -204,6 +204,161 @@
         }
       ]
     },
+    {
+      "name": "sparkfun",
+      "maintainer": "SparkFun Electronics",
+      "websiteURL": "http://SparkFun.com/",
+      "email": "TechSupport@SparkFun.com",
+      "help": {
+        "online": "http://learn.sparkfun.com/tutorials/installing-arduino-ide/board-add-ons-with-arduino-board-manager"
+      },
+      "platforms": [
+        {
+          "name": "SparkFun Renesas Boards",
+          "architecture": "sparkfun_renesas",
+          "version": "%%VERSION%%",
+          "category": "Contributed",
+          "url": "http://downloads.arduino.cc/cores/staging/%%FILENAME_THINGPLUS%%",
+          "archiveFileName": "%%FILENAME_THINGPLUS%%",
+          "checksum": "SHA-256:%%CHECKSUM_THINGPLUS%%",
+          "size": "%%SIZE_THINGPLUS%%",
+          "help": {
+            "online": "https://github.com/arduino/ArduinoCore-renesas/issues"
+          },
+          "boards": [
+            {
+              "name": "SparkFun Thing Plus RA6M5"
+            }
+          ],
+          "toolsDependencies": [
+            {
+              "packager": "arduino",
+              "name": "openocd",
+              "version": "0.11.0-arduino2"
+            },
+            {
+              "packager": "arduino",
+              "name": "arm-none-eabi-gcc",
+              "version": "7-2017q4"
+            },
+            {
+              "packager": "arduino",
+              "version": "0.11.0-arduino5",
+              "name": "dfu-util"
+            },
+            {
+              "packager": "arduino",
+              "version": "1.9.1-arduino5",
+              "name": "bossac"
+            }
+          ],
+          "discoveryDependencies": [
+            {
+              "packager": "builtin",
+              "name": "dfu-discovery"
+            }
+          ]
+        }
+      ],
+      "tools": [
+        {
+          "name": "dfu-util",
+          "version": "0.11.0-arduino5",
+          "systems": [
+            {
+              "host": "i386-apple-darwin11",
+              "url": "http://downloads.arduino.cc/tools/dfu-util-0.11-arduino5-darwin_amd64.tar.gz",
+              "archiveFileName": "dfu-util-0.11-arduino5-darwin_amd64.tar.gz",
+              "size": "72429",
+              "checksum": "SHA-256:9e576c6e44f54b1e921a43ea77bcc08ec99e0e4e0905f4b9acf9ab2c979f0a22"
+            },
+            {
+              "host": "arm-linux-gnueabihf",
+              "url": "http://downloads.arduino.cc/tools/dfu-util-0.11-arduino5-linux_arm.tar.gz",
+              "archiveFileName": "dfu-util-0.11-arduino5-linux_arm.tar.gz",
+              "size": "2512819",
+              "checksum": "SHA-256:acd4bd283fd408515279a44dd830499ad37b0767e8f2fde5c27e878ded909dc3"
+            },
+            {
+              "host": "aarch64-linux-gnu",
+              "url": "http://downloads.arduino.cc/tools/dfu-util-0.11-arduino5-linux_arm64.tar.gz",
+              "archiveFileName": "dfu-util-0.11-arduino5-linux_arm64.tar.gz",
+              "size": "2607592",
+              "checksum": "SHA-256:b3f46a65da0c2fed2449dc5a3351c3c74953a868aa7f8d99ba2bb8c418344fe9"
+            },
+            {
+              "host": "x86_64-linux-gnu",
+              "url": "http://downloads.arduino.cc/tools/dfu-util-0.11-arduino5-linux_amd64.tar.gz",
+              "archiveFileName": "dfu-util-0.11-arduino5-linux_amd64.tar.gz",
+              "size": "2283425",
+              "checksum": "SHA-256:96c64c278561af806b585c123c85748926ad02b1aedc07e5578ca9bee2be0d2a"
+            },
+            {
+              "host": "i686-linux-gnu",
+              "url": "http://downloads.arduino.cc/tools/dfu-util-0.11-arduino5-linux_386.tar.gz",
+              "archiveFileName": "dfu-util-0.11-arduino5-linux_386.tar.gz",
+              "size": "2524406",
+              "checksum": "SHA-256:9a707692261e5710ed79a6d8a4031ffd0bfe1e585216569934346e9b2d68d0c2"
+            },
+            {
+              "host": "i686-mingw32",
+              "url": "http://downloads.arduino.cc/tools/dfu-util-0.11-arduino5-windows_386.tar.gz",
+              "archiveFileName": "dfu-util-0.11-arduino5-windows_386.tar.gz",
+              "size": "571340",
+              "checksum": "SHA-256:6451e16bf77600fe2436c8708ab4b75077c49997cf8bedf03221d9d6726bb641"
+            }
+          ]
+        },
+        {
+          "name": "bossac",
+          "version": "1.9.1-arduino5",
+          "systems": [
+            {
+              "host": "i386-apple-darwin11",
+              "url": "http://downloads.arduino.cc/tools/bossac-1.9.1-arduino5-osx.tar.gz",
+              "archiveFileName": "bossac-1.9.1-arduino5-osx.tar.gz",
+              "size": "47862",
+              "checksum": "SHA-256:c76eae00874a44265029b452303fb355e9ffa006e7ba214ca7ae01b1416867da"
+            },
+            {
+              "host": "aarch64-linux-gnu",
+              "url": "http://downloads.arduino.cc/tools/bossac-1.9.1-arduino5-linuxaarch64.tar.gz",
+              "archiveFileName": "bossac-1.9.1-arduino5-linuxaarch64.tar.gz",
+              "size": "442901",
+              "checksum": "SHA-256:f91dbbe90d57dd8074cd9b0ca7a2f5d41ee71bdf15e9bfd68bf2048a08e4a286"
+            },
+            {
+              "host": "arm-linux-gnueabihf",
+              "url": "http://downloads.arduino.cc/tools/bossac-1.9.1-arduino5-linuxarm.tar.gz",
+              "archiveFileName": "bossac-1.9.1-arduino5-linuxarm.tar.gz",
+              "size": "362365",
+              "checksum": "SHA-256:a0680ac5067ca8134f28fd7f86320d4c3099c782cefecd2e9b1edfde57f5947b"
+            },
+            {
+              "host": "x86_64-linux-gnu",
+              "url": "http://downloads.arduino.cc/tools/bossac-1.9.1-arduino5-linux64.tar.gz",
+              "archiveFileName": "bossac-1.9.1-arduino5-linux64.tar.gz",
+              "size": "399674",
+              "checksum": "SHA-256:ef80d247c431db2686a3e6728cb4897b708b92cd67687100c125684f3c12fc80"
+            },
+            {
+              "host": "i686-linux-gnu",
+              "url": "http://downloads.arduino.cc/tools/bossac-1.9.1-arduino5-linux32.tar.gz",
+              "archiveFileName": "bossac-1.9.1-arduino5-linux32.tar.gz",
+              "size": "385086",
+              "checksum": "SHA-256:d9c7ddab312bfc330ed7a98916ffa2c7a9c44798863ce1f4467fb240abc1830a"
+            },
+            {
+              "host": "i686-mingw32",
+              "url": "http://downloads.arduino.cc/tools/bossac-1.9.1-arduino5-windows.tar.gz",
+              "archiveFileName": "bossac-1.9.1-arduino5-windows.tar.gz",
+              "size": "1260650",
+              "checksum": "SHA-256:99e1982cf29600152e1c89b3389c1b4ce853201491ed52a12b4a327200cc6af0"
+            }
+          ]
+        }
+      ]
+    },
     {
       "name": "builtin",
       "maintainer": "Arduino",
@@ -279,4 +434,5 @@
       ]
     }
   ]
+
 }

libraries/BlockDevices/BlockDevice.cpp

@@ -17,7 +17,7 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifdef ARDUINO_PORTENTA_C33
+#if defined(ARDUINO_PORTENTA_C33) || defined(ARDUINO_THINGPLUS_RA6M5)
 
 #include <QSPIFlashBlockDevice.h>
 

libraries/BlockDevices/QSPIFlashBlockDevice.h

@@ -17,7 +17,7 @@
      License along with this library; if not, write to the Free Software
      Foundation, Inc.,51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA */
 /* ########################################################################## */
-#ifndef ARDUINO_QSIP_FLASH_BLOCK_DEVICE
+#ifndef ARDUINO_QSPI_FLASH_BLOCK_DEVICE
 #define ARDUINO_QSPI_FLASH_BLOCK_DEVICE
 
 

post_install.sh

@@ -9,12 +9,22 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="2341", MODE:="0666"
 EOF
 }
 
+sparkfun_renesas_core_rules () {
+    echo ""
+    echo "# Renesas based SparkFun bootloader UDEV rules"
+    echo ""
+cat <<EOF
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="1b4f", MODE:="0666"
+EOF
+}
+
 if [ "$EUID" -ne 0 ]
   then echo "Please run as root"
   exit
 fi
 
 arduino_renesas_core_rules > /etc/udev/rules.d/60-arduino-renesas.rules
+sparkfun_renesas_core_rules > /etc/udev/rules.d/60-sparkfun-renesas.rules
 
 # reload udev rules
 echo "Reload rules..."

variants/THINGPLUS_RA6M5/cflags.txt

@@ -0,0 +1,19 @@
+-mcpu=cortex-m33
+-mthumb
+-mfloat-abi=hard
+-mfpu=fpv5-sp-d16
+-fmessage-length=0
+-fsigned-char
+-ffunction-sections
+-fdata-sections
+-Wunused
+-Wuninitialized
+-Wall
+-Wextra
+-Wmissing-declarations
+-Wconversion
+-Wpointer-arith
+-Wshadow
+-Wlogical-op
+-Waggregate-return
+-Wfloat-equal

variants/THINGPLUS_RA6M5/cxxflags.txt

@@ -0,0 +1,19 @@
+-mcpu=cortex-m33
+-mthumb
+-mfloat-abi=hard
+-mfpu=fpv5-sp-d16
+-fmessage-length=0
+-fsigned-char
+-ffunction-sections
+-fdata-sections
+-Wunused
+-Wuninitialized
+-Wall
+-Wextra
+-Wmissing-declarations
+-Wconversion
+-Wpointer-arith
+-Wshadow
+-Wlogical-op
+-Waggregate-return
+-Wfloat-equal

variants/THINGPLUS_RA6M5/defines.txt

@@ -0,0 +1,3 @@
+-D_RA_CORE=CM33
+-D_RENESAS_RA_
+-D_RA_ORDINAL=1

variants/THINGPLUS_RA6M5/includes.txt

@@ -0,0 +1,12 @@
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra/arm/CMSIS_5/CMSIS/Core/Include
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra_gen
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc
+-iwithprefixbefore/variants/THINGPLUS_RA6M5/includes/ra_cfg/driver

variants/THINGPLUS_RA6M5/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h

@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

variants/THINGPLUS_RA6M5/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.5
+ * @date     02. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 6U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

variants/THINGPLUS_RA6M5/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h

@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.2
+ * @date     25. May 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

variants/THINGPLUS_RA6M5/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h

@@ -0,0 +1,352 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.3
+ * @date     03. February 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  (((BASE) & MPU_RBAR_BASE_Msk) | \
+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

variants/THINGPLUS_RA6M5/includes/ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h

@@ -0,0 +1,206 @@
+/******************************************************************************
+ * @file     pac_armv81.h
+ * @brief    CMSIS PAC key functions for Armv8.1-M PAC extension
+ * @version  V1.0.0
+ * @date     23. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef PAC_ARMV81_H
+#define PAC_ARMV81_H
+
+
+/* ###################  PAC Key functions  ########################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
+  \brief    Functions that access the PAC keys.
+  @{
+ */
+
+#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
+
+/**
+  \brief   read the PAC key used for privileged mode
+  \details Reads the PAC key stored in the PAC_KEY_P registers.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_p_0\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_p_1\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_p_2\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_p_3\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for privileged mode
+  \details writes the given PAC key to the PAC_KEY_P registers.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_p_0, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_p_1, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_p_2, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_p_3, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   read the PAC key used for unprivileged mode
+  \details Reads the PAC key stored in the PAC_KEY_U registers.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_u_0\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_u_1\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_u_2\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_u_3\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for unprivileged mode
+  \details writes the given PAC key to the PAC_KEY_U registers.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_u_0, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_u_1, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_u_2, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_u_3, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+
+/**
+  \brief   read the PAC key used for privileged mode (non-secure)
+  \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_p_0_ns\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_p_1_ns\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_p_2_ns\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_p_3_ns\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for privileged mode (non-secure)
+  \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_p_0_ns, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_p_1_ns, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_p_2_ns, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_p_3_ns, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   read the PAC key used for unprivileged mode (non-secure)
+  \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_u_0_ns\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_u_1_ns\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_u_2_ns\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_u_3_ns\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for unprivileged mode (non-secure)
+  \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_u_0_ns, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_u_1_ns, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_u_2_ns, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_u_3_ns, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
+
+#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
+
+/*@} end of CMSIS_Core_PacKeyFunctions */
+
+
+#endif /* PAC_ARMV81_H */