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‎Makefile

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
#This is a simple wrapper which hides cmake (for convenience, and from non-expert end users).
1+
# This is a simple wrapper which hides cmake (for convenience, and from non-expert end users).
22
#
33
# It supports the targets:
44
# 'make' - builds everything (all libaries/executables)
@@ -15,12 +15,14 @@
1515
#
1616
# 'make BUILD_TYPE=debug VERBOSE=1'
1717

18-
#Default build type
19-
# Possible values:
20-
# release_pgo #Perform a 2-stage build with profile-guided compiler optimization
21-
# release #Build with compiler optimization
22-
# debug #Build with debug info and no compiler optimization
23-
# strict #Build VPR with warnings treated as errors
18+
# Build type
19+
# Possible values (not case sensitive):
20+
# release #Build with compiler optimization (Default)
21+
# RelWithDebInfo #Build with debug info and compiler optimizations
22+
# debug #Build with debug info and no compiler optimization
23+
# Possible suffixes:
24+
# _pgo #Perform a 2-stage build with profile-guided compiler optimization
25+
# _strict #Build VPR with warnings treated as errors
2426
BUILD_TYPE ?= release
2527

2628
#Debugging verbosity enable

‎doc/src/tutorials/timing_analysis/index.rst

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,8 @@ Post-Implementation Timing Analysis
66
This tutorial describes how to perform static timing analysis (STA) on a circuit which has
77
been implemented by :ref:`VPR` using OpenSTA, an external timing analysis tool.
88

9+
A video of this tutorial can be found here: https://youtu.be/yihFJc7WOfE
10+
911
External timing analysis can be useful since VPR's timing analyzer (Tatum) does
1012
not support all timing constraints and does not provide a TCL interface to allow
1113
you to directly interrogate the timing graph. VPR also has limited support for

‎doc/src/vpr/command_line_usage.rst

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -416,9 +416,14 @@ Use the options below to override this default naming behaviour.
416416
.. option:: --write_placement_delay_lookup <file>
417417

418418
Writes the placement delay lookup to the specified file. Expects a file extension of either ``.capnp`` or ``.bin``.
419+
420+
.. option:: --read_initial_place_file <file>
421+
422+
Reads in the initial cluster-level placement (in :ref:`.place file format <vpr_place_file>`) from the specified file and uses it as the starting point for annealing improvement, instead of generating an initial placement internally.
423+
419424
.. option:: --write_initial_place_file <file>
420425

421-
Writes out the the placement chosen by the initial placement algorithm to the specified file.
426+
Writes out the clustered netlist placement chosen by the initial placement algorithm to the specified file, in :ref:`.place file format <vpr_place_file>`.
422427

423428
.. option:: --outfile_prefix <string>
424429

@@ -838,9 +843,9 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe
838843

839844
Controls how the placer handles blocks (of any type) during placement.
840845

841-
* ``<file.place>``: A path to a file listing the desired location of blocks in the netlist.
846+
* ``<file.place>``: A path to a file listing the desired location of clustered blocks in the netlist.
842847

843-
This place location file is in the same format as a :ref:`normal placement file <vpr_place_file>`, but does not require the first two lines which are normally at the top of a placement file that specify the netlist file, netlist ID, and array size.
848+
This place location file is in the same format as a :ref:`.place file <vpr_place_file>`, but does not require the first two lines which are normally at the top of a placement file that specify the netlist file, netlist ID, and array size.
844849

845850
**Default:** ````.
846851

‎libs/libarchfpga/src/arch_check.cpp

Lines changed: 24 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -159,20 +159,18 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
159159
//Check from the pb_type's delay annotations match the model
160160
//
161161
// This ensures that the pb_types' delay annotations are consistent with the model
162-
for (int i = 0; i < pb_type->num_annotations; ++i) {
163-
const t_pin_to_pin_annotation* annot = &pb_type->annotations[i];
164-
165-
if (annot->type == E_ANNOT_PIN_TO_PIN_DELAY) {
162+
for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
163+
if (annotation.type == E_ANNOT_PIN_TO_PIN_DELAY) {
166164
//Check that any combinational delays specified match the 'combinational_sinks_ports' in the model
167165

168-
if (annot->clock) {
166+
if (annotation.clock) {
169167
//Sequential annotation, check that the clock on the specified port matches the model
170168

171169
//Annotations always put the pin in the input_pins field
172-
VTR_ASSERT(annot->input_pins);
173-
for (const std::string& input_pin : vtr::split(annot->input_pins)) {
170+
VTR_ASSERT(annotation.input_pins);
171+
for (const std::string& input_pin : vtr::split(annotation.input_pins)) {
174172
InstPort annot_port(input_pin);
175-
for (const std::string& clock : vtr::split(annot->clock)) {
173+
for (const std::string& clock : vtr::split(annotation.clock)) {
176174
InstPort annot_clock(clock);
177175

178176
//Find the model port
@@ -187,34 +185,34 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
187185
if (model_port != nullptr) break;
188186
}
189187
if (model_port == nullptr) {
190-
archfpga_throw(get_arch_file_name(), annot->line_num,
188+
archfpga_throw(get_arch_file_name(), annotation.line_num,
191189
"Failed to find port '%s' on '%s' for sequential delay annotation",
192190
annot_port.port_name().c_str(), annot_port.instance_name().c_str());
193191
}
194192

195193
//Check that the clock matches the model definition
196194
std::string model_clock = model_port->clock;
197195
if (model_clock.empty()) {
198-
archfpga_throw(get_arch_file_name(), annot->line_num,
196+
archfpga_throw(get_arch_file_name(), annotation.line_num,
199197
"<pb_type> timing-annotation/<model> mismatch on port '%s' of model '%s', model specifies"
200198
" no clock but timing annotation specifies '%s'",
201199
annot_port.port_name().c_str(), model.name, annot_clock.port_name().c_str());
202200
}
203201
if (model_port->clock != annot_clock.port_name()) {
204-
archfpga_throw(get_arch_file_name(), annot->line_num,
202+
archfpga_throw(get_arch_file_name(), annotation.line_num,
205203
"<pb_type> timing-annotation/<model> mismatch on port '%s' of model '%s', model specifies"
206204
" clock as '%s' but timing annotation specifies '%s'",
207205
annot_port.port_name().c_str(), model.name, model_clock.c_str(), annot_clock.port_name().c_str());
208206
}
209207
}
210208
}
211209

212-
} else if (annot->input_pins && annot->output_pins) {
210+
} else if (annotation.input_pins && annotation.output_pins) {
213211
//Combinational annotation
214-
VTR_ASSERT_MSG(!annot->clock, "Combinational annotations should have no clock");
215-
for (const std::string& input_pin : vtr::split(annot->input_pins)) {
212+
VTR_ASSERT_MSG(!annotation.clock, "Combinational annotations should have no clock");
213+
for (const std::string& input_pin : vtr::split(annotation.input_pins)) {
216214
InstPort annot_in(input_pin);
217-
for (const std::string& output_pin : vtr::split(annot->output_pins)) {
215+
for (const std::string& output_pin : vtr::split(annotation.output_pins)) {
218216
InstPort annot_out(output_pin);
219217

220218
//Find the input model port
@@ -227,7 +225,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
227225
}
228226

229227
if (model_port == nullptr) {
230-
archfpga_throw(get_arch_file_name(), annot->line_num,
228+
archfpga_throw(get_arch_file_name(), annotation.line_num,
231229
"Failed to find port '%s' on '%s' for combinational delay annotation",
232230
annot_in.port_name().c_str(), annot_in.instance_name().c_str());
233231
}
@@ -237,7 +235,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
237235
auto e = model_port->combinational_sink_ports.end();
238236
auto iter = std::find(b, e, annot_out.port_name());
239237
if (iter == e) {
240-
archfpga_throw(get_arch_file_name(), annot->line_num,
238+
archfpga_throw(get_arch_file_name(), annotation.line_num,
241239
"<pb_type> timing-annotation/<model> mismatch on port '%s' of model '%s', timing annotation"
242240
" specifies combinational connection to port '%s' but the connection does not exist in the model",
243241
model_port->name, model.name, annot_out.port_name().c_str());
@@ -276,8 +274,8 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
276274

277275
if (model_port->dir == IN_PORT) {
278276
//Sequential inputs must have a T_setup or T_hold
279-
if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) == nullptr
280-
&& find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) {
277+
if (!has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP)
278+
&& !has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD)) {
281279
std::stringstream msg;
282280
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
283281
msg << " port '" << model_port->name << "' of model '" << model.name << "',";
@@ -293,8 +291,8 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
293291

294292
if (!model_port->combinational_sink_ports.empty()) {
295293
//Sequential input with internal combinational connectsion it must also have T_clock_to_Q
296-
if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) == nullptr
297-
&& find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) {
294+
if (!has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX)
295+
&& !has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN)) {
298296
std::stringstream msg;
299297
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
300298
msg << " port '" << model_port->name << "' of model '" << model.name << "',";
@@ -313,8 +311,8 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
313311
} else {
314312
VTR_ASSERT(model_port->dir == OUT_PORT);
315313
//Sequential outputs must have T_clock_to_Q
316-
if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) == nullptr
317-
&& find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) {
314+
if (!has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX)
315+
&& !has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN)) {
318316
std::stringstream msg;
319317
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
320318
msg << " port '" << model_port->name << "' of model '" << model.name << "',";
@@ -330,8 +328,8 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
330328

331329
if (comb_connected_outputs.count(model_port->name)) {
332330
//Sequential output with internal combinational connectison must have T_setup/T_hold
333-
if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) == nullptr
334-
&& find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) {
331+
if (!has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP)
332+
&& !has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD)) {
335333
std::stringstream msg;
336334
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
337335
msg << " port '" << model_port->name << "' of model '" << model.name << "',";
@@ -352,7 +350,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
352350
//Check that combinationally connected inputs/outputs have combinational delays between them
353351
if (model_port->dir == IN_PORT) {
354352
for (const auto& sink_port : model_port->combinational_sink_ports) {
355-
if (find_combinational_annotation(pb_type, model_port->name, sink_port) == nullptr) {
353+
if (!has_combinational_annotation(pb_type, model_port->name, sink_port)) {
356354
std::stringstream msg;
357355
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
358356
msg << " port '" << model_port->name << "' of model '" << model.name << "',";

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