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lines changed Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- 7series_BRAM_DSP_carry.xml stereovision3.v common 2.87 vpr 72.69 MiB -1 -1 0.32 26404 4 0.08 -1 -1 35804 -1 -1 -1 11 0 -1 success v8.0.0-12999-gf153e4447-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4 .0 on Linux-5.15 .0-119 -generic x86_64 2025-06-12T17:00:21 goeders10 /home/chem3000/GitClones/vtr_pulls/vtr_ccl/ vtr-verilog-to-routing/vtr_flow/tasks 74436 11 2 303 283 2 114 35 7 7 49 CLB auto 33.4 MiB 1.15 577.007 408 947 108 584 255 72 .7 MiB 0.01 0.00 3.1717 3.1717 -180.982 -3.1717 2.89952 0.12 0.000180919 0.000138049 0.00514751 0.00458797 -1 -1 -1 -1 40 911 27 1.34735e+06 1.18567e+06 152291. 3107.98 0.59 0.032835 0.0284564 6668 73471 -1 385 12 297 988 127228 60728 2.91111 2.8252 -221.503 -2.91111 -2.452 -0.04 215465. 4397.25 0.02 0.02 0.04 -1 -1 0.02 0.0099349 0.00925009
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+ 7series_BRAM_DSP_carry.xml stereovision3.v common 5.34 vpr 74.72 MiB -1 -1 0.36 34424 5 0.10 -1 -1 36444 -1 -1 -1 11 0 -1 success v8.0.0-13075-g071b36c3f release VTR_ASSERT_LEVEL=3 GNU 13.3 .0 on Linux-6.8 .0-58 -generic x86_64 2025-06-16T21:07:45 srivatsan-Precision-Tower-5810 /home/alex/ vtr-verilog-to-routing 76512 11 2 303 283 2 114 35 7 7 49 CLB auto 35.3 MiB 1.64 569.025 404 890 113 545 232 74 .7 MiB 0.02 0.00 3.1717 3.1717 -181.811 -3.1717 2.89952 0.27 0.00043783 0.000361293 0.0101279 0.00875535 -1 -1 -1 -1 44 529 20 1.34735e+06 1.18567e+06 177202. 3616.36 1.77 0.144934 0.119762 6848 92556 -1 373 9 263 823 105258 48434 2.83816 2.83244 -218.271 -2.83816 -2.452 -0.04 257836. 5261.96 0.06 0.03 0.13 -1 -1 0.06 0.0166581 0.0151597
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