Merge pull request verilog-to-routing#2715 from verilog-to-routing/temp_update_noc_bw_mlp_arch

Update NoC link bandwidth in the MLP architecture file

Author: vaughnbetz

vtr_flow/arch/noc/mesh_noc_topology/mlp_benchmarks.stratixiv_arch.timing_with_a_embedded_4x4_mesh_noc_topology.xml

@@ -48449,7 +48449,7 @@
     </switchblock>
   </switchblocklist>
   <!-- The NoC routers were added to the FPGA device in the fixed layout section-->
-  <noc link_bandwidth="1e6" router_latency="1e-9" link_latency="1e-9" noc_router_tile_name="noc_router_adapter">
+  <noc link_bandwidth="1.28e11" router_latency="1e-9" link_latency="1e-9" noc_router_tile_name="noc_router_adapter">
 	  <mesh startx="0" starty="0" endx="340" endy="270" size="4"/>
   </noc>
 </architecture>