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AlexandreSingerAlexandreSinger
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Merge pull request verilog-to-routing#3128 from AlexandreSinger/feature-ci-task-list-checker
[CI] Revived Simple Missing Strong Tests
2 parents 3b984a7 + 16e857e commit 6e534fd

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‎dev/vtr_test_suite_verifier/test_suites_info.json

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{
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"name": "vtr_reg_strong",
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"ignored_tasks": [
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"strong_ap/gen_mass_report",
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"strong_cluster_seed_type",
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"strong_router_heap",
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"strong_verify_rr_graph_3d",
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"strong_xilinx_support"
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{
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"name": "vtr_reg_strong_odin",
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"ignored_tasks": [
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"strong_pack_modes",
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"strong_xilinx_support",
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"strong_router_heap",
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"strong_cluster_seed_type"

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cluster_seed_type/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_outputs num_memories num_mult vpr_revision vpr_status max_vpr_mem num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height device_limiting_resources pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time
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EArch.xml diffeq2.v common_-vpr_cluster_seed_type_blend 18.11 0.01 6864 37 0.00 -1 -1 32620 -1 -1 18 66 96 0 5 41106a6 success 53772 787 599 456 185 16 16 mult_36 0.32 7121 0.75 11.911 -741.335 -11.911 46 11188 24 1.21132e+07 2.95009e+06 786648. 3072.85 15.33 9045 31 13.5401 -906.141 -13.5401 0 0 1.01260e+06 3955.47 1.12
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EArch.xml diffeq2.v common_-vpr_cluster_seed_type_timing 15.14 0.01 6868 37 0.01 -1 -1 32532 -1 -1 18 66 96 0 5 41106a6 success 53732 787 599 455 185 16 16 mult_36 0.32 7198 0.76 11.4848 -739.971 -11.4848 54 11301 23 1.21132e+07 2.95009e+06 903890. 3530.82 12.53 8323 25 13.0434 -878.425 -13.0434 0 0 1.17254e+06 4580.24 0.88
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EArch.xml diffeq2.v common_-vpr_cluster_seed_type_max_inputs 12.92 0.01 6860 37 0.00 -1 -1 32620 -1 -1 17 66 96 0 5 41106a6 success 53880 787 599 455 184 16 16 mult_36 0.32 6117 0.80 11.466 -708.661 -11.466 54 9641 22 1.21132e+07 2.8962e+06 903890. 3530.82 10.13 8279 23 13.069 -865.82 -13.069 0 0 1.17254e+06 4580.24 1.04
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EArch.xml diffeq2.v common_-vpr_cluster_seed_type_max_pins 27.71 0.01 6852 37 0.01 -1 -1 32576 -1 -1 18 66 96 0 5 41106a6 success 54008 787 599 455 185 16 16 mult_36 0.32 6437 0.76 11.3718 -717.272 -11.3718 68 10365 35 1.21132e+07 2.95009e+06 1.14646e+06 4478.35 25.01 7906 25 13.2966 -878.535 -13.2966 0 0 1.41383e+06 5522.77 1.00
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EArch.xml diffeq2.v common_-vpr_cluster_seed_type_max_input_pins 16.35 0.01 6868 37 0.00 -1 -1 32528 -1 -1 18 66 96 0 5 41106a6 success 54008 787 599 455 185 16 16 mult_36 0.34 6434 0.82 11.3848 -718.622 -11.3848 56 10729 22 1.21132e+07 2.95009e+06 941869. 3679.18 13.66 8756 25 13.2369 -890.17 -13.2369 0 0 1.19778e+06 4678.85 0.91
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EArch.xml diffeq2.v common_-vpr_cluster_seed_type_blend2 14.27 0.01 6912 37 0.00 -1 -1 32576 -1 -1 18 66 96 0 5 41106a6 success 53944 787 599 455 185 16 16 mult_36 0.32 7191 0.75 11.5639 -729.893 -11.5639 52 9933 27 1.21132e+07 2.95009e+06 870783. 3401.49 11.63 8660 26 12.9662 -879.727 -12.9662 0 0 1.14646e+06 4478.35 0.91
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
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EArch.xml diffeq2.v common_--cluster_seed_type_blend 15.64 vpr 71.20 MiB -1 -1 0.22 24604 5 0.10 -1 -1 37404 -1 -1 19 66 0 5 success v8.0.0-12967-gc1fb06539f release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-09T22:53:51 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 72904 66 96 778 595 1 450 186 16 16 256 mult_36 auto 32.1 MiB 0.68 6675.15 3790 44176 15630 27997 549 71.2 MiB 0.69 0.01 13.022 12.0577 -746.776 -12.0577 12.0577 0.56 0.00288518 0.00263477 0.267106 0.245392 -1 -1 -1 -1 44 10345 47 1.21132e+07 3.00399e+06 751766. 2936.59 11.60 1.22018 1.12261 27376 157980 -1 8309 20 4168 8066 1469857 405043 13.2731 13.2731 -895.158 -13.2731 0 0 979172. 3824.89 0.04 0.32 0.14 -1 -1 0.04 0.0762285 0.0707975
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EArch.xml diffeq2.v common_--cluster_seed_type_timing 10.43 vpr 70.56 MiB -1 -1 0.39 24604 5 0.09 -1 -1 37404 -1 -1 19 66 0 5 success v8.0.0-12967-gc1fb06539f release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-09T22:53:51 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 72256 66 96 778 595 1 450 186 16 16 256 mult_36 auto 31.3 MiB 0.38 6015.41 3710 44176 13016 30202 958 70.6 MiB 0.34 0.01 12.9223 11.8949 -747.083 -11.8949 11.8949 0.32 0.00143517 0.0012914 0.135016 0.122517 -1 -1 -1 -1 62 8716 30 1.21132e+07 3.00399e+06 1.04918e+06 4098.38 7.36 0.813199 0.741128 30184 211102 -1 6880 22 3560 7162 1408754 410607 12.634 12.634 -828.912 -12.634 0 0 1.29183e+06 5046.22 0.05 0.32 0.19 -1 -1 0.05 0.0871991 0.0811534
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EArch.xml diffeq2.v common_--cluster_seed_type_max_inputs 11.71 vpr 70.27 MiB -1 -1 0.39 24432 5 0.10 -1 -1 37024 -1 -1 19 66 0 5 success v8.0.0-12967-gc1fb06539f release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-09T22:53:51 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 71956 66 96 778 595 1 449 186 16 16 256 mult_36 auto 31.1 MiB 0.50 6049.48 3706 42056 11301 30225 530 70.3 MiB 0.33 0.01 12.7131 11.8714 -738.04 -11.8714 11.8714 0.32 0.00165678 0.00150511 0.130607 0.118453 -1 -1 -1 -1 52 8409 27 1.21132e+07 3.00399e+06 870783. 3401.49 8.56 0.872075 0.794724 28652 182587 -1 7517 22 2952 5864 1148041 333936 13.03 13.03 -852.047 -13.03 0 0 1.14646e+06 4478.35 0.05 0.29 0.16 -1 -1 0.05 0.0863763 0.0803076
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EArch.xml diffeq2.v common_--cluster_seed_type_max_pins 11.70 vpr 71.11 MiB -1 -1 0.39 24604 5 0.16 -1 -1 37404 -1 -1 18 66 0 5 success v8.0.0-12967-gc1fb06539f release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-09T22:53:51 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 72820 66 96 778 595 1 451 185 16 16 256 mult_36 auto 32.0 MiB 0.78 6111.16 3608 38057 10673 26480 904 71.1 MiB 0.56 0.01 12.9974 12.169 -743.127 -12.169 12.169 0.55 0.00297039 0.00273122 0.225542 0.207494 -1 -1 -1 -1 60 8768 20 1.21132e+07 2.95009e+06 1.01260e+06 3955.47 7.39 1.13909 1.05271 29928 206364 -1 7378 21 2689 5009 919027 265897 12.9752 12.9752 -842.836 -12.9752 0 0 1.26536e+06 4942.82 0.05 0.24 0.19 -1 -1 0.05 0.0830927 0.0772513
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EArch.xml diffeq2.v common_--cluster_seed_type_max_input_pins 17.18 vpr 71.23 MiB -1 -1 0.39 24688 5 0.16 -1 -1 37280 -1 -1 18 66 0 5 success v8.0.0-12967-gc1fb06539f release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-09T22:53:51 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 72944 66 96 778 595 1 451 185 16 16 256 mult_36 auto 31.9 MiB 0.82 6031.25 4018 37005 11119 25078 808 71.2 MiB 0.54 0.01 12.9974 11.878 -748.86 -11.878 11.878 0.56 0.00305051 0.00280179 0.220974 0.203118 -1 -1 -1 -1 52 9339 48 1.21132e+07 2.95009e+06 870783. 3401.49 12.89 1.20118 1.1032 28652 182587 -1 7851 20 3011 5787 1219158 361977 12.9938 12.9938 -855.957 -12.9938 0 0 1.14646e+06 4478.35 0.05 0.28 0.16 -1 -1 0.05 0.0762721 0.0707323
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EArch.xml diffeq2.v common_--cluster_seed_type_blend2 14.36 vpr 71.31 MiB -1 -1 0.21 24608 5 0.10 -1 -1 37280 -1 -1 19 66 0 5 success v8.0.0-12967-gc1fb06539f release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-09T22:53:51 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 73020 66 96 778 595 1 450 186 16 16 256 mult_36 auto 32.2 MiB 0.68 6783.04 3667 45236 13440 30583 1213 71.3 MiB 0.64 0.01 13.8108 11.9163 -742.181 -11.9163 11.9163 0.55 0.00286798 0.00263061 0.271337 0.249766 -1 -1 -1 -1 50 9502 49 1.21132e+07 3.00399e+06 843554. 3295.13 10.40 1.36875 1.26045 28144 172338 -1 7445 21 3518 7008 1194202 366119 13.1722 13.1722 -849.129 -13.1722 0 0 1.08719e+06 4246.82 0.04 0.28 0.15 -1 -1 0.04 0.0815325 0.0757153

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

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regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering
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regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver
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regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver
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regression_tests/vtr_reg_strong/strong_ap/gen_mass_report
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regression_tests/vtr_reg_strong/strong_absorb_buffers
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regression_tests/vtr_reg_strong/strong_analysis_only
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regression_tests/vtr_reg_strong/strong_bidir
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regression_tests/vtr_reg_strong/strong_clock_buf
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regression_tests/vtr_reg_strong/strong_clock_modeling
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regression_tests/vtr_reg_strong/strong_clock_pll
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regression_tests/vtr_reg_strong/strong_cluster_seed_type
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regression_tests/vtr_reg_strong/strong_constant_outputs
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regression_tests/vtr_reg_strong/strong_custom_grid
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regression_tests/vtr_reg_strong/strong_custom_pin_locs

‎vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt

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regression_tests/vtr_reg_strong_odin/strong_pack
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regression_tests/vtr_reg_strong_odin/strong_pack_and_place
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regression_tests/vtr_reg_strong_odin/strong_pack_disable
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#regression_tests/vtr_reg_strong_odin/strong_pack_modes
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regression_tests/vtr_reg_strong_odin/strong_pack_modes
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regression_tests/vtr_reg_strong_odin/strong_place
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regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method
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regression_tests/vtr_reg_strong_odin/strong_place_delay_model

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