Merge pull request verilog-to-routing#3130 from verilog-to-routing/docs-run-vtr-includes

Updating VTR Docs -include Command

Author: AlexandreSinger

doc/src/vtr/run_vtr_flow.rst

@@ -90,6 +90,13 @@ Enable Synlig tool with the ``-DSYNLIG_SYSTEMVERILOG=ON`` compile flag for the P
 
 Will run the VTR flow (default configuration) with Yosys frontend using Parmys plugin as partial mapper. To utilize the Parmys plugin, the ``-DYOSYS_PARMYS_PLUGIN=ON`` compile flag should be passed while building the VTR project with Yosys as a frontend.
 
+.. code-block:: bash
+
+    # Using the Parmys (Partial Mapper for Yosys) plugin as partial mapper with include files
+    ./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -include <path/to/include/directory>/*.v*
+
+Will run the VTR flow (default configuration) with Yosys frontend using Parmys plugin as partial mapper. In addition to the main circuit passed in with the architecture, it will also pass in every HDL file with the specified file type within the include directory.
+
 Detailed Command-line Options
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -123,6 +130,15 @@ Detailed Command-line Options
       * ``vpr``
 
     **Default:** ``vpr``
+    
+.. option:: -include <path_to_file(s)>/*.<file_type(s)>
+
+    List of include files to a benchmark circuit 
+    (pass to VTR frontends as a benchmark design set).
+    
+    Include files can be any file supported by yosys+parmys (normally .v or .vh files).
+    
+    The include directory should not contain the circuit passed in with the architecture.
 
 .. option:: -power
 

vtr_flow/scripts/python_libs/vtr/parmys/parmys.py

@@ -151,7 +151,7 @@ def run(
             Circuit file to optimize
 
         include_files :
-            list of header files
+            List of include files to a benchmark circuit. Passed in by run_vtr_flow with -include
 
         output_netlist :
             File name to output the resulting circuit to