Pinned Loading

1. MagicLS MagicLS Public

   Magic Logic Synthesis

   Verilog

2. veriSIMPLER veriSIMPLER Public

   veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing

   Verilog 1 1

3. SIMPLEST-MAGIC SIMPLEST-MAGIC Public

   SIMPLEST MAGIC:SynthesIs and MaPping of in-memory Logic Executed through area-aware heuriSTic methods

4. panhomyoung/phyLS panhomyoung/phyLS Public

   A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

   C++ 36 7