[BugFix] Fix H100 CuTeDSL full-run edge cases#1
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The README declares SM90 GPUs as supported, but the Engram grad-w reduce kernel hard-coded four persistent batches and asserted that the persistent block count was divisible by four. That assumption is not true for all SM90 parts. For example, H100 PCIe exposes 114 SMs, so the CUDA/CuTeDSL full test path can fail before code generation reaches the actual kernel logic. Choose the largest batch count up to four that divides the persistent block count. This keeps the original four-batch layout when it is valid, while allowing other SM90 block counts to use the same persistent kernel shape without tripping the launch-time assertion. Co-authored-by: dingsg <shengge.ding@enflame-tech.com>
Full H100/CuTeDSL coverage exercises MoE routing shapes where the generated work loops are rounded up to alignment or warp-size boundaries. The logical tensors remain sized by the real hidden dimension, scaling-factor dimension, and token-topk count. The expand-to-fused kernel previously iterated over aligned hidden and scaling-factor extents and wrote every lane into the destination tensors. For tail dimensions this can address columns outside the real tensor shape, especially with TMA-aligned column-major scaling-factor layouts. The fused mapping kernel also used a Select expression whose inactive arm could still expose an out-of-range topk_idx load to code generation, and its fallback allocation estimate rounded the per-expert alignment upper bound down to an alignment multiple. Guard aligned expand stores with the real hidden/scaling-factor extents, initialize the shared cumsum buffer for all threads, avoid the speculative out-of-range topk load, and reserve a rounded-up per-expert alignment upper bound before trimming with the synchronized expert counts. Co-authored-by: dingsg <shengge.ding@enflame-tech.com>
The full H100/CuTeDSL correctness run covers token and hidden sizes that do not land exactly on the kernel tile, scaling-factor block, or E5M6 packing granularity. Those edge tiles exposed two independent quantization issues. First, cast-back and lossless/per-token cast kernels could load or store scaling factors for padded token/channel blocks. The same edge condition also applied to packed E5M6 output rows and columns, where the final tile may not contain a full logical token row or hidden group. Second, per-token scale generation used in_config.dtype as the absmax fragment dtype. That dtype describes the input tensor storage, not the reduction accumulator. For BF16 and narrow quantization paths, keeping absmax in the input dtype can round or overflow the scale path before the final output cast, producing byte mismatches against the PyTorch reference. Guard scale loads/stores and packed E5M6 stores with the real token/channel extents, keep invalid scale lanes zero-initialized, and use FP32 fragments for per-token absmax reductions before computing the reciprocal scale. Co-authored-by: dingsg <shengge.ding@enflame-tech.com>
Full H100/CuTeDSL validation needs to run correctness and benchmark coverage under xdist while preserving host GPU pinning, separating TileLang compile caches, and collecting enough per-worker information to debug late failures without re-running the whole suite blindly. Keep externally provided CUDA_VISIBLE_DEVICES instead of overwriting it in every xdist worker, allow per-worker TileLang cache directories, add optional per-test CUDA synchronization for benchmark/debug runs, and write optional trace/failure reports controlled by environment variables. Benchmark-only sweeps also need a way to record new results before a baseline file exists. Add an opt-in missing-baseline override and make the timer backend configurable so local H100 runs can use CUDA events when CUPTI is not the desired backend. Add a small run_cutedsl_tests.sh wrapper that rebuilds a local TileLang checkout, selects correctness/benchmark/all modes, stores logs and JSONL output under .test-logs, and leaves local virtualenv/log directories ignored. Co-authored-by: dingsg <shengge.ding@enflame-tech.com>
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Context
This PR collects the TileKernels-side fixes needed after running the full H100 CuTeDSL correctness and benchmark coverage with a local TileLang CuTeDSL backend.
The failures were not tied to a single benchmark configuration. They came from broader edge cases that full coverage exposes more reliably:
Changes
Engram
num_batches = 4assumption inengram_grad_w_reduce_kernel.pywith the largest batch count up to four that divides the persistent block count.MoE
expand_to_fusedwrites with the real hidden and scaling-factor extents when iterating over aligned loop sizes.topk_idxloads in the aligned tail ofget_fused_mapping.Quantization
in_config.dtypeas the accumulator dtype.Test and benchmark tooling
run_cutedsl_tests.shfor one-command CuTeDSL correctness, benchmark, or combined full runs.CUDA_VISIBLE_DEVICESunder xdist instead of always overriding it.TK_BENCHMARK_BACKEND.Why these are TileKernels fixes
These changes address TileKernels assumptions about launch geometry, tensor bounds, allocation sizing, and reduction accumulator dtype. They are not CuTeDSL-version-specific workarounds:
Validation
Validated on NVIDIA H100 PCIe with the local TileLang CuTeDSL backend after the corresponding TileLang CuTeDSL fixes:
git diff --check HEAD~4..HEAD.venv-tk-test/bin/python -m ruff check ...on changed Python files.venv-tk-test/bin/python -m py_compile ...on changed Python filesbash -n run_cutedsl_tests.shCommit Structure
[BugFix][Engram] Support non-divisible SM90 block counts[BugFix][MoE] Guard fused mapping edge tiles[BugFix][Quant] Guard scale tails and FP32 absmax[Test] Add reusable CuTeDSL full-run controls