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Technological University Dublin
- Dublin
- https://14sea.github.io/
- in/14sea
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Cyclone_CRAM_Mapper
Cyclone_CRAM_Mapper PublicA physical-aware routing codec for Intel Cyclone IV FPGAs.
Python 5
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see_neorv32_run_linux
see_neorv32_run_linux PublicBooting nommu Linux (kernel 6.6.83) on a NEORV32 RV32IMC soft-core FPGA
C++ 10
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zynq-xpart
zynq-xpart PublicLive Xilinx Partial-Reconfiguration (XPART) demo on EBAZ4205 / Zynq-7010 (XC7Z010): DFX module hot-swap + prjxray/ICAP live LUT-INIT surgery, PS-hosted with a NEORV32 soft-core RoT. Continuation of…
C 2
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zynq-agentctl
zynq-agentctl PublicAgent (Claude) controlling live FPGA fabric state on EBAZ4205 (Zynq-7010): runtime LUT-INIT edit via Linux /dev/mem HWICAP ICAP, no reset, as a perceive-decide-act-verify loop
Python
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neorv32_rot
neorv32_rot PublicHardware Root of Trust PoC on NEORV32 — SHA-256 Wishbone peripheral + bitstream-anchored measured boot (Phase A CRTM). Fork of see_neorv32_run_linux.
C++
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rot_tpu_handoff
rot_tpu_handoff PublicCross-repo orchestrator + patches + silicon captures for CRTM closed-loop bring-up on AX301 (Cyclone IV E). Plan B asmiblock SPI master + ALTREMOTE_UPDATE direct-primitive. 35 patches, Phase 3+8 si…
Python
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