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undefined_identifier error is reported for generic interface used as function param #2091

@taichi-ishitani

Description

@taichi-ishitani

Veryl compiler reports undefined_identifier error during analyzing the code below.

interface a_if::<T: type> {
  var ready: logic;
  var valid: logic;
  var data : T    ;

  modport master {
    ready: input ,
    valid: output,
    data : output,
  }

  modport slave {
    ..converse(master)
  }
}

proto package b_proto_pkg {
  const WIDTH: u32;
  struct b_struct {
    b: logic<WIDTH>,
  }
}

package b_pkg::<W: u32> for b_proto_pkg {
  const WIDTH: u32 = W;
  struct b_struct {
    b: logic<WIDTH>,
  }
}

interface c_if::<B_PKG: b_proto_pkg> {
  var ready: logic;
  var valid: logic;
  var data : B_PKG::b_struct;

  function connect_if(
    aif: modport a_if::<B_PKG::b_struct>::slave,
  ) {
    aif.ready = ready;
    valid     = aif.valid;
    data.b    = aif.data.b;
  }

  modport master {
    ready     : input ,
    valid     : output,
    data      : output,
    connect_if: import,
  }
}
Error: undefined_identifier (link)

  × B_PKG is undefined
    ╭─[/home/taichi/workspace/temp/veryl/39/a.veryl:41:17]
 40 │     valid     = aif.valid;
 41 │     data.b    = aif.data.b;
    ·                 ─────┬────
    ·                      ╰── Error location
 42 │   }
    ╰────
  help:

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