Why initial
#2075
Replies: 2 comments
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For FPGA, initial block with initial begin
$readmemh("data.hex", array_reg);
endVeryl supports refs: #140 |
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Thanks for clarifying such subtle detail |
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Why initial blocks exist in the first place, if I can't use them to initialize variables i.e assignments?
Maybe this is part of the language design, but I don't understand the reason behind it.
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