ISCA Tokyo (Fourth Workshop on Open-Source Computer Architecture Research (OSCAR))

[nblei]

This might be a nice opportunity to highlight Veryl, especially since it is in Tokyo.

Abstracts are due on 5 May. I think an introduction to Veryl HDL plus a practical demonstration (e.g., a parametric OOO processor implementation) could be a nice presentation.

Excerpts from the call:

Topics of interest of the OSCAR workshop include, but are not limited to:
• Open-source processors (CPU, GPU, AI processors…)
• Open-source accelerators (programmable, configurable, fixed-function…)
• Open-source components (e.g., caches, busses, network-on-chip, peripherals, sensors…)
• CAD tools and methodologies for design, integration, and full-system simulation of open-source architectures
• Artificial intelligence (AI) methods for the design of open-source architectures and components
• Software aspects of heterogeneous component integration
• Security, reliability, and verification of open-source architectures and components
• Infrastructures specialized for FPGA prototyping or chip designs of open-source architectures
• Design experiences with the use of open-source components, tools, and platforms
• Discussion of case studies, applications that benefit from open-source architecture research
Workshop Format: OSCAR will feature a mix of invited talks and presentations selected from submissions to this call for
participation. Abstracts should be submitted in PDF format (max 2 pages) and must include a title, author names and
affiliations, and the contact author’s e-mail address. Including the URL of the release website for the open-source
contribution described in the abstract is recommended. Submissions of early work and position papers are encouraged.
Workshop submissions do not preclude future publications. While no formal proceedings are planned, the OSCAR
organizers may explore the possibility a journal special issue featuring a subset of the contributions, after the workshop.
Organizers:
• Luca Carloni, Columbia University (Chair)
• Pradip Bose, IBM
• Margaret Martonosi, Princeton University
• Sophia Shao, University of California at Berkeley
• Caroline Trippel, Stanford University

[dalance]

Thank you for your suggestion. It looks good opportunity.
Surely, it seems easy to participate for me because I don't need travel expenses and 1 day registration is available, if I can't accept the expense help from my company.

I already plan to give a presentation about Veryl in a workshop of VLSI symposium 2025.
So I need to consider about the content to avoid duplication.
If I have an actual processor implementation in Veryl, it is good, but I don't have enough time to do it since now.
There are some implementations by some people, I may be to able to introduce them.

[taichi-ishitani]

an actual processor implementation in Veryl

I can re-write my RISC-V core written in SystemVerilog to Veryl for this purpose.

[nblei]

https://www.overleaf.com/read/phrbwkpxbzff#ddae86

I've created a draft abstract.

I'll email you two a link with edit access.

[dalance]

Thanks! I'll read it later.

[nblei]

Any chance to take a look?

[dalance]

I wrote some review comments. Could you see it?

[nblei]

Yes. It looks good. I've also modified the code blocks a bit to get it to two pages.

I think we can improve this paragraph, though:

Optimized Syntax: Veryl simplifies common hardware de-
sign patterns while removing ambiguities and unsynthesizable
constructs. The language guarantees synthesizability, ensuring
consistency between simulation results and final implemen-
tation. For example, Veryl eliminates the need for separate
blocking and non-blocking assignment operators, instead in-
ferring the correct behavior based on context.

Its not obvious to me that the example is relevant. Is this actually showing consistency between simulation results and final implementation? Perhaps there is a different example to give, or perhaps we change the preceeding sentence?

[dalance]

How about focusing "simplifies common hardware design patterns"?
Taichi pointed out to add description about omitting clock and reset in the review comment.
So I think it can be inserted to this section.

Optimized Syntax: Veryl simplifies common hardware de-
sign patterns while removing ambiguities and unsynthesizable
constructs. For example, if a module contains only one clock and one reset,
the Veryl compiler automatically infers their usage without requiring explicit declaration.
At the same time, it allows explicit handling of multiple clocks when needed.
This approach simplifies the description of common patterns while ensuring expressiveness for rare cases.

[nblei]

That's a great suggestion. If you approve, I'll submit this two-pager to HotCRP.

…

On Tue, Apr 22, 2025 at 10:46 AM Naoya Hatta ***@***.***> wrote: How about focusing "simplifies common hardware design patterns"? Taichi pointed out to add description about omitting clock and reset in the review comment. So I think it can be inserted to this section. Optimized Syntax: Veryl simplifies common hardware de- sign patterns while removing ambiguities and unsynthesizable constructs. For example, if a module contains only one clock and one reset, the Veryl compiler automatically infers their usage without requiring explicit declaration. At the same time, it allows explicit handling of multiple clocks when needed. This approach simplifies the description of common patterns while ensuring expressiveness for rare cases. — Reply to this email directly, view it on GitHub <https://urldefense.com/v3/__https://github.com/orgs/veryl-lang/discussions/1525*discussioncomment-12911601__;Iw!!DZ3fjg!8TbXKAfZkC0Arhp4VbrR_ZJ7WeWuGMrhkwU3aYpJLYYDWagElXaHXGqi2Xf7jtao48LA60_pIqRnRVdhCnK14jjVFSQB$>, or unsubscribe <https://urldefense.com/v3/__https://github.com/notifications/unsubscribe-auth/AFAMUBECAIYTKY62ZMLZX6T22ZI4ZAVCNFSM6AAAAAB3BPAGDWVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTEOJRGE3DAMI__;!!DZ3fjg!8TbXKAfZkC0Arhp4VbrR_ZJ7WeWuGMrhkwU3aYpJLYYDWagElXaHXGqi2Xf7jtao48LA60_pIqRnRVdhCnK14mGhrTd-$> . You are receiving this because you authored the thread.Message ID: ***@***.***>

-- Very Respectfully, Nathaniel Bleier ***@***.*** 773-531-8229 (Cell)

[dalance]

Yes, of course.

[nblei]

I'll be attending the conference and the workshop, so I can give the talk. Are either of you two planning on attending?

[dalance]

Congratulations on your acceptance! I'm only attending the workshop, and I'm looking forward to hearing your talk.

[nblei]

Naoya, you are of course more than welcome to deliver the talk if you would like!

[dalance]

To be honest, I'm preparing for a presentation at a VLSI Symposium workshop the week before OSCAR, which is likely to take up a lot of time. So, it would be greatly appreciated if you could handle this presentation.

[nblei]

Yeah, no problem.