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dalancedalance
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Merge pull request #1587 from taichi-ishitani/axi_if
Remove unnecessary prefix from struct types and add some typedef
2 parents c9ab618 + 864731b commit d803fc1

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2 files changed

+104
-85
lines changed

2 files changed

+104
-85
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‎crates/std/veryl/src/axi_if/axi_if.veryl‎

Lines changed: 56 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -47,19 +47,19 @@ pub interface axi4_if::<PKG: axi4_prototype> {
4747
import PKG::*;
4848

4949
//Write address channel
50-
var awvalid : logic ;
51-
var awready : logic ;
52-
var awaddr : addr_t ;
53-
var awsize : size_t ;
54-
var awburst : burst_t ;
55-
var awcache : axi4_config::awcache_bits ;
56-
var awprot : axi4_config::axprot_bits ;
57-
var awid : id_t ;
58-
var awlen : num_bursts_t ; //AXI3: 4 bits, AXI4: 8 bits
59-
var awlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
60-
var awqos : logic <4>; //Only AXI4
61-
var awregion: logic <4>; //Only AXI4
62-
var awuser : awuser_t ; //Only AXI4
50+
var awvalid : logic ;
51+
var awready : logic ;
52+
var awaddr : addr_t ;
53+
var awsize : size_t ;
54+
var awburst : burst_t ;
55+
var awcache : wcache_t ;
56+
var awprot : proto_t ;
57+
var awid : id_t ;
58+
var awlen : num_bursts_t; //AXI3: 4 bits, AXI4: 8 bits
59+
var awlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
60+
var awqos : qos_t ; //Only AXI4
61+
var awregion: region_t ; //Only AXI4
62+
var awuser : awuser_t ; //Only AXI4
6363

6464
//Write data channel
6565
var wvalid: logic ;
@@ -77,19 +77,19 @@ pub interface axi4_if::<PKG: axi4_prototype> {
7777
var buser : buser_t; //Only AXI4
7878

7979
//Read address channel
80-
var arvalid : logic ;
81-
var arready : logic ;
82-
var araddr : addr_t ;
83-
var arsize : size_t ;
84-
var arburst : burst_t ;
85-
var arcache : axi4_config::arcache_bits ;
86-
var arprot : axi4_config::axprot_bits ;
87-
var arid : id_t ;
88-
var arlen : num_bursts_t ; //AXI3: 4 bits, AXI4: 8 bits
89-
var arlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
90-
var arqos : logic <4>; //Only AXI4
91-
var arregion: logic <4>; //Only AXI4
92-
var aruser : aruser_t ; //Only AXI4
80+
var arvalid : logic ;
81+
var arready : logic ;
82+
var araddr : addr_t ;
83+
var arsize : size_t ;
84+
var arburst : burst_t ;
85+
var arcache : rcache_t ;
86+
var arprot : proto_t ;
87+
var arid : id_t ;
88+
var arlen : num_bursts_t; //AXI3: 4 bits, AXI4: 8 bits
89+
var arlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
90+
var arqos : qos_t ; //Only AXI4
91+
var arregion: region_t ; //Only AXI4
92+
var aruser : aruser_t ; //Only AXI4
9393

9494
//Read data channel
9595
var rvalid: logic ;
@@ -235,7 +235,6 @@ pub interface axi4_if::<PKG: axi4_prototype> {
235235
}
236236

237237
modport read_master {
238-
239238
arvalid : output,
240239
arready : input ,
241240
araddr : output,
@@ -326,16 +325,16 @@ pub interface axi3_if::<PKG: axi3_prototype> {
326325
import PKG::*;
327326

328327
//Write address channel
329-
var awvalid: logic ;
330-
var awready: logic ;
331-
var awaddr : addr_t ;
332-
var awsize : size_t ;
333-
var awburst: burst_t ;
334-
var awcache: axi3_config::axcache_bits;
335-
var awprot : axi3_config::axprot_bits ;
336-
var awid : id_t ;
337-
var awlen : num_bursts_t ; //AXI3: 4 bits, AXI4: 8 bits
338-
var awlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
328+
var awvalid: logic ;
329+
var awready: logic ;
330+
var awaddr : addr_t ;
331+
var awsize : size_t ;
332+
var awburst: burst_t ;
333+
var awcache: cache_t ;
334+
var awprot : proto_t ;
335+
var awid : id_t ;
336+
var awlen : num_bursts_t; //AXI3: 4 bits, AXI4: 8 bits
337+
var awlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
339338

340339
//Write data channel
341340
var wvalid: logic ;
@@ -352,16 +351,16 @@ pub interface axi3_if::<PKG: axi3_prototype> {
352351
var bid : id_t ;
353352

354353
//Read address channel
355-
var arvalid: logic ;
356-
var arready: logic ;
357-
var araddr : addr_t ;
358-
var arsize : size_t ;
359-
var arburst: burst_t ;
360-
var arcache: axi3_config::axcache_bits;
361-
var arprot : axi3_config::axprot_bits ;
362-
var arid : id_t ;
363-
var arlen : num_bursts_t ; //AXI3: 4 bits, AXI4: 8 bits
364-
var arlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
354+
var arvalid: logic ;
355+
var arready: logic ;
356+
var araddr : addr_t ;
357+
var arsize : size_t ;
358+
var arburst: burst_t ;
359+
var arcache: cache_t ;
360+
var arprot : proto_t ;
361+
var arid : id_t ;
362+
var arlen : num_bursts_t; //AXI3: 4 bits, AXI4: 8 bits
363+
var arlock : lock_t ; //AXI3: 2 bits, AXI4: 1 bit
365364

366365
//Read data channel
367366
var rvalid: logic ;
@@ -588,11 +587,11 @@ pub interface axi4_lite_if::<PKG: axi4_lite_prototype> {
588587
import PKG::*;
589588

590589
//Write address channel
591-
var awvalid: logic ;
592-
var awready: logic ;
593-
var awaddr : addr_t ;
594-
var awprot : axi4_lite_config::axprot_bits;
595-
var awid : id_t ;
590+
var awvalid: logic ;
591+
var awready: logic ;
592+
var awaddr : addr_t ;
593+
var awprot : proto_t;
594+
var awid : id_t ;
596595

597596
//Write data channel
598597
var wvalid: logic ;
@@ -607,11 +606,11 @@ pub interface axi4_lite_if::<PKG: axi4_lite_prototype> {
607606
var bid : id_t ;
608607

609608
//Read address channel
610-
var arvalid: logic ;
611-
var arready: logic ;
612-
var araddr : addr_t ;
613-
var arprot : axi4_lite_config::axprot_bits;
614-
var arid : id_t ;
609+
var arvalid: logic ;
610+
var arready: logic ;
611+
var araddr : addr_t ;
612+
var arprot : proto_t;
613+
var arid : id_t ;
615614

616615
//Read data channel
617616
var rvalid: logic ;

‎crates/std/veryl/src/axi_if/axi_pkg.veryl‎

Lines changed: 48 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@ pub proto package axi4_prototype {
44
const DATA_WIDTH_BYTES: u32;
55
const NUM_BURSTS_LEN : u32;
66
const LOCK_LEN : u32;
7+
const QOS_LEN : u32;
8+
const REGION_LEN : u32;
79
const ID_LENGTH : u32;
810
const AWUSER_LENGTH : u32;
911
const WUSER_LENGTH : u32;
@@ -16,16 +18,21 @@ pub proto package axi4_prototype {
1618
type strb_t ;
1719
type num_bursts_t;
1820
type lock_t ;
21+
type qos_t ;
22+
type region_t ;
1923
type id_t ;
2024
type awuser_t ;
2125
type wuser_t ;
2226
type buser_t ;
2327
type aruser_t ;
2428
type ruser_t ;
2529

26-
type size_t ;
27-
type burst_t;
28-
type resp_t ;
30+
type size_t ;
31+
type burst_t ;
32+
type wcache_t;
33+
type rcache_t;
34+
type proto_t ;
35+
type resp_t ;
2936
}
3037

3138
///### AXI3 bus package prototype
@@ -45,6 +52,8 @@ pub proto package axi3_prototype {
4552

4653
type size_t ;
4754
type burst_t;
55+
type cache_t;
56+
type proto_t;
4857
type resp_t ;
4958
}
5059

@@ -56,6 +65,7 @@ pub proto package axi4_lite_prototype {
5665
type data_t ;
5766
type strb_t ;
5867
type id_t ;
68+
type proto_t ;
5969
type resp_t ;
6070
}
6171

@@ -80,23 +90,23 @@ pub package axi4_config {
8090
}
8191

8292
struct awcache_bits {
83-
AWCACHE_ALLOCATE : logic,
84-
AWCACHE_OTHER_ALLOCATE: logic,
85-
AWCACHE_MODIFIABLE : logic,
86-
AWCACHE_BUFFERABLE : logic,
93+
allocate : logic,
94+
other_allocate: logic,
95+
modifiable : logic,
96+
bufferable : logic,
8797
}
8898

8999
struct arcache_bits {
90-
ARCACHE_OTHER_ALLOCATE: logic,
91-
ARCACHE_ALLOCATE : logic,
92-
ARCACHE_MODIFIABLE : logic,
93-
ARCACHE_BUFFERABLE : logic,
100+
other_allocate: logic,
101+
allocate : logic,
102+
modifiable : logic,
103+
bufferable : logic,
94104
}
95105

96106
struct axprot_bits {
97-
AXPROT_INSTRUCTION_ACCESS: logic,
98-
AXPROT_NON_SECURE : logic,
99-
AXPROT_PRIVILEGED : logic,
107+
instruction_access: logic,
108+
non_secure : logic,
109+
privileged : logic,
100110
}
101111

102112
enum resp_variants: logic<2> {
@@ -114,6 +124,8 @@ pub package axi4_pkg::<ADDR_W: u32, DATA_W_BYTES: u32, ID_W: u32, AWUSER_W: u32,
114124
const DATA_WIDTH_BYTES: u32 = DATA_W_BYTES;
115125
const NUM_BURSTS_LEN : u32 = 8;
116126
const LOCK_LEN : u32 = 1;
127+
const QOS_LEN : u32 = 4;
128+
const REGION_LEN : u32 = 4;
117129
const ID_LENGTH : u32 = ID_W;
118130
const AWUSER_LENGTH : u32 = AWUSER_W;
119131
const WUSER_LENGTH : u32 = WUSER_W;
@@ -126,16 +138,21 @@ pub package axi4_pkg::<ADDR_W: u32, DATA_W_BYTES: u32, ID_W: u32, AWUSER_W: u32,
126138
type strb_t = logic<DATA_WIDTH_BYTES> ;
127139
type num_bursts_t = logic<NUM_BURSTS_LEN> ;
128140
type lock_t = logic<LOCK_LEN> ;
141+
type qos_t = logic<QOS_LEN> ;
142+
type region_t = logic<REGION_LEN> ;
129143
type id_t = logic<ID_LENGTH> ;
130144
type awuser_t = logic<AWUSER_LENGTH> ;
131145
type wuser_t = logic<WUSER_LENGTH> ;
132146
type buser_t = logic<BUSER_LENGTH> ;
133147
type aruser_t = logic<ARUSER_LENGTH> ;
134148
type ruser_t = logic<RUSER_LENGTH> ;
135149

136-
type size_t = axi4_config::axsize_variants ;
137-
type burst_t = axi4_config::axburst_variants;
138-
type resp_t = axi4_config::resp_variants ;
150+
type size_t = axi4_config::axsize_variants ;
151+
type burst_t = axi4_config::axburst_variants;
152+
type wcache_t = axi4_config::awcache_bits ;
153+
type rcache_t = axi4_config::arcache_bits ;
154+
type proto_t = axi4_config::axprot_bits ;
155+
type resp_t = axi4_config::resp_variants ;
139156

140157
}
141158

@@ -160,16 +177,16 @@ pub package axi3_config {
160177
}
161178

162179
struct axcache_bits {
163-
AXCACHE_WRITE_ALLOCATE: logic,
164-
AXCACHE_READ_ALLOCATE : logic,
165-
AXCACHE_CACHEABLE : logic,
166-
AXCACHE_BUFFERABLE : logic,
180+
write_allocate: logic,
181+
read_allocate : logic,
182+
cacheable : logic,
183+
bufferable : logic,
167184
}
168185

169186
struct axprot_bits {
170-
AXPROT_INSTRUCTION_ACCESS: logic,
171-
AXPROT_NON_SECURE : logic,
172-
AXPROT_PRIVILEGED : logic,
187+
instruction_access: logic,
188+
non_secure : logic,
189+
privileged : logic,
173190
}
174191

175192
enum resp_variants: logic<2> {
@@ -198,16 +215,18 @@ pub package axi3_pkg::<ADDR_W: u32, DATA_W_BYTES: u32, ID_W: u32> for axi3_proto
198215

199216
type size_t = axi3_config::axsize_variants ;
200217
type burst_t = axi3_config::axburst_variants;
218+
type cache_t = axi3_config::axcache_bits ;
219+
type proto_t = axi3_config::axprot_bits ;
201220
type resp_t = axi3_config::resp_variants ;
202221
}
203222

204223
///### AXI4-Lite configuration definitions
205224
pub package axi4_lite_config {
206225

207226
struct axprot_bits {
208-
AXPROT_INSTRUCTION_ACCESS: logic,
209-
AXPROT_NON_SECURE : logic,
210-
AXPROT_PRIVILEGED : logic,
227+
instruction_access: logic,
228+
non_secure : logic,
229+
privileged : logic,
211230
}
212231

213232
enum resp_variants: logic<2> {
@@ -231,6 +250,7 @@ pub package axi4_lite_pkg::<ADDR_W: u32, DATA_W_BYTES: u32, ID_W: u32> for axi4_
231250

232251
type id_t = logic<ID_LENGTH>;
233252

234-
type resp_t = axi4_lite_config::resp_variants;
253+
type proto_t = axi4_lite_config::axprot_bits ;
254+
type resp_t = axi4_lite_config::resp_variants;
235255

236256
}

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