From 4f8abac8209edd8241c9783b7b3cc3f476ece389 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Thu, 26 Jun 2025 17:38:17 -0300 Subject: [PATCH 01/15] Added in yosys-slang as a submodule and configured it to build and install with vtr when enabled with the cmake parameter -DSLANG_SYSTEMVERILOG=ON --- .gitmodules | 3 + CMakeLists.txt | 5 +- libs/EXTERNAL/CMakeLists.txt | 183 ++++++++++++++++++++--------------- libs/EXTERNAL/yosys-slang | 1 + 4 files changed, 111 insertions(+), 81 deletions(-) create mode 160000 libs/EXTERNAL/yosys-slang diff --git a/.gitmodules b/.gitmodules index 48709ae2f4..b2b3b51fee 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,3 +13,6 @@ [submodule "libs/EXTERNAL/yosys"] path = libs/EXTERNAL/yosys url = https://github.com/YosysHQ/yosys.git +[submodule "libs/EXTERNAL/yosys-slang"] + path = libs/EXTERNAL/yosys-slang + url = https://github.com/povik/yosys-slang.git diff --git a/CMakeLists.txt b/CMakeLists.txt index 4fb30b2f9e..ca6c89e601 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -56,7 +56,8 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF) # Allow the user to enable building Yosys option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON) -option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF) +#option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF) +option(SLANG_SYSTEMVERILOG "Enable building and installing Yosys-Slang plugin for parsing SystemVerilog" OFF) set(VTR_VERSION_MAJOR 9) set(VTR_VERSION_MINOR 0) @@ -438,7 +439,7 @@ if(${WITH_ODIN}) endif() # handle cmake params to compile Yosys SystemVerilog/UHDM plugins -if(${SYNLIG_SYSTEMVERILOG}) +if(${SLANG_SYSTEMVERILOG}) # avoid compiling plugins in case the Parmys frontend is not active if(NOT ${WITH_PARMYS}) message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.") diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index e109b267bb..f8e69f809a 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -79,92 +79,117 @@ if (${WITH_PARMYS}) add_custom_target(yosys ALL DEPENDS ${YOSYS_BUILD_DIR}) - if (${SYNLIG_SYSTEMVERILOG}) - - set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog) - set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build) - set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins) - - ExternalProject_Add(surelog - # root directory for Surelog project - PREFIX "surelog" - - GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git - GIT_TAG v1.71 - GIT_PROGRESS TRUE - GIT_SHALLOW TRUE - - # setting source, build and install directories - SOURCE_DIR "${SURELOG_SOURCE_DIR}" - BUILD_IN_SOURCE FALSE - INSTALL_DIR "${SURELOG_BINARY_DIR}" - - # define Surelog cache values - CMAKE_CACHE_ARGS - "-DCMAKE_BUILD_TYPE:STRING=Release" - "-DCMAKE_INSTALL_PREFIX:PATH=${CMAKE_BINARY_DIR}" - "-DCMAKE_POSITION_INDEPENDENT_CODE:BOOL=ON" - "-DCMAKE_WARN_DEPRECATED:BOOL=OFF" - - # redirect logs to a logfile - LOG_BUILD ON - LOG_UPDATE ON - LOG_INSTALL ON - LOG_CONFIGURE OFF - LOG_OUTPUT_ON_FAILURE ON - - # dependency - DEPENDS yosys - ) - - # Synlig integration (manages Surelog and UHDM internally) - - # Synlig integration (manages Surelog and UHDM internally) - set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig) - - # Clone Synlig repository and ensure submodules are synced before building - ExternalProject_Add(synlig - PREFIX "synlig" - - # Clone the Synlig repository - GIT_REPOSITORY https://github.com/chipsalliance/synlig.git - GIT_TAG main - GIT_PROGRESS TRUE - GIT_SHALLOW TRUE + if (${SLANG_SYSTEMVERILOG}) + set(SLANG_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-slang) + set(SLANG_BUILD_DIR ${CMAKE_BINARY_DIR}/yosys-slang) + set(YOSYS_CONFIG_EXECUTABLE ${CMAKE_BINARY_DIR}/bin/yosys-config CACHE STRING "Path to the yosys-config helper" FORCE) + execute_process( + COMMAND git submodule update --init + WORKING_DIRECTORY ${SLANG_SRC_DIR} + ) + execute_process( + COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive git\ submodule\ update\ --init + WORKING_DIRECTORY ${SLANG_SRC_DIR} + ) + ExternalProject_Add( + yosys-slang + SOURCE_DIR ${SLANG_SRC_DIR} + BINARY_DIR ${SLANG_BUILD_DIR} + + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -DCMAKE_BUILD_TYPE=Release + -DYOSYS_CONFIG=${YOSYS_CONFIG_EXECUTABLE} + ${SLANG_SRC_DIR} + + BUILD_COMMAND ${CMAKE_COMMAND} --build ${SLANG_BUILD_DIR} -- -j${PROCESSOR_COUNT} + INSTALL_COMMAND ${CMAKE_COMMAND} --install ${SLANG_BUILD_DIR} + DEPENDS yosys + ) - # Set source and build directories - SOURCE_DIR "${SYNLIG_SOURCE_DIR}" - BUILD_IN_SOURCE FALSE - INSTALL_DIR " " + # set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog) + # set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build) + # set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins) + + # ExternalProject_Add(surelog + # # root directory for Surelog project + # PREFIX "surelog" + + # GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git + # GIT_TAG v1.71 + # GIT_PROGRESS TRUE + # GIT_SHALLOW TRUE + + # # setting source, build and install directories + # SOURCE_DIR "${SURELOG_SOURCE_DIR}" + # BUILD_IN_SOURCE FALSE + # INSTALL_DIR "${SURELOG_BINARY_DIR}" + + # # define Surelog cache values + # CMAKE_CACHE_ARGS + # "-DCMAKE_BUILD_TYPE:STRING=Release" + # "-DCMAKE_INSTALL_PREFIX:PATH=${CMAKE_BINARY_DIR}" + # "-DCMAKE_POSITION_INDEPENDENT_CODE:BOOL=ON" + # "-DCMAKE_WARN_DEPRECATED:BOOL=OFF" + + # # redirect logs to a logfile + # LOG_BUILD ON + # LOG_UPDATE ON + # LOG_INSTALL ON + # LOG_CONFIGURE OFF + # LOG_OUTPUT_ON_FAILURE ON + + # # dependency + # DEPENDS yosys + # ) + + # # Synlig integration (manages Surelog and UHDM internally) + + # # Synlig integration (manages Surelog and UHDM internally) + # set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig) + + # # Clone Synlig repository and ensure submodules are synced before building + # ExternalProject_Add(synlig + # PREFIX "synlig" + + # # Clone the Synlig repository + # GIT_REPOSITORY https://github.com/chipsalliance/synlig.git + # GIT_TAG main + # GIT_PROGRESS TRUE + # GIT_SHALLOW TRUE + + # # Set source and build directories + # SOURCE_DIR "${SYNLIG_SOURCE_DIR}" + # BUILD_IN_SOURCE FALSE + # INSTALL_DIR " " - # Sync submodules after cloning + # # Sync submodules after cloning - UPDATE_COMMAND git submodule update --init --recursive third_party/surelog - WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR} + # UPDATE_COMMAND git submodule update --init --recursive third_party/surelog + # WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR} - BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT} - INSTALL_COMMAND "" - CONFIGURE_COMMAND "" + # BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT} + # INSTALL_COMMAND "" + # CONFIGURE_COMMAND "" - # Pass necessary paths and set environment variables - CMAKE_CACHE_ARGS - "-DCMAKE_BUILD_TYPE:STRING=Release" - "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog" - "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys" - "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}" - "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build" - "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}" + # # Pass necessary paths and set environment variables + # CMAKE_CACHE_ARGS + # "-DCMAKE_BUILD_TYPE:STRING=Release" + # "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog" + # "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys" + # "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}" + # "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build" + # "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}" - LOG_BUILD ON - LOG_UPDATE ON - LOG_INSTALL ON - LOG_CONFIGURE OFF - LOG_OUTPUT_ON_FAILURE ON - - # Ensure dependencies like Yosys are built first - DEPENDS yosys # Ensure submodule sync runs before synlig build - ) + # LOG_BUILD ON + # LOG_UPDATE ON + # LOG_INSTALL ON + # LOG_CONFIGURE OFF + # LOG_OUTPUT_ON_FAILURE ON + + # # Ensure dependencies like Yosys are built first + # DEPENDS yosys # Ensure submodule sync runs before synlig build + # ) endif () endif () diff --git a/libs/EXTERNAL/yosys-slang b/libs/EXTERNAL/yosys-slang new file mode 160000 index 0000000000..76b83eb5b7 --- /dev/null +++ b/libs/EXTERNAL/yosys-slang @@ -0,0 +1 @@ +Subproject commit 76b83eb5b73ba871797e6db7bc5fed10af380be4 From efb1d876c228ec2a3505c49718a7cd6332530566 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Fri, 27 Jun 2025 14:16:46 -0300 Subject: [PATCH 02/15] Set up yosys-slang to be used as a frontend for Yosys --- vtr_flow/misc/yosys/synthesis.tcl | 38 +++++++++++-------- .../scripts/python_libs/vtr/parmys/parmys.py | 5 ++- .../f4pga_button_controller/config/config.txt | 2 +- .../f4pga_pulse_width_led/config/config.txt | 2 +- .../f4pga_timer/config/config.txt | 2 +- 5 files changed, 29 insertions(+), 20 deletions(-) diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 24bae6877c..2ef9e4256f 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -1,6 +1,7 @@ yosys -import plugin -i parmys +plugin -i slang yosys -import read_verilog -nomem2reg +/parmys/vtr_primitives.v @@ -24,17 +25,20 @@ if {[catch {set synlig $::env(synlig_exe_path)} err]} { # output file: ZZZ parmys_arch -a QQQ +if {$env(PARSER) == "slang" } { + puts "Using yosys-slang read_slang command" + read_slang XXX +} -if {$env(PARSER) == "surelog" } { - puts "Using Synlig read_uhdm command" - - exec $synlig -p "read_uhdm XXX" +#if {$env(PARSER) == "surelog" } { +# puts "Using Synlig read_uhdm command" +# exec $synlig -p "read_uhdm XXX" -} elseif {$env(PARSER) == "system-verilog" } { - puts "Using Synlig read_systemverilog " - exec $synlig -p "read_systemverilog XXX" - -} elseif {$env(PARSER) == "default" } { +#} elseif {$env(PARSER) == "system-verilog" } { +# puts "Using Synlig read_systemverilog " +# exec $synlig -p "read_systemverilog XXX" +# } +elseif {$env(PARSER) == "default" } { puts "Using Yosys read_verilog command" read_verilog -sv -nolatches XXX } else { @@ -74,13 +78,17 @@ techmap -map +/parmys/aldffe2dff.v opt -full # Separate options for Parmys execution (Verilog or SystemVerilog) -if {$env(PARSER) == "default"} { +if {$env(PARSER) == "default" || $env(PARSER) == "slang"} { # For Verilog, use -nopass for a simpler, faster flow parmys -a QQQ -nopass -c CCC YYY -} elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} { - # For Synlig SystemVerilog, run additional passes to handle complexity - parmys -a QQQ -c CCC YYY -} +} #elseif {$env(PARSER) == "slang"} { + # For Slang, run additional passes to handle complexity +# parmys -a QQQ -c CCC YYY +#} +#elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} { +# # For Synlig SystemVerilog, run additional passes to handle complexity +# parmys -a QQQ -c CCC YYY +#} opt -full @@ -95,4 +103,4 @@ stat hierarchy -check -auto-top -purge_lib -write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ \ No newline at end of file +write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index ae0bd0a1c3..40c855b9f7 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -22,7 +22,8 @@ ".ys": "RTLIL", } -YOSYS_PARSERS = ["default", "surelog", "system-verilog"] +#YOSYS_PARSERS = ["default", "surelog", "system-verilog"] +YOSYS_PARSERS = ["default", "slang"] def create_circuits_list(main_circuit, include_files): @@ -246,7 +247,7 @@ def run( del parmys_args["parser"] else: raise vtr.VtrError( - "Invalid parser is specified for Yosys, available parsers are [{}]".format( + parmys_args["parser"] + "Invalid parser is specified for Yosys, available parsers are [{}]".format( " ".join(str(x) for x in YOSYS_PARSERS) ) ) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt index 5005a12aac..17d18c484e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt @@ -35,4 +35,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog +script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt index c59221ce1d..70c60b720f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt @@ -32,4 +32,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog +script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt index c2c180dab1..670f3a50d7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt @@ -34,4 +34,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog +script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang From 90e180b23e2fa28fbe6753c79412c156c838ec0c Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Thu, 3 Jul 2025 12:30:31 -0300 Subject: [PATCH 03/15] Fully implemented yosys-slang as a plugin for yosys --- libs/EXTERNAL/CMakeLists.txt | 6 ++++ libs/EXTERNAL/patch_slang.cmake | 9 ++++++ vtr_flow/misc/yosys/synthesis.tcl | 46 ++++++++++++++++++++++++------- 3 files changed, 51 insertions(+), 10 deletions(-) create mode 100644 libs/EXTERNAL/patch_slang.cmake diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index f8e69f809a..382ad48ba4 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -91,11 +91,17 @@ if (${WITH_PARMYS}) COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive git\ submodule\ update\ --init WORKING_DIRECTORY ${SLANG_SRC_DIR} ) + set(SLANG_FE "${SLANG_SRC_DIR}/src/slang_frontend.cc") ExternalProject_Add( yosys-slang SOURCE_DIR ${SLANG_SRC_DIR} BINARY_DIR ${SLANG_BUILD_DIR} + PATCH_COMMAND + ${CMAKE_COMMAND} -E echo "Patching slang_frontend.cc to disable UndrivenPass" && + ${CMAKE_COMMAND} -DIN=${SLANG_FE} -P ${CMAKE_CURRENT_SOURCE_DIR}/patch_slang.cmake + + CONFIGURE_COMMAND ${CMAKE_COMMAND} -DCMAKE_BUILD_TYPE=Release -DYOSYS_CONFIG=${YOSYS_CONFIG_EXECUTABLE} diff --git a/libs/EXTERNAL/patch_slang.cmake b/libs/EXTERNAL/patch_slang.cmake new file mode 100644 index 0000000000..81c8a2f392 --- /dev/null +++ b/libs/EXTERNAL/patch_slang.cmake @@ -0,0 +1,9 @@ +if(NOT DEFINED IN) + message(FATAL_ERROR "patch_slang.cmake: IN (SLANG_FE) variable not set.") +endif() +file(READ "${IN}" SLANG_FRONTEND_CONTENTS) +string(REPLACE "call(design, \"undriven\");" "// call(design, \"undriven\");" SLANG_PATCHED "${SLANG_FRONTEND_CONTENTS}") + if(NOT SLANG_FRONTEND_CONTENTS STREQUAL SLANG_PATCHED) + message(STATUS "Patching slang_frontend.cc to disable UndrivenPass") + file(WRITE "${IN}" "${SLANG_PATCHED}") + endif() diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 2ef9e4256f..acbe7a91e0 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -1,12 +1,14 @@ yosys -import - +#puts "Files in here: [glob -nocomplain *]" plugin -i parmys -plugin -i slang -yosys -import read_verilog -nomem2reg +/parmys/vtr_primitives.v setattr -mod -set keep_hierarchy 1 single_port_ram setattr -mod -set keep_hierarchy 1 dual_port_ram +setattr -mod -set keep 1 dual_port_ram + +plugin -i slang +yosys -import # synlig path error handling if {[catch {set synlig $::env(synlig_exe_path)} err]} { @@ -25,10 +27,6 @@ if {[catch {set synlig $::env(synlig_exe_path)} err]} { # output file: ZZZ parmys_arch -a QQQ -if {$env(PARSER) == "slang" } { - puts "Using yosys-slang read_slang command" - read_slang XXX -} #if {$env(PARSER) == "surelog" } { # puts "Using Synlig read_uhdm command" @@ -37,8 +35,35 @@ if {$env(PARSER) == "slang" } { #} elseif {$env(PARSER) == "system-verilog" } { # puts "Using Synlig read_systemverilog " # exec $synlig -p "read_systemverilog XXX" -# } -elseif {$env(PARSER) == "default" } { +# } + +if {$env(PARSER) == "slang" } { + # Create a file list containing the name(s) of file(s) + # to read together with read_slang + set sv_files {} + set v_files {} + set readfile [file join [pwd] "filelist.txt"] + set fh [open $readfile "w"] + foreach f {XXX} { + set ext [string tolower [file extension $f]] + switch -- $ext { + .sv { + lappend $sv_files $f + puts $fh $f + } + .v { + error "Use default parser to parse .v files." + } + } + } + close $fh + if {[llength $sv_files] > 0} { + #puts "Using Yosys read_slang command" + #read_slang -C $readfile + } + puts "Using Yosys read_slang command" + read_slang -C $readfile +} elseif {$env(PARSER) == "default" } { puts "Using Yosys read_verilog command" read_verilog -sv -nolatches XXX } else { @@ -81,7 +106,8 @@ opt -full if {$env(PARSER) == "default" || $env(PARSER) == "slang"} { # For Verilog, use -nopass for a simpler, faster flow parmys -a QQQ -nopass -c CCC YYY -} #elseif {$env(PARSER) == "slang"} { +} +#elseif {$env(PARSER) == "slang"} { # For Slang, run additional passes to handle complexity # parmys -a QQQ -c CCC YYY #} From c1c2a5d8be8f358b52a1ed495c8a0616da5a8f07 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Thu, 3 Jul 2025 16:01:10 -0300 Subject: [PATCH 04/15] Updating configs for vtr_reg_system_verilog tests. They now read in multiple .sv files instead of single flattened .sv files (with the exception of the f4pga_pulse_width_led test since it uses .v files instead of .sv) --- vtr_flow/misc/yosys/synthesis.tcl | 7 ++-- .../koios_medium/config/config.txt | 2 +- .../f4pga_button_controller/config/config.txt | 10 ++--- .../f4pga_timer/config/config.txt | 11 +++--- .../koios_sv/config/config.txt | 37 +++++++++++++++++++ .../vtr_reg_system_verilog/task_list.txt | 1 + 6 files changed, 53 insertions(+), 15 deletions(-) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index acbe7a91e0..08800758db 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -1,5 +1,4 @@ yosys -import -#puts "Files in here: [glob -nocomplain *]" plugin -i parmys read_verilog -nomem2reg +/parmys/vtr_primitives.v @@ -38,7 +37,7 @@ parmys_arch -a QQQ # } if {$env(PARSER) == "slang" } { - # Create a file list containing the name(s) of file(s) + # Create a file list containing the name(s) of file(s) \ # to read together with read_slang set sv_files {} set v_files {} @@ -57,10 +56,10 @@ if {$env(PARSER) == "slang" } { } } close $fh - if {[llength $sv_files] > 0} { + #if {[llength $sv_files] > 0} { #puts "Using Yosys read_slang command" #read_slang -C $readfile - } + #} puts "Using Yosys read_slang command" read_slang -C $readfile } elseif {$env(PARSER) == "default" } { diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt index 4c09466d34..2af1583c15 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt @@ -46,4 +46,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements_fixed_chan_width.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 \ No newline at end of file +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt index 17d18c484e..f47770e46e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt @@ -12,14 +12,14 @@ archs_dir=arch/timing # Add circuits to list to sweep -#include_list_add=display_control.sv -#include_list_add=timer.sv -#include_list_add=debounce.sv +include_list_add=display_control.sv +include_list_add=timer.sv +include_list_add=debounce.sv # Add circuits to list to sweep -#circuit_list_add=button_controller.sv +#circuit_list_add=flattened_button_controller.sv -circuit_list_add=flattened_button_controller.sv +circuit_list_add=button_controller.sv # Add architectures to list to sweep diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt index 670f3a50d7..ee62c8c894 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt @@ -12,13 +12,14 @@ archs_dir=arch/timing # Add circuits to list to sweep -#include_list_add=timer.sv -#include_list_add=display_control.sv -#include_list_add=time_counter.sv -#include_list_add=modify_count.sv +include_list_add=modify_count.sv +include_list_add=display_control.sv +include_list_add=time_counter.sv +include_list_add=timer.sv # Add circuits to list to sweep -circuit_list_add=flattened_timer.sv +#circuit_list_add=flattened_timer.sv +circuit_list_add=clock.sv # Add architectures to list to sweep diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt new file mode 100644 index 0000000000..a7baf14269 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt @@ -0,0 +1,37 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/system_verilog/koios_sv +includes_dir=benchmarks/system_verilog/koios_sv + +# Path to directory of architectures to use +archs_dir=arch/timing + + +# Add circuits to list to sweep +#include_list_add=display_control.sv +#include_list_add=timer.sv +#include_list_add=debounce.sv + +# Add circuits to list to sweep +circuit_list_add=deepfreeze.style1.sv + + + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt index 509f77a643..a073b4f2f6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt @@ -1,3 +1,4 @@ regression_tests/vtr_reg_system_verilog/f4pga_button_controller/ +#regression_tests/vtr_reg_system_verilog/koios_sv/ regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/ regression_tests/vtr_reg_system_verilog/f4pga_timer/ From 0152c36a090bfad6082ab11cf27c5c8d26b7f09b Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Thu, 3 Jul 2025 16:44:57 -0300 Subject: [PATCH 05/15] Adding SystemVerilog reg test to CI --- .github/workflows/test.yml | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index fc80c9d523..088d13269e 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -417,6 +417,38 @@ jobs: ./.github/scripts/build.sh ./run_reg_test.py parmys_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count }} + SystemVerilog: + name: 'System Verilog Regression' + runs-on: ubuntu-24.04 + steps: + + - uses: actions/setup-python@v5 + with: + python-version: 3.12.3 + + # NOTE: This is using recursive on purpose. In order to use the System + # Verilog feature, need submodules inside of a submodule. + # - uses: actions/checkout@v4 + # with: + # submodules: 'recursive' + + - name: Get number of CPU cores + uses: SimenB/github-actions-cpu-cores@v2 + id: cpu-cores + + - name: Install dependencies + run: ./.github/scripts/install_dependencies.sh + + - uses: hendrikmuhs/ccache-action@v1.2 + + - name: Test + env: + CMAKE_PARAMS: '-DSLANG_SYSTEMVERILOG=ON' + NUM_PROC: ${{ steps.cpu-cores.outputs.count }} + run: | + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + ./.github/scripts/build.sh + ./run_reg_test.py vtr_reg_system_verilog -show_failures -j${{ steps.cpu-cores.outputs.count}} ODINII: name: 'ODIN-II Basic Test' @@ -565,6 +597,7 @@ jobs: - Regression - Sanitized - Parmys + - SystemVerilog - ODINII - VQM2BLIF - Compatibility From f7ae912d9ba78d0bc2c3cbcb822b8ffc2e4ad8e8 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Thu, 3 Jul 2025 17:31:12 -0300 Subject: [PATCH 06/15] Trying to fix issue with install dependencies for SystemVerilog Regression Test --- .github/workflows/test.yml | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 088d13269e..8420a82508 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -426,11 +426,9 @@ jobs: with: python-version: 3.12.3 - # NOTE: This is using recursive on purpose. In order to use the System - # Verilog feature, need submodules inside of a submodule. - # - uses: actions/checkout@v4 - # with: - # submodules: 'recursive' + - uses: actions/checkout@v4 + with: + submodules: 'true' - name: Get number of CPU cores uses: SimenB/github-actions-cpu-cores@v2 From 81b7ee4f3f2053fc7bab9dc9ccc41990ca8bb77c Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Fri, 4 Jul 2025 12:30:13 -0300 Subject: [PATCH 07/15] Fixing regression test run failures due to yosys-slang plugin being loaded in when not enabled. --- vtr_flow/misc/yosys/synthesis.tcl | 39 +++++++++++++++---- .../scripts/python_libs/vtr/parmys/parmys.py | 9 ++++- vtr_flow/scripts/python_libs/vtr/paths.py | 1 + 3 files changed, 39 insertions(+), 10 deletions(-) diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 08800758db..81d4cc6941 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -6,16 +6,32 @@ setattr -mod -set keep_hierarchy 1 single_port_ram setattr -mod -set keep_hierarchy 1 dual_port_ram setattr -mod -set keep 1 dual_port_ram -plugin -i slang -yosys -import - # synlig path error handling -if {[catch {set synlig $::env(synlig_exe_path)} err]} { - puts "Error: $err" - puts "synlig_exe_path is not set" +#if {[catch {set synlig $::env(synlig_exe_path)} err]} { +# puts "Error: $err" +# puts "synlig_exe_path is not set" +#} else { +# set synlig $::env(synlig_exe_path) +# puts "Using parmys as partial mapper" +#} + +# yosys-slang plugin error handling +if {$env(PARSER) == "slang" } { + if {![info exists ::env(yosys_slang_path)]} { + puts "Error: $err" + puts "yosys_slang_path is not set" + } elseif {![file exists $::env(yosys_slang_path)]} { + error "Error: cannot find plugin at '$::env(yosys_slang_path)'. Run make with CMake param -DSLANG_SYSTEMVERILOG=ON to enable yosys-slang plugin." + } else { + plugin -i slang + yosys -import + puts "Using yosys-slang as yosys frontend" + } +} elseif {$env(PARSER) == "default" } { + yosys -import + puts "Using Yosys read_verilog as yosys frontend" } else { - set synlig $::env(synlig_exe_path) - puts "Using parmys as partial mapper" + error "Invalid PARSER" } @@ -50,9 +66,16 @@ if {$env(PARSER) == "slang" } { lappend $sv_files $f puts $fh $f } + .svh { + lappend $sv_files $f + puts $fh $f + } .v { error "Use default parser to parse .v files." } + .vh { + error "Use default parser to parse .v files." + } } } close $fh diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index 40c855b9f7..7b50038baa 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -236,10 +236,15 @@ def run( # Set the synlig exe script path in the environment variable # (handle if it is not set or system-verilog OFF) + # try: + # os.environ["synlig_exe_path"] = str(vtr.paths.synlig_exe_path) + # except KeyError: + # os.environ["synlig_exe_path"] = "/dummy/path" + try: - os.environ["synlig_exe_path"] = str(vtr.paths.synlig_exe_path) + os.environ["yosys_slang_path"] = str(vtr.paths.yosys_slang_path) except KeyError: - os.environ["synlig_exe_path"] = "/dummy/path" + os.environ["yosys_slang_path"] = "/dummy/path" # set the parser if parmys_args["parser"] in YOSYS_PARSERS: diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py index 2ab1e4c31b..344a79e515 100644 --- a/vtr_flow/scripts/python_libs/vtr/paths.py +++ b/vtr_flow/scripts/python_libs/vtr/paths.py @@ -21,6 +21,7 @@ yosys_exe_path = yosys_path / "yosys" yosys_tcl_path = vtr_flow_path / "misc" / "yosys" yosys_script_path = yosys_tcl_path / "synthesis.tcl" +yosys_slang_path = root_path / "build" / "share" / "yosys" / "plugins" / "slang.so" # Synlig paths synlig_path = root_path / "build" / "bin" / "synlig_install" From ce26e71f2b29b6e931a4ddec7e69f94b6a12fe45 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 7 Jul 2025 10:30:00 -0300 Subject: [PATCH 08/15] Fixing code format in python script (python.cc) and resolving conflicts in test.yml --- .github/workflows/test.yml | 382 ++++++++++-------- .../scripts/python_libs/vtr/parmys/parmys.py | 7 +- 2 files changed, 219 insertions(+), 170 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 8420a82508..6e7cd91ce6 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -34,21 +34,51 @@ env: MATRIX_EVAL: "CC=gcc-13 && CXX=g++-13" jobs: - Build: - name: 'B: Building VtR' + BuildVTR: + name: 'B: Building VTR Release' runs-on: ubuntu-24.04 - strategy: - fail-fast: false - matrix: - include: - - { build_type: 'release', verbose: '0' } - - { build_type: 'debug', verbose: '0' } - - { build_type: 'debug', verbose: '1' } steps: + - uses: actions/checkout@v4 + with: + submodules: 'true' - - uses: actions/setup-python@v5 + - name: Get number of CPU cores + uses: SimenB/github-actions-cpu-cores@v2 + id: cpu-cores + + - name: Install dependencies + run: ./.github/scripts/install_dependencies.sh + + - uses: hendrikmuhs/ccache-action@v1.2 with: - python-version: 3.12.3 + key: ${{ github.job }} + + - name: Build + env: + CMAKE_PARAMS: "-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3" + BUILD_TYPE: release + NUM_PROC: ${{ steps.cpu-cores.outputs.count }} + run: | + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + make -j${{ steps.cpu-cores.outputs.count}} + + - name: Pack Build + shell: bash + run: | + tar -czvf build.tar.gz --exclude='CMakeFiles' --exclude='*.a' --exclude='*.cmake' build/ + + - name: Store Build Artifact + uses: actions/upload-artifact@v4 + with: + name: build-release.tar.gz + path: build.tar.gz + retention-days: 1 + + + BuildVTRWithOdin: + name: 'B: Building VTR Release With Odin' + runs-on: ubuntu-24.04 + steps: - uses: actions/checkout@v4 with: submodules: 'true' @@ -61,14 +91,29 @@ jobs: run: ./.github/scripts/install_dependencies.sh - uses: hendrikmuhs/ccache-action@v1.2 + with: + key: ${{ github.job }} - - name: Test + - name: Build env: - BUILD_TYPE: ${{ matrix.build_type }} + CMAKE_PARAMS: "-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on" + BUILD_TYPE: release NUM_PROC: ${{ steps.cpu-cores.outputs.count }} run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh VERBOSE=${{ matrix.verbose }} + make -j${{ steps.cpu-cores.outputs.count}} + + - name: Pack Build + shell: bash + run: | + tar -czvf build.tar.gz --exclude='CMakeFiles' --exclude='*.a' --exclude='*.cmake' build/ + + - name: Store Build Artifact + uses: actions/upload-artifact@v4 + with: + name: build-release-with-odin.tar.gz + path: build.tar.gz + retention-days: 1 Format: @@ -88,6 +133,7 @@ jobs: - uses: actions/setup-python@v5 with: python-version: 3.10.10 + - uses: actions/checkout@v4 with: submodules: 'true' @@ -121,11 +167,9 @@ jobs: UnitTests: name: 'U: C++ Unit Tests' runs-on: ubuntu-24.04 + needs: [BuildVTR] steps: - - uses: actions/setup-python@v5 - with: - python-version: 3.12.3 - uses: actions/checkout@v4 with: submodules: 'true' @@ -137,11 +181,20 @@ jobs: - name: Install dependencies run: ./.github/scripts/install_dependencies.sh + - name: Download Build Artifact + uses: actions/download-artifact@v4 + with: + name: build-release.tar.gz + + - name: Unpack Build + shell: bash + run: | + tar -xvzf build.tar.gz + - name: Test - env: - CMAKE_PARAMS: "-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on" - NUM_PROC: ${{ steps.cpu-cores.outputs.count }} - run: ./.github/scripts/unittest.sh + run: | + cd build + make test -j${{ steps.cpu-cores.outputs.count }} # This test builds different variations of VTR (with different CMake Params) @@ -173,6 +226,8 @@ jobs: - name: 'ccache' uses: hendrikmuhs/ccache-action@v1.2 + with: + key: ${{ github.job }} - name: 'Test with VTR_ASSERT_LEVEL 4' if: success() || failure() @@ -229,54 +284,110 @@ jobs: make -j${{ steps.cpu-cores.outputs.count}} ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}} + - name: 'Test with VTR_ENABLE_DEBUG_LOGGING enabled' + if: success() || failure() + env: + CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ENABLE_DEBUG_LOGGING=on" + NUM_PROC: ${{ steps.cpu-cores.outputs.count }} + run: | + rm -f build/CMakeCache.txt + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + make -j${{ steps.cpu-cores.outputs.count}} + ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}} + Regression: runs-on: ubuntu-24.04 + needs: [BuildVTR] strategy: fail-fast: false matrix: include: [ { name: 'Basic', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on', - suite: 'vtr_reg_basic', - extra_pkgs: "" - }, - { - name: 'Basic_odin', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on', - suite: 'vtr_reg_basic_odin', - extra_pkgs: "" + suite: 'vtr_reg_basic' }, { - name: 'Basic with VTR_ENABLE_DEBUG_LOGGING', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on', - suite: 'vtr_reg_basic', - extra_pkgs: "" + name: 'Strong', + suite: 'vtr_reg_strong' }, { - name: 'Basic_odin with VTR_ENABLE_DEBUG_LOGGING', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on -DWITH_PARMYS=OFF -DWITH_ODIN=on', - suite: 'vtr_reg_basic_odin', - extra_pkgs: "" - }, + name: 'Valgrind Memory', + suite: 'vtr_reg_valgrind_small' + } + ] + name: 'R: ${{ matrix.name }}' + steps: + + - uses: actions/setup-python@v5 + with: + python-version: 3.12.3 + + - uses: actions/checkout@v4 + with: + submodules: 'true' + + - name: Get number of CPU cores + uses: SimenB/github-actions-cpu-cores@v2 + id: cpu-cores + + - name: Install dependencies + run: ./.github/scripts/install_dependencies.sh + + - name: Download Build Artifact + uses: actions/download-artifact@v4 + with: + name: build-release.tar.gz + + - name: Unpack Build + shell: bash + run: | + tar -xvzf build.tar.gz + + - name: Test + run: | + ./run_reg_test.py ${{ matrix.suite }} -show_failures -j${{ steps.cpu-cores.outputs.count}} + + - name: Upload regression run files + if: ${{ !cancelled() }} + uses: actions/upload-artifact@v4 + with: + name: ${{matrix.name}}_run_files + path: | + vtr_flow/**/*.out + # vtr_flow/**/*.blif # Removed since it was taking too much space and was hardly used. + vtr_flow/**/*.p + vtr_flow/**/*.net + vtr_flow/**/*.r + + - name: Upload regression results + if: ${{ !cancelled() }} + uses: actions/upload-artifact@v4 + with: + name: ${{matrix.name}}_results + path: | + vtr_flow/**/*.log + vtr_flow/**/parse_results*.txt + + + RegressionWithOdin: + runs-on: ubuntu-24.04 + needs: [BuildVTRWithOdin] + strategy: + fail-fast: false + matrix: + include: [ { - name: 'Strong', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on', - suite: 'vtr_reg_strong', - extra_pkgs: "libeigen3-dev" + name: 'Basic_odin', + suite: 'vtr_reg_basic_odin' }, { name: 'Strong_odin', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on', - suite: 'vtr_reg_strong_odin', - extra_pkgs: "" + suite: 'vtr_reg_strong_odin' }, { - name: 'Valgrind Memory', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_ODIN=on', - suite: 'vtr_reg_valgrind_small', - extra_pkgs: "" + name: 'Valgrind Memory Odin', + suite: 'vtr_reg_valgrind_small_odin' } ] name: 'R: ${{ matrix.name }}' @@ -297,19 +408,18 @@ jobs: - name: Install dependencies run: ./.github/scripts/install_dependencies.sh - - name: Install external libraries - run: sudo apt install -y ${{ matrix.extra_pkgs }} - if: ${{ matrix.extra_pkgs }} + - name: Download Build Artifact + uses: actions/download-artifact@v4 + with: + name: build-release-with-odin.tar.gz - - uses: hendrikmuhs/ccache-action@v1.2 + - name: Unpack Build + shell: bash + run: | + tar -xvzf build.tar.gz - name: Test - env: - CMAKE_PARAMS: ${{ matrix.params }} - NUM_PROC: ${{ steps.cpu-cores.outputs.count }} run: | - export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh ./run_reg_test.py ${{ matrix.suite }} -show_failures -j${{ steps.cpu-cores.outputs.count}} - name: Upload regression run files @@ -333,6 +443,7 @@ jobs: vtr_flow/**/*.log vtr_flow/**/parse_results*.txt + Sanitized: runs-on: ubuntu-24.04 strategy: @@ -366,6 +477,8 @@ jobs: run: ./.github/scripts/install_dependencies.sh - uses: hendrikmuhs/ccache-action@v1.2 + with: + key: ${{ github.job }}-${{ matrix.suite }} - name: Test env: @@ -389,6 +502,7 @@ jobs: Parmys: name: 'Parmys Basic Test' runs-on: ubuntu-24.04 + needs: [BuildVTR] steps: - uses: actions/setup-python@v5 @@ -405,52 +519,25 @@ jobs: - name: Install dependencies run: ./.github/scripts/install_dependencies.sh - - uses: hendrikmuhs/ccache-action@v1.2 - - - name: Test - env: - CMAKE_PARAMS: '-DVTR_IPO_BUILD=off' - BUILD_TYPE: debug - NUM_PROC: ${{ steps.cpu-cores.outputs.count }} - run: | - export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh - ./run_reg_test.py parmys_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count }} - - SystemVerilog: - name: 'System Verilog Regression' - runs-on: ubuntu-24.04 - steps: - - - uses: actions/setup-python@v5 - with: - python-version: 3.12.3 - - - uses: actions/checkout@v4 + - name: Download Build Artifact + uses: actions/download-artifact@v4 with: - submodules: 'true' + name: build-release.tar.gz - - name: Get number of CPU cores - uses: SimenB/github-actions-cpu-cores@v2 - id: cpu-cores - - - name: Install dependencies - run: ./.github/scripts/install_dependencies.sh - - - uses: hendrikmuhs/ccache-action@v1.2 + - name: Unpack Build + shell: bash + run: | + tar -xvzf build.tar.gz - name: Test - env: - CMAKE_PARAMS: '-DSLANG_SYSTEMVERILOG=ON' - NUM_PROC: ${{ steps.cpu-cores.outputs.count }} run: | - export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh - ./run_reg_test.py vtr_reg_system_verilog -show_failures -j${{ steps.cpu-cores.outputs.count}} + ./run_reg_test.py parmys_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count }} + ODINII: name: 'ODIN-II Basic Test' runs-on: ubuntu-24.04 + needs: [BuildVTRWithOdin] steps: - uses: actions/setup-python@v5 @@ -467,23 +554,26 @@ jobs: - name: Install dependencies run: ./.github/scripts/install_dependencies.sh - - uses: hendrikmuhs/ccache-action@v1.2 + - name: Download Build Artifact + uses: actions/download-artifact@v4 + with: + name: build-release-with-odin.tar.gz + + - name: Unpack Build + shell: bash + run: | + tar -xvzf build.tar.gz - name: Test - env: - CMAKE_PARAMS: '-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=on -DVTR_IPO_BUILD=off -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on' - BUILD_TYPE: debug - NUM_PROC: ${{ steps.cpu-cores.outputs.count }} run: | sudo sysctl -w vm.mmap_rnd_bits=28 - export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh ./run_reg_test.py odin_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count }} VQM2BLIF: name: 'VQM2BLIF Basic Tests' runs-on: ubuntu-24.04 + needs: [BuildVTR] steps: - uses: actions/setup-python@v5 @@ -500,29 +590,33 @@ jobs: - name: Install dependencies run: ./.github/scripts/install_dependencies.sh - - uses: hendrikmuhs/ccache-action@v1.2 + - name: Download Build Artifact + uses: actions/download-artifact@v4 + with: + name: build-release.tar.gz + + - name: Unpack Build + shell: bash + run: | + tar -xvzf build.tar.gz - name: Test - env: - BUILD_TYPE: release - NUM_PROC: ${{ steps.cpu-cores.outputs.count }} run: | - export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh ./utils/vqm2blif/test/scripts/test_vqm2blif.sh Compatibility: runs-on: ubuntu-24.04 + needs: [BuildVTR] strategy: fail-fast: false matrix: include: - - { name: 'GCC 11 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-11 && CXX=g++-11', } - - { name: 'GCC 12 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-12 && CXX=g++-12', } - - { name: 'GCC 14 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-14 && CXX=g++-14', } - - { name: 'Clang 16 (Ubuntu Noble - 24.04)', eval: 'CC=clang-16 && CXX=clang++-16', } - - { name: 'Clang 17 (Ubuntu Noble - 24.04)', eval: 'CC=clang-17 && CXX=clang++-17', } - - { name: 'Clang 18 (Ubuntu Noble - 24.04)', eval: 'CC=clang-18 && CXX=clang++-18', } + - { name: 'GCC 11 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-11 && CXX=g++-11', key: 'gcc-11', } + - { name: 'GCC 12 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-12 && CXX=g++-12', key: 'gcc-12', } + - { name: 'GCC 14 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-14 && CXX=g++-14', key: 'gcc-14', } + - { name: 'Clang 16 (Ubuntu Noble - 24.04)', eval: 'CC=clang-16 && CXX=clang++-16', key: 'clang-16', } + - { name: 'Clang 17 (Ubuntu Noble - 24.04)', eval: 'CC=clang-17 && CXX=clang++-17', key: 'clang-17', } + - { name: 'Clang 18 (Ubuntu Noble - 24.04)', eval: 'CC=clang-18 && CXX=clang++-18', key: 'clang-18', } # Note: We do not include GCC-13 since it is the default and is already tested. name: 'B: ${{ matrix.name }}' steps: @@ -542,12 +636,14 @@ jobs: run: ./.github/scripts/install_dependencies.sh - uses: hendrikmuhs/ccache-action@v1.2 + with: + key: ${{ github.job }}-${{ matrix.key }} - name: Test env: - CMAKE_PARAMS: "-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_ODIN=on" + CMAKE_PARAMS: "-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_ODIN=on -DVTR_IPO_BUILD=off" MATRIX_EVAL: ${{ matrix.eval }} - BUILD_TYPE: release + BUILD_TYPE: debug # Note: We use the debug build here to make the build time faster since we do not care about run time. NUM_PROC: ${{ steps.cpu-cores.outputs.count }} run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" @@ -556,6 +652,7 @@ jobs: JammyCompatibility: name: 'Ubuntu Jammy - 22.04 Compatibility Test' runs-on: ubuntu-22.04 + needs: [BuildVTR] steps: - uses: actions/setup-python@v5 with: @@ -573,58 +670,15 @@ jobs: run: ./.github/scripts/install_jammy_dependencies.sh - uses: hendrikmuhs/ccache-action@v1.2 + with: + key: ${{ github.job }} - name: Test env: CMAKE_PARAMS: "-DVTR_ASSERT_LEVEL=3 -DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off" MATRIX_EVAL: 'CC=gcc-11 && CXX=g++-11' - BUILD_TYPE: release - NUM_PROC: ${{ steps.cpu-cores.outputs.count }} - run: | - export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh - - Coverity: - name: 'Coverity Scan' - needs: - - Build - - Format - - VerifyTestSuites - - UnitTests - - BuildVariations - - Regression - - Sanitized - - Parmys - - SystemVerilog - - ODINII - - VQM2BLIF - - Compatibility - runs-on: ubuntu-24.04 - steps: - - - uses: actions/setup-python@v5 - with: - python-version: 3.12.3 - - uses: actions/checkout@v4 - with: - submodules: 'true' - - - name: Get number of CPU cores - uses: SimenB/github-actions-cpu-cores@v2 - id: cpu-cores - - - name: Install dependencies - run: ./.github/scripts/install_dependencies.sh - - - uses: hendrikmuhs/ccache-action@v1.2 - - - name: Test - env: - CMAKE_PARAMS: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on' + BUILD_TYPE: debug # Note: We use the debug build here to make the build time faster since we do not care about run time. NUM_PROC: ${{ steps.cpu-cores.outputs.count }} - _COVERITY_URL: 'https://scan.coverity.com/download/linux64' - _COVERITY_MD5: 'd0d7d7df9d6609e578f85096a755fb8f' run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh - + ./.github/scripts/build.sh \ No newline at end of file diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index 7b50038baa..9cee221f81 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -22,7 +22,6 @@ ".ys": "RTLIL", } -#YOSYS_PARSERS = ["default", "surelog", "system-verilog"] YOSYS_PARSERS = ["default", "slang"] @@ -236,11 +235,7 @@ def run( # Set the synlig exe script path in the environment variable # (handle if it is not set or system-verilog OFF) - # try: - # os.environ["synlig_exe_path"] = str(vtr.paths.synlig_exe_path) - # except KeyError: - # os.environ["synlig_exe_path"] = "/dummy/path" - + try: os.environ["yosys_slang_path"] = str(vtr.paths.yosys_slang_path) except KeyError: From d2ffe14030e6f0afb61ad08e1ffbac1b5455886a Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 7 Jul 2025 10:31:24 -0300 Subject: [PATCH 09/15] Further resolving conflicts with test.yml --- .github/workflows/test.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 6e7cd91ce6..3176d6276b 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -681,4 +681,5 @@ jobs: NUM_PROC: ${{ steps.cpu-cores.outputs.count }} run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh \ No newline at end of file + ./.github/scripts/build.sh + \ No newline at end of file From 172758b263bd48c7a74d20a157e87b3e635e1045 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 7 Jul 2025 10:36:28 -0300 Subject: [PATCH 10/15] Further resolving conflicts with test.yml --- .github/workflows/test.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 3176d6276b..6e7cd91ce6 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -681,5 +681,4 @@ jobs: NUM_PROC: ${{ steps.cpu-cores.outputs.count }} run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh - \ No newline at end of file + ./.github/scripts/build.sh \ No newline at end of file From 9b51cbc53ebc360ad7fbb8f3ab6af52ccaf9ac77 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 7 Jul 2025 11:18:54 -0300 Subject: [PATCH 11/15] Fixing line format errors in parmys.cc --- vtr_flow/scripts/python_libs/vtr/parmys/parmys.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index 9cee221f81..4a0ee36015 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -235,7 +235,6 @@ def run( # Set the synlig exe script path in the environment variable # (handle if it is not set or system-verilog OFF) - try: os.environ["yosys_slang_path"] = str(vtr.paths.yosys_slang_path) except KeyError: @@ -247,7 +246,7 @@ def run( del parmys_args["parser"] else: raise vtr.VtrError( - parmys_args["parser"] + "Invalid parser is specified for Yosys, available parsers are [{}]".format( + parmys_args["parser"]+"Invalid parser is specified for Yosys, available parsers are [{}]".format( " ".join(str(x) for x in YOSYS_PARSERS) ) ) From 8d8d6835128f67d9e91f0f882c29da87b67ad2f7 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 7 Jul 2025 11:33:35 -0300 Subject: [PATCH 12/15] Further fixing line format/length errors in parmys.cc --- vtr_flow/scripts/python_libs/vtr/parmys/parmys.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index 4a0ee36015..88f007045e 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -246,7 +246,7 @@ def run( del parmys_args["parser"] else: raise vtr.VtrError( - parmys_args["parser"]+"Invalid parser is specified for Yosys, available parsers are [{}]".format( + parmys_args["parser"]+"Invalid parser is specified for Yosys. Parsers are [{}]".format( " ".join(str(x) for x in YOSYS_PARSERS) ) ) From 2d107fb4b6f5220a02002d31efe8c8f9752dd310 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 7 Jul 2025 11:40:08 -0300 Subject: [PATCH 13/15] Further fixing line format/length errors in parmys.cc --- vtr_flow/scripts/python_libs/vtr/parmys/parmys.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index 88f007045e..a7a8d8153d 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -246,7 +246,8 @@ def run( del parmys_args["parser"] else: raise vtr.VtrError( - parmys_args["parser"]+"Invalid parser is specified for Yosys. Parsers are [{}]".format( + parmys_args["parser"] + + "Invalid parser is specified for Yosys. Parsers are [{}]".format( " ".join(str(x) for x in YOSYS_PARSERS) ) ) From 3cf1050ba3b0e6ed4a6e356ff963a7053b6c48e2 Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Mon, 7 Jul 2025 12:33:47 -0300 Subject: [PATCH 14/15] Updating parser documentation for run_vtr_flow to replace synlig/surelog with yosys-slang --- doc/src/vtr/run_vtr_flow.rst | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/doc/src/vtr/run_vtr_flow.rst b/doc/src/vtr/run_vtr_flow.rst index 98026e6896..7534be08a1 100644 --- a/doc/src/vtr/run_vtr_flow.rst +++ b/doc/src/vtr/run_vtr_flow.rst @@ -73,15 +73,12 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer .. code-block:: bash - # Using the Synlig System_Verilog tool if installed, otherwise the Yosys conventional Verilog parser - ./run_vtr_flow -parser system-verilog - - # Using the Surelog plugin if installed, otherwise failure on the unsupported file type - ./run_vtr_flow -parser surelog + # Using the Yosys-Slang plugin for Yosys, otherwise the Yosys conventional Verilog parser + ./run_vtr_flow -parser slang -Running the default VTR flow using the Parmys standalone front-end. -The Synlig HDL parser supports the (i.e., ``read_systemverilog``) and (i.e., ``read_uhdm``) commands. It utilizes Surelog for SystemVerilog 2017 processing and Yosys for synthesis. -Enable Synlig tool with the ``-DSYNLIG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end. +Will run the VTR flow (default configuration) with Yosys-Slang plugin for Yosys frontend using Parmys plugin as partial mapper. +The Yosys-Slang SystemVerilog parser supports the (i.e., ``read_slang``) command. Yosys-Slang builds on top of the slang library to provide comprehensive SystemVerilog support. +Enable the Yosys-Slang plugin with the ``-DSLANG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end. .. code-block:: bash @@ -260,19 +257,24 @@ Detailed Command-line Options .. option:: -parser - Specify a parser for the Yosys synthesizer [default (Verilog-2005), surelog (UHDM), system-verilog]. + Specify a parser for the Yosys synthesizer [default (Verilog-2005), slang (SystemVerilog)]. The script uses the default conventional Verilog parser if this argument is not used. **Default:** default .. note:: - Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. - UHDM is used as a compiled interchange format in between SystemVerilog tools. Typical inputs to the UHDM flow are files with ``.v`` or ``.sv`` extensions. - The ``system-verilog`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys. - It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] `_ - On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys `_, `Surelog] `_ + Yosys-Slang is a Yosys plugin that is built on top of the slang library to provide comprehensive SystemVerilog support. + It supports the ``read_slang`` command, used with the ``-C`` command-line option to read include-files from a text file containing include-file names. + It is used to read SystemVerilog files directly in Yosys. + For more information on Yosys-Slang, see `[Yosys-Slang] `_ .. note:: Parmys is a Yosys plugin which provides intelligent partial mapping features (inference, binding, and hard/soft logic trade-offs) from Odin-II for Yosys. For more information on available paramters see the `Parmys `_ plugin page. + +.. Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. +.. UHDM is used as a compiled interchange format in between SystemVerilog tools. Typical inputs to the UHDM flow are files with ``.v`` or ``.sv`` extensions. +.. The ``system-verilog`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys. +.. It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] `_ +.. On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys `_, `Surelog] `_ From 3fbe39f45e56771ae2cbc2cf3f7397f714b4554d Mon Sep 17 00:00:00 2001 From: Logan Lavigne Date: Tue, 8 Jul 2025 17:24:47 -0300 Subject: [PATCH 15/15] Cleaning up some code in synthesis.tcl --- vtr_flow/misc/yosys/synthesis.tcl | 41 ++++--------------------------- 1 file changed, 5 insertions(+), 36 deletions(-) diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 81d4cc6941..c80b921151 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -6,15 +6,6 @@ setattr -mod -set keep_hierarchy 1 single_port_ram setattr -mod -set keep_hierarchy 1 dual_port_ram setattr -mod -set keep 1 dual_port_ram -# synlig path error handling -#if {[catch {set synlig $::env(synlig_exe_path)} err]} { -# puts "Error: $err" -# puts "synlig_exe_path is not set" -#} else { -# set synlig $::env(synlig_exe_path) -# puts "Using parmys as partial mapper" -#} - # yosys-slang plugin error handling if {$env(PARSER) == "slang" } { if {![info exists ::env(yosys_slang_path)]} { @@ -34,7 +25,6 @@ if {$env(PARSER) == "slang" } { error "Invalid PARSER" } - # arch file: QQQ # input files: [XXX] # other args: [YYY] @@ -46,43 +36,22 @@ parmys_arch -a QQQ #if {$env(PARSER) == "surelog" } { # puts "Using Synlig read_uhdm command" # exec $synlig -p "read_uhdm XXX" - -#} elseif {$env(PARSER) == "system-verilog" } { -# puts "Using Synlig read_systemverilog " -# exec $synlig -p "read_systemverilog XXX" -# } +#} if {$env(PARSER) == "slang" } { # Create a file list containing the name(s) of file(s) \ # to read together with read_slang - set sv_files {} - set v_files {} set readfile [file join [pwd] "filelist.txt"] set fh [open $readfile "w"] foreach f {XXX} { set ext [string tolower [file extension $f]] - switch -- $ext { - .sv { - lappend $sv_files $f - puts $fh $f - } - .svh { - lappend $sv_files $f - puts $fh $f - } - .v { - error "Use default parser to parse .v files." - } - .vh { - error "Use default parser to parse .v files." - } + if {$ext == ".sv" || $ext == ".svh" || $ext == ".v" || $ext == ".vh"} { + puts $fh $f + } else { + error "Unsupported file type. Yosys-Slang accepts .sv .svh .v .vh" } } close $fh - #if {[llength $sv_files] > 0} { - #puts "Using Yosys read_slang command" - #read_slang -C $readfile - #} puts "Using Yosys read_slang command" read_slang -C $readfile } elseif {$env(PARSER) == "default" } {