diff --git a/.gitmodules b/.gitmodules
index 48709ae2f42..b2b3b51feef 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,3 +13,6 @@
 [submodule "libs/EXTERNAL/yosys"]
 	path = libs/EXTERNAL/yosys
 	url = https://github.com/YosysHQ/yosys.git
+[submodule "libs/EXTERNAL/yosys-slang"]
+	path = libs/EXTERNAL/yosys-slang
+	url = https://github.com/povik/yosys-slang.git
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 4fb30b2f9e1..ca6c89e601c 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -56,7 +56,8 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 
 # Allow the user to enable building Yosys
 option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON)
-option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF)
+#option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF)
+option(SLANG_SYSTEMVERILOG "Enable building and installing Yosys-Slang plugin for parsing SystemVerilog" OFF)
 
 set(VTR_VERSION_MAJOR 9)
 set(VTR_VERSION_MINOR 0)
@@ -438,7 +439,7 @@ if(${WITH_ODIN})
 endif()
 
 # handle cmake params to compile Yosys SystemVerilog/UHDM plugins
-if(${SYNLIG_SYSTEMVERILOG})
+if(${SLANG_SYSTEMVERILOG})
     # avoid compiling plugins in case the Parmys frontend is not active
     if(NOT ${WITH_PARMYS})
         message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.")
diff --git a/doc/src/vtr/run_vtr_flow.rst b/doc/src/vtr/run_vtr_flow.rst
index 98026e68965..7534be08a16 100644
--- a/doc/src/vtr/run_vtr_flow.rst
+++ b/doc/src/vtr/run_vtr_flow.rst
@@ -73,15 +73,12 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer
 
 .. code-block:: bash
 
-    # Using the Synlig System_Verilog tool if installed, otherwise the Yosys conventional Verilog parser
-    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -parser system-verilog
-
-    # Using the Surelog plugin if installed, otherwise failure on the unsupported file type
-    ./run_vtr_flow <path/to/UHDM/File> <path/to/arch/file> -parser surelog
+    # Using the Yosys-Slang plugin for Yosys, otherwise the Yosys conventional Verilog parser
+    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -parser slang
 
-Running the default VTR flow using the Parmys standalone front-end.
-The Synlig HDL parser supports the (i.e., ``read_systemverilog``) and (i.e., ``read_uhdm``) commands. It utilizes Surelog for SystemVerilog 2017 processing and Yosys for synthesis.
-Enable Synlig tool with the ``-DSYNLIG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end.
+Will run the VTR flow (default configuration) with Yosys-Slang plugin for Yosys frontend using Parmys plugin as partial mapper.
+The Yosys-Slang SystemVerilog parser supports the (i.e., ``read_slang``) command. Yosys-Slang builds on top of the slang library to provide comprehensive SystemVerilog support.
+Enable the Yosys-Slang plugin with the ``-DSLANG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end.
 
 .. code-block:: bash
 
@@ -260,19 +257,24 @@ Detailed Command-line Options
 
 .. option:: -parser <PARSER>
 
-    Specify a parser for the Yosys synthesizer [default (Verilog-2005), surelog (UHDM), system-verilog].
+    Specify a parser for the Yosys synthesizer [default (Verilog-2005), slang (SystemVerilog)].
     The script uses the default conventional Verilog parser if this argument is not used.
     
     **Default:** default
 
 .. note::
 
-    Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.
-    UHDM is used as a compiled interchange format in between SystemVerilog tools. Typical inputs to the UHDM flow are files with ``.v`` or ``.sv`` extensions.
-    The ``system-verilog`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys.
-    It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] <https://github.com/antmicro/yosys-systemverilog#usage>`_
-    On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys <https://github.com/chipsalliance/UHDM-integration-tests#uhdm-yosys>`_, `Surelog] <https://github.com/chipsalliance/Surelog#surelog>`_
+    Yosys-Slang is a Yosys plugin that is built on top of the slang library to provide comprehensive SystemVerilog support.
+    It supports the ``read_slang`` command, used with the ``-C`` command-line option to read include-files from a text file containing include-file names.
+    It is used to read SystemVerilog files directly in Yosys.
+    For more information on Yosys-Slang, see `[Yosys-Slang] <https://github.com/povik/yosys-slang.git>`_
 
 .. note::
 
     Parmys is a Yosys plugin which provides intelligent partial mapping features (inference, binding, and hard/soft logic trade-offs) from Odin-II for Yosys. For more information on available paramters see the `Parmys <https://github.com/CAS-Atlantic/parmys-plugin.git>`_ plugin page.
+
+.. Universal Hardware Data Model (UHDM) is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.
+..     UHDM is used as a compiled interchange format in between SystemVerilog tools. Typical inputs to the UHDM flow are files with ``.v`` or ``.sv`` extensions.
+..     The ``system-verilog`` parser, which represents the ``read_systemverilog`` command, reads SystemVerilog files directly in Yosys.
+..     It executes Surelog with provided filenames and converts them (in memory) into UHDM file. Then, this UHDM file is converted into Yosys AST. `[Yosys-SystemVerilog] <https://github.com/antmicro/yosys-systemverilog#usage>`_
+..     On the other hand, the ``surelog`` parser, which uses the ``read_uhdm`` Yosys command, walks the design tree and converts its nodes into Yosys AST nodes using Surelog. `[UHDM-Yosys <https://github.com/chipsalliance/UHDM-integration-tests#uhdm-yosys>`_, `Surelog] <https://github.com/chipsalliance/Surelog#surelog>`_
diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt
index ff2256bc77c..01005a14cbf 100644
--- a/libs/EXTERNAL/CMakeLists.txt
+++ b/libs/EXTERNAL/CMakeLists.txt
@@ -84,92 +84,123 @@ if (${WITH_PARMYS})
 
 	add_custom_target(yosys ALL DEPENDS ${YOSYS_BUILD_DIR})
 
-    if (${SYNLIG_SYSTEMVERILOG})
-
-        set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
-        set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build)
-        set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins)
-
-        ExternalProject_Add(surelog
-                # root directory for Surelog project
-                PREFIX "surelog"
-
-                GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git
-                GIT_TAG v1.71
-                GIT_PROGRESS TRUE
-                GIT_SHALLOW TRUE
-
-                # setting source, build and install directories
-                SOURCE_DIR "${SURELOG_SOURCE_DIR}"
-                BUILD_IN_SOURCE FALSE
-                INSTALL_DIR "${SURELOG_BINARY_DIR}"
-
-                # define Surelog cache values
-                CMAKE_CACHE_ARGS
-                "-DCMAKE_BUILD_TYPE:STRING=Release"
-                "-DCMAKE_INSTALL_PREFIX:PATH=${CMAKE_BINARY_DIR}"
-                "-DCMAKE_POSITION_INDEPENDENT_CODE:BOOL=ON"
-                "-DCMAKE_WARN_DEPRECATED:BOOL=OFF"
-
-                # redirect logs to a logfile
-                LOG_BUILD ON
-                LOG_UPDATE ON
-                LOG_INSTALL ON
-                LOG_CONFIGURE OFF
-                LOG_OUTPUT_ON_FAILURE ON
-
-                # dependency
-                DEPENDS  yosys
-                )
-
-     # Synlig integration (manages Surelog and UHDM internally)                
-
-        # Synlig integration (manages Surelog and UHDM internally)
-        set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig)
-
-        # Clone Synlig repository and ensure submodules are synced before building
-        ExternalProject_Add(synlig
-            PREFIX "synlig"
-
-            # Clone the Synlig repository
-            GIT_REPOSITORY https://github.com/chipsalliance/synlig.git
-            GIT_TAG main
-            GIT_PROGRESS TRUE
-            GIT_SHALLOW TRUE
+    if (${SLANG_SYSTEMVERILOG})
+        set(SLANG_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-slang)
+        set(SLANG_BUILD_DIR ${CMAKE_BINARY_DIR}/yosys-slang)
+        set(YOSYS_CONFIG_EXECUTABLE ${CMAKE_BINARY_DIR}/bin/yosys-config CACHE STRING "Path to the yosys-config helper" FORCE)
+        execute_process(
+	        COMMAND git submodule update --init
+	        WORKING_DIRECTORY ${SLANG_SRC_DIR}
+	    )
+	    execute_process(
+	        COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive git\ submodule\ update\ --init
+	        WORKING_DIRECTORY ${SLANG_SRC_DIR}
+	    )
+        set(SLANG_FE "${SLANG_SRC_DIR}/src/slang_frontend.cc")
+        ExternalProject_Add(
+            yosys-slang
+            SOURCE_DIR ${SLANG_SRC_DIR}
+            BINARY_DIR ${SLANG_BUILD_DIR}
+
+            PATCH_COMMAND
+                ${CMAKE_COMMAND} -E echo "Patching slang_frontend.cc to disable UndrivenPass" &&
+                ${CMAKE_COMMAND} -DIN=${SLANG_FE} -P ${CMAKE_CURRENT_SOURCE_DIR}/patch_slang.cmake
+                
+
+            CONFIGURE_COMMAND
+                ${CMAKE_COMMAND} -DCMAKE_BUILD_TYPE=Release
+                -DYOSYS_CONFIG=${YOSYS_CONFIG_EXECUTABLE}
+                ${SLANG_SRC_DIR}
+            
+            BUILD_COMMAND ${CMAKE_COMMAND} --build ${SLANG_BUILD_DIR} -- -j${PROCESSOR_COUNT}
+            INSTALL_COMMAND ${CMAKE_COMMAND} --install ${SLANG_BUILD_DIR}
+            DEPENDS yosys
+        )
 
-            # Set source and build directories
-            SOURCE_DIR "${SYNLIG_SOURCE_DIR}"
-            BUILD_IN_SOURCE FALSE
-            INSTALL_DIR " "
+    #     set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
+    #     set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build)
+    #     set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins)
+
+    #     ExternalProject_Add(surelog
+    #             # root directory for Surelog project
+    #             PREFIX "surelog"
+
+    #             GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git
+    #             GIT_TAG v1.71
+    #             GIT_PROGRESS TRUE
+    #             GIT_SHALLOW TRUE
+
+    #             # setting source, build and install directories
+    #             SOURCE_DIR "${SURELOG_SOURCE_DIR}"
+    #             BUILD_IN_SOURCE FALSE
+    #             INSTALL_DIR "${SURELOG_BINARY_DIR}"
+
+    #             # define Surelog cache values
+    #             CMAKE_CACHE_ARGS
+    #             "-DCMAKE_BUILD_TYPE:STRING=Release"
+    #             "-DCMAKE_INSTALL_PREFIX:PATH=${CMAKE_BINARY_DIR}"
+    #             "-DCMAKE_POSITION_INDEPENDENT_CODE:BOOL=ON"
+    #             "-DCMAKE_WARN_DEPRECATED:BOOL=OFF"
+
+    #             # redirect logs to a logfile
+    #             LOG_BUILD ON
+    #             LOG_UPDATE ON
+    #             LOG_INSTALL ON
+    #             LOG_CONFIGURE OFF
+    #             LOG_OUTPUT_ON_FAILURE ON
+
+    #             # dependency
+    #             DEPENDS  yosys
+    #             )
+
+    #  # Synlig integration (manages Surelog and UHDM internally)                
+
+    #     # Synlig integration (manages Surelog and UHDM internally)
+    #     set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig)
+
+    #     # Clone Synlig repository and ensure submodules are synced before building
+    #     ExternalProject_Add(synlig
+    #         PREFIX "synlig"
+
+    #         # Clone the Synlig repository
+    #         GIT_REPOSITORY https://github.com/chipsalliance/synlig.git
+    #         GIT_TAG main
+    #         GIT_PROGRESS TRUE
+    #         GIT_SHALLOW TRUE
+
+    #         # Set source and build directories
+    #         SOURCE_DIR "${SYNLIG_SOURCE_DIR}"
+    #         BUILD_IN_SOURCE FALSE
+    #         INSTALL_DIR " "
             
-            # Sync submodules after cloning
+    #         # Sync submodules after cloning
             
             
-            UPDATE_COMMAND git submodule update --init --recursive third_party/surelog
-            WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR}
+    #         UPDATE_COMMAND git submodule update --init --recursive third_party/surelog
+    #         WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR}
             
-            BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT}
-            INSTALL_COMMAND ""
-            CONFIGURE_COMMAND ""
+    #         BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT}
+    #         INSTALL_COMMAND ""
+    #         CONFIGURE_COMMAND ""
             
-            # Pass necessary paths and set environment variables
-            CMAKE_CACHE_ARGS
-                "-DCMAKE_BUILD_TYPE:STRING=Release"
-                "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog"
-                "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys"
-                "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}"
-                "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build"
-                "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}"
+    #         # Pass necessary paths and set environment variables
+    #         CMAKE_CACHE_ARGS
+    #             "-DCMAKE_BUILD_TYPE:STRING=Release"
+    #             "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog"
+    #             "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys"
+    #             "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}"
+    #             "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build"
+    #             "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}"
             
-            LOG_BUILD ON
-            LOG_UPDATE ON
-            LOG_INSTALL ON
-            LOG_CONFIGURE OFF
-            LOG_OUTPUT_ON_FAILURE ON
-
-            # Ensure dependencies like Yosys are built first
-            DEPENDS yosys  # Ensure submodule sync runs before synlig build
-        )
+    #         LOG_BUILD ON
+    #         LOG_UPDATE ON
+    #         LOG_INSTALL ON
+    #         LOG_CONFIGURE OFF
+    #         LOG_OUTPUT_ON_FAILURE ON
+
+    #         # Ensure dependencies like Yosys are built first
+    #         DEPENDS yosys  # Ensure submodule sync runs before synlig build
+    #     )
 
     endif ()
 endif ()
diff --git a/libs/EXTERNAL/patch_slang.cmake b/libs/EXTERNAL/patch_slang.cmake
new file mode 100644
index 00000000000..81c8a2f392a
--- /dev/null
+++ b/libs/EXTERNAL/patch_slang.cmake
@@ -0,0 +1,9 @@
+if(NOT DEFINED IN)
+	message(FATAL_ERROR "patch_slang.cmake: IN (SLANG_FE) variable not set.")
+endif()
+file(READ "${IN}" SLANG_FRONTEND_CONTENTS)
+string(REPLACE "call(design, \"undriven\");" "// call(design, \"undriven\");" SLANG_PATCHED "${SLANG_FRONTEND_CONTENTS}")
+        if(NOT SLANG_FRONTEND_CONTENTS STREQUAL SLANG_PATCHED)
+            message(STATUS "Patching slang_frontend.cc to disable UndrivenPass")
+            file(WRITE "${IN}" "${SLANG_PATCHED}")
+        endif()
diff --git a/libs/EXTERNAL/yosys-slang b/libs/EXTERNAL/yosys-slang
new file mode 160000
index 00000000000..76b83eb5b73
--- /dev/null
+++ b/libs/EXTERNAL/yosys-slang
@@ -0,0 +1 @@
+Subproject commit 76b83eb5b73ba871797e6db7bc5fed10af380be4
diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl
index 24bae6877cc..81d4cc69410 100644
--- a/vtr_flow/misc/yosys/synthesis.tcl
+++ b/vtr_flow/misc/yosys/synthesis.tcl
@@ -1,19 +1,37 @@
 yosys -import
-
 plugin -i parmys
-yosys -import
 
 read_verilog -nomem2reg +/parmys/vtr_primitives.v
 setattr -mod -set keep_hierarchy 1 single_port_ram
 setattr -mod -set keep_hierarchy 1 dual_port_ram
+setattr -mod -set keep 1 dual_port_ram
 
 # synlig path error handling
-if {[catch {set synlig $::env(synlig_exe_path)} err]} {
-	puts "Error: $err"
-	puts "synlig_exe_path is not set"
+#if {[catch {set synlig $::env(synlig_exe_path)} err]} {
+#	puts "Error: $err"
+#	puts "synlig_exe_path is not set"
+#} else {
+#	set synlig $::env(synlig_exe_path)
+#	puts "Using parmys as partial mapper"
+#}
+
+# yosys-slang plugin error handling
+if {$env(PARSER) == "slang" } {
+	if {![info exists ::env(yosys_slang_path)]} {
+		puts "Error: $err"
+		puts "yosys_slang_path is not set"
+	} elseif {![file exists $::env(yosys_slang_path)]} {
+		error "Error: cannot find plugin at '$::env(yosys_slang_path)'. Run make with CMake param -DSLANG_SYSTEMVERILOG=ON to enable yosys-slang plugin."
+	} else {
+		plugin -i slang
+		yosys -import
+		puts "Using yosys-slang as yosys frontend"
+	}
+} elseif {$env(PARSER) == "default" } {
+	yosys -import
+	puts "Using Yosys read_verilog as yosys frontend"
 } else {
-	set synlig $::env(synlig_exe_path)
-	puts "Using parmys as partial mapper"
+	error "Invalid PARSER"
 }
 
 
@@ -25,15 +43,48 @@ if {[catch {set synlig $::env(synlig_exe_path)} err]} {
 
 parmys_arch -a QQQ
 
-if {$env(PARSER) == "surelog" } {
-	puts "Using Synlig read_uhdm command"
-	
-	exec $synlig -p "read_uhdm XXX"
-	
-} elseif {$env(PARSER) == "system-verilog" } {
-	puts "Using Synlig read_systemverilog "
-	exec $synlig -p "read_systemverilog XXX"
+#if {$env(PARSER) == "surelog" } {
+#	puts "Using Synlig read_uhdm command"
+#	exec $synlig -p "read_uhdm XXX"
 	
+#} elseif {$env(PARSER) == "system-verilog" } {
+#	puts "Using Synlig read_systemverilog "
+#	exec $synlig -p "read_systemverilog XXX"
+#	}
+
+if {$env(PARSER) == "slang" } {
+	# Create a file list containing the name(s) of file(s) \
+	# to read together with read_slang
+	set sv_files {}
+	set v_files {}
+	set readfile [file join [pwd] "filelist.txt"]
+	set fh [open $readfile "w"]
+	foreach f {XXX} {
+		set ext [string tolower [file extension $f]]
+		switch -- $ext {
+			.sv {
+				lappend $sv_files $f
+				puts $fh $f
+			}
+			.svh {
+				lappend $sv_files $f
+				puts $fh $f
+			}
+			.v {
+				error "Use default parser to parse .v files."
+			}
+			.vh {
+				error "Use default parser to parse .v files."
+			}
+		}
+	}
+	close $fh
+	#if {[llength $sv_files] > 0} {
+		#puts "Using Yosys read_slang command"
+		#read_slang -C $readfile
+	#}
+	puts "Using Yosys read_slang command"
+	read_slang -C $readfile
 } elseif {$env(PARSER) == "default" } {
 	puts "Using Yosys read_verilog command"
 	read_verilog -sv -nolatches XXX
@@ -74,13 +125,18 @@ techmap -map +/parmys/aldffe2dff.v
 opt -full
 
 # Separate options for Parmys execution (Verilog or SystemVerilog)
-if {$env(PARSER) == "default"} {
+if {$env(PARSER) == "default" || $env(PARSER) == "slang"} {
     # For Verilog, use -nopass for a simpler, faster flow
     parmys -a QQQ -nopass -c CCC YYY
-} elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} {
-    # For Synlig SystemVerilog, run additional passes to handle complexity
-    parmys -a QQQ -c CCC YYY
-}
+} 
+#elseif {$env(PARSER) == "slang"} {
+    # For Slang, run additional passes to handle complexity
+#    parmys -a QQQ -c CCC YYY
+#}
+#elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} {
+#    # For Synlig SystemVerilog, run additional passes to handle complexity
+#    parmys -a QQQ -c CCC YYY
+#}
 
 opt -full
 
@@ -95,4 +151,4 @@ stat
 
 hierarchy -check -auto-top -purge_lib
 
-write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ
\ No newline at end of file
+write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ
diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py
index ae0bd0a1c35..a7a8d8153de 100644
--- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py
+++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py
@@ -22,7 +22,7 @@
     ".ys": "RTLIL",
 }
 
-YOSYS_PARSERS = ["default", "surelog", "system-verilog"]
+YOSYS_PARSERS = ["default", "slang"]
 
 
 def create_circuits_list(main_circuit, include_files):
@@ -236,9 +236,9 @@ def run(
     # Set the synlig exe script path in the environment variable
     # (handle if it is not set or system-verilog OFF)
     try:
-        os.environ["synlig_exe_path"] = str(vtr.paths.synlig_exe_path)
+        os.environ["yosys_slang_path"] = str(vtr.paths.yosys_slang_path)
     except KeyError:
-        os.environ["synlig_exe_path"] = "/dummy/path"
+        os.environ["yosys_slang_path"] = "/dummy/path"
 
     # set the parser
     if parmys_args["parser"] in YOSYS_PARSERS:
@@ -246,7 +246,8 @@ def run(
         del parmys_args["parser"]
     else:
         raise vtr.VtrError(
-            "Invalid parser is specified for Yosys, available parsers are [{}]".format(
+            parmys_args["parser"]
+            + "Invalid parser is specified for Yosys. Parsers are [{}]".format(
                 " ".join(str(x) for x in YOSYS_PARSERS)
             )
         )
diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py
index 2ab1e4c31b5..344a79e5155 100644
--- a/vtr_flow/scripts/python_libs/vtr/paths.py
+++ b/vtr_flow/scripts/python_libs/vtr/paths.py
@@ -21,6 +21,7 @@
 yosys_exe_path = yosys_path / "yosys"
 yosys_tcl_path = vtr_flow_path / "misc" / "yosys"
 yosys_script_path = yosys_tcl_path / "synthesis.tcl"
+yosys_slang_path = root_path / "build" / "share" / "yosys" / "plugins" / "slang.so"
 
 # Synlig paths
 synlig_path = root_path / "build" / "bin" / "synlig_install"
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt
index 4c09466d341..2af1583c159 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt
@@ -46,4 +46,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements_fixed_chan_width.txt
 
 #Script parameters
-script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300
\ No newline at end of file
+script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt
index 5005a12aaca..f47770e46ec 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt
@@ -12,14 +12,14 @@ archs_dir=arch/timing
 
 
 # Add circuits to list to sweep
-#include_list_add=display_control.sv
-#include_list_add=timer.sv
-#include_list_add=debounce.sv
+include_list_add=display_control.sv
+include_list_add=timer.sv
+include_list_add=debounce.sv
 
 # Add circuits to list to sweep
-#circuit_list_add=button_controller.sv
+#circuit_list_add=flattened_button_controller.sv
 
-circuit_list_add=flattened_button_controller.sv
+circuit_list_add=button_controller.sv
 
 
 # Add architectures to list to sweep
@@ -35,4 +35,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements.txt
 
 #Script parameters
-script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog
+script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt
index c59221ce1d4..70c60b720f8 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt
@@ -32,4 +32,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements.txt
 
 #Script parameters
-script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog
+script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt
index c2c180dab1d..ee62c8c894a 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt
@@ -12,13 +12,14 @@ archs_dir=arch/timing
 
 
 # Add circuits to list to sweep
-#include_list_add=timer.sv
-#include_list_add=display_control.sv
-#include_list_add=time_counter.sv
-#include_list_add=modify_count.sv
+include_list_add=modify_count.sv
+include_list_add=display_control.sv
+include_list_add=time_counter.sv
+include_list_add=timer.sv
 
 # Add circuits to list to sweep
-circuit_list_add=flattened_timer.sv
+#circuit_list_add=flattened_timer.sv
+circuit_list_add=clock.sv
 
 
 # Add architectures to list to sweep
@@ -34,4 +35,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements.txt
 
 #Script parameters
-script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog
+script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt
new file mode 100644
index 00000000000..a7baf142692
--- /dev/null
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt
@@ -0,0 +1,37 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/system_verilog/koios_sv
+includes_dir=benchmarks/system_verilog/koios_sv
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+
+# Add circuits to list to sweep
+#include_list_add=display_control.sv
+#include_list_add=timer.sv
+#include_list_add=debounce.sv
+
+# Add circuits to list to sweep
+circuit_list_add=deepfreeze.style1.sv
+
+
+
+# Add architectures to list to sweep
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+#Script parameters
+script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt
index 509f77a6434..a073b4f2f6b 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt
@@ -1,3 +1,4 @@
 regression_tests/vtr_reg_system_verilog/f4pga_button_controller/
+#regression_tests/vtr_reg_system_verilog/koios_sv/
 regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/
 regression_tests/vtr_reg_system_verilog/f4pga_timer/