From 0de1df1b3cd9ee2b0de9a37f04602b01d1b037d5 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Wed, 10 Apr 2024 15:22:46 -0400 Subject: [PATCH 001/176] [Bison] Raised Minimum Bison Version from 3.0 to 3.3 Raised the minimum Bison version to 3.3 since deprecation warnings were showing up in libblifparse and libsdcparse which could not be resolved unless the Bison version was 3.3. --- libs/EXTERNAL/libblifparse/CMakeLists.txt | 2 +- libs/EXTERNAL/libblifparse/src/blif_parser.y | 6 +++--- libs/EXTERNAL/libsdcparse/CMakeLists.txt | 2 +- libs/EXTERNAL/libsdcparse/src/sdc_parser.y | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/libs/EXTERNAL/libblifparse/CMakeLists.txt b/libs/EXTERNAL/libblifparse/CMakeLists.txt index 714c54d775f..211eb7ec4ea 100644 --- a/libs/EXTERNAL/libblifparse/CMakeLists.txt +++ b/libs/EXTERNAL/libblifparse/CMakeLists.txt @@ -13,7 +13,7 @@ if(${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_CURRENT_SOURCE_DIR}) endif() #Flex and Bison are used to generate the parser -find_package(BISON REQUIRED 3.0) +find_package(BISON REQUIRED 3.3) find_package(FLEX REQUIRED) file(GLOB_RECURSE LIB_SOURCES src/blif*.cpp) diff --git a/libs/EXTERNAL/libblifparse/src/blif_parser.y b/libs/EXTERNAL/libblifparse/src/blif_parser.y index 2b51dd7cc7e..495d495b6d8 100644 --- a/libs/EXTERNAL/libblifparse/src/blif_parser.y +++ b/libs/EXTERNAL/libblifparse/src/blif_parser.y @@ -1,5 +1,5 @@ -/* C++ parsers require Bison 3 */ -%require "3.0" +/* C++ parsers require Bison 3.3 */ +%require "3.3" %language "C++" /* Write-out tokens header file */ @@ -34,7 +34,7 @@ %define api.namespace {blifparse} /* Name the parser class */ -%define parser_class_name {Parser} +%define api.parser.class {Parser} /* Match the flex prefix */ %define api.prefix {blifparse_} diff --git a/libs/EXTERNAL/libsdcparse/CMakeLists.txt b/libs/EXTERNAL/libsdcparse/CMakeLists.txt index 24a7b2973c8..5afc97f3117 100644 --- a/libs/EXTERNAL/libsdcparse/CMakeLists.txt +++ b/libs/EXTERNAL/libsdcparse/CMakeLists.txt @@ -13,7 +13,7 @@ if(${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_CURRENT_SOURCE_DIR}) endif() #Flex and Bison are used to generate the parser -find_package(BISON REQUIRED 3.0) +find_package(BISON REQUIRED 3.3) find_package(FLEX REQUIRED) file(GLOB_RECURSE LIB_SOURCES src/sdc*.cpp) diff --git a/libs/EXTERNAL/libsdcparse/src/sdc_parser.y b/libs/EXTERNAL/libsdcparse/src/sdc_parser.y index 1dadaee3745..686173392bf 100644 --- a/libs/EXTERNAL/libsdcparse/src/sdc_parser.y +++ b/libs/EXTERNAL/libsdcparse/src/sdc_parser.y @@ -1,5 +1,5 @@ -/* C++ parsers require Bison 3 */ -%require "3.0" +/* C++ parsers require Bison 3.3 */ +%require "3.3" %language "C++" /* Write-out tokens header file */ @@ -34,7 +34,7 @@ %define api.namespace {sdcparse} /* Name the parser class */ -%define parser_class_name {Parser} +%define api.parser.class {Parser} /* Match the flex prefix */ %define api.prefix {sdcparse_} From 06d02f4d266f580ddd367e4b45de0280b47acea3 Mon Sep 17 00:00:00 2001 From: Fahrican Kosar Date: Tue, 21 Jan 2025 08:07:38 -0500 Subject: [PATCH 002/176] more fixes for bitstream generation with flat router --- vpr/src/base/netlist_writer.cpp | 5 +- vpr/src/base/vpr_api.cpp | 31 +++++++ vpr/src/pack/post_routing_pb_pin_fixup.cpp | 1 + .../pack/sync_netlists_to_routing_flat.cpp | 84 +++++++++---------- vpr/src/route/annotate_routing.cpp | 14 +++- vpr/src/route/annotate_routing.h | 1 + 6 files changed, 88 insertions(+), 48 deletions(-) diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp index d8efdab5b42..e8b1ba333bf 100644 --- a/vpr/src/base/netlist_writer.cpp +++ b/vpr/src/base/netlist_writer.cpp @@ -1245,7 +1245,10 @@ class NetlistWriterVisitor : public NetlistVisitor { //Add the single output connection { - auto atom_net_id = top_pb_route[sink_cluster_pin_idx].atom_net_id; //Connected net in atom netlist + /* Check if the output is connected */ + AtomNetId atom_net_id = AtomNetId::INVALID(); + if (top_pb_route.count(sink_cluster_pin_idx)) + atom_net_id = top_pb_route[sink_cluster_pin_idx].atom_net_id; //Connected net in atom netlist std::string net; if (!atom_net_id) { diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 1e3a4c390e9..75a4d71e8e0 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -17,6 +17,7 @@ #include "FlatPlacementInfo.h" #include "cluster_util.h" +#include "physical_types.h" #include "verify_placement.h" #include "vpr_context.h" #include "vtr_assert.h" @@ -115,6 +116,13 @@ static void get_intercluster_switch_fanin_estimates(const t_vpr_setup& vpr_setup int* opin_switch_fanin, int* wire_switch_fanin, int* ipin_switch_fanin); + +/** Set all port equivalences in the architecture to NONE. This is used in the + * case of the flat router where port equivalence does not make sense. + * We could just keep it set and ignore it, but that prevents compatibility + * with OpenFPGA which takes it seriously. */ +static void unset_port_equivalences(DeviceContext& device_ctx); + /* Local subroutines end */ ///@brief Display general VPR information @@ -369,6 +377,25 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a device_ctx.pad_loc_type = vpr_setup->PlacerOpts.pad_loc_type; } +/** Port equivalence does not make sense during flat routing. + * Remove port equivalence from all ports in the architecture */ +static void unset_port_equivalences(DeviceContext& device_ctx){ + for(auto& physical_type: device_ctx.physical_tile_types){ + for(auto& sub_tile: physical_type.sub_tiles){ + for(auto& port: sub_tile.ports){ + port.equivalent = PortEquivalence::NONE; + } + } + } + for(auto& logical_type: device_ctx.logical_block_types){ + if(!logical_type.pb_type) + continue; + for(int i=0; inum_ports; i++){ + logical_type.pb_type->ports[i].equivalent = PortEquivalence::NONE; + } + } +} + bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { if (vpr_setup.exit_before_pack) { VTR_LOG_WARN("Exiting before packing as requested.\n"); @@ -425,6 +452,10 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { bool is_flat = vpr_setup.RouterOpts.flat_routing; const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + if (is_flat){ + VTR_LOG_WARN("Disabling port equivalence in the architecture since flat routing is enabled.\n"); + unset_port_equivalences(g_vpr_ctx.mutable_device()); + } RouteStatus route_status; { //Route route_status = vpr_route_flow(router_net_list, vpr_setup, arch, is_flat); diff --git a/vpr/src/pack/post_routing_pb_pin_fixup.cpp b/vpr/src/pack/post_routing_pb_pin_fixup.cpp index 78084d56df3..1d03ca7f74b 100644 --- a/vpr/src/pack/post_routing_pb_pin_fixup.cpp +++ b/vpr/src/pack/post_routing_pb_pin_fixup.cpp @@ -1034,6 +1034,7 @@ void sync_netlists_to_routing(const Netlist<>& net_list, /* Create net-to-rr_node mapping */ vtr::vector rr_node_nets = annotate_rr_node_nets(clustering_ctx, device_ctx, + atom_ctx, verbose); IntraLbPbPinLookup intra_lb_pb_pin_lookup(device_ctx.logical_block_types); diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 8aa54bb7f1a..403d0a722af 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -47,23 +47,6 @@ static void fixup_atom_pb_graph_pin_mapping(void); /* Function definitions */ -/** Is the clock net found in the routing results? - * (If not, clock_modeling is probably ideal and we should preserve clock routing while rebuilding.) */ -inline bool is_clock_net_routed(void){ - auto& atom_ctx = g_vpr_ctx.atom(); - auto& route_ctx = g_vpr_ctx.routing(); - - for(auto net_id: atom_ctx.nlist.nets()){ - auto& tree = route_ctx.route_trees[net_id]; - if(!tree) - continue; - if(route_ctx.is_clock_net[net_id]) /* Clock net has routing */ - return true; - } - - return false; -} - /** Get the ClusterBlockId for a given RRNodeId. */ inline ClusterBlockId get_cluster_block_from_rr_node(RRNodeId inode){ auto& device_ctx = g_vpr_ctx.device(); @@ -193,18 +176,16 @@ static void sync_pb_routes_to_routing(void){ auto& route_ctx = g_vpr_ctx.routing(); auto& rr_graph = device_ctx.rr_graph; - /* Was the clock net routed? */ - bool clock_net_is_routed = is_clock_net_routed(); - /* Clear out existing pb_routes: they were made by the intra cluster router and are invalid now */ for (ClusterBlockId clb_blk_id : cluster_ctx.clb_nlist.blocks()) { - /* If we don't have routing for the clock net, don't erase entries associated with a clock net. - * Otherwise we won't have data to rebuild them */ + /* Don't erase entries for nets without routing in place (clocks, globals...) */ std::vector pins_to_erase; auto& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; for(auto& [pin, pb_route]: pb_routes){ - if(clock_net_is_routed || !route_ctx.is_clock_net[pb_route.atom_net_id]) - pins_to_erase.push_back(pin); + /* No route tree: no routing in place, it is global or clock */ + if(!route_ctx.route_trees[ParentNetId(int(pb_route.atom_net_id))]) + continue; + pins_to_erase.push_back(pin); } for(int pin: pins_to_erase){ @@ -286,37 +267,37 @@ static void sync_clustered_netlist_to_routing(void){ auto& atom_ctx = g_vpr_ctx.mutable_atom(); auto& atom_lookup = atom_ctx.lookup; - bool clock_net_is_routed = is_clock_net_routed(); - /* 1. Remove all nets, pins and ports from the clustered netlist. - * If the clock net is not routed, don't remove entries for the clock net - * otherwise we won't have data to rebuild them. */ + * Do not remove entries for nets without an existing route tree, + * since we don't have the information to rebuild those parts. */ std::vector nets_to_remove; std::vector pins_to_remove; std::vector ports_to_remove; for(auto net_id: clb_netlist.nets()){ auto atom_net_id = atom_lookup.atom_net(net_id); - if(!clock_net_is_routed && route_ctx.is_clock_net[atom_net_id]) + if(!route_ctx.route_trees[ParentNetId(int(atom_net_id))]) continue; nets_to_remove.push_back(net_id); } - for(auto pin_id: clb_netlist.pins()){ - ClusterNetId clb_net_id = clb_netlist.pin_net(pin_id); - auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if(!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) - continue; - - pins_to_remove.push_back(pin_id); - } + /* Mark ports and pins for removal. Don't remove a port if + * it has at least one pin remaining */ for(auto port_id: clb_netlist.ports()){ - ClusterNetId clb_net_id = clb_netlist.port_net(port_id, 0); - auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if(!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) - continue; + size_t skipped_pins = 0; + + for(auto pin_id: clb_netlist.port_pins(port_id)){ + ClusterNetId clb_net_id = clb_netlist.pin_net(pin_id); + auto atom_net_id = atom_lookup.atom_net(clb_net_id); + if(atom_net_id && !route_ctx.route_trees[ParentNetId(int(atom_net_id))]){ + skipped_pins++; + }else{ + pins_to_remove.push_back(pin_id); + } + } - ports_to_remove.push_back(port_id); + if(!skipped_pins) // All pins have been removed, remove port + ports_to_remove.push_back(port_id); } /* ClusteredNetlist's iterators rely on internal lookups, so we mark for removal @@ -366,8 +347,7 @@ static void sync_clustered_netlist_to_routing(void){ * Due to how the route tree is traversed, all nodes until the next OPIN on the tile will * be under this OPIN, so this is valid (we don't need to get the branch explicitly) */ if(node_type == OPIN){ - std::string net_name; - net_name = atom_ctx.nlist.net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); + std::string net_name = atom_ctx.nlist.net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); clb_net_id = clb_netlist.create_net(net_name); atom_lookup.add_atom_clb_net(atom_net_id, clb_net_id); clb_nets_so_far++; @@ -375,6 +355,7 @@ static void sync_clustered_netlist_to_routing(void){ t_pb_graph_pin* pb_graph_pin = get_pb_graph_node_pin_from_block_pin(clb, pin_index); + /* Get or create port */ ClusterPortId port_id = clb_netlist.find_port(clb, pb_graph_pin->port->name); if(!port_id){ PortType port_type; @@ -390,6 +371,15 @@ static void sync_clustered_netlist_to_routing(void){ } PinType pin_type = node_type == OPIN ? PinType::DRIVER : PinType::SINK; + /* Pin already exists. This means a global was connected to here. */ + if (clb_netlist.port_pin(port_id, pb_graph_pin->pin_number)) { + VTR_LOG_WARN("Pin %s of block %s has a global or clock net" + " connected and it has a routing clash with the flat router." + " This may cause inconsistent results.\n", + pb_graph_pin->to_string().c_str(), + clb_netlist.block_name(clb).c_str()); + continue; + } ClusterPinId new_pin = clb_netlist.create_pin(port_id, pb_graph_pin->pin_number, clb_net_id, pin_type, pb_graph_pin->pin_count_in_cluster); clb_netlist.set_pin_net(new_pin, pin_type, clb_net_id); } @@ -431,6 +421,12 @@ static void fixup_atom_pb_graph_pin_mapping(void){ /* Find atom port from pbg pin's model port */ AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atb, atom_pbg_pin->port->model_port); + + /* Not an equivalent port, so no need to do fixup */ + if (atom_pbg_pin->port->equivalent != PortEquivalence::FULL) { + continue; + } + for(AtomPinId atom_pin: atom_ctx.nlist.port_pins(atom_port)){ /* Match net IDs from pb_route and atom netlist and connect in lookup */ if(pb_route.atom_net_id == atom_ctx.nlist.pin_net(atom_pin)){ diff --git a/vpr/src/route/annotate_routing.cpp b/vpr/src/route/annotate_routing.cpp index 42b798d4d02..f8f79df68fd 100644 --- a/vpr/src/route/annotate_routing.cpp +++ b/vpr/src/route/annotate_routing.cpp @@ -15,11 +15,13 @@ vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, const DeviceContext& device_ctx, + const AtomContext& atom_ctx, const bool& verbose) { size_t counter = 0; vtr::ScopedStartFinishTimer timer("Annotating rr_node with routed nets"); const auto& rr_graph = device_ctx.rr_graph; + auto& atom_lookup = atom_ctx.lookup; auto& netlist = cluster_ctx.clb_nlist; vtr::vector rr_node_nets; @@ -47,11 +49,17 @@ vtr::vector annotate_rr_node_nets(const ClusteringContex * In some routing architectures, node capacity is more than 1 * which allows a node to be mapped by multiple nets * Therefore, the sanity check should focus on the nodes - * whose capacity is 1 - */ + * whose capacity is 1. + * Flat routing may create two clustered nets from a single + * atom net if the atom net ended up exiting the block through + * different pins. Those clustered nets will point to the same + * atom net routing. Ignore clashes if that is the case. */ + AtomNetId my_atom = atom_lookup.atom_net(net_id); + AtomNetId existing_atom = atom_lookup.atom_net(rr_node_nets[rr_node]); if ((rr_node_nets[rr_node]) && (1 == rr_graph.node_capacity(rr_node)) - && (net_id != rr_node_nets[rr_node])) { + && (net_id != rr_node_nets[rr_node]) + && (my_atom != existing_atom)) { VPR_FATAL_ERROR(VPR_ERROR_ANALYSIS, "Detect two nets '%s' and '%s' that are mapped to the same rr_node '%ld'!\n%s\n", netlist.net_name(net_id).c_str(), diff --git a/vpr/src/route/annotate_routing.h b/vpr/src/route/annotate_routing.h index cf548e1e0fe..3d6d87b2575 100644 --- a/vpr/src/route/annotate_routing.h +++ b/vpr/src/route/annotate_routing.h @@ -12,6 +12,7 @@ *******************************************************************/ vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, const DeviceContext& device_ctx, + const AtomContext& atom_ctx, const bool& verbose); #endif From fd2797f72efefd243a58075c36c61bb1e81d2e23 Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Mon, 3 Mar 2025 09:55:54 -0500 Subject: [PATCH 003/176] [Router] Upstream Fine-Grained Parallel Router (FPT'24) Upstreamed the fine-grained parallel router implementation into the VTR master. The original branch is https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/mq-parallel-router. Modified the MultiQueue (SPAA'24) implementation and integrated it into the VTR codebase. --- utils/route_diag/src/main.cpp | 3 +- vpr/src/base/SetupVPR.cpp | 6 + vpr/src/base/ShowSetup.cpp | 6 + vpr/src/base/read_options.cpp | 30 + vpr/src/base/read_options.h | 6 + vpr/src/base/vpr_types.h | 6 + vpr/src/route/DecompNetlistRouter.h | 8 +- vpr/src/route/DecompNetlistRouter.tpp | 4 +- vpr/src/route/ParallelNetlistRouter.h | 8 +- vpr/src/route/ParallelNetlistRouter.tpp | 4 +- vpr/src/route/SerialNetlistRouter.h | 49 +- vpr/src/route/SerialNetlistRouter.tpp | 6 +- vpr/src/route/connection_router_interface.h | 2 + vpr/src/route/d_ary_heap.h | 2 + vpr/src/route/multi_queue_d_ary_heap.h | 127 ++ vpr/src/route/multi_queue_d_ary_heap.tpp | 435 +++++++ vpr/src/route/netlist_routers.h | 3 +- vpr/src/route/parallel_connection_router.cpp | 1084 +++++++++++++++++ vpr/src/route/parallel_connection_router.h | 429 +++++++ vpr/src/route/partition_tree.cpp | 2 +- vpr/src/route/partition_tree.h | 4 +- vpr/src/route/route_net.tpp | 2 + vpr/src/route/router_delay_profiling.cpp | 6 +- vpr/src/route/router_delay_profiling.h | 4 +- ...outer.cpp => serial_connection_router.cpp} | 42 +- ...on_router.h => serial_connection_router.h} | 22 +- vpr/test/test_connection_router.cpp | 5 +- 27 files changed, 2234 insertions(+), 71 deletions(-) create mode 100644 vpr/src/route/multi_queue_d_ary_heap.h create mode 100644 vpr/src/route/multi_queue_d_ary_heap.tpp create mode 100644 vpr/src/route/parallel_connection_router.cpp create mode 100644 vpr/src/route/parallel_connection_router.h rename vpr/src/route/{connection_router.cpp => serial_connection_router.cpp} (96%) rename vpr/src/route/{connection_router.h => serial_connection_router.h} (95%) diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index 6812b5bc881..a0fb1616edd 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -97,7 +97,8 @@ static void do_one_route(const Netlist<>& net_list, segment_inf, is_flat); - ConnectionRouter router( + // TODO: adding tests for parallel connection router + SerialConnectionRouter router( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 09f44326899..93b52d7397e 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -433,6 +433,12 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->astar_fac = Options.astar_fac; RouterOpts->astar_offset = Options.astar_offset; RouterOpts->router_profiler_astar_fac = Options.router_profiler_astar_fac; + RouterOpts->enable_parallel_connection_router = Options.enable_parallel_connection_router; + RouterOpts->post_target_prune_fac = Options.post_target_prune_fac; + RouterOpts->post_target_prune_offset = Options.post_target_prune_offset; + RouterOpts->multi_queue_num_threads = Options.multi_queue_num_threads; + RouterOpts->multi_queue_num_queues = Options.multi_queue_num_queues; + RouterOpts->multi_queue_direct_draining = Options.multi_queue_direct_draining; RouterOpts->bb_factor = Options.bb_factor; RouterOpts->criticality_exp = Options.criticality_exp; RouterOpts->max_criticality = Options.max_criticality; diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index 9b8af556c8d..beb4d136f4a 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -376,6 +376,12 @@ static void ShowRouterOpts(const t_router_opts& RouterOpts) { VTR_LOG("RouterOpts.astar_fac: %f\n", RouterOpts.astar_fac); VTR_LOG("RouterOpts.astar_offset: %f\n", RouterOpts.astar_offset); VTR_LOG("RouterOpts.router_profiler_astar_fac: %f\n", RouterOpts.router_profiler_astar_fac); + VTR_LOG("RouterOpts.enable_parallel_connection_router: %s\n", RouterOpts.enable_parallel_connection_router ? "true" : "false"); + VTR_LOG("RouterOpts.post_target_prune_fac: %f\n", RouterOpts.post_target_prune_fac); + VTR_LOG("RouterOpts.post_target_prune_offset: %f\n", RouterOpts.post_target_prune_offset); + VTR_LOG("RouterOpts.multi_queue_num_threads: %d\n", RouterOpts.multi_queue_num_threads); + VTR_LOG("RouterOpts.multi_queue_num_queues: %d\n", RouterOpts.multi_queue_num_queues); + VTR_LOG("RouterOpts.multi_queue_direct_draining: %s\n", RouterOpts.multi_queue_direct_draining ? "true" : "false"); VTR_LOG("RouterOpts.criticality_exp: %f\n", RouterOpts.criticality_exp); VTR_LOG("RouterOpts.max_criticality: %f\n", RouterOpts.max_criticality); VTR_LOG("RouterOpts.init_wirelength_abort_threshold: %f\n", RouterOpts.init_wirelength_abort_threshold); diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 5803f05f896..7cfb3078fd2 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -2549,6 +2549,36 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("1.2") .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.enable_parallel_connection_router, "--enable_parallel_connection_router") + .help("TODO") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.post_target_prune_fac, "--post_target_prune_fac") + .help("TODO") + .default_value("1.2") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.post_target_prune_offset, "--post_target_prune_offset") + .help("TODO") + .default_value("0.0") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.multi_queue_num_threads, "--multi_queue_num_threads") + .help("TODO") + .default_value("1") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.multi_queue_num_queues, "--multi_queue_num_queues") + .help("TODO") + .default_value("2") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.multi_queue_direct_draining, "--multi_queue_direct_draining") + .help("TODO") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.max_criticality, "--max_criticality") .help( "Sets the maximum fraction of routing cost derived from delay (vs routability) for any net." diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 9f9d1242e13..e133ef3f6cf 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -226,6 +226,12 @@ struct t_options { argparse::ArgValue astar_fac; argparse::ArgValue astar_offset; argparse::ArgValue router_profiler_astar_fac; + argparse::ArgValue enable_parallel_connection_router; + argparse::ArgValue post_target_prune_fac; + argparse::ArgValue post_target_prune_offset; + argparse::ArgValue multi_queue_num_threads; + argparse::ArgValue multi_queue_num_queues; + argparse::ArgValue multi_queue_direct_draining; argparse::ArgValue max_criticality; argparse::ArgValue criticality_exp; argparse::ArgValue router_init_wirelength_abort_threshold; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 91863b33fe2..3021a1373ba 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1191,6 +1191,12 @@ struct t_router_opts { float astar_fac; float astar_offset; float router_profiler_astar_fac; + bool enable_parallel_connection_router; + float post_target_prune_fac; + float post_target_prune_offset; + int multi_queue_num_threads; + int multi_queue_num_queues; + bool multi_queue_direct_draining; float max_criticality; float criticality_exp; float init_wirelength_abort_threshold; diff --git a/vpr/src/route/DecompNetlistRouter.h b/vpr/src/route/DecompNetlistRouter.h index a41d656c240..e670bc5597d 100644 --- a/vpr/src/route/DecompNetlistRouter.h +++ b/vpr/src/route/DecompNetlistRouter.h @@ -85,11 +85,11 @@ class DecompNetlistRouter : public NetlistRouter { /** A single task to route nets inside a PartitionTree node and add tasks for its child nodes to task group \p g. */ void route_partition_tree_node(tbb::task_group& g, PartitionTreeNode& node); - ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + SerialConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); - return ConnectionRouter( + return SerialConnectionRouter( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -101,8 +101,8 @@ class DecompNetlistRouter : public NetlistRouter { } /* Context fields. Most of them will be forwarded to route_net (see route_net.tpp) */ - /** Per-thread storage for ConnectionRouters. */ - tbb::enumerable_thread_specific> _routers_th; + /** Per-thread storage for SerialConnectionRouter. */ + tbb::enumerable_thread_specific> _routers_th; const Netlist<>& _net_list; const t_router_opts& _router_opts; CBRR& _connections_inf; diff --git a/vpr/src/route/DecompNetlistRouter.tpp b/vpr/src/route/DecompNetlistRouter.tpp index 47de291a14c..6a774ecbb1d 100644 --- a/vpr/src/route/DecompNetlistRouter.tpp +++ b/vpr/src/route/DecompNetlistRouter.tpp @@ -204,12 +204,12 @@ void DecompNetlistRouter::route_partition_tree_node(tbb::task_group& g route_ctx.route_bb[net_id], false); if (!flags.success && !flags.retry_with_full_bb) { - /* Disconnected RRG and ConnectionRouter doesn't think growing the BB will work */ + /* Disconnected RRG and SerialConnectionRouter doesn't think growing the BB will work */ _results_th.local().is_routable = false; return; } if (flags.retry_with_full_bb) { - /* ConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ + /*SerialConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ route_ctx.route_bb[net_id] = full_device_bb(); _results_th.local().bb_updated_nets.push_back(net_id); /* Disable decomposition for nets like this: they're already problematic */ diff --git a/vpr/src/route/ParallelNetlistRouter.h b/vpr/src/route/ParallelNetlistRouter.h index e77fdf8344e..68b240321b2 100644 --- a/vpr/src/route/ParallelNetlistRouter.h +++ b/vpr/src/route/ParallelNetlistRouter.h @@ -15,7 +15,7 @@ #include /** Parallel impl for NetlistRouter. - * Holds enough context members to glue together ConnectionRouter and net routing functions, + * Holds enough context members to glue together SerialConnectionRouter and net routing functions, * such as \ref route_net. Keeps the members in thread-local storage where needed, * i.e. ConnectionRouters and RouteIterResults-es. * See \ref route_net. */ @@ -62,11 +62,11 @@ class ParallelNetlistRouter : public NetlistRouter { /** A single task to route nets inside a PartitionTree node and add tasks for its child nodes to task group \p g. */ void route_partition_tree_node(tbb::task_group& g, PartitionTreeNode& node); - ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + SerialConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); - return ConnectionRouter( + return SerialConnectionRouter( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -79,7 +79,7 @@ class ParallelNetlistRouter : public NetlistRouter { /* Context fields. Most of them will be forwarded to route_net (see route_net.tpp) */ /** Per-thread storage for ConnectionRouters. */ - tbb::enumerable_thread_specific> _routers_th; + tbb::enumerable_thread_specific> _routers_th; const Netlist<>& _net_list; const t_router_opts& _router_opts; CBRR& _connections_inf; diff --git a/vpr/src/route/ParallelNetlistRouter.tpp b/vpr/src/route/ParallelNetlistRouter.tpp index 1268ed6030e..fa42c882929 100644 --- a/vpr/src/route/ParallelNetlistRouter.tpp +++ b/vpr/src/route/ParallelNetlistRouter.tpp @@ -79,12 +79,12 @@ void ParallelNetlistRouter::route_partition_tree_node(tbb::task_group& route_ctx.route_bb[net_id]); if (!flags.success && !flags.retry_with_full_bb) { - /* Disconnected RRG and ConnectionRouter doesn't think growing the BB will work */ + /* Disconnected RRG and SerialConnectionRouter doesn't think growing the BB will work */ _results_th.local().is_routable = false; return; } if (flags.retry_with_full_bb) { - /* ConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ + /* SerialConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ route_ctx.route_bb[net_id] = full_device_bb(); _results_th.local().bb_updated_nets.push_back(net_id); continue; diff --git a/vpr/src/route/SerialNetlistRouter.h b/vpr/src/route/SerialNetlistRouter.h index 352de125b68..67df5130ebd 100644 --- a/vpr/src/route/SerialNetlistRouter.h +++ b/vpr/src/route/SerialNetlistRouter.h @@ -3,6 +3,8 @@ /** @file Serial case for \ref NetlistRouter: just loop through nets */ #include "netlist_routers.h" +#include "serial_connection_router.h" +#include "parallel_connection_router.h" template class SerialNetlistRouter : public NetlistRouter { @@ -20,7 +22,7 @@ class SerialNetlistRouter : public NetlistRouter { const RoutingPredictor& routing_predictor, const vtr::vector>>& choking_spots, bool is_flat) - : _router(_make_router(router_lookahead, is_flat)) + : _router(_make_router(router_lookahead, router_opts, is_flat)) , _net_list(net_list) , _router_opts(router_opts) , _connections_inf(connections_inf) @@ -32,7 +34,9 @@ class SerialNetlistRouter : public NetlistRouter { , _routing_predictor(routing_predictor) , _choking_spots(choking_spots) , _is_flat(is_flat) {} - ~SerialNetlistRouter() {} + ~SerialNetlistRouter() { + delete _router; + } RouteIterResults route_netlist(int itry, float pres_fac, float worst_neg_slack); void handle_bb_updated_nets(const std::vector& nets); @@ -40,22 +44,41 @@ class SerialNetlistRouter : public NetlistRouter { void set_timing_info(std::shared_ptr timing_info); private: - ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + ConnectionRouterInterface *_make_router(const RouterLookahead* router_lookahead, + const t_router_opts& router_opts, + bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); - return ConnectionRouter( - device_ctx.grid, - *router_lookahead, - device_ctx.rr_graph.rr_nodes(), - &device_ctx.rr_graph, - device_ctx.rr_rc_data, - device_ctx.rr_graph.rr_switch(), - route_ctx.rr_node_route_inf, - is_flat); + if (!router_opts.enable_parallel_connection_router) { + // Serial Connection Router + return new SerialConnectionRouter( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat); + } else { + // Parallel Connection Router + return new ParallelConnectionRouter( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat, + router_opts.multi_queue_num_threads, + router_opts.multi_queue_num_queues, + router_opts.multi_queue_direct_draining); + } } /* Context fields */ - ConnectionRouter _router; + ConnectionRouterInterface *_router; const Netlist<>& _net_list; const t_router_opts& _router_opts; CBRR& _connections_inf; diff --git a/vpr/src/route/SerialNetlistRouter.tpp b/vpr/src/route/SerialNetlistRouter.tpp index 63497d7d394..b84acfbd58f 100644 --- a/vpr/src/route/SerialNetlistRouter.tpp +++ b/vpr/src/route/SerialNetlistRouter.tpp @@ -22,7 +22,7 @@ inline RouteIterResults SerialNetlistRouter::route_netlist(int itry, f for (size_t inet = 0; inet < sorted_nets.size(); inet++) { ParentNetId net_id = sorted_nets[inet]; NetResultFlags flags = route_net( - _router, + *_router, _net_list, net_id, itry, @@ -42,7 +42,7 @@ inline RouteIterResults SerialNetlistRouter::route_netlist(int itry, f route_ctx.route_bb[net_id]); if (!flags.success && !flags.retry_with_full_bb) { - /* Disconnected RRG and ConnectionRouter doesn't think growing the BB will work */ + /* Disconnected RRG and SerialConnectionRouter doesn't think growing the BB will work */ out.is_routable = false; return out; } @@ -74,7 +74,7 @@ void SerialNetlistRouter::handle_bb_updated_nets(const std::vector void SerialNetlistRouter::set_rcv_enabled(bool x) { - _router.set_rcv_enabled(x); + _router->set_rcv_enabled(x); } template diff --git a/vpr/src/route/connection_router_interface.h b/vpr/src/route/connection_router_interface.h index 62111edc285..6c3af9d0f69 100644 --- a/vpr/src/route/connection_router_interface.h +++ b/vpr/src/route/connection_router_interface.h @@ -24,6 +24,8 @@ struct t_conn_cost_params { float criticality = 1.; float astar_fac = 1.2; float astar_offset = 0.f; + float post_target_prune_fac = 1.2f; + float post_target_prune_offset = 0.f; float bend_cost = 1.; float pres_fac = 1.; const t_conn_delay_budget* delay_budget = nullptr; diff --git a/vpr/src/route/d_ary_heap.h b/vpr/src/route/d_ary_heap.h index 5ac59f1eef2..c42a3356598 100644 --- a/vpr/src/route/d_ary_heap.h +++ b/vpr/src/route/d_ary_heap.h @@ -21,6 +21,8 @@ template class DAryHeap : public HeapInterface { public: + static constexpr unsigned arg_D = D; + using priority_queue = customized_d_ary_priority_queue, HeapNodeComparator>; DAryHeap() {} diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h new file mode 100644 index 00000000000..d81544135a3 --- /dev/null +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -0,0 +1,127 @@ +/******************************************************************** + * MultiQueue Implementation + * + * Originally authored by Guozheng Zhang, Gilead Posluns, and Mark C. Jeffrey + * Published at the 36th ACM Symposium on Parallelism in Algorithms and + * Architectures (SPAA), June 2024 + * + * Original source: https://github.com/mcj-group/cps + * + * This implementation has been modified from the original to: + * - Support queue draining functionality + * - Enable integration with the VTR project + * + * The MultiQueue data structure provides an efficient concurrent priority + * queue implementation designed for parallel processing applications. + * + * Modified: February 2025 + ********************************************************************/ + +#ifndef _MULTI_QUEUE_D_ARY_HEAP_H +#define _MULTI_QUEUE_D_ARY_HEAP_H + +#include + +#include "device_grid.h" +#include "heap_type.h" +#include "multi_queue_d_ary_heap.tpp" + +using MQHeapNode = std::tuple; + +// FIXME: use unified heap node struct and comparator in heap_type.h +struct MQHeapNodeTupleComparator { + bool operator()(const MQHeapNode& u, const MQHeapNode& v) { + return std::get<0>(u) > std::get<0>(v); + } +}; + +template +class MultiQueueDAryHeap { + public: + using MQ_IO = MultiQueueIO; + + MultiQueueDAryHeap() { + pq_ = new MQ_IO(2, 1, 0); // Serial (#threads=1, #queues=2) by default + } + + MultiQueueDAryHeap(size_t num_threads, size_t num_queues) { + pq_ = new MQ_IO(num_queues, num_threads, 0 /*Dont care (batch size for only popBatch)*/); + } + + ~MultiQueueDAryHeap() { + delete pq_; + } + + void init_heap(const DeviceGrid& grid) { + (void)grid; + // TODO: Reserve storage for MQ_IO + } + + bool try_pop(HeapNode& heap_node) { + auto tmp = pq_->tryPop(); + if (!tmp) { + return false; + } else { + uint32_t node_id; + std::tie(heap_node.prio, node_id) = tmp.get(); // FIXME: eliminate type cast by modifying MQ_IO + heap_node.node = RRNodeId(node_id); + return true; + } + } + + void add_to_heap(const HeapNode& heap_node) { + HeapNodePriority prio = heap_node.prio; + uint32_t node = size_t(heap_node.node); + pq_->push({prio, node}); + } + + void push_back(const HeapNode& heap_node) { + HeapNodePriority prio = heap_node.prio; + uint32_t node = size_t(heap_node.node); + pq_->push({prio, node}); // FIXME: add to heap without maintaining the heap property + } + + void build_heap() { + // FIXME: restore the heap property after pushing back nodes + } + + bool is_valid() const { + return true; // FIXME: checking if the heap property is maintained or not + } + + void empty_heap() { + pq_->reset(); // TODO: check if adding clear function for MQ_IO is necessary + } + + bool is_empty_heap() const { + return (bool)(pq_->empty()); + } + + uint64_t getNumPushes() const { + return pq_->getNumPushes(); + } + + uint64_t getNumPops() const { + return pq_->getNumPops(); + } + + uint64_t getHeapOccupancy() const { + return pq_->getQueueOccupancy(); + } + + void reset() { + pq_->reset(); + } + +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + void setMinPrioForPop(const HeapNodePriority& minPrio) { + pq_->setMinPrioForPop(minPrio); + } +#endif + + private: + MQ_IO *pq_; +}; + + +#endif \ No newline at end of file diff --git a/vpr/src/route/multi_queue_d_ary_heap.tpp b/vpr/src/route/multi_queue_d_ary_heap.tpp new file mode 100644 index 00000000000..059689a0693 --- /dev/null +++ b/vpr/src/route/multi_queue_d_ary_heap.tpp @@ -0,0 +1,435 @@ +/******************************************************************** + * MultiQueue Implementation + * + * Originally authored by Guozheng Zhang, Gilead Posluns, and Mark C. Jeffrey + * Published at the 36th ACM Symposium on Parallelism in Algorithms and + * Architectures (SPAA), June 2024 + * + * Original source: https://github.com/mcj-group/cps + * + * This implementation and interface has been modified from the original to: + * - Support queue draining functionality + * - Enable integration with the VTR project + * + * The MultiQueue data structure provides an efficient concurrent priority + * queue implementation designed for parallel processing applications. + * + * Modified: February 2025 + ********************************************************************/ + +#pragma once + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "d_ary_heap.tpp" + +#define CACHELINE 64 + +// #define PERF 1 +#define MQ_IO_ENABLE_CLEAR_FOR_POP + +template< + unsigned D, + typename PQElement, + typename Comparator, + typename PrioType +> +class MultiQueueIO { + using PQ = customized_d_ary_priority_queue, Comparator>; + Comparator compare; + + // Special value used to signify that there is no 'min' element in a PQ + // container. The user should ensure that they do not use this priority + // while using the MQ. + static constexpr PrioType EMPTY_PRIO = std::numeric_limits::max(); + + struct PQContainer { + uint64_t pushes = 0; + uint64_t pops = 0; + PQ pq; + std::atomic_flag queueLock = ATOMIC_FLAG_INIT; + std::atomic min{EMPTY_PRIO}; + + void lock() { while(queueLock.test_and_set(std::memory_order_acquire)); } + bool try_lock() { return queueLock.test_and_set(std::memory_order_acquire); } + void unlock() { queueLock.clear(std::memory_order_release); } + + } __attribute__((aligned (CACHELINE))); + + std::vector< + PQContainer, + boost::alignment::aligned_allocator + > queues; + uint64_t NUM_QUEUES; + + // Termination: + // - numIdle records the number of threads that believe + // there are no more work to do. + // -numEmpty records number of queues that are empty + uint64_t threadNum; + std::atomic numIdle{0}; + std::atomic numEmpty; +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + std::atomic minPrioForPop{std::numeric_limits::max()}; +#endif + + uint64_t batchSize; + + public: + + MultiQueueIO(uint64_t numQueues, uint64_t numThreads, uint64_t batch) + : queues(numQueues) + , NUM_QUEUES(numQueues) + , threadNum(numThreads) + , numEmpty(numQueues) + , batchSize(batch) {} + +#ifdef PERF + uint64_t __attribute__ ((noinline)) ThreadLocalRandom() { +#else + uint64_t ThreadLocalRandom() { +#endif + // static thread_local std::mt19937_64 generator; + // std::uniform_real_distribution<> distribution(min,max); + // return distribution(generator); + static uint64_t modMask = NUM_QUEUES - 1; + static thread_local uint64_t x = pthread_self(); + uint64_t z = (x += UINT64_C(0x9E3779B97F4A7C15)); + z = (z ^ (z >> 30)) * UINT64_C(0xBF58476D1CE4E5B9); + z = (z ^ (z >> 27)) * UINT64_C(0x94D049BB133111EB); + return (z ^ (z >> 31)) & modMask; + } + +#ifdef PERF + void __attribute__ ((noinline)) pushInt(uint64_t queue, PQElement item) { + queues[queue].pq.push(item); + } +#endif + +#ifdef PERF + void __attribute__ ((noinline)) push(PQElement item) { +#else + inline void push(PQElement item) { +#endif + uint64_t queue; + while (true) { + queue = ThreadLocalRandom(); + if (!queues[queue].try_lock()) break; + } + auto& q = queues[queue]; + q.pushes++; + if (q.pq.empty()) + numEmpty.fetch_sub(1, std::memory_order_relaxed); +#ifdef PERF + pushInt(queue, item); +#else + q.pq.push(item); +#endif + q.min.store( + q.pq.size() > 0 + ? std::get<0>(q.pq.top()) + : EMPTY_PRIO, + std::memory_order_release + ); + q.unlock(); + } + +#ifdef PERF + void __attribute__ ((noinline)) pushBatch(uint64_t size, PQElement *items) { +#else + inline void pushBatch(uint64_t size, PQElement *items) { +#endif + uint64_t queue; + while (true) { + queue = ThreadLocalRandom(); + if (!queues[queue].try_lock()) break; + } + auto& q = queues[queue]; + q.pushes += size; + if (q.pq.empty()) + numEmpty.fetch_sub(1, std::memory_order_relaxed); + for (uint64_t i = 0; i < size; i++) { +#ifdef PERF + pushInt(queue, items[i]); +#else + q.pq.push(items[i]); +#endif + } + q.min.store( + q.pq.size() > 0 + ? std::get<0>(q.pq.top()) + : EMPTY_PRIO, + std::memory_order_release + ); + q.unlock(); + } + + // Simplified Termination detection idea from the 2021 MultiQueue paper: + // Repeatedly try popping and stop when numIdle >= threadNum, + // That is, stop when all threads agree that there are no more work +#ifdef PERF + boost::optional __attribute__ ((noinline)) tryPop() { +#else + inline boost::optional tryPop() { +#endif + auto item = pop(); + if (item) return item; + + // increment count and keep on trying to pop + uint64_t num = numIdle.fetch_add(1, std::memory_order_relaxed) + 1; + do { + item = pop(); + if (item) break; + if (num >= threadNum) return boost::none; + + num = numIdle.load(std::memory_order_relaxed); + + } while (true); + + numIdle.fetch_sub(1, std::memory_order_relaxed); + return item; + } + +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + inline void setMinPrioForPop(PrioType newMinPrio) { + PrioType oldMinPrio = minPrioForPop.load(std::memory_order_relaxed); + while (compare({oldMinPrio, 0}, {newMinPrio, 0}) /* old > new */ && + !minPrioForPop.compare_exchange_weak(oldMinPrio, newMinPrio)) ; + } +#endif + +#ifdef PERF + boost::optional __attribute__ ((noinline)) pop() { +#else + inline boost::optional pop() { +#endif + uint64_t poppingQueue = NUM_QUEUES; + while (true) { + // Pick the higher priority max of queue i and j + uint64_t i = ThreadLocalRandom(); + uint64_t j = ThreadLocalRandom(); + while (j == i) { + j = ThreadLocalRandom(); + } + + PrioType minI = queues[i].min.load(std::memory_order_acquire); + PrioType minJ = queues[j].min.load(std::memory_order_acquire); + + if (minI == EMPTY_PRIO && minJ == EMPTY_PRIO) { + uint64_t emptyQueues = numEmpty.load(std::memory_order_relaxed); + if (emptyQueues >= queues.size()) break; + else continue; + } + + if (minI != EMPTY_PRIO && minJ != EMPTY_PRIO) { + poppingQueue = compare({minJ, 0}, {minI, 0}) ? i : j; + } else if (minJ == EMPTY_PRIO) { + poppingQueue = i; + } else { + poppingQueue = j; + } + if (queues[poppingQueue].try_lock()) continue; + auto& q = queues[poppingQueue]; + if (!q.pq.empty()) { +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + PrioType minPrio = minPrioForPop.load(std::memory_order_acquire); + if (compare(q.pq.top(), {minPrio, 0})) { + q.pq.clear(); + // do not add `q.pops` on purpose + numEmpty.fetch_add(1, std::memory_order_relaxed); + q.min.store(EMPTY_PRIO, std::memory_order_release); + } else { +#endif + PQElement retItem = q.pq.top(); + q.pq.pop(); + q.pops++; + if (q.pq.empty()) + numEmpty.fetch_add(1, std::memory_order_relaxed); + q.min.store( + q.pq.size() > 0 + ? std::get<0>(q.pq.top()) + : EMPTY_PRIO, + std::memory_order_release + ); + q.unlock(); + return retItem; +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + } +#endif + } + q.unlock(); + } + return boost::none; + } + +#ifdef PERF + boost::optional __attribute__ ((noinline)) tryPopBatch(PQElement* ret) { +#else + inline boost::optional tryPopBatch(PQElement* ret) { +#endif + auto item = popBatch(ret); + if (item) return item; + + // increment count and keep on trying to pop + uint64_t num = numIdle.fetch_add(1, std::memory_order_relaxed) + 1; + do { + item = popBatch(ret); + if (item) break; + if (num >= threadNum) return boost::none; + + num = numIdle.load(std::memory_order_relaxed); + + } while (true); + + numIdle.fetch_sub(1, std::memory_order_relaxed); + return item; + } + +#ifdef PERF + void __attribute__ ((noinline)) popInt(uint64_t queue, PQElement *ret) { + auto& q = queues[queue]; + *ret = q.pq.top(); + q.pq.pop(); + } +#endif + + +#ifdef PERF + boost::optional __attribute__ ((noinline)) popBatch(PQElement* ret) { +#else + inline boost::optional popBatch(PQElement* ret) { +#endif + uint64_t poppingQueue = NUM_QUEUES; + while (true) { + // Pick the higher priority max of queue i and j + uint64_t i = ThreadLocalRandom(); + uint64_t j = ThreadLocalRandom(); + while (j == i) { + j = ThreadLocalRandom(); + } + + PrioType minI = queues[i].min.load(std::memory_order_acquire); + PrioType minJ = queues[j].min.load(std::memory_order_acquire); + + if (minI == EMPTY_PRIO && minJ == EMPTY_PRIO) { + uint64_t emptyQueues = numEmpty.load(std::memory_order_relaxed); + if (emptyQueues >= queues.size()) break; + else continue; + } + + if (minI != EMPTY_PRIO && minJ != EMPTY_PRIO) { + poppingQueue = compare({minJ, 0}, {minI, 0}) ? i : j; + } else if (minJ == EMPTY_PRIO) { + poppingQueue = i; + } else { + poppingQueue = j; + } + if (queues[poppingQueue].try_lock()) continue; + auto& q = queues[poppingQueue]; + if (q.pq.empty()) { + q.unlock(); + continue; + } + + uint64_t num = 0; + for (num = 0; num < batchSize; num++) { + if (q.pq.empty()) break; +#ifdef PERF + popInt(poppingQueue, &ret[num]); +#else + ret[num] = q.pq.top(); + q.pq.pop(); +#endif + + } + q.pops += num; + if (q.pq.empty()) + numEmpty.fetch_add(1, std::memory_order_relaxed); + q.min.store( + q.pq.size() > 0 + ? std::get<0>(q.pq.top()) + : EMPTY_PRIO, + std::memory_order_release + ); + q.unlock(); + if (num == 0) continue; + + return num; + } + return boost::none; + } + + inline uint64_t getQueueOccupancy() const { + uint64_t maxOccupancy = 0; + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + maxOccupancy = std::max(maxOccupancy, queues[i].pq.size()); + } + return maxOccupancy; + } + + // Get the number of pushes to all queues. + // Note: this is not lock protected. + inline uint64_t getNumPushes() const { + uint64_t totalPushes = 0; + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + totalPushes += queues[i].pushes; + } + return totalPushes; + } + + // Get the number of pops to all queues. + // Note: this is not lock protected. + inline uint64_t getNumPops() const { + uint64_t totalPops = 0; + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + totalPops += queues[i].pops; + } + return totalPops; + } + + inline void stat() const { + std::cout << "total pushes "<< getNumPushes() << "\n"; + std::cout << "total pops "<< getNumPops() << "\n"; + } + + // Note: this is only called at the end of algorithm as a + // sanity check, therefore it is not lock protected. + inline bool empty() const { + for (uint i = 0; i < NUM_QUEUES;i++) { + if (!queues[i].pq.empty()) { + return false; + } + } + return true; + } + + // Resets the MultiQueue to a state as if it was reinitialized. + // This must be called before using the MQ again after using TypPop(). + // Note: this assumes the queues are already empty and unlocked. + inline void reset() { + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + assert(queues[i].pq.empty() && "reset() assumes empty queues"); + assert((queues[i].queueLock.test(std::memory_order_relaxed) == 0) + && "reset() assumes unlocked queues"); + queues[i].pushes = 0; + queues[i].pops = 0; + queues[i].min.store(EMPTY_PRIO, std::memory_order_relaxed); + } + numIdle.store(0, std::memory_order_relaxed); + numEmpty.store(NUM_QUEUES, std::memory_order_relaxed); +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + minPrioForPop.store(std::numeric_limits::max(), std::memory_order_relaxed); +#endif + } +}; diff --git a/vpr/src/route/netlist_routers.h b/vpr/src/route/netlist_routers.h index 1524c2ddb38..6668ecdc7a9 100644 --- a/vpr/src/route/netlist_routers.h +++ b/vpr/src/route/netlist_routers.h @@ -3,7 +3,7 @@ /** @file Interface for a netlist router. * * A NetlistRouter manages the required bits of state to complete the netlist routing process, - * which requires finding a path for every connection in the netlist using a ConnectionRouter. + * which requires finding a path for every connection in the netlist using a SerialConnectionRouter. * This needs to be an interface because there may be different netlist routing schedules, * i.e. parallel or net-decomposing routers. * @@ -19,7 +19,6 @@ #include "NetPinTimingInvalidator.h" #include "clustered_netlist_utils.h" #include "connection_based_routing_fwd.h" -#include "connection_router.h" #include "globals.h" #include "heap_type.h" #include "netlist_fwd.h" diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp new file mode 100644 index 00000000000..1794f53d5a7 --- /dev/null +++ b/vpr/src/route/parallel_connection_router.cpp @@ -0,0 +1,1084 @@ +#include "parallel_connection_router.h" + +#include +#include "route_tree.h" +#include "rr_graph.h" +#include "rr_graph_fwd.h" + +/** Used for the flat router. The node isn't relevant to the target if + * it is an intra-block node outside of our target block */ +static bool relevant_node_to_target(const RRGraphView* rr_graph, + RRNodeId node_to_add, + RRNodeId target_node); + +static void update_router_stats(RouterStats* router_stats, + bool is_push, + RRNodeId rr_node_id, + const RRGraphView* rr_graph); + +/** return tuple */ +template +std::tuple ParallelConnectionRouter::timing_driven_route_connection_from_route_tree( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) { + router_stats_ = &router_stats; + conn_params_ = &conn_params; + + bool retry = false; + retry = timing_driven_route_connection_common_setup(rt_root, sink_node, cost_params, bounding_box); + + if (!std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + // Only the `index`, `prev_edge`, and `rcv_path_backward_delay` fields of `out` + // are used after this function returns. + RTExploredNode out; + out.index = sink_node; + out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; + if (rcv_path_manager.is_enabled()) { + out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; + rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); + rcv_path_manager.empty_heap(); + } + heap_.empty_heap(); + return std::make_tuple(true, /*retry=*/false, out); + } else { + reset_path_costs(); + clear_modified_rr_node_info(); + heap_.empty_heap(); + rcv_path_manager.empty_heap(); + return std::make_tuple(false, retry, RTExploredNode()); + } +} + +/** Return whether to retry with full bb */ +template +bool ParallelConnectionRouter::timing_driven_route_connection_common_setup( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { + //Re-add route nodes from the existing route tree to the heap. + //They need to be repushed onto the heap since each node's cost is target specific. + + add_route_tree_to_heap(rt_root, sink_node, cost_params, bounding_box); + heap_.build_heap(); // via sifting down everything + + RRNodeId source_node = rt_root.inode; + + if (heap_.is_empty_heap()) { + VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + return false; + } + + VTR_LOGV_DEBUG(router_debug_, " Routing to %d as normal net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, + bounding_box.layer_min, bounding_box.xmin, bounding_box.ymin, + bounding_box.layer_max, bounding_box.xmax, bounding_box.ymax); + + timing_driven_route_connection_from_heap(sink_node, + cost_params, + bounding_box); + + if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + // No path found within the current bounding box. + // + // If the bounding box is already max size, just fail + if (bounding_box.xmin == 0 + && bounding_box.ymin == 0 + && bounding_box.xmax == (int)(grid_.width() - 1) + && bounding_box.ymax == (int)(grid_.height() - 1) + && bounding_box.layer_min == 0 + && bounding_box.layer_max == (int)(grid_.get_num_layers() - 1)) { + VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + return false; + } + + // Otherwise, leave unrouted and bubble up a signal to retry this net with a full-device bounding box + VTR_LOG_WARN("No routing path for connection to sink_rr %d, leaving unrouted to retry later\n", sink_node); + return true; + } + + return false; +} + +// Finds a path from the route tree rooted at rt_root to sink_node for a high fanout net. +// +// Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree +// which is spatially close to the sink is added to the heap. +// Returns a tuple of */ +template +std::tuple ParallelConnectionRouter::timing_driven_route_connection_from_route_tree_high_fanout( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bounding_box, + const SpatialRouteTreeLookup& spatial_rt_lookup, + RouterStats& router_stats, + const ConnectionParameters& conn_params) { + router_stats_ = &router_stats; + conn_params_ = &conn_params; + + // re-explore route tree from root to add any new nodes (buildheap afterwards) + // route tree needs to be repushed onto the heap since each node's cost is target specific + t_bb high_fanout_bb = add_high_fanout_route_tree_to_heap(rt_root, sink_node, cost_params, spatial_rt_lookup, net_bounding_box); + heap_.build_heap(); + + RRNodeId source_node = rt_root.inode; + + if (heap_.is_empty_heap()) { + VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + return std::make_tuple(false, false, RTExploredNode()); + } + + VTR_LOGV_DEBUG(router_debug_, " Routing to %d as high fanout net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, + high_fanout_bb.layer_min, high_fanout_bb.xmin, high_fanout_bb.ymin, + high_fanout_bb.layer_max, high_fanout_bb.xmax, high_fanout_bb.ymax); + + bool retry_with_full_bb = false; + timing_driven_route_connection_from_heap(sink_node, + cost_params, + high_fanout_bb); + + if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + //Found no path, that may be due to an unlucky choice of existing route tree sub-set, + //try again with the full route tree to be sure this is not an artifact of high-fanout routing + VTR_LOG_WARN("No routing path found in high-fanout mode for net %zu connection (to sink_rr %d), retrying with full route tree\n", size_t(conn_params.net_id_), sink_node); + + //Reset any previously recorded node costs so timing_driven_route_connection() + //starts over from scratch. + reset_path_costs(); + clear_modified_rr_node_info(); + + retry_with_full_bb = timing_driven_route_connection_common_setup(rt_root, + sink_node, + cost_params, + net_bounding_box); + } + + if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + + heap_.empty_heap(); + rcv_path_manager.empty_heap(); + return std::make_tuple(false, retry_with_full_bb, RTExploredNode()); + } + + RTExploredNode out; + out.index = sink_node; + out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; + if (rcv_path_manager.is_enabled()) { + out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; + rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); + rcv_path_manager.empty_heap(); + } + heap_.empty_heap(); + + return std::make_tuple(true, retry_with_full_bb, out); +} + +static inline bool post_target_prune_node(float new_total_cost, + float new_back_cost, + float best_back_cost_to_target, + const t_conn_cost_params& params) { + // Divide out the astar_fac, then multiply to get determinism + // This is a correction factor to the forward cost to make the total + // cost an under-estimate. + // TODO: Should investigate creating a heuristic function that is + // gaurenteed to be an under-estimate. + // NOTE: Found experimentally that using the original heuristic to order + // the nodes in the queue and then post-target pruning based on the + // under-estimating heuristic has better runtime. + float expected_cost = new_total_cost - new_back_cost; + float new_expected_cost = expected_cost; + // h1 = (h - offset) * fac + // Protection for division by zero + if (params.astar_fac > 0.001) + // To save time, does not recompute the heuristic, just divideds out + // the astar_fac. + new_expected_cost /= params.astar_fac; + new_expected_cost = new_expected_cost - params.post_target_prune_offset; + // Max function to prevent the heuristic from going negative + new_expected_cost = std::max(0.f, new_expected_cost); + new_expected_cost *= params.post_target_prune_fac; + if ((new_back_cost + new_expected_cost) > best_back_cost_to_target) + return true; + // NOTE: we do NOT check for equality here. Equality does not matter for + // determinism when draining the queues (may just lead to a bit more work). + return false; +} + +// TODO: Once we have a heap node struct, clean this up! +static inline bool prune_node(RRNodeId inode, + float new_total_cost, + float new_back_cost, + RREdgeId new_prev_edge, + RRNodeId target_node, + vtr::vector& rr_node_route_inf_, + const t_conn_cost_params& params) { + // Post-target pruning: After the target is reached the first time, should + // use the heuristic to help drain the queues. + if (inode != target_node) { + t_rr_node_route_inf* target_route_inf = &rr_node_route_inf_[target_node]; + float best_back_cost_to_target = target_route_inf->backward_path_cost; + if (post_target_prune_node(new_total_cost, new_back_cost, best_back_cost_to_target, params)) + return true; + } + + // Backwards Pruning + // NOTE: When going to the target, we only want to prune on the truth. + // The queues handle using the heuristic to explore nodes faster. + t_rr_node_route_inf* route_inf = &rr_node_route_inf_[inode]; + float best_back_cost = route_inf->backward_path_cost; + if (new_back_cost > best_back_cost) + return true; + // In the case of a tie, need to be picky about whether to prune or not in + // order to get determinism. + // FIXME: This may not be thread safe. If the best node changes while this + // function is being called, we may have the new_back_cost and best + // prev_edge's being from different heap nodes! + // TODO: Move this to within the lock (the rest can stay for performance). + if (new_back_cost == best_back_cost) { +#ifndef NON_DETERMINISTIC_PRUNING + // With deterministic pruning, cannot always prune on ties. + // In the case of a true tie, just prune, no need to explore neightbors + RREdgeId best_prev_edge = route_inf->prev_edge; + if (new_prev_edge == best_prev_edge) + return true; + // When it comes to invalid edge IDs, in the case of a tied back cost, + // always try to keep the invalid edge ID (likely the start node). + // TODO: Verify this. + // If the best previous edge is invalid, prune + if (!best_prev_edge.is_valid()) + return true; + // If the new previous edge is invalid (assuming the best is not), accept + if (!new_prev_edge.is_valid()) + return false; + // Finally, if this node is not coming from a preferred edge, prune + // Deterministic version prefers a given EdgeID, so a unique path is returned since, + // in the case of a tie, a determinstic path wins. + // Is first preferred over second? + auto is_preferred_edge = [](RREdgeId first, RREdgeId second) { + return first < second; + }; + if (!is_preferred_edge(new_prev_edge, best_prev_edge)) + return true; +#else + std::ignore = new_prev_edge; + // When we do not care about determinism, always prune on equality. + return true; +#endif + } + + // If all above passes, do not prune. + return false; +} + +static inline bool should_not_explore_neighbors(RRNodeId inode, + float new_total_cost, + float new_back_cost, + RRNodeId target_node, + vtr::vector& rr_node_route_inf_, + const t_conn_cost_params& params) { +#ifndef NON_DETERMINISTIC_PRUNING + // For deterministic pruning, cannot enforce anything on the total cost since + // traversal order is not gaurenteed. However, since total cost is used as a + // "key" to signify that this node is the last node that was pushed, we can + // just check for equality. There is a chance this may cause some duplicates + // for the deterministic case, but thats ok they will be handled. + // TODO: Maybe consider having the non-deterministic version do this too. + if (new_total_cost != rr_node_route_inf_[inode].path_cost) + return true; +#else + // For non-deterministic pruning, can greadily just ignore nodes with higher + // total cost. + if (new_total_cost > rr_node_route_inf_[inode].path_cost) + return true; +#endif + // Perform post-target pruning. If this is not done, there is a chance that + // several duplicates of a node is in the queue that will never reach the + // target better than what we found and they will explore all of their + // neighbors which is not good. This is done before obtaining the lock to + // prevent lock contention where possible. + if (inode != target_node) { + float best_back_cost_to_target = rr_node_route_inf_[target_node].backward_path_cost; + if (post_target_prune_node(new_total_cost, new_back_cost, best_back_cost_to_target, params)) + return true; + } + return false; +} + +// Finds a path to sink_node, starting from the elements currently in the heap. +// This is the core maze routing routine. +template +void ParallelConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { + VTR_ASSERT_SAFE(heap_.is_valid()); + + if (heap_.is_empty_heap()) { //No source + VTR_LOGV_DEBUG(router_debug_, " Initial heap empty (no source)\n"); + } + + // Get bounding box for sink node used in timing_driven_expand_neighbour + VTR_ASSERT_SAFE(sink_node != RRNodeId::INVALID()); + + t_bb target_bb; + if (rr_graph_->node_type(sink_node) == SINK) { // We need to get a bounding box for the sink's entire tile + vtr::Rect tile_bb = grid_.get_tile_bb({rr_graph_->node_xlow(sink_node), + rr_graph_->node_ylow(sink_node), + rr_graph_->node_layer(sink_node)}); + + target_bb.xmin = tile_bb.xmin(); + target_bb.ymin = tile_bb.ymin(); + target_bb.xmax = tile_bb.xmax(); + target_bb.ymax = tile_bb.ymax(); + } else { + target_bb.xmin = rr_graph_->node_xlow(sink_node); + target_bb.ymin = rr_graph_->node_ylow(sink_node); + target_bb.xmax = rr_graph_->node_xhigh(sink_node); + target_bb.ymax = rr_graph_->node_yhigh(sink_node); + } + + target_bb.layer_min = rr_graph_->node_layer(RRNodeId(sink_node)); + target_bb.layer_max = rr_graph_->node_layer(RRNodeId(sink_node)); + + // Start measuring path search time + std::chrono::steady_clock::time_point begin_time = std::chrono::steady_clock::now(); + + this->sink_node_ = &sink_node; + this->cost_params_ = const_cast(&cost_params); + this->bounding_box_ = const_cast(&bounding_box); + this->target_bb_ = const_cast(&target_bb); + + thread_barrier_.wait(); + this->timing_driven_route_connection_from_heap_thread_func(*this->sink_node_, *this->cost_params_, *this->bounding_box_, *this->target_bb_, 0); + thread_barrier_.wait(); + + // Collect the number of heap pushes and pops + router_stats_->heap_pushes += heap_.getNumPushes(); + router_stats_->heap_pops += heap_.getNumPops(); + + // Reset the heap for the next connection + heap_.reset(); + + // Stop measuring path search time + std::chrono::steady_clock::time_point end_time = std::chrono::steady_clock::now(); + path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); +} + +template +void ParallelConnectionRouter::timing_driven_route_connection_from_heap_sub_thread_wrapper(const size_t thread_idx) { + thread_barrier_.init(); + while (true) { + thread_barrier_.wait(); + if (is_router_destroying_ == true) { + return; + } else { + timing_driven_route_connection_from_heap_thread_func(*this->sink_node_, *this->cost_params_, *this->bounding_box_, *this->target_bb_, thread_idx); + } + thread_barrier_.wait(); + } +} + +template +void ParallelConnectionRouter::timing_driven_route_connection_from_heap_thread_func(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb, + const size_t thread_idx) { + HeapNode cheapest; + while (heap_.try_pop(cheapest)) { + // inode with the cheapest total cost in current route tree to be expanded on + const auto& [ new_total_cost, inode ] = cheapest; + + // Should we explore the neighbors of this node? + if (should_not_explore_neighbors(inode, new_total_cost, rr_node_route_inf_[inode].backward_path_cost, sink_node, rr_node_route_inf_, cost_params)) { + continue; + } + + obtainSpinLock(inode); + + RTExploredNode current; + current.index = inode; + current.backward_path_cost = rr_node_route_inf_[inode].backward_path_cost; + current.prev_edge = rr_node_route_inf_[inode].prev_edge; + current.R_upstream = rr_node_route_inf_[inode].R_upstream; + + releaseLock(inode); + + // Double check now just to be sure that we should still explore neighbors + // NOTE: A good question is what happened to the uniqueness pruning. The idea + // is that at this point it does not matter. Basically any duplicates + // will act like they were the last one pushed in. This may create some + // duplicates, but it is a simple way of handling this situation. + // It may be worth investigating a better way to do this in the future. + // TODO: This is still doing post-target pruning. May want to investigate + // if this is worth doing. + // TODO: should try testing without the pruning below and see if anything changes. + if (should_not_explore_neighbors(inode, new_total_cost, current.backward_path_cost, sink_node, rr_node_route_inf_, cost_params)) { + continue; + } + + // Adding nodes to heap + timing_driven_expand_neighbours(current, cost_params, bounding_box, sink_node, target_bb, thread_idx); + } +} + +// Find shortest paths from specified route tree to all nodes in the RR graph +template +vtr::vector ParallelConnectionRouter::timing_driven_find_all_shortest_paths_from_route_tree( + const RouteTreeNode& rt_root, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) { + (void)rt_root; + (void)cost_params; + (void)bounding_box; + (void)router_stats; + (void)conn_params; + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_route_tree not yet implemented (nor is the focus of this project). Not expected to be called."); +} + +// Find shortest paths from current heap to all nodes in the RR graph +// +// Since there is no single *target* node this uses Dijkstra's algorithm +// with a modified exit condition (runs until heap is empty). +template +vtr::vector ParallelConnectionRouter::timing_driven_find_all_shortest_paths_from_heap( + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { + (void)cost_params; + (void)bounding_box; + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_heap not yet implemented (nor is the focus of this project). Not expected to be called."); +} + +template +void ParallelConnectionRouter::timing_driven_expand_neighbours(const RTExploredNode& current, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx) { + /* Puts all the rr_nodes adjacent to current on the heap. */ + + // For each node associated with the current heap element, expand all of it's neighbors + auto edges = rr_nodes_.edge_range(current.index); + + // This is a simple prefetch that prefetches: + // - RR node data reachable from this node + // - rr switch data to reach those nodes from this node. + // + // This code will be a NOP on compiler targets that do not have a + // builtin to emit prefetch instructions. + // + // This code will be a NOP on CPU targets that lack prefetch instructions. + // All modern x86 and ARM64 platforms provide prefetch instructions. + // + // This code delivers ~6-8% reduction in wallclock time when running Titan + // benchmarks, and was specifically measured against the gsm_switch and + // directrf vtr_reg_weekly running in high effort. + // + // - directrf_stratixiv_arch_timing.blif + // - gsm_switch_stratixiv_arch_timing.blif + // + for (RREdgeId from_edge : edges) { + RRNodeId to_node = rr_nodes_.edge_sink_node(from_edge); + rr_nodes_.prefetch_node(to_node); + + int switch_idx = rr_nodes_.edge_switch(from_edge); + VTR_PREFETCH(&rr_switch_inf_[switch_idx], 0, 0); + } + + for (RREdgeId from_edge : edges) { + RRNodeId to_node = rr_nodes_.edge_sink_node(from_edge); + timing_driven_expand_neighbour(current, + from_edge, + to_node, + cost_params, + bounding_box, + target_node, + target_bb, + thread_idx); + } +} + +// Conditionally adds to_node to the router heap (via path from from_node via from_edge). +// RR nodes outside the expanded bounding box specified in bounding_box are not added +// to the heap. +template +void ParallelConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, + RREdgeId from_edge, + RRNodeId to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx) { + // VTR_ASSERT(bounding_box.layer_max < g_vpr_ctx.device().grid.get_num_layers()); + + // const RRNodeId& from_node = current.index; + + // BB-pruning + // Disable BB-pruning if RCV is enabled, as this can make it harder for circuits with high negative hold slack to resolve this + // TODO: Only disable pruning if the net has negative hold slack, maybe go off budgets + if (!inside_bb(to_node, bounding_box)) { + // VTR_LOGV_DEBUG(router_debug_, + // " Pruned expansion of node %d edge %zu -> %d" + // " (to node location %d,%d,%d x %d,%d,%d outside of expanded" + // " net bounding box %d,%d,%d x %d,%d,%d)\n", + // from_node, size_t(from_edge), size_t(to_node), + // rr_graph_->node_xlow(to_node), rr_graph_->node_ylow(to_node), rr_graph_->node_layer(to_node), + // rr_graph_->node_xhigh(to_node), rr_graph_->node_yhigh(to_node), rr_graph_->node_layer(to_node), + // bounding_box.xmin, bounding_box.ymin, bounding_box.layer_min, + // bounding_box.xmax, bounding_box.ymax, bounding_box.layer_max); + return; /* Node is outside (expanded) bounding box. */ + } + + /* Prune away IPINs that lead to blocks other than the target one. Avoids * + * the issue of how to cost them properly so they don't get expanded before * + * more promising routes, but makes route-through (via CLBs) impossible. * + * Change this if you want to investigate route-throughs. */ + if (target_node != RRNodeId::INVALID()) { + t_rr_type to_type = rr_graph_->node_type(to_node); + if (to_type == IPIN) { + // Check if this IPIN leads to the target block + // IPIN's of the target block should be contained within it's bounding box + int to_xlow = rr_graph_->node_xlow(to_node); + int to_ylow = rr_graph_->node_ylow(to_node); + int to_layer = rr_graph_->node_layer(to_node); + int to_xhigh = rr_graph_->node_xhigh(to_node); + int to_yhigh = rr_graph_->node_yhigh(to_node); + if (to_xlow < target_bb.xmin + || to_ylow < target_bb.ymin + || to_xhigh > target_bb.xmax + || to_yhigh > target_bb.ymax + || to_layer < target_bb.layer_min + || to_layer > target_bb.layer_max) { + // VTR_LOGV_DEBUG(router_debug_, + // " Pruned expansion of node %d edge %zu -> %d" + // " (to node is IPIN at %d,%d,%d x %d,%d,%d which does not" + // " lead to target block %d,%d,%d x %d,%d,%d)\n", + // from_node, size_t(from_edge), size_t(to_node), + // to_xlow, to_ylow, to_layer, + // to_xhigh, to_yhigh, to_layer, + // target_bb.xmin, target_bb.ymin, target_bb.layer_min, + // target_bb.xmax, target_bb.ymax, target_bb.layer_max); + return; + } + } + } + + // VTR_LOGV_DEBUG(router_debug_, " Expanding node %d edge %zu -> %d\n", + // from_node, size_t(from_edge), size_t(to_node)); + + timing_driven_add_to_heap(cost_params, + current, + to_node, + from_edge, + target_node, + thread_idx); +} + +// Add to_node to the heap, and also add any nodes which are connected by non-configurable edges +template +void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, + const RTExploredNode& current, + RRNodeId to_node, + const RREdgeId from_edge, + RRNodeId target_node, + size_t thread_idx) { + const RRNodeId& from_node = current.index; + + // Initialized to current + RTExploredNode next; + next.R_upstream = current.R_upstream; + next.index = to_node; + next.prev_edge = from_edge; + next.total_cost = std::numeric_limits::infinity(); // Not used directly + next.backward_path_cost = current.backward_path_cost; + + evaluate_timing_driven_node_costs(&next, + cost_params, + from_node, + target_node); + + float new_total_cost = next.total_cost; + float new_back_cost = next.backward_path_cost; + + if (prune_node(to_node, new_total_cost, new_back_cost, from_edge, target_node, rr_node_route_inf_, cost_params)) { + return; + } + + obtainSpinLock(to_node); + + if (prune_node(to_node, new_total_cost, new_back_cost, from_edge, target_node, rr_node_route_inf_, cost_params)) { + releaseLock(to_node); + return; + } + + update_cheapest(next, thread_idx); + + releaseLock(to_node); + + if (to_node == target_node) { +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + if (multi_queue_direct_draining_) { + heap_.setMinPrioForPop(new_total_cost); + } +#endif + return ; + } + heap_.add_to_heap({new_total_cost, to_node}); + + // update_router_stats(router_stats_, + // /*is_push=*/true, + // to_node, + // rr_graph_); +} + +#ifdef VTR_ASSERT_SAFE_ENABLED + +//Returns true if both nodes are part of the same non-configurable edge set +static bool same_non_config_node_set(RRNodeId from_node, RRNodeId to_node) { + auto& device_ctx = g_vpr_ctx.device(); + + auto from_itr = device_ctx.rr_node_to_non_config_node_set.find(from_node); + auto to_itr = device_ctx.rr_node_to_non_config_node_set.find(to_node); + + if (from_itr == device_ctx.rr_node_to_non_config_node_set.end() + || to_itr == device_ctx.rr_node_to_non_config_node_set.end()) { + return false; //Not part of a non-config node set + } + + return from_itr->second == to_itr->second; //Check for same non-config set IDs +} + +#endif + +// Empty the route tree set node, use this after each net is routed +template +void ParallelConnectionRouter::empty_rcv_route_tree_set() { +} + +// Enable or disable RCV +template +void ParallelConnectionRouter::set_rcv_enabled(bool enable) { + (void)enable; + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "RCV for parallel connection router not yet implemented. Not expected to be called."); +} + +//Calculates the cost of reaching to_node (i.e., to->index) +template +void ParallelConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, + const t_conn_cost_params& cost_params, + RRNodeId from_node, + RRNodeId target_node) { + /* new_costs.backward_cost: is the "known" part of the cost to this node -- the + * congestion cost of all the routing resources back to the existing route + * plus the known delay of the total path back to the source. + * + * new_costs.total_cost: is this "known" backward cost + an expected cost to get to the target. + * + * new_costs.R_upstream: is the upstream resistance at the end of this node + */ + + //Info for the switch connecting from_node to_node (i.e., to->index) + int iswitch = rr_nodes_.edge_switch(to->prev_edge); + bool switch_buffered = rr_switch_inf_[iswitch].buffered(); + bool reached_configurably = rr_switch_inf_[iswitch].configurable(); + float switch_R = rr_switch_inf_[iswitch].R; + float switch_Tdel = rr_switch_inf_[iswitch].Tdel; + float switch_Cinternal = rr_switch_inf_[iswitch].Cinternal; + + //To node info + auto rc_index = rr_graph_->node_rc_index(to->index); + float node_C = rr_rc_data_[rc_index].C; + float node_R = rr_rc_data_[rc_index].R; + + //From node info + float from_node_R = rr_rc_data_[rr_graph_->node_rc_index(from_node)].R; + + //Update R_upstream + if (switch_buffered) { + to->R_upstream = 0.; //No upstream resistance + } else { + //R_Upstream already initialized + } + + to->R_upstream += switch_R; //Switch resistance + to->R_upstream += node_R; //Node resistance + + //Calculate delay + float Rdel = to->R_upstream - 0.5 * node_R; //Only consider half node's resistance for delay + float Tdel = switch_Tdel + Rdel * node_C; + + //Depending on the switch used, the Tdel of the upstream node (from_node) may change due to + //increased loading from the switch's internal capacitance. + // + //Even though this delay physically affects from_node, we make the adjustment (now) on the to_node, + //since only once we've reached to to_node do we know the connection used (and the switch enabled). + // + //To adjust for the time delay, we compute the product of the Rdel associated with from_node and + //the internal capacitance of the switch. + // + //First, we will calculate Rdel_adjust (just like in the computation for Rdel, we consider only + //half of from_node's resistance). + float Rdel_adjust = to->R_upstream - 0.5 * from_node_R; + + //Second, we adjust the Tdel to account for the delay caused by the internal capacitance. + Tdel += Rdel_adjust * switch_Cinternal; + + float cong_cost = 0.; + if (reached_configurably) { + cong_cost = get_rr_cong_cost(to->index, cost_params.pres_fac); + } else { + //Reached by a non-configurable edge. + //Therefore the from_node and to_node are part of the same non-configurable node set. +#ifdef VTR_ASSERT_SAFE_ENABLED + VTR_ASSERT_SAFE_MSG(same_non_config_node_set(from_node, to->index), + "Non-configurably connected edges should be part of the same node set"); +#endif + + //The congestion cost of all nodes in the set has already been accounted for (when + //the current path first expanded a node in the set). Therefore do *not* re-add the congestion + //cost. + cong_cost = 0.; + } + if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == IPIN) { + auto find_res = conn_params_->connection_choking_spots_.find(to->index); + if (find_res != conn_params_->connection_choking_spots_.end()) { + cong_cost = cong_cost / pow(2, (float)find_res->second); + } + } + + //Update the backward cost (upstream already included) + to->backward_path_cost += (1. - cost_params.criticality) * cong_cost; //Congestion cost + to->backward_path_cost += cost_params.criticality * Tdel; //Delay cost + + if (cost_params.bend_cost != 0.) { + t_rr_type from_type = rr_graph_->node_type(from_node); + t_rr_type to_type = rr_graph_->node_type(to->index); + if ((from_type == CHANX && to_type == CHANY) || (from_type == CHANY && to_type == CHANX)) { + to->backward_path_cost += cost_params.bend_cost; //Bend cost + } + } + + float total_cost = 0.; + + // const auto& device_ctx = g_vpr_ctx.device(); + //Update total cost + float expected_cost = router_lookahead_.get_expected_cost(to->index, target_node, cost_params, to->R_upstream); + total_cost += to->backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); + + to->total_cost = total_cost; +} + +//Adds the route tree rooted at rt_node to the heap, preparing it to be +//used as branch-points for further routing. +template +void ParallelConnectionRouter::add_route_tree_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb) { + /* Puts the entire partial routing below and including rt_node onto the heap * + * (except for those parts marked as not to be expanded) by calling itself * + * recursively. */ + + /* Pre-order depth-first traversal */ + // IPINs and SINKS are not re_expanded + if (rt_node.re_expand) { + add_route_tree_node_to_heap(rt_node, + target_node, + cost_params, + net_bb); + } + + for (const RouteTreeNode& child_node : rt_node.child_nodes()) { + if (is_flat_) { + if (relevant_node_to_target(rr_graph_, + child_node.inode, + target_node)) { + add_route_tree_to_heap(child_node, + target_node, + cost_params, + net_bb); + } + } else { + add_route_tree_to_heap(child_node, + target_node, + cost_params, + net_bb); + } + } +} + +//Unconditionally adds rt_node to the heap +// +//Note that if you want to respect rt_node.re_expand that is the caller's +//responsibility. +template +void ParallelConnectionRouter::add_route_tree_node_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb) { + const auto& device_ctx = g_vpr_ctx.device(); + const RRNodeId inode = rt_node.inode; + float backward_path_cost = cost_params.criticality * rt_node.Tdel; + float R_upstream = rt_node.R_upstream; + + /* Don't push to heap if not in bounding box: no-op for serial router, important for parallel router */ + if (!inside_bb(rt_node.inode, net_bb)) + return; + + // after budgets are loaded, calculate delay cost as described by RCV paper + /* R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While + * Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of + * Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008.*/ + // float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); + + if (!rcv_path_manager.is_enabled()) { + // tot_cost = backward_path_cost + cost_params.astar_fac * expected_cost; + float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); + float tot_cost = backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); + VTR_LOGV_DEBUG(router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", + inode, + tot_cost, + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, is_flat_).c_str()); + + if (prune_node(inode, tot_cost, backward_path_cost, RREdgeId::INVALID(), target_node, rr_node_route_inf_, cost_params)) { + return ; + } + add_to_mod_list(inode, 0/*main thread*/); + rr_node_route_inf_[inode].path_cost = tot_cost; + rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); + rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; + rr_node_route_inf_[inode].R_upstream = R_upstream; + heap_.push_back({tot_cost, inode}); + + // push_back_node(&heap_, rr_node_route_inf_, + // inode, tot_cost, RREdgeId::INVALID(), + // backward_path_cost, R_upstream); + } + // if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { + // router_stats_->rt_node_pushes[rr_graph_->node_type(inode)]++; + // } +} + +/* Expand bb by inode's extents and clip against net_bb */ +inline void expand_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb, RRNodeId inode, const RRGraphView* rr_graph) { + bb.xmin = std::max(net_bb.xmin, std::min(bb.xmin, rr_graph->node_xlow(inode))); + bb.ymin = std::max(net_bb.ymin, std::min(bb.ymin, rr_graph->node_ylow(inode))); + bb.xmax = std::min(net_bb.xmax, std::max(bb.xmax, rr_graph->node_xhigh(inode))); + bb.ymax = std::min(net_bb.ymax, std::max(bb.ymax, rr_graph->node_yhigh(inode))); + bb.layer_min = std::min(bb.layer_min, rr_graph->node_layer(inode)); + bb.layer_max = std::max(bb.layer_max, rr_graph->node_layer(inode)); +} + +/* Expand bb by HIGH_FANOUT_BB_FAC and clip against net_bb */ +inline void adjust_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb) { + constexpr int HIGH_FANOUT_BB_FAC = 3; + + bb.xmin = std::max(net_bb.xmin, bb.xmin - HIGH_FANOUT_BB_FAC); + bb.ymin = std::max(net_bb.ymin, bb.ymin - HIGH_FANOUT_BB_FAC); + bb.xmax = std::min(net_bb.xmax, bb.xmax + HIGH_FANOUT_BB_FAC); + bb.ymax = std::min(net_bb.ymax, bb.ymax + HIGH_FANOUT_BB_FAC); + bb.layer_min = std::min(net_bb.layer_min, bb.layer_min); + bb.layer_max = std::max(net_bb.layer_max, bb.layer_max); +} + +template +t_bb ParallelConnectionRouter::add_high_fanout_route_tree_to_heap( + const RouteTreeNode& rt_root, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const SpatialRouteTreeLookup& spatial_rt_lookup, + const t_bb& net_bounding_box) { + //For high fanout nets we only add those route tree nodes which are spatially close + //to the sink. + // + //Based on: + // J. Swartz, V. Betz, J. Rose, "A Fast Routability-Driven Router for FPGAs", FPGA, 1998 + // + //We rely on a grid-based spatial look-up which is maintained for high fanout nets by + //update_route_tree(), which allows us to add spatially close route tree nodes without traversing + //the entire route tree (which is likely large for a high fanout net). + + //Determine which bin the target node is located in + + int target_bin_x = grid_to_bin_x(rr_graph_->node_xlow(target_node), spatial_rt_lookup); + int target_bin_y = grid_to_bin_y(rr_graph_->node_ylow(target_node), spatial_rt_lookup); + + auto target_layer = rr_graph_->node_layer(target_node); + + int chan_nodes_added = 0; + + t_bb highfanout_bb; + highfanout_bb.xmin = rr_graph_->node_xlow(target_node); + highfanout_bb.xmax = rr_graph_->node_xhigh(target_node); + highfanout_bb.ymin = rr_graph_->node_ylow(target_node); + highfanout_bb.ymax = rr_graph_->node_yhigh(target_node); + highfanout_bb.layer_min = target_layer; + highfanout_bb.layer_max = target_layer; + + //Add existing routing starting from the target bin. + //If the target's bin has insufficient existing routing add from the surrounding bins + constexpr int SINGLE_BIN_MIN_NODES = 2; + bool done = false; + bool found_node_on_same_layer = false; + for (int dx : {0, -1, +1}) { + size_t bin_x = target_bin_x + dx; + + if (bin_x > spatial_rt_lookup.dim_size(0) - 1) continue; //Out of range + + for (int dy : {0, -1, +1}) { + size_t bin_y = target_bin_y + dy; + + if (bin_y > spatial_rt_lookup.dim_size(1) - 1) continue; //Out of range + + for (const RouteTreeNode& rt_node : spatial_rt_lookup[bin_x][bin_y]) { + if (!rt_node.re_expand) // Some nodes (like IPINs) shouldn't be re-expanded + continue; + RRNodeId rr_node_to_add = rt_node.inode; + + /* Flat router: don't go into clusters other than the target one */ + if (is_flat_) { + if (!relevant_node_to_target(rr_graph_, rr_node_to_add, target_node)) + continue; + } + + /* In case of the parallel router, we may be dealing with a virtual net + * so prune the nodes from the HF lookup against the bounding box just in case */ + if (!inside_bb(rr_node_to_add, net_bounding_box)) + continue; + + auto rt_node_layer_num = rr_graph_->node_layer(rr_node_to_add); + if (rt_node_layer_num == target_layer) + found_node_on_same_layer = true; + + // Put the node onto the heap + add_route_tree_node_to_heap(rt_node, target_node, cost_params, net_bounding_box); + + // Expand HF BB to include the node (clip by original BB) + expand_highfanout_bounding_box(highfanout_bb, net_bounding_box, rr_node_to_add, rr_graph_); + + if (rr_graph_->node_type(rr_node_to_add) == CHANY || rr_graph_->node_type(rr_node_to_add) == CHANX) { + chan_nodes_added++; + } + } + + if (dx == 0 && dy == 0 && chan_nodes_added > SINGLE_BIN_MIN_NODES && found_node_on_same_layer) { + //Target bin contained at least minimum amount of routing + // + //We require at least SINGLE_BIN_MIN_NODES to be added. + //This helps ensure we don't end up with, for example, a single + //routing wire running in the wrong direction which may not be + //able to reach the target within the bounding box. + done = true; + break; + } + } + if (done) break; + } + /* If we didn't find enough nodes to branch off near the target + * or they are on the wrong grid layer, just add the full route tree */ + if (chan_nodes_added <= SINGLE_BIN_MIN_NODES || !found_node_on_same_layer) { + add_route_tree_to_heap(rt_root, target_node, cost_params, net_bounding_box); + return net_bounding_box; + } else { + //We found nearby routing, replace original bounding box to be localized around that routing + adjust_highfanout_bounding_box(highfanout_bb, net_bounding_box); + return highfanout_bb; + } +} + +static inline bool relevant_node_to_target(const RRGraphView* rr_graph, + RRNodeId node_to_add, + RRNodeId target_node) { + VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == t_rr_type::SINK); + auto node_to_add_type = rr_graph->node_type(node_to_add); + return node_to_add_type != t_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); +} + +static inline void update_router_stats(RouterStats* router_stats, + bool is_push, + RRNodeId rr_node_id, + const RRGraphView* rr_graph) { + if (is_push) { + router_stats->heap_pushes++; + } else { + router_stats->heap_pops++; + } + + if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { + auto node_type = rr_graph->node_type(rr_node_id); + VTR_ASSERT(node_type != NUM_RR_TYPES); + + if (is_inter_cluster_node(*rr_graph, rr_node_id)) { + if (is_push) { + router_stats->inter_cluster_node_pushes++; + router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; + } else { + router_stats->inter_cluster_node_pops++; + router_stats->inter_cluster_node_type_cnt_pops[node_type]++; + } + } else { + if (is_push) { + router_stats->intra_cluster_node_pushes++; + router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; + } else { + router_stats->intra_cluster_node_pops++; + router_stats->intra_cluster_node_type_cnt_pops[node_type]++; + } + } + } +} + +std::unique_ptr make_parallel_connection_router(e_heap_type heap_type, + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat, + int multi_queue_num_threads, + int multi_queue_num_queues, + bool multi_queue_direct_draining) { + switch (heap_type) { + case e_heap_type::BINARY_HEAP: + return std::make_unique>( + grid, + router_lookahead, + rr_nodes, + rr_graph, + rr_rc_data, + rr_switch_inf, + rr_node_route_inf, + is_flat, + multi_queue_num_threads, + multi_queue_num_queues, + multi_queue_direct_draining); + case e_heap_type::FOUR_ARY_HEAP: + return std::make_unique>( + grid, + router_lookahead, + rr_nodes, + rr_graph, + rr_rc_data, + rr_switch_inf, + rr_node_route_inf, + is_flat, + multi_queue_num_threads, + multi_queue_num_queues, + multi_queue_direct_draining); + default: + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Unknown heap_type %d", + heap_type); + } +} diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h new file mode 100644 index 00000000000..692c285c2cd --- /dev/null +++ b/vpr/src/route/parallel_connection_router.h @@ -0,0 +1,429 @@ +#ifndef _PARALLEL_CONNECTION_ROUTER_H +#define _PARALLEL_CONNECTION_ROUTER_H + +#include "connection_router_interface.h" +#include "rr_graph_storage.h" +#include "route_common.h" +#include "router_lookahead.h" +#include "route_tree.h" +#include "rr_rc_data.h" +#include "router_stats.h" +#include "spatial_route_tree_lookup.h" + +#include "d_ary_heap.h" +#include "multi_queue_d_ary_heap.h" + +#include +#include +#include +#include + +class spin_lock_t { + std::atomic_flag lock_ = ATOMIC_FLAG_INIT; +public: + void acquire() { + while (std::atomic_flag_test_and_set_explicit(&lock_, std::memory_order_acquire)); + } + + void release() { + std::atomic_flag_clear_explicit(&lock_, std::memory_order_release); + } +}; + +class barrier_mutex_t { + std::mutex mutex_; + std::condition_variable cv_; + size_t count_; + size_t max_count_; + size_t generation_ = 0; +public: + explicit barrier_mutex_t(size_t num_threads) : count_(num_threads), max_count_(num_threads) { } + + void wait() { + std::unique_lock lock{mutex_}; + size_t gen = generation_; + if (--count_ == 0) { + generation_ ++; + count_ = max_count_; + cv_.notify_all(); + } else { + cv_.wait(lock, [this, &gen] { return gen != generation_; }); + } + } +}; + +class barrier_spin_t { + size_t num_threads_ = 1; + std::atomic count_ = 0; + std::atomic sense_ = false; // global sense shared by multiple threads + inline static thread_local bool local_sense_ = false; + +public: + explicit barrier_spin_t(size_t num_threads) { num_threads_ = num_threads; } + + void init() { + local_sense_ = false; + } + + void wait() { + bool s = !local_sense_; + local_sense_ = s; + size_t num_arrivals = count_.fetch_add(1) + 1; + if (num_arrivals == num_threads_) { + count_.store(0); + sense_.store(s); + } else { + while (sense_.load() != s) ; + } + } +}; + +using barrier_t = barrier_spin_t; + +// This class encapsulates the timing driven connection router. This class +// routes from some initial set of sources (via the input rt tree) to a +// particular sink. +// +// When the ParallelConnectionRouter is used, it mutates the provided +// rr_node_route_inf. The routed path can be found by tracing from the sink +// node (which is returned) through the rr_node_route_inf. See +// update_traceback as an example of this tracing. +template +class ParallelConnectionRouter : public ConnectionRouterInterface { + public: + ParallelConnectionRouter( + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat, + int multi_queue_num_threads, + int multi_queue_num_queues, + bool multi_queue_direct_draining) + : grid_(grid) + , router_lookahead_(router_lookahead) + , rr_nodes_(rr_nodes.view()) + , rr_graph_(rr_graph) + , rr_rc_data_(rr_rc_data.data(), rr_rc_data.size()) + , rr_switch_inf_(rr_switch_inf.data(), rr_switch_inf.size()) + , net_terminal_groups(g_vpr_ctx.routing().net_terminal_groups) + , net_terminal_group_num(g_vpr_ctx.routing().net_terminal_group_num) + , rr_node_route_inf_(rr_node_route_inf) + , is_flat_(is_flat) + , modified_rr_node_inf_(multi_queue_num_threads) + , router_stats_(nullptr) + , heap_(multi_queue_num_threads, multi_queue_num_queues) + , thread_barrier_(multi_queue_num_threads) + , is_router_destroying_(false) + , locks_(rr_node_route_inf.size()) + , multi_queue_direct_draining_(multi_queue_direct_draining) + , router_debug_(false) + , path_search_cumulative_time(0) { + heap_.init_heap(grid); + only_opin_inter_layer = (grid.get_num_layers() > 1) && inter_layer_connections_limited_to_opin(*rr_graph); + + sub_threads_.resize(multi_queue_num_threads - 1); + thread_barrier_.init(); + for (int i = 0 ; i < multi_queue_num_threads - 1; ++i) { + sub_threads_[i] = std::thread(&ParallelConnectionRouter::timing_driven_route_connection_from_heap_sub_thread_wrapper, this, i + 1 /*0: main thread*/); + sub_threads_[i].detach(); + } + } + + ~ParallelConnectionRouter() { + is_router_destroying_ = true; + thread_barrier_.wait(); + + VTR_LOG("Parallel Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", + std::chrono::duration(path_search_cumulative_time).count()); + } + + // Clear's the modified list. Should be called after reset_path_costs + // have been called. + void clear_modified_rr_node_info() final { + for (auto& thread_visited_rr_nodes : modified_rr_node_inf_) { + thread_visited_rr_nodes.clear(); + } + } + + // Reset modified data in rr_node_route_inf based on modified_rr_node_inf. + // Derived from `reset_path_costs` from route_common.cpp as a specific version + // for the parallel connection router. + void reset_path_costs() final { + auto& route_ctx = g_vpr_ctx.mutable_routing(); + for (const auto& thread_visited_rr_nodes : modified_rr_node_inf_) { + for (const auto node : thread_visited_rr_nodes) { + route_ctx.rr_node_route_inf[node].path_cost = std::numeric_limits::infinity(); + route_ctx.rr_node_route_inf[node].backward_path_cost = std::numeric_limits::infinity(); + route_ctx.rr_node_route_inf[node].prev_edge = RREdgeId::INVALID(); + } + } + } + + /** Finds a path from the route tree rooted at rt_root to sink_node. + * This is used when you want to allow previous routing of the same net to + * serve as valid start locations for the current connection. + * + * Returns a tuple of: + * bool: path exists? (hard failure, rr graph disconnected) + * bool: should retry with full bounding box? (only used in parallel routing) + * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ + std::tuple timing_driven_route_connection_from_route_tree( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) final; + + /** Finds a path from the route tree rooted at rt_root to sink_node for a + * high fanout net. + * + * Unlike timing_driven_route_connection_from_route_tree(), only part of + * the route tree which is spatially close to the sink is added to the heap. + * + * Returns a tuple of: + * bool: path exists? (hard failure, rr graph disconnected) + * bool: should retry with full bounding box? (only used in parallel routing) + * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ + std::tuple timing_driven_route_connection_from_route_tree_high_fanout( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bounding_box, + const SpatialRouteTreeLookup& spatial_rt_lookup, + RouterStats& router_stats, + const ConnectionParameters& conn_params) final; + + // Finds a path from the route tree rooted at rt_root to all sinks + // available. + // + // Each element of the returned vector is a reachable sink. + // + // If cost_params.astar_fac is set to 0, this effectively becomes + // Dijkstra's algorithm with a modified exit condition (runs until heap is + // empty). When using cost_params.astar_fac = 0, for efficiency the + // RouterLookahead used should be the NoOpLookahead. + // + // Note: This routine is currently used only to generate information that + // may be helpful in debugging an architecture. + vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( + const RouteTreeNode& rt_root, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) final; + + void set_router_debug(bool router_debug) final { + router_debug_ = router_debug; + } + + // Empty the route tree set used for RCV node detection + // Will return if RCV is disabled + // Called after each net is finished routing to flush the set + void empty_rcv_route_tree_set() final; + + // Enable or disable RCV in connection router + // Enabling this will utilize extra path structures, as well as the RCV cost function + // + // Ensure route budgets have been calculated before enabling this + void set_rcv_enabled(bool enable) final; + + private: + // Mark that data associated with rr_node "inode" has been modified, and + // needs to be reset in reset_path_costs. + void add_to_mod_list(RRNodeId inode, size_t thread_idx) { + if (std::isinf(rr_node_route_inf_[inode].path_cost)) { + modified_rr_node_inf_[thread_idx].push_back(inode); + } + } + + // Update the route path to the node `cheapest.index` via the path from + // `from_node` via `cheapest.prev_edge`. + inline void update_cheapest(RTExploredNode& cheapest, size_t thread_idx) { + const RRNodeId& inode = cheapest.index; + add_to_mod_list(inode, thread_idx); + rr_node_route_inf_[inode].prev_edge = cheapest.prev_edge; + rr_node_route_inf_[inode].path_cost = cheapest.total_cost; + rr_node_route_inf_[inode].backward_path_cost = cheapest.backward_path_cost; + } + + inline void obtainSpinLock(const RRNodeId& inode) { + locks_[size_t(inode)].acquire(); + } + + inline void releaseLock(const RRNodeId& inode) { + locks_[size_t(inode)].release(); + } + + /** Common logic from timing_driven_route_connection_from_route_tree and + * timing_driven_route_connection_from_route_tree_high_fanout for running + * the connection router. + * @param[in] rt_root RouteTreeNode describing the current routing state + * @param[in] sink_node Sink node ID to route to + * @param[in] cost_params + * @param[in] bounding_box Keep search confined to this bounding box + * @return bool Signal to retry this connection with a full-device bounding box */ + bool timing_driven_route_connection_common_setup( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box); + + // Finds a path to sink_node, starting from the elements currently in the + // heap. + // + // If the path is not found, which means that the path_cost of sink_node in + // RR node route info has never been updated, `rr_node_route_inf_[sink_node] + // .path_cost` will be the initial value (i.e., float infinity). This case + // can be detected by `std::isinf(rr_node_route_inf_[sink_node].path_cost)`. + // + // This is the core maze routing routine. + // + // Note: For understanding the connection router, start here. + void timing_driven_route_connection_from_heap( + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box); + + void timing_driven_route_connection_from_heap_sub_thread_wrapper( + const size_t thread_idx); + + void timing_driven_route_connection_from_heap_thread_func( + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb, + const size_t thread_idx); + + // Expand each neighbor of the current node. + void timing_driven_expand_neighbours( + const RTExploredNode& current, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx); + + // Conditionally adds to_node to the router heap (via path from current.index + // via from_edge). + // + // RR nodes outside bounding box specified in bounding_box are not added + // to the heap. + void timing_driven_expand_neighbour( + const RTExploredNode& current, + RREdgeId from_edge, + RRNodeId to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx); + + // Add to_node to the heap, and also add any nodes which are connected by + // non-configurable edges + void timing_driven_add_to_heap( + const t_conn_cost_params& cost_params, + const RTExploredNode& current, + RRNodeId to_node, + RREdgeId from_edge, + RRNodeId target_node, + size_t thread_idx); + + // Calculates the cost of reaching to_node + void evaluate_timing_driven_node_costs( + RTExploredNode* to, + const t_conn_cost_params& cost_params, + RRNodeId from_node, + RRNodeId target_node); + + // Find paths from current heap to all nodes in the RR graph + vtr::vector timing_driven_find_all_shortest_paths_from_heap( + const t_conn_cost_params& cost_params, + const t_bb& bounding_box); + + //Adds the route tree rooted at rt_node to the heap, preparing it to be + //used as branch-points for further routing. + void add_route_tree_to_heap(const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb); + + //Unconditionally adds rt_node to the heap + // + //Note that if you want to respect rt_node->re_expand that is the caller's + //responsibility. + void add_route_tree_node_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb); + + t_bb add_high_fanout_route_tree_to_heap( + const RouteTreeNode& rt_root, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const SpatialRouteTreeLookup& spatial_route_tree_lookup, + const t_bb& net_bounding_box); + + const DeviceGrid& grid_; + const RouterLookahead& router_lookahead_; + const t_rr_graph_view rr_nodes_; + const RRGraphView* rr_graph_; + vtr::array_view rr_rc_data_; + vtr::array_view rr_switch_inf_; + const vtr::vector>>& net_terminal_groups; + const vtr::vector>& net_terminal_group_num; + vtr::vector& rr_node_route_inf_; + bool is_flat_; + std::vector> modified_rr_node_inf_; + RouterStats* router_stats_; + const ConnectionParameters* conn_params_; + MultiQueueDAryHeap heap_; + std::vector sub_threads_; + barrier_t thread_barrier_; + std::atomic is_router_destroying_; + std::vector locks_; + bool multi_queue_direct_draining_; + + bool router_debug_; + + bool only_opin_inter_layer; + + std::atomic sink_node_; + std::atomic cost_params_; + std::atomic bounding_box_; + std::atomic target_bb_; + + // Cumulative time spent in the path search part of the connection router. + std::chrono::microseconds path_search_cumulative_time; + + // The path manager for RCV, keeps track of the route tree as a set, also + // manages the allocation of `rcv_path_data`. + PathManager rcv_path_manager; + vtr::vector rcv_path_data; +}; + +/** Construct a parallel connection router that uses the specified heap type. + * This function is not used, but removing it will result in "undefined reference" + * errors since heap type specializations won't get emitted from parallel_connection_router.cpp + * without it. + * The alternative is moving all ParallelConnectionRouter fn implementations into the header. */ +std::unique_ptr make_parallel_connection_router( + e_heap_type heap_type, + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat, + int multi_queue_num_threads, + int multi_queue_num_queues, + bool multi_queue_direct_draining); + +#endif /* _PARALLEL_CONNECTION_ROUTER_H */ diff --git a/vpr/src/route/partition_tree.cpp b/vpr/src/route/partition_tree.cpp index ac95a9a5285..0abe48530ce 100644 --- a/vpr/src/route/partition_tree.cpp +++ b/vpr/src/route/partition_tree.cpp @@ -44,7 +44,7 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& * Do this for every step with only given nets, because each cutline takes some nets out * of the game, so if we just built a global lookup it wouldn't yield accurate results. * - * VPR's bounding boxes include the borders (see ConnectionRouter::timing_driven_expand_neighbour()) + * VPR's bounding boxes include the borders (see SerialConnectionRouter::timing_driven_expand_neighbour()) * so try to include x=bb.xmax, y=bb.ymax etc. when calculating things. */ int width = x2 - x1 + 1; int height = y2 - y1 + 1; diff --git a/vpr/src/route/partition_tree.h b/vpr/src/route/partition_tree.h index 82b75976b83..a62b552e065 100644 --- a/vpr/src/route/partition_tree.h +++ b/vpr/src/route/partition_tree.h @@ -1,6 +1,6 @@ #pragma once -#include "connection_router.h" +#include "serial_connection_router.h" #include "netlist_fwd.h" #include "router_stats.h" @@ -27,7 +27,7 @@ inline Side operator!(const Side& rhs) { } /** Part of a net in the context of the \ref DecompNetlistRouter. Sinks and routing resources - * routable/usable by the \ref ConnectionRouter are constrained to ones inside clipped_bb + * routable/usable by the \ref SerialConnectionRouter are constrained to ones inside clipped_bb * (\see inside_bb()) */ class VirtualNet { public: diff --git a/vpr/src/route/route_net.tpp b/vpr/src/route/route_net.tpp index 0e8c4c268a5..71256eb6c22 100644 --- a/vpr/src/route/route_net.tpp +++ b/vpr/src/route/route_net.tpp @@ -140,6 +140,8 @@ inline NetResultFlags route_net(ConnectionRouter& router, t_conn_cost_params cost_params; cost_params.astar_fac = router_opts.astar_fac; cost_params.astar_offset = router_opts.astar_offset; + cost_params.post_target_prune_fac = router_opts.post_target_prune_fac; + cost_params.post_target_prune_offset = router_opts.post_target_prune_offset; cost_params.bend_cost = router_opts.bend_cost; cost_params.pres_fac = pres_fac; cost_params.delay_budget = ((budgeting_inf.if_set()) ? &conn_delay_budget : nullptr); diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index f9c4c1d74a8..6c13e3b58c0 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -88,6 +88,8 @@ bool RouterDelayProfiler::calculate_delay(RRNodeId source_node, cost_params.criticality = 1.; cost_params.astar_fac = router_opts.router_profiler_astar_fac; cost_params.astar_offset = router_opts.astar_offset; + cost_params.post_target_prune_fac = router_opts.post_target_prune_fac; + cost_params.post_target_prune_offset = router_opts.post_target_prune_offset; cost_params.bend_cost = router_opts.bend_cost; route_budgets budgeting_inf(net_list_, is_flat_); @@ -163,6 +165,8 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src cost_params.criticality = 1.; cost_params.astar_fac = router_opts.astar_fac; cost_params.astar_offset = router_opts.astar_offset; + cost_params.post_target_prune_fac = router_opts.post_target_prune_fac; + cost_params.post_target_prune_offset = router_opts.post_target_prune_offset; cost_params.bend_cost = router_opts.bend_cost; /* This function is called during placement. Thus, the flat routing option should be disabled. */ //TODO: Placement is run with is_flat=false. However, since is_flat is passed, det_routing_arch should @@ -174,7 +178,7 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src /*segment_inf=*/{}, is_flat); - ConnectionRouter router( + SerialConnectionRouter router( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h index ca855720d85..f137e143df9 100644 --- a/vpr/src/route/router_delay_profiling.h +++ b/vpr/src/route/router_delay_profiling.h @@ -2,7 +2,7 @@ #define ROUTER_DELAY_PROFILING_H_ #include "vpr_types.h" -#include "connection_router.h" +#include "serial_connection_router.h" #include @@ -43,7 +43,7 @@ class RouterDelayProfiler { private: const Netlist<>& net_list_; RouterStats router_stats_; - ConnectionRouter router_; + SerialConnectionRouter router_; vtr::NdMatrix min_delays_; // [physical_type_idx][from_layer][to_layer][dx][dy] bool is_flat_; }; diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/serial_connection_router.cpp similarity index 96% rename from vpr/src/route/connection_router.cpp rename to vpr/src/route/serial_connection_router.cpp index 7216820726a..3dfdffc09c2 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/serial_connection_router.cpp @@ -1,4 +1,4 @@ -#include "connection_router.h" +#include "serial_connection_router.h" #include #include "rr_graph.h" @@ -17,7 +17,7 @@ static void update_router_stats(RouterStats* router_stats, /** return tuple */ template -std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree( +std::tuple SerialConnectionRouter::timing_driven_route_connection_from_route_tree( const RouteTreeNode& rt_root, RRNodeId sink_node, const t_conn_cost_params& cost_params, @@ -54,7 +54,7 @@ std::tuple ConnectionRouter::timing_driven_rou /** Return whether to retry with full bb */ template -bool ConnectionRouter::timing_driven_route_connection_common_setup( +bool SerialConnectionRouter::timing_driven_route_connection_common_setup( const RouteTreeNode& rt_root, RRNodeId sink_node, const t_conn_cost_params& cost_params, @@ -108,7 +108,7 @@ bool ConnectionRouter::timing_driven_route_connection_common_setup( // which is spatially close to the sink is added to the heap. // Returns a tuple of */ template -std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree_high_fanout( +std::tuple SerialConnectionRouter::timing_driven_route_connection_from_route_tree_high_fanout( const RouteTreeNode& rt_root, RRNodeId sink_node, const t_conn_cost_params& cost_params, @@ -180,7 +180,7 @@ std::tuple ConnectionRouter::timing_driven_rou // Finds a path to sink_node, starting from the elements currently in the heap. // This is the core maze routing routine. template -void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, +void SerialConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, const t_conn_cost_params& cost_params, const t_bb& bounding_box) { VTR_ASSERT_SAFE(heap_.is_valid()); @@ -261,7 +261,7 @@ void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId s // Find shortest paths from specified route tree to all nodes in the RR graph template -vtr::vector ConnectionRouter::timing_driven_find_all_shortest_paths_from_route_tree( +vtr::vector SerialConnectionRouter::timing_driven_find_all_shortest_paths_from_route_tree( const RouteTreeNode& rt_root, const t_conn_cost_params& cost_params, const t_bb& bounding_box, @@ -286,7 +286,7 @@ vtr::vector ConnectionRouter::timing_driven_find // Since there is no single *target* node this uses Dijkstra's algorithm // with a modified exit condition (runs until heap is empty). template -vtr::vector ConnectionRouter::timing_driven_find_all_shortest_paths_from_heap( +vtr::vector SerialConnectionRouter::timing_driven_find_all_shortest_paths_from_heap( const t_conn_cost_params& cost_params, const t_bb& bounding_box) { vtr::vector cheapest_paths(rr_nodes_.size()); @@ -344,7 +344,7 @@ vtr::vector ConnectionRouter::timing_driven_find } template -void ConnectionRouter::timing_driven_expand_cheapest(RRNodeId from_node, +void SerialConnectionRouter::timing_driven_expand_cheapest(RRNodeId from_node, float new_total_cost, RRNodeId target_node, const t_conn_cost_params& cost_params, @@ -392,7 +392,7 @@ void ConnectionRouter::timing_driven_expand_cheapest(RRNodeId from_node, } template -void ConnectionRouter::timing_driven_expand_neighbours(const RTExploredNode& current, +void SerialConnectionRouter::timing_driven_expand_neighbours(const RTExploredNode& current, const t_conn_cost_params& cost_params, const t_bb& bounding_box, RRNodeId target_node, @@ -443,7 +443,7 @@ void ConnectionRouter::timing_driven_expand_neighbours(const RTExploredNod // RR nodes outside the expanded bounding box specified in bounding_box are not added // to the heap. template -void ConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, +void SerialConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, RREdgeId from_edge, RRNodeId to_node, const t_conn_cost_params& cost_params, @@ -527,7 +527,7 @@ void ConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode // Add to_node to the heap, and also add any nodes which are connected by non-configurable edges template -void ConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, +void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, const RTExploredNode& current, RRNodeId to_node, const RREdgeId from_edge, @@ -628,7 +628,7 @@ static bool same_non_config_node_set(RRNodeId from_node, RRNodeId to_node) { #endif template -float ConnectionRouter::compute_node_cost_using_rcv(const t_conn_cost_params cost_params, +float SerialConnectionRouter::compute_node_cost_using_rcv(const t_conn_cost_params cost_params, RRNodeId to_node, RRNodeId target_node, float backwards_delay, @@ -669,13 +669,13 @@ float ConnectionRouter::compute_node_cost_using_rcv(const t_conn_cost_para // Empty the route tree set node, use this after each net is routed template -void ConnectionRouter::empty_rcv_route_tree_set() { +void SerialConnectionRouter::empty_rcv_route_tree_set() { rcv_path_manager.empty_route_tree_nodes(); } // Enable or disable RCV template -void ConnectionRouter::set_rcv_enabled(bool enable) { +void SerialConnectionRouter::set_rcv_enabled(bool enable) { rcv_path_manager.set_enabled(enable); if (enable) { rcv_path_data.resize(rr_node_route_inf_.size()); @@ -684,7 +684,7 @@ void ConnectionRouter::set_rcv_enabled(bool enable) { //Calculates the cost of reaching to_node (i.e., to->index) template -void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, +void SerialConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, const t_conn_cost_params& cost_params, RRNodeId from_node, RRNodeId target_node) { @@ -804,7 +804,7 @@ void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* t //Adds the route tree rooted at rt_node to the heap, preparing it to be //used as branch-points for further routing. template -void ConnectionRouter::add_route_tree_to_heap( +void SerialConnectionRouter::add_route_tree_to_heap( const RouteTreeNode& rt_node, RRNodeId target_node, const t_conn_cost_params& cost_params, @@ -846,7 +846,7 @@ void ConnectionRouter::add_route_tree_to_heap( //Note that if you want to respect rt_node.re_expand that is the caller's //responsibility. template -void ConnectionRouter::add_route_tree_node_to_heap( +void SerialConnectionRouter::add_route_tree_node_to_heap( const RouteTreeNode& rt_node, RRNodeId target_node, const t_conn_cost_params& cost_params, @@ -939,7 +939,7 @@ inline void adjust_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb) { } template -t_bb ConnectionRouter::add_high_fanout_route_tree_to_heap( +t_bb SerialConnectionRouter::add_high_fanout_route_tree_to_heap( const RouteTreeNode& rt_root, RRNodeId target_node, const t_conn_cost_params& cost_params, @@ -1085,7 +1085,7 @@ static inline void update_router_stats(RouterStats* router_stats, } } -std::unique_ptr make_connection_router(e_heap_type heap_type, +std::unique_ptr make_serial_connection_router(e_heap_type heap_type, const DeviceGrid& grid, const RouterLookahead& router_lookahead, const t_rr_graph_storage& rr_nodes, @@ -1096,7 +1096,7 @@ std::unique_ptr make_connection_router(e_heap_type he bool is_flat) { switch (heap_type) { case e_heap_type::BINARY_HEAP: - return std::make_unique>( + return std::make_unique>( grid, router_lookahead, rr_nodes, @@ -1106,7 +1106,7 @@ std::unique_ptr make_connection_router(e_heap_type he rr_node_route_inf, is_flat); case e_heap_type::FOUR_ARY_HEAP: - return std::make_unique>( + return std::make_unique>( grid, router_lookahead, rr_nodes, diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/serial_connection_router.h similarity index 95% rename from vpr/src/route/connection_router.h rename to vpr/src/route/serial_connection_router.h index cee93384974..f7178e8cfc0 100644 --- a/vpr/src/route/connection_router.h +++ b/vpr/src/route/serial_connection_router.h @@ -1,5 +1,5 @@ -#ifndef _CONNECTION_ROUTER_H -#define _CONNECTION_ROUTER_H +#ifndef _SERIAL_CONNECTION_ROUTER_H +#define _SERIAL_CONNECTION_ROUTER_H #include "connection_router_interface.h" #include "rr_graph_storage.h" @@ -16,14 +16,14 @@ // routes from some initial set of sources (via the input rt tree) to a // particular sink. // -// When the ConnectionRouter is used, it mutates the provided +// When the SerialConnectionRouter is used, it mutates the provided // rr_node_route_inf. The routed path can be found by tracing from the sink // node (which is returned) through the rr_node_route_inf. See // update_traceback as an example of this tracing. template -class ConnectionRouter : public ConnectionRouterInterface { +class SerialConnectionRouter : public ConnectionRouterInterface { public: - ConnectionRouter( + SerialConnectionRouter( const DeviceGrid& grid, const RouterLookahead& router_lookahead, const t_rr_graph_storage& rr_nodes, @@ -49,7 +49,7 @@ class ConnectionRouter : public ConnectionRouterInterface { only_opin_inter_layer = (grid.get_num_layers() > 1) && inter_layer_connections_limited_to_opin(*rr_graph); } - ~ConnectionRouter() { + ~SerialConnectionRouter() { VTR_LOG("Serial Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", std::chrono::duration(path_search_cumulative_time).count()); } @@ -311,12 +311,12 @@ class ConnectionRouter : public ConnectionRouterInterface { vtr::vector rcv_path_data; }; -/** Construct a connection router that uses the specified heap type. +/** Construct a serial connection router that uses the specified heap type. * This function is not used, but removing it will result in "undefined reference" - * errors since heap type specializations won't get emitted from connection_router.cpp + * errors since heap type specializations won't get emitted from serial_connection_router.cpp * without it. - * The alternative is moving all ConnectionRouter fn implementations into the header. */ -std::unique_ptr make_connection_router( + * The alternative is moving all SerialConnectionRouter fn implementations into the header. */ +std::unique_ptr make_serial_connection_router( e_heap_type heap_type, const DeviceGrid& grid, const RouterLookahead& router_lookahead, @@ -327,4 +327,4 @@ std::unique_ptr make_connection_router( vtr::vector& rr_node_route_inf, bool is_flat); -#endif /* _CONNECTION_ROUTER_H */ +#endif /* _SERIAL_CONNECTION_ROUTER_H */ diff --git a/vpr/test/test_connection_router.cpp b/vpr/test/test_connection_router.cpp index fbf1a63e142..1169d5f4b3d 100644 --- a/vpr/test/test_connection_router.cpp +++ b/vpr/test/test_connection_router.cpp @@ -8,7 +8,7 @@ #include "globals.h" #include "net_delay.h" #include "place_and_route.h" -#include "connection_router.h" +#include "serial_connection_router.h" #include "router_delay_profiling.h" static constexpr const char kArchFile[] = "../../vtr_flow/arch/timing/k6_frac_N10_mem32K_40nm.xml"; @@ -56,7 +56,8 @@ static float do_one_route(RRNodeId source_node, segment_inf, is_flat); - ConnectionRouter router( + // TODO: adding tests for parallel connection router + SerialConnectionRouter router( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), From 875b98efb13404a23dce2f3786d924904c27772b Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Sun, 9 Mar 2025 22:05:36 -0400 Subject: [PATCH 004/176] [ParallelRouter] Removed Boost from FG Parallel Router The original FG parallel router used to use boost. VTR does not install boost by default. Moved to STL instead. --- vpr/src/route/multi_queue_d_ary_heap.h | 9 +++---- vpr/src/route/multi_queue_d_ary_heap.tpp | 31 ++++++++++++------------ 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h index d81544135a3..27a2168429e 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.h +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -20,8 +20,7 @@ #ifndef _MULTI_QUEUE_D_ARY_HEAP_H #define _MULTI_QUEUE_D_ARY_HEAP_H -#include - +#include #include "device_grid.h" #include "heap_type.h" #include "multi_queue_d_ary_heap.tpp" @@ -59,11 +58,11 @@ class MultiQueueDAryHeap { bool try_pop(HeapNode& heap_node) { auto tmp = pq_->tryPop(); - if (!tmp) { + if (!tmp.has_value()) { return false; } else { uint32_t node_id; - std::tie(heap_node.prio, node_id) = tmp.get(); // FIXME: eliminate type cast by modifying MQ_IO + std::tie(heap_node.prio, node_id) = tmp.value(); // FIXME: eliminate type cast by modifying MQ_IO heap_node.node = RRNodeId(node_id); return true; } @@ -124,4 +123,4 @@ class MultiQueueDAryHeap { }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/route/multi_queue_d_ary_heap.tpp b/vpr/src/route/multi_queue_d_ary_heap.tpp index 059689a0693..5e768fa67c3 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.tpp +++ b/vpr/src/route/multi_queue_d_ary_heap.tpp @@ -22,16 +22,11 @@ #include #include #include -#include +#include #include #include -#include -#include -#include #include #include -#include -#include #include "d_ary_heap.tpp" #define CACHELINE 64 @@ -68,8 +63,12 @@ class MultiQueueIO { } __attribute__((aligned (CACHELINE))); std::vector< - PQContainer, - boost::alignment::aligned_allocator + PQContainer + // FIXME: Disabled this due to VTR not using Boost. There is a C++ way + // of doing this, but it requires making an aligned allocator + // class. May be a good idea to add to VTR util in the future. + // Should profile for performance first; may not be worth it. + // , boost::alignment::aligned_allocator > queues; uint64_t NUM_QUEUES; @@ -181,7 +180,7 @@ class MultiQueueIO { #ifdef PERF boost::optional __attribute__ ((noinline)) tryPop() { #else - inline boost::optional tryPop() { + inline std::optional tryPop() { #endif auto item = pop(); if (item) return item; @@ -191,7 +190,7 @@ class MultiQueueIO { do { item = pop(); if (item) break; - if (num >= threadNum) return boost::none; + if (num >= threadNum) return {}; num = numIdle.load(std::memory_order_relaxed); @@ -212,7 +211,7 @@ class MultiQueueIO { #ifdef PERF boost::optional __attribute__ ((noinline)) pop() { #else - inline boost::optional pop() { + inline std::optional pop() { #endif uint64_t poppingQueue = NUM_QUEUES; while (true) { @@ -270,13 +269,13 @@ class MultiQueueIO { } q.unlock(); } - return boost::none; + return {}; } #ifdef PERF boost::optional __attribute__ ((noinline)) tryPopBatch(PQElement* ret) { #else - inline boost::optional tryPopBatch(PQElement* ret) { + inline std::optional tryPopBatch(PQElement* ret) { #endif auto item = popBatch(ret); if (item) return item; @@ -286,7 +285,7 @@ class MultiQueueIO { do { item = popBatch(ret); if (item) break; - if (num >= threadNum) return boost::none; + if (num >= threadNum) return {}; num = numIdle.load(std::memory_order_relaxed); @@ -308,7 +307,7 @@ class MultiQueueIO { #ifdef PERF boost::optional __attribute__ ((noinline)) popBatch(PQElement* ret) { #else - inline boost::optional popBatch(PQElement* ret) { + inline std::optional popBatch(PQElement* ret) { #endif uint64_t poppingQueue = NUM_QUEUES; while (true) { @@ -367,7 +366,7 @@ class MultiQueueIO { return num; } - return boost::none; + return {}; } inline uint64_t getQueueOccupancy() const { From 25bfd189de4dfc29573852385e330069db72d9cb Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Tue, 25 Mar 2025 09:40:51 -0400 Subject: [PATCH 005/176] [Router] Fix Code Formatting Issues --- .../src/include/internal_bits.hpp | 8 +- vpr/src/route/SerialNetlistRouter.h | 6 +- vpr/src/route/multi_queue_d_ary_heap.h | 5 +- vpr/src/route/multi_queue_d_ary_heap.tpp | 262 +++++++++--------- vpr/src/route/parallel_connection_router.cpp | 102 +++---- vpr/src/route/parallel_connection_router.h | 24 +- vpr/src/route/serial_connection_router.cpp | 74 ++--- 7 files changed, 244 insertions(+), 237 deletions(-) diff --git a/libs/librtlnumber/src/include/internal_bits.hpp b/libs/librtlnumber/src/include/internal_bits.hpp index 0d5c7388470..ffefb5a4d9a 100644 --- a/libs/librtlnumber/src/include/internal_bits.hpp +++ b/libs/librtlnumber/src/include/internal_bits.hpp @@ -27,14 +27,14 @@ constexpr short integer_t_size = (sizeof(integer_t) * 8); } #define unroll_1d(lut) \ - { lut[_0], lut[_1], lut[_x], lut[_z] } + {lut[_0], lut[_1], lut[_x], lut[_z]} #define unroll_2d(lut) \ - { unroll_1d(lut[_0]), unroll_1d(lut[_1]), unroll_1d(lut[_x]), unroll_1d(lut[_z]) } + {unroll_1d(lut[_0]), unroll_1d(lut[_1]), unroll_1d(lut[_x]), unroll_1d(lut[_z])} #define unroll_1d_invert(lut) \ - { l_not[lut[_0]], l_not[lut[_1]], l_not[lut[_x]], l_not[lut[_z]] } + {l_not[lut[_0]], l_not[lut[_1]], l_not[lut[_x]], l_not[lut[_z]]} #define unroll_2d_invert(lut) \ - { unroll_1d_invert(lut[_0]), unroll_1d_invert(lut[_1]), unroll_1d_invert(lut[_x]), unroll_1d_invert(lut[_z]) } + {unroll_1d_invert(lut[_0]), unroll_1d_invert(lut[_1]), unroll_1d_invert(lut[_x]), unroll_1d_invert(lut[_z])} namespace BitSpace { typedef uint8_t bit_value_t; diff --git a/vpr/src/route/SerialNetlistRouter.h b/vpr/src/route/SerialNetlistRouter.h index 67df5130ebd..896c5173b13 100644 --- a/vpr/src/route/SerialNetlistRouter.h +++ b/vpr/src/route/SerialNetlistRouter.h @@ -35,7 +35,7 @@ class SerialNetlistRouter : public NetlistRouter { , _choking_spots(choking_spots) , _is_flat(is_flat) {} ~SerialNetlistRouter() { - delete _router; + delete _router; } RouteIterResults route_netlist(int itry, float pres_fac, float worst_neg_slack); @@ -44,7 +44,7 @@ class SerialNetlistRouter : public NetlistRouter { void set_timing_info(std::shared_ptr timing_info); private: - ConnectionRouterInterface *_make_router(const RouterLookahead* router_lookahead, + ConnectionRouterInterface* _make_router(const RouterLookahead* router_lookahead, const t_router_opts& router_opts, bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); @@ -78,7 +78,7 @@ class SerialNetlistRouter : public NetlistRouter { } } /* Context fields */ - ConnectionRouterInterface *_router; + ConnectionRouterInterface* _router; const Netlist<>& _net_list; const t_router_opts& _router_opts; CBRR& _connections_inf; diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h index 27a2168429e..b200e0db0d4 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.h +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -25,7 +25,7 @@ #include "heap_type.h" #include "multi_queue_d_ary_heap.tpp" -using MQHeapNode = std::tuple; +using MQHeapNode = std::tuple; // FIXME: use unified heap node struct and comparator in heap_type.h struct MQHeapNodeTupleComparator { @@ -119,8 +119,7 @@ class MultiQueueDAryHeap { #endif private: - MQ_IO *pq_; + MQ_IO* pq_; }; - #endif diff --git a/vpr/src/route/multi_queue_d_ary_heap.tpp b/vpr/src/route/multi_queue_d_ary_heap.tpp index 5e768fa67c3..e7ed202a7e4 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.tpp +++ b/vpr/src/route/multi_queue_d_ary_heap.tpp @@ -38,8 +38,7 @@ template< unsigned D, typename PQElement, typename Comparator, - typename PrioType -> + typename PrioType> class MultiQueueIO { using PQ = customized_d_ary_priority_queue, Comparator>; Comparator compare; @@ -56,11 +55,14 @@ class MultiQueueIO { std::atomic_flag queueLock = ATOMIC_FLAG_INIT; std::atomic min{EMPTY_PRIO}; - void lock() { while(queueLock.test_and_set(std::memory_order_acquire)); } + void lock() { + while (queueLock.test_and_set(std::memory_order_acquire)) + ; + } bool try_lock() { return queueLock.test_and_set(std::memory_order_acquire); } void unlock() { queueLock.clear(std::memory_order_release); } - } __attribute__((aligned (CACHELINE))); + } __attribute__((aligned(CACHELINE))); std::vector< PQContainer @@ -69,7 +71,8 @@ class MultiQueueIO { // class. May be a good idea to add to VTR util in the future. // Should profile for performance first; may not be worth it. // , boost::alignment::aligned_allocator - > queues; + > + queues; uint64_t NUM_QUEUES; // Termination: @@ -86,7 +89,6 @@ class MultiQueueIO { uint64_t batchSize; public: - MultiQueueIO(uint64_t numQueues, uint64_t numThreads, uint64_t batch) : queues(numQueues) , NUM_QUEUES(numQueues) @@ -95,7 +97,7 @@ class MultiQueueIO { , batchSize(batch) {} #ifdef PERF - uint64_t __attribute__ ((noinline)) ThreadLocalRandom() { + uint64_t __attribute__((noinline)) ThreadLocalRandom() { #else uint64_t ThreadLocalRandom() { #endif @@ -111,13 +113,13 @@ class MultiQueueIO { } #ifdef PERF - void __attribute__ ((noinline)) pushInt(uint64_t queue, PQElement item) { + void __attribute__((noinline)) pushInt(uint64_t queue, PQElement item) { queues[queue].pq.push(item); } #endif #ifdef PERF - void __attribute__ ((noinline)) push(PQElement item) { + void __attribute__((noinline)) push(PQElement item) { #else inline void push(PQElement item) { #endif @@ -139,15 +141,14 @@ class MultiQueueIO { q.pq.size() > 0 ? std::get<0>(q.pq.top()) : EMPTY_PRIO, - std::memory_order_release - ); + std::memory_order_release); q.unlock(); } #ifdef PERF - void __attribute__ ((noinline)) pushBatch(uint64_t size, PQElement *items) { + void __attribute__((noinline)) pushBatch(uint64_t size, PQElement* items) { #else - inline void pushBatch(uint64_t size, PQElement *items) { + inline void pushBatch(uint64_t size, PQElement* items) { #endif uint64_t queue; while (true) { @@ -169,8 +170,7 @@ class MultiQueueIO { q.pq.size() > 0 ? std::get<0>(q.pq.top()) : EMPTY_PRIO, - std::memory_order_release - ); + std::memory_order_release); q.unlock(); } @@ -178,7 +178,7 @@ class MultiQueueIO { // Repeatedly try popping and stop when numIdle >= threadNum, // That is, stop when all threads agree that there are no more work #ifdef PERF - boost::optional __attribute__ ((noinline)) tryPop() { + boost::optional __attribute__((noinline)) tryPop() { #else inline std::optional tryPop() { #endif @@ -203,13 +203,13 @@ class MultiQueueIO { #ifdef MQ_IO_ENABLE_CLEAR_FOR_POP inline void setMinPrioForPop(PrioType newMinPrio) { PrioType oldMinPrio = minPrioForPop.load(std::memory_order_relaxed); - while (compare({oldMinPrio, 0}, {newMinPrio, 0}) /* old > new */ && - !minPrioForPop.compare_exchange_weak(oldMinPrio, newMinPrio)) ; + while (compare({oldMinPrio, 0}, {newMinPrio, 0}) /* old > new */ && !minPrioForPop.compare_exchange_weak(oldMinPrio, newMinPrio)) + ; } #endif #ifdef PERF - boost::optional __attribute__ ((noinline)) pop() { + boost::optional __attribute__((noinline)) pop() { #else inline std::optional pop() { #endif @@ -227,8 +227,10 @@ class MultiQueueIO { if (minI == EMPTY_PRIO && minJ == EMPTY_PRIO) { uint64_t emptyQueues = numEmpty.load(std::memory_order_relaxed); - if (emptyQueues >= queues.size()) break; - else continue; + if (emptyQueues >= queues.size()) + break; + else + continue; } if (minI != EMPTY_PRIO && minJ != EMPTY_PRIO) { @@ -259,8 +261,7 @@ class MultiQueueIO { q.pq.size() > 0 ? std::get<0>(q.pq.top()) : EMPTY_PRIO, - std::memory_order_release - ); + std::memory_order_release); q.unlock(); return retItem; #ifdef MQ_IO_ENABLE_CLEAR_FOR_POP @@ -273,7 +274,7 @@ class MultiQueueIO { } #ifdef PERF - boost::optional __attribute__ ((noinline)) tryPopBatch(PQElement* ret) { + boost::optional __attribute__((noinline)) tryPopBatch(PQElement* ret) { #else inline std::optional tryPopBatch(PQElement* ret) { #endif @@ -296,139 +297,140 @@ class MultiQueueIO { } #ifdef PERF - void __attribute__ ((noinline)) popInt(uint64_t queue, PQElement *ret) { + void __attribute__((noinline)) popInt(uint64_t queue, PQElement* ret) { auto& q = queues[queue]; *ret = q.pq.top(); q.pq.pop(); } #endif - #ifdef PERF - boost::optional __attribute__ ((noinline)) popBatch(PQElement* ret) { + boost::optional __attribute__((noinline)) popBatch(PQElement* ret){ #else inline std::optional popBatch(PQElement* ret) { #endif uint64_t poppingQueue = NUM_QUEUES; - while (true) { - // Pick the higher priority max of queue i and j - uint64_t i = ThreadLocalRandom(); - uint64_t j = ThreadLocalRandom(); - while (j == i) { - j = ThreadLocalRandom(); - } - - PrioType minI = queues[i].min.load(std::memory_order_acquire); - PrioType minJ = queues[j].min.load(std::memory_order_acquire); + while (true) { + // Pick the higher priority max of queue i and j + uint64_t i = ThreadLocalRandom(); + uint64_t j = ThreadLocalRandom(); + while (j == i) { + j = ThreadLocalRandom(); + } - if (minI == EMPTY_PRIO && minJ == EMPTY_PRIO) { - uint64_t emptyQueues = numEmpty.load(std::memory_order_relaxed); - if (emptyQueues >= queues.size()) break; - else continue; - } + PrioType minI = queues[i].min.load(std::memory_order_acquire); + PrioType minJ = queues[j].min.load(std::memory_order_acquire); - if (minI != EMPTY_PRIO && minJ != EMPTY_PRIO) { - poppingQueue = compare({minJ, 0}, {minI, 0}) ? i : j; - } else if (minJ == EMPTY_PRIO) { - poppingQueue = i; - } else { - poppingQueue = j; - } - if (queues[poppingQueue].try_lock()) continue; - auto& q = queues[poppingQueue]; - if (q.pq.empty()) { - q.unlock(); + if (minI == EMPTY_PRIO && minJ == EMPTY_PRIO) { + uint64_t emptyQueues = numEmpty.load(std::memory_order_relaxed); + if (emptyQueues >= queues.size()) + break; + else continue; - } + } - uint64_t num = 0; - for (num = 0; num < batchSize; num++) { - if (q.pq.empty()) break; + if (minI != EMPTY_PRIO && minJ != EMPTY_PRIO) { + poppingQueue = compare({minJ, 0}, {minI, 0}) ? i : j; + } else if (minJ == EMPTY_PRIO) { + poppingQueue = i; + } else { + poppingQueue = j; + } + if (queues[poppingQueue].try_lock()) continue; + auto& q = queues[poppingQueue]; + if (q.pq.empty()) { + q.unlock(); + continue; + } + + uint64_t num = 0; + for (num = 0; num < batchSize; num++) { + if (q.pq.empty()) break; #ifdef PERF - popInt(poppingQueue, &ret[num]); + popInt(poppingQueue, &ret[num]); #else ret[num] = q.pq.top(); q.pq.pop(); #endif - - } - q.pops += num; - if (q.pq.empty()) - numEmpty.fetch_add(1, std::memory_order_relaxed); - q.min.store( - q.pq.size() > 0 - ? std::get<0>(q.pq.top()) - : EMPTY_PRIO, - std::memory_order_release - ); - q.unlock(); - if (num == 0) continue; - - return num; } - return {}; - } + q.pops += num; + if (q.pq.empty()) + numEmpty.fetch_add(1, std::memory_order_relaxed); + q.min.store( + q.pq.size() > 0 + ? std::get<0>(q.pq.top()) + : EMPTY_PRIO, + std::memory_order_release); + q.unlock(); + if (num == 0) continue; - inline uint64_t getQueueOccupancy() const { - uint64_t maxOccupancy = 0; - for (uint64_t i = 0; i < NUM_QUEUES; i++) { - maxOccupancy = std::max(maxOccupancy, queues[i].pq.size()); - } - return maxOccupancy; + return num; } - - // Get the number of pushes to all queues. - // Note: this is not lock protected. - inline uint64_t getNumPushes() const { - uint64_t totalPushes = 0; - for (uint64_t i = 0; i < NUM_QUEUES; i++) { - totalPushes += queues[i].pushes; - } - return totalPushes; + return {}; +} + +inline uint64_t +getQueueOccupancy() const { + uint64_t maxOccupancy = 0; + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + maxOccupancy = std::max(maxOccupancy, queues[i].pq.size()); } - - // Get the number of pops to all queues. - // Note: this is not lock protected. - inline uint64_t getNumPops() const { - uint64_t totalPops = 0; - for (uint64_t i = 0; i < NUM_QUEUES; i++) { - totalPops += queues[i].pops; - } - return totalPops; + return maxOccupancy; +} + +// Get the number of pushes to all queues. +// Note: this is not lock protected. +inline uint64_t getNumPushes() const { + uint64_t totalPushes = 0; + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + totalPushes += queues[i].pushes; } - - inline void stat() const { - std::cout << "total pushes "<< getNumPushes() << "\n"; - std::cout << "total pops "<< getNumPops() << "\n"; + return totalPushes; +} + +// Get the number of pops to all queues. +// Note: this is not lock protected. +inline uint64_t getNumPops() const { + uint64_t totalPops = 0; + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + totalPops += queues[i].pops; } - - // Note: this is only called at the end of algorithm as a - // sanity check, therefore it is not lock protected. - inline bool empty() const { - for (uint i = 0; i < NUM_QUEUES;i++) { - if (!queues[i].pq.empty()) { - return false; - } + return totalPops; +} + +inline void stat() const { + std::cout << "total pushes " << getNumPushes() << "\n"; + std::cout << "total pops " << getNumPops() << "\n"; +} + +// Note: this is only called at the end of algorithm as a +// sanity check, therefore it is not lock protected. +inline bool empty() const { + for (uint i = 0; i < NUM_QUEUES; i++) { + if (!queues[i].pq.empty()) { + return false; } - return true; } - - // Resets the MultiQueue to a state as if it was reinitialized. - // This must be called before using the MQ again after using TypPop(). - // Note: this assumes the queues are already empty and unlocked. - inline void reset() { - for (uint64_t i = 0; i < NUM_QUEUES; i++) { - assert(queues[i].pq.empty() && "reset() assumes empty queues"); - assert((queues[i].queueLock.test(std::memory_order_relaxed) == 0) - && "reset() assumes unlocked queues"); - queues[i].pushes = 0; - queues[i].pops = 0; - queues[i].min.store(EMPTY_PRIO, std::memory_order_relaxed); - } - numIdle.store(0, std::memory_order_relaxed); - numEmpty.store(NUM_QUEUES, std::memory_order_relaxed); + return true; +} + +// Resets the MultiQueue to a state as if it was reinitialized. +// This must be called before using the MQ again after using TypPop(). +// Note: this assumes the queues are already empty and unlocked. +inline void reset() { + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + assert(queues[i].pq.empty() && "reset() assumes empty queues"); + assert((queues[i].queueLock.test(std::memory_order_relaxed) == 0) + && "reset() assumes unlocked queues"); + queues[i].pushes = 0; + queues[i].pops = 0; + queues[i].min.store(EMPTY_PRIO, std::memory_order_relaxed); + } + numIdle.store(0, std::memory_order_relaxed); + numEmpty.store(NUM_QUEUES, std::memory_order_relaxed); #ifdef MQ_IO_ENABLE_CLEAR_FOR_POP - minPrioForPop.store(std::numeric_limits::max(), std::memory_order_relaxed); + minPrioForPop.store(std::numeric_limits::max(), std::memory_order_relaxed); #endif - } -}; +} +} +; diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp index 1794f53d5a7..98df4d341cc 100644 --- a/vpr/src/route/parallel_connection_router.cpp +++ b/vpr/src/route/parallel_connection_router.cpp @@ -276,11 +276,11 @@ static inline bool prune_node(RRNodeId inode, } static inline bool should_not_explore_neighbors(RRNodeId inode, - float new_total_cost, - float new_back_cost, - RRNodeId target_node, - vtr::vector& rr_node_route_inf_, - const t_conn_cost_params& params) { + float new_total_cost, + float new_back_cost, + RRNodeId target_node, + vtr::vector& rr_node_route_inf_, + const t_conn_cost_params& params) { #ifndef NON_DETERMINISTIC_PRUNING // For deterministic pruning, cannot enforce anything on the total cost since // traversal order is not gaurenteed. However, since total cost is used as a @@ -313,8 +313,8 @@ static inline bool should_not_explore_neighbors(RRNodeId inode, // This is the core maze routing routine. template void ParallelConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { VTR_ASSERT_SAFE(heap_.is_valid()); if (heap_.is_empty_heap()) { //No source @@ -384,14 +384,14 @@ void ParallelConnectionRouter::timing_driven_route_connection_from_heap_su template void ParallelConnectionRouter::timing_driven_route_connection_from_heap_thread_func(RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - const t_bb& target_bb, - const size_t thread_idx) { + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb, + const size_t thread_idx) { HeapNode cheapest; while (heap_.try_pop(cheapest)) { // inode with the cheapest total cost in current route tree to be expanded on - const auto& [ new_total_cost, inode ] = cheapest; + const auto& [new_total_cost, inode] = cheapest; // Should we explore the neighbors of this node? if (should_not_explore_neighbors(inode, new_total_cost, rr_node_route_inf_[inode].backward_path_cost, sink_node, rr_node_route_inf_, cost_params)) { @@ -457,11 +457,11 @@ vtr::vector ParallelConnectionRouter::timing_dri template void ParallelConnectionRouter::timing_driven_expand_neighbours(const RTExploredNode& current, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RRNodeId target_node, - const t_bb& target_bb, - size_t thread_idx) { + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx) { /* Puts all the rr_nodes adjacent to current on the heap. */ // For each node associated with the current heap element, expand all of it's neighbors @@ -510,13 +510,13 @@ void ParallelConnectionRouter::timing_driven_expand_neighbours(const RTExp // to the heap. template void ParallelConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, - RREdgeId from_edge, - RRNodeId to_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RRNodeId target_node, - const t_bb& target_bb, - size_t thread_idx) { + RREdgeId from_edge, + RRNodeId to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx) { // VTR_ASSERT(bounding_box.layer_max < g_vpr_ctx.device().grid.get_num_layers()); // const RRNodeId& from_node = current.index; @@ -575,21 +575,21 @@ void ParallelConnectionRouter::timing_driven_expand_neighbour(const RTExpl // from_node, size_t(from_edge), size_t(to_node)); timing_driven_add_to_heap(cost_params, - current, - to_node, - from_edge, - target_node, - thread_idx); + current, + to_node, + from_edge, + target_node, + thread_idx); } // Add to_node to the heap, and also add any nodes which are connected by non-configurable edges template void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, - const RTExploredNode& current, - RRNodeId to_node, - const RREdgeId from_edge, - RRNodeId target_node, - size_t thread_idx) { + const RTExploredNode& current, + RRNodeId to_node, + const RREdgeId from_edge, + RRNodeId target_node, + size_t thread_idx) { const RRNodeId& from_node = current.index; // Initialized to current @@ -629,7 +629,7 @@ void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost heap_.setMinPrioForPop(new_total_cost); } #endif - return ; + return; } heap_.add_to_heap({new_total_cost, to_node}); @@ -673,9 +673,9 @@ void ParallelConnectionRouter::set_rcv_enabled(bool enable) { //Calculates the cost of reaching to_node (i.e., to->index) template void ParallelConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, - const t_conn_cost_params& cost_params, - RRNodeId from_node, - RRNodeId target_node) { + const t_conn_cost_params& cost_params, + RRNodeId from_node, + RRNodeId target_node) { /* new_costs.backward_cost: is the "known" part of the cost to this node -- the * congestion cost of all the routing resources back to the existing route * plus the known delay of the total path back to the source. @@ -851,9 +851,9 @@ void ParallelConnectionRouter::add_route_tree_node_to_heap( describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, is_flat_).c_str()); if (prune_node(inode, tot_cost, backward_path_cost, RREdgeId::INVALID(), target_node, rr_node_route_inf_, cost_params)) { - return ; + return; } - add_to_mod_list(inode, 0/*main thread*/); + add_to_mod_list(inode, 0 /*main thread*/); rr_node_route_inf_[inode].path_cost = tot_cost; rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; @@ -1039,17 +1039,17 @@ static inline void update_router_stats(RouterStats* router_stats, } std::unique_ptr make_parallel_connection_router(e_heap_type heap_type, - const DeviceGrid& grid, - const RouterLookahead& router_lookahead, - const t_rr_graph_storage& rr_nodes, - const RRGraphView* rr_graph, - const std::vector& rr_rc_data, - const vtr::vector& rr_switch_inf, - vtr::vector& rr_node_route_inf, - bool is_flat, - int multi_queue_num_threads, - int multi_queue_num_queues, - bool multi_queue_direct_draining) { + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat, + int multi_queue_num_threads, + int multi_queue_num_queues, + bool multi_queue_direct_draining) { switch (heap_type) { case e_heap_type::BINARY_HEAP: return std::make_unique>( diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h index 692c285c2cd..1c8fd19c35d 100644 --- a/vpr/src/route/parallel_connection_router.h +++ b/vpr/src/route/parallel_connection_router.h @@ -20,9 +20,11 @@ class spin_lock_t { std::atomic_flag lock_ = ATOMIC_FLAG_INIT; -public: + + public: void acquire() { - while (std::atomic_flag_test_and_set_explicit(&lock_, std::memory_order_acquire)); + while (std::atomic_flag_test_and_set_explicit(&lock_, std::memory_order_acquire)) + ; } void release() { @@ -36,14 +38,17 @@ class barrier_mutex_t { size_t count_; size_t max_count_; size_t generation_ = 0; -public: - explicit barrier_mutex_t(size_t num_threads) : count_(num_threads), max_count_(num_threads) { } + + public: + explicit barrier_mutex_t(size_t num_threads) + : count_(num_threads) + , max_count_(num_threads) {} void wait() { std::unique_lock lock{mutex_}; size_t gen = generation_; if (--count_ == 0) { - generation_ ++; + generation_++; count_ = max_count_; cv_.notify_all(); } else { @@ -58,7 +63,7 @@ class barrier_spin_t { std::atomic sense_ = false; // global sense shared by multiple threads inline static thread_local bool local_sense_ = false; -public: + public: explicit barrier_spin_t(size_t num_threads) { num_threads_ = num_threads; } void init() { @@ -73,7 +78,8 @@ class barrier_spin_t { count_.store(0); sense_.store(s); } else { - while (sense_.load() != s) ; + while (sense_.load() != s) + ; } } }; @@ -127,7 +133,7 @@ class ParallelConnectionRouter : public ConnectionRouterInterface { sub_threads_.resize(multi_queue_num_threads - 1); thread_barrier_.init(); - for (int i = 0 ; i < multi_queue_num_threads - 1; ++i) { + for (int i = 0; i < multi_queue_num_threads - 1; ++i) { sub_threads_[i] = std::thread(&ParallelConnectionRouter::timing_driven_route_connection_from_heap_sub_thread_wrapper, this, i + 1 /*0: main thread*/); sub_threads_[i].detach(); } @@ -138,7 +144,7 @@ class ParallelConnectionRouter : public ConnectionRouterInterface { thread_barrier_.wait(); VTR_LOG("Parallel Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", - std::chrono::duration(path_search_cumulative_time).count()); + std::chrono::duration(path_search_cumulative_time).count()); } // Clear's the modified list. Should be called after reset_path_costs diff --git a/vpr/src/route/serial_connection_router.cpp b/vpr/src/route/serial_connection_router.cpp index 0080424bd2a..3c03ed71fa6 100644 --- a/vpr/src/route/serial_connection_router.cpp +++ b/vpr/src/route/serial_connection_router.cpp @@ -181,8 +181,8 @@ std::tuple SerialConnectionRouter::timing_driv // This is the core maze routing routine. template void SerialConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { VTR_ASSERT_SAFE(heap_.is_valid()); if (heap_.is_empty_heap()) { //No source @@ -345,11 +345,11 @@ vtr::vector SerialConnectionRouter::timing_drive template void SerialConnectionRouter::timing_driven_expand_cheapest(RRNodeId from_node, - float new_total_cost, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - const t_bb& target_bb) { + float new_total_cost, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) { float best_total_cost = rr_node_route_inf_[from_node].path_cost; if (best_total_cost == new_total_cost) { // Explore from this node, since its total cost is exactly the same as @@ -393,10 +393,10 @@ void SerialConnectionRouter::timing_driven_expand_cheapest(RRNodeId from_n template void SerialConnectionRouter::timing_driven_expand_neighbours(const RTExploredNode& current, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RRNodeId target_node, - const t_bb& target_bb) { + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb) { /* Puts all the rr_nodes adjacent to current on the heap. */ // For each node associated with the current heap element, expand all of it's neighbors @@ -444,12 +444,12 @@ void SerialConnectionRouter::timing_driven_expand_neighbours(const RTExplo // to the heap. template void SerialConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, - RREdgeId from_edge, - RRNodeId to_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RRNodeId target_node, - const t_bb& target_bb) { + RREdgeId from_edge, + RRNodeId to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb) { VTR_ASSERT(bounding_box.layer_max < g_vpr_ctx.device().grid.get_num_layers()); const RRNodeId& from_node = current.index; @@ -528,10 +528,10 @@ void SerialConnectionRouter::timing_driven_expand_neighbour(const RTExplor // Add to_node to the heap, and also add any nodes which are connected by non-configurable edges template void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, - const RTExploredNode& current, - RRNodeId to_node, - const RREdgeId from_edge, - RRNodeId target_node) { + const RTExploredNode& current, + RRNodeId to_node, + const RREdgeId from_edge, + RRNodeId target_node) { const auto& device_ctx = g_vpr_ctx.device(); const RRNodeId& from_node = current.index; @@ -628,11 +628,11 @@ static bool same_non_config_node_set(RRNodeId from_node, RRNodeId to_node) { template float SerialConnectionRouter::compute_node_cost_using_rcv(const t_conn_cost_params cost_params, - RRNodeId to_node, - RRNodeId target_node, - float backwards_delay, - float backwards_cong, - float R_upstream) { + RRNodeId to_node, + RRNodeId target_node, + float backwards_delay, + float backwards_cong, + float R_upstream) { float expected_delay; float expected_cong; @@ -684,9 +684,9 @@ void SerialConnectionRouter::set_rcv_enabled(bool enable) { //Calculates the cost of reaching to_node (i.e., to->index) template void SerialConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, - const t_conn_cost_params& cost_params, - RRNodeId from_node, - RRNodeId target_node) { + const t_conn_cost_params& cost_params, + RRNodeId from_node, + RRNodeId target_node) { /* new_costs.backward_cost: is the "known" part of the cost to this node -- the * congestion cost of all the routing resources back to the existing route * plus the known delay of the total path back to the source. @@ -1085,14 +1085,14 @@ static inline void update_router_stats(RouterStats* router_stats, } std::unique_ptr make_serial_connection_router(e_heap_type heap_type, - const DeviceGrid& grid, - const RouterLookahead& router_lookahead, - const t_rr_graph_storage& rr_nodes, - const RRGraphView* rr_graph, - const std::vector& rr_rc_data, - const vtr::vector& rr_switch_inf, - vtr::vector& rr_node_route_inf, - bool is_flat) { + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat) { switch (heap_type) { case e_heap_type::BINARY_HEAP: return std::make_unique>( From 203c7382b6c74cb8872e1125a8997261a8b7e5b0 Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Mon, 31 Mar 2025 10:01:49 -0400 Subject: [PATCH 006/176] [Router] Added ConnectionRouter Abstraction and Reduced Code Duplication Added a partial abstract class for ConnectionRouter, derived from the pure abstract ConnectionRouterInterface. The SerialConnectionRouter and ParallelConnectionRouter classes are now derived from the ConnectionRouter class, utilizing the common class members and helper functions to reduce code duplication. --- vpr/src/route/connection_router.h | 238 ++++++ vpr/src/route/connection_router.tpp | 600 ++++++++++++++ vpr/src/route/parallel_connection_router.cpp | 698 ++-------------- vpr/src/route/parallel_connection_router.h | 241 ++---- vpr/src/route/route_net.tpp | 12 +- vpr/src/route/serial_connection_router.cpp | 826 +++---------------- vpr/src/route/serial_connection_router.h | 205 +---- 7 files changed, 1090 insertions(+), 1730 deletions(-) create mode 100644 vpr/src/route/connection_router.h create mode 100644 vpr/src/route/connection_router.tpp diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/connection_router.h new file mode 100644 index 00000000000..12e488aa413 --- /dev/null +++ b/vpr/src/route/connection_router.h @@ -0,0 +1,238 @@ +#ifndef _CONNECTION_ROUTER_H +#define _CONNECTION_ROUTER_H + +#include "connection_router_interface.h" +#include "rr_graph_storage.h" +#include "route_common.h" +#include "router_lookahead.h" +#include "route_tree.h" +#include "rr_rc_data.h" +#include "router_stats.h" +#include "spatial_route_tree_lookup.h" + +// This class encapsulates the timing driven connection router. This class +// routes from some initial set of sources (via the input rt tree) to a +// particular sink. +// +// When the ConnectionRouter is used, it mutates the provided +// rr_node_route_inf. The routed path can be found by tracing from the sink +// node (which is returned) through the rr_node_route_inf. See +// update_traceback as an example of this tracing. +template +class ConnectionRouter : public ConnectionRouterInterface { + public: + ConnectionRouter( + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat) + : grid_(grid) + , router_lookahead_(router_lookahead) + , rr_nodes_(rr_nodes.view()) + , rr_graph_(rr_graph) + , rr_rc_data_(rr_rc_data.data(), rr_rc_data.size()) + , rr_switch_inf_(rr_switch_inf.data(), rr_switch_inf.size()) + , net_terminal_groups(g_vpr_ctx.routing().net_terminal_groups) + , net_terminal_group_num(g_vpr_ctx.routing().net_terminal_group_num) + , rr_node_route_inf_(rr_node_route_inf) + , is_flat_(is_flat) + , router_stats_(nullptr) + , router_debug_(false) + , path_search_cumulative_time(0) { + heap_.init_heap(grid); + only_opin_inter_layer = (grid.get_num_layers() > 1) && inter_layer_connections_limited_to_opin(*rr_graph); + } + + virtual ~ConnectionRouter() {} + + // Clear's the modified list. Should be called after reset_path_costs + // have been called. + virtual void clear_modified_rr_node_info() = 0; + + // Reset modified data in rr_node_route_inf based on modified_rr_node_inf. + virtual void reset_path_costs() = 0; + + /** Finds a path from the route tree rooted at rt_root to sink_node. + * This is used when you want to allow previous routing of the same net to + * serve as valid start locations for the current connection. + * + * Returns a tuple of: + * bool: path exists? (hard failure, rr graph disconnected) + * bool: should retry with full bounding box? (only used in parallel routing) + * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ + std::tuple timing_driven_route_connection_from_route_tree( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) final; + + /** Finds a path from the route tree rooted at rt_root to sink_node for a + * high fanout net. + * + * Unlike timing_driven_route_connection_from_route_tree(), only part of + * the route tree which is spatially close to the sink is added to the heap. + * + * Returns a tuple of: + * bool: path exists? (hard failure, rr graph disconnected) + * bool: should retry with full bounding box? (only used in parallel routing) + * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ + std::tuple timing_driven_route_connection_from_route_tree_high_fanout( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bounding_box, + const SpatialRouteTreeLookup& spatial_rt_lookup, + RouterStats& router_stats, + const ConnectionParameters& conn_params) final; + + // Finds a path from the route tree rooted at rt_root to all sinks + // available. + // + // Each element of the returned vector is a reachable sink. + // + // If cost_params.astar_fac is set to 0, this effectively becomes + // Dijkstra's algorithm with a modified exit condition (runs until heap is + // empty). When using cost_params.astar_fac = 0, for efficiency the + // RouterLookahead used should be the NoOpLookahead. + // + // Note: This routine is currently used only to generate information that + // may be helpful in debugging an architecture. + virtual vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( + const RouteTreeNode& rt_root, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) = 0; + + void set_router_debug(bool router_debug) final { + router_debug_ = router_debug; + } + + // Empty the route tree set used for RCV node detection + // Will return if RCV is disabled + // Called after each net is finished routing to flush the set + void empty_rcv_route_tree_set() final; + + // Enable or disable RCV in connection router + // Enabling this will utilize extra path structures, as well as the RCV cost function + // + // Ensure route budgets have been calculated before enabling this + virtual void set_rcv_enabled(bool enable) = 0; + + protected: + /** Common logic from timing_driven_route_connection_from_route_tree and + * timing_driven_route_connection_from_route_tree_high_fanout for running + * the connection router. + * @param[in] rt_root RouteTreeNode describing the current routing state + * @param[in] sink_node Sink node ID to route to + * @param[in] cost_params + * @param[in] bounding_box Keep search confined to this bounding box + * @return bool Signal to retry this connection with a full-device bounding box */ + bool timing_driven_route_connection_common_setup( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box); + + // Finds a path to sink_node, starting from the elements currently in the + // heap. + // + // If the path is not found, which means that the path_cost of sink_node in + // RR node route info has never been updated, `rr_node_route_inf_[sink_node] + // .path_cost` will be the initial value (i.e., float infinity). This case + // can be detected by `std::isinf(rr_node_route_inf_[sink_node].path_cost)`. + // + // This is the core maze routing routine. + // + // Note: For understanding the connection router, start here. + void timing_driven_route_connection_from_heap( + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box); + + // Find the shortest path from current heap to the sink node in the RR graph + virtual void timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) = 0; + + // Find paths from current heap to all nodes in the RR graph + virtual vtr::vector timing_driven_find_all_shortest_paths_from_heap( + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) = 0; + + //Unconditionally adds rt_node to the heap + // + //Note that if you want to respect rt_node->re_expand that is the caller's + //responsibility. + virtual void add_route_tree_node_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb) = 0; + + // Calculates the cost of reaching to_node + void evaluate_timing_driven_node_costs( + RTExploredNode* to, + const t_conn_cost_params& cost_params, + RRNodeId from_node, + RRNodeId target_node); + + // Evaluate node costs using the RCV algorith + float compute_node_cost_using_rcv(const t_conn_cost_params cost_params, + RRNodeId to_node, + RRNodeId target_node, + float backwards_delay, + float backwards_cong, + float R_upstream); + + //Adds the route tree rooted at rt_node to the heap, preparing it to be + //used as branch-points for further routing. + void add_route_tree_to_heap(const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb); + + t_bb add_high_fanout_route_tree_to_heap( + const RouteTreeNode& rt_root, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const SpatialRouteTreeLookup& spatial_route_tree_lookup, + const t_bb& net_bounding_box); + + const DeviceGrid& grid_; + const RouterLookahead& router_lookahead_; + const t_rr_graph_view rr_nodes_; + const RRGraphView* rr_graph_; + vtr::array_view rr_rc_data_; + vtr::array_view rr_switch_inf_; + const vtr::vector>>& net_terminal_groups; + const vtr::vector>& net_terminal_group_num; + vtr::vector& rr_node_route_inf_; + bool is_flat_; + std::vector modified_rr_node_inf_; + RouterStats* router_stats_; + const ConnectionParameters* conn_params_; + HeapImplementation heap_; + bool router_debug_; + + bool only_opin_inter_layer; + + // Cumulative time spent in the path search part of the connection router. + std::chrono::microseconds path_search_cumulative_time; + + // The path manager for RCV, keeps track of the route tree as a set, also + // manages the allocation of `rcv_path_data`. + PathManager rcv_path_manager; + vtr::vector rcv_path_data; +}; + +#include "connection_router.tpp" + +#endif /* _CONNECTION_ROUTER_H */ diff --git a/vpr/src/route/connection_router.tpp b/vpr/src/route/connection_router.tpp new file mode 100644 index 00000000000..2356b225728 --- /dev/null +++ b/vpr/src/route/connection_router.tpp @@ -0,0 +1,600 @@ +#pragma once + +#include "connection_router.h" + +#include +#include "rr_graph.h" +#include "rr_graph_fwd.h" + +/** Used for the flat router. The node isn't relevant to the target if + * it is an intra-block node outside of our target block */ +inline bool relevant_node_to_target(const RRGraphView* rr_graph, + RRNodeId node_to_add, + RRNodeId target_node); + +inline void update_router_stats(RouterStats* router_stats, + bool is_push, + RRNodeId rr_node_id, + const RRGraphView* rr_graph); + +/** return tuple */ +template +std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) { + router_stats_ = &router_stats; + conn_params_ = &conn_params; + + bool retry = false; + retry = timing_driven_route_connection_common_setup(rt_root, sink_node, cost_params, bounding_box); + + if (!std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + // Only the `index`, `prev_edge`, and `rcv_path_backward_delay` fields of `out` + // are used after this function returns. + RTExploredNode out; + out.index = sink_node; + out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; + if (rcv_path_manager.is_enabled()) { + out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; + rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); + rcv_path_manager.empty_heap(); + } + heap_.empty_heap(); + return std::make_tuple(true, /*retry=*/false, out); + } else { + reset_path_costs(); + clear_modified_rr_node_info(); + heap_.empty_heap(); + rcv_path_manager.empty_heap(); + return std::make_tuple(false, retry, RTExploredNode()); + } +} + +// Finds a path from the route tree rooted at rt_root to sink_node for a high fanout net. +// +// Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree +// which is spatially close to the sink is added to the heap. +// Returns a tuple of */ +template +std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree_high_fanout( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bounding_box, + const SpatialRouteTreeLookup& spatial_rt_lookup, + RouterStats& router_stats, + const ConnectionParameters& conn_params) { + router_stats_ = &router_stats; + conn_params_ = &conn_params; + + // re-explore route tree from root to add any new nodes (buildheap afterwards) + // route tree needs to be repushed onto the heap since each node's cost is target specific + t_bb high_fanout_bb = add_high_fanout_route_tree_to_heap(rt_root, sink_node, cost_params, spatial_rt_lookup, net_bounding_box); + heap_.build_heap(); + + RRNodeId source_node = rt_root.inode; + + if (heap_.is_empty_heap()) { + VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + return std::make_tuple(false, false, RTExploredNode()); + } + + VTR_LOGV_DEBUG(router_debug_, " Routing to %d as high fanout net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, + high_fanout_bb.layer_min, high_fanout_bb.xmin, high_fanout_bb.ymin, + high_fanout_bb.layer_max, high_fanout_bb.xmax, high_fanout_bb.ymax); + + bool retry_with_full_bb = false; + timing_driven_route_connection_from_heap(sink_node, cost_params, high_fanout_bb); + + if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + //Found no path, that may be due to an unlucky choice of existing route tree sub-set, + //try again with the full route tree to be sure this is not an artifact of high-fanout routing + VTR_LOG_WARN("No routing path found in high-fanout mode for net %zu connection (to sink_rr %d), retrying with full route tree\n", size_t(conn_params.net_id_), sink_node); + + //Reset any previously recorded node costs so timing_driven_route_connection() + //starts over from scratch. + reset_path_costs(); + clear_modified_rr_node_info(); + + retry_with_full_bb = timing_driven_route_connection_common_setup(rt_root, sink_node, cost_params, net_bounding_box); + } + + if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + + heap_.empty_heap(); + rcv_path_manager.empty_heap(); + return std::make_tuple(false, retry_with_full_bb, RTExploredNode()); + } + + RTExploredNode out; + out.index = sink_node; + out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; + if (rcv_path_manager.is_enabled()) { + out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; + rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); + rcv_path_manager.empty_heap(); + } + heap_.empty_heap(); + + return std::make_tuple(true, retry_with_full_bb, out); +} + +/** Return whether to retry with full bb */ +template +bool ConnectionRouter::timing_driven_route_connection_common_setup( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { + //Re-add route nodes from the existing route tree to the heap. + //They need to be repushed onto the heap since each node's cost is target specific. + + add_route_tree_to_heap(rt_root, sink_node, cost_params, bounding_box); + heap_.build_heap(); // via sifting down everything + + RRNodeId source_node = rt_root.inode; + + if (heap_.is_empty_heap()) { + VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + return false; + } + + VTR_LOGV_DEBUG(router_debug_, " Routing to %d as normal net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, + bounding_box.layer_min, bounding_box.xmin, bounding_box.ymin, + bounding_box.layer_max, bounding_box.xmax, bounding_box.ymax); + + timing_driven_route_connection_from_heap(sink_node, cost_params, bounding_box); + + if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + // No path found within the current bounding box. + // + // If the bounding box is already max size, just fail + if (bounding_box.xmin == 0 + && bounding_box.ymin == 0 + && bounding_box.xmax == (int)(grid_.width() - 1) + && bounding_box.ymax == (int)(grid_.height() - 1) + && bounding_box.layer_min == 0 + && bounding_box.layer_max == (int)(grid_.get_num_layers() - 1)) { + VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + return false; + } + + // Otherwise, leave unrouted and bubble up a signal to retry this net with a full-device bounding box + VTR_LOG_WARN("No routing path for connection to sink_rr %d, leaving unrouted to retry later\n", sink_node); + return true; + } + + return false; +} + +// Finds a path to sink_node, starting from the elements currently in the heap. +// This is the core maze routing routine. +template +void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { + VTR_ASSERT_SAFE(heap_.is_valid()); + + if (heap_.is_empty_heap()) { //No source + VTR_LOGV_DEBUG(router_debug_, " Initial heap empty (no source)\n"); + } + + // Get bounding box for sink node used in timing_driven_expand_neighbour + VTR_ASSERT_SAFE(sink_node != RRNodeId::INVALID()); + + t_bb target_bb; + if (rr_graph_->node_type(sink_node) == SINK) { // We need to get a bounding box for the sink's entire tile + vtr::Rect tile_bb = grid_.get_tile_bb({rr_graph_->node_xlow(sink_node), + rr_graph_->node_ylow(sink_node), + rr_graph_->node_layer(sink_node)}); + + target_bb.xmin = tile_bb.xmin(); + target_bb.ymin = tile_bb.ymin(); + target_bb.xmax = tile_bb.xmax(); + target_bb.ymax = tile_bb.ymax(); + } else { + target_bb.xmin = rr_graph_->node_xlow(sink_node); + target_bb.ymin = rr_graph_->node_ylow(sink_node); + target_bb.xmax = rr_graph_->node_xhigh(sink_node); + target_bb.ymax = rr_graph_->node_yhigh(sink_node); + } + + target_bb.layer_min = rr_graph_->node_layer(RRNodeId(sink_node)); + target_bb.layer_max = rr_graph_->node_layer(RRNodeId(sink_node)); + + // Start measuring path search time + std::chrono::steady_clock::time_point begin_time = std::chrono::steady_clock::now(); + + timing_driven_find_single_shortest_path_from_heap(sink_node, cost_params, bounding_box, target_bb); + + // Stop measuring path search time + std::chrono::steady_clock::time_point end_time = std::chrono::steady_clock::now(); + path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); +} + +#ifdef VTR_ASSERT_SAFE_ENABLED + +//Returns true if both nodes are part of the same non-configurable edge set +inline bool same_non_config_node_set(RRNodeId from_node, RRNodeId to_node) { + auto& device_ctx = g_vpr_ctx.device(); + + auto from_itr = device_ctx.rr_node_to_non_config_node_set.find(from_node); + auto to_itr = device_ctx.rr_node_to_non_config_node_set.find(to_node); + + if (from_itr == device_ctx.rr_node_to_non_config_node_set.end() + || to_itr == device_ctx.rr_node_to_non_config_node_set.end()) { + return false; //Not part of a non-config node set + } + + return from_itr->second == to_itr->second; //Check for same non-config set IDs +} + +#endif + +template +float ConnectionRouter::compute_node_cost_using_rcv(const t_conn_cost_params cost_params, + RRNodeId to_node, + RRNodeId target_node, + float backwards_delay, + float backwards_cong, + float R_upstream) { + float expected_delay; + float expected_cong; + + const t_conn_delay_budget* delay_budget = cost_params.delay_budget; + // TODO: This function is not tested for is_flat == true + VTR_ASSERT(is_flat_ != true); + std::tie(expected_delay, expected_cong) = router_lookahead_.get_expected_delay_and_cong(to_node, target_node, cost_params, R_upstream); + + float expected_total_delay_cost; + float expected_total_cong_cost; + + float expected_total_cong = expected_cong + backwards_cong; + float expected_total_delay = expected_delay + backwards_delay; + + //If budgets specified calculate cost as described by RCV paper: + // R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While + // Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of + // Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008. + + // Normalization constant defined in RCV paper cited above + constexpr float NORMALIZATION_CONSTANT = 100e-12; + + expected_total_delay_cost = expected_total_delay; + expected_total_delay_cost += (delay_budget->short_path_criticality + cost_params.criticality) * std::max(0.f, delay_budget->target_delay - expected_total_delay); + // expected_total_delay_cost += std::pow(std::max(0.f, expected_total_delay - delay_budget->max_delay), 2) / NORMALIZATION_CONSTANT; + expected_total_delay_cost += std::pow(std::max(0.f, delay_budget->min_delay - expected_total_delay), 2) / NORMALIZATION_CONSTANT; + expected_total_cong_cost = expected_total_cong; + + float total_cost = expected_total_delay_cost + expected_total_cong_cost; + + return total_cost; +} + +// Empty the route tree set node, use this after each net is routed +template +void ConnectionRouter::empty_rcv_route_tree_set() { + rcv_path_manager.empty_route_tree_nodes(); +} + +//Calculates the cost of reaching to_node (i.e., to->index) +template +void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, + const t_conn_cost_params& cost_params, + RRNodeId from_node, + RRNodeId target_node) { + /* new_costs.backward_cost: is the "known" part of the cost to this node -- the + * congestion cost of all the routing resources back to the existing route + * plus the known delay of the total path back to the source. + * + * new_costs.total_cost: is this "known" backward cost + an expected cost to get to the target. + * + * new_costs.R_upstream: is the upstream resistance at the end of this node + */ + + //Info for the switch connecting from_node to_node (i.e., to->index) + int iswitch = rr_nodes_.edge_switch(to->prev_edge); + bool switch_buffered = rr_switch_inf_[iswitch].buffered(); + bool reached_configurably = rr_switch_inf_[iswitch].configurable(); + float switch_R = rr_switch_inf_[iswitch].R; + float switch_Tdel = rr_switch_inf_[iswitch].Tdel; + float switch_Cinternal = rr_switch_inf_[iswitch].Cinternal; + + //To node info + auto rc_index = rr_graph_->node_rc_index(to->index); + float node_C = rr_rc_data_[rc_index].C; + float node_R = rr_rc_data_[rc_index].R; + + //From node info + float from_node_R = rr_rc_data_[rr_graph_->node_rc_index(from_node)].R; + + //Update R_upstream + if (switch_buffered) { + to->R_upstream = 0.; //No upstream resistance + } else { + //R_Upstream already initialized + } + + to->R_upstream += switch_R; //Switch resistance + to->R_upstream += node_R; //Node resistance + + //Calculate delay + float Rdel = to->R_upstream - 0.5 * node_R; //Only consider half node's resistance for delay + float Tdel = switch_Tdel + Rdel * node_C; + + //Depending on the switch used, the Tdel of the upstream node (from_node) may change due to + //increased loading from the switch's internal capacitance. + // + //Even though this delay physically affects from_node, we make the adjustment (now) on the to_node, + //since only once we've reached to to_node do we know the connection used (and the switch enabled). + // + //To adjust for the time delay, we compute the product of the Rdel associated with from_node and + //the internal capacitance of the switch. + // + //First, we will calculate Rdel_adjust (just like in the computation for Rdel, we consider only + //half of from_node's resistance). + float Rdel_adjust = to->R_upstream - 0.5 * from_node_R; + + //Second, we adjust the Tdel to account for the delay caused by the internal capacitance. + Tdel += Rdel_adjust * switch_Cinternal; + + float cong_cost = 0.; + if (reached_configurably) { + cong_cost = get_rr_cong_cost(to->index, cost_params.pres_fac); + } else { + //Reached by a non-configurable edge. + //Therefore the from_node and to_node are part of the same non-configurable node set. +#ifdef VTR_ASSERT_SAFE_ENABLED + VTR_ASSERT_SAFE_MSG(same_non_config_node_set(from_node, to->index), + "Non-configurably connected edges should be part of the same node set"); +#endif + + //The congestion cost of all nodes in the set has already been accounted for (when + //the current path first expanded a node in the set). Therefore do *not* re-add the congestion + //cost. + cong_cost = 0.; + } + if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == IPIN) { + auto find_res = conn_params_->connection_choking_spots_.find(to->index); + if (find_res != conn_params_->connection_choking_spots_.end()) { + cong_cost = cong_cost / pow(2, (float)find_res->second); + } + } + + //Update the backward cost (upstream already included) + to->backward_path_cost += (1. - cost_params.criticality) * cong_cost; //Congestion cost + to->backward_path_cost += cost_params.criticality * Tdel; //Delay cost + + if (cost_params.bend_cost != 0.) { + t_rr_type from_type = rr_graph_->node_type(from_node); + t_rr_type to_type = rr_graph_->node_type(to->index); + if ((from_type == CHANX && to_type == CHANY) || (from_type == CHANY && to_type == CHANX)) { + to->backward_path_cost += cost_params.bend_cost; //Bend cost + } + } + + float total_cost = 0.; + + if (rcv_path_manager.is_enabled() && to->path_data != nullptr) { + to->path_data->backward_delay += cost_params.criticality * Tdel; + to->path_data->backward_cong += (1. - cost_params.criticality) * get_rr_cong_cost(to->index, cost_params.pres_fac); + + total_cost = compute_node_cost_using_rcv(cost_params, to->index, target_node, to->path_data->backward_delay, to->path_data->backward_cong, to->R_upstream); + } else { + const auto& device_ctx = g_vpr_ctx.device(); + //Update total cost + float expected_cost = router_lookahead_.get_expected_cost(to->index, target_node, cost_params, to->R_upstream); + VTR_LOGV_DEBUG(router_debug_ && !std::isfinite(expected_cost), + " Lookahead from %s (%s) to %s (%s) is non-finite, expected_cost = %f, to->R_upstream = %f\n", + rr_node_arch_name(to->index, is_flat_).c_str(), + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to->index, is_flat_).c_str(), + rr_node_arch_name(target_node, is_flat_).c_str(), + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, target_node, is_flat_).c_str(), + expected_cost, to->R_upstream); + total_cost += to->backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); + } + to->total_cost = total_cost; +} + +//Adds the route tree rooted at rt_node to the heap, preparing it to be +//used as branch-points for further routing. +template +void ConnectionRouter::add_route_tree_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb) { + /* Puts the entire partial routing below and including rt_node onto the heap * + * (except for those parts marked as not to be expanded) by calling itself * + * recursively. */ + + /* Pre-order depth-first traversal */ + // IPINs and SINKS are not re_expanded + if (rt_node.re_expand) { + add_route_tree_node_to_heap(rt_node, target_node, cost_params, net_bb); + } + + for (const RouteTreeNode& child_node : rt_node.child_nodes()) { + if (is_flat_) { + if (relevant_node_to_target(rr_graph_, child_node.inode, target_node)) { + add_route_tree_to_heap(child_node, target_node, cost_params, net_bb); + } + } else { + add_route_tree_to_heap(child_node, target_node, cost_params, net_bb); + } + } +} + +/* Expand bb by inode's extents and clip against net_bb */ +inline void expand_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb, RRNodeId inode, const RRGraphView* rr_graph) { + bb.xmin = std::max(net_bb.xmin, std::min(bb.xmin, rr_graph->node_xlow(inode))); + bb.ymin = std::max(net_bb.ymin, std::min(bb.ymin, rr_graph->node_ylow(inode))); + bb.xmax = std::min(net_bb.xmax, std::max(bb.xmax, rr_graph->node_xhigh(inode))); + bb.ymax = std::min(net_bb.ymax, std::max(bb.ymax, rr_graph->node_yhigh(inode))); + bb.layer_min = std::min(bb.layer_min, rr_graph->node_layer(inode)); + bb.layer_max = std::max(bb.layer_max, rr_graph->node_layer(inode)); +} + +/* Expand bb by HIGH_FANOUT_BB_FAC and clip against net_bb */ +inline void adjust_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb) { + constexpr int HIGH_FANOUT_BB_FAC = 3; + + bb.xmin = std::max(net_bb.xmin, bb.xmin - HIGH_FANOUT_BB_FAC); + bb.ymin = std::max(net_bb.ymin, bb.ymin - HIGH_FANOUT_BB_FAC); + bb.xmax = std::min(net_bb.xmax, bb.xmax + HIGH_FANOUT_BB_FAC); + bb.ymax = std::min(net_bb.ymax, bb.ymax + HIGH_FANOUT_BB_FAC); + bb.layer_min = std::min(net_bb.layer_min, bb.layer_min); + bb.layer_max = std::max(net_bb.layer_max, bb.layer_max); +} + +template +t_bb ConnectionRouter::add_high_fanout_route_tree_to_heap( + const RouteTreeNode& rt_root, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const SpatialRouteTreeLookup& spatial_rt_lookup, + const t_bb& net_bounding_box) { + //For high fanout nets we only add those route tree nodes which are spatially close + //to the sink. + // + //Based on: + // J. Swartz, V. Betz, J. Rose, "A Fast Routability-Driven Router for FPGAs", FPGA, 1998 + // + //We rely on a grid-based spatial look-up which is maintained for high fanout nets by + //update_route_tree(), which allows us to add spatially close route tree nodes without traversing + //the entire route tree (which is likely large for a high fanout net). + + //Determine which bin the target node is located in + + int target_bin_x = grid_to_bin_x(rr_graph_->node_xlow(target_node), spatial_rt_lookup); + int target_bin_y = grid_to_bin_y(rr_graph_->node_ylow(target_node), spatial_rt_lookup); + + auto target_layer = rr_graph_->node_layer(target_node); + + int chan_nodes_added = 0; + + t_bb highfanout_bb; + highfanout_bb.xmin = rr_graph_->node_xlow(target_node); + highfanout_bb.xmax = rr_graph_->node_xhigh(target_node); + highfanout_bb.ymin = rr_graph_->node_ylow(target_node); + highfanout_bb.ymax = rr_graph_->node_yhigh(target_node); + highfanout_bb.layer_min = target_layer; + highfanout_bb.layer_max = target_layer; + + //Add existing routing starting from the target bin. + //If the target's bin has insufficient existing routing add from the surrounding bins + constexpr int SINGLE_BIN_MIN_NODES = 2; + bool done = false; + bool found_node_on_same_layer = false; + for (int dx : {0, -1, +1}) { + size_t bin_x = target_bin_x + dx; + + if (bin_x > spatial_rt_lookup.dim_size(0) - 1) continue; //Out of range + + for (int dy : {0, -1, +1}) { + size_t bin_y = target_bin_y + dy; + + if (bin_y > spatial_rt_lookup.dim_size(1) - 1) continue; //Out of range + + for (const RouteTreeNode& rt_node : spatial_rt_lookup[bin_x][bin_y]) { + if (!rt_node.re_expand) // Some nodes (like IPINs) shouldn't be re-expanded + continue; + RRNodeId rr_node_to_add = rt_node.inode; + + /* Flat router: don't go into clusters other than the target one */ + if (is_flat_) { + if (!relevant_node_to_target(rr_graph_, rr_node_to_add, target_node)) + continue; + } + + /* In case of the parallel router, we may be dealing with a virtual net + * so prune the nodes from the HF lookup against the bounding box just in case */ + if (!inside_bb(rr_node_to_add, net_bounding_box)) + continue; + + auto rt_node_layer_num = rr_graph_->node_layer(rr_node_to_add); + if (rt_node_layer_num == target_layer) + found_node_on_same_layer = true; + + // Put the node onto the heap + add_route_tree_node_to_heap(rt_node, target_node, cost_params, net_bounding_box); + + // Expand HF BB to include the node (clip by original BB) + expand_highfanout_bounding_box(highfanout_bb, net_bounding_box, rr_node_to_add, rr_graph_); + + if (rr_graph_->node_type(rr_node_to_add) == CHANY || rr_graph_->node_type(rr_node_to_add) == CHANX) { + chan_nodes_added++; + } + } + + if (dx == 0 && dy == 0 && chan_nodes_added > SINGLE_BIN_MIN_NODES && found_node_on_same_layer) { + //Target bin contained at least minimum amount of routing + // + //We require at least SINGLE_BIN_MIN_NODES to be added. + //This helps ensure we don't end up with, for example, a single + //routing wire running in the wrong direction which may not be + //able to reach the target within the bounding box. + done = true; + break; + } + } + if (done) break; + } + /* If we didn't find enough nodes to branch off near the target + * or they are on the wrong grid layer, just add the full route tree */ + if (chan_nodes_added <= SINGLE_BIN_MIN_NODES || !found_node_on_same_layer) { + add_route_tree_to_heap(rt_root, target_node, cost_params, net_bounding_box); + return net_bounding_box; + } else { + //We found nearby routing, replace original bounding box to be localized around that routing + adjust_highfanout_bounding_box(highfanout_bb, net_bounding_box); + return highfanout_bb; + } +} + +inline bool relevant_node_to_target(const RRGraphView* rr_graph, + RRNodeId node_to_add, + RRNodeId target_node) { + VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == t_rr_type::SINK); + auto node_to_add_type = rr_graph->node_type(node_to_add); + return node_to_add_type != t_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); +} + +inline void update_router_stats(RouterStats* router_stats, + bool is_push, + RRNodeId rr_node_id, + const RRGraphView* rr_graph) { + if (is_push) { + router_stats->heap_pushes++; + } else { + router_stats->heap_pops++; + } + + if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { + auto node_type = rr_graph->node_type(rr_node_id); + VTR_ASSERT(node_type != NUM_RR_TYPES); + + if (is_inter_cluster_node(*rr_graph, rr_node_id)) { + if (is_push) { + router_stats->inter_cluster_node_pushes++; + router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; + } else { + router_stats->inter_cluster_node_pops++; + router_stats->inter_cluster_node_type_cnt_pops[node_type]++; + } + } else { + if (is_push) { + router_stats->intra_cluster_node_pushes++; + router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; + } else { + router_stats->intra_cluster_node_pops++; + router_stats->intra_cluster_node_type_cnt_pops[node_type]++; + } + } + } +} diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp index 98df4d341cc..0543a7a76d4 100644 --- a/vpr/src/route/parallel_connection_router.cpp +++ b/vpr/src/route/parallel_connection_router.cpp @@ -5,179 +5,6 @@ #include "rr_graph.h" #include "rr_graph_fwd.h" -/** Used for the flat router. The node isn't relevant to the target if - * it is an intra-block node outside of our target block */ -static bool relevant_node_to_target(const RRGraphView* rr_graph, - RRNodeId node_to_add, - RRNodeId target_node); - -static void update_router_stats(RouterStats* router_stats, - bool is_push, - RRNodeId rr_node_id, - const RRGraphView* rr_graph); - -/** return tuple */ -template -std::tuple ParallelConnectionRouter::timing_driven_route_connection_from_route_tree( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RouterStats& router_stats, - const ConnectionParameters& conn_params) { - router_stats_ = &router_stats; - conn_params_ = &conn_params; - - bool retry = false; - retry = timing_driven_route_connection_common_setup(rt_root, sink_node, cost_params, bounding_box); - - if (!std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - // Only the `index`, `prev_edge`, and `rcv_path_backward_delay` fields of `out` - // are used after this function returns. - RTExploredNode out; - out.index = sink_node; - out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; - if (rcv_path_manager.is_enabled()) { - out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; - rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); - rcv_path_manager.empty_heap(); - } - heap_.empty_heap(); - return std::make_tuple(true, /*retry=*/false, out); - } else { - reset_path_costs(); - clear_modified_rr_node_info(); - heap_.empty_heap(); - rcv_path_manager.empty_heap(); - return std::make_tuple(false, retry, RTExploredNode()); - } -} - -/** Return whether to retry with full bb */ -template -bool ParallelConnectionRouter::timing_driven_route_connection_common_setup( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { - //Re-add route nodes from the existing route tree to the heap. - //They need to be repushed onto the heap since each node's cost is target specific. - - add_route_tree_to_heap(rt_root, sink_node, cost_params, bounding_box); - heap_.build_heap(); // via sifting down everything - - RRNodeId source_node = rt_root.inode; - - if (heap_.is_empty_heap()) { - VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - return false; - } - - VTR_LOGV_DEBUG(router_debug_, " Routing to %d as normal net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, - bounding_box.layer_min, bounding_box.xmin, bounding_box.ymin, - bounding_box.layer_max, bounding_box.xmax, bounding_box.ymax); - - timing_driven_route_connection_from_heap(sink_node, - cost_params, - bounding_box); - - if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - // No path found within the current bounding box. - // - // If the bounding box is already max size, just fail - if (bounding_box.xmin == 0 - && bounding_box.ymin == 0 - && bounding_box.xmax == (int)(grid_.width() - 1) - && bounding_box.ymax == (int)(grid_.height() - 1) - && bounding_box.layer_min == 0 - && bounding_box.layer_max == (int)(grid_.get_num_layers() - 1)) { - VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - return false; - } - - // Otherwise, leave unrouted and bubble up a signal to retry this net with a full-device bounding box - VTR_LOG_WARN("No routing path for connection to sink_rr %d, leaving unrouted to retry later\n", sink_node); - return true; - } - - return false; -} - -// Finds a path from the route tree rooted at rt_root to sink_node for a high fanout net. -// -// Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree -// which is spatially close to the sink is added to the heap. -// Returns a tuple of */ -template -std::tuple ParallelConnectionRouter::timing_driven_route_connection_from_route_tree_high_fanout( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bounding_box, - const SpatialRouteTreeLookup& spatial_rt_lookup, - RouterStats& router_stats, - const ConnectionParameters& conn_params) { - router_stats_ = &router_stats; - conn_params_ = &conn_params; - - // re-explore route tree from root to add any new nodes (buildheap afterwards) - // route tree needs to be repushed onto the heap since each node's cost is target specific - t_bb high_fanout_bb = add_high_fanout_route_tree_to_heap(rt_root, sink_node, cost_params, spatial_rt_lookup, net_bounding_box); - heap_.build_heap(); - - RRNodeId source_node = rt_root.inode; - - if (heap_.is_empty_heap()) { - VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - return std::make_tuple(false, false, RTExploredNode()); - } - - VTR_LOGV_DEBUG(router_debug_, " Routing to %d as high fanout net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, - high_fanout_bb.layer_min, high_fanout_bb.xmin, high_fanout_bb.ymin, - high_fanout_bb.layer_max, high_fanout_bb.xmax, high_fanout_bb.ymax); - - bool retry_with_full_bb = false; - timing_driven_route_connection_from_heap(sink_node, - cost_params, - high_fanout_bb); - - if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - //Found no path, that may be due to an unlucky choice of existing route tree sub-set, - //try again with the full route tree to be sure this is not an artifact of high-fanout routing - VTR_LOG_WARN("No routing path found in high-fanout mode for net %zu connection (to sink_rr %d), retrying with full route tree\n", size_t(conn_params.net_id_), sink_node); - - //Reset any previously recorded node costs so timing_driven_route_connection() - //starts over from scratch. - reset_path_costs(); - clear_modified_rr_node_info(); - - retry_with_full_bb = timing_driven_route_connection_common_setup(rt_root, - sink_node, - cost_params, - net_bounding_box); - } - - if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - - heap_.empty_heap(); - rcv_path_manager.empty_heap(); - return std::make_tuple(false, retry_with_full_bb, RTExploredNode()); - } - - RTExploredNode out; - out.index = sink_node; - out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; - if (rcv_path_manager.is_enabled()) { - out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; - rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); - rcv_path_manager.empty_heap(); - } - heap_.empty_heap(); - - return std::make_tuple(true, retry_with_full_bb, out); -} - static inline bool post_target_prune_node(float new_total_cost, float new_back_cost, float best_back_cost_to_target, @@ -309,92 +136,63 @@ static inline bool should_not_explore_neighbors(RRNodeId inode, return false; } -// Finds a path to sink_node, starting from the elements currently in the heap. -// This is the core maze routing routine. template -void ParallelConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { - VTR_ASSERT_SAFE(heap_.is_valid()); - - if (heap_.is_empty_heap()) { //No source - VTR_LOGV_DEBUG(router_debug_, " Initial heap empty (no source)\n"); - } - - // Get bounding box for sink node used in timing_driven_expand_neighbour - VTR_ASSERT_SAFE(sink_node != RRNodeId::INVALID()); - - t_bb target_bb; - if (rr_graph_->node_type(sink_node) == SINK) { // We need to get a bounding box for the sink's entire tile - vtr::Rect tile_bb = grid_.get_tile_bb({rr_graph_->node_xlow(sink_node), - rr_graph_->node_ylow(sink_node), - rr_graph_->node_layer(sink_node)}); - - target_bb.xmin = tile_bb.xmin(); - target_bb.ymin = tile_bb.ymin(); - target_bb.xmax = tile_bb.xmax(); - target_bb.ymax = tile_bb.ymax(); - } else { - target_bb.xmin = rr_graph_->node_xlow(sink_node); - target_bb.ymin = rr_graph_->node_ylow(sink_node); - target_bb.xmax = rr_graph_->node_xhigh(sink_node); - target_bb.ymax = rr_graph_->node_yhigh(sink_node); - } - - target_bb.layer_min = rr_graph_->node_layer(RRNodeId(sink_node)); - target_bb.layer_max = rr_graph_->node_layer(RRNodeId(sink_node)); - - // Start measuring path search time - std::chrono::steady_clock::time_point begin_time = std::chrono::steady_clock::now(); +void ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) { this->sink_node_ = &sink_node; this->cost_params_ = const_cast(&cost_params); this->bounding_box_ = const_cast(&bounding_box); this->target_bb_ = const_cast(&target_bb); - thread_barrier_.wait(); - this->timing_driven_route_connection_from_heap_thread_func(*this->sink_node_, *this->cost_params_, *this->bounding_box_, *this->target_bb_, 0); - thread_barrier_.wait(); + this->thread_barrier_.wait(); + this->timing_driven_find_single_shortest_path_from_heap_thread_func(*this->sink_node_, + *this->cost_params_, + *this->bounding_box_, + *this->target_bb_, 0); + this->thread_barrier_.wait(); // Collect the number of heap pushes and pops - router_stats_->heap_pushes += heap_.getNumPushes(); - router_stats_->heap_pops += heap_.getNumPops(); + this->router_stats_->heap_pushes += this->heap_.getNumPushes(); + this->router_stats_->heap_pops += this->heap_.getNumPops(); // Reset the heap for the next connection - heap_.reset(); - - // Stop measuring path search time - std::chrono::steady_clock::time_point end_time = std::chrono::steady_clock::now(); - path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); + this->heap_.reset(); } template -void ParallelConnectionRouter::timing_driven_route_connection_from_heap_sub_thread_wrapper(const size_t thread_idx) { - thread_barrier_.init(); +void ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap_sub_thread_wrapper(const size_t thread_idx) { + this->thread_barrier_.init(); while (true) { - thread_barrier_.wait(); - if (is_router_destroying_ == true) { + this->thread_barrier_.wait(); + if (this->is_router_destroying_ == true) { return; } else { - timing_driven_route_connection_from_heap_thread_func(*this->sink_node_, *this->cost_params_, *this->bounding_box_, *this->target_bb_, thread_idx); + timing_driven_find_single_shortest_path_from_heap_thread_func(*this->sink_node_, + *this->cost_params_, + *this->bounding_box_, + *this->target_bb_, + thread_idx); } - thread_barrier_.wait(); + this->thread_barrier_.wait(); } } template -void ParallelConnectionRouter::timing_driven_route_connection_from_heap_thread_func(RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - const t_bb& target_bb, - const size_t thread_idx) { +void ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap_thread_func(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb, + const size_t thread_idx) { HeapNode cheapest; - while (heap_.try_pop(cheapest)) { + while (this->heap_.try_pop(cheapest)) { // inode with the cheapest total cost in current route tree to be expanded on const auto& [new_total_cost, inode] = cheapest; // Should we explore the neighbors of this node? - if (should_not_explore_neighbors(inode, new_total_cost, rr_node_route_inf_[inode].backward_path_cost, sink_node, rr_node_route_inf_, cost_params)) { + if (should_not_explore_neighbors(inode, new_total_cost, this->rr_node_route_inf_[inode].backward_path_cost, sink_node, this->rr_node_route_inf_, cost_params)) { continue; } @@ -402,9 +200,9 @@ void ParallelConnectionRouter::timing_driven_route_connection_from_heap_th RTExploredNode current; current.index = inode; - current.backward_path_cost = rr_node_route_inf_[inode].backward_path_cost; - current.prev_edge = rr_node_route_inf_[inode].prev_edge; - current.R_upstream = rr_node_route_inf_[inode].R_upstream; + current.backward_path_cost = this->rr_node_route_inf_[inode].backward_path_cost; + current.prev_edge = this->rr_node_route_inf_[inode].prev_edge; + current.R_upstream = this->rr_node_route_inf_[inode].R_upstream; releaseLock(inode); @@ -417,7 +215,7 @@ void ParallelConnectionRouter::timing_driven_route_connection_from_heap_th // TODO: This is still doing post-target pruning. May want to investigate // if this is worth doing. // TODO: should try testing without the pruning below and see if anything changes. - if (should_not_explore_neighbors(inode, new_total_cost, current.backward_path_cost, sink_node, rr_node_route_inf_, cost_params)) { + if (should_not_explore_neighbors(inode, new_total_cost, current.backward_path_cost, sink_node, this->rr_node_route_inf_, cost_params)) { continue; } @@ -426,35 +224,6 @@ void ParallelConnectionRouter::timing_driven_route_connection_from_heap_th } } -// Find shortest paths from specified route tree to all nodes in the RR graph -template -vtr::vector ParallelConnectionRouter::timing_driven_find_all_shortest_paths_from_route_tree( - const RouteTreeNode& rt_root, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RouterStats& router_stats, - const ConnectionParameters& conn_params) { - (void)rt_root; - (void)cost_params; - (void)bounding_box; - (void)router_stats; - (void)conn_params; - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_route_tree not yet implemented (nor is the focus of this project). Not expected to be called."); -} - -// Find shortest paths from current heap to all nodes in the RR graph -// -// Since there is no single *target* node this uses Dijkstra's algorithm -// with a modified exit condition (runs until heap is empty). -template -vtr::vector ParallelConnectionRouter::timing_driven_find_all_shortest_paths_from_heap( - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { - (void)cost_params; - (void)bounding_box; - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_heap not yet implemented (nor is the focus of this project). Not expected to be called."); -} - template void ParallelConnectionRouter::timing_driven_expand_neighbours(const RTExploredNode& current, const t_conn_cost_params& cost_params, @@ -465,7 +234,7 @@ void ParallelConnectionRouter::timing_driven_expand_neighbours(const RTExp /* Puts all the rr_nodes adjacent to current on the heap. */ // For each node associated with the current heap element, expand all of it's neighbors - auto edges = rr_nodes_.edge_range(current.index); + auto edges = this->rr_nodes_.edge_range(current.index); // This is a simple prefetch that prefetches: // - RR node data reachable from this node @@ -485,15 +254,15 @@ void ParallelConnectionRouter::timing_driven_expand_neighbours(const RTExp // - gsm_switch_stratixiv_arch_timing.blif // for (RREdgeId from_edge : edges) { - RRNodeId to_node = rr_nodes_.edge_sink_node(from_edge); - rr_nodes_.prefetch_node(to_node); + RRNodeId to_node = this->rr_nodes_.edge_sink_node(from_edge); + this->rr_nodes_.prefetch_node(to_node); - int switch_idx = rr_nodes_.edge_switch(from_edge); - VTR_PREFETCH(&rr_switch_inf_[switch_idx], 0, 0); + int switch_idx = this->rr_nodes_.edge_switch(from_edge); + VTR_PREFETCH(&this->rr_switch_inf_[switch_idx], 0, 0); } for (RREdgeId from_edge : edges) { - RRNodeId to_node = rr_nodes_.edge_sink_node(from_edge); + RRNodeId to_node = this->rr_nodes_.edge_sink_node(from_edge); timing_driven_expand_neighbour(current, from_edge, to_node, @@ -542,15 +311,15 @@ void ParallelConnectionRouter::timing_driven_expand_neighbour(const RTExpl * more promising routes, but makes route-through (via CLBs) impossible. * * Change this if you want to investigate route-throughs. */ if (target_node != RRNodeId::INVALID()) { - t_rr_type to_type = rr_graph_->node_type(to_node); + t_rr_type to_type = this->rr_graph_->node_type(to_node); if (to_type == IPIN) { // Check if this IPIN leads to the target block // IPIN's of the target block should be contained within it's bounding box - int to_xlow = rr_graph_->node_xlow(to_node); - int to_ylow = rr_graph_->node_ylow(to_node); - int to_layer = rr_graph_->node_layer(to_node); - int to_xhigh = rr_graph_->node_xhigh(to_node); - int to_yhigh = rr_graph_->node_yhigh(to_node); + int to_xlow = this->rr_graph_->node_xlow(to_node); + int to_ylow = this->rr_graph_->node_ylow(to_node); + int to_layer = this->rr_graph_->node_layer(to_node); + int to_xhigh = this->rr_graph_->node_xhigh(to_node); + int to_yhigh = this->rr_graph_->node_yhigh(to_node); if (to_xlow < target_bb.xmin || to_ylow < target_bb.ymin || to_xhigh > target_bb.xmax @@ -600,21 +369,18 @@ void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost next.total_cost = std::numeric_limits::infinity(); // Not used directly next.backward_path_cost = current.backward_path_cost; - evaluate_timing_driven_node_costs(&next, - cost_params, - from_node, - target_node); + this->evaluate_timing_driven_node_costs(&next, cost_params, from_node, target_node); float new_total_cost = next.total_cost; float new_back_cost = next.backward_path_cost; - if (prune_node(to_node, new_total_cost, new_back_cost, from_edge, target_node, rr_node_route_inf_, cost_params)) { + if (prune_node(to_node, new_total_cost, new_back_cost, from_edge, target_node, this->rr_node_route_inf_, cost_params)) { return; } obtainSpinLock(to_node); - if (prune_node(to_node, new_total_cost, new_back_cost, from_edge, target_node, rr_node_route_inf_, cost_params)) { + if (prune_node(to_node, new_total_cost, new_back_cost, from_edge, target_node, this->rr_node_route_inf_, cost_params)) { releaseLock(to_node); return; } @@ -639,183 +405,6 @@ void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost // rr_graph_); } -#ifdef VTR_ASSERT_SAFE_ENABLED - -//Returns true if both nodes are part of the same non-configurable edge set -static bool same_non_config_node_set(RRNodeId from_node, RRNodeId to_node) { - auto& device_ctx = g_vpr_ctx.device(); - - auto from_itr = device_ctx.rr_node_to_non_config_node_set.find(from_node); - auto to_itr = device_ctx.rr_node_to_non_config_node_set.find(to_node); - - if (from_itr == device_ctx.rr_node_to_non_config_node_set.end() - || to_itr == device_ctx.rr_node_to_non_config_node_set.end()) { - return false; //Not part of a non-config node set - } - - return from_itr->second == to_itr->second; //Check for same non-config set IDs -} - -#endif - -// Empty the route tree set node, use this after each net is routed -template -void ParallelConnectionRouter::empty_rcv_route_tree_set() { -} - -// Enable or disable RCV -template -void ParallelConnectionRouter::set_rcv_enabled(bool enable) { - (void)enable; - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "RCV for parallel connection router not yet implemented. Not expected to be called."); -} - -//Calculates the cost of reaching to_node (i.e., to->index) -template -void ParallelConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, - const t_conn_cost_params& cost_params, - RRNodeId from_node, - RRNodeId target_node) { - /* new_costs.backward_cost: is the "known" part of the cost to this node -- the - * congestion cost of all the routing resources back to the existing route - * plus the known delay of the total path back to the source. - * - * new_costs.total_cost: is this "known" backward cost + an expected cost to get to the target. - * - * new_costs.R_upstream: is the upstream resistance at the end of this node - */ - - //Info for the switch connecting from_node to_node (i.e., to->index) - int iswitch = rr_nodes_.edge_switch(to->prev_edge); - bool switch_buffered = rr_switch_inf_[iswitch].buffered(); - bool reached_configurably = rr_switch_inf_[iswitch].configurable(); - float switch_R = rr_switch_inf_[iswitch].R; - float switch_Tdel = rr_switch_inf_[iswitch].Tdel; - float switch_Cinternal = rr_switch_inf_[iswitch].Cinternal; - - //To node info - auto rc_index = rr_graph_->node_rc_index(to->index); - float node_C = rr_rc_data_[rc_index].C; - float node_R = rr_rc_data_[rc_index].R; - - //From node info - float from_node_R = rr_rc_data_[rr_graph_->node_rc_index(from_node)].R; - - //Update R_upstream - if (switch_buffered) { - to->R_upstream = 0.; //No upstream resistance - } else { - //R_Upstream already initialized - } - - to->R_upstream += switch_R; //Switch resistance - to->R_upstream += node_R; //Node resistance - - //Calculate delay - float Rdel = to->R_upstream - 0.5 * node_R; //Only consider half node's resistance for delay - float Tdel = switch_Tdel + Rdel * node_C; - - //Depending on the switch used, the Tdel of the upstream node (from_node) may change due to - //increased loading from the switch's internal capacitance. - // - //Even though this delay physically affects from_node, we make the adjustment (now) on the to_node, - //since only once we've reached to to_node do we know the connection used (and the switch enabled). - // - //To adjust for the time delay, we compute the product of the Rdel associated with from_node and - //the internal capacitance of the switch. - // - //First, we will calculate Rdel_adjust (just like in the computation for Rdel, we consider only - //half of from_node's resistance). - float Rdel_adjust = to->R_upstream - 0.5 * from_node_R; - - //Second, we adjust the Tdel to account for the delay caused by the internal capacitance. - Tdel += Rdel_adjust * switch_Cinternal; - - float cong_cost = 0.; - if (reached_configurably) { - cong_cost = get_rr_cong_cost(to->index, cost_params.pres_fac); - } else { - //Reached by a non-configurable edge. - //Therefore the from_node and to_node are part of the same non-configurable node set. -#ifdef VTR_ASSERT_SAFE_ENABLED - VTR_ASSERT_SAFE_MSG(same_non_config_node_set(from_node, to->index), - "Non-configurably connected edges should be part of the same node set"); -#endif - - //The congestion cost of all nodes in the set has already been accounted for (when - //the current path first expanded a node in the set). Therefore do *not* re-add the congestion - //cost. - cong_cost = 0.; - } - if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == IPIN) { - auto find_res = conn_params_->connection_choking_spots_.find(to->index); - if (find_res != conn_params_->connection_choking_spots_.end()) { - cong_cost = cong_cost / pow(2, (float)find_res->second); - } - } - - //Update the backward cost (upstream already included) - to->backward_path_cost += (1. - cost_params.criticality) * cong_cost; //Congestion cost - to->backward_path_cost += cost_params.criticality * Tdel; //Delay cost - - if (cost_params.bend_cost != 0.) { - t_rr_type from_type = rr_graph_->node_type(from_node); - t_rr_type to_type = rr_graph_->node_type(to->index); - if ((from_type == CHANX && to_type == CHANY) || (from_type == CHANY && to_type == CHANX)) { - to->backward_path_cost += cost_params.bend_cost; //Bend cost - } - } - - float total_cost = 0.; - - // const auto& device_ctx = g_vpr_ctx.device(); - //Update total cost - float expected_cost = router_lookahead_.get_expected_cost(to->index, target_node, cost_params, to->R_upstream); - total_cost += to->backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); - - to->total_cost = total_cost; -} - -//Adds the route tree rooted at rt_node to the heap, preparing it to be -//used as branch-points for further routing. -template -void ParallelConnectionRouter::add_route_tree_to_heap( - const RouteTreeNode& rt_node, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bb) { - /* Puts the entire partial routing below and including rt_node onto the heap * - * (except for those parts marked as not to be expanded) by calling itself * - * recursively. */ - - /* Pre-order depth-first traversal */ - // IPINs and SINKS are not re_expanded - if (rt_node.re_expand) { - add_route_tree_node_to_heap(rt_node, - target_node, - cost_params, - net_bb); - } - - for (const RouteTreeNode& child_node : rt_node.child_nodes()) { - if (is_flat_) { - if (relevant_node_to_target(rr_graph_, - child_node.inode, - target_node)) { - add_route_tree_to_heap(child_node, - target_node, - cost_params, - net_bb); - } - } else { - add_route_tree_to_heap(child_node, - target_node, - cost_params, - net_bb); - } - } -} - //Unconditionally adds rt_node to the heap // //Note that if you want to respect rt_node.re_expand that is the caller's @@ -841,24 +430,24 @@ void ParallelConnectionRouter::add_route_tree_node_to_heap( * Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008.*/ // float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); - if (!rcv_path_manager.is_enabled()) { + if (!this->rcv_path_manager.is_enabled()) { // tot_cost = backward_path_cost + cost_params.astar_fac * expected_cost; - float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); + float expected_cost = this->router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); float tot_cost = backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); - VTR_LOGV_DEBUG(router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", + VTR_LOGV_DEBUG(this->router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", inode, tot_cost, - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, is_flat_).c_str()); + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, this->is_flat_).c_str()); - if (prune_node(inode, tot_cost, backward_path_cost, RREdgeId::INVALID(), target_node, rr_node_route_inf_, cost_params)) { + if (prune_node(inode, tot_cost, backward_path_cost, RREdgeId::INVALID(), target_node, this->rr_node_route_inf_, cost_params)) { return; } add_to_mod_list(inode, 0 /*main thread*/); - rr_node_route_inf_[inode].path_cost = tot_cost; - rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); - rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; - rr_node_route_inf_[inode].R_upstream = R_upstream; - heap_.push_back({tot_cost, inode}); + this->rr_node_route_inf_[inode].path_cost = tot_cost; + this->rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); + this->rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; + this->rr_node_route_inf_[inode].R_upstream = R_upstream; + this->heap_.push_back({tot_cost, inode}); // push_back_node(&heap_, rr_node_route_inf_, // inode, tot_cost, RREdgeId::INVALID(), @@ -869,175 +458,6 @@ void ParallelConnectionRouter::add_route_tree_node_to_heap( // } } -/* Expand bb by inode's extents and clip against net_bb */ -inline void expand_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb, RRNodeId inode, const RRGraphView* rr_graph) { - bb.xmin = std::max(net_bb.xmin, std::min(bb.xmin, rr_graph->node_xlow(inode))); - bb.ymin = std::max(net_bb.ymin, std::min(bb.ymin, rr_graph->node_ylow(inode))); - bb.xmax = std::min(net_bb.xmax, std::max(bb.xmax, rr_graph->node_xhigh(inode))); - bb.ymax = std::min(net_bb.ymax, std::max(bb.ymax, rr_graph->node_yhigh(inode))); - bb.layer_min = std::min(bb.layer_min, rr_graph->node_layer(inode)); - bb.layer_max = std::max(bb.layer_max, rr_graph->node_layer(inode)); -} - -/* Expand bb by HIGH_FANOUT_BB_FAC and clip against net_bb */ -inline void adjust_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb) { - constexpr int HIGH_FANOUT_BB_FAC = 3; - - bb.xmin = std::max(net_bb.xmin, bb.xmin - HIGH_FANOUT_BB_FAC); - bb.ymin = std::max(net_bb.ymin, bb.ymin - HIGH_FANOUT_BB_FAC); - bb.xmax = std::min(net_bb.xmax, bb.xmax + HIGH_FANOUT_BB_FAC); - bb.ymax = std::min(net_bb.ymax, bb.ymax + HIGH_FANOUT_BB_FAC); - bb.layer_min = std::min(net_bb.layer_min, bb.layer_min); - bb.layer_max = std::max(net_bb.layer_max, bb.layer_max); -} - -template -t_bb ParallelConnectionRouter::add_high_fanout_route_tree_to_heap( - const RouteTreeNode& rt_root, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const SpatialRouteTreeLookup& spatial_rt_lookup, - const t_bb& net_bounding_box) { - //For high fanout nets we only add those route tree nodes which are spatially close - //to the sink. - // - //Based on: - // J. Swartz, V. Betz, J. Rose, "A Fast Routability-Driven Router for FPGAs", FPGA, 1998 - // - //We rely on a grid-based spatial look-up which is maintained for high fanout nets by - //update_route_tree(), which allows us to add spatially close route tree nodes without traversing - //the entire route tree (which is likely large for a high fanout net). - - //Determine which bin the target node is located in - - int target_bin_x = grid_to_bin_x(rr_graph_->node_xlow(target_node), spatial_rt_lookup); - int target_bin_y = grid_to_bin_y(rr_graph_->node_ylow(target_node), spatial_rt_lookup); - - auto target_layer = rr_graph_->node_layer(target_node); - - int chan_nodes_added = 0; - - t_bb highfanout_bb; - highfanout_bb.xmin = rr_graph_->node_xlow(target_node); - highfanout_bb.xmax = rr_graph_->node_xhigh(target_node); - highfanout_bb.ymin = rr_graph_->node_ylow(target_node); - highfanout_bb.ymax = rr_graph_->node_yhigh(target_node); - highfanout_bb.layer_min = target_layer; - highfanout_bb.layer_max = target_layer; - - //Add existing routing starting from the target bin. - //If the target's bin has insufficient existing routing add from the surrounding bins - constexpr int SINGLE_BIN_MIN_NODES = 2; - bool done = false; - bool found_node_on_same_layer = false; - for (int dx : {0, -1, +1}) { - size_t bin_x = target_bin_x + dx; - - if (bin_x > spatial_rt_lookup.dim_size(0) - 1) continue; //Out of range - - for (int dy : {0, -1, +1}) { - size_t bin_y = target_bin_y + dy; - - if (bin_y > spatial_rt_lookup.dim_size(1) - 1) continue; //Out of range - - for (const RouteTreeNode& rt_node : spatial_rt_lookup[bin_x][bin_y]) { - if (!rt_node.re_expand) // Some nodes (like IPINs) shouldn't be re-expanded - continue; - RRNodeId rr_node_to_add = rt_node.inode; - - /* Flat router: don't go into clusters other than the target one */ - if (is_flat_) { - if (!relevant_node_to_target(rr_graph_, rr_node_to_add, target_node)) - continue; - } - - /* In case of the parallel router, we may be dealing with a virtual net - * so prune the nodes from the HF lookup against the bounding box just in case */ - if (!inside_bb(rr_node_to_add, net_bounding_box)) - continue; - - auto rt_node_layer_num = rr_graph_->node_layer(rr_node_to_add); - if (rt_node_layer_num == target_layer) - found_node_on_same_layer = true; - - // Put the node onto the heap - add_route_tree_node_to_heap(rt_node, target_node, cost_params, net_bounding_box); - - // Expand HF BB to include the node (clip by original BB) - expand_highfanout_bounding_box(highfanout_bb, net_bounding_box, rr_node_to_add, rr_graph_); - - if (rr_graph_->node_type(rr_node_to_add) == CHANY || rr_graph_->node_type(rr_node_to_add) == CHANX) { - chan_nodes_added++; - } - } - - if (dx == 0 && dy == 0 && chan_nodes_added > SINGLE_BIN_MIN_NODES && found_node_on_same_layer) { - //Target bin contained at least minimum amount of routing - // - //We require at least SINGLE_BIN_MIN_NODES to be added. - //This helps ensure we don't end up with, for example, a single - //routing wire running in the wrong direction which may not be - //able to reach the target within the bounding box. - done = true; - break; - } - } - if (done) break; - } - /* If we didn't find enough nodes to branch off near the target - * or they are on the wrong grid layer, just add the full route tree */ - if (chan_nodes_added <= SINGLE_BIN_MIN_NODES || !found_node_on_same_layer) { - add_route_tree_to_heap(rt_root, target_node, cost_params, net_bounding_box); - return net_bounding_box; - } else { - //We found nearby routing, replace original bounding box to be localized around that routing - adjust_highfanout_bounding_box(highfanout_bb, net_bounding_box); - return highfanout_bb; - } -} - -static inline bool relevant_node_to_target(const RRGraphView* rr_graph, - RRNodeId node_to_add, - RRNodeId target_node) { - VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == t_rr_type::SINK); - auto node_to_add_type = rr_graph->node_type(node_to_add); - return node_to_add_type != t_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); -} - -static inline void update_router_stats(RouterStats* router_stats, - bool is_push, - RRNodeId rr_node_id, - const RRGraphView* rr_graph) { - if (is_push) { - router_stats->heap_pushes++; - } else { - router_stats->heap_pops++; - } - - if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - auto node_type = rr_graph->node_type(rr_node_id); - VTR_ASSERT(node_type != NUM_RR_TYPES); - - if (is_inter_cluster_node(*rr_graph, rr_node_id)) { - if (is_push) { - router_stats->inter_cluster_node_pushes++; - router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; - } else { - router_stats->inter_cluster_node_pops++; - router_stats->inter_cluster_node_type_cnt_pops[node_type]++; - } - } else { - if (is_push) { - router_stats->intra_cluster_node_pushes++; - router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; - } else { - router_stats->intra_cluster_node_pops++; - router_stats->intra_cluster_node_type_cnt_pops[node_type]++; - } - } - } -} - std::unique_ptr make_parallel_connection_router(e_heap_type heap_type, const DeviceGrid& grid, const RouterLookahead& router_lookahead, diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h index 1c8fd19c35d..e38789ed3d5 100644 --- a/vpr/src/route/parallel_connection_router.h +++ b/vpr/src/route/parallel_connection_router.h @@ -1,14 +1,7 @@ #ifndef _PARALLEL_CONNECTION_ROUTER_H #define _PARALLEL_CONNECTION_ROUTER_H -#include "connection_router_interface.h" -#include "rr_graph_storage.h" -#include "route_common.h" -#include "router_lookahead.h" -#include "route_tree.h" -#include "rr_rc_data.h" -#include "router_stats.h" -#include "spatial_route_tree_lookup.h" +#include "connection_router.h" #include "d_ary_heap.h" #include "multi_queue_d_ary_heap.h" @@ -95,7 +88,7 @@ using barrier_t = barrier_spin_t; // node (which is returned) through the rr_node_route_inf. See // update_traceback as an example of this tracing. template -class ParallelConnectionRouter : public ConnectionRouterInterface { +class ParallelConnectionRouter : public ConnectionRouter { public: ParallelConnectionRouter( const DeviceGrid& grid, @@ -109,58 +102,38 @@ class ParallelConnectionRouter : public ConnectionRouterInterface { int multi_queue_num_threads, int multi_queue_num_queues, bool multi_queue_direct_draining) - : grid_(grid) - , router_lookahead_(router_lookahead) - , rr_nodes_(rr_nodes.view()) - , rr_graph_(rr_graph) - , rr_rc_data_(rr_rc_data.data(), rr_rc_data.size()) - , rr_switch_inf_(rr_switch_inf.data(), rr_switch_inf.size()) - , net_terminal_groups(g_vpr_ctx.routing().net_terminal_groups) - , net_terminal_group_num(g_vpr_ctx.routing().net_terminal_group_num) - , rr_node_route_inf_(rr_node_route_inf) - , is_flat_(is_flat) + : ConnectionRouter(grid, router_lookahead, rr_nodes, rr_graph, rr_rc_data, rr_switch_inf, rr_node_route_inf, is_flat) , modified_rr_node_inf_(multi_queue_num_threads) - , router_stats_(nullptr) , heap_(multi_queue_num_threads, multi_queue_num_queues) , thread_barrier_(multi_queue_num_threads) , is_router_destroying_(false) , locks_(rr_node_route_inf.size()) - , multi_queue_direct_draining_(multi_queue_direct_draining) - , router_debug_(false) - , path_search_cumulative_time(0) { - heap_.init_heap(grid); - only_opin_inter_layer = (grid.get_num_layers() > 1) && inter_layer_connections_limited_to_opin(*rr_graph); - - sub_threads_.resize(multi_queue_num_threads - 1); - thread_barrier_.init(); + , multi_queue_direct_draining_(multi_queue_direct_draining) { + this->sub_threads_.resize(multi_queue_num_threads - 1); + this->thread_barrier_.init(); for (int i = 0; i < multi_queue_num_threads - 1; ++i) { - sub_threads_[i] = std::thread(&ParallelConnectionRouter::timing_driven_route_connection_from_heap_sub_thread_wrapper, this, i + 1 /*0: main thread*/); - sub_threads_[i].detach(); + this->sub_threads_[i] = std::thread(&ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap_sub_thread_wrapper, this, i + 1 /*0: main thread*/); + this->sub_threads_[i].detach(); } } ~ParallelConnectionRouter() { - is_router_destroying_ = true; - thread_barrier_.wait(); + this->is_router_destroying_ = true; + this->thread_barrier_.wait(); VTR_LOG("Parallel Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", - std::chrono::duration(path_search_cumulative_time).count()); + std::chrono::duration(this->path_search_cumulative_time).count()); } - // Clear's the modified list. Should be called after reset_path_costs - // have been called. void clear_modified_rr_node_info() final { - for (auto& thread_visited_rr_nodes : modified_rr_node_inf_) { + for (auto& thread_visited_rr_nodes : this->modified_rr_node_inf_) { thread_visited_rr_nodes.clear(); } } - // Reset modified data in rr_node_route_inf based on modified_rr_node_inf. - // Derived from `reset_path_costs` from route_common.cpp as a specific version - // for the parallel connection router. void reset_path_costs() final { auto& route_ctx = g_vpr_ctx.mutable_routing(); - for (const auto& thread_visited_rr_nodes : modified_rr_node_inf_) { + for (const auto& thread_visited_rr_nodes : this->modified_rr_node_inf_) { for (const auto node : thread_visited_rr_nodes) { route_ctx.rr_node_route_inf[node].path_cost = std::numeric_limits::infinity(); route_ctx.rr_node_route_inf[node].backward_path_cost = std::numeric_limits::infinity(); @@ -169,81 +142,25 @@ class ParallelConnectionRouter : public ConnectionRouterInterface { } } - /** Finds a path from the route tree rooted at rt_root to sink_node. - * This is used when you want to allow previous routing of the same net to - * serve as valid start locations for the current connection. - * - * Returns a tuple of: - * bool: path exists? (hard failure, rr graph disconnected) - * bool: should retry with full bounding box? (only used in parallel routing) - * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ - std::tuple timing_driven_route_connection_from_route_tree( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RouterStats& router_stats, - const ConnectionParameters& conn_params) final; - - /** Finds a path from the route tree rooted at rt_root to sink_node for a - * high fanout net. - * - * Unlike timing_driven_route_connection_from_route_tree(), only part of - * the route tree which is spatially close to the sink is added to the heap. - * - * Returns a tuple of: - * bool: path exists? (hard failure, rr graph disconnected) - * bool: should retry with full bounding box? (only used in parallel routing) - * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ - std::tuple timing_driven_route_connection_from_route_tree_high_fanout( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bounding_box, - const SpatialRouteTreeLookup& spatial_rt_lookup, - RouterStats& router_stats, - const ConnectionParameters& conn_params) final; + void set_rcv_enabled(bool) final { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "RCV for parallel connection router not yet implemented. Not expected to be called."); + } - // Finds a path from the route tree rooted at rt_root to all sinks - // available. - // - // Each element of the returned vector is a reachable sink. - // - // If cost_params.astar_fac is set to 0, this effectively becomes - // Dijkstra's algorithm with a modified exit condition (runs until heap is - // empty). When using cost_params.astar_fac = 0, for efficiency the - // RouterLookahead used should be the NoOpLookahead. - // - // Note: This routine is currently used only to generate information that - // may be helpful in debugging an architecture. vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( - const RouteTreeNode& rt_root, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RouterStats& router_stats, - const ConnectionParameters& conn_params) final; - - void set_router_debug(bool router_debug) final { - router_debug_ = router_debug; + const RouteTreeNode&, + const t_conn_cost_params&, + const t_bb&, + RouterStats&, + const ConnectionParameters&) final { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_route_tree not yet implemented (nor is the focus of this project). Not expected to be called."); } - // Empty the route tree set used for RCV node detection - // Will return if RCV is disabled - // Called after each net is finished routing to flush the set - void empty_rcv_route_tree_set() final; - - // Enable or disable RCV in connection router - // Enabling this will utilize extra path structures, as well as the RCV cost function - // - // Ensure route budgets have been calculated before enabling this - void set_rcv_enabled(bool enable) final; - - private: + protected: // Mark that data associated with rr_node "inode" has been modified, and // needs to be reset in reset_path_costs. - void add_to_mod_list(RRNodeId inode, size_t thread_idx) { - if (std::isinf(rr_node_route_inf_[inode].path_cost)) { - modified_rr_node_inf_[thread_idx].push_back(inode); + inline void add_to_mod_list(RRNodeId inode, size_t thread_idx) { + if (std::isinf(this->rr_node_route_inf_[inode].path_cost)) { + this->modified_rr_node_inf_[thread_idx].push_back(inode); } } @@ -252,53 +169,29 @@ class ParallelConnectionRouter : public ConnectionRouterInterface { inline void update_cheapest(RTExploredNode& cheapest, size_t thread_idx) { const RRNodeId& inode = cheapest.index; add_to_mod_list(inode, thread_idx); - rr_node_route_inf_[inode].prev_edge = cheapest.prev_edge; - rr_node_route_inf_[inode].path_cost = cheapest.total_cost; - rr_node_route_inf_[inode].backward_path_cost = cheapest.backward_path_cost; + this->rr_node_route_inf_[inode].prev_edge = cheapest.prev_edge; + this->rr_node_route_inf_[inode].path_cost = cheapest.total_cost; + this->rr_node_route_inf_[inode].backward_path_cost = cheapest.backward_path_cost; } inline void obtainSpinLock(const RRNodeId& inode) { - locks_[size_t(inode)].acquire(); + this->locks_[size_t(inode)].acquire(); } inline void releaseLock(const RRNodeId& inode) { - locks_[size_t(inode)].release(); + this->locks_[size_t(inode)].release(); } - /** Common logic from timing_driven_route_connection_from_route_tree and - * timing_driven_route_connection_from_route_tree_high_fanout for running - * the connection router. - * @param[in] rt_root RouteTreeNode describing the current routing state - * @param[in] sink_node Sink node ID to route to - * @param[in] cost_params - * @param[in] bounding_box Keep search confined to this bounding box - * @return bool Signal to retry this connection with a full-device bounding box */ - bool timing_driven_route_connection_common_setup( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box); - - // Finds a path to sink_node, starting from the elements currently in the - // heap. - // - // If the path is not found, which means that the path_cost of sink_node in - // RR node route info has never been updated, `rr_node_route_inf_[sink_node] - // .path_cost` will be the initial value (i.e., float infinity). This case - // can be detected by `std::isinf(rr_node_route_inf_[sink_node].path_cost)`. - // - // This is the core maze routing routine. - // - // Note: For understanding the connection router, start here. - void timing_driven_route_connection_from_heap( - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box); + // Find the shortest path from current heap to the sink node in the RR graph + void timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) final; - void timing_driven_route_connection_from_heap_sub_thread_wrapper( + void timing_driven_find_single_shortest_path_from_heap_sub_thread_wrapper( const size_t thread_idx); - void timing_driven_route_connection_from_heap_thread_func( + void timing_driven_find_single_shortest_path_from_heap_thread_func( RRNodeId sink_node, const t_conn_cost_params& cost_params, const t_bb& bounding_box, @@ -339,25 +232,7 @@ class ParallelConnectionRouter : public ConnectionRouterInterface { RRNodeId target_node, size_t thread_idx); - // Calculates the cost of reaching to_node - void evaluate_timing_driven_node_costs( - RTExploredNode* to, - const t_conn_cost_params& cost_params, - RRNodeId from_node, - RRNodeId target_node); - - // Find paths from current heap to all nodes in the RR graph - vtr::vector timing_driven_find_all_shortest_paths_from_heap( - const t_conn_cost_params& cost_params, - const t_bb& bounding_box); - - //Adds the route tree rooted at rt_node to the heap, preparing it to be - //used as branch-points for further routing. - void add_route_tree_to_heap(const RouteTreeNode& rt_node, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bb); - + // TODO: move this function into ConnectionRouter class //Unconditionally adds rt_node to the heap // //Note that if you want to respect rt_node->re_expand that is the caller's @@ -368,26 +243,14 @@ class ParallelConnectionRouter : public ConnectionRouterInterface { const t_conn_cost_params& cost_params, const t_bb& net_bb); - t_bb add_high_fanout_route_tree_to_heap( - const RouteTreeNode& rt_root, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const SpatialRouteTreeLookup& spatial_route_tree_lookup, - const t_bb& net_bounding_box); - - const DeviceGrid& grid_; - const RouterLookahead& router_lookahead_; - const t_rr_graph_view rr_nodes_; - const RRGraphView* rr_graph_; - vtr::array_view rr_rc_data_; - vtr::array_view rr_switch_inf_; - const vtr::vector>>& net_terminal_groups; - const vtr::vector>& net_terminal_group_num; - vtr::vector& rr_node_route_inf_; - bool is_flat_; + // Find paths from current heap to all nodes in the RR graph + vtr::vector timing_driven_find_all_shortest_paths_from_heap( + const t_conn_cost_params&, + const t_bb&) final { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_heap not yet implemented (nor is the focus of this project). Not expected to be called."); + } + std::vector> modified_rr_node_inf_; - RouterStats* router_stats_; - const ConnectionParameters* conn_params_; MultiQueueDAryHeap heap_; std::vector sub_threads_; barrier_t thread_barrier_; @@ -395,22 +258,10 @@ class ParallelConnectionRouter : public ConnectionRouterInterface { std::vector locks_; bool multi_queue_direct_draining_; - bool router_debug_; - - bool only_opin_inter_layer; - std::atomic sink_node_; std::atomic cost_params_; std::atomic bounding_box_; std::atomic target_bb_; - - // Cumulative time spent in the path search part of the connection router. - std::chrono::microseconds path_search_cumulative_time; - - // The path manager for RCV, keeps track of the route tree as a set, also - // manages the allocation of `rcv_path_data`. - PathManager rcv_path_manager; - vtr::vector rcv_path_data; }; /** Construct a parallel connection router that uses the specified heap type. diff --git a/vpr/src/route/route_net.tpp b/vpr/src/route/route_net.tpp index 71256eb6c22..a30b2e07adc 100644 --- a/vpr/src/route/route_net.tpp +++ b/vpr/src/route/route_net.tpp @@ -40,8 +40,8 @@ * @param should_setup Should we reset/prune the existing route tree first? * @param sink_mask Which sinks to route? Assumed all sinks if nullopt, otherwise a mask of [1..num_sinks+1] where set bits request the sink to be routed * @return NetResultFlags for this net */ -template -inline NetResultFlags route_net(ConnectionRouter& router, +template +inline NetResultFlags route_net(ConnectionRouterType& router, const Netlist<>& net_list, const ParentNetId& net_id, int itry, @@ -287,8 +287,8 @@ inline NetResultFlags route_net(ConnectionRouter& router, /** Route to a "virtual sink" in the netlist which corresponds to the start point * of the global clock network. */ -template -inline NetResultFlags pre_route_to_clock_root(ConnectionRouter& router, +template +inline NetResultFlags pre_route_to_clock_root(ConnectionRouterType& router, ParentNetId net_id, const Netlist<>& net_list, RRNodeId sink_node, @@ -401,8 +401,8 @@ inline NetResultFlags pre_route_to_clock_root(ConnectionRouter& router, * @param is_flat * @param net_bb Bounding box for the net (Routing resources outside net_bb will not be used) * @return NetResultFlags for this sink to be bubbled up through route_net */ -template -inline NetResultFlags route_sink(ConnectionRouter& router, +template +inline NetResultFlags route_sink(ConnectionRouterType& router, const Netlist<>& net_list, ParentNetId net_id, unsigned itarget, diff --git a/vpr/src/route/serial_connection_router.cpp b/vpr/src/route/serial_connection_router.cpp index 3c03ed71fa6..cc017506385 100644 --- a/vpr/src/route/serial_connection_router.cpp +++ b/vpr/src/route/serial_connection_router.cpp @@ -4,230 +4,24 @@ #include "rr_graph.h" #include "rr_graph_fwd.h" -/** Used for the flat router. The node isn't relevant to the target if - * it is an intra-block node outside of our target block */ -static bool relevant_node_to_target(const RRGraphView* rr_graph, - RRNodeId node_to_add, - RRNodeId target_node); - -static void update_router_stats(RouterStats* router_stats, - bool is_push, - RRNodeId rr_node_id, - const RRGraphView* rr_graph); - -/** return tuple */ -template -std::tuple SerialConnectionRouter::timing_driven_route_connection_from_route_tree( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RouterStats& router_stats, - const ConnectionParameters& conn_params) { - router_stats_ = &router_stats; - conn_params_ = &conn_params; - - bool retry = false; - retry = timing_driven_route_connection_common_setup(rt_root, sink_node, cost_params, bounding_box); - - if (!std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - // Only the `index`, `prev_edge`, and `rcv_path_backward_delay` fields of `out` - // are used after this function returns. - RTExploredNode out; - out.index = sink_node; - out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; - if (rcv_path_manager.is_enabled()) { - out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; - rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); - rcv_path_manager.empty_heap(); - } - heap_.empty_heap(); - return std::make_tuple(true, /*retry=*/false, out); - } else { - reset_path_costs(); - clear_modified_rr_node_info(); - heap_.empty_heap(); - rcv_path_manager.empty_heap(); - return std::make_tuple(false, retry, RTExploredNode()); - } -} - -/** Return whether to retry with full bb */ -template -bool SerialConnectionRouter::timing_driven_route_connection_common_setup( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { - //Re-add route nodes from the existing route tree to the heap. - //They need to be repushed onto the heap since each node's cost is target specific. - - add_route_tree_to_heap(rt_root, sink_node, cost_params, bounding_box); - heap_.build_heap(); // via sifting down everything - - RRNodeId source_node = rt_root.inode; - - if (heap_.is_empty_heap()) { - VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - return false; - } - - VTR_LOGV_DEBUG(router_debug_, " Routing to %d as normal net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, - bounding_box.layer_min, bounding_box.xmin, bounding_box.ymin, - bounding_box.layer_max, bounding_box.xmax, bounding_box.ymax); - - timing_driven_route_connection_from_heap(sink_node, - cost_params, - bounding_box); - - if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - // No path found within the current bounding box. - // - // If the bounding box is already max size, just fail - if (bounding_box.xmin == 0 - && bounding_box.ymin == 0 - && bounding_box.xmax == (int)(grid_.width() - 1) - && bounding_box.ymax == (int)(grid_.height() - 1) - && bounding_box.layer_min == 0 - && bounding_box.layer_max == (int)(grid_.get_num_layers() - 1)) { - VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - return false; - } - - // Otherwise, leave unrouted and bubble up a signal to retry this net with a full-device bounding box - VTR_LOG_WARN("No routing path for connection to sink_rr %d, leaving unrouted to retry later\n", sink_node); - return true; - } - - return false; -} - -// Finds a path from the route tree rooted at rt_root to sink_node for a high fanout net. -// -// Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree -// which is spatially close to the sink is added to the heap. -// Returns a tuple of */ -template -std::tuple SerialConnectionRouter::timing_driven_route_connection_from_route_tree_high_fanout( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bounding_box, - const SpatialRouteTreeLookup& spatial_rt_lookup, - RouterStats& router_stats, - const ConnectionParameters& conn_params) { - router_stats_ = &router_stats; - conn_params_ = &conn_params; - - // re-explore route tree from root to add any new nodes (buildheap afterwards) - // route tree needs to be repushed onto the heap since each node's cost is target specific - t_bb high_fanout_bb = add_high_fanout_route_tree_to_heap(rt_root, sink_node, cost_params, spatial_rt_lookup, net_bounding_box); - heap_.build_heap(); - - RRNodeId source_node = rt_root.inode; - - if (heap_.is_empty_heap()) { - VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - return std::make_tuple(false, false, RTExploredNode()); - } - - VTR_LOGV_DEBUG(router_debug_, " Routing to %d as high fanout net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, - high_fanout_bb.layer_min, high_fanout_bb.xmin, high_fanout_bb.ymin, - high_fanout_bb.layer_max, high_fanout_bb.xmax, high_fanout_bb.ymax); - - bool retry_with_full_bb = false; - timing_driven_route_connection_from_heap(sink_node, - cost_params, - high_fanout_bb); - - if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - //Found no path, that may be due to an unlucky choice of existing route tree sub-set, - //try again with the full route tree to be sure this is not an artifact of high-fanout routing - VTR_LOG_WARN("No routing path found in high-fanout mode for net %zu connection (to sink_rr %d), retrying with full route tree\n", size_t(conn_params.net_id_), sink_node); - - //Reset any previously recorded node costs so timing_driven_route_connection() - //starts over from scratch. - reset_path_costs(); - clear_modified_rr_node_info(); - - retry_with_full_bb = timing_driven_route_connection_common_setup(rt_root, - sink_node, - cost_params, - net_bounding_box); - } - - if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - - heap_.empty_heap(); - rcv_path_manager.empty_heap(); - return std::make_tuple(false, retry_with_full_bb, RTExploredNode()); - } - - RTExploredNode out; - out.index = sink_node; - out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; - if (rcv_path_manager.is_enabled()) { - out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; - rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); - rcv_path_manager.empty_heap(); - } - heap_.empty_heap(); - - return std::make_tuple(true, retry_with_full_bb, out); -} - -// Finds a path to sink_node, starting from the elements currently in the heap. -// This is the core maze routing routine. template -void SerialConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { - VTR_ASSERT_SAFE(heap_.is_valid()); - - if (heap_.is_empty_heap()) { //No source - VTR_LOGV_DEBUG(router_debug_, " Initial heap empty (no source)\n"); - } - +void SerialConnectionRouter::timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) { const auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); - // Get bounding box for sink node used in timing_driven_expand_neighbour - VTR_ASSERT_SAFE(sink_node != RRNodeId::INVALID()); - - t_bb target_bb; - if (rr_graph_->node_type(sink_node) == SINK) { // We need to get a bounding box for the sink's entire tile - vtr::Rect tile_bb = grid_.get_tile_bb({rr_graph_->node_xlow(sink_node), - rr_graph_->node_ylow(sink_node), - rr_graph_->node_layer(sink_node)}); - - target_bb.xmin = tile_bb.xmin(); - target_bb.ymin = tile_bb.ymin(); - target_bb.xmax = tile_bb.xmax(); - target_bb.ymax = tile_bb.ymax(); - } else { - target_bb.xmin = rr_graph_->node_xlow(sink_node); - target_bb.ymin = rr_graph_->node_ylow(sink_node); - target_bb.xmax = rr_graph_->node_xhigh(sink_node); - target_bb.ymax = rr_graph_->node_yhigh(sink_node); - } - - target_bb.layer_min = rr_graph_->node_layer(RRNodeId(sink_node)); - target_bb.layer_max = rr_graph_->node_layer(RRNodeId(sink_node)); - - // Start measuring path search time - std::chrono::steady_clock::time_point begin_time = std::chrono::steady_clock::now(); - HeapNode cheapest; - while (heap_.try_pop(cheapest)) { + while (this->heap_.try_pop(cheapest)) { // inode with the cheapest total cost in current route tree to be expanded on const auto& [new_total_cost, inode] = cheapest; - update_router_stats(router_stats_, + update_router_stats(this->router_stats_, /*is_push=*/false, inode, - rr_graph_); + this->rr_graph_); - VTR_LOGV_DEBUG(router_debug_, " Popping node %d (cost: %g)\n", + VTR_LOGV_DEBUG(this->router_debug_, " Popping node %d (cost: %g)\n", inode, new_total_cost); // Have we found the target? @@ -235,13 +29,13 @@ void SerialConnectionRouter::timing_driven_route_connection_from_heap(RRNo // If we're running RCV, the path will be stored in the path_data->path_rr vector // This is then placed into the traceback so that the correct path is returned // TODO: This can be eliminated by modifying the actual traceback function in route_timing - if (rcv_path_manager.is_enabled()) { - rcv_path_manager.insert_backwards_path_into_traceback(rcv_path_data[inode], - rr_node_route_inf_[inode].path_cost, - rr_node_route_inf_[inode].backward_path_cost, - route_ctx); + if (this->rcv_path_manager.is_enabled()) { + this->rcv_path_manager.insert_backwards_path_into_traceback(this->rcv_path_data[inode], + this->rr_node_route_inf_[inode].path_cost, + this->rr_node_route_inf_[inode].backward_path_cost, + route_ctx); } - VTR_LOGV_DEBUG(router_debug_, " Found target %8d (%s)\n", inode, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, is_flat_).c_str()); + VTR_LOGV_DEBUG(this->router_debug_, " Found target %8d (%s)\n", inode, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, this->is_flat_).c_str()); break; } @@ -253,10 +47,6 @@ void SerialConnectionRouter::timing_driven_route_connection_from_heap(RRNo bounding_box, target_bb); } - - // Stop measuring path search time - std::chrono::steady_clock::time_point end_time = std::chrono::steady_clock::now(); - path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); } // Find shortest paths from specified route tree to all nodes in the RR graph @@ -267,16 +57,16 @@ vtr::vector SerialConnectionRouter::timing_drive const t_bb& bounding_box, RouterStats& router_stats, const ConnectionParameters& conn_params) { - router_stats_ = &router_stats; - conn_params_ = &conn_params; + this->router_stats_ = &router_stats; + this->conn_params_ = &conn_params; // Add the route tree to the heap with no specific target node RRNodeId target_node = RRNodeId::INVALID(); - add_route_tree_to_heap(rt_root, target_node, cost_params, bounding_box); - heap_.build_heap(); // via sifting down everything + this->add_route_tree_to_heap(rt_root, target_node, cost_params, bounding_box); + this->heap_.build_heap(); // via sifting down everything auto res = timing_driven_find_all_shortest_paths_from_heap(cost_params, bounding_box); - heap_.empty_heap(); + this->heap_.empty_heap(); return res; } @@ -289,27 +79,27 @@ template vtr::vector SerialConnectionRouter::timing_driven_find_all_shortest_paths_from_heap( const t_conn_cost_params& cost_params, const t_bb& bounding_box) { - vtr::vector cheapest_paths(rr_nodes_.size()); + vtr::vector cheapest_paths(this->rr_nodes_.size()); - VTR_ASSERT_SAFE(heap_.is_valid()); + VTR_ASSERT_SAFE(this->heap_.is_valid()); - if (heap_.is_empty_heap()) { // No source - VTR_LOGV_DEBUG(router_debug_, " Initial heap empty (no source)\n"); + if (this->heap_.is_empty_heap()) { // No source + VTR_LOGV_DEBUG(this->router_debug_, " Initial heap empty (no source)\n"); } // Start measuring path search time std::chrono::steady_clock::time_point begin_time = std::chrono::steady_clock::now(); HeapNode cheapest; - while (heap_.try_pop(cheapest)) { + while (this->heap_.try_pop(cheapest)) { // inode with the cheapest total cost in current route tree to be expanded on const auto& [new_total_cost, inode] = cheapest; - update_router_stats(router_stats_, + update_router_stats(this->router_stats_, /*is_push=*/false, inode, - rr_graph_); + this->rr_graph_); - VTR_LOGV_DEBUG(router_debug_, " Popping node %d (cost: %g)\n", + VTR_LOGV_DEBUG(this->router_debug_, " Popping node %d (cost: %g)\n", inode, new_total_cost); // Since we want to find shortest paths to all nodes in the graph @@ -327,18 +117,18 @@ vtr::vector SerialConnectionRouter::timing_drive t_bb()); if (cheapest_paths[inode].index == RRNodeId::INVALID() || cheapest_paths[inode].total_cost >= new_total_cost) { - VTR_LOGV_DEBUG(router_debug_, " Better cost to node %d: %g (was %g)\n", inode, new_total_cost, cheapest_paths[inode].total_cost); + VTR_LOGV_DEBUG(this->router_debug_, " Better cost to node %d: %g (was %g)\n", inode, new_total_cost, cheapest_paths[inode].total_cost); // Only the `index` and `prev_edge` fields of `cheapest_paths[inode]` are used after this function returns cheapest_paths[inode].index = inode; - cheapest_paths[inode].prev_edge = rr_node_route_inf_[inode].prev_edge; + cheapest_paths[inode].prev_edge = this->rr_node_route_inf_[inode].prev_edge; } else { - VTR_LOGV_DEBUG(router_debug_, " Worse cost to node %d: %g (better %g)\n", inode, new_total_cost, cheapest_paths[inode].total_cost); + VTR_LOGV_DEBUG(this->router_debug_, " Worse cost to node %d: %g (better %g)\n", inode, new_total_cost, cheapest_paths[inode].total_cost); } } // Stop measuring path search time std::chrono::steady_clock::time_point end_time = std::chrono::steady_clock::now(); - path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); + this->path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); return cheapest_paths; } @@ -350,7 +140,7 @@ void SerialConnectionRouter::timing_driven_expand_cheapest(RRNodeId from_n const t_conn_cost_params& cost_params, const t_bb& bounding_box, const t_bb& target_bb) { - float best_total_cost = rr_node_route_inf_[from_node].path_cost; + float best_total_cost = this->rr_node_route_inf_[from_node].path_cost; if (best_total_cost == new_total_cost) { // Explore from this node, since its total cost is exactly the same as // the best total cost ever seen for this node. Otherwise, prune this node @@ -365,29 +155,29 @@ void SerialConnectionRouter::timing_driven_expand_cheapest(RRNodeId from_n // (including expected delay to sink, going through a cost function that // checks that against the target delay) might be lower than the previously // stored value. In that case we want to re-expand the node so long as - // it doesn't create a loop. That `rcv_path_manager` should store enough + // it doesn't create a loop. That `this->rcv_path_manager` should store enough // info for us to avoid loops. RTExploredNode current; current.index = from_node; - current.backward_path_cost = rr_node_route_inf_[from_node].backward_path_cost; - current.prev_edge = rr_node_route_inf_[from_node].prev_edge; - current.R_upstream = rr_node_route_inf_[from_node].R_upstream; + current.backward_path_cost = this->rr_node_route_inf_[from_node].backward_path_cost; + current.prev_edge = this->rr_node_route_inf_[from_node].prev_edge; + current.R_upstream = this->rr_node_route_inf_[from_node].R_upstream; - VTR_LOGV_DEBUG(router_debug_, " Better cost to %d\n", from_node); - VTR_LOGV_DEBUG(router_debug_, " New total cost: %g\n", new_total_cost); - VTR_LOGV_DEBUG(router_debug_ && (current.prev_edge != RREdgeId::INVALID()), + VTR_LOGV_DEBUG(this->router_debug_, " Better cost to %d\n", from_node); + VTR_LOGV_DEBUG(this->router_debug_, " New total cost: %g\n", new_total_cost); + VTR_LOGV_DEBUG(this->router_debug_ && (current.prev_edge != RREdgeId::INVALID()), " Setting path costs for associated node %d (from %d edge %zu)\n", from_node, - static_cast(rr_graph_->edge_src_node(current.prev_edge)), + static_cast(this->rr_graph_->edge_src_node(current.prev_edge)), static_cast(current.prev_edge)); timing_driven_expand_neighbours(current, cost_params, bounding_box, target_node, target_bb); } else { // Post-heap prune, do not re-explore from the current/new partial path as it // has worse cost than the best partial path to this node found so far - VTR_LOGV_DEBUG(router_debug_, " Worse cost to %d\n", from_node); - VTR_LOGV_DEBUG(router_debug_, " Old total cost: %g\n", best_total_cost); - VTR_LOGV_DEBUG(router_debug_, " New total cost: %g\n", new_total_cost); + VTR_LOGV_DEBUG(this->router_debug_, " Worse cost to %d\n", from_node); + VTR_LOGV_DEBUG(this->router_debug_, " Old total cost: %g\n", best_total_cost); + VTR_LOGV_DEBUG(this->router_debug_, " New total cost: %g\n", new_total_cost); } } @@ -400,7 +190,7 @@ void SerialConnectionRouter::timing_driven_expand_neighbours(const RTExplo /* Puts all the rr_nodes adjacent to current on the heap. */ // For each node associated with the current heap element, expand all of it's neighbors - auto edges = rr_nodes_.edge_range(current.index); + auto edges = this->rr_nodes_.edge_range(current.index); // This is a simple prefetch that prefetches: // - RR node data reachable from this node @@ -420,15 +210,15 @@ void SerialConnectionRouter::timing_driven_expand_neighbours(const RTExplo // - gsm_switch_stratixiv_arch_timing.blif // for (RREdgeId from_edge : edges) { - RRNodeId to_node = rr_nodes_.edge_sink_node(from_edge); - rr_nodes_.prefetch_node(to_node); + RRNodeId to_node = this->rr_nodes_.edge_sink_node(from_edge); + this->rr_nodes_.prefetch_node(to_node); - int switch_idx = rr_nodes_.edge_switch(from_edge); - VTR_PREFETCH(&rr_switch_inf_[switch_idx], 0, 0); + int switch_idx = this->rr_nodes_.edge_switch(from_edge); + VTR_PREFETCH(&this->rr_switch_inf_[switch_idx], 0, 0); } for (RREdgeId from_edge : edges) { - RRNodeId to_node = rr_nodes_.edge_sink_node(from_edge); + RRNodeId to_node = this->rr_nodes_.edge_sink_node(from_edge); timing_driven_expand_neighbour(current, from_edge, to_node, @@ -458,14 +248,14 @@ void SerialConnectionRouter::timing_driven_expand_neighbour(const RTExplor // Disable BB-pruning if RCV is enabled, as this can make it harder for circuits with high negative hold slack to resolve this // TODO: Only disable pruning if the net has negative hold slack, maybe go off budgets if (!inside_bb(to_node, bounding_box) - && !rcv_path_manager.is_enabled()) { - VTR_LOGV_DEBUG(router_debug_, + && !this->rcv_path_manager.is_enabled()) { + VTR_LOGV_DEBUG(this->router_debug_, " Pruned expansion of node %d edge %zu -> %d" " (to node location %d,%d,%d x %d,%d,%d outside of expanded" " net bounding box %d,%d,%d x %d,%d,%d)\n", from_node, size_t(from_edge), size_t(to_node), - rr_graph_->node_xlow(to_node), rr_graph_->node_ylow(to_node), rr_graph_->node_layer(to_node), - rr_graph_->node_xhigh(to_node), rr_graph_->node_yhigh(to_node), rr_graph_->node_layer(to_node), + this->rr_graph_->node_xlow(to_node), this->rr_graph_->node_ylow(to_node), this->rr_graph_->node_layer(to_node), + this->rr_graph_->node_xhigh(to_node), this->rr_graph_->node_yhigh(to_node), this->rr_graph_->node_layer(to_node), bounding_box.xmin, bounding_box.ymin, bounding_box.layer_min, bounding_box.xmax, bounding_box.ymax, bounding_box.layer_max); return; /* Node is outside (expanded) bounding box. */ @@ -476,22 +266,22 @@ void SerialConnectionRouter::timing_driven_expand_neighbour(const RTExplor * more promising routes, but makes route-through (via CLBs) impossible. * * Change this if you want to investigate route-throughs. */ if (target_node != RRNodeId::INVALID()) { - t_rr_type to_type = rr_graph_->node_type(to_node); + t_rr_type to_type = this->rr_graph_->node_type(to_node); if (to_type == IPIN) { // Check if this IPIN leads to the target block // IPIN's of the target block should be contained within it's bounding box - int to_xlow = rr_graph_->node_xlow(to_node); - int to_ylow = rr_graph_->node_ylow(to_node); - int to_layer = rr_graph_->node_layer(to_node); - int to_xhigh = rr_graph_->node_xhigh(to_node); - int to_yhigh = rr_graph_->node_yhigh(to_node); + int to_xlow = this->rr_graph_->node_xlow(to_node); + int to_ylow = this->rr_graph_->node_ylow(to_node); + int to_layer = this->rr_graph_->node_layer(to_node); + int to_xhigh = this->rr_graph_->node_xhigh(to_node); + int to_yhigh = this->rr_graph_->node_yhigh(to_node); if (to_xlow < target_bb.xmin || to_ylow < target_bb.ymin || to_xhigh > target_bb.xmax || to_yhigh > target_bb.ymax || to_layer < target_bb.layer_min || to_layer > target_bb.layer_max) { - VTR_LOGV_DEBUG(router_debug_, + VTR_LOGV_DEBUG(this->router_debug_, " Pruned expansion of node %d edge %zu -> %d" " (to node is IPIN at %d,%d,%d x %d,%d,%d which does not" " lead to target block %d,%d,%d x %d,%d,%d)\n", @@ -505,18 +295,18 @@ void SerialConnectionRouter::timing_driven_expand_neighbour(const RTExplor } } - VTR_LOGV_DEBUG(router_debug_, " Expanding node %d edge %zu -> %d\n", + VTR_LOGV_DEBUG(this->router_debug_, " Expanding node %d edge %zu -> %d\n", from_node, size_t(from_edge), size_t(to_node)); // Check if the node exists in the route tree when RCV is enabled // Other pruning methods have been disabled when RCV is on, so this method is required to prevent "loops" from being created bool node_exists = false; - if (rcv_path_manager.is_enabled()) { - node_exists = rcv_path_manager.node_exists_in_tree(rcv_path_data[from_node], - to_node); + if (this->rcv_path_manager.is_enabled()) { + node_exists = this->rcv_path_manager.node_exists_in_tree(this->rcv_path_data[from_node], + to_node); } - if (!node_exists || !rcv_path_manager.is_enabled()) { + if (!node_exists || !this->rcv_path_manager.is_enabled()) { timing_driven_add_to_heap(cost_params, current, to_node, @@ -544,20 +334,17 @@ void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_p next.backward_path_cost = current.backward_path_cost; // Initalize RCV data struct if needed, otherwise it's set to nullptr - rcv_path_manager.alloc_path_struct(next.path_data); + this->rcv_path_manager.alloc_path_struct(next.path_data); // path_data variables are initialized to current values - if (rcv_path_manager.is_enabled() && rcv_path_data[from_node]) { - next.path_data->backward_cong = rcv_path_data[from_node]->backward_cong; - next.path_data->backward_delay = rcv_path_data[from_node]->backward_delay; + if (this->rcv_path_manager.is_enabled() && this->rcv_path_data[from_node]) { + next.path_data->backward_cong = this->rcv_path_data[from_node]->backward_cong; + next.path_data->backward_delay = this->rcv_path_data[from_node]->backward_delay; } - evaluate_timing_driven_node_costs(&next, - cost_params, - from_node, - target_node); + this->evaluate_timing_driven_node_costs(&next, cost_params, from_node, target_node); - float best_total_cost = rr_node_route_inf_[to_node].path_cost; - float best_back_cost = rr_node_route_inf_[to_node].backward_path_cost; + float best_total_cost = this->rr_node_route_inf_[to_node].path_cost; + float best_back_cost = this->rr_node_route_inf_[to_node].backward_path_cost; float new_total_cost = next.total_cost; float new_back_cost = next.backward_path_cost; @@ -573,15 +360,15 @@ void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_p // When RCV is enabled, prune based on the RCV-specific total path cost (see // in `compute_node_cost_using_rcv` in `evaluate_timing_driven_node_costs`) // to allow detours to get better QoR. - if ((!rcv_path_manager.is_enabled() && best_back_cost > new_back_cost) || (rcv_path_manager.is_enabled() && best_total_cost > new_total_cost)) { - VTR_LOGV_DEBUG(router_debug_, " Expanding to node %d (%s)\n", to_node, + if ((!this->rcv_path_manager.is_enabled() && best_back_cost > new_back_cost) || (this->rcv_path_manager.is_enabled() && best_total_cost > new_total_cost)) { + VTR_LOGV_DEBUG(this->router_debug_, " Expanding to node %d (%s)\n", to_node, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to_node, - is_flat_) + this->is_flat_) .c_str()); - VTR_LOGV_DEBUG(router_debug_, " New Total Cost %g New back Cost %g\n", new_total_cost, new_back_cost); + VTR_LOGV_DEBUG(this->router_debug_, " New Total Cost %g New back Cost %g\n", new_total_cost, new_back_cost); //Add node to the heap only if the cost via the current partial path is less than the //best known cost, since there is no reason for the router to expand more expensive paths. // @@ -590,253 +377,29 @@ void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_p update_cheapest(next, from_node); - heap_.add_to_heap({new_total_cost, to_node}); - update_router_stats(router_stats_, + this->heap_.add_to_heap({new_total_cost, to_node}); + update_router_stats(this->router_stats_, /*is_push=*/true, to_node, - rr_graph_); + this->rr_graph_); } else { - VTR_LOGV_DEBUG(router_debug_, " Didn't expand to %d (%s)\n", to_node, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to_node, is_flat_).c_str()); - VTR_LOGV_DEBUG(router_debug_, " Prev Total Cost %g Prev back Cost %g \n", best_total_cost, best_back_cost); - VTR_LOGV_DEBUG(router_debug_, " New Total Cost %g New back Cost %g \n", new_total_cost, new_back_cost); - } - - if (rcv_path_manager.is_enabled() && next.path_data != nullptr) { - rcv_path_manager.free_path_struct(next.path_data); + VTR_LOGV_DEBUG(this->router_debug_, " Didn't expand to %d (%s)\n", to_node, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to_node, this->is_flat_).c_str()); + VTR_LOGV_DEBUG(this->router_debug_, " Prev Total Cost %g Prev back Cost %g \n", best_total_cost, best_back_cost); + VTR_LOGV_DEBUG(this->router_debug_, " New Total Cost %g New back Cost %g \n", new_total_cost, new_back_cost); } -} - -#ifdef VTR_ASSERT_SAFE_ENABLED - -//Returns true if both nodes are part of the same non-configurable edge set -static bool same_non_config_node_set(RRNodeId from_node, RRNodeId to_node) { - auto& device_ctx = g_vpr_ctx.device(); - auto from_itr = device_ctx.rr_node_to_non_config_node_set.find(from_node); - auto to_itr = device_ctx.rr_node_to_non_config_node_set.find(to_node); - - if (from_itr == device_ctx.rr_node_to_non_config_node_set.end() - || to_itr == device_ctx.rr_node_to_non_config_node_set.end()) { - return false; //Not part of a non-config node set + if (this->rcv_path_manager.is_enabled() && next.path_data != nullptr) { + this->rcv_path_manager.free_path_struct(next.path_data); } - - return from_itr->second == to_itr->second; //Check for same non-config set IDs -} - -#endif - -template -float SerialConnectionRouter::compute_node_cost_using_rcv(const t_conn_cost_params cost_params, - RRNodeId to_node, - RRNodeId target_node, - float backwards_delay, - float backwards_cong, - float R_upstream) { - float expected_delay; - float expected_cong; - - const t_conn_delay_budget* delay_budget = cost_params.delay_budget; - // TODO: This function is not tested for is_flat == true - VTR_ASSERT(is_flat_ != true); - std::tie(expected_delay, expected_cong) = router_lookahead_.get_expected_delay_and_cong(to_node, target_node, cost_params, R_upstream); - - float expected_total_delay_cost; - float expected_total_cong_cost; - - float expected_total_cong = expected_cong + backwards_cong; - float expected_total_delay = expected_delay + backwards_delay; - - //If budgets specified calculate cost as described by RCV paper: - // R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While - // Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of - // Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008. - - // Normalization constant defined in RCV paper cited above - constexpr float NORMALIZATION_CONSTANT = 100e-12; - - expected_total_delay_cost = expected_total_delay; - expected_total_delay_cost += (delay_budget->short_path_criticality + cost_params.criticality) * std::max(0.f, delay_budget->target_delay - expected_total_delay); - // expected_total_delay_cost += std::pow(std::max(0.f, expected_total_delay - delay_budget->max_delay), 2) / NORMALIZATION_CONSTANT; - expected_total_delay_cost += std::pow(std::max(0.f, delay_budget->min_delay - expected_total_delay), 2) / NORMALIZATION_CONSTANT; - expected_total_cong_cost = expected_total_cong; - - float total_cost = expected_total_delay_cost + expected_total_cong_cost; - - return total_cost; -} - -// Empty the route tree set node, use this after each net is routed -template -void SerialConnectionRouter::empty_rcv_route_tree_set() { - rcv_path_manager.empty_route_tree_nodes(); } // Enable or disable RCV template void SerialConnectionRouter::set_rcv_enabled(bool enable) { - rcv_path_manager.set_enabled(enable); + this->rcv_path_manager.set_enabled(enable); if (enable) { - rcv_path_data.resize(rr_node_route_inf_.size()); - } -} - -//Calculates the cost of reaching to_node (i.e., to->index) -template -void SerialConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, - const t_conn_cost_params& cost_params, - RRNodeId from_node, - RRNodeId target_node) { - /* new_costs.backward_cost: is the "known" part of the cost to this node -- the - * congestion cost of all the routing resources back to the existing route - * plus the known delay of the total path back to the source. - * - * new_costs.total_cost: is this "known" backward cost + an expected cost to get to the target. - * - * new_costs.R_upstream: is the upstream resistance at the end of this node - */ - - //Info for the switch connecting from_node to_node (i.e., to->index) - int iswitch = rr_nodes_.edge_switch(to->prev_edge); - bool switch_buffered = rr_switch_inf_[iswitch].buffered(); - bool reached_configurably = rr_switch_inf_[iswitch].configurable(); - float switch_R = rr_switch_inf_[iswitch].R; - float switch_Tdel = rr_switch_inf_[iswitch].Tdel; - float switch_Cinternal = rr_switch_inf_[iswitch].Cinternal; - - //To node info - auto rc_index = rr_graph_->node_rc_index(to->index); - float node_C = rr_rc_data_[rc_index].C; - float node_R = rr_rc_data_[rc_index].R; - - //From node info - float from_node_R = rr_rc_data_[rr_graph_->node_rc_index(from_node)].R; - - //Update R_upstream - if (switch_buffered) { - to->R_upstream = 0.; //No upstream resistance - } else { - //R_Upstream already initialized - } - - to->R_upstream += switch_R; //Switch resistance - to->R_upstream += node_R; //Node resistance - - //Calculate delay - float Rdel = to->R_upstream - 0.5 * node_R; //Only consider half node's resistance for delay - float Tdel = switch_Tdel + Rdel * node_C; - - //Depending on the switch used, the Tdel of the upstream node (from_node) may change due to - //increased loading from the switch's internal capacitance. - // - //Even though this delay physically affects from_node, we make the adjustment (now) on the to_node, - //since only once we've reached to to_node do we know the connection used (and the switch enabled). - // - //To adjust for the time delay, we compute the product of the Rdel associated with from_node and - //the internal capacitance of the switch. - // - //First, we will calculate Rdel_adjust (just like in the computation for Rdel, we consider only - //half of from_node's resistance). - float Rdel_adjust = to->R_upstream - 0.5 * from_node_R; - - //Second, we adjust the Tdel to account for the delay caused by the internal capacitance. - Tdel += Rdel_adjust * switch_Cinternal; - - float cong_cost = 0.; - if (reached_configurably) { - cong_cost = get_rr_cong_cost(to->index, cost_params.pres_fac); - } else { - //Reached by a non-configurable edge. - //Therefore the from_node and to_node are part of the same non-configurable node set. -#ifdef VTR_ASSERT_SAFE_ENABLED - VTR_ASSERT_SAFE_MSG(same_non_config_node_set(from_node, to->index), - "Non-configurably connected edges should be part of the same node set"); -#endif - - //The congestion cost of all nodes in the set has already been accounted for (when - //the current path first expanded a node in the set). Therefore do *not* re-add the congestion - //cost. - cong_cost = 0.; - } - if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == IPIN) { - auto find_res = conn_params_->connection_choking_spots_.find(to->index); - if (find_res != conn_params_->connection_choking_spots_.end()) { - cong_cost = cong_cost / pow(2, (float)find_res->second); - } - } - - //Update the backward cost (upstream already included) - to->backward_path_cost += (1. - cost_params.criticality) * cong_cost; //Congestion cost - to->backward_path_cost += cost_params.criticality * Tdel; //Delay cost - - if (cost_params.bend_cost != 0.) { - t_rr_type from_type = rr_graph_->node_type(from_node); - t_rr_type to_type = rr_graph_->node_type(to->index); - if ((from_type == CHANX && to_type == CHANY) || (from_type == CHANY && to_type == CHANX)) { - to->backward_path_cost += cost_params.bend_cost; //Bend cost - } - } - - float total_cost = 0.; - - if (rcv_path_manager.is_enabled() && to->path_data != nullptr) { - to->path_data->backward_delay += cost_params.criticality * Tdel; - to->path_data->backward_cong += (1. - cost_params.criticality) * get_rr_cong_cost(to->index, cost_params.pres_fac); - - total_cost = compute_node_cost_using_rcv(cost_params, to->index, target_node, to->path_data->backward_delay, to->path_data->backward_cong, to->R_upstream); - } else { - const auto& device_ctx = g_vpr_ctx.device(); - //Update total cost - float expected_cost = router_lookahead_.get_expected_cost(to->index, target_node, cost_params, to->R_upstream); - VTR_LOGV_DEBUG(router_debug_ && !std::isfinite(expected_cost), - " Lookahead from %s (%s) to %s (%s) is non-finite, expected_cost = %f, to->R_upstream = %f\n", - rr_node_arch_name(to->index, is_flat_).c_str(), - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to->index, is_flat_).c_str(), - rr_node_arch_name(target_node, is_flat_).c_str(), - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, target_node, is_flat_).c_str(), - expected_cost, to->R_upstream); - total_cost += to->backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); - } - to->total_cost = total_cost; -} - -//Adds the route tree rooted at rt_node to the heap, preparing it to be -//used as branch-points for further routing. -template -void SerialConnectionRouter::add_route_tree_to_heap( - const RouteTreeNode& rt_node, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bb) { - /* Puts the entire partial routing below and including rt_node onto the heap * - * (except for those parts marked as not to be expanded) by calling itself * - * recursively. */ - - /* Pre-order depth-first traversal */ - // IPINs and SINKS are not re_expanded - if (rt_node.re_expand) { - add_route_tree_node_to_heap(rt_node, - target_node, - cost_params, - net_bb); - } - - for (const RouteTreeNode& child_node : rt_node.child_nodes()) { - if (is_flat_) { - if (relevant_node_to_target(rr_graph_, - child_node.inode, - target_node)) { - add_route_tree_to_heap(child_node, - target_node, - cost_params, - net_bb); - } - } else { - add_route_tree_to_heap(child_node, - target_node, - cost_params, - net_bb); - } + this->rcv_path_data.resize(this->rr_node_route_inf_.size()); } } @@ -865,222 +428,53 @@ void SerialConnectionRouter::add_route_tree_node_to_heap( * Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008.*/ // float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); - if (!rcv_path_manager.is_enabled()) { + if (!this->rcv_path_manager.is_enabled()) { // tot_cost = backward_path_cost + cost_params.astar_fac * expected_cost; - float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); + float expected_cost = this->router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); float tot_cost = backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); - VTR_LOGV_DEBUG(router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", + VTR_LOGV_DEBUG(this->router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", inode, tot_cost, - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, is_flat_).c_str()); + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, this->is_flat_).c_str()); - if (tot_cost > rr_node_route_inf_[inode].path_cost) { + if (tot_cost > this->rr_node_route_inf_[inode].path_cost) { return; } add_to_mod_list(inode); - rr_node_route_inf_[inode].path_cost = tot_cost; - rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); - rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; - rr_node_route_inf_[inode].R_upstream = R_upstream; - heap_.push_back({tot_cost, inode}); + this->rr_node_route_inf_[inode].path_cost = tot_cost; + this->rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); + this->rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; + this->rr_node_route_inf_[inode].R_upstream = R_upstream; + this->heap_.push_back({tot_cost, inode}); - // push_back_node(&heap_, rr_node_route_inf_, + // push_back_node(&this->heap_, this->rr_node_route_inf_, // inode, tot_cost, RREdgeId::INVALID(), // backward_path_cost, R_upstream); } else { - float expected_total_cost = compute_node_cost_using_rcv(cost_params, inode, target_node, rt_node.Tdel, 0, R_upstream); + float expected_total_cost = this->compute_node_cost_using_rcv(cost_params, inode, target_node, rt_node.Tdel, 0, R_upstream); add_to_mod_list(inode); - rr_node_route_inf_[inode].path_cost = expected_total_cost; - rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); - rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; - rr_node_route_inf_[inode].R_upstream = R_upstream; + this->rr_node_route_inf_[inode].path_cost = expected_total_cost; + this->rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); + this->rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; + this->rr_node_route_inf_[inode].R_upstream = R_upstream; - rcv_path_manager.alloc_path_struct(rcv_path_data[inode]); - rcv_path_data[inode]->backward_delay = rt_node.Tdel; + this->rcv_path_manager.alloc_path_struct(this->rcv_path_data[inode]); + this->rcv_path_data[inode]->backward_delay = rt_node.Tdel; - heap_.push_back({expected_total_cost, inode}); + this->heap_.push_back({expected_total_cost, inode}); - // push_back_node_with_info(&heap_, inode, expected_total_cost, - // backward_path_cost, R_upstream, rt_node.Tdel, &rcv_path_manager); + // push_back_node_with_info(&this->heap_, inode, expected_total_cost, + // backward_path_cost, R_upstream, rt_node.Tdel, &this->rcv_path_manager); } - update_router_stats(router_stats_, + update_router_stats(this->router_stats_, /*is_push=*/true, inode, - rr_graph_); - - if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - router_stats_->rt_node_pushes[rr_graph_->node_type(inode)]++; - } -} - -/* Expand bb by inode's extents and clip against net_bb */ -inline void expand_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb, RRNodeId inode, const RRGraphView* rr_graph) { - bb.xmin = std::max(net_bb.xmin, std::min(bb.xmin, rr_graph->node_xlow(inode))); - bb.ymin = std::max(net_bb.ymin, std::min(bb.ymin, rr_graph->node_ylow(inode))); - bb.xmax = std::min(net_bb.xmax, std::max(bb.xmax, rr_graph->node_xhigh(inode))); - bb.ymax = std::min(net_bb.ymax, std::max(bb.ymax, rr_graph->node_yhigh(inode))); - bb.layer_min = std::min(bb.layer_min, rr_graph->node_layer(inode)); - bb.layer_max = std::max(bb.layer_max, rr_graph->node_layer(inode)); -} - -/* Expand bb by HIGH_FANOUT_BB_FAC and clip against net_bb */ -inline void adjust_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb) { - constexpr int HIGH_FANOUT_BB_FAC = 3; - - bb.xmin = std::max(net_bb.xmin, bb.xmin - HIGH_FANOUT_BB_FAC); - bb.ymin = std::max(net_bb.ymin, bb.ymin - HIGH_FANOUT_BB_FAC); - bb.xmax = std::min(net_bb.xmax, bb.xmax + HIGH_FANOUT_BB_FAC); - bb.ymax = std::min(net_bb.ymax, bb.ymax + HIGH_FANOUT_BB_FAC); - bb.layer_min = std::min(net_bb.layer_min, bb.layer_min); - bb.layer_max = std::max(net_bb.layer_max, bb.layer_max); -} - -template -t_bb SerialConnectionRouter::add_high_fanout_route_tree_to_heap( - const RouteTreeNode& rt_root, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const SpatialRouteTreeLookup& spatial_rt_lookup, - const t_bb& net_bounding_box) { - //For high fanout nets we only add those route tree nodes which are spatially close - //to the sink. - // - //Based on: - // J. Swartz, V. Betz, J. Rose, "A Fast Routability-Driven Router for FPGAs", FPGA, 1998 - // - //We rely on a grid-based spatial look-up which is maintained for high fanout nets by - //update_route_tree(), which allows us to add spatially close route tree nodes without traversing - //the entire route tree (which is likely large for a high fanout net). - - //Determine which bin the target node is located in - - int target_bin_x = grid_to_bin_x(rr_graph_->node_xlow(target_node), spatial_rt_lookup); - int target_bin_y = grid_to_bin_y(rr_graph_->node_ylow(target_node), spatial_rt_lookup); - - auto target_layer = rr_graph_->node_layer(target_node); - - int chan_nodes_added = 0; - - t_bb highfanout_bb; - highfanout_bb.xmin = rr_graph_->node_xlow(target_node); - highfanout_bb.xmax = rr_graph_->node_xhigh(target_node); - highfanout_bb.ymin = rr_graph_->node_ylow(target_node); - highfanout_bb.ymax = rr_graph_->node_yhigh(target_node); - highfanout_bb.layer_min = target_layer; - highfanout_bb.layer_max = target_layer; - - //Add existing routing starting from the target bin. - //If the target's bin has insufficient existing routing add from the surrounding bins - constexpr int SINGLE_BIN_MIN_NODES = 2; - bool done = false; - bool found_node_on_same_layer = false; - for (int dx : {0, -1, +1}) { - size_t bin_x = target_bin_x + dx; - - if (bin_x > spatial_rt_lookup.dim_size(0) - 1) continue; //Out of range - - for (int dy : {0, -1, +1}) { - size_t bin_y = target_bin_y + dy; - - if (bin_y > spatial_rt_lookup.dim_size(1) - 1) continue; //Out of range - - for (const RouteTreeNode& rt_node : spatial_rt_lookup[bin_x][bin_y]) { - if (!rt_node.re_expand) // Some nodes (like IPINs) shouldn't be re-expanded - continue; - RRNodeId rr_node_to_add = rt_node.inode; - - /* Flat router: don't go into clusters other than the target one */ - if (is_flat_) { - if (!relevant_node_to_target(rr_graph_, rr_node_to_add, target_node)) - continue; - } - - /* In case of the parallel router, we may be dealing with a virtual net - * so prune the nodes from the HF lookup against the bounding box just in case */ - if (!inside_bb(rr_node_to_add, net_bounding_box)) - continue; - - auto rt_node_layer_num = rr_graph_->node_layer(rr_node_to_add); - if (rt_node_layer_num == target_layer) - found_node_on_same_layer = true; - - // Put the node onto the heap - add_route_tree_node_to_heap(rt_node, target_node, cost_params, net_bounding_box); - - // Expand HF BB to include the node (clip by original BB) - expand_highfanout_bounding_box(highfanout_bb, net_bounding_box, rr_node_to_add, rr_graph_); - - if (rr_graph_->node_type(rr_node_to_add) == CHANY || rr_graph_->node_type(rr_node_to_add) == CHANX) { - chan_nodes_added++; - } - } - - if (dx == 0 && dy == 0 && chan_nodes_added > SINGLE_BIN_MIN_NODES && found_node_on_same_layer) { - //Target bin contained at least minimum amount of routing - // - //We require at least SINGLE_BIN_MIN_NODES to be added. - //This helps ensure we don't end up with, for example, a single - //routing wire running in the wrong direction which may not be - //able to reach the target within the bounding box. - done = true; - break; - } - } - if (done) break; - } - /* If we didn't find enough nodes to branch off near the target - * or they are on the wrong grid layer, just add the full route tree */ - if (chan_nodes_added <= SINGLE_BIN_MIN_NODES || !found_node_on_same_layer) { - add_route_tree_to_heap(rt_root, target_node, cost_params, net_bounding_box); - return net_bounding_box; - } else { - //We found nearby routing, replace original bounding box to be localized around that routing - adjust_highfanout_bounding_box(highfanout_bb, net_bounding_box); - return highfanout_bb; - } -} - -static inline bool relevant_node_to_target(const RRGraphView* rr_graph, - RRNodeId node_to_add, - RRNodeId target_node) { - VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == t_rr_type::SINK); - auto node_to_add_type = rr_graph->node_type(node_to_add); - return node_to_add_type != t_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); -} - -static inline void update_router_stats(RouterStats* router_stats, - bool is_push, - RRNodeId rr_node_id, - const RRGraphView* rr_graph) { - if (is_push) { - router_stats->heap_pushes++; - } else { - router_stats->heap_pops++; - } + this->rr_graph_); if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - auto node_type = rr_graph->node_type(rr_node_id); - VTR_ASSERT(node_type != NUM_RR_TYPES); - - if (is_inter_cluster_node(*rr_graph, rr_node_id)) { - if (is_push) { - router_stats->inter_cluster_node_pushes++; - router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; - } else { - router_stats->inter_cluster_node_pops++; - router_stats->inter_cluster_node_type_cnt_pops[node_type]++; - } - } else { - if (is_push) { - router_stats->intra_cluster_node_pushes++; - router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; - } else { - router_stats->intra_cluster_node_pops++; - router_stats->intra_cluster_node_type_cnt_pops[node_type]++; - } - } + this->router_stats_->rt_node_pushes[this->rr_graph_->node_type(inode)]++; } } diff --git a/vpr/src/route/serial_connection_router.h b/vpr/src/route/serial_connection_router.h index 413cc228f22..b0cc6e5c7f5 100644 --- a/vpr/src/route/serial_connection_router.h +++ b/vpr/src/route/serial_connection_router.h @@ -1,14 +1,7 @@ #ifndef _SERIAL_CONNECTION_ROUTER_H #define _SERIAL_CONNECTION_ROUTER_H -#include "connection_router_interface.h" -#include "rr_graph_storage.h" -#include "route_common.h" -#include "router_lookahead.h" -#include "route_tree.h" -#include "rr_rc_data.h" -#include "router_stats.h" -#include "spatial_route_tree_lookup.h" +#include "connection_router.h" #include "d_ary_heap.h" @@ -21,7 +14,7 @@ // node (which is returned) through the rr_node_route_inf. See // update_traceback as an example of this tracing. template -class SerialConnectionRouter : public ConnectionRouterInterface { +class SerialConnectionRouter : public ConnectionRouter { public: SerialConnectionRouter( const DeviceGrid& grid, @@ -32,81 +25,32 @@ class SerialConnectionRouter : public ConnectionRouterInterface { const vtr::vector& rr_switch_inf, vtr::vector& rr_node_route_inf, bool is_flat) - : grid_(grid) - , router_lookahead_(router_lookahead) - , rr_nodes_(rr_nodes.view()) - , rr_graph_(rr_graph) - , rr_rc_data_(rr_rc_data.data(), rr_rc_data.size()) - , rr_switch_inf_(rr_switch_inf.data(), rr_switch_inf.size()) - , net_terminal_groups(g_vpr_ctx.routing().net_terminal_groups) - , net_terminal_group_num(g_vpr_ctx.routing().net_terminal_group_num) - , rr_node_route_inf_(rr_node_route_inf) - , is_flat_(is_flat) - , router_stats_(nullptr) - , router_debug_(false) - , path_search_cumulative_time(0) { - heap_.init_heap(grid); - only_opin_inter_layer = (grid.get_num_layers() > 1) && inter_layer_connections_limited_to_opin(*rr_graph); + : ConnectionRouter(grid, router_lookahead, rr_nodes, rr_graph, rr_rc_data, rr_switch_inf, rr_node_route_inf, is_flat) { } ~SerialConnectionRouter() { VTR_LOG("Serial Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", - std::chrono::duration(path_search_cumulative_time).count()); + std::chrono::duration(this->path_search_cumulative_time).count()); } // Clear's the modified list. Should be called after reset_path_costs // have been called. void clear_modified_rr_node_info() final { - modified_rr_node_inf_.clear(); + this->modified_rr_node_inf_.clear(); } // Reset modified data in rr_node_route_inf based on modified_rr_node_inf. void reset_path_costs() final { // Reset the node info stored in rr_node_route_inf variable - ::reset_path_costs(modified_rr_node_inf_); + ::reset_path_costs(this->modified_rr_node_inf_); // Reset the node info stored inside the connection router - if (rcv_path_manager.is_enabled()) { - for (const auto& node : modified_rr_node_inf_) { - rcv_path_data[node] = nullptr; + if (this->rcv_path_manager.is_enabled()) { + for (const auto& node : this->modified_rr_node_inf_) { + this->rcv_path_data[node] = nullptr; } } } - /** Finds a path from the route tree rooted at rt_root to sink_node. - * This is used when you want to allow previous routing of the same net to - * serve as valid start locations for the current connection. - * - * Returns a tuple of: - * bool: path exists? (hard failure, rr graph disconnected) - * bool: should retry with full bounding box? (only used in parallel routing) - * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ - std::tuple timing_driven_route_connection_from_route_tree( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RouterStats& router_stats, - const ConnectionParameters& conn_params) final; - - /** Finds a path from the route tree rooted at rt_root to sink_node for a - * high fanout net. - * - * Unlike timing_driven_route_connection_from_route_tree(), only part of - * the route tree which is spatially close to the sink is added to the heap. - * - * Returns a tuple of: - * bool: path exists? (hard failure, rr graph disconnected) - * bool: should retry with full bounding box? (only used in parallel routing) - * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ - std::tuple timing_driven_route_connection_from_route_tree_high_fanout( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bounding_box, - const SpatialRouteTreeLookup& spatial_rt_lookup, - RouterStats& router_stats, - const ConnectionParameters& conn_params) final; - // Finds a path from the route tree rooted at rt_root to all sinks // available. // @@ -126,27 +70,18 @@ class SerialConnectionRouter : public ConnectionRouterInterface { RouterStats& router_stats, const ConnectionParameters& conn_params) final; - void set_router_debug(bool router_debug) final { - router_debug_ = router_debug; - } - - // Empty the route tree set used for RCV node detection - // Will return if RCV is disabled - // Called after each net is finished routing to flush the set - void empty_rcv_route_tree_set() final; - // Enable or disable RCV in connection router // Enabling this will utilize extra path structures, as well as the RCV cost function // // Ensure route budgets have been calculated before enabling this void set_rcv_enabled(bool enable) final; - private: + protected: // Mark that data associated with rr_node "inode" has been modified, and // needs to be reset in reset_path_costs. - void add_to_mod_list(RRNodeId inode) { - if (std::isinf(rr_node_route_inf_[inode].path_cost)) { - modified_rr_node_inf_.push_back(inode); + inline void add_to_mod_list(RRNodeId inode) { + if (std::isinf(this->rr_node_route_inf_[inode].path_cost)) { + this->modified_rr_node_inf_.push_back(inode); } } @@ -155,50 +90,26 @@ class SerialConnectionRouter : public ConnectionRouterInterface { inline void update_cheapest(RTExploredNode& cheapest, const RRNodeId& from_node) { const RRNodeId& inode = cheapest.index; add_to_mod_list(inode); - rr_node_route_inf_[inode].prev_edge = cheapest.prev_edge; - rr_node_route_inf_[inode].path_cost = cheapest.total_cost; - rr_node_route_inf_[inode].backward_path_cost = cheapest.backward_path_cost; + this->rr_node_route_inf_[inode].prev_edge = cheapest.prev_edge; + this->rr_node_route_inf_[inode].path_cost = cheapest.total_cost; + this->rr_node_route_inf_[inode].backward_path_cost = cheapest.backward_path_cost; // Use the already created next path structure pointer when RCV is enabled - if (rcv_path_manager.is_enabled()) { - rcv_path_manager.move(rcv_path_data[inode], cheapest.path_data); + if (this->rcv_path_manager.is_enabled()) { + this->rcv_path_manager.move(this->rcv_path_data[inode], cheapest.path_data); - rcv_path_data[inode]->path_rr = rcv_path_data[from_node]->path_rr; - rcv_path_data[inode]->edge = rcv_path_data[from_node]->edge; - rcv_path_data[inode]->path_rr.push_back(from_node); - rcv_path_data[inode]->edge.push_back(cheapest.prev_edge); + this->rcv_path_data[inode]->path_rr = this->rcv_path_data[from_node]->path_rr; + this->rcv_path_data[inode]->edge = this->rcv_path_data[from_node]->edge; + this->rcv_path_data[inode]->path_rr.push_back(from_node); + this->rcv_path_data[inode]->edge.push_back(cheapest.prev_edge); } } - /** Common logic from timing_driven_route_connection_from_route_tree and - * timing_driven_route_connection_from_route_tree_high_fanout for running - * the connection router. - * @param[in] rt_root RouteTreeNode describing the current routing state - * @param[in] sink_node Sink node ID to route to - * @param[in] cost_params - * @param[in] bounding_box Keep search confined to this bounding box - * @return bool Signal to retry this connection with a full-device bounding box */ - bool timing_driven_route_connection_common_setup( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box); - - // Finds a path to sink_node, starting from the elements currently in the - // heap. - // - // If the path is not found, which means that the path_cost of sink_node in - // RR node route info has never been updated, `rr_node_route_inf_[sink_node] - // .path_cost` will be the initial value (i.e., float infinity). This case - // can be detected by `std::isinf(rr_node_route_inf_[sink_node].path_cost)`. - // - // This is the core maze routing routine. - // - // Note: For understanding the connection router, start here. - void timing_driven_route_connection_from_heap( - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box); + // Find the shortest path from current heap to the sink node in the RR graph + void timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) final; // Expand this current node if it is a cheaper path. void timing_driven_expand_cheapest( @@ -240,33 +151,7 @@ class SerialConnectionRouter : public ConnectionRouterInterface { RREdgeId from_edge, RRNodeId target_node); - // Calculates the cost of reaching to_node - void evaluate_timing_driven_node_costs( - RTExploredNode* to, - const t_conn_cost_params& cost_params, - RRNodeId from_node, - RRNodeId target_node); - - // Find paths from current heap to all nodes in the RR graph - vtr::vector timing_driven_find_all_shortest_paths_from_heap( - const t_conn_cost_params& cost_params, - const t_bb& bounding_box); - - //Adds the route tree rooted at rt_node to the heap, preparing it to be - //used as branch-points for further routing. - void add_route_tree_to_heap(const RouteTreeNode& rt_node, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bb); - - // Evaluate node costs using the RCV algorith - float compute_node_cost_using_rcv(const t_conn_cost_params cost_params, - RRNodeId to_node, - RRNodeId target_node, - float backwards_delay, - float backwards_cong, - float R_upstream); - + // TODO: move this function into ConnectionRouter class //Unconditionally adds rt_node to the heap // //Note that if you want to respect rt_node->re_expand that is the caller's @@ -277,38 +162,10 @@ class SerialConnectionRouter : public ConnectionRouterInterface { const t_conn_cost_params& cost_params, const t_bb& net_bb); - t_bb add_high_fanout_route_tree_to_heap( - const RouteTreeNode& rt_root, - RRNodeId target_node, + // Find paths from current heap to all nodes in the RR graph + vtr::vector timing_driven_find_all_shortest_paths_from_heap( const t_conn_cost_params& cost_params, - const SpatialRouteTreeLookup& spatial_route_tree_lookup, - const t_bb& net_bounding_box); - - const DeviceGrid& grid_; - const RouterLookahead& router_lookahead_; - const t_rr_graph_view rr_nodes_; - const RRGraphView* rr_graph_; - vtr::array_view rr_rc_data_; - vtr::array_view rr_switch_inf_; - const vtr::vector>>& net_terminal_groups; - const vtr::vector>& net_terminal_group_num; - vtr::vector& rr_node_route_inf_; - bool is_flat_; - std::vector modified_rr_node_inf_; - RouterStats* router_stats_; - const ConnectionParameters* conn_params_; - HeapImplementation heap_; - bool router_debug_; - - bool only_opin_inter_layer; - - // Cumulative time spent in the path search part of the connection router. - std::chrono::microseconds path_search_cumulative_time; - - // The path manager for RCV, keeps track of the route tree as a set, also - // manages the allocation of `rcv_path_data`. - PathManager rcv_path_manager; - vtr::vector rcv_path_data; + const t_bb& bounding_box) final; }; /** Construct a serial connection router that uses the specified heap type. From fe5cad854a1de515cad523bcef08adeb50f0304f Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Fri, 4 Apr 2025 03:53:37 -0400 Subject: [PATCH 007/176] [Router] Added Code Comments and Documentation for Connection Routers Added Doxygen-style code comments and documentation for connection routers, including the ConnectionRouter abstract class, the Parallel- ConnectionRouter concrete class, and the SerialConnectionRouter concrete class. Updated the helper messages for command-line options added for parallel connection router. --- .../vprinternals/router_connection_router.rst | 18 ++ doc/src/api/vprinternals/vpr_router.rst | 1 + vpr/src/base/read_options.cpp | 42 ++- vpr/src/route/connection_router.h | 291 +++++++++++++----- vpr/src/route/connection_router.tpp | 59 +--- vpr/src/route/multi_queue_d_ary_heap.h | 2 +- vpr/src/route/parallel_connection_router.cpp | 91 +++--- vpr/src/route/parallel_connection_router.h | 233 +++++++++++--- vpr/src/route/serial_connection_router.cpp | 124 ++++---- vpr/src/route/serial_connection_router.h | 169 ++++++---- 10 files changed, 690 insertions(+), 340 deletions(-) create mode 100644 doc/src/api/vprinternals/router_connection_router.rst diff --git a/doc/src/api/vprinternals/router_connection_router.rst b/doc/src/api/vprinternals/router_connection_router.rst new file mode 100644 index 00000000000..32a7c7dc673 --- /dev/null +++ b/doc/src/api/vprinternals/router_connection_router.rst @@ -0,0 +1,18 @@ +========== +Connection Router +========== + +ConnectionRouter +--------- +.. doxygenfile:: connection_router.h + :project: vpr + +SerialConnectionRouter +---------- +.. doxygenclass:: SerialConnectionRouter + :project: vpr + +ParallelConnectionRouter +---------- +.. doxygenclass:: ParallelConnectionRouter + :project: vpr diff --git a/doc/src/api/vprinternals/vpr_router.rst b/doc/src/api/vprinternals/vpr_router.rst index 63624cd8b39..5e72894aba7 100644 --- a/doc/src/api/vprinternals/vpr_router.rst +++ b/doc/src/api/vprinternals/vpr_router.rst @@ -9,3 +9,4 @@ VPR Router router_heap router_lookahead + router_connection_router diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 1b32fd9c83a..d8eff3053d1 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -2660,32 +2660,62 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .show_in(argparse::ShowIn::HELP_ONLY); route_timing_grp.add_argument(args.enable_parallel_connection_router, "--enable_parallel_connection_router") - .help("TODO") + .help( + "Controls whether the parallel connection router is used during a single connection routing." + " When enabled, the parallel connection router accelerates the path search for individual" + " source-sink connections using multi-threading without altering the net routing order.") .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); route_timing_grp.add_argument(args.post_target_prune_fac, "--post_target_prune_fac") - .help("TODO") + .help( + "Controls the post-target pruning heuristic calculation in the parallel connection router." + " This parameter is used as a multiplicative factor applied to the VPR heuristic" + " (not guaranteed to be admissible, i.e., might over-predict the cost to the sink)" + " to calculate the 'stopping heuristic' when pruning nodes after the target has been" + " reached. The 'stopping heuristic' must be admissible for the path search algorithm" + " to guarantee optimal paths and be deterministic. Values of this parameter are" + " architecture-specific and have to be empirically found." + " This parameter has no effect if --enable_parallel_connection_router is not set.") .default_value("1.2") .show_in(argparse::ShowIn::HELP_ONLY); route_timing_grp.add_argument(args.post_target_prune_offset, "--post_target_prune_offset") - .help("TODO") + .help( + "Controls the post-target pruning heuristic calculation in the parallel connection router." + " This parameter is used as a subtractive offset together with --post_target_prune_fac" + " to apply an affine transformation on the VPR heuristic to calculate the 'stopping" + " heuristic'. The 'stopping heuristic' must be admissible for the path search" + " algorithm to guarantee optimal paths and be deterministic. Values of this" + " parameter are architecture-specific and have to be empirically found." + " This parameter has no effect if --enable_parallel_connection_router is not set." .default_value("0.0") .show_in(argparse::ShowIn::HELP_ONLY); route_timing_grp.add_argument(args.multi_queue_num_threads, "--multi_queue_num_threads") - .help("TODO") + .help( + "Controls the number of threads used by MultiQueue-based parallel connection router." + " If not explicitly specified, defaults to 1, implying the parallel connection router" + " works in 'serial' mode using only one main thread to route." + " This parameter has no effect if --enable_parallel_connection_router is not set.") .default_value("1") .show_in(argparse::ShowIn::HELP_ONLY); route_timing_grp.add_argument(args.multi_queue_num_queues, "--multi_queue_num_queues") - .help("TODO") + .help( + "Controls the number of queues used by MultiQueue in the parallel connection router." + " Must be set >= 2. A common configuration for this parameter is the number of threads" + " used by MultiQueue * 4 (the number of queues per thread)." + " This parameter has no effect if --enable_parallel_connection_router is not set.") .default_value("2") .show_in(argparse::ShowIn::HELP_ONLY); route_timing_grp.add_argument(args.multi_queue_direct_draining, "--multi_queue_direct_draining") - .help("TODO") + .help( + "Controls whether to enable queue draining optimization for MultiQueue-based parallel connection" + " router. When enabled, queues can be emptied quickly by draining all elements if no further" + " solutions need to be explored in the path search to guarantee optimality or determinism after" + " reaching the target. This parameter has no effect if --enable_parallel_connection_router is not set.") .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/connection_router.h index 12e488aa413..99a8b393c94 100644 --- a/vpr/src/route/connection_router.h +++ b/vpr/src/route/connection_router.h @@ -1,6 +1,26 @@ #ifndef _CONNECTION_ROUTER_H #define _CONNECTION_ROUTER_H +/** + * @file + * @brief This file defines the ConnectionRouter class. + * + * Overview + * ======== + * The ConnectionRouter represents the timing-driven connection routers, which + * route from some initial set of sources (via the input rt tree) to a particular + * sink. VPR supports two timing-driven connection routers, including the serial + * connection router and the MultiQueue-based parallel connection router. This + * class defines the interface for the two connection routers and encapsulates + * the common member variables and helper functions for them. + * + * @note + * When the ConnectionRouter is used, it mutates the provided rr_node_route_inf. + * The routed path can be found by tracing from the sink node (which is returned) + * through the rr_node_route_inf. See update_traceback as an example of this tracing. + * + */ + #include "connection_router_interface.h" #include "rr_graph_storage.h" #include "route_common.h" @@ -10,14 +30,10 @@ #include "router_stats.h" #include "spatial_route_tree_lookup.h" -// This class encapsulates the timing driven connection router. This class -// routes from some initial set of sources (via the input rt tree) to a -// particular sink. -// -// When the ConnectionRouter is used, it mutates the provided -// rr_node_route_inf. The routed path can be found by tracing from the sink -// node (which is returned) through the rr_node_route_inf. See -// update_traceback as an example of this tracing. +/** + * @class ConnectionRouter defines the interface for the serial and parallel connection + * routers and encapsulates the common variables and helper functions for the two routers + */ template class ConnectionRouter : public ConnectionRouterInterface { public: @@ -44,26 +60,36 @@ class ConnectionRouter : public ConnectionRouterInterface { , router_debug_(false) , path_search_cumulative_time(0) { heap_.init_heap(grid); - only_opin_inter_layer = (grid.get_num_layers() > 1) && inter_layer_connections_limited_to_opin(*rr_graph); } virtual ~ConnectionRouter() {} - // Clear's the modified list. Should be called after reset_path_costs - // have been called. + /** + * @brief Clears the modified list + * @note Should be called after reset_path_costs have been called + */ virtual void clear_modified_rr_node_info() = 0; - // Reset modified data in rr_node_route_inf based on modified_rr_node_inf. + /** + * @brief Resets modified data in rr_node_route_inf based on modified_rr_node_inf + */ virtual void reset_path_costs() = 0; - /** Finds a path from the route tree rooted at rt_root to sink_node. - * This is used when you want to allow previous routing of the same net to - * serve as valid start locations for the current connection. - * - * Returns a tuple of: - * bool: path exists? (hard failure, rr graph disconnected) - * bool: should retry with full bounding box? (only used in parallel routing) - * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ + /** + * @brief Finds a path from the route tree rooted at rt_root to sink_node + * @note This is used when you want to allow previous routing of the same + * net to serve as valid start locations for the current connection. + * @param rt_root RouteTreeNode describing the current routing state + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param router_stats Update router statistics + * @param conn_params Parameters to guide the routing of the given connection + * @return A tuple of: + * - bool: path exists? (hard failure, rr graph disconnected) + * - bool: should retry with full bounding box? (only used in parallel routing) + * - RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing + */ std::tuple timing_driven_route_connection_from_route_tree( const RouteTreeNode& rt_root, RRNodeId sink_node, @@ -72,16 +98,22 @@ class ConnectionRouter : public ConnectionRouterInterface { RouterStats& router_stats, const ConnectionParameters& conn_params) final; - /** Finds a path from the route tree rooted at rt_root to sink_node for a - * high fanout net. - * - * Unlike timing_driven_route_connection_from_route_tree(), only part of - * the route tree which is spatially close to the sink is added to the heap. - * - * Returns a tuple of: - * bool: path exists? (hard failure, rr graph disconnected) - * bool: should retry with full bounding box? (only used in parallel routing) - * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ + /** + * @brief Finds a path from the route tree rooted at rt_root to sink_node for a high fanout net + * @note Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree which + * is spatially close to the sink is added to the heap. + * @param rt_root RouteTreeNode describing the current routing state + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param net_bounding_box Keep search confined to this bounding box + * @param spatial_rt_lookup Route tree spatial lookup + * @param router_stats Update router statistics + * @param conn_params Parameters to guide the routing of the given connection + * @return A tuple of: + * - bool: path exists? (hard failure, rr graph disconnected) + * - bool: should retry with full bounding box? (only used in parallel routing) + * - RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing + */ std::tuple timing_driven_route_connection_from_route_tree_high_fanout( const RouteTreeNode& rt_root, RRNodeId sink_node, @@ -91,18 +123,22 @@ class ConnectionRouter : public ConnectionRouterInterface { RouterStats& router_stats, const ConnectionParameters& conn_params) final; - // Finds a path from the route tree rooted at rt_root to all sinks - // available. - // - // Each element of the returned vector is a reachable sink. - // - // If cost_params.astar_fac is set to 0, this effectively becomes - // Dijkstra's algorithm with a modified exit condition (runs until heap is - // empty). When using cost_params.astar_fac = 0, for efficiency the - // RouterLookahead used should be the NoOpLookahead. - // - // Note: This routine is currently used only to generate information that - // may be helpful in debugging an architecture. + /** + * @brief Finds shortest paths from the route tree rooted at rt_root to all sinks available + * @note Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree which + * is spatially close to the sink is added to the heap. + * @note If cost_params.astar_fac is set to 0, this effectively becomes Dijkstra's algorithm with a + * modified exit condition (runs until heap is empty). When using cost_params.astar_fac = 0, for + * efficiency the RouterLookahead used should be the NoOpLookahead. + * @note This routine is currently used only to generate information that may be helpful in debugging + * an architecture. + * @param rt_root RouteTreeNode describing the current routing state + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param router_stats Update router statistics + * @param conn_params Parameters to guide the routing of the given connection + * @return A vector where each element is a reachable sink + */ virtual vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( const RouteTreeNode& rt_root, const t_conn_cost_params& cost_params, @@ -110,81 +146,127 @@ class ConnectionRouter : public ConnectionRouterInterface { RouterStats& router_stats, const ConnectionParameters& conn_params) = 0; + /** + * @brief Sets router debug option + * @param router_debug Router debug option + */ void set_router_debug(bool router_debug) final { router_debug_ = router_debug; } - // Empty the route tree set used for RCV node detection - // Will return if RCV is disabled - // Called after each net is finished routing to flush the set - void empty_rcv_route_tree_set() final; + /** + * @brief Empties the route tree set used for RCV node detection + * @note Will immediately return if RCV is disabled. Called after + * each net is finished routing to flush the set. + */ + void empty_rcv_route_tree_set() final { + rcv_path_manager.empty_route_tree_nodes(); + } - // Enable or disable RCV in connection router - // Enabling this will utilize extra path structures, as well as the RCV cost function - // - // Ensure route budgets have been calculated before enabling this + /** + * @brief Enables or disables RCV in connection router + * @note Enabling this will utilize extra path structures, as well as + * the RCV cost function. Ensure route budgets have been calculated + * before enabling this. + * @param enable Whether enabling RCV or not + */ virtual void set_rcv_enabled(bool enable) = 0; protected: - /** Common logic from timing_driven_route_connection_from_route_tree and + /** + * @brief Common logic from timing_driven_route_connection_from_route_tree and * timing_driven_route_connection_from_route_tree_high_fanout for running * the connection router. - * @param[in] rt_root RouteTreeNode describing the current routing state - * @param[in] sink_node Sink node ID to route to - * @param[in] cost_params - * @param[in] bounding_box Keep search confined to this bounding box - * @return bool Signal to retry this connection with a full-device bounding box */ + * @param rt_root RouteTreeNode describing the current routing state + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @return bool signal to retry this connection with a full-device bounding box + */ bool timing_driven_route_connection_common_setup( const RouteTreeNode& rt_root, RRNodeId sink_node, const t_conn_cost_params& cost_params, const t_bb& bounding_box); - // Finds a path to sink_node, starting from the elements currently in the - // heap. - // - // If the path is not found, which means that the path_cost of sink_node in - // RR node route info has never been updated, `rr_node_route_inf_[sink_node] - // .path_cost` will be the initial value (i.e., float infinity). This case - // can be detected by `std::isinf(rr_node_route_inf_[sink_node].path_cost)`. - // - // This is the core maze routing routine. - // - // Note: For understanding the connection router, start here. + /** + * @brief Finds a path to sink_node, starting from the elements currently in the heap + * @note If the path is not found, which means that the path_cost of sink_node in RR + * node route info has never been updated, `rr_node_route_inf_[sink_node].path_cost` + * will be the initial value (i.e., float infinity). This case can be detected by + * `std::isinf(rr_node_route_inf_[sink_node].path_cost)`. + * @note This is the core maze routing routine. For understanding the connection + * router, start here. + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + */ void timing_driven_route_connection_from_heap( RRNodeId sink_node, const t_conn_cost_params& cost_params, const t_bb& bounding_box); - // Find the shortest path from current heap to the sink node in the RR graph + /** + * @brief Finds the single shortest path from current heap to the sink node in the RR graph + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ virtual void timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, const t_conn_cost_params& cost_params, const t_bb& bounding_box, const t_bb& target_bb) = 0; - // Find paths from current heap to all nodes in the RR graph + /** + * @brief Finds shortest paths from current heap to all nodes in the RR graph + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @return A vector where each element contains the shortest route to a specific sink node + */ virtual vtr::vector timing_driven_find_all_shortest_paths_from_heap( const t_conn_cost_params& cost_params, const t_bb& bounding_box) = 0; - //Unconditionally adds rt_node to the heap - // - //Note that if you want to respect rt_node->re_expand that is the caller's - //responsibility. + /** + * @brief Unconditionally adds rt_node to the heap + * @note If you want to respect rt_node->re_expand that is the caller's responsibility. + * @todo Consider moving this function into the ConnectionRouter class after checking + * the different prune functions of the serial and parallel connection routers. + * @param rt_node RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param net_bb Do not push to heap if not in bounding box + */ virtual void add_route_tree_node_to_heap( const RouteTreeNode& rt_node, RRNodeId target_node, const t_conn_cost_params& cost_params, const t_bb& net_bb) = 0; - // Calculates the cost of reaching to_node + /** + * @brief Calculates the cost of reaching to_node + * @param to Neighbor node to calculate costs before being expanded + * @param cost_params Cost function parameters + * @param from_node Current node ID being explored + * @param target_node Target node ID to route to + */ void evaluate_timing_driven_node_costs( RTExploredNode* to, const t_conn_cost_params& cost_params, RRNodeId from_node, RRNodeId target_node); - // Evaluate node costs using the RCV algorith + /** + * @brief Evaluate node costs using the RCV algorithm + * @param cost_params Cost function parameters + * @param to_node Neighbor node to calculate costs before being expanded + * @param target_node Target node ID to route to + * @param backwards_delay "Known" delay up to and including to_node + * @param backwards_cong "Known" congestion up to and including to_node + * @param R_upstream Upstream resistance to ground from to_node + * @return Node cost using RCV + */ float compute_node_cost_using_rcv(const t_conn_cost_params cost_params, RRNodeId to_node, RRNodeId target_node, @@ -192,13 +274,27 @@ class ConnectionRouter : public ConnectionRouterInterface { float backwards_cong, float R_upstream); - //Adds the route tree rooted at rt_node to the heap, preparing it to be - //used as branch-points for further routing. + /** + * @brief Adds the route tree rooted at rt_node to the heap, preparing + * it to be used as branch-points for further routing + * @param rt_node RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param net_bb Do not push to heap if not in bounding box + */ void add_route_tree_to_heap(const RouteTreeNode& rt_node, RRNodeId target_node, const t_conn_cost_params& cost_params, const t_bb& net_bb); - + /** + * @brief For high fanout nets, adds only route tree nodes which are + * spatially close to the sink + * @param rt_root RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param spatial_route_tree_lookup Route tree spatial lookup + * @param net_bounding_box Do not push to heap if not in bounding box + */ t_bb add_high_fanout_route_tree_to_heap( const RouteTreeNode& rt_root, RRNodeId target_node, @@ -206,31 +302,60 @@ class ConnectionRouter : public ConnectionRouterInterface { const SpatialRouteTreeLookup& spatial_route_tree_lookup, const t_bb& net_bounding_box); + /** Device grid */ const DeviceGrid& grid_; + + /** Router lookahead */ const RouterLookahead& router_lookahead_; + + /** RR node data */ const t_rr_graph_view rr_nodes_; + + /** RR graph */ const RRGraphView* rr_graph_; + + /** RR node resistance/capacitance data */ vtr::array_view rr_rc_data_; + + /** RR switch data */ vtr::array_view rr_switch_inf_; + + //@{ + /** Net terminal groups */ const vtr::vector>>& net_terminal_groups; const vtr::vector>& net_terminal_group_num; + //@} + + /** RR node extra information needed during routing */ vtr::vector& rr_node_route_inf_; + + /** Is flat router enabled or not? */ bool is_flat_; + + /** Node IDs of modified nodes in rr_node_route_inf */ std::vector modified_rr_node_inf_; + + /** Router statistics (e.g., heap push/pop counts) */ RouterStats* router_stats_; + + /** Parameters to guide the routing of the given connection */ const ConnectionParameters* conn_params_; + + /** Templated heap instance (e.g., binary heap, 4-ary heap, MultiQueue-based parallel heap) */ HeapImplementation heap_; - bool router_debug_; - bool only_opin_inter_layer; + /** Router debug option */ + bool router_debug_; - // Cumulative time spent in the path search part of the connection router. + /** Cumulative time spent in the path search part of the connection router */ std::chrono::microseconds path_search_cumulative_time; - // The path manager for RCV, keeps track of the route tree as a set, also - // manages the allocation of `rcv_path_data`. + //@{ + /** The path manager for RCV, keeps track of the route tree as a set, also + * manages the allocation of `rcv_path_data`. */ PathManager rcv_path_manager; vtr::vector rcv_path_data; + //@} }; #include "connection_router.tpp" diff --git a/vpr/src/route/connection_router.tpp b/vpr/src/route/connection_router.tpp index 2356b225728..e47fa0abceb 100644 --- a/vpr/src/route/connection_router.tpp +++ b/vpr/src/route/connection_router.tpp @@ -12,12 +12,6 @@ inline bool relevant_node_to_target(const RRGraphView* rr_graph, RRNodeId node_to_add, RRNodeId target_node); -inline void update_router_stats(RouterStats* router_stats, - bool is_push, - RRNodeId rr_node_id, - const RRGraphView* rr_graph); - -/** return tuple */ template std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree( const RouteTreeNode& rt_root, @@ -54,11 +48,6 @@ std::tuple ConnectionRouter::timing_driven_rou } } -// Finds a path from the route tree rooted at rt_root to sink_node for a high fanout net. -// -// Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree -// which is spatially close to the sink is added to the heap. -// Returns a tuple of */ template std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree_high_fanout( const RouteTreeNode& rt_root, @@ -124,7 +113,6 @@ std::tuple ConnectionRouter::timing_driven_rou return std::make_tuple(true, retry_with_full_bb, out); } -/** Return whether to retry with full bb */ template bool ConnectionRouter::timing_driven_route_connection_common_setup( const RouteTreeNode& rt_root, @@ -172,8 +160,6 @@ bool ConnectionRouter::timing_driven_route_connection_common_setup( return false; } -// Finds a path to sink_node, starting from the elements currently in the heap. -// This is the core maze routing routine. template void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, const t_conn_cost_params& cost_params, @@ -276,13 +262,6 @@ float ConnectionRouter::compute_node_cost_using_rcv(const t_conn_cost_para return total_cost; } -// Empty the route tree set node, use this after each net is routed -template -void ConnectionRouter::empty_rcv_route_tree_set() { - rcv_path_manager.empty_route_tree_nodes(); -} - -//Calculates the cost of reaching to_node (i.e., to->index) template void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, const t_conn_cost_params& cost_params, @@ -401,8 +380,6 @@ void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* t to->total_cost = total_cost; } -//Adds the route tree rooted at rt_node to the heap, preparing it to be -//used as branch-points for further routing. template void ConnectionRouter::add_route_tree_to_heap( const RouteTreeNode& rt_node, @@ -557,6 +534,8 @@ t_bb ConnectionRouter::add_high_fanout_route_tree_to_heap( } } +/** Used for the flat router. The node isn't relevant to the target if + * it is an intra-block node outside of our target block */ inline bool relevant_node_to_target(const RRGraphView* rr_graph, RRNodeId node_to_add, RRNodeId target_node) { @@ -564,37 +543,3 @@ inline bool relevant_node_to_target(const RRGraphView* rr_graph, auto node_to_add_type = rr_graph->node_type(node_to_add); return node_to_add_type != t_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); } - -inline void update_router_stats(RouterStats* router_stats, - bool is_push, - RRNodeId rr_node_id, - const RRGraphView* rr_graph) { - if (is_push) { - router_stats->heap_pushes++; - } else { - router_stats->heap_pops++; - } - - if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - auto node_type = rr_graph->node_type(rr_node_id); - VTR_ASSERT(node_type != NUM_RR_TYPES); - - if (is_inter_cluster_node(*rr_graph, rr_node_id)) { - if (is_push) { - router_stats->inter_cluster_node_pushes++; - router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; - } else { - router_stats->inter_cluster_node_pops++; - router_stats->inter_cluster_node_type_cnt_pops[node_type]++; - } - } else { - if (is_push) { - router_stats->intra_cluster_node_pushes++; - router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; - } else { - router_stats->intra_cluster_node_pops++; - router_stats->intra_cluster_node_type_cnt_pops[node_type]++; - } - } - } -} diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h index b200e0db0d4..165317c08cd 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.h +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -7,7 +7,7 @@ * * Original source: https://github.com/mcj-group/cps * - * This implementation has been modified from the original to: + * This implementation and interface has been modified from the original to: * - Support queue draining functionality * - Enable integration with the VTR project * diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp index 0543a7a76d4..46cdc70f557 100644 --- a/vpr/src/route/parallel_connection_router.cpp +++ b/vpr/src/route/parallel_connection_router.cpp @@ -2,9 +2,12 @@ #include #include "route_tree.h" -#include "rr_graph.h" #include "rr_graph_fwd.h" +/** Post-target pruning: Prune a given node (do not explore it) if the cost of + * the best possible path from the source, through the node, to the target is + * higher than the cost of the best path found to the target so far. Cited from + * the FPT'24 conference paper (more details can also be found there). */ static inline bool post_target_prune_node(float new_total_cost, float new_back_cost, float best_back_cost_to_target, @@ -36,6 +39,11 @@ static inline bool post_target_prune_node(float new_total_cost, return false; } +/** Pre-push pruning: when iterating over the neighbors of u, this function + * determines whether a path through u to its neighbor node v has a better + * backward cost than the best path to v found so far (breaking ties if needed). + * Cited from the FPT'24 conference paper (more details can also be found there). + */ // TODO: Once we have a heap node struct, clean this up! static inline bool prune_node(RRNodeId inode, float new_total_cost, @@ -102,6 +110,19 @@ static inline bool prune_node(RRNodeId inode, return false; } +/** Post-pop pruning: After node u is popped from the queue, this function + * decides whether to explore the neighbors of u or to prune. Initially, it + * performs Post-Target Pruning based on the stopping criterion. Then, the + * current total estimated cost of the path through node u (f_u) is compared + * to the best total cost so far (most recently pushed) for that node and, + * if the two are different, the node u is pruned. During the wave expansion, + * u may be pushed to the queue multiple times. For example, node u may be + * pushed to the queue and then, before u is popped from the queue, a better + * path to u may be found and pushed to the queue. Here we are using f_u as + * an optimistic identifier to check if the pair (u, f_u) is the most recently + * pushed element for node u. This reduces redundant work. + * Cited from the FPT'24 conference paper (more details can also be found there). + */ static inline bool should_not_explore_neighbors(RRNodeId inode, float new_total_cost, float new_back_cost, @@ -141,17 +162,22 @@ void ParallelConnectionRouter::timing_driven_find_single_shortest_path_fro const t_conn_cost_params& cost_params, const t_bb& bounding_box, const t_bb& target_bb) { - + // Assign the thread task function parameters to atomic variables this->sink_node_ = &sink_node; this->cost_params_ = const_cast(&cost_params); this->bounding_box_ = const_cast(&bounding_box); this->target_bb_ = const_cast(&target_bb); + // Synchronize at the barrier before executing a new thread task this->thread_barrier_.wait(); + + // Main thread executes a new thread task (helper threads are doing the same in the background) this->timing_driven_find_single_shortest_path_from_heap_thread_func(*this->sink_node_, *this->cost_params_, *this->bounding_box_, *this->target_bb_, 0); + + // Synchronize at the barrier before resetting the heap this->thread_barrier_.wait(); // Collect the number of heap pushes and pops @@ -188,14 +214,15 @@ void ParallelConnectionRouter::timing_driven_find_single_shortest_path_fro const size_t thread_idx) { HeapNode cheapest; while (this->heap_.try_pop(cheapest)) { - // inode with the cheapest total cost in current route tree to be expanded on + // Pop a new inode with the cheapest total cost in current route tree to be expanded on const auto& [new_total_cost, inode] = cheapest; - // Should we explore the neighbors of this node? + // Check if we should explore the neighbors of this node if (should_not_explore_neighbors(inode, new_total_cost, this->rr_node_route_inf_[inode].backward_path_cost, sink_node, this->rr_node_route_inf_, cost_params)) { continue; } + // Get the current RR node info within a critical section to prevent data races obtainSpinLock(inode); RTExploredNode current; @@ -274,9 +301,6 @@ void ParallelConnectionRouter::timing_driven_expand_neighbours(const RTExp } } -// Conditionally adds to_node to the router heap (via path from from_node via from_edge). -// RR nodes outside the expanded bounding box specified in bounding_box are not added -// to the heap. template void ParallelConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, RREdgeId from_edge, @@ -286,23 +310,11 @@ void ParallelConnectionRouter::timing_driven_expand_neighbour(const RTExpl RRNodeId target_node, const t_bb& target_bb, size_t thread_idx) { - // VTR_ASSERT(bounding_box.layer_max < g_vpr_ctx.device().grid.get_num_layers()); - - // const RRNodeId& from_node = current.index; - // BB-pruning // Disable BB-pruning if RCV is enabled, as this can make it harder for circuits with high negative hold slack to resolve this // TODO: Only disable pruning if the net has negative hold slack, maybe go off budgets if (!inside_bb(to_node, bounding_box)) { - // VTR_LOGV_DEBUG(router_debug_, - // " Pruned expansion of node %d edge %zu -> %d" - // " (to node location %d,%d,%d x %d,%d,%d outside of expanded" - // " net bounding box %d,%d,%d x %d,%d,%d)\n", - // from_node, size_t(from_edge), size_t(to_node), - // rr_graph_->node_xlow(to_node), rr_graph_->node_ylow(to_node), rr_graph_->node_layer(to_node), - // rr_graph_->node_xhigh(to_node), rr_graph_->node_yhigh(to_node), rr_graph_->node_layer(to_node), - // bounding_box.xmin, bounding_box.ymin, bounding_box.layer_min, - // bounding_box.xmax, bounding_box.ymax, bounding_box.layer_max); + // Note: Logging are disabled for parallel connection router return; /* Node is outside (expanded) bounding box. */ } @@ -326,22 +338,12 @@ void ParallelConnectionRouter::timing_driven_expand_neighbour(const RTExpl || to_yhigh > target_bb.ymax || to_layer < target_bb.layer_min || to_layer > target_bb.layer_max) { - // VTR_LOGV_DEBUG(router_debug_, - // " Pruned expansion of node %d edge %zu -> %d" - // " (to node is IPIN at %d,%d,%d x %d,%d,%d which does not" - // " lead to target block %d,%d,%d x %d,%d,%d)\n", - // from_node, size_t(from_edge), size_t(to_node), - // to_xlow, to_ylow, to_layer, - // to_xhigh, to_yhigh, to_layer, - // target_bb.xmin, target_bb.ymin, target_bb.layer_min, - // target_bb.xmax, target_bb.ymax, target_bb.layer_max); + // Note: Logging are disabled for parallel connection router return; } } } - - // VTR_LOGV_DEBUG(router_debug_, " Expanding node %d edge %zu -> %d\n", - // from_node, size_t(from_edge), size_t(to_node)); + // Note: Logging are disabled for parallel connection router timing_driven_add_to_heap(cost_params, current, @@ -351,7 +353,6 @@ void ParallelConnectionRouter::timing_driven_expand_neighbour(const RTExpl thread_idx); } -// Add to_node to the heap, and also add any nodes which are connected by non-configurable edges template void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, const RTExploredNode& current, @@ -361,7 +362,7 @@ void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost size_t thread_idx) { const RRNodeId& from_node = current.index; - // Initialized to current + // Initialize the neighbor RTExploredNode RTExploredNode next; next.R_upstream = current.R_upstream; next.index = to_node; @@ -374,6 +375,7 @@ void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost float new_total_cost = next.total_cost; float new_back_cost = next.backward_path_cost; + // To further reduce lock contention, we add a cheap read-only check before acquiring the lock, motivated by Shun et al. if (prune_node(to_node, new_total_cost, new_back_cost, from_edge, target_node, this->rr_node_route_inf_, cost_params)) { return; } @@ -398,17 +400,8 @@ void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost return; } heap_.add_to_heap({new_total_cost, to_node}); - - // update_router_stats(router_stats_, - // /*is_push=*/true, - // to_node, - // rr_graph_); } -//Unconditionally adds rt_node to the heap -// -//Note that if you want to respect rt_node.re_expand that is the caller's -//responsibility. template void ParallelConnectionRouter::add_route_tree_node_to_heap( const RouteTreeNode& rt_node, @@ -424,14 +417,12 @@ void ParallelConnectionRouter::add_route_tree_node_to_heap( if (!inside_bb(rt_node.inode, net_bb)) return; - // after budgets are loaded, calculate delay cost as described by RCV paper + // After budgets are loaded, calculate delay cost as described by RCV paper /* R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While * Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of * Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008.*/ - // float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); if (!this->rcv_path_manager.is_enabled()) { - // tot_cost = backward_path_cost + cost_params.astar_fac * expected_cost; float expected_cost = this->router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); float tot_cost = backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); VTR_LOGV_DEBUG(this->router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", @@ -448,14 +439,8 @@ void ParallelConnectionRouter::add_route_tree_node_to_heap( this->rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; this->rr_node_route_inf_[inode].R_upstream = R_upstream; this->heap_.push_back({tot_cost, inode}); - - // push_back_node(&heap_, rr_node_route_inf_, - // inode, tot_cost, RREdgeId::INVALID(), - // backward_path_cost, R_upstream); } - // if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - // router_stats_->rt_node_pushes[rr_graph_->node_type(inode)]++; - // } + // Note: RCV is not supported by parallel connection router } std::unique_ptr make_parallel_connection_router(e_heap_type heap_type, diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h index e38789ed3d5..12daba4a293 100644 --- a/vpr/src/route/parallel_connection_router.h +++ b/vpr/src/route/parallel_connection_router.h @@ -11,21 +11,44 @@ #include #include +/** + * @brief Spin lock implementation using std::atomic_flag + * + * It is used per RR node for protecting the update to node costs + * to prevent data races. Since different threads rarely work on + * the same node simultaneously, this fine-grained locking strategy + * of one lock per node reduces contention. + */ class spin_lock_t { + /** Atomic flag used for the lock implementation */ std::atomic_flag lock_ = ATOMIC_FLAG_INIT; public: + /** + * @brief Acquires the spin lock, repeatedly attempting until successful + */ void acquire() { while (std::atomic_flag_test_and_set_explicit(&lock_, std::memory_order_acquire)) ; } + /** + * @brief Releases the spin lock, allowing other threads to acquire it + */ void release() { std::atomic_flag_clear_explicit(&lock_, std::memory_order_release); } }; +/** + * @brief Thread barrier implementation using std::mutex + * + * It ensures all participating threads reach a synchronization point + * before any are allowed to proceed further. It uses a mutex and + * condition variable to coordinate thread synchronization. + */ class barrier_mutex_t { + // FIXME: Try std::barrier (since C++20) to replace this mutex barrier std::mutex mutex_; std::condition_variable cv_; size_t count_; @@ -33,10 +56,21 @@ class barrier_mutex_t { size_t generation_ = 0; public: + /** + * @brief Constructs a barrier for a specific number of threads + * @param num_threads Number of threads that must call wait() before + * any thread is allowed to proceed + */ explicit barrier_mutex_t(size_t num_threads) : count_(num_threads) , max_count_(num_threads) {} + /** + * @brief Blocks the calling thread until all threads have called wait() + * + * When the specified number of threads have called this method, all + * threads are unblocked and the barrier is reset for the next use. + */ void wait() { std::unique_lock lock{mutex_}; size_t gen = generation_; @@ -50,19 +84,50 @@ class barrier_mutex_t { } }; +/** + * @brief Spin-based thread barrier implementation using std::atomic + * + * It ensures all participating threads reach a synchronization point + * before any are allowed to proceed further. It uses atomic operations + * to implement Sense-Reversing Centralized Barrier (from Section 5.2.1 + * of Michael L. Scott's textbook) without using mutex locks. + */ class barrier_spin_t { + /** Number of threads that must reach the barrier */ size_t num_threads_ = 1; + + /** Atomic counter tracking the number of threads that have arrived at the barrier */ std::atomic count_ = 0; - std::atomic sense_ = false; // global sense shared by multiple threads + + /** Global sense shared by all participating threads */ + std::atomic sense_ = false; + + /** Thread-local sense value for each participating thread */ inline static thread_local bool local_sense_ = false; public: + /** + * @brief Constructs a barrier for a specific number of threads + * @param num_threads Number of threads that must call wait() before + * any thread is allowed to proceed + */ explicit barrier_spin_t(size_t num_threads) { num_threads_ = num_threads; } + /** + * @brief Initializes the thread-local sense flag + * @note Should be called by each thread before first using the barrier. + */ void init() { local_sense_ = false; } + /** + * @brief Blocks the calling thread until all threads have called wait() + * + * Uses a sense-reversing algorithm to synchronize threads. The last thread + * to arrive unblocks all waiting threads. This method avoids using locks or + * condition variables, making it potentially more efficient for short waits. + */ void wait() { bool s = !local_sense_; local_sense_ = s; @@ -72,21 +137,21 @@ class barrier_spin_t { sense_.store(s); } else { while (sense_.load() != s) - ; + ; // spin until the last thread arrives } } }; -using barrier_t = barrier_spin_t; +using barrier_t = barrier_spin_t; // Using the spin-based thread barrier -// This class encapsulates the timing driven connection router. This class -// routes from some initial set of sources (via the input rt tree) to a -// particular sink. -// -// When the ParallelConnectionRouter is used, it mutates the provided -// rr_node_route_inf. The routed path can be found by tracing from the sink -// node (which is returned) through the rr_node_route_inf. See -// update_traceback as an example of this tracing. +/** + * @class ParallelConnectionRouter implements the MultiQueue-based parallel connection + * router (FPT'24) based on the ConnectionRouter interface. + * @details The details of the algorithm can be found from the conference paper: + * A. Singer, H. Yan, G. Zhang, M. Jeffrey, M. Stojilovic and V. Betz, "MultiQueue-Based FPGA Routing: + * Relaxed A* Priority Ordering for Improved Parallelism," Int. Conf. on Field-Programmable Technology, + * Dec. 2024. + */ template class ParallelConnectionRouter : public ConnectionRouter { public: @@ -109,8 +174,10 @@ class ParallelConnectionRouter : public ConnectionRouter { , is_router_destroying_(false) , locks_(rr_node_route_inf.size()) , multi_queue_direct_draining_(multi_queue_direct_draining) { - this->sub_threads_.resize(multi_queue_num_threads - 1); + // Initialize the thread barrier this->thread_barrier_.init(); + // Instantiate (multi_queue_num_threads - 1) helper threads + this->sub_threads_.resize(multi_queue_num_threads - 1); for (int i = 0; i < multi_queue_num_threads - 1; ++i) { this->sub_threads_[i] = std::thread(&ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap_sub_thread_wrapper, this, i + 1 /*0: main thread*/); this->sub_threads_[i].detach(); @@ -118,19 +185,26 @@ class ParallelConnectionRouter : public ConnectionRouter { } ~ParallelConnectionRouter() { - this->is_router_destroying_ = true; - this->thread_barrier_.wait(); + this->is_router_destroying_ = true; // signal the helper threads to exit + this->thread_barrier_.wait(); // wait until all threads reach the barrier VTR_LOG("Parallel Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", std::chrono::duration(this->path_search_cumulative_time).count()); } + /** + * @brief Clears the modified list per thread + * @note Should be called after reset_path_costs have been called + */ void clear_modified_rr_node_info() final { for (auto& thread_visited_rr_nodes : this->modified_rr_node_inf_) { thread_visited_rr_nodes.clear(); } } + /** + * @brief Resets modified data in rr_node_route_inf based on modified_rr_node_inf + */ void reset_path_costs() final { auto& route_ctx = g_vpr_ctx.mutable_routing(); for (const auto& thread_visited_rr_nodes : this->modified_rr_node_inf_) { @@ -142,30 +216,44 @@ class ParallelConnectionRouter : public ConnectionRouter { } } + /** + * @brief [Not supported] Enables RCV feature + * @note RCV for parallel connection router has not been implemented yet. + * Thus this function is not expected to be called. + */ void set_rcv_enabled(bool) final { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "RCV for parallel connection router not yet implemented. Not expected to be called."); } + /** + * @brief [Not supported] Finds shortest paths from the route tree rooted at rt_root to all sinks available + * @note This function has not been implemented yet and is not the focus of parallel connection router. + * Thus this function is not expected to be called. + */ vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( const RouteTreeNode&, const t_conn_cost_params&, const t_bb&, RouterStats&, const ConnectionParameters&) final { - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_route_tree not yet implemented (nor is the focus of this project). Not expected to be called."); + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_route_tree not yet implemented (nor is the focus of the parallel connection router). Not expected to be called."); } protected: - // Mark that data associated with rr_node "inode" has been modified, and - // needs to be reset in reset_path_costs. + /** + * @brief Marks that data associated with rr_node 'inode' has + * been modified, and needs to be reset in reset_path_costs + */ inline void add_to_mod_list(RRNodeId inode, size_t thread_idx) { if (std::isinf(this->rr_node_route_inf_[inode].path_cost)) { this->modified_rr_node_inf_[thread_idx].push_back(inode); } } - // Update the route path to the node `cheapest.index` via the path from - // `from_node` via `cheapest.prev_edge`. + /** + * @brief Updates the route path to the node `cheapest.index` + * via the path from `from_node` via `cheapest.prev_edge` + */ inline void update_cheapest(RTExploredNode& cheapest, size_t thread_idx) { const RRNodeId& inode = cheapest.index; add_to_mod_list(inode, thread_idx); @@ -174,23 +262,51 @@ class ParallelConnectionRouter : public ConnectionRouter { this->rr_node_route_inf_[inode].backward_path_cost = cheapest.backward_path_cost; } + /** + * @brief Obtains the per-node spin locks for protecting node cost updates + */ inline void obtainSpinLock(const RRNodeId& inode) { this->locks_[size_t(inode)].acquire(); } + /** + * @brief Releases the per-node spin lock, allowing other + * threads working on the same node to obtain it + */ inline void releaseLock(const RRNodeId& inode) { this->locks_[size_t(inode)].release(); } - // Find the shortest path from current heap to the sink node in the RR graph + /** + * @brief Finds the single shortest path from current heap to the sink node in the RR graph + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ void timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, const t_conn_cost_params& cost_params, const t_bb& bounding_box, const t_bb& target_bb) final; + /** + * @brief Helper thread wrapper function, passed to std::thread instantiation and running a + * while-loop to obtain and execute new helper thread tasks until the main thread signals the + * threads to exit + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ void timing_driven_find_single_shortest_path_from_heap_sub_thread_wrapper( const size_t thread_idx); + /** + * @brief Helper thread task function to find the single shortest path from current heap to + * the sink node in the RR graph + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ void timing_driven_find_single_shortest_path_from_heap_thread_func( RRNodeId sink_node, const t_conn_cost_params& cost_params, @@ -198,7 +314,15 @@ class ParallelConnectionRouter : public ConnectionRouter { const t_bb& target_bb, const size_t thread_idx); - // Expand each neighbor of the current node. + /** + * @brief Expands each neighbor of the current node in the wave expansion + * @param current Current node being explored + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_node Target node ID to route to + * @param target_bb Prune IPINs that lead to blocks other than the target block + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ void timing_driven_expand_neighbours( const RTExploredNode& current, const t_conn_cost_params& cost_params, @@ -207,11 +331,18 @@ class ParallelConnectionRouter : public ConnectionRouter { const t_bb& target_bb, size_t thread_idx); - // Conditionally adds to_node to the router heap (via path from current.index - // via from_edge). - // - // RR nodes outside bounding box specified in bounding_box are not added - // to the heap. + /** + * @brief Conditionally adds to_node to the router heap (via path from current.index via from_edge) + * @note RR nodes outside bounding box specified in bounding_box are not added to the heap. + * @param current Current node being explored + * @param from_edge Edge between the current node and the neighbor node + * @param to_node Neighbor node to be expanded + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_node Target node ID to route to + * @param target_bb Prune IPINs that lead to blocks other than the target block + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ void timing_driven_expand_neighbour( const RTExploredNode& current, RREdgeId from_edge, @@ -222,8 +353,15 @@ class ParallelConnectionRouter : public ConnectionRouter { const t_bb& target_bb, size_t thread_idx); - // Add to_node to the heap, and also add any nodes which are connected by - // non-configurable edges + /** + * @brief Adds to_node to the heap, and also adds any nodes which are connected by non-configurable edges + * @param cost_params Cost function parameters + * @param current Current node being explored + * @param to_node Neighbor node to be expanded + * @param from_edge Edge between the current node and the neighbor node + * @param target_node Target node ID to route to + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ void timing_driven_add_to_heap( const t_conn_cost_params& cost_params, const RTExploredNode& current, @@ -232,36 +370,61 @@ class ParallelConnectionRouter : public ConnectionRouter { RRNodeId target_node, size_t thread_idx); - // TODO: move this function into ConnectionRouter class - //Unconditionally adds rt_node to the heap - // - //Note that if you want to respect rt_node->re_expand that is the caller's - //responsibility. + /** + * @brief Unconditionally adds rt_node to the heap + * @note If you want to respect rt_node->re_expand that is the caller's responsibility. + * @todo Consider moving this function into the ConnectionRouter class after checking + * the different prune functions of the serial and parallel connection routers. + * @param rt_node RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param net_bb Do not push to heap if not in bounding box + */ void add_route_tree_node_to_heap( const RouteTreeNode& rt_node, RRNodeId target_node, const t_conn_cost_params& cost_params, - const t_bb& net_bb); + const t_bb& net_bb) final; - // Find paths from current heap to all nodes in the RR graph + /** + * @brief [Not supported] Finds shortest paths from current heap to all nodes in the RR graph + * @note This function has not been implemented yet and is not the focus of parallel connection router. + * Thus this function is not expected to be called. + */ vtr::vector timing_driven_find_all_shortest_paths_from_heap( const t_conn_cost_params&, const t_bb&) final { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_heap not yet implemented (nor is the focus of this project). Not expected to be called."); } + /** Node IDs of modified nodes in rr_node_route_inf for each thread*/ std::vector> modified_rr_node_inf_; + + /** MultiQueue-based parallel heap */ MultiQueueDAryHeap heap_; + + /** Helper threads */ std::vector sub_threads_; + + /** Thread barrier for synchronization */ barrier_t thread_barrier_; + + /** Signal for helper threads to exit */ std::atomic is_router_destroying_; + + /** Fine-grained locks per RR node */ std::vector locks_; + + /** Is queue draining optimization enabled? */ bool multi_queue_direct_draining_; + //@{ + /** Atomic parameters of thread task functions to pass from main thread to helper threads */ std::atomic sink_node_; std::atomic cost_params_; std::atomic bounding_box_; std::atomic target_bb_; + //@} }; /** Construct a parallel connection router that uses the specified heap type. diff --git a/vpr/src/route/serial_connection_router.cpp b/vpr/src/route/serial_connection_router.cpp index cc017506385..f5c3a1762e5 100644 --- a/vpr/src/route/serial_connection_router.cpp +++ b/vpr/src/route/serial_connection_router.cpp @@ -4,6 +4,12 @@ #include "rr_graph.h" #include "rr_graph_fwd.h" +/** Used to update router statistics for serial connection router */ +inline void update_serial_router_stats(RouterStats* router_stats, + bool is_push, + RRNodeId rr_node_id, + const RRGraphView* rr_graph); + template void SerialConnectionRouter::timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, const t_conn_cost_params& cost_params, @@ -14,12 +20,12 @@ void SerialConnectionRouter::timing_driven_find_single_shortest_path_from_ HeapNode cheapest; while (this->heap_.try_pop(cheapest)) { - // inode with the cheapest total cost in current route tree to be expanded on + // Pop a new inode with the cheapest total cost in current route tree to be expanded on const auto& [new_total_cost, inode] = cheapest; - update_router_stats(this->router_stats_, - /*is_push=*/false, - inode, - this->rr_graph_); + update_serial_router_stats(this->router_stats_, + /*is_push=*/false, + inode, + this->rr_graph_); VTR_LOGV_DEBUG(this->router_debug_, " Popping node %d (cost: %g)\n", inode, new_total_cost); @@ -49,7 +55,6 @@ void SerialConnectionRouter::timing_driven_find_single_shortest_path_from_ } } -// Find shortest paths from specified route tree to all nodes in the RR graph template vtr::vector SerialConnectionRouter::timing_driven_find_all_shortest_paths_from_route_tree( const RouteTreeNode& rt_root, @@ -71,14 +76,13 @@ vtr::vector SerialConnectionRouter::timing_drive return res; } -// Find shortest paths from current heap to all nodes in the RR graph -// -// Since there is no single *target* node this uses Dijkstra's algorithm -// with a modified exit condition (runs until heap is empty). template vtr::vector SerialConnectionRouter::timing_driven_find_all_shortest_paths_from_heap( const t_conn_cost_params& cost_params, const t_bb& bounding_box) { + // Since there is no single *target* node this uses Dijkstra's algorithm + // with a modified exit condition (runs until heap is empty). + vtr::vector cheapest_paths(this->rr_nodes_.size()); VTR_ASSERT_SAFE(this->heap_.is_valid()); @@ -92,12 +96,12 @@ vtr::vector SerialConnectionRouter::timing_drive HeapNode cheapest; while (this->heap_.try_pop(cheapest)) { - // inode with the cheapest total cost in current route tree to be expanded on + // Pop a new inode with the cheapest total cost in current route tree to be expanded on const auto& [new_total_cost, inode] = cheapest; - update_router_stats(this->router_stats_, - /*is_push=*/false, - inode, - this->rr_graph_); + update_serial_router_stats(this->router_stats_, + /*is_push=*/false, + inode, + this->rr_graph_); VTR_LOGV_DEBUG(this->router_debug_, " Popping node %d (cost: %g)\n", inode, new_total_cost); @@ -229,9 +233,6 @@ void SerialConnectionRouter::timing_driven_expand_neighbours(const RTExplo } } -// Conditionally adds to_node to the router heap (via path from from_node via from_edge). -// RR nodes outside the expanded bounding box specified in bounding_box are not added -// to the heap. template void SerialConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, RREdgeId from_edge, @@ -315,7 +316,6 @@ void SerialConnectionRouter::timing_driven_expand_neighbour(const RTExplor } } -// Add to_node to the heap, and also add any nodes which are connected by non-configurable edges template void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, const RTExploredNode& current, @@ -325,7 +325,7 @@ void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_p const auto& device_ctx = g_vpr_ctx.device(); const RRNodeId& from_node = current.index; - // Initialized to current + // Initialize the neighbor RTExploredNode RTExploredNode next; next.R_upstream = current.R_upstream; next.index = to_node; @@ -333,7 +333,7 @@ void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_p next.total_cost = std::numeric_limits::infinity(); // Not used directly next.backward_path_cost = current.backward_path_cost; - // Initalize RCV data struct if needed, otherwise it's set to nullptr + // Initialize RCV data struct if needed, otherwise it's set to nullptr this->rcv_path_manager.alloc_path_struct(next.path_data); // path_data variables are initialized to current values if (this->rcv_path_manager.is_enabled() && this->rcv_path_data[from_node]) { @@ -354,8 +354,8 @@ void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_p // be other (previously explored) paths to this node in the heap already, // but they will be pruned when we pop those heap nodes later as we'll see // they have inferior costs to what is in the `rr_node_route_inf` data for - // this node. - // FIXME: Adding a link to the FPT paper when it is public + // this node. More details can be found from the FPT'24 parallel connection + // router paper. // // When RCV is enabled, prune based on the RCV-specific total path cost (see // in `compute_node_cost_using_rcv` in `evaluate_timing_driven_node_costs`) @@ -378,10 +378,10 @@ void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_p update_cheapest(next, from_node); this->heap_.add_to_heap({new_total_cost, to_node}); - update_router_stats(this->router_stats_, - /*is_push=*/true, - to_node, - this->rr_graph_); + update_serial_router_stats(this->router_stats_, + /*is_push=*/true, + to_node, + this->rr_graph_); } else { VTR_LOGV_DEBUG(this->router_debug_, " Didn't expand to %d (%s)\n", to_node, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to_node, this->is_flat_).c_str()); @@ -394,19 +394,6 @@ void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_p } } -// Enable or disable RCV -template -void SerialConnectionRouter::set_rcv_enabled(bool enable) { - this->rcv_path_manager.set_enabled(enable); - if (enable) { - this->rcv_path_data.resize(this->rr_node_route_inf_.size()); - } -} - -//Unconditionally adds rt_node to the heap -// -//Note that if you want to respect rt_node.re_expand that is the caller's -//responsibility. template void SerialConnectionRouter::add_route_tree_node_to_heap( const RouteTreeNode& rt_node, @@ -422,14 +409,13 @@ void SerialConnectionRouter::add_route_tree_node_to_heap( if (!inside_bb(rt_node.inode, net_bb)) return; - // after budgets are loaded, calculate delay cost as described by RCV paper + // After budgets are loaded, calculate delay cost as described by RCV paper /* R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While * Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of * Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008.*/ // float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); if (!this->rcv_path_manager.is_enabled()) { - // tot_cost = backward_path_cost + cost_params.astar_fac * expected_cost; float expected_cost = this->router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); float tot_cost = backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); VTR_LOGV_DEBUG(this->router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", @@ -446,10 +432,6 @@ void SerialConnectionRouter::add_route_tree_node_to_heap( this->rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; this->rr_node_route_inf_[inode].R_upstream = R_upstream; this->heap_.push_back({tot_cost, inode}); - - // push_back_node(&this->heap_, this->rr_node_route_inf_, - // inode, tot_cost, RREdgeId::INVALID(), - // backward_path_cost, R_upstream); } else { float expected_total_cost = this->compute_node_cost_using_rcv(cost_params, inode, target_node, rt_node.Tdel, 0, R_upstream); @@ -463,15 +445,12 @@ void SerialConnectionRouter::add_route_tree_node_to_heap( this->rcv_path_data[inode]->backward_delay = rt_node.Tdel; this->heap_.push_back({expected_total_cost, inode}); - - // push_back_node_with_info(&this->heap_, inode, expected_total_cost, - // backward_path_cost, R_upstream, rt_node.Tdel, &this->rcv_path_manager); } - update_router_stats(this->router_stats_, - /*is_push=*/true, - inode, - this->rr_graph_); + update_serial_router_stats(this->router_stats_, + /*is_push=*/true, + inode, + this->rr_graph_); if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { this->router_stats_->rt_node_pushes[this->rr_graph_->node_type(inode)]++; @@ -513,3 +492,42 @@ std::unique_ptr make_serial_connection_router(e_heap_ heap_type); } } + +/** This function is only used for the serial connection router since some + * statistic variables in router_stats are not thread-safe for the parallel + * connection router. To update router_stats (more precisely heap_pushes/pops) + * for parallel connection router, we use the MultiQueue internal statistics + * method instead. */ +inline void update_serial_router_stats(RouterStats* router_stats, + bool is_push, + RRNodeId rr_node_id, + const RRGraphView* rr_graph) { + if (is_push) { + router_stats->heap_pushes++; + } else { + router_stats->heap_pops++; + } + + if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { + auto node_type = rr_graph->node_type(rr_node_id); + VTR_ASSERT(node_type != NUM_RR_TYPES); + + if (is_inter_cluster_node(*rr_graph, rr_node_id)) { + if (is_push) { + router_stats->inter_cluster_node_pushes++; + router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; + } else { + router_stats->inter_cluster_node_pops++; + router_stats->inter_cluster_node_type_cnt_pops[node_type]++; + } + } else { + if (is_push) { + router_stats->intra_cluster_node_pushes++; + router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; + } else { + router_stats->intra_cluster_node_pops++; + router_stats->intra_cluster_node_type_cnt_pops[node_type]++; + } + } + } +} diff --git a/vpr/src/route/serial_connection_router.h b/vpr/src/route/serial_connection_router.h index b0cc6e5c7f5..8899550ff22 100644 --- a/vpr/src/route/serial_connection_router.h +++ b/vpr/src/route/serial_connection_router.h @@ -5,14 +5,11 @@ #include "d_ary_heap.h" -// This class encapsulates the timing driven connection router. This class -// routes from some initial set of sources (via the input rt tree) to a -// particular sink. -// -// When the SerialConnectionRouter is used, it mutates the provided -// rr_node_route_inf. The routed path can be found by tracing from the sink -// node (which is returned) through the rr_node_route_inf. See -// update_traceback as an example of this tracing. +/** + * @class SerialConnectionRouter implements the AIR's serial timing-driven connection router + * @details This class routes from some initial set of sources (via the input rt tree) to a + * particular sink using single thread. + */ template class SerialConnectionRouter : public ConnectionRouter { public: @@ -33,17 +30,21 @@ class SerialConnectionRouter : public ConnectionRouter { std::chrono::duration(this->path_search_cumulative_time).count()); } - // Clear's the modified list. Should be called after reset_path_costs - // have been called. + /** + * @brief Clears the modified list per thread + * @note Should be called after reset_path_costs have been called + */ void clear_modified_rr_node_info() final { this->modified_rr_node_inf_.clear(); } - // Reset modified data in rr_node_route_inf based on modified_rr_node_inf. + /** + * @brief Resets modified data in rr_node_route_inf based on modified_rr_node_inf + */ void reset_path_costs() final { // Reset the node info stored in rr_node_route_inf variable ::reset_path_costs(this->modified_rr_node_inf_); - // Reset the node info stored inside the connection router + // Reset the node (RCV-related) info stored inside the connection router if (this->rcv_path_manager.is_enabled()) { for (const auto& node : this->modified_rr_node_inf_) { this->rcv_path_data[node] = nullptr; @@ -51,18 +52,36 @@ class SerialConnectionRouter : public ConnectionRouter { } } - // Finds a path from the route tree rooted at rt_root to all sinks - // available. - // - // Each element of the returned vector is a reachable sink. - // - // If cost_params.astar_fac is set to 0, this effectively becomes - // Dijkstra's algorithm with a modified exit condition (runs until heap is - // empty). When using cost_params.astar_fac = 0, for efficiency the - // RouterLookahead used should be the NoOpLookahead. - // - // Note: This routine is currently used only to generate information that - // may be helpful in debugging an architecture. + /** + * @brief Enables or disables RCV in connection router + * @note Enabling this will utilize extra path structures, as well as + * the RCV cost function. Ensure route budgets have been calculated + * before enabling this. + * @param enable Whether enabling RCV or not + */ + void set_rcv_enabled(bool enable) final { + this->rcv_path_manager.set_enabled(enable); + if (enable) { + this->rcv_path_data.resize(this->rr_node_route_inf_.size()); + } + } + + /** + * @brief Finds shortest paths from the route tree rooted at rt_root to all sinks available + * @note Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree which + * is spatially close to the sink is added to the heap. + * @note If cost_params.astar_fac is set to 0, this effectively becomes Dijkstra's algorithm with a + * modified exit condition (runs until heap is empty). When using cost_params.astar_fac = 0, for + * efficiency the RouterLookahead used should be the NoOpLookahead. + * @note This routine is currently used only to generate information that may be helpful in debugging + * an architecture. + * @param rt_root RouteTreeNode describing the current routing state + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param router_stats Update router statistics + * @param conn_params Parameters to guide the routing of the given connection + * @return A vector where each element is a reachable sink + */ vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( const RouteTreeNode& rt_root, const t_conn_cost_params& cost_params, @@ -70,23 +89,21 @@ class SerialConnectionRouter : public ConnectionRouter { RouterStats& router_stats, const ConnectionParameters& conn_params) final; - // Enable or disable RCV in connection router - // Enabling this will utilize extra path structures, as well as the RCV cost function - // - // Ensure route budgets have been calculated before enabling this - void set_rcv_enabled(bool enable) final; - protected: - // Mark that data associated with rr_node "inode" has been modified, and - // needs to be reset in reset_path_costs. + /** + * @brief Marks that data associated with rr_node 'inode' has + * been modified, and needs to be reset in reset_path_costs + */ inline void add_to_mod_list(RRNodeId inode) { if (std::isinf(this->rr_node_route_inf_[inode].path_cost)) { this->modified_rr_node_inf_.push_back(inode); } } - // Update the route path to the node `cheapest.index` via the path from - // `from_node` via `cheapest.prev_edge`. + /** + * @brief Updates the route path to the node `cheapest.index` + * via the path from `from_node` via `cheapest.prev_edge` + */ inline void update_cheapest(RTExploredNode& cheapest, const RRNodeId& from_node) { const RRNodeId& inode = cheapest.index; add_to_mod_list(inode); @@ -105,13 +122,28 @@ class SerialConnectionRouter : public ConnectionRouter { } } - // Find the shortest path from current heap to the sink node in the RR graph + /** + * @brief Finds the single shortest path from current heap to the sink node in the RR graph + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ void timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, const t_conn_cost_params& cost_params, const t_bb& bounding_box, const t_bb& target_bb) final; - // Expand this current node if it is a cheaper path. + /** + * @brief Expands this current node if it is a cheaper path + * @param from_node Current node ID being explored + * @param new_total_cost Identifier popped from the heap to detect if the element (pair) + (from_node, new_total_cost) was the most recently pushed element for from_node + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ void timing_driven_expand_cheapest( RRNodeId from_node, float new_total_cost, @@ -120,7 +152,14 @@ class SerialConnectionRouter : public ConnectionRouter { const t_bb& bounding_box, const t_bb& target_bb); - // Expand each neighbor of the current node. + /** + * @brief Expands each neighbor of the current node in the wave expansion + * @param current Current node being explored + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_node Target node ID to route to + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ void timing_driven_expand_neighbours( const RTExploredNode& current, const t_conn_cost_params& cost_params, @@ -128,11 +167,17 @@ class SerialConnectionRouter : public ConnectionRouter { RRNodeId target_node, const t_bb& target_bb); - // Conditionally adds to_node to the router heap (via path from current.index - // via from_edge). - // - // RR nodes outside bounding box specified in bounding_box are not added - // to the heap. + /** + * @brief Conditionally adds to_node to the router heap (via path from current.index via from_edge) + * @note RR nodes outside bounding box specified in bounding_box are not added to the heap. + * @param current Current node being explored + * @param from_edge Edge between the current node and the neighbor node + * @param to_node Neighbor node to be expanded + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_node Target node ID to route to + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ void timing_driven_expand_neighbour( const RTExploredNode& current, RREdgeId from_edge, @@ -142,8 +187,14 @@ class SerialConnectionRouter : public ConnectionRouter { RRNodeId target_node, const t_bb& target_bb); - // Add to_node to the heap, and also add any nodes which are connected by - // non-configurable edges + /** + * @brief Adds to_node to the heap, and also adds any nodes which are connected by non-configurable edges + * @param cost_params Cost function parameters + * @param current Current node being explored + * @param to_node Neighbor node to be expanded + * @param from_edge Edge between the current node and the neighbor node + * @param target_node Target node ID to route to + */ void timing_driven_add_to_heap( const t_conn_cost_params& cost_params, const RTExploredNode& current, @@ -151,18 +202,32 @@ class SerialConnectionRouter : public ConnectionRouter { RREdgeId from_edge, RRNodeId target_node); - // TODO: move this function into ConnectionRouter class - //Unconditionally adds rt_node to the heap - // - //Note that if you want to respect rt_node->re_expand that is the caller's - //responsibility. + /** + * @brief Unconditionally adds rt_node to the heap + * @note If you want to respect rt_node->re_expand that is the caller's responsibility. + * @todo Consider moving this function into the ConnectionRouter class after checking + * the different prune functions of the serial and parallel connection routers. + * @param rt_node RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param net_bb Do not push to heap if not in bounding box + */ void add_route_tree_node_to_heap( const RouteTreeNode& rt_node, RRNodeId target_node, const t_conn_cost_params& cost_params, - const t_bb& net_bb); - - // Find paths from current heap to all nodes in the RR graph + const t_bb& net_bb) final; + + /** + * @brief Finds shortest paths from current heap to all nodes in the RR graph + * + * Since there is no single *target* node this uses Dijkstra's algorithm with + * a modified exit condition (runs until heap is empty). + * + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @return A vector where each element contains the shortest route to a specific sink node + */ vtr::vector timing_driven_find_all_shortest_paths_from_heap( const t_conn_cost_params& cost_params, const t_bb& bounding_box) final; From d07398fb7d15233832bffda5ac92922d85afbbfc Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Fri, 4 Apr 2025 04:48:13 -0400 Subject: [PATCH 008/176] [Router] Fixed Interface Issues in NestedNetlistRouter and Code Formats Fixed the interface issues of ConnectionRouter in NestedNetlistRouter. Fixed code formats. Fixed typo in read_options.cpp. --- vpr/src/base/read_options.cpp | 2 +- vpr/src/route/NestedNetlistRouter.h | 53 ++++++++++++++++------ vpr/src/route/NestedNetlistRouter.tpp | 5 +- vpr/src/route/SerialNetlistRouter.h | 8 ++-- vpr/src/route/parallel_connection_router.h | 2 +- vpr/src/route/route_net.tpp | 4 +- vpr/src/route/serial_connection_router.h | 2 +- 7 files changed, 50 insertions(+), 26 deletions(-) diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index d8eff3053d1..64ea014643d 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -2688,7 +2688,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio " heuristic'. The 'stopping heuristic' must be admissible for the path search" " algorithm to guarantee optimal paths and be deterministic. Values of this" " parameter are architecture-specific and have to be empirically found." - " This parameter has no effect if --enable_parallel_connection_router is not set." + " This parameter has no effect if --enable_parallel_connection_router is not set.") .default_value("0.0") .show_in(argparse::ShowIn::HELP_ONLY); diff --git a/vpr/src/route/NestedNetlistRouter.h b/vpr/src/route/NestedNetlistRouter.h index 6870842af8f..fec3820ce45 100644 --- a/vpr/src/route/NestedNetlistRouter.h +++ b/vpr/src/route/NestedNetlistRouter.h @@ -4,6 +4,8 @@ #include "netlist_routers.h" #include "vtr_optional.h" #include "vtr_thread_pool.h" +#include "serial_connection_router.h" +#include "parallel_connection_router.h" #include /* Add cmd line option for this later */ @@ -49,7 +51,11 @@ class NestedNetlistRouter : public NetlistRouter { , _choking_spots(choking_spots) , _is_flat(is_flat) , _thread_pool(MAX_THREADS) {} - ~NestedNetlistRouter() {} + ~NestedNetlistRouter() { + for (auto& [_, router] : _routers_th) { + delete router; + } + } /** Run a single iteration of netlist routing for this->_net_list. This usually means calling * \ref route_net for each net, which will handle other global updates. @@ -67,19 +73,38 @@ class NestedNetlistRouter : public NetlistRouter { /** Route all nets in a PartitionTree node and add its children to the task queue. */ void route_partition_tree_node(PartitionTreeNode& node); - ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + ConnectionRouter* _make_router(const RouterLookahead* router_lookahead, + const t_router_opts& router_opts, + bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); - return ConnectionRouter( - device_ctx.grid, - *router_lookahead, - device_ctx.rr_graph.rr_nodes(), - &device_ctx.rr_graph, - device_ctx.rr_rc_data, - device_ctx.rr_graph.rr_switch(), - route_ctx.rr_node_route_inf, - is_flat); + if (!router_opts.enable_parallel_connection_router) { + // Serial Connection Router + return new SerialConnectionRouter( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat); + } else { + // Parallel Connection Router + return new ParallelConnectionRouter( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat, + router_opts.multi_queue_num_threads, + router_opts.multi_queue_num_queues, + router_opts.multi_queue_direct_draining); + } } /* Context fields. Most of them will be forwarded to route_net (see route_net.tpp) */ @@ -109,17 +134,17 @@ class NestedNetlistRouter : public NetlistRouter { /* Thread-local storage. * These are maps because thread::id is a random integer instead of 1, 2, ... */ - std::unordered_map> _routers_th; + std::unordered_map*> _routers_th; std::unordered_map _results_th; std::mutex _storage_mutex; /** Get a thread-local ConnectionRouter. We lock the id->router lookup, but this is * accessed once per partition so the overhead should be small */ - ConnectionRouter& get_thread_router() { + ConnectionRouter* get_thread_router() { auto id = std::this_thread::get_id(); std::lock_guard lock(_storage_mutex); if (!_routers_th.count(id)) { - _routers_th.emplace(id, _make_router(_router_lookahead, _is_flat)); + _routers_th.emplace(id, _make_router(_router_lookahead, _router_opts, _is_flat)); } return _routers_th.at(id); } diff --git a/vpr/src/route/NestedNetlistRouter.tpp b/vpr/src/route/NestedNetlistRouter.tpp index 333be28ea3b..9a7aa91a3f3 100644 --- a/vpr/src/route/NestedNetlistRouter.tpp +++ b/vpr/src/route/NestedNetlistRouter.tpp @@ -66,10 +66,9 @@ void NestedNetlistRouter::route_partition_tree_node(PartitionTreeNode& /* Route all nets in this node serially */ for (auto net_id : nets) { auto& results = get_thread_results(); - auto& router = get_thread_router(); auto flags = route_net( - router, + *get_thread_router(), _net_list, net_id, _itry, @@ -131,7 +130,7 @@ void NestedNetlistRouter::handle_bb_updated_nets(const std::vector void NestedNetlistRouter::set_rcv_enabled(bool x) { for (auto& [_, router] : _routers_th) { - router.set_rcv_enabled(x); + router->set_rcv_enabled(x); } } diff --git a/vpr/src/route/SerialNetlistRouter.h b/vpr/src/route/SerialNetlistRouter.h index 896c5173b13..4529a4e15fd 100644 --- a/vpr/src/route/SerialNetlistRouter.h +++ b/vpr/src/route/SerialNetlistRouter.h @@ -44,9 +44,9 @@ class SerialNetlistRouter : public NetlistRouter { void set_timing_info(std::shared_ptr timing_info); private: - ConnectionRouterInterface* _make_router(const RouterLookahead* router_lookahead, - const t_router_opts& router_opts, - bool is_flat) { + ConnectionRouter* _make_router(const RouterLookahead* router_lookahead, + const t_router_opts& router_opts, + bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); @@ -78,7 +78,7 @@ class SerialNetlistRouter : public NetlistRouter { } } /* Context fields */ - ConnectionRouterInterface* _router; + ConnectionRouter* _router; const Netlist<>& _net_list; const t_router_opts& _router_opts; CBRR& _connections_inf; diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h index 12daba4a293..960e2cd2348 100644 --- a/vpr/src/route/parallel_connection_router.h +++ b/vpr/src/route/parallel_connection_router.h @@ -186,7 +186,7 @@ class ParallelConnectionRouter : public ConnectionRouter { ~ParallelConnectionRouter() { this->is_router_destroying_ = true; // signal the helper threads to exit - this->thread_barrier_.wait(); // wait until all threads reach the barrier + this->thread_barrier_.wait(); // wait until all threads reach the barrier VTR_LOG("Parallel Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", std::chrono::duration(this->path_search_cumulative_time).count()); diff --git a/vpr/src/route/route_net.tpp b/vpr/src/route/route_net.tpp index a30b2e07adc..1a5715b7341 100644 --- a/vpr/src/route/route_net.tpp +++ b/vpr/src/route/route_net.tpp @@ -17,7 +17,7 @@ /** Attempt to route a single net. * - * @param router The ConnectionRouter instance + * @param router The ConnectionRouterType instance * @param net_list Input netlist * @param net_id * @param itry # of iteration @@ -384,7 +384,7 @@ inline NetResultFlags pre_route_to_clock_root(ConnectionRouterType& router, * In the process, update global pathfinder costs, rr_node_route_inf and extend the global RouteTree * for this net. * - * @param router The ConnectionRouter instance + * @param router The ConnectionRouterType instance * @param net_list Input netlist * @param net_id * @param itarget # of this connection in the net (only used for debug output) diff --git a/vpr/src/route/serial_connection_router.h b/vpr/src/route/serial_connection_router.h index 8899550ff22..7dbd209203a 100644 --- a/vpr/src/route/serial_connection_router.h +++ b/vpr/src/route/serial_connection_router.h @@ -138,7 +138,7 @@ class SerialConnectionRouter : public ConnectionRouter { * @brief Expands this current node if it is a cheaper path * @param from_node Current node ID being explored * @param new_total_cost Identifier popped from the heap to detect if the element (pair) - (from_node, new_total_cost) was the most recently pushed element for from_node + * (from_node, new_total_cost) was the most recently pushed element for from_node * @param target_node Target node ID to route to * @param cost_params Cost function parameters * @param bounding_box Keep search confined to this bounding box From ebc56a3be1500896fe2a080ad6efc7462e4c899c Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Fri, 4 Apr 2025 05:27:34 -0400 Subject: [PATCH 009/176] [Router] Updated Command-Line Usage for Parallel Connection Router Updated the command-line usage for parallel connection router in both Read the Docs and read_options.cpp. --- doc/src/vpr/command_line_usage.rst | 131 ++++++++++++++++++++++------- vpr/src/base/read_options.cpp | 4 +- 2 files changed, 103 insertions(+), 32 deletions(-) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index c370562fd58..8e869efde50 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -47,12 +47,12 @@ By default VPR will perform a binary search routing to find the minimum channel Detailed Command-line Options ----------------------------- -VPR has a lot of options. Running :option:`vpr --help` will display all the available options and their usage information. +VPR has a lot of options. Running :option:`vpr --help` will display all the available options and their usage information. .. option:: -h, --help Display help message then exit. - + The options most people will be interested in are: * :option:`--route_chan_width` (route at a fixed channel width), and @@ -208,7 +208,7 @@ General Options * Any string matching ``name`` attribute of a device layout defined with a ```` tag in the :ref:`arch_grid_layout` section of the architecture file. If the value specified is neither ``auto`` nor matches the ``name`` attribute value of a ```` tag, VPR issues an error. - + .. note:: If the only layout in the architecture file is a single device specified using ````, it is recommended to always specify the ``--device`` option; this prevents the value ``--device auto`` from interfering with operations supported only for ```` grids. **Default:** ``auto`` @@ -892,7 +892,7 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe .. option:: --place_agent_algorithm {e_greedy | softmax} - Controls which placement RL agent is used. + Controls which placement RL agent is used. **Default:** ``softmax`` @@ -914,10 +914,10 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe .. option:: --place_reward_fun {basic | nonPenalizing_basic | runtime_aware | WLbiased_runtime_aware} - The reward function used by the placement RL agent to learn the best action at each anneal stage. + The reward function used by the placement RL agent to learn the best action at each anneal stage. + + .. note:: The latter two are only available for timing-driven placement. - .. note:: The latter two are only available for timing-driven placement. - **Default:** ``WLbiased_runtime_aware`` .. option:: --place_agent_space {move_type | move_block_type} @@ -927,20 +927,20 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe **Default:** ``move_block_type`` .. option:: --place_quench_only {on | off} - + If this option is set to ``on``, the placement will skip the annealing phase and only perform the placement quench. - This option is useful when the the quality of initial placement is good enough and there is no need to perform the + This option is useful when the the quality of initial placement is good enough and there is no need to perform the annealing phase. **Default:** ``off`` .. option:: --placer_debug_block - + .. note:: This option is likely only of interest to developers debugging the placement algorithm - Controls which block the placer produces detailed debug information for. - + Controls which block the placer produces detailed debug information for. + If the block being moved has the same ID as the number assigned to this parameter, the placer will print debugging information about it. * For values >= 0, the value is the block ID for which detailed placer debug information should be produced. @@ -952,7 +952,7 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe **Default:** ``-2`` .. option:: --placer_debug_net - + .. note:: This option is likely only of interest to developers debugging the placement algorithm Controls which net the placer produces detailed debug information for. @@ -996,7 +996,7 @@ The following options are only valid when the placement engine is in timing-driv .. option:: --quench_recompute_divider - Controls how many times the placer performs a timing analysis to update its criticality estimates during a quench. + Controls how many times the placer performs a timing analysis to update its criticality estimates during a quench. If unspecified, uses the value from --inner_loop_recompute_divider. **Default:** ``0`` @@ -1080,7 +1080,7 @@ The following options are only valid when the placement engine is in timing-driv NoC Options ^^^^^^^^^^^^^^ -The following options are only used when FPGA device and netlist contain a NoC router. +The following options are only used when FPGA device and netlist contain a NoC router. .. option:: --noc {on | off} @@ -1090,7 +1090,7 @@ The following options are only used when FPGA device and netlist contain a NoC r **Default:** ``off`` .. option:: --noc_flows_file - + XML file containing the list of traffic flows within the NoC (communication between routers). .. note:: noc_flows_file are required to specify if NoC optimization is turned on (--noc on). @@ -1098,7 +1098,7 @@ The following options are only used when FPGA device and netlist contain a NoC r .. option:: --noc_routing_algorithm {xy_routing | bfs_routing | west_first_routing | north_last_routing | negative_first_routing | odd_even_routing} Controls the algorithm used by the NoC to route packets. - + * ``xy_routing`` Uses the direction oriented routing algorithm. This is recommended to be used with mesh NoC topologies. * ``bfs_routing`` Uses the breadth first search algorithm. The objective is to find a route that uses a minimum number of links. This algorithm is not guaranteed to generate deadlock-free traffic flow routes, but can be used with any NoC topology. * ``west_first_routing`` Uses the west-first routing algorithm. This is recommended to be used with mesh NoC topologies. @@ -1111,11 +1111,11 @@ The following options are only used when FPGA device and netlist contain a NoC r .. option:: --noc_placement_weighting Controls the importance of the NoC placement parameters relative to timing and wirelength of the design. - + * ``noc_placement_weighting = 0`` means the placement is based solely on timing and wirelength. * ``noc_placement_weighting = 1`` means noc placement is considered equal to timing and wirelength. * ``noc_placement_weighting > 1`` means the placement is increasingly dominated by NoC parameters. - + **Default:** ``5.0`` .. option:: --noc_aggregate_bandwidth_weighting @@ -1133,7 +1133,7 @@ The following options are only used when FPGA device and netlist contain a NoC r Other positive numbers specify the importance of meeting latency constraints compared to other NoC-related cost terms. Weighting factors for NoC-related cost terms are normalized internally. Therefore, their absolute values are not important, and only their relative ratios determine the importance of each cost term. - + **Default:** ``0.6`` .. option:: --noc_latency_weighting @@ -1143,7 +1143,7 @@ The following options are only used when FPGA device and netlist contain a NoC r Other positive numbers specify the importance of minimizing aggregate latency compared to other NoC-related cost terms. Weighting factors for NoC-related cost terms are normalized internally. Therefore, their absolute values are not important, and only their relative ratios determine the importance of each cost term. - + **Default:** ``0.02`` .. option:: --noc_congestion_weighting @@ -1159,11 +1159,11 @@ The following options are only used when FPGA device and netlist contain a NoC r .. option:: --noc_swap_percentage Sets the minimum fraction of swaps attempted by the placer that are NoC blocks. - This value is an integer ranging from [0-100]. - - * ``0`` means NoC blocks will be moved at the same rate as other blocks. + This value is an integer ranging from [0-100]. + + * ``0`` means NoC blocks will be moved at the same rate as other blocks. * ``100`` means all swaps attempted by the placer are NoC router blocks. - + **Default:** ``0`` .. option:: --noc_placement_file_name @@ -1249,7 +1249,7 @@ Analytical Placement is generally split into three stages: * ``none`` Do not use any Detailed Placer. - * ``annealer`` Use the Annealer from the Placement stage as a Detailed Placer. This will use the same Placer Options from the Place stage to configure the annealer. + * ``annealer`` Use the Annealer from the Placement stage as a Detailed Placer. This will use the same Placer Options from the Place stage to configure the annealer. **Default:** ``annealer`` @@ -1326,8 +1326,8 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout .. option:: --max_pres_fac - Sets the maximum present overuse penalty factor that can ever result during routing. Should always be less than 1e25 or so to prevent overflow. - Smaller values may help prevent circuitous routing in difficult routing problems, but may increase + Sets the maximum present overuse penalty factor that can ever result during routing. Should always be less than 1e25 or so to prevent overflow. + Smaller values may help prevent circuitous routing in difficult routing problems, but may increase the number of routing iterations needed and hence runtime. **Default:** ``1000.0`` @@ -1406,7 +1406,7 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout .. option:: --router_algorithm {timing_driven | parallel | parallel_decomp} - Selects which router algorithm to use. + Selects which router algorithm to use. * ``timing_driven`` is the default single-threaded PathFinder algorithm. @@ -1488,13 +1488,84 @@ The following options are only valid when the router is in timing-driven mode (t **Default:** ``0.0`` .. option:: --router_profiler_astar_fac - + Controls the directedness of the timing-driven router's exploration when doing router delay profiling of an architecture. The router delay profiling step is currently used to calculate the place delay matrix lookup. Values between 1 and 2 are resonable; higher values trade some quality for reduced run-time. **Default:** ``1.2`` +.. option:: --enable_parallel_connection_router {on | off} + + Controls whether the MultiQueue-based parallel connection router is used during a single connection routing. + + When enabled, the parallel connection router accelerates the path search for individual source-sink connections using + multi-threading without altering the net routing order. + + **Default:** ``off`` + +.. option:: --post_target_prune_fac + + Controls the post-target pruning heuristic calculation in the parallel connection router. + + This parameter is used as a multiplicative factor applied to the VPR heuristic (not guaranteed to be admissible, i.e., + might over-predict the cost to the sink) to calculate the 'stopping heuristic' when pruning nodes after the target has + been reached. The 'stopping heuristic' must be admissible for the path search algorithm to guarantee optimal paths and + be deterministic. + + Values of this parameter are architecture-specific and have to be empirically found. + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``1.2`` + +.. option:: --post_target_prune_offset + + Controls the post-target pruning heuristic calculation in the parallel connection router. + + This parameter is used as a subtractive offset together with :option:`--post_target_prune_fac` to apply an affine + transformation on the VPR heuristic to calculate the 'stopping heuristic'. The 'stopping heuristic' must be admissible + for the path search algorithm to guarantee optimal paths and be deterministic. + + Values of this parameter are architecture-specific and have to be empirically found. + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``0.0`` + +.. option:: --multi_queue_num_threads + + Controls the number of threads used by MultiQueue-based parallel connection router. + + If not explicitly specified, defaults to 1, implying the parallel connection router works in 'serial' mode using only + one main thread to route. + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``1`` + +.. option:: --multi_queue_num_queues + + Controls the number of queues used by MultiQueue in the parallel connection router. + + Must be set >= 2. A common configuration for this parameter is the number of threads used by MultiQueue * 4 (the number + of queues per thread). + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``2`` + +.. option:: --multi_queue_direct_draining {on | off} + + Controls whether to enable queue draining optimization for MultiQueue-based parallel connection router. + + When enabled, queues can be emptied quickly by draining all elements if no further solutions need to be explored in the + path search to guarantee optimality or determinism after reaching the target. + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``off`` + .. option:: --max_criticality Sets the maximum fraction of routing cost that can come from delay (vs. coming from routability) for any net. diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 9d1a13dc58e..616ddf472f0 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -2704,8 +2704,8 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio route_timing_grp.add_argument(args.enable_parallel_connection_router, "--enable_parallel_connection_router") .help( - "Controls whether the parallel connection router is used during a single connection routing." - " When enabled, the parallel connection router accelerates the path search for individual" + "Controls whether the MultiQueue-based parallel connection router is used during a single connection" + " routing. When enabled, the parallel connection router accelerates the path search for individual" " source-sink connections using multi-threading without altering the net routing order.") .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); From 19ff0fb90d9eb135c020d13d0b0757f0c026a1cc Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Fri, 4 Apr 2025 05:37:13 -0400 Subject: [PATCH 010/176] [Router] Added Regression Tests for Parallel Connection Router Added regression tests for parallel connection router by appending extra sets of configurations to those VTR flow regression tests previously selected by Fahri for testing coarse-grained parallel router. Removed VPR connection router test (vpr/test/test_connection_router.cpp), since it has been out-dated for a very long time and has caused lots of trouble for running VPR C++ tests locally. --- vpr/test/test_connection_router.cpp | 196 ------------------ .../koios_test/config/config.txt | 3 + .../strong_flat_router/config/config.txt | 3 + .../strong_multiclock/config/config.txt | 3 + .../strong_timing/config/config.txt | 3 + .../config/config.txt | 6 + 6 files changed, 18 insertions(+), 196 deletions(-) delete mode 100644 vpr/test/test_connection_router.cpp diff --git a/vpr/test/test_connection_router.cpp b/vpr/test/test_connection_router.cpp deleted file mode 100644 index 1169d5f4b3d..00000000000 --- a/vpr/test/test_connection_router.cpp +++ /dev/null @@ -1,196 +0,0 @@ -#include -#include "catch2/catch_test_macros.hpp" - -#include "route_net.h" -#include "rr_graph_fwd.h" -#include "vpr_api.h" -#include "vpr_signal_handler.h" -#include "globals.h" -#include "net_delay.h" -#include "place_and_route.h" -#include "serial_connection_router.h" -#include "router_delay_profiling.h" - -static constexpr const char kArchFile[] = "../../vtr_flow/arch/timing/k6_frac_N10_mem32K_40nm.xml"; -static constexpr int kMaxHops = 10; - -namespace { - -// Route from source_node to sink_node, returning either the delay, or infinity if unroutable. -static float do_one_route(RRNodeId source_node, - RRNodeId sink_node, - const t_det_routing_arch& det_routing_arch, - const t_router_opts& router_opts, - const std::vector& segment_inf) { - bool is_flat = router_opts.flat_routing; - auto& device_ctx = g_vpr_ctx.device(); - - RouteTree tree((RRNodeId(source_node))); - - // Update base costs according to fanout and criticality rules. - update_rr_base_costs(1); - - // Bounding box includes the entire grid. - t_bb bounding_box; - bounding_box.xmin = 0; - bounding_box.xmax = device_ctx.grid.width() + 1; - bounding_box.ymin = 0; - bounding_box.ymax = device_ctx.grid.height() + 1; - bounding_box.layer_min = 0; - bounding_box.layer_max = device_ctx.grid.get_num_layers() - 1; - - t_conn_cost_params cost_params; - cost_params.criticality = router_opts.max_criticality; - cost_params.astar_fac = router_opts.astar_fac; - cost_params.astar_offset = router_opts.astar_offset; - cost_params.bend_cost = router_opts.bend_cost; - - const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; - route_budgets budgeting_inf(net_list, is_flat); - - RouterStats router_stats; - auto router_lookahead = make_router_lookahead(det_routing_arch, - router_opts.lookahead_type, - router_opts.write_router_lookahead, - router_opts.read_router_lookahead, - segment_inf, - is_flat); - - // TODO: adding tests for parallel connection router - SerialConnectionRouter router( - device_ctx.grid, - *router_lookahead, - device_ctx.rr_graph.rr_nodes(), - &device_ctx.rr_graph, - device_ctx.rr_rc_data, - device_ctx.rr_graph.rr_switch(), - g_vpr_ctx.mutable_routing().rr_node_route_inf, - is_flat); - - // Find the cheapest route if possible. - bool found_path; - RTExploredNode cheapest; - ConnectionParameters conn_params(ParentNetId::INVALID(), - -1, - false, - std::unordered_map()); - std::tie(found_path, std::ignore, cheapest) = router.timing_driven_route_connection_from_route_tree(tree.root(), - sink_node, - cost_params, - bounding_box, - router_stats, - conn_params); - - // Default delay is infinity, which indicates that a route was not found. - float delay = std::numeric_limits::infinity(); - if (found_path) { - // Check that the route goes to the requested sink. - REQUIRE(RRNodeId(cheapest.index) == sink_node); - - // Get the delay - vtr::optional rt_node_of_sink; - std::tie(std::ignore, rt_node_of_sink) = tree.update_from_heap(&cheapest, OPEN, nullptr, router_opts.flat_routing); - delay = rt_node_of_sink.value().Tdel; - } - - // Reset for the next router call. - router.reset_path_costs(); - return delay; -} - -// Find a source and a sink by walking edges. -std::tuple find_source_and_sink() { - auto& device_ctx = g_vpr_ctx.device(); - auto& rr_graph = device_ctx.rr_graph; - - // Current longest walk - std::tuple longest = std::make_tuple(RRNodeId::INVALID(), RRNodeId::INVALID(), 0); - - // Start from each RR node - for (size_t id = 0; id < rr_graph.num_nodes(); id++) { - RRNodeId source(id), sink = source; - for (int hops = 0; hops < kMaxHops; hops++) { - // Take the first edge, if there is one. - auto edge = rr_graph.node_first_edge(sink); - if (edge == rr_graph.node_last_edge(sink)) { - break; - } - sink = rr_graph.rr_nodes().edge_sink_node(edge); - - // If this is the new longest walk, store it. - if (hops > std::get<2>(longest)) { - longest = std::make_tuple(source, sink, hops); - } - } - } - return longest; -} - -// Test that the router can route nets individually, not considering congestion. -// This is a minimal timing driven routing test that can be used as documentation, -// and as a starting point for experimentation. -TEST_CASE("connection_router", "[vpr]") { - // Minimal setup - auto options = t_options(); - auto arch = t_arch(); - auto vpr_setup = t_vpr_setup(); - - vpr_install_signal_handler(); - vpr_initialize_logging(); - - // Command line arguments - const char* argv[] = { - "test_vpr", - kArchFile, - "wire.eblif", - "--route_chan_width", "100"}; - vpr_init(sizeof(argv) / sizeof(argv[0]), argv, - &options, &vpr_setup, &arch); - - vpr_create_device_grid(vpr_setup, arch); - vpr_setup_clock_networks(vpr_setup, arch); - auto det_routing_arch = &vpr_setup.RoutingArch; - auto& router_opts = vpr_setup.RouterOpts; - t_graph_type graph_directionality; - - if (router_opts.route_type == GLOBAL) { - graph_directionality = GRAPH_BIDIR; - } else { - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); - } - - auto chan_width = init_chan(vpr_setup.RouterOpts.fixed_channel_width, arch.Chans, graph_directionality); - - alloc_routing_structs( - chan_width, - vpr_setup.RouterOpts, - &vpr_setup.RoutingArch, - vpr_setup.Segments, - arch.directs, - router_opts.flat_routing); - - // Find a source and sink to route - RRNodeId source_rr_node, sink_rr_node; - int hops; - std::tie(source_rr_node, sink_rr_node, hops) = find_source_and_sink(); - - // Check that the route will be non-trivial - REQUIRE(source_rr_node != sink_rr_node); - REQUIRE(hops >= 3); - - // Find the route - float delay = do_one_route(source_rr_node, - sink_rr_node, - vpr_setup.RoutingArch, - vpr_setup.RouterOpts, - vpr_setup.Segments); - - // Check that a route was found - REQUIRE(delay < std::numeric_limits::infinity()); - - // Clean up - free_routing_structs(); - vpr_free_all(arch, vpr_setup); -} - -} // namespace diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt index 1ccd16490d7..623a460bc36 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt @@ -38,3 +38,6 @@ pass_requirements_file=pass_requirements.txt script_params_common=-track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel +script_params_list_add = --enable_parallel_connection_router +script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt index d59d17d4831..cd2605467c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt @@ -27,3 +27,6 @@ pass_requirements_file=pass_requirements.txt script_params_common=-track_memory_usage --route_chan_width 100 --max_router_iterations 100 --router_lookahead map --flat_routing on script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 +script_params_list_add = --enable_parallel_connection_router +script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt index dbceb44a4dc..feb50b99350 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt @@ -27,3 +27,6 @@ pass_requirements_file=pass_requirements_multiclock.txt script_params_common=-starting_stage vpr -sdc_file tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/multiclock.sdc script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 +script_params_list_add = --enable_parallel_connection_router +script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt index dac263af64c..f8843fa41e0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt @@ -27,3 +27,6 @@ pass_requirements_file=pass_requirements.txt script_params_common = -track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 +script_params_list_add = --enable_parallel_connection_router +script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt index 17b20f60f24..fe98854a2da 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt @@ -31,3 +31,9 @@ script_params_list_add = --timing_update_type incremental script_params_list_add = --timing_update_type incremental --quench_recompute_divider 999999999 #Do post-move incremental STA during quench script_params_list_add = --timing_update_type incremental --router_algorithm parallel --num_workers 4 # rarely exercised code path script_params_list_add = --timing_update_type full --router_algorithm parallel --num_workers 4 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining +script_params_list_add = --timing_update_type full --enable_parallel_connection_router +script_params_list_add = --timing_update_type full --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining From b109d139b558b381a7b0e0aedc53b4ac7210934a Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Fri, 4 Apr 2025 06:02:07 -0400 Subject: [PATCH 011/176] Fixed Code Formatting Issue Fixed a weird code formatting issue in libs/librtlnumber/src/include/ internal_bits.hpp. GitHub CI said the file failed dev/check-format.sh, however, the same script runs perfectly in my local environment. Double checked the version of clang-format, which seemed to be the same as CI. Directly copied the file from the GitHub repo to resolve this issue. --- libs/librtlnumber/src/include/internal_bits.hpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libs/librtlnumber/src/include/internal_bits.hpp b/libs/librtlnumber/src/include/internal_bits.hpp index ffefb5a4d9a..0d5c7388470 100644 --- a/libs/librtlnumber/src/include/internal_bits.hpp +++ b/libs/librtlnumber/src/include/internal_bits.hpp @@ -27,14 +27,14 @@ constexpr short integer_t_size = (sizeof(integer_t) * 8); } #define unroll_1d(lut) \ - {lut[_0], lut[_1], lut[_x], lut[_z]} + { lut[_0], lut[_1], lut[_x], lut[_z] } #define unroll_2d(lut) \ - {unroll_1d(lut[_0]), unroll_1d(lut[_1]), unroll_1d(lut[_x]), unroll_1d(lut[_z])} + { unroll_1d(lut[_0]), unroll_1d(lut[_1]), unroll_1d(lut[_x]), unroll_1d(lut[_z]) } #define unroll_1d_invert(lut) \ - {l_not[lut[_0]], l_not[lut[_1]], l_not[lut[_x]], l_not[lut[_z]]} + { l_not[lut[_0]], l_not[lut[_1]], l_not[lut[_x]], l_not[lut[_z]] } #define unroll_2d_invert(lut) \ - {unroll_1d_invert(lut[_0]), unroll_1d_invert(lut[_1]), unroll_1d_invert(lut[_x]), unroll_1d_invert(lut[_z])} + { unroll_1d_invert(lut[_0]), unroll_1d_invert(lut[_1]), unroll_1d_invert(lut[_x]), unroll_1d_invert(lut[_z]) } namespace BitSpace { typedef uint8_t bit_value_t; From f73212cd76b65e58ce58624a26204c3c8bb3c070 Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Fri, 11 Apr 2025 13:48:11 -0400 Subject: [PATCH 012/176] [Router] Fixed `No source in route tree` in ParallelConnectionRouter The `No source in route tree` bug in ParallelConnectionRouter (since commit 875b98e) has been fixed. It turns out that putting another member variable `MultiQueueDAryHeap heap_` in the derived class ParallelConnectionRouter together with the existing `HeapImplementation heap_` in the base class ConnectionRouter causes the issue. The solution is to keep `heap_` only in the base class and use `ConnectionRouter>` rather than `ConnectionRouter` for deriving the parallel connection router. Please note that ParallelConnectionRouter still has some bugs (i.e., getting stuck in the MultiQueue pop). This commit is not fully working. Please do not use it for any experiments. Updated the previously incorrect command-line options for the parallel connection router in the regression tests. --- vpr/src/route/NestedNetlistRouter.h | 21 ++++++++----------- vpr/src/route/SerialNetlistRouter.h | 16 +++++++------- vpr/src/route/connection_router.h | 3 --- vpr/src/route/multi_queue_d_ary_heap.h | 17 +++++++++------ vpr/src/route/parallel_connection_router.cpp | 4 ++-- vpr/src/route/parallel_connection_router.h | 10 ++++----- vpr/src/route/serial_connection_router.h | 3 +++ .../koios_test/config/config.txt | 6 +++--- .../strong_flat_router/config/config.txt | 6 +++--- .../strong_multiclock/config/config.txt | 6 +++--- .../strong_timing/config/config.txt | 6 +++--- .../config/config.txt | 12 +++++------ 12 files changed, 54 insertions(+), 56 deletions(-) diff --git a/vpr/src/route/NestedNetlistRouter.h b/vpr/src/route/NestedNetlistRouter.h index fec3820ce45..9aa2a675e62 100644 --- a/vpr/src/route/NestedNetlistRouter.h +++ b/vpr/src/route/NestedNetlistRouter.h @@ -6,6 +6,7 @@ #include "vtr_thread_pool.h" #include "serial_connection_router.h" #include "parallel_connection_router.h" +#include #include /* Add cmd line option for this later */ @@ -51,11 +52,7 @@ class NestedNetlistRouter : public NetlistRouter { , _choking_spots(choking_spots) , _is_flat(is_flat) , _thread_pool(MAX_THREADS) {} - ~NestedNetlistRouter() { - for (auto& [_, router] : _routers_th) { - delete router; - } - } + ~NestedNetlistRouter() {} /** Run a single iteration of netlist routing for this->_net_list. This usually means calling * \ref route_net for each net, which will handle other global updates. @@ -73,15 +70,15 @@ class NestedNetlistRouter : public NetlistRouter { /** Route all nets in a PartitionTree node and add its children to the task queue. */ void route_partition_tree_node(PartitionTreeNode& node); - ConnectionRouter* _make_router(const RouterLookahead* router_lookahead, - const t_router_opts& router_opts, - bool is_flat) { + std::shared_ptr _make_router(const RouterLookahead* router_lookahead, + const t_router_opts& router_opts, + bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); if (!router_opts.enable_parallel_connection_router) { // Serial Connection Router - return new SerialConnectionRouter( + return std::make_shared>( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -92,7 +89,7 @@ class NestedNetlistRouter : public NetlistRouter { is_flat); } else { // Parallel Connection Router - return new ParallelConnectionRouter( + return std::make_shared>( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -134,13 +131,13 @@ class NestedNetlistRouter : public NetlistRouter { /* Thread-local storage. * These are maps because thread::id is a random integer instead of 1, 2, ... */ - std::unordered_map*> _routers_th; + std::unordered_map> _routers_th; std::unordered_map _results_th; std::mutex _storage_mutex; /** Get a thread-local ConnectionRouter. We lock the id->router lookup, but this is * accessed once per partition so the overhead should be small */ - ConnectionRouter* get_thread_router() { + std::shared_ptr get_thread_router() { auto id = std::this_thread::get_id(); std::lock_guard lock(_storage_mutex); if (!_routers_th.count(id)) { diff --git a/vpr/src/route/SerialNetlistRouter.h b/vpr/src/route/SerialNetlistRouter.h index 4529a4e15fd..d56414d00af 100644 --- a/vpr/src/route/SerialNetlistRouter.h +++ b/vpr/src/route/SerialNetlistRouter.h @@ -34,9 +34,7 @@ class SerialNetlistRouter : public NetlistRouter { , _routing_predictor(routing_predictor) , _choking_spots(choking_spots) , _is_flat(is_flat) {} - ~SerialNetlistRouter() { - delete _router; - } + ~SerialNetlistRouter() {} RouteIterResults route_netlist(int itry, float pres_fac, float worst_neg_slack); void handle_bb_updated_nets(const std::vector& nets); @@ -44,15 +42,15 @@ class SerialNetlistRouter : public NetlistRouter { void set_timing_info(std::shared_ptr timing_info); private: - ConnectionRouter* _make_router(const RouterLookahead* router_lookahead, - const t_router_opts& router_opts, - bool is_flat) { + std::unique_ptr _make_router(const RouterLookahead* router_lookahead, + const t_router_opts& router_opts, + bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); if (!router_opts.enable_parallel_connection_router) { // Serial Connection Router - return new SerialConnectionRouter( + return std::make_unique>( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -63,7 +61,7 @@ class SerialNetlistRouter : public NetlistRouter { is_flat); } else { // Parallel Connection Router - return new ParallelConnectionRouter( + return std::make_unique>( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -78,7 +76,7 @@ class SerialNetlistRouter : public NetlistRouter { } } /* Context fields */ - ConnectionRouter* _router; + std::unique_ptr _router; const Netlist<>& _net_list; const t_router_opts& _router_opts; CBRR& _connections_inf; diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/connection_router.h index 99a8b393c94..f5bb7c57aa9 100644 --- a/vpr/src/route/connection_router.h +++ b/vpr/src/route/connection_router.h @@ -332,9 +332,6 @@ class ConnectionRouter : public ConnectionRouterInterface { /** Is flat router enabled or not? */ bool is_flat_; - /** Node IDs of modified nodes in rr_node_route_inf */ - std::vector modified_rr_node_inf_; - /** Router statistics (e.g., heap push/pop counts) */ RouterStats* router_stats_; diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h index 165317c08cd..8df6cacb5ac 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.h +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -20,10 +20,11 @@ #ifndef _MULTI_QUEUE_D_ARY_HEAP_H #define _MULTI_QUEUE_D_ARY_HEAP_H -#include #include "device_grid.h" #include "heap_type.h" #include "multi_queue_d_ary_heap.tpp" +#include +#include using MQHeapNode = std::tuple; @@ -40,20 +41,24 @@ class MultiQueueDAryHeap { using MQ_IO = MultiQueueIO; MultiQueueDAryHeap() { - pq_ = new MQ_IO(2, 1, 0); // Serial (#threads=1, #queues=2) by default + set_num_threads_and_queues(2, 1); // Serial (#threads=1, #queues=2) by default } MultiQueueDAryHeap(size_t num_threads, size_t num_queues) { - pq_ = new MQ_IO(num_queues, num_threads, 0 /*Dont care (batch size for only popBatch)*/); + set_num_threads_and_queues(num_threads, num_queues); } - ~MultiQueueDAryHeap() { - delete pq_; + ~MultiQueueDAryHeap() {} + + void set_num_threads_and_queues(size_t num_threads, size_t num_queues) { + pq_.reset(); + pq_ = std::make_unique(num_threads, num_queues, 0 /*Dont care (batch size for only popBatch)*/); } void init_heap(const DeviceGrid& grid) { (void)grid; // TODO: Reserve storage for MQ_IO + // Note: This function could be called before setting num_threads/num_queues } bool try_pop(HeapNode& heap_node) { @@ -119,7 +124,7 @@ class MultiQueueDAryHeap { #endif private: - MQ_IO* pq_; + std::unique_ptr pq_; }; #endif diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp index 46cdc70f557..c0d6db96547 100644 --- a/vpr/src/route/parallel_connection_router.cpp +++ b/vpr/src/route/parallel_connection_router.cpp @@ -394,12 +394,12 @@ void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost if (to_node == target_node) { #ifdef MQ_IO_ENABLE_CLEAR_FOR_POP if (multi_queue_direct_draining_) { - heap_.setMinPrioForPop(new_total_cost); + this->heap_.setMinPrioForPop(new_total_cost); } #endif return; } - heap_.add_to_heap({new_total_cost, to_node}); + this->heap_.add_to_heap({new_total_cost, to_node}); } template diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h index 960e2cd2348..45a469be24f 100644 --- a/vpr/src/route/parallel_connection_router.h +++ b/vpr/src/route/parallel_connection_router.h @@ -153,7 +153,7 @@ using barrier_t = barrier_spin_t; // Using the spin-based thread barrier * Dec. 2024. */ template -class ParallelConnectionRouter : public ConnectionRouter { +class ParallelConnectionRouter : public ConnectionRouter> { public: ParallelConnectionRouter( const DeviceGrid& grid, @@ -167,13 +167,14 @@ class ParallelConnectionRouter : public ConnectionRouter { int multi_queue_num_threads, int multi_queue_num_queues, bool multi_queue_direct_draining) - : ConnectionRouter(grid, router_lookahead, rr_nodes, rr_graph, rr_rc_data, rr_switch_inf, rr_node_route_inf, is_flat) + : ConnectionRouter>(grid, router_lookahead, rr_nodes, rr_graph, rr_rc_data, rr_switch_inf, rr_node_route_inf, is_flat) , modified_rr_node_inf_(multi_queue_num_threads) - , heap_(multi_queue_num_threads, multi_queue_num_queues) , thread_barrier_(multi_queue_num_threads) , is_router_destroying_(false) , locks_(rr_node_route_inf.size()) , multi_queue_direct_draining_(multi_queue_direct_draining) { + // Set the MultiQueue parameters + this->heap_.set_num_threads_and_queues(multi_queue_num_threads, multi_queue_num_queues); // Initialize the thread barrier this->thread_barrier_.init(); // Instantiate (multi_queue_num_threads - 1) helper threads @@ -400,9 +401,6 @@ class ParallelConnectionRouter : public ConnectionRouter { /** Node IDs of modified nodes in rr_node_route_inf for each thread*/ std::vector> modified_rr_node_inf_; - /** MultiQueue-based parallel heap */ - MultiQueueDAryHeap heap_; - /** Helper threads */ std::vector sub_threads_; diff --git a/vpr/src/route/serial_connection_router.h b/vpr/src/route/serial_connection_router.h index 7dbd209203a..2cd23f1460e 100644 --- a/vpr/src/route/serial_connection_router.h +++ b/vpr/src/route/serial_connection_router.h @@ -231,6 +231,9 @@ class SerialConnectionRouter : public ConnectionRouter { vtr::vector timing_driven_find_all_shortest_paths_from_heap( const t_conn_cost_params& cost_params, const t_bb& bounding_box) final; + + /** Node IDs of modified nodes in rr_node_route_inf */ + std::vector modified_rr_node_inf_; }; /** Construct a serial connection router that uses the specified heap type. diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt index 623a460bc36..3ca35cef4c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt @@ -38,6 +38,6 @@ pass_requirements_file=pass_requirements.txt script_params_common=-track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel -script_params_list_add = --enable_parallel_connection_router -script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining +script_params_list_add = --enable_parallel_connection_router on +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt index cd2605467c4..122e16a14a2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt @@ -27,6 +27,6 @@ pass_requirements_file=pass_requirements.txt script_params_common=-track_memory_usage --route_chan_width 100 --max_router_iterations 100 --router_lookahead map --flat_routing on script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 -script_params_list_add = --enable_parallel_connection_router -script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining +script_params_list_add = --enable_parallel_connection_router on +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt index feb50b99350..09855147b8b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt @@ -27,6 +27,6 @@ pass_requirements_file=pass_requirements_multiclock.txt script_params_common=-starting_stage vpr -sdc_file tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/multiclock.sdc script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 -script_params_list_add = --enable_parallel_connection_router -script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining +script_params_list_add = --enable_parallel_connection_router on +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt index f8843fa41e0..1ec5bc88ec3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt @@ -27,6 +27,6 @@ pass_requirements_file=pass_requirements.txt script_params_common = -track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 -script_params_list_add = --enable_parallel_connection_router -script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining +script_params_list_add = --enable_parallel_connection_router on +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt index fe98854a2da..6af15346384 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt @@ -31,9 +31,9 @@ script_params_list_add = --timing_update_type incremental script_params_list_add = --timing_update_type incremental --quench_recompute_divider 999999999 #Do post-move incremental STA during quench script_params_list_add = --timing_update_type incremental --router_algorithm parallel --num_workers 4 # rarely exercised code path script_params_list_add = --timing_update_type full --router_algorithm parallel --num_workers 4 -script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router -script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining -script_params_list_add = --timing_update_type full --enable_parallel_connection_router -script_params_list_add = --timing_update_type full --enable_parallel_connection_router --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --timing_update_type full --enable_parallel_connection_router --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on From f336abb841ae82b837b41f6bcafb5fa3d23371a1 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Tue, 22 Apr 2025 14:23:16 -0400 Subject: [PATCH 013/176] [AP][MassLegalizer] Revistited Mass Legalizer Found that the mass legalizer was not spreading out the blocks well enough according to the mass. Revistied the spatial partitioning in the mass legalizer. Before, we just cut the window in half in the larger dimension. This was fine, however it may create an inbalanced cut which can cause things to not spread well. Instead, we now search for the best partition by trying different partition lines and computing how balanced the partition is. Although this is more expensive than before, by creating more balanced partitions, it should allow the mass legalizer to converge faster. Time in the mass legalizer is also dominated by partitioning the blocks, so increasing the time to choose the partition line should not have that large of an effect anyways. Found an oversight with how blocks were partitioned when one of the partitions become overfilled. Fixed this issue. --- .../analytical_place/partial_legalizer.cpp | 162 ++++++++++++------ vpr/src/analytical_place/partial_legalizer.h | 2 +- vpr/src/analytical_place/primitive_vector.h | 14 ++ vpr/test/test_ap_primitive_vector.cpp | 18 ++ 4 files changed, 138 insertions(+), 58 deletions(-) diff --git a/vpr/src/analytical_place/partial_legalizer.cpp b/vpr/src/analytical_place/partial_legalizer.cpp index 7021734f8d5..1f5103ba02b 100644 --- a/vpr/src/analytical_place/partial_legalizer.cpp +++ b/vpr/src/analytical_place/partial_legalizer.cpp @@ -1271,7 +1271,7 @@ void BiPartitioningPartialLegalizer::spread_over_windows(std::vectorverify()); } -PartitionedWindow BiPartitioningPartialLegalizer::partition_window(SpreadingWindow& window) { +PartitionedWindow BiPartitioningPartialLegalizer::partition_window( + SpreadingWindow& window, + ModelGroupId group_id) { + + // Search for the ideal partition line on the window. Here, we attempt each + // partition and measure how well this cuts the capacity of the region in + // half. Cutting the capacity of the region in half should allow the blocks + // within the region to also be cut in half (assuming a good initial window + // was chosen). This should allow the spreader to spread things more evenly + // and converge faster. Hence, it is worth spending more time trying to find + // better partition lines. + // + // Here, we compute the score of a partition as a number between 0 and 1 + // which represents how balanced the partition is. 0 means that all of the + // capacity is on one side of the partition, 1 means that the capacities of + // the two partitions are perfectly balanced (equal on both sides). + float best_score = -1.0f; PartitionedWindow partitioned_window; + const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); - // Select the partition direction. - // To keep it simple, we partition the direction which would cut the - // region the most. - // TODO: Should explore making the partition line based on the capacity - // of the two partitioned regions. We may want to cut the - // region in half such that the mass of the atoms contained within - // the two future regions is equal. - partitioned_window.partition_dir = e_partition_dir::VERTICAL; - if (window.region.height() > window.region.width()) - partitioned_window.partition_dir = e_partition_dir::HORIZONTAL; - - // To keep it simple, just cut the space in half. - // TODO: Should investigate other cutting techniques. Cutting perfectly - // in half may not be the most efficient technique. - SpreadingWindow& lower_window = partitioned_window.lower_window; - SpreadingWindow& upper_window = partitioned_window.upper_window; - partitioned_window.pivot_pos = 0.f; - if (partitioned_window.partition_dir == e_partition_dir::VERTICAL) { - // Find the x-coordinate of a cut line directly in the middle of the - // region. We floor this to prevent fractional cut lines. - double pivot_x = std::floor((window.region.xmin() + window.region.xmax()) / 2.0); + // First, try all of the vertical partitions. + double min_pivot_x = std::floor(window.region.xmin()) + 1.0; + double max_pivot_x = std::ceil(window.region.xmax()) - 1.0; + for (double pivot_x = min_pivot_x; pivot_x <= max_pivot_x; pivot_x++) { + // Cut the region at this cut line. + auto lower_region = vtr::Rect(vtr::Point(window.region.xmin(), + window.region.ymin()), + vtr::Point(pivot_x, + window.region.ymax())); + + auto upper_region = vtr::Rect(vtr::Point(pivot_x, + window.region.ymin()), + vtr::Point(window.region.xmax(), + window.region.ymax())); + + // Compute the capacity of each partition for the models that we care + // about. + // TODO: This can be made better by looking at the mass of all blocks + // within the window and scaling the capacity based on that. + float lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, lower_region).manhattan_norm(); + lower_window_capacity = std::max(lower_window_capacity, 0.0f); + float upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, upper_region).manhattan_norm(); + upper_window_capacity = std::max(upper_window_capacity, 0.0f); + + // Compute the score of this partition line. The score is simply just + // the minimum of the two capacities dividided by the maximum of the + // two capacities. + float smaller_capacity = std::min(lower_window_capacity, upper_window_capacity); + float larger_capacity = std::max(lower_window_capacity, upper_window_capacity); + float cut_score = smaller_capacity / larger_capacity; + + // If this is the best cut we have ever seen, save it as the result. + if (cut_score > best_score) { + best_score = cut_score; + partitioned_window.partition_dir = e_partition_dir::VERTICAL; + partitioned_window.pivot_pos = pivot_x; + partitioned_window.lower_window.region = lower_region; + partitioned_window.upper_window.region = upper_region; + } + } + // Next, try all of the horizontal partitions. + double min_pivot_y = std::floor(window.region.ymin()) + 1.0; + double max_pivot_y = std::ceil(window.region.ymax()) - 1.0; + for (double pivot_y = min_pivot_y; pivot_y <= max_pivot_y; pivot_y++) { // Cut the region at this cut line. - lower_window.region = vtr::Rect(vtr::Point(window.region.xmin(), - window.region.ymin()), - vtr::Point(pivot_x, - window.region.ymax())); - - upper_window.region = vtr::Rect(vtr::Point(pivot_x, - window.region.ymin()), - vtr::Point(window.region.xmax(), - window.region.ymax())); - partitioned_window.pivot_pos = pivot_x; - } else { - VTR_ASSERT(partitioned_window.partition_dir == e_partition_dir::HORIZONTAL); - // Similarly in the y direction, find the non-fractional y coordinate - // to make a horizontal cut. - double pivot_y = std::floor((window.region.ymin() + window.region.ymax()) / 2.0); - - // Then cut the window. - lower_window.region = vtr::Rect(vtr::Point(window.region.xmin(), - window.region.ymin()), - vtr::Point(window.region.xmax(), - pivot_y)); - - upper_window.region = vtr::Rect(vtr::Point(window.region.xmin(), - pivot_y), - vtr::Point(window.region.xmax(), - window.region.ymax())); - partitioned_window.pivot_pos = pivot_y; + auto lower_region = vtr::Rect(vtr::Point(window.region.xmin(), + window.region.ymin()), + vtr::Point(window.region.xmax(), + pivot_y)); + + auto upper_region = vtr::Rect(vtr::Point(window.region.xmin(), + pivot_y), + vtr::Point(window.region.xmax(), + window.region.ymax())); + + // Compute the capacity of each partition for the models that we care + // about. + // TODO: This can be made better by looking at the mass of all blocks + // within the window and scaling the capacity based on that. + float lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, lower_region).manhattan_norm(); + lower_window_capacity = std::max(lower_window_capacity, 0.0f); + float upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, upper_region).manhattan_norm(); + upper_window_capacity = std::max(upper_window_capacity, 0.0f); + + // Compute the score of this partition line. The score is simply just + // the minimum of the two capacities dividided by the maximum of the + // two capacities. + float smaller_capacity = std::min(lower_window_capacity, upper_window_capacity); + float larger_capacity = std::max(lower_window_capacity, upper_window_capacity); + float cut_score = smaller_capacity / larger_capacity; + + // If this is the best cut we have ever seen, save it as the result. + if (cut_score > best_score) { + best_score = cut_score; + partitioned_window.partition_dir = e_partition_dir::HORIZONTAL; + partitioned_window.pivot_pos = pivot_y; + partitioned_window.lower_window.region = lower_region; + partitioned_window.upper_window.region = upper_region; + } } + VTR_ASSERT_MSG(best_score >= 0.0f, + "Could not find a partition line for given window"); + return partitioned_window; } @@ -1475,7 +1525,7 @@ void BiPartitioningPartialLegalizer::partition_blocks_in_window( // NOTE: This needs to be an int in case the pivot is 0. for (int i = window.contained_blocks.size() - 1; i >= (int)pivot; i--) { const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(window.contained_blocks[i]); - VTR_ASSERT_SAFE(lower_window_underfill.is_non_negative()); + VTR_ASSERT_SAFE(upper_window_underfill.is_non_negative()); upper_window_underfill -= blk_mass; if (upper_window_underfill.is_non_negative()) upper_window.contained_blocks.push_back(window.contained_blocks[i]); @@ -1490,8 +1540,6 @@ void BiPartitioningPartialLegalizer::partition_blocks_in_window( // windows. To do this we sort the unplaced blocks by largest mass to // smallest mass. Then we place each block in the bin with the highest // underfill. - // FIXME: Above was the intuition; however, after experimentation, found that - // sorting by smallest mass to largest mass worked better... // FIXME: I think large blocks (like carry chains) need to be handled special // early on. If they are put into a partition too late, they may have // to create overfill! Perhaps the partitions can hold two lists. @@ -1500,20 +1548,20 @@ void BiPartitioningPartialLegalizer::partition_blocks_in_window( [&](APBlockId a, APBlockId b) { const auto& blk_a_mass = density_manager_->mass_calculator().get_block_mass(a); const auto& blk_b_mass = density_manager_->mass_calculator().get_block_mass(b); - return blk_a_mass.manhattan_norm() < blk_b_mass.manhattan_norm(); + return blk_a_mass.manhattan_norm() > blk_b_mass.manhattan_norm(); }); for (APBlockId blk_id : unplaced_blocks) { // Project the underfill from each window onto the mass. This gives us // the overfill in the dimensions the mass cares about. const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(blk_id); PrimitiveVector projected_lower_window_underfill = lower_window_underfill; - lower_window_underfill.project(blk_mass); + projected_lower_window_underfill.project(blk_mass); PrimitiveVector projected_upper_window_underfill = upper_window_underfill; - upper_window_underfill.project(blk_mass); + projected_upper_window_underfill.project(blk_mass); // Put the block in the window with a higher underfill. This tries to // balance the overfill as much as possible. This works even if the // overfill becomes negative. - if (projected_lower_window_underfill.manhattan_norm() >= projected_upper_window_underfill.manhattan_norm()) { + if (projected_lower_window_underfill.sum() >= projected_upper_window_underfill.sum()) { lower_window.contained_blocks.push_back(blk_id); lower_window_underfill -= blk_mass; } else { diff --git a/vpr/src/analytical_place/partial_legalizer.h b/vpr/src/analytical_place/partial_legalizer.h index 2eb4e5771da..5f82c787724 100644 --- a/vpr/src/analytical_place/partial_legalizer.h +++ b/vpr/src/analytical_place/partial_legalizer.h @@ -483,7 +483,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { * the direction of the partition (vertical / horizontal) and the position * of the cut. */ - PartitionedWindow partition_window(SpreadingWindow& window); + PartitionedWindow partition_window(SpreadingWindow& window, ModelGroupId group_id); /** * @brief Partition the blocks in the given window into the partitioned diff --git a/vpr/src/analytical_place/primitive_vector.h b/vpr/src/analytical_place/primitive_vector.h index d76ae8b509d..52b0cb8a560 100644 --- a/vpr/src/analytical_place/primitive_vector.h +++ b/vpr/src/analytical_place/primitive_vector.h @@ -266,6 +266,20 @@ class PrimitiveVector { return mag; } + /** + * @brief Computes the sum across all dimensions of the vector. + * + * This is similar to manhattan_norm, however this does not take the + * absolute value of each dimension. + */ + inline float sum() const { + float sum = 0.f; + for (const auto& p : data_) { + sum += p.second; + } + return sum; + } + /** * @brief Project this vector onto the given vector. * diff --git a/vpr/test/test_ap_primitive_vector.cpp b/vpr/test/test_ap_primitive_vector.cpp index 425f4e20f35..d3455d7cfe7 100644 --- a/vpr/test/test_ap_primitive_vector.cpp +++ b/vpr/test/test_ap_primitive_vector.cpp @@ -241,6 +241,24 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { vec2 *= -1.f; REQUIRE(vec2.manhattan_norm() == vec1.manhattan_norm()); + // sum: + vec1.clear(); + // Sum of the zero vector is zero. + REQUIRE(vec1.sum() == 0.f); + // Sum of a non-negative vector is the sum of its dims. + vec1.set_dim_val(0, 1.f); + REQUIRE(vec1.sum() == 1.f); + vec1.set_dim_val(1, 2.f); + vec1.set_dim_val(2, 3.f); + vec1.set_dim_val(3, 4.f); + vec1.set_dim_val(4, 5.f); + REQUIRE(vec1.sum() == 15.f); + // Sum of a negative vector is the opposite of the sum of the absolute + // value of its dims. + vec2 = vec1; + vec2 *= -1.f; + REQUIRE(vec2.sum() == -1.f * vec1.sum()); + // Projection: // Basic example: vec1.clear(); From 6be051ec9676c7fd382b1176e02e7930e6461037 Mon Sep 17 00:00:00 2001 From: Fred Tombs Date: Wed, 16 Apr 2025 16:36:53 -0400 Subject: [PATCH 014/176] Inverse use of macro_can_be_placed argument check_all_legality to align with meaning --- vpr/src/place/analytic_placer.cpp | 4 ++-- vpr/src/place/initial_placement.cpp | 9 ++++----- vpr/src/place/place_util.cpp | 2 +- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/vpr/src/place/analytic_placer.cpp b/vpr/src/place/analytic_placer.cpp index a0897af6785..e460c5bd58f 100644 --- a/vpr/src/place/analytic_placer.cpp +++ b/vpr/src/place/analytic_placer.cpp @@ -411,7 +411,7 @@ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { void AnalyticPlacer::update_macros() { for (auto& macro : place_macros_.macros()) { ClusterBlockId head_id = macro.members[0].blk_index; - bool mac_can_be_placed = macro_can_be_placed(macro, blk_locs[head_id].loc, true, blk_loc_registry_ref_); + bool mac_can_be_placed = macro_can_be_placed(macro, blk_locs[head_id].loc, false, blk_loc_registry_ref_); //if macro can not be placed in this head pos, change the head pos if (!mac_can_be_placed) { @@ -420,7 +420,7 @@ void AnalyticPlacer::update_macros() { } //macro should be placed successfully after changing the head position - VTR_ASSERT(macro_can_be_placed(macro, blk_locs[head_id].loc, true, blk_loc_registry_ref_)); + VTR_ASSERT(macro_can_be_placed(macro, blk_locs[head_id].loc, false, blk_loc_registry_ref_)); //update other member's location based on head pos for (auto member = ++macro.members.begin(); member != macro.members.end(); ++member) { diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index aac91e0fd65..5fb0d5f1734 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -742,12 +742,10 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat // floorplanning constraints and compatibility for all // members of the macro. This prevents some macros being // placed where they obviously cannot be implemented. - // Note: The check_all_legality flag is poorly named. false means - // that it WILL check all legality... t_pl_loc new_loc = t_pl_loc(grid_loc.x, grid_loc.y, new_sub_tile, grid_loc.layer_num); bool site_legal_for_macro = macro_can_be_placed(pl_macro, new_loc, - false /*check_all_legality*/, + true /*check_all_legality*/, blk_loc_registry); if (site_legal_for_macro) { // Update the best solition. @@ -1210,9 +1208,10 @@ bool try_place_macro(const t_pl_macro& pl_macro, return macro_placed; } - bool mac_can_be_placed = macro_can_be_placed(pl_macro, head_pos, /*check_all_legality=*/false, blk_loc_registry); + // called from initial placement + bool macro_can_be_placed = macro_can_be_placed(pl_macro, head_pos, /*check_all_legality=*/true, blk_loc_registry); - if (mac_can_be_placed) { + if (macro_can_be_placed) { // Place down the macro macro_placed = true; VTR_LOGV_DEBUG(f_placer_debug, "\t\t\t\tMacro is placed at the given location\n"); diff --git a/vpr/src/place/place_util.cpp b/vpr/src/place/place_util.cpp index 1ac0899fbdf..ad201120acb 100644 --- a/vpr/src/place/place_util.cpp +++ b/vpr/src/place/place_util.cpp @@ -191,7 +191,7 @@ bool macro_can_be_placed(const t_pl_macro& pl_macro, * floorplan constraint is not supported by analytical placement yet, * hence, if macro_can_be_placed is called from analytical placer, no further actions are required. */ - if (check_all_legality) { + if (not check_all_legality) { continue; } From ad8bfcef3428873b4e63d06c293ddf8fe3241078 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Wed, 23 Apr 2025 08:07:18 -0700 Subject: [PATCH 015/176] [vpr][pack] fix merge issues w/ flat sync list --- .../pack/sync_netlists_to_routing_flat.cpp | 63 +------------------ 1 file changed, 3 insertions(+), 60 deletions(-) diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 48737693ece..4b23a8cab6b 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -42,26 +42,6 @@ static void fixup_atom_pb_graph_pin_mapping(void); /* Function definitions */ -<<<<<<< HEAD -======= -/** Is the clock net found in the routing results? - * (If not, clock_modeling is probably ideal and we should preserve clock routing while rebuilding.) */ -inline bool is_clock_net_routed(void) { - auto& atom_ctx = g_vpr_ctx.atom(); - auto& route_ctx = g_vpr_ctx.routing(); - - for (auto net_id : atom_ctx.netlist().nets()) { - auto& tree = route_ctx.route_trees[net_id]; - if (!tree) - continue; - if (route_ctx.is_clock_net[net_id]) /* Clock net has routing */ - return true; - } - - return false; -} - ->>>>>>> 1e479b90837fdc89cbf9089c691ed58200642fe0 /** Get the ClusterBlockId for a given RRNodeId. */ inline ClusterBlockId get_cluster_block_from_rr_node(RRNodeId inode) { auto& device_ctx = g_vpr_ctx.device(); @@ -193,17 +173,11 @@ static void sync_pb_routes_to_routing(void) { /* Don't erase entries for nets without routing in place (clocks, globals...) */ std::vector pins_to_erase; auto& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; -<<<<<<< HEAD for(auto& [pin, pb_route]: pb_routes){ /* No route tree: no routing in place, it is global or clock */ if(!route_ctx.route_trees[ParentNetId(int(pb_route.atom_net_id))]) continue; pins_to_erase.push_back(pin); -======= - for (auto& [pin, pb_route] : pb_routes) { - if (clock_net_is_routed || !route_ctx.is_clock_net[pb_route.atom_net_id]) - pins_to_erase.push_back(pin); ->>>>>>> 1e479b90837fdc89cbf9089c691ed58200642fe0 } for (int pin : pins_to_erase) { @@ -292,16 +266,11 @@ static void sync_clustered_netlist_to_routing(void) { for (auto net_id : clb_netlist.nets()) { auto atom_net_id = atom_lookup.atom_net(net_id); -<<<<<<< HEAD if(!route_ctx.route_trees[ParentNetId(int(atom_net_id))]) -======= - if (!clock_net_is_routed && route_ctx.is_clock_net[atom_net_id]) ->>>>>>> 1e479b90837fdc89cbf9089c691ed58200642fe0 continue; nets_to_remove.push_back(net_id); } -<<<<<<< HEAD /* Mark ports and pins for removal. Don't remove a port if * it has at least one pin remaining */ for(auto port_id: clb_netlist.ports()){ @@ -316,21 +285,6 @@ static void sync_clustered_netlist_to_routing(void) { pins_to_remove.push_back(pin_id); } } -======= - for (auto pin_id : clb_netlist.pins()) { - ClusterNetId clb_net_id = clb_netlist.pin_net(pin_id); - auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if (!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) - continue; - - pins_to_remove.push_back(pin_id); - } - for (auto port_id : clb_netlist.ports()) { - ClusterNetId clb_net_id = clb_netlist.port_net(port_id, 0); - auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if (!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) - continue; ->>>>>>> 1e479b90837fdc89cbf9089c691ed58200642fe0 if(!skipped_pins) // All pins have been removed, remove port ports_to_remove.push_back(port_id); @@ -380,14 +334,8 @@ static void sync_clustered_netlist_to_routing(void) { /* OPIN on the tile: create a new clb_net_id and add all ports & pins into here * Due to how the route tree is traversed, all nodes until the next OPIN on the tile will * be under this OPIN, so this is valid (we don't need to get the branch explicitly) */ -<<<<<<< HEAD if(node_type == OPIN){ - std::string net_name = atom_ctx.nlist.net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); -======= - if (node_type == OPIN) { - std::string net_name; - net_name = atom_ctx.netlist().net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); ->>>>>>> 1e479b90837fdc89cbf9089c691ed58200642fe0 + std::string net_name = atom_ctx.netlist().net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); clb_net_id = clb_netlist.create_net(net_name); atom_ctx.mutable_lookup().add_atom_clb_net(atom_net_id, clb_net_id); clb_nets_so_far++; @@ -460,19 +408,14 @@ static void fixup_atom_pb_graph_pin_mapping(void) { continue; /* Find atom port from pbg pin's model port */ -<<<<<<< HEAD - AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atb, atom_pbg_pin->port->model_port); + AtomPortId atom_port = atom_ctx.netlist().find_atom_port(atb, atom_pbg_pin->port->model_port); /* Not an equivalent port, so no need to do fixup */ if (atom_pbg_pin->port->equivalent != PortEquivalence::FULL) { continue; } - for(AtomPinId atom_pin: atom_ctx.nlist.port_pins(atom_port)){ -======= - AtomPortId atom_port = atom_ctx.netlist().find_atom_port(atb, atom_pbg_pin->port->model_port); - for (AtomPinId atom_pin : atom_ctx.netlist().port_pins(atom_port)) { ->>>>>>> 1e479b90837fdc89cbf9089c691ed58200642fe0 + for(AtomPinId atom_pin: atom_ctx.netlist().port_pins(atom_port)){ /* Match net IDs from pb_route and atom netlist and connect in lookup */ if (pb_route.atom_net_id == atom_ctx.netlist().pin_net(atom_pin)) { atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(atom_pin, atom_pbg_pin); From fbd20151844c2b1d2cbf41fe32f8ed04bc39ef04 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 23 Apr 2025 19:08:09 +0000 Subject: [PATCH 016/176] make format --- vpr/src/base/vpr_api.cpp | 16 ++++++------ vpr/src/pack/post_routing_pb_pin_fixup.cpp | 6 ++--- .../pack/sync_netlists_to_routing_flat.cpp | 26 +++++++++---------- vpr/src/route/annotate_routing.cpp | 6 ++--- vpr/src/route/annotate_routing.h | 6 ++--- 5 files changed, 30 insertions(+), 30 deletions(-) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index a6564a8ca98..43d5d862bd1 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -373,18 +373,18 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a /** Port equivalence does not make sense during flat routing. * Remove port equivalence from all ports in the architecture */ -static void unset_port_equivalences(DeviceContext& device_ctx){ - for(auto& physical_type: device_ctx.physical_tile_types){ - for(auto& sub_tile: physical_type.sub_tiles){ - for(auto& port: sub_tile.ports){ +static void unset_port_equivalences(DeviceContext& device_ctx) { + for (auto& physical_type : device_ctx.physical_tile_types) { + for (auto& sub_tile : physical_type.sub_tiles) { + for (auto& port : sub_tile.ports) { port.equivalent = PortEquivalence::NONE; } } } - for(auto& logical_type: device_ctx.logical_block_types){ - if(!logical_type.pb_type) + for (auto& logical_type : device_ctx.logical_block_types) { + if (!logical_type.pb_type) continue; - for(int i=0; inum_ports; i++){ + for (int i=0; i < logical_type.pb_type->num_ports; i++) { logical_type.pb_type->ports[i].equivalent = PortEquivalence::NONE; } } @@ -468,7 +468,7 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { bool is_flat = vpr_setup.RouterOpts.flat_routing; const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; - if (is_flat){ + if (is_flat) { VTR_LOG_WARN("Disabling port equivalence in the architecture since flat routing is enabled.\n"); unset_port_equivalences(g_vpr_ctx.mutable_device()); } diff --git a/vpr/src/pack/post_routing_pb_pin_fixup.cpp b/vpr/src/pack/post_routing_pb_pin_fixup.cpp index 923bdfe8c3a..5e737724391 100644 --- a/vpr/src/pack/post_routing_pb_pin_fixup.cpp +++ b/vpr/src/pack/post_routing_pb_pin_fixup.cpp @@ -1032,9 +1032,9 @@ void sync_netlists_to_routing(const Netlist<>& net_list, /* Create net-to-rr_node mapping */ vtr::vector rr_node_nets = annotate_rr_node_nets(clustering_ctx, - device_ctx, - atom_ctx, - verbose); + device_ctx, + atom_ctx, + verbose); IntraLbPbPinLookup intra_lb_pb_pin_lookup(device_ctx.logical_block_types); diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 4b23a8cab6b..d2c9480ea90 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -173,7 +173,7 @@ static void sync_pb_routes_to_routing(void) { /* Don't erase entries for nets without routing in place (clocks, globals...) */ std::vector pins_to_erase; auto& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; - for(auto& [pin, pb_route]: pb_routes){ + for (auto& [pin, pb_route] : pb_routes) { /* No route tree: no routing in place, it is global or clock */ if(!route_ctx.route_trees[ParentNetId(int(pb_route.atom_net_id))]) continue; @@ -266,27 +266,27 @@ static void sync_clustered_netlist_to_routing(void) { for (auto net_id : clb_netlist.nets()) { auto atom_net_id = atom_lookup.atom_net(net_id); - if(!route_ctx.route_trees[ParentNetId(int(atom_net_id))]) + if (!route_ctx.route_trees[ParentNetId(int(atom_net_id))]) continue; nets_to_remove.push_back(net_id); } /* Mark ports and pins for removal. Don't remove a port if * it has at least one pin remaining */ - for(auto port_id: clb_netlist.ports()){ + for (auto port_id : clb_netlist.ports()) { size_t skipped_pins = 0; - for(auto pin_id: clb_netlist.port_pins(port_id)){ + for (auto pin_id : clb_netlist.port_pins(port_id)) { ClusterNetId clb_net_id = clb_netlist.pin_net(pin_id); auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if(atom_net_id && !route_ctx.route_trees[ParentNetId(int(atom_net_id))]){ + if (atom_net_id && !route_ctx.route_trees[ParentNetId(int(atom_net_id))]) { skipped_pins++; - }else{ + } else { pins_to_remove.push_back(pin_id); } } - if(!skipped_pins) // All pins have been removed, remove port + if (!skipped_pins) // All pins have been removed, remove port ports_to_remove.push_back(port_id); } @@ -334,7 +334,7 @@ static void sync_clustered_netlist_to_routing(void) { /* OPIN on the tile: create a new clb_net_id and add all ports & pins into here * Due to how the route tree is traversed, all nodes until the next OPIN on the tile will * be under this OPIN, so this is valid (we don't need to get the branch explicitly) */ - if(node_type == OPIN){ + if (node_type == OPIN) { std::string net_name = atom_ctx.netlist().net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); clb_net_id = clb_netlist.create_net(net_name); atom_ctx.mutable_lookup().add_atom_clb_net(atom_net_id, clb_net_id); @@ -362,10 +362,10 @@ static void sync_clustered_netlist_to_routing(void) { /* Pin already exists. This means a global was connected to here. */ if (clb_netlist.port_pin(port_id, pb_graph_pin->pin_number)) { VTR_LOG_WARN("Pin %s of block %s has a global or clock net" - " connected and it has a routing clash with the flat router." - " This may cause inconsistent results.\n", - pb_graph_pin->to_string().c_str(), - clb_netlist.block_name(clb).c_str()); + " connected and it has a routing clash with the flat router." + " This may cause inconsistent results.\n", + pb_graph_pin->to_string().c_str(), + clb_netlist.block_name(clb).c_str()); continue; } ClusterPinId new_pin = clb_netlist.create_pin(port_id, pb_graph_pin->pin_number, clb_net_id, pin_type, pb_graph_pin->pin_count_in_cluster); @@ -415,7 +415,7 @@ static void fixup_atom_pb_graph_pin_mapping(void) { continue; } - for(AtomPinId atom_pin: atom_ctx.netlist().port_pins(atom_port)){ + for (AtomPinId atom_pin : atom_ctx.netlist().port_pins(atom_port)) { /* Match net IDs from pb_route and atom netlist and connect in lookup */ if (pb_route.atom_net_id == atom_ctx.netlist().pin_net(atom_pin)) { atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(atom_pin, atom_pbg_pin); diff --git a/vpr/src/route/annotate_routing.cpp b/vpr/src/route/annotate_routing.cpp index 5dc1d957678..442d7840726 100644 --- a/vpr/src/route/annotate_routing.cpp +++ b/vpr/src/route/annotate_routing.cpp @@ -14,9 +14,9 @@ #include "annotate_routing.h" vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, - const DeviceContext& device_ctx, - const AtomContext& atom_ctx, - const bool& verbose) { + const DeviceContext& device_ctx, + const AtomContext& atom_ctx, + const bool& verbose) { size_t counter = 0; vtr::ScopedStartFinishTimer timer("Annotating rr_node with routed nets"); diff --git a/vpr/src/route/annotate_routing.h b/vpr/src/route/annotate_routing.h index 3d6d87b2575..e00be549259 100644 --- a/vpr/src/route/annotate_routing.h +++ b/vpr/src/route/annotate_routing.h @@ -11,8 +11,8 @@ * - Unmapped rr_node will use invalid ids *******************************************************************/ vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, - const DeviceContext& device_ctx, - const AtomContext& atom_ctx, - const bool& verbose); + const DeviceContext& device_ctx, + const AtomContext& atom_ctx, + const bool& verbose); #endif From 9d313093fb8b614398eb45ad2431fd8ef5c7aabb Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 23 Apr 2025 19:14:13 +0000 Subject: [PATCH 017/176] [packages] add clang-format --- install_apt_packages.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/install_apt_packages.sh b/install_apt_packages.sh index 76c705a2c34..d79f3d14fec 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -40,3 +40,7 @@ sudo apt-get install -y \ # Required to build the documentation sudo apt-get install -y \ sphinx-common + +# Required for code formatting +sudo apt-get install -y \ + clang-format-18 From 8b15437939d0b630a20064d04ddd0060def531ef Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 23 Apr 2025 19:15:48 +0000 Subject: [PATCH 018/176] make format 2 --- vpr/src/base/vpr_api.cpp | 2 +- vpr/src/pack/sync_netlists_to_routing_flat.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 43d5d862bd1..928839410f2 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -384,7 +384,7 @@ static void unset_port_equivalences(DeviceContext& device_ctx) { for (auto& logical_type : device_ctx.logical_block_types) { if (!logical_type.pb_type) continue; - for (int i=0; i < logical_type.pb_type->num_ports; i++) { + for (int i = 0; i < logical_type.pb_type->num_ports; i++) { logical_type.pb_type->ports[i].equivalent = PortEquivalence::NONE; } } diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index d2c9480ea90..9a8f584b966 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -175,7 +175,7 @@ static void sync_pb_routes_to_routing(void) { auto& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; for (auto& [pin, pb_route] : pb_routes) { /* No route tree: no routing in place, it is global or clock */ - if(!route_ctx.route_trees[ParentNetId(int(pb_route.atom_net_id))]) + if (!route_ctx.route_trees[ParentNetId(int(pb_route.atom_net_id))]) continue; pins_to_erase.push_back(pin); } @@ -286,7 +286,7 @@ static void sync_clustered_netlist_to_routing(void) { } } - if (!skipped_pins) // All pins have been removed, remove port + if (!skipped_pins) // All pins have been removed, remove port ports_to_remove.push_back(port_id); } From 08c18099282ab339b23aa4130147f2db9e2281b4 Mon Sep 17 00:00:00 2001 From: Fred Tombs Date: Wed, 23 Apr 2025 15:24:34 -0400 Subject: [PATCH 019/176] Invalid C++ fix --- vpr/src/place/initial_placement.cpp | 6 ++---- vpr/src/place/place_util.h | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 5fb0d5f1734..7f658ccb968 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -1209,10 +1209,8 @@ bool try_place_macro(const t_pl_macro& pl_macro, } // called from initial placement - bool macro_can_be_placed = macro_can_be_placed(pl_macro, head_pos, /*check_all_legality=*/true, blk_loc_registry); - - if (macro_can_be_placed) { - // Place down the macro + if (macro_can_be_placed(pl_macro, head_pos, /*check_all_legality=*/true, blk_loc_registry)) { + // Place down the macromacro_can_be_placed macro_placed = true; VTR_LOGV_DEBUG(f_placer_debug, "\t\t\t\tMacro is placed at the given location\n"); for (const t_pl_macro_member& pl_macro_member : pl_macro.members) { diff --git a/vpr/src/place/place_util.h b/vpr/src/place/place_util.h index 14cf44455c6..6faa963106a 100644 --- a/vpr/src/place/place_util.h +++ b/vpr/src/place/place_util.h @@ -261,7 +261,7 @@ inline bool is_loc_on_chip(t_physical_tile_loc loc) { * determines whether the routine should check all legality constraint * Analytic placer does not require to check block's capacity or * floorplanning constraints. However, initial placement or SA-based approach - * require to check for all legality constraints. + * require checking all legality constraints. * @param blk_loc_registry Placement block location information. * */ From b7c1f1f7fe0a928207d70b9a101154e3dfb9ceea Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 23 Apr 2025 22:56:52 +0000 Subject: [PATCH 020/176] [docker] set ubuntu version to 24.04 --- Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Dockerfile b/Dockerfile index 2b36ac5c5e5..91de2373d7f 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,4 +1,4 @@ -FROM ubuntu:22.04 +FROM ubuntu:24.04 ARG DEBIAN_FRONTEND=noninteractive # set out workspace ENV WORKSPACE=/workspace From d56576e8d6736cc306e1f4c583388e032f218f82 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 24 Apr 2025 11:46:51 +0000 Subject: [PATCH 021/176] [dockerfile] enable system-wide python package installation for pip --- Dockerfile | 1 + 1 file changed, 1 insertion(+) diff --git a/Dockerfile b/Dockerfile index 91de2373d7f..7b3b94a2668 100644 --- a/Dockerfile +++ b/Dockerfile @@ -5,6 +5,7 @@ ENV WORKSPACE=/workspace RUN mkdir -p ${WORKSPACE} WORKDIR ${WORKSPACE} COPY . ${WORKSPACE} +ENV PIP_BREAK_SYSTEM_PACKAGES=1 # Install and cleanup is done in one command to minimize the build cache size RUN apt-get update -qq \ # Extract package names from install_apt_packages.sh From 0afdfff63aabae0ee3165876d9727f13ae324a00 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 24 Apr 2025 10:05:43 -0700 Subject: [PATCH 022/176] [dockerfile] add comment --- Dockerfile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Dockerfile b/Dockerfile index 7b3b94a2668..29c3cd94c66 100644 --- a/Dockerfile +++ b/Dockerfile @@ -5,6 +5,8 @@ ENV WORKSPACE=/workspace RUN mkdir -p ${WORKSPACE} WORKDIR ${WORKSPACE} COPY . ${WORKSPACE} +# Required to bypass Python's protection on system-wide package installations in Ubuntu 23.04+. +# This allows pip to install packages globally without using a virtual environment. ENV PIP_BREAK_SYSTEM_PACKAGES=1 # Install and cleanup is done in one command to minimize the build cache size RUN apt-get update -qq \ @@ -30,4 +32,4 @@ RUN apt-get update -qq \ # Build VTR RUN rm -rf build && make -j$(nproc) && make install # Container's default launch command -SHELL ["/bin/bash", "-c"] \ No newline at end of file +SHELL ["/bin/bash", "-c"] From dfc89dc47d9befa7ad3c01e05c5263a767097a51 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 24 Apr 2025 12:29:58 -0700 Subject: [PATCH 023/176] [package] check whehter clang-format-18 package exist --- install_apt_packages.sh | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/install_apt_packages.sh b/install_apt_packages.sh index d79f3d14fec..c6cc8a6200a 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -42,5 +42,8 @@ sudo apt-get install -y \ sphinx-common # Required for code formatting -sudo apt-get install -y \ - clang-format-18 +if apt-cache search --names-only 'clang-format-18' | grep -q 'clang-format-18'; then + sudo apt-get install -y clang-format-18 +else + echo "clang-format-18 not found in apt-cache. Skipping installation." +fi From af7c0440426e623ab3ea48a36b7a4018d88af876 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 24 Apr 2025 12:43:09 -0700 Subject: [PATCH 024/176] [package] remove deprecated names-only option --- install_apt_packages.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/install_apt_packages.sh b/install_apt_packages.sh index c6cc8a6200a..aed5e630ed8 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -42,7 +42,7 @@ sudo apt-get install -y \ sphinx-common # Required for code formatting -if apt-cache search --names-only 'clang-format-18' | grep -q 'clang-format-18'; then +if apt-cache search '^clang-format-18$' | grep -q 'clang-format-18'; then sudo apt-get install -y clang-format-18 else echo "clang-format-18 not found in apt-cache. Skipping installation." From f13addcfd6b531d01a82801c28743509de535fd2 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 24 Apr 2025 14:07:29 -0700 Subject: [PATCH 025/176] [package] remove if condition --- install_apt_packages.sh | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/install_apt_packages.sh b/install_apt_packages.sh index aed5e630ed8..2d0dbf399e2 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -42,8 +42,6 @@ sudo apt-get install -y \ sphinx-common # Required for code formatting -if apt-cache search '^clang-format-18$' | grep -q 'clang-format-18'; then - sudo apt-get install -y clang-format-18 -else - echo "clang-format-18 not found in apt-cache. Skipping installation." -fi +sudo apt-get install -y \ + clang-format-18 + From 1bd97f14527b9a8eced37ee7294f204d25376d70 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 24 Apr 2025 14:11:46 -0700 Subject: [PATCH 026/176] [doc] update quick start on installing packages --- doc/src/quickstart/index.rst | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/doc/src/quickstart/index.rst b/doc/src/quickstart/index.rst index 242079bef99..c2dd8512824 100644 --- a/doc/src/quickstart/index.rst +++ b/doc/src/quickstart/index.rst @@ -23,8 +23,29 @@ If you cloned the repository, you will need to set up the git submodules (if you > git submodule init > git submodule update - -VTR requires several system packages and Python packages to build and run the flow. Ubuntu users can install the required system packages using the following command (this works on Ubuntu 18.04, 20.04, 22.04 and 24.04, but you may require different packages on other Linux distributions). Our CI testing is on Ubuntu 24.04, so that is the best tested platform and recommended for development. + +VTR requires several system and Python packages to build and run the flow. +Ubuntu users can install the required system packages using the provided script or +the command below. This setup works on Ubuntu 18.04, 20.04, 22.04, and 24.04, but note +that some packages (such as ``clang-format-18``) are only available by default on Ubuntu 24.04. +On older versions, this package will not be installed unless you manually add the appropriate +LLVM APT repository. + +To install ``clang-format-18`` on older Ubuntu versions (e.g., 20.04 or 22.04), you must add the +LLVM repository manually: + +.. code-block:: bash + + sudo apt install wget gnupg lsb-release + wget https://apt.llvm.org/llvm.sh + chmod +x llvm.sh + sudo ./llvm.sh 18 + +After that, you can install ``clang-format-18`` using: + +.. code-block:: bash + + sudo apt install clang-format-18 .. code-block:: bash From eb54502a4571f5cd5c20b7691c33d101e12e53b5 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Thu, 24 Apr 2025 17:22:40 -0400 Subject: [PATCH 027/176] make format enum class e_rr_type a few remaining t_rr_type vals CHANY ---> t_rr_type::CHANY CHANX ---> t_rr_type::CHANX OPIN ---> t_rr_type::OPIN IPIN ---> t_rr_type::IPIN SINK ---> t_rr_type::SINK SOURCE ---> t_rr_type::SOURCE --- libs/librrgraph/src/base/check_rr_graph.cpp | 72 +++++----- .../src/base/check_rr_graph_obj.cpp | 4 +- libs/librrgraph/src/base/rr_graph_builder.cpp | 12 +- libs/librrgraph/src/base/rr_graph_obj.cpp | 63 +++++---- libs/librrgraph/src/base/rr_graph_obj.h | 2 +- libs/librrgraph/src/base/rr_graph_storage.cpp | 34 ++--- libs/librrgraph/src/base/rr_graph_storage.h | 12 +- libs/librrgraph/src/base/rr_graph_utils.cpp | 20 +-- libs/librrgraph/src/base/rr_graph_view.h | 12 +- libs/librrgraph/src/base/rr_node_types.h | 14 +- .../librrgraph/src/base/rr_spatial_lookup.cpp | 104 +++++++------- libs/librrgraph/src/base/rr_spatial_lookup.h | 2 +- .../src/io/rr_graph_uxsdcxx_serializer.h | 54 +++---- .../utils/alloc_and_load_rr_indexed_data.cpp | 10 +- .../librrgraph/src/utils/describe_rr_node.cpp | 6 +- utils/fasm/test/test_fasm.cpp | 10 +- utils/route_diag/src/main.cpp | 2 +- vpr/src/base/old_traceback.cpp | 8 +- vpr/src/base/read_route.cpp | 27 ++-- vpr/src/base/read_route.h | 5 +- vpr/src/base/stats.cpp | 10 +- vpr/src/base/vpr_types.h | 17 +-- vpr/src/draw/draw.cpp | 4 +- vpr/src/draw/draw_basic.cpp | 38 ++--- vpr/src/draw/draw_rr.cpp | 92 ++++++------ vpr/src/draw/draw_rr_edges.cpp | 18 +-- vpr/src/draw/draw_searchbar.cpp | 4 +- vpr/src/draw/search_bar.cpp | 8 +- vpr/src/pack/post_routing_pb_pin_fixup.cpp | 8 +- .../pack/sync_netlists_to_routing_flat.cpp | 8 +- .../compute_delta_delays_utils.cpp | 20 +-- vpr/src/place/place_macro.cpp | 14 +- vpr/src/power/power.cpp | 38 ++--- vpr/src/route/annotate_routing.cpp | 4 +- vpr/src/route/build_switchblocks.cpp | 28 ++-- vpr/src/route/channel_stats.cpp | 12 +- vpr/src/route/check_route.cpp | 56 ++++---- vpr/src/route/clock_connection_builders.cpp | 17 +-- vpr/src/route/clock_network_builders.cpp | 4 +- vpr/src/route/connection_router.cpp | 24 ++-- vpr/src/route/overuse_report.cpp | 12 +- vpr/src/route/route.cpp | 2 +- vpr/src/route/route_common.cpp | 26 ++-- vpr/src/route/route_net.cpp | 2 +- vpr/src/route/route_profiling.cpp | 4 +- vpr/src/route/route_tree.cpp | 24 ++-- vpr/src/route/route_utilization.cpp | 26 ++-- vpr/src/route/router_lookahead.cpp | 6 +- .../route/router_lookahead_compressed_map.cpp | 24 ++-- .../route/router_lookahead_extended_map.cpp | 15 +- vpr/src/route/router_lookahead_map.cpp | 36 ++--- vpr/src/route/router_lookahead_map_utils.cpp | 46 +++--- vpr/src/route/router_lookahead_sampling.cpp | 4 +- vpr/src/route/router_stats.h | 12 +- vpr/src/route/rr_graph.cpp | 66 ++++----- vpr/src/route/rr_graph2.cpp | 132 +++++++++--------- vpr/src/route/rr_graph_area.cpp | 32 ++--- vpr/src/route/rr_graph_timing_params.cpp | 14 +- vpr/src/route/segment_stats.cpp | 5 +- vpr/src/timing/VprTimingGraphResolver.cpp | 10 +- vpr/src/util/vpr_utils.cpp | 22 +-- vpr/test/test_vpr.cpp | 4 +- 62 files changed, 701 insertions(+), 720 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 39e859b61dc..f74995aeff9 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -154,22 +154,22 @@ void check_rr_graph(const RRGraphView& rr_graph, * - CHAN -> IPIN connections (unique rr_node for IPIN nodes on multiple sides) * - OPIN -> CHAN connections (unique rr_node for OPIN nodes on multiple sides) */ - bool is_chan_to_chan = (rr_type == CHANX || rr_type == CHANY) && (to_rr_type == CHANY || to_rr_type == CHANX); - bool is_chan_to_ipin = (rr_type == CHANX || rr_type == CHANY) && to_rr_type == IPIN; - bool is_opin_to_chan = rr_type == OPIN && (to_rr_type == CHANX || to_rr_type == CHANY); + bool is_chan_to_chan = (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY) && (to_rr_type == t_rr_type::CHANY || to_rr_type == t_rr_type::CHANX); + bool is_chan_to_ipin = (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY) && to_rr_type == t_rr_type::IPIN; + bool is_opin_to_chan = rr_type == t_rr_type::OPIN && (to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY); bool is_internal_edge = false; if (is_flat) { - is_internal_edge = (rr_type == IPIN && to_rr_type == IPIN) || (rr_type == OPIN && to_rr_type == OPIN); + is_internal_edge = (rr_type == t_rr_type::IPIN && to_rr_type == t_rr_type::IPIN) || (rr_type == t_rr_type::OPIN && to_rr_type == t_rr_type::OPIN); } if (!(is_chan_to_chan || is_chan_to_ipin || is_opin_to_chan || is_internal_edge)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d (%s) connects to node %d (%s) %zu times - multi-connections only expected for CHAN<->CHAN, CHAN->IPIN, OPIN->CHAN.\n", - inode, rr_node_typename[rr_type], to_node, rr_node_typename[to_rr_type], num_edges_to_node); + inode, rr_node_typename[(size_t)rr_type], to_node, rr_node_typename[(size_t)to_rr_type], num_edges_to_node); } //Between two wire segments - VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY || to_rr_type == IPIN, "Expect channel type or input pin type"); - VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY || rr_type == OPIN, "Expect channel type or output pin type"); + VTR_ASSERT_MSG(to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY || to_rr_type == t_rr_type::IPIN, "Expect channel type or input pin type"); + VTR_ASSERT_MSG(rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY || rr_type == t_rr_type::OPIN, "Expect channel type or output pin type"); //While multiple connections between the same wires can be electrically legal, //they are redundant if they are of the same switch type. @@ -190,8 +190,8 @@ void check_rr_graph(const RRGraphView& rr_graph, /* Redundant edges are not allowed for chan <-> chan connections * but allowed for input pin <-> chan or output pin <-> chan connections */ - if ((to_rr_type == CHANX || to_rr_type == CHANY) - && (rr_type == CHANX || rr_type == CHANY)) { + if ((to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY) + && (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY)) { auto switch_type = rr_graph.rr_switch_inf(RRSwitchId(kv.first)).type(); VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)", @@ -240,22 +240,22 @@ void check_rr_graph(const RRGraphView& rr_graph, t_physical_tile_type_ptr type = grid.get_physical_type({xlow, ylow, layer_num}); - if (rr_type == IPIN || rr_type == OPIN) { + if (rr_type == t_rr_type::IPIN || rr_type == t_rr_type::OPIN) { // #TODO: No edges are added for internal pins. However, they need to be checked somehow! if (ptc_num >= type->num_pins) { VTR_LOG_ERROR("in check_rr_graph: node %d (%s) type: %s is internal node.\n", - inode, rr_graph.node_type_string(rr_node), rr_node_typename[rr_type]); + inode, rr_graph.node_type_string(rr_node), rr_node_typename[(size_t)rr_type]); } } - if (rr_type != SOURCE) { + if (rr_type != t_rr_type::SOURCE) { if (total_edges_to_node[inode] < 1 && !rr_node_is_global_clb_ipin(rr_graph, grid, rr_node)) { /* A global CLB input pin will not have any edges, and neither will * * a SOURCE or the start of a carry-chain. Anything else is an error. * For simplicity, carry-chain input pin are entirely ignored in this test */ bool is_chain = false; - if (rr_type == IPIN) { + if (rr_type == t_rr_type::IPIN) { for (const t_fc_specification& fc_spec : types[type->index].fc_specs) { if (fc_spec.fc_value == 0 && fc_spec.seg_index == 0) { is_chain = true; @@ -269,11 +269,11 @@ void check_rr_graph(const RRGraphView& rr_graph, || (rr_graph.node_ylow(rr_node) == 1) || (rr_graph.node_xhigh(rr_node) == int(grid.width()) - 2) || (rr_graph.node_yhigh(rr_node) == int(grid.height()) - 2)); - bool is_wire = (rr_graph.node_type(rr_node) == CHANX - || rr_graph.node_type(rr_node) == CHANY); + bool is_wire = (rr_graph.node_type(rr_node) == t_rr_type::CHANX + || rr_graph.node_type(rr_node) == t_rr_type::CHANY); if (!is_chain && !is_fringe && !is_wire) { - if (rr_graph.node_type(rr_node) == IPIN || rr_graph.node_type(rr_node) == OPIN) { + if (rr_graph.node_type(rr_node) == t_rr_type::IPIN || rr_graph.node_type(rr_node) == t_rr_type::OPIN) { if (has_adjacent_channel(rr_graph, grid, node)) { auto block_type = grid.get_physical_type({rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), @@ -320,7 +320,7 @@ static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const Device rr_graph.node_ylow(inode), rr_graph.node_layer(inode)}); - if (rr_graph.node_type(inode) != IPIN) + if (rr_graph.node_type(inode) != t_rr_type::IPIN) return (false); ipin = rr_graph.node_pin_num(inode); @@ -389,7 +389,7 @@ void check_rr_node(const RRGraphView& rr_graph, type = grid.get_physical_type({xlow, ylow, layer_num}); switch (rr_type) { - case SOURCE: + case t_rr_type::SOURCE: if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow); @@ -400,7 +400,7 @@ void check_rr_node(const RRGraphView& rr_graph, "in check_rr_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d)\n", inode, rr_type, xlow, ylow, xhigh, yhigh); } break; - case SINK: { + case t_rr_type::SINK: { if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow); @@ -413,8 +413,8 @@ void check_rr_node(const RRGraphView& rr_graph, } break; } - case IPIN: - case OPIN: + case t_rr_type::IPIN: + case t_rr_type::OPIN: if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow); @@ -425,7 +425,7 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case CHANX: + case t_rr_type::CHANX: if (xlow < 1 || xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 2 || yhigh != ylow) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); @@ -436,7 +436,7 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case CHANY: + case t_rr_type::CHANY: if (xhigh > int(grid.width()) - 2 || ylow < 1 || yhigh > int(grid.height()) - 2 || xlow != xhigh) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Error in check_rr_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); @@ -459,12 +459,12 @@ void check_rr_node(const RRGraphView& rr_graph, e_pin_type class_type = OPEN; int class_num_pins = -1; switch (rr_type) { - case SOURCE: - case SINK: + case t_rr_type::SOURCE: + case t_rr_type::SINK: class_type = get_class_type_from_class_physical_num(type, ptc_num); class_num_pins = get_class_num_pins_from_class_physical_num(type, ptc_num); if (ptc_num >= class_max_ptc - || class_type != ((rr_type == SOURCE) ? DRIVER : RECEIVER)) { + || class_type != ((rr_type == t_rr_type::SOURCE) ? DRIVER : RECEIVER)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); } @@ -474,11 +474,11 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case OPIN: - case IPIN: + case t_rr_type::OPIN: + case t_rr_type::IPIN: class_type = get_pin_type_from_pin_physical_num(type, ptc_num); if (ptc_num >= pin_max_ptc - || class_type != ((rr_type == OPIN) ? DRIVER : RECEIVER)) { + || class_type != ((rr_type == t_rr_type::OPIN) ? DRIVER : RECEIVER)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); } @@ -488,14 +488,14 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case CHANX: - case CHANY: + case t_rr_type::CHANX: + case t_rr_type::CHANY: if (route_type == DETAILED) { nodes_per_chan = chan_width.max; tracks_per_node = 1; } else { nodes_per_chan = 1; - tracks_per_node = ((rr_type == CHANX) ? chan_width.x_list[ylow] : chan_width.y_list[xlow]); + tracks_per_node = ((rr_type == t_rr_type::CHANX) ? chan_width.x_list[ylow] : chan_width.y_list[xlow]); } //if a chanx/chany has length 0, it means it is used to connect different dice together @@ -522,7 +522,7 @@ void check_rr_node(const RRGraphView& rr_graph, C = rr_graph.node_C(rr_node); R = rr_graph.node_R(rr_node); - if (rr_type == CHANX || rr_type == CHANY) { + if (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY) { if (C < 0. || R < 0.) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d of type %d has R = %g and C = %g.\n", inode, rr_type, R, C); @@ -545,7 +545,7 @@ static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node) { bool trans_matched; from_rr_type = rr_graph.node_type(RRNodeId(from_node)); - if (from_rr_type != CHANX && from_rr_type != CHANY) + if (from_rr_type != t_rr_type::CHANX && from_rr_type != t_rr_type::CHANY) return; from_num_edges = rr_graph.num_edges(RRNodeId(from_node)); @@ -554,7 +554,7 @@ static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node) { to_node = size_t(rr_graph.edge_sink_node(RRNodeId(from_node), from_edge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type != CHANX && to_rr_type != CHANY) + if (to_rr_type != t_rr_type::CHANX && to_rr_type != t_rr_type::CHANY) continue; from_switch_type = rr_graph.edge_switch(RRNodeId(from_node), from_edge); @@ -592,7 +592,7 @@ static bool has_adjacent_channel(const RRGraphView& rr_graph, const DeviceGrid& /* TODO: this function should be reworked later to adapt RRGraphView interface * once xlow(), ylow(), side() APIs are implemented */ - VTR_ASSERT(rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN); + VTR_ASSERT(rr_graph.node_type(node.id()) == t_rr_type::IPIN || rr_graph.node_type(node.id()) == e_rr_type::OPIN); if ((rr_graph.node_xlow(node.id()) == 0 && !rr_graph.is_node_on_specific_side(node.id(), RIGHT)) //left device edge connects only along block's right side || (rr_graph.node_ylow(node.id()) == int(grid.height() - 1) && !rr_graph.is_node_on_specific_side(node.id(), BOTTOM)) //top device edge connects only along block's bottom side diff --git a/libs/librrgraph/src/base/check_rr_graph_obj.cpp b/libs/librrgraph/src/base/check_rr_graph_obj.cpp index d78a6ea266e..300b2dd9515 100644 --- a/libs/librrgraph/src/base/check_rr_graph_obj.cpp +++ b/libs/librrgraph/src/base/check_rr_graph_obj.cpp @@ -94,7 +94,7 @@ static bool check_rr_graph_source_nodes(const RRGraph& rr_graph) { */ for (auto node : rr_graph.nodes()) { /* Pass nodes whose types are not SOURCE */ - if (SOURCE != rr_graph.node_type(node)) { + if (t_rr_type::SOURCE != rr_graph.node_type(node)) { continue; } if ((0 != rr_graph.node_fan_in(node)) @@ -123,7 +123,7 @@ static bool check_rr_graph_sink_nodes(const RRGraph& rr_graph) { */ for (auto node : rr_graph.nodes()) { /* Pass nodes whose types are not SINK */ - if (SINK != rr_graph.node_type(node)) { + if (t_rr_type::SINK != rr_graph.node_type(node)) { continue; } if ((0 == rr_graph.node_fan_in(node)) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 565c99e3f75..9233639a9ab 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -36,20 +36,20 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { node_ptc_num += node_twist * node_offset; node_offset++; switch (node_type) { - case SOURCE: - case SINK: - case CHANY: + case t_rr_type::SOURCE: + case t_rr_type::SINK: + case t_rr_type::CHANY: node_lookup_.add_node(node, node_layer, ix, iy, node_type, node_ptc_num, TOTAL_2D_SIDES[0]); break; - case CHANX: + case t_rr_type::CHANX: /* Currently need to swap x and y for CHANX because of chan, seg convention * TODO: Once the builders is reworked for use consistent (x, y) convention, * the following swapping can be removed */ node_lookup_.add_node(node, node_layer, iy, ix, node_type, node_ptc_num, TOTAL_2D_SIDES[0]); break; - case OPIN: - case IPIN: + case t_rr_type::OPIN: + case t_rr_type::IPIN: for (const e_side& side : TOTAL_2D_SIDES) { if (node_storage_.is_node_on_specific_side(node, side)) { node_lookup_.add_node(node,node_layer, ix, iy, node_type, node_ptc_num, side); diff --git a/libs/librrgraph/src/base/rr_graph_obj.cpp b/libs/librrgraph/src/base/rr_graph_obj.cpp index fae02caf26e..91c18e9cb4c 100644 --- a/libs/librrgraph/src/base/rr_graph_obj.cpp +++ b/libs/librrgraph/src/base/rr_graph_obj.cpp @@ -81,7 +81,7 @@ vtr::Rect RRGraph::node_bounding_box(const RRNodeId& node) const { ***********************************************************************/ vtr::Point RRGraph::node_start_coordinate(const RRNodeId& node) const { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == node_type(node)) || (CHANY == node_type(node))); + VTR_ASSERT((e_rr_type::CHANX == node_type(node)) || (e_rr_type::CHANY == node_type(node))); vtr::Point start_coordinate(node_xlow(node), node_ylow(node)); @@ -105,7 +105,7 @@ vtr::Point RRGraph::node_start_coordinate(const RRNodeId& node) const { ***********************************************************************/ vtr::Point RRGraph::node_end_coordinate(const RRNodeId& node) const { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == node_type(node)) || (CHANY == node_type(node))); + VTR_ASSERT((e_rr_type::CHANX == node_type(node)) || (e_rr_type::CHANY == node_type(node))); vtr::Point end_coordinate(node_xhigh(node), node_yhigh(node)); @@ -135,19 +135,19 @@ short RRGraph::node_ptc_num(const RRNodeId& node) const { } short RRGraph::node_pin_num(const RRNodeId& node) const { - VTR_ASSERT_MSG(node_type(node) == IPIN || node_type(node) == OPIN, + VTR_ASSERT_MSG(node_type(node) == e_rr_type::IPIN || node_type(node) == e_rr_type::OPIN, "Pin number valid only for IPIN/OPIN RR nodes"); return node_ptc_num(node); } short RRGraph::node_track_num(const RRNodeId& node) const { - VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, + VTR_ASSERT_MSG(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY, "Track number valid only for CHANX/CHANY RR nodes"); return node_ptc_num(node); } short RRGraph::node_class_num(const RRNodeId& node) const { - VTR_ASSERT_MSG(node_type(node) == SOURCE || node_type(node) == SINK, "Class number valid only for SOURCE/SINK RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::SOURCE || node_type(node) == e_rr_type::SINK, "Class number valid only for SOURCE/SINK RR nodes"); return node_ptc_num(node); } @@ -158,13 +158,13 @@ RRIndexedDataId RRGraph::node_cost_index(const RRNodeId& node) const { Direction RRGraph::node_direction(const RRNodeId& node) const { VTR_ASSERT_SAFE(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, "Direction valid only for CHANX/CHANY RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY, "Direction valid only for CHANX/CHANY RR nodes"); return node_directions_[node]; } e_side RRGraph::node_side(const RRNodeId& node) const { VTR_ASSERT_SAFE(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == IPIN || node_type(node) == OPIN, "Side valid only for IPIN/OPIN RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::IPIN || node_type(node) == e_rr_type::OPIN, "Side valid only for IPIN/OPIN RR nodes"); return node_sides_[node]; } @@ -372,11 +372,11 @@ std::vector RRGraph::find_edges(const RRNodeId& src_node, const RRNode return matching_edges; } -RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& type, const int& ptc, const e_side& side) const { +RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type type, const int& ptc, const e_side& side) const { initialize_fast_node_lookup(); - size_t itype = type; - size_t iside = side; + const size_t itype = (size_t)type; + const size_t iside = side; /* Check if x, y, type and ptc, side is valid */ if ((x < 0) /* See if x is smaller than the index of first element */ @@ -401,14 +401,14 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ /* Check if x, y, type and ptc, side is valid */ if ((ptc < 0) /* See if ptc is smaller than the index of first element */ - || (size_t(ptc) > node_lookup_[x][y][type].size() - 1)) { /* See if ptc is large than the index of last element */ + || (size_t(ptc) > node_lookup_[x][y][itype].size() - 1)) { /* See if ptc is large than the index of last element */ /* Return a zero range! */ return RRNodeId::INVALID(); } /* Check if x, y, type and ptc, side is valid */ /* iside is always larger than -1, we can skip checking */ - if (iside > node_lookup_[x][y][type][ptc].size() - 1) { /* See if side is large than the index of last element */ + if (iside > node_lookup_[x][y][itype][ptc].size() - 1) { /* See if side is large than the index of last element */ /* Return a zero range! */ return RRNodeId::INVALID(); } @@ -419,7 +419,7 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ /* Find the channel width (number of tracks) of a channel [x][y] */ short RRGraph::chan_num_tracks(const short& x, const short& y, const t_rr_type& type) const { /* Must be CHANX or CHANY */ - VTR_ASSERT_MSG(CHANX == type || CHANY == type, + VTR_ASSERT_MSG(e_rr_type::CHANX == type || e_rr_type::CHANY == type, "Required node_type to be CHANX or CHANY!"); initialize_fast_node_lookup(); @@ -432,18 +432,18 @@ short RRGraph::chan_num_tracks(const short& x, const short& y, const t_rr_type& /* Check if x, y, type and ptc is valid */ if ((y < 0) /* See if y is smaller than the index of first element */ - || (size_t(y) > node_lookup_[x].size() - 1)) { /* See if y is large than the index of last element */ + || (size_t(y) > node_lookup_[x].size() - 1)) { /* See if y is larger than the index of last element */ /* Return a zero range! */ return 0; } /* Check if x, y, type and ptc is valid */ - if ((size_t(type) > node_lookup_[x][y].size() - 1)) { /* See if type is large than the index of last element */ + if ((size_t(type) > node_lookup_[x][y].size() - 1)) { /* See if type is larger than the index of last element */ /* Return a zero range! */ return 0; } - const auto& matching_nodes = node_lookup_[x][y][type]; + const auto& matching_nodes = node_lookup_[x][y][(size_t)type]; return vtr::make_range(matching_nodes.begin(), matching_nodes.end()).size(); } @@ -451,7 +451,7 @@ short RRGraph::chan_num_tracks(const short& x, const short& y, const t_rr_type& /* This function aims to print basic information about a node */ void RRGraph::print_node(const RRNodeId& node) const { VTR_LOG("Node id: %d\n", node_index(node)); - VTR_LOG("Node type: %s\n", rr_node_typename[node_type(node)]); + VTR_LOG("Node type: %s\n", rr_node_typename[(size_t)node_type(node)]); VTR_LOG("Node xlow: %d\n", node_xlow(node)); VTR_LOG("Node ylow: %d\n", node_ylow(node)); VTR_LOG("Node xhigh: %d\n", node_xhigh(node)); @@ -465,8 +465,8 @@ void RRGraph::print_node(const RRNodeId& node) const { bool RRGraph::validate_node_segment(const RRNodeId& node) const { VTR_ASSERT_SAFE(valid_node_id(node)); /* Only CHANX and CHANY requires a valid segment id */ - if ((CHANX == node_type(node)) - || (CHANY == node_type(node))) { + if ((e_rr_type::CHANX == node_type(node)) + || (e_rr_type::CHANY == node_type(node))) { return valid_segment_id(node_segments_[node]); } else { return true; @@ -477,7 +477,7 @@ bool RRGraph::validate_node_segment(const RRNodeId& node) const { bool RRGraph::validate_node_segments() const { bool all_valid = true; for (auto node : nodes()) { - if (true == validate_node_segment(node)) { + if (validate_node_segment(node)) { continue; } /* Reach here it means we find an invalid segment id */ @@ -499,7 +499,7 @@ bool RRGraph::validate_edge_switch(const RREdgeId& edge) const { bool RRGraph::validate_edge_switches() const { bool all_valid = true; for (auto edge : edges()) { - if (true == validate_edge_switch(edge)) { + if (validate_edge_switch(edge)) { continue; } /* Reach here it means we find an invalid segment id */ @@ -971,21 +971,24 @@ void RRGraph::set_node_ptc_num(const RRNodeId& node, const short& ptc) { void RRGraph::set_node_pin_num(const RRNodeId& node, const short& pin_id) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == IPIN || node_type(node) == OPIN, "Pin number valid only for IPIN/OPIN RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::IPIN || node_type(node) == e_rr_type::OPIN, + "Pin number valid only for IPIN/OPIN RR nodes"); set_node_ptc_num(node, pin_id); } void RRGraph::set_node_track_num(const RRNodeId& node, const short& track_id) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, "Track number valid only for CHANX/CHANY RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY, + "Track number valid only for CHANX/CHANY RR nodes"); set_node_ptc_num(node, track_id); } void RRGraph::set_node_class_num(const RRNodeId& node, const short& class_id) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == SOURCE || node_type(node) == SINK, "Class number valid only for SOURCE/SINK RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::SOURCE || node_type(node) == e_rr_type::SINK, + "Class number valid only for SOURCE/SINK RR nodes"); set_node_ptc_num(node, class_id); } @@ -997,14 +1000,14 @@ void RRGraph::set_node_cost_index(const RRNodeId& node, const RRIndexedDataId& c void RRGraph::set_node_direction(const RRNodeId& node, const Direction& direction) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, "Direct can only be specified on CHANX/CNAY rr nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY, "Direct can only be specified on CHANX/CNAY rr nodes"); node_directions_[node] = direction; } void RRGraph::set_node_side(const RRNodeId& node, const e_side& side) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == IPIN || node_type(node) == OPIN, "Side can only be specified on IPIN/OPIN rr nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::IPIN || node_type(node) == e_rr_type::OPIN, "Side can only be specified on IPIN/OPIN rr nodes"); node_sides_[node] = side; } @@ -1028,8 +1031,8 @@ void RRGraph::set_node_segment(const RRNodeId& node, const RRSegmentId& segment_ VTR_ASSERT(valid_node_id(node)); /* Only CHANX and CHANY requires a valid segment id */ - if ((CHANX == node_type(node)) - || (CHANY == node_type(node))) { + if ((e_rr_type::CHANX == node_type(node)) + || (e_rr_type::CHANY == node_type(node))) { VTR_ASSERT(valid_segment_id(segment_id)); } @@ -1119,7 +1122,7 @@ void RRGraph::build_fast_node_lookup() const { node_lookup_[x].resize(y + 1); } - size_t itype = node_type(node); + size_t itype = (size_t)node_type(node); if (itype >= node_lookup_[x][y].size()) { node_lookup_[x][y].resize(itype + 1); } @@ -1130,7 +1133,7 @@ void RRGraph::build_fast_node_lookup() const { } size_t iside = -1; - if (node_type(node) == OPIN || node_type(node) == IPIN) { + if (node_type(node) == e_rr_type::OPIN || node_type(node) == e_rr_type::IPIN) { iside = node_side(node); } else { iside = NUM_2D_SIDES; diff --git a/libs/librrgraph/src/base/rr_graph_obj.h b/libs/librrgraph/src/base/rr_graph_obj.h index 5ad31ba7f01..bd4e781046e 100644 --- a/libs/librrgraph/src/base/rr_graph_obj.h +++ b/libs/librrgraph/src/base/rr_graph_obj.h @@ -510,7 +510,7 @@ class RRGraph { /* Find the edges connecting two nodes */ std::vector find_edges(const RRNodeId& src_node, const RRNodeId& sink_node) const; /* Find a node with given features from internal fast look-up */ - RRNodeId find_node(const short& x, const short& y, const t_rr_type& type, const int& ptc, const e_side& side = NUM_2D_SIDES) const; + RRNodeId find_node(const short& x, const short& y, const t_rr_type type, const int& ptc, const e_side& side = NUM_2D_SIDES) const; /* Find the number of routing tracks in a routing channel with a given coordinate */ short chan_num_tracks(const short& x, const short& y, const t_rr_type& type) const; diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index cb7ad810dd8..89afcaeeba4 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -608,10 +608,10 @@ bool t_rr_graph_storage::validate(const vtr::vector } const char* t_rr_graph_storage::node_type_string(RRNodeId id) const { - return rr_node_typename[node_type(id)]; + return rr_node_typename[(size_t)node_type(id)]; } const char* t_rr_graph_view::node_type_string(RRNodeId id) const { - return rr_node_typename[node_type(id)]; + return rr_node_typename[(size_t)node_type(id)]; } const std::string& t_rr_graph_storage::node_direction_string(RRNodeId id) const { @@ -645,21 +645,21 @@ void t_rr_graph_storage::set_node_ptc_num(RRNodeId id, int new_ptc_num) { node_ptc_[id].ptc_.pin_num = new_ptc_num; //TODO: eventually remove } void t_rr_graph_storage::set_node_pin_num(RRNodeId id, int new_pin_num) { - if (node_type(id) != IPIN && node_type(id) != OPIN) { + if (node_type(id) != e_rr_type::IPIN && node_type(id) != e_rr_type::OPIN) { VTR_LOG_ERROR("Attempted to set RR node 'pin_num' for non-IPIN/OPIN type '%s'", node_type_string(id)); } node_ptc_[id].ptc_.pin_num = new_pin_num; } void t_rr_graph_storage::set_node_track_num(RRNodeId id, int new_track_num) { - if (node_type(id) != CHANX && node_type(id) != CHANY) { + if (node_type(id) != e_rr_type::CHANX && node_type(id) != e_rr_type::CHANY) { VTR_LOG_ERROR("Attempted to set RR node 'track_num' for non-CHANX/CHANY type '%s'", node_type_string(id)); } node_ptc_[id].ptc_.track_num = new_track_num; } void t_rr_graph_storage::set_node_class_num(RRNodeId id, int new_class_num) { - if (node_type(id) != SOURCE && node_type(id) != SINK) { + if (node_type(id) != e_rr_type::SOURCE && node_type(id) != e_rr_type::SINK) { VTR_LOG_ERROR("Attempted to set RR node 'class_num' for non-SOURCE/SINK type '%s'", node_type_string(id)); } node_ptc_[id].ptc_.class_num = new_class_num; @@ -673,9 +673,9 @@ static int get_node_pin_num( vtr::array_view_id node_storage, vtr::array_view_id node_ptc, RRNodeId id) { - auto node_type = node_storage[id].type_; - if (node_type != IPIN && node_type != OPIN) { - VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'", rr_node_typename[node_type]); + t_rr_type node_type = node_storage[id].type_; + if (node_type != e_rr_type::IPIN && node_type != e_rr_type::OPIN) { + VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'", rr_node_typename[(size_t)node_type]); } return node_ptc[id].ptc_.pin_num; } @@ -684,9 +684,9 @@ static int get_node_track_num( vtr::array_view_id node_storage, vtr::array_view_id node_ptc, RRNodeId id) { - auto node_type = node_storage[id].type_; - if (node_type != CHANX && node_type != CHANY) { - VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'", rr_node_typename[node_type]); + t_rr_type node_type = node_storage[id].type_; + if (node_type != e_rr_type::CHANX && node_type != e_rr_type::CHANY) { + VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'", rr_node_typename[(size_t)node_type]); } return node_ptc[id].ptc_.track_num; } @@ -695,9 +695,9 @@ static int get_node_class_num( vtr::array_view_id node_storage, vtr::array_view_id node_ptc, RRNodeId id) { - auto node_type = node_storage[id].type_; - if (node_type != SOURCE && node_type != SINK) { - VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'", rr_node_typename[node_type]); + t_rr_type node_type = node_storage[id].type_; + if (node_type != e_rr_type::SOURCE && node_type != e_rr_type::SINK) { + VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'", rr_node_typename[(size_t)node_type]); } return node_ptc[id].ptc_.class_num; } @@ -725,7 +725,7 @@ void t_rr_graph_storage::set_node_type(RRNodeId id, t_rr_type new_type) { node_storage_[id].type_ = new_type; } -void t_rr_graph_storage::set_node_name(RRNodeId id, std::string new_name) { +void t_rr_graph_storage::set_node_name(RRNodeId id, const std::string& new_name) { node_name_.insert(std::make_pair(id, new_name)); } void t_rr_graph_storage::set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2) { @@ -766,14 +766,14 @@ void t_rr_graph_storage::set_node_capacity(RRNodeId id, short new_capacity) { } void t_rr_graph_storage::set_node_direction(RRNodeId id, Direction new_direction) { - if (node_type(id) != CHANX && node_type(id) != CHANY) { + if (node_type(id) != e_rr_type::CHANX && node_type(id) != e_rr_type::CHANY) { VTR_LOG_ERROR("Attempted to set RR node 'direction' for non-channel type '%s'", node_type_string(id)); } node_storage_[id].dir_side_.direction = new_direction; } void t_rr_graph_storage::add_node_side(RRNodeId id, e_side new_side) { - if (node_type(id) != IPIN && node_type(id) != OPIN) { + if (node_type(id) != e_rr_type::IPIN && node_type(id) != e_rr_type::OPIN) { VTR_LOG_ERROR("Attempted to set RR node 'side' for non-channel type '%s'", node_type_string(id)); } std::bitset side_bits = node_storage_[id].dir_side_.sides; diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index ac6bece7526..3bb930f55b2 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -25,10 +25,10 @@ * parallel rr_node_* structures. * * * * This structure should **only** contain data used in the inner loop of the * - * router. This data is consider "hot" and the router performance is * + * router. This data is considered "hot" and the router performance is * * sensitive to layout and size of this "hot" data. * - * Cold data should be stored seperately in t_rr_graph_storage. * + * Cold data should be stored separately in t_rr_graph_storage. * * * * xlow, xhigh, ylow, yhigh: Integer coordinates (see route.c for * * coordinate system) of the ends of this routing resource. * @@ -63,7 +63,7 @@ struct alignas(16) t_rr_node_data { int16_t xhigh_ = -1; int16_t yhigh_ = -1; - t_rr_type type_ = NUM_RR_TYPES; + t_rr_type type_ = t_rr_type::NUM_RR_TYPES; /* The character is a hex number which is a 4-bit truth table for node sides * The 4-bits in serial represent 4 sides on which a node could appear @@ -620,7 +620,7 @@ class t_rr_graph_storage { void set_node_class_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_type(RRNodeId id, t_rr_type new_type); - void set_node_name(RRNodeId id, std::string new_name); + void set_node_name(RRNodeId id, const std::string& new_name); void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2); void set_node_layer(RRNodeId id, short layer); void set_node_ptc_twist_incr(RRNodeId id, short twist); @@ -781,9 +781,9 @@ class t_rr_graph_storage { const RRNodeId& id, const e_side& side) { auto& node_data = node_storage[id]; - if (node_data.type_ != IPIN && node_data.type_ != OPIN) { + if (node_data.type_ != e_rr_type::IPIN && node_data.type_ != e_rr_type::OPIN) { VTR_LOG_ERROR("Attempted to access RR node 'side' for non-IPIN/OPIN type '%s'", - rr_node_typename[node_data.type_]); + rr_node_typename[(size_t)node_data.type_]); } // Return a vector showing only the sides that the node appears std::bitset side_tt = node_storage[id].dir_side_.sides; diff --git a/libs/librrgraph/src/base/rr_graph_utils.cpp b/libs/librrgraph/src/base/rr_graph_utils.cpp index 1769d1cae5f..215ef5cc9d8 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.cpp +++ b/libs/librrgraph/src/base/rr_graph_utils.cpp @@ -76,7 +76,7 @@ std::vector find_rr_graph_switches(const RRGraph& rr_graph, } int seg_index_of_cblock(const RRGraphView& rr_graph, t_rr_type from_rr_type, int to_node) { - if (from_rr_type == CHANX) + if (from_rr_type == t_rr_type::CHANX) return (rr_graph.node_xlow(RRNodeId(to_node))); else /* CHANY */ @@ -89,10 +89,10 @@ int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) from_rr_type = rr_graph.node_type(RRNodeId(from_node)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (from_rr_type == CHANX) { - if (to_rr_type == CHANY) { + if (from_rr_type == t_rr_type::CHANX) { + if (to_rr_type == t_rr_type::CHANY) { return (rr_graph.node_xlow(RRNodeId(to_node))); - } else if (to_rr_type == CHANX) { + } else if (to_rr_type == t_rr_type::CHANX) { if (rr_graph.node_xlow(RRNodeId(to_node)) > rr_graph.node_xlow(RRNodeId(from_node))) { /* Going right */ return (rr_graph.node_xhigh(RRNodeId(from_node))); } else { /* Going left */ @@ -106,10 +106,10 @@ int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) } } /* End from_rr_type is CHANX */ - else if (from_rr_type == CHANY) { - if (to_rr_type == CHANX) { + else if (from_rr_type == t_rr_type::CHANY) { + if (to_rr_type == t_rr_type::CHANX) { return (rr_graph.node_ylow(RRNodeId(to_node))); - } else if (to_rr_type == CHANY) { + } else if (to_rr_type == t_rr_type::CHANY) { if (rr_graph.node_ylow(RRNodeId(to_node)) > rr_graph.node_ylow(RRNodeId(from_node))) { /* Going up */ return (rr_graph.node_yhigh(RRNodeId(from_node))); } else { /* Going down */ @@ -218,17 +218,17 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil } // Remove old locations from lookup - VTR_ASSERT(rr_graph_builder.node_lookup().find_node(node_layer, new_loc.x(), new_loc.y(), SINK, node_ptc) != RRNodeId::INVALID()); + VTR_ASSERT(rr_graph_builder.node_lookup().find_node(node_layer, new_loc.x(), new_loc.y(), t_rr_type::SINK, node_ptc) != RRNodeId::INVALID()); for (int x = tile_bb.xmin(); x <= tile_bb.xmax(); ++x) { for (int y = tile_bb.ymin(); y <= tile_bb.ymax(); ++y) { if (x == new_loc.x() && y == new_loc.y()) /* The new sink location */ continue; - if (rr_graph_builder.node_lookup().find_node(node_layer, x, y, SINK, node_ptc) == RRNodeId::INVALID()) /* Already removed */ + if (rr_graph_builder.node_lookup().find_node(node_layer, x, y, t_rr_type::SINK, node_ptc) == RRNodeId::INVALID()) /* Already removed */ continue; - bool removed_successfully = rr_graph_builder.node_lookup().remove_node(node_id, node_layer, x, y, SINK, node_ptc); + bool removed_successfully = rr_graph_builder.node_lookup().remove_node(node_id, node_layer, x, y, t_rr_type::SINK, node_ptc); VTR_ASSERT(removed_successfully); } } diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index c3a2ff6273f..83668e05d08 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -244,7 +244,7 @@ class RRGraphView { * @note node_length() only applies to CHANX or CHANY and is always a positive number */ inline int node_length(RRNodeId node) const { - VTR_ASSERT(node_type(node) == CHANX || node_type(node) == CHANY); + VTR_ASSERT(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY); if (node_direction(node) == Direction::NONE) { return 0; //length zero wire } @@ -256,7 +256,7 @@ class RRGraphView { /** @brief Check if a routing resource node is initialized. */ inline bool node_is_initialized(RRNodeId node) const { - return !((node_type(node) == NUM_RR_TYPES) + return !((node_type(node) == t_rr_type::NUM_RR_TYPES) && (node_xlow(node) == -1) && (node_ylow(node) == -1) && (node_xhigh(node) == -1) && (node_yhigh(node) == -1)); } @@ -265,7 +265,7 @@ class RRGraphView { * @note This function performs error checking by determining whether two nodes are physically adjacent based on their geometry. It does not verify the routing edges to confirm if a connection is feasible within the current routing graph. */ inline bool nodes_are_adjacent(RRNodeId chanx_node, RRNodeId chany_node) const { - VTR_ASSERT(node_type(chanx_node) == CHANX && node_type(chany_node) == CHANY); + VTR_ASSERT(node_type(chanx_node) == e_rr_type::CHANX && node_type(chany_node) == e_rr_type::CHANY); if (node_ylow(chany_node) > node_ylow(chanx_node) + 1 || // verifies that chany_node is not more than one unit above chanx_node node_yhigh(chany_node) < node_ylow(chanx_node)) // verifies that chany_node is not more than one unit beneath chanx_node return false; @@ -319,7 +319,7 @@ class RRGraphView { coordinate_string += ":" + std::to_string(size_t(node)) + " "; //add the index of the routing resource node int node_layer_num = node_layer(node); - if (node_type(node) == OPIN || node_type(node) == IPIN) { + if (node_type(node) == e_rr_type::OPIN || node_type(node) == e_rr_type::IPIN) { coordinate_string += "side: ("; //add the side of the routing resource node for (const e_side& node_side : TOTAL_2D_SIDES) { if (!is_node_on_specific_side(node, node_side)) { @@ -333,12 +333,12 @@ class RRGraphView { start_x = " (" + std::to_string(node_xhigh(node)) + ","; //start and end coordinates are the same for OPINs and IPINs start_y = std::to_string(node_yhigh(node)) + ","; start_layer_str = std::to_string(node_layer_num) + ")"; - } else if (node_type(node) == SOURCE || node_type(node) == SINK) { + } else if (node_type(node) == e_rr_type::SOURCE || node_type(node) == e_rr_type::SINK) { // For SOURCE and SINK the starting and ending coordinate are identical, so just use start start_x = " (" + std::to_string(node_xhigh(node)) + ","; start_y = std::to_string(node_yhigh(node)) + ","; start_layer_str = std::to_string(node_layer_num) + ")"; - } else if (node_type(node) == CHANX || node_type(node) == CHANY) { //for channels, we would like to describe the component with segment specific information + } else if (node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY) { //for channels, we would like to describe the component with segment specific information RRIndexedDataId cost_index = node_cost_index(node); int seg_index = rr_indexed_data_[cost_index].seg_index; coordinate_string += rr_segments(RRSegmentId(seg_index)).name; //Write the segment name diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index f8a9af655bb..3895861e3d0 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -1,5 +1,4 @@ -#ifndef RR_NODE_TYPES_H -#define RR_NODE_TYPES_H +#pragma once #include #include @@ -21,7 +20,7 @@ * - SOURCE * - SINK */ -typedef enum e_rr_type : unsigned char { +typedef enum class e_rr_type : unsigned char { SOURCE = 0, /// RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; -constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; +constexpr std::array RR_TYPES = {{e_rr_type::SOURCE, e_rr_type::SINK, e_rr_type::IPIN, + e_rr_type::OPIN, e_rr_type::CHANX, e_rr_type::CHANY}}; +constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; /* * Direction::INC: wire driver is positioned at the low-coordinate end of the wire. @@ -124,6 +124,4 @@ struct t_rr_rc_data { // This is the data type of fast lookups of an rr-node given an (rr_type, layer, x, y, and the side) //[0..num_rr_types-1][0..num_layer-1][0..grid_width-1][0..grid_height-1][0..NUM_2D_SIDES-1][0..max_ptc-1] -typedef std::array, 4>, NUM_RR_TYPES> t_rr_node_indices; - -#endif +typedef std::array, 4>, (size_t)t_rr_type::NUM_RR_TYPES> t_rr_node_indices; diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 6cc8102f502..00db875b932 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -21,10 +21,10 @@ RRNodeId RRSpatialLookup::find_node(int layer, * Please note that in the add_node function, we should keep the SAME convention! */ e_side node_side = side; - if (type == IPIN || type == OPIN) { + if (type == e_rr_type::IPIN || type == e_rr_type::OPIN) { VTR_ASSERT_MSG(side != NUM_2D_SIDES, "IPIN/OPIN must specify desired side (can not be default NUM_2D_SIDES)"); } else { - VTR_ASSERT_SAFE(type != IPIN && type != OPIN); + VTR_ASSERT_SAFE(type != e_rr_type::IPIN && type != e_rr_type::OPIN); node_side = TOTAL_2D_SIDES[0]; } @@ -41,11 +41,11 @@ RRNodeId RRSpatialLookup::find_node(int layer, */ size_t node_x = x; size_t node_y = y; - if (type == CHANX) { + if (type == e_rr_type::CHANX) { std::swap(node_x, node_y); } - VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); /* Sanity check to ensure the layer, x, y, side and ptc are in range * - Return an valid id by searching in look-up when all the parameters are in range @@ -55,27 +55,27 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - if (size_t(layer) >= rr_node_indices_[type].dim_size(0)) { + if (size_t(layer) >= rr_node_indices_[(size_t)type].dim_size(0)) { return RRNodeId::INVALID(); } - if (node_x >= rr_node_indices_[type].dim_size(1)) { + if (node_x >= rr_node_indices_[(size_t)type].dim_size(1)) { return RRNodeId::INVALID(); } - if(node_y >= rr_node_indices_[type].dim_size(2)){ + if(node_y >= rr_node_indices_[(size_t)type].dim_size(2)){ return RRNodeId::INVALID(); } - if (node_side >= rr_node_indices_[type].dim_size(3)) { + if (node_side >= rr_node_indices_[(size_t)type].dim_size(3)) { return RRNodeId::INVALID(); } - if (size_t(ptc) >= rr_node_indices_[type][layer][node_x][node_y][node_side].size()) { + if (size_t(ptc) >= rr_node_indices_[(size_t)type][layer][node_x][node_y][node_side].size()) { return RRNodeId::INVALID(); } - return rr_node_indices_[type][layer][node_x][node_y][node_side][ptc]; + return rr_node_indices_[(size_t)type][layer][node_x][node_y][node_side][ptc]; } std::vector RRSpatialLookup::find_nodes_in_range(int layer, @@ -122,11 +122,11 @@ std::vector RRSpatialLookup::find_nodes(int layer, */ size_t node_x = x; size_t node_y = y; - if (type == CHANX) { + if (type == e_rr_type::CHANX) { std::swap(node_x, node_y); } - VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); /* Sanity check to ensure the x, y, side are in range * - Return a list of valid ids by searching in look-up when all the parameters are in range @@ -136,32 +136,32 @@ std::vector RRSpatialLookup::find_nodes(int layer, return nodes; } - if (size_t(layer) >= rr_node_indices_[type].dim_size(0)) { + if (size_t(layer) >= rr_node_indices_[(size_t)type].dim_size(0)) { return nodes; } - if (node_x >= rr_node_indices_[type].dim_size(1)) { + if (node_x >= rr_node_indices_[(size_t)type].dim_size(1)) { return nodes; } - if(node_y >= rr_node_indices_[type].dim_size(2)){ + if(node_y >= rr_node_indices_[(size_t)type].dim_size(2)){ return nodes; } - if (side >= rr_node_indices_[type].dim_size(3)) { + if (side >= rr_node_indices_[(size_t)type].dim_size(3)) { return nodes; } /* Reserve space to avoid memory fragmentation */ size_t num_nodes = 0; - for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { + for (const auto& node : rr_node_indices_[(size_t)type][layer][node_x][node_y][side]) { if (node.is_valid()) { num_nodes++; } } nodes.reserve(num_nodes); - for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { + for (const auto& node : rr_node_indices_[(size_t)type][layer][node_x][node_y][side]) { if (node.is_valid()) { nodes.emplace_back(node); } @@ -175,7 +175,7 @@ std::vector RRSpatialLookup::find_channel_nodes(int layer, int y, t_rr_type type) const { /* Pre-check: node type should be routing tracks! */ - if (type != CHANX && type != CHANY) { + if (type != e_rr_type::CHANX && type != e_rr_type::CHANY) { return std::vector(); } @@ -190,7 +190,7 @@ std::vector RRSpatialLookup::find_nodes_at_all_sides(int layer, std::vector indices; /* TODO: Consider to access the raw data like find_node() rather than calling find_node() many times, which hurts runtime */ - if (rr_type == IPIN || rr_type == OPIN) { + if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { indices.reserve(NUM_2D_SIDES); //For pins, we need to look at all the sides of the current grid tile for (e_side side : TOTAL_2D_SIDES) { @@ -215,8 +215,8 @@ std::vector RRSpatialLookup::find_grid_nodes_at_all_sides(int layer, int x, int y, t_rr_type rr_type) const { - VTR_ASSERT(rr_type == SOURCE || rr_type == OPIN || rr_type == IPIN || rr_type == SINK); - if (rr_type == SOURCE || rr_type == SINK) { + VTR_ASSERT(rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::OPIN || rr_type == e_rr_type::IPIN || rr_type == e_rr_type::SINK); + if (rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::SINK) { return find_nodes(layer,x, y, rr_type); } @@ -241,16 +241,16 @@ void RRSpatialLookup::reserve_nodes(int layer, t_rr_type type, int num_nodes, e_side side) { - VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); /* For non-IPIN/OPIN nodes, the side should always be the TOP side which follows the convention in find_node() API! */ - if (type != IPIN && type != OPIN) { + if (type != e_rr_type::IPIN && type != e_rr_type::OPIN) { VTR_ASSERT(side == TOTAL_2D_SIDES[0]); } resize_nodes(layer, x, y, type, side); - rr_node_indices_[type][layer][x][y][side].reserve(num_nodes); + rr_node_indices_[(size_t)type][layer][x][y][side].reserve(num_nodes); } void RRSpatialLookup::add_node(RRNodeId node, @@ -261,22 +261,22 @@ void RRSpatialLookup::add_node(RRNodeId node, int ptc, e_side side) { VTR_ASSERT(node.is_valid()); /* Must have a valid node id to be added */ - VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); /* For non-IPIN/OPIN nodes, the side should always be the TOP side which follows the convention in find_node() API! */ - if (type != IPIN && type != OPIN) { + if (type != e_rr_type::IPIN && type != e_rr_type::OPIN) { VTR_ASSERT(side == TOTAL_2D_SIDES[0]); } resize_nodes(layer, x, y, type, side); - if (size_t(ptc) >= rr_node_indices_[type][layer][x][y][side].size()) { + if (size_t(ptc) >= rr_node_indices_[(size_t)type][layer][x][y][side].size()) { /* Deposit invalid ids to newly allocated elements while original elements are untouched */ - rr_node_indices_[type][layer][x][y][side].resize(ptc + 1, RRNodeId::INVALID()); + rr_node_indices_[(size_t)type][layer][x][y][side].resize(ptc + 1, RRNodeId::INVALID()); } /* Resize on demand finished; Register the node */ - rr_node_indices_[type][layer][x][y][side][ptc] = node; + rr_node_indices_[(size_t)type][layer][x][y][side][ptc] = node; } bool RRSpatialLookup::remove_node(RRNodeId node, @@ -287,26 +287,26 @@ bool RRSpatialLookup::remove_node(RRNodeId node, int ptc, e_side side) { VTR_ASSERT(node.is_valid()); - VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); VTR_ASSERT_SAFE(layer >= 0); VTR_ASSERT_SAFE(x >= 0); VTR_ASSERT_SAFE(y >= 0); - VTR_ASSERT_SAFE(type != NUM_RR_TYPES); + VTR_ASSERT_SAFE(type != t_rr_type::NUM_RR_TYPES); VTR_ASSERT_SAFE(ptc >= 0); VTR_ASSERT_SAFE(side != NUM_2D_SIDES); // Check if the node given is in the spatial lookup at the given indices - if (type >= rr_node_indices_.size()) return false; - if ((size_t)layer >= rr_node_indices_[type].dim_size(0)) return false; - if ((size_t)x >= rr_node_indices_[type].dim_size(1)) return false; - if ((size_t)y >= rr_node_indices_[type].dim_size(2)) return false; - if (side >= rr_node_indices_[type].dim_size(3)) return false; - if ((size_t)ptc >= rr_node_indices_[type][layer][x][y][side].size()) return false; - if (rr_node_indices_[type][layer][x][y][side][ptc] != node) return false; + if ((size_t)type >= rr_node_indices_.size()) return false; + if ((size_t)layer >= rr_node_indices_[(size_t)type].dim_size(0)) return false; + if ((size_t)x >= rr_node_indices_[(size_t)type].dim_size(1)) return false; + if ((size_t)y >= rr_node_indices_[(size_t)type].dim_size(2)) return false; + if (side >= rr_node_indices_[(size_t)type].dim_size(3)) return false; + if ((size_t)ptc >= rr_node_indices_[(size_t)type][layer][x][y][side].size()) return false; + if (rr_node_indices_[(size_t)type][layer][x][y][side][ptc] != node) return false; // The node was in the spatial lookup; remove it. -1 corresponds to an invalid node id, // and so is treated as absent in the spatial lookup - rr_node_indices_[type][layer][x][y][side][ptc] = RRNodeId::INVALID(); + rr_node_indices_[(size_t)type][layer][x][y][side][ptc] = RRNodeId::INVALID(); return true; } @@ -315,9 +315,9 @@ void RRSpatialLookup::mirror_nodes(const int layer, const vtr::Point& des_coord, t_rr_type type, e_side side) { - VTR_ASSERT(SOURCE == type); + VTR_ASSERT(e_rr_type::SOURCE == type); resize_nodes(layer, des_coord.x(), des_coord.y(), type, side); - rr_node_indices_[type][layer][des_coord.x()][des_coord.y()][side] = rr_node_indices_[type][layer][src_coord.x()][src_coord.y()][side]; + rr_node_indices_[(size_t)type][layer][des_coord.x()][des_coord.y()][side] = rr_node_indices_[(size_t)type][layer][src_coord.x()][src_coord.y()][side]; } void RRSpatialLookup::resize_nodes(int layer, @@ -329,23 +329,23 @@ void RRSpatialLookup::resize_nodes(int layer, * This may seldom happen because the rr_graph building function * should ensure the fast look-up well organized */ - VTR_ASSERT(type < rr_node_indices_.size()); + VTR_ASSERT((size_t)type < rr_node_indices_.size()); VTR_ASSERT(x >= 0); VTR_ASSERT(y >= 0); VTR_ASSERT(layer >= 0); - if ((layer >= int(rr_node_indices_[type].dim_size(0))) - || (x >= int(rr_node_indices_[type].dim_size(1))) - || (y >= int(rr_node_indices_[type].dim_size(2))) - || (size_t(side) >= rr_node_indices_[type].dim_size(3))) { - rr_node_indices_[type].resize({std::max(rr_node_indices_[type].dim_size(0),size_t(layer)+1), - std::max(rr_node_indices_[type].dim_size(1), size_t(x) + 1), - std::max(rr_node_indices_[type].dim_size(2), size_t(y) + 1), - std::max(rr_node_indices_[type].dim_size(3), size_t(side) + 1)}); + if ((layer >= int(rr_node_indices_[(size_t)type].dim_size(0))) + || (x >= int(rr_node_indices_[(size_t)type].dim_size(1))) + || (y >= int(rr_node_indices_[(size_t)type].dim_size(2))) + || (size_t(side) >= rr_node_indices_[(size_t)type].dim_size(3))) { + rr_node_indices_[(size_t)type].resize({std::max(rr_node_indices_[(size_t)type].dim_size(0),size_t(layer)+1), + std::max(rr_node_indices_[(size_t)type].dim_size(1), size_t(x) + 1), + std::max(rr_node_indices_[(size_t)type].dim_size(2), size_t(y) + 1), + std::max(rr_node_indices_[(size_t)type].dim_size(3), size_t(side) + 1)}); } } -void RRSpatialLookup::reorder(const vtr::vector dest_order) { +void RRSpatialLookup::reorder(const vtr::vector& dest_order) { // update rr_node_indices, a map to optimize rr_index lookups for (auto& grid : rr_node_indices_) { for(size_t l = 0; l < grid.dim_size(0); l++) { diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.h b/libs/librrgraph/src/base/rr_spatial_lookup.h index 6a4ca5f1b1c..049175e587c 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.h +++ b/libs/librrgraph/src/base/rr_spatial_lookup.h @@ -270,7 +270,7 @@ class RRSpatialLookup { e_side side); /** @brief Reorder the internal look up to be more memory efficient */ - void reorder(const vtr::vector dest_order); + void reorder(const vtr::vector& dest_order); /** @brief Clear all the data inside */ void clear(); diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index c97039f1821..ad23948815d 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -744,7 +744,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { if (uxsd::enum_loc_side::UXSD_INVALID == side) { // node_loc.side is only expected on IPIN/OPIN. - if (rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN) { + if (rr_graph.node_type(node.id()) == e_rr_type::IPIN || rr_graph.node_type(node.id()) == e_rr_type::OPIN) { report_error( "inode %d is type %d, which requires a side, but no side was supplied.", inode, rr_graph.node_type(node.id())); @@ -767,7 +767,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { inline uxsd::enum_loc_side get_node_loc_side(const t_rr_node& node) final { const auto& rr_graph = (*rr_graph_); - if (rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN) { + if (rr_graph.node_type(node.id()) == e_rr_type::IPIN || rr_graph.node_type(node.id()) == e_rr_type::OPIN) { std::bitset sides_bitset; for (const e_side& side : TOTAL_2D_SIDES) { if (rr_graph.is_node_on_specific_side(node.id(), side)) { @@ -825,11 +825,11 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { if (e_graph_type::GLOBAL == graph_type_) { rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(0)); - } else if (rr_graph.node_type(node.id()) == CHANX) { + } else if (rr_graph.node_type(node.id()) == e_rr_type::CHANX) { int seg_ind_x = find_segment_index_along_axis(segment_id, X_AXIS); rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(CHANX_COST_INDEX_START + seg_ind_x)); seg_index_[rr_graph.node_cost_index(node.id())] = segment_id; - } else if (rr_graph.node_type(node.id()) == CHANY) { + } else if (rr_graph.node_type(node.id()) == e_rr_type::CHANY) { int seg_ind_y = find_segment_index_along_axis(segment_id, Y_AXIS); rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(CHANX_COST_INDEX_START + segment_inf_x_.size() + seg_ind_y)); seg_index_[rr_graph.node_cost_index(node.id())] = segment_id; @@ -889,20 +889,20 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { rr_graph_builder_->set_node_capacity(node_id, capacity); switch (rr_graph.node_type(node.id())) { - case CHANX: + case e_rr_type::CHANX: break; - case CHANY: + case e_rr_type::CHANY: break; - case SOURCE: + case e_rr_type::SOURCE: rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(SOURCE_COST_INDEX)); break; - case SINK: + case e_rr_type::SINK: rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(SINK_COST_INDEX)); break; - case OPIN: + case e_rr_type::OPIN: rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(OPIN_COST_INDEX)); break; - case IPIN: + case e_rr_type::IPIN: rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(IPIN_COST_INDEX)); break; default: @@ -962,7 +962,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { RRNodeId node_id = node.id(); if (direction == uxsd::enum_node_direction::UXSD_INVALID) { - if (rr_graph.node_type(node.id()) == CHANX || rr_graph.node_type(node.id()) == CHANY) { + if (rr_graph.node_type(node.id()) == e_rr_type::CHANX || rr_graph.node_type(node.id()) == e_rr_type::CHANY) { report_error( "inode %d is type %d, which requires a direction, but no direction was supplied.", inode, rr_graph.node_type(node.id())); @@ -973,7 +973,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { } inline uxsd::enum_node_direction get_node_direction(const t_rr_node& node) final { const auto& rr_graph = (*rr_graph_); - if (rr_graph.node_type(node.id()) == CHANX || rr_graph.node_type(node.id()) == CHANY) { + if (rr_graph.node_type(node.id()) == e_rr_type::CHANX || rr_graph.node_type(node.id()) == e_rr_type::CHANY) { return to_uxsd_node_direction(rr_graph.node_direction(node.id())); } else { return uxsd::enum_node_direction::UXSD_INVALID; @@ -1158,8 +1158,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { /*Keeps track of the number of the specific type of switch that connects a wire to an ipin * use the pair data structure to keep the maximum*/ - if (rr_graph.node_type(node.id()) == CHANX || rr_graph.node_type(node.id()) == CHANY) { - if(rr_graph.node_type(RRNodeId(sink_node)) == IPIN){ + if (rr_graph.node_type(node.id()) == e_rr_type::CHANX || rr_graph.node_type(node.id()) == e_rr_type::CHANY) { + if(rr_graph.node_type(RRNodeId(sink_node)) == e_rr_type::IPIN){ if (rr_graph.node_layer(RRNodeId(sink_node)) == rr_graph.node_layer(RRNodeId(source_node))) { count_for_wire_to_ipin_switches[switch_id]++; if (count_for_wire_to_ipin_switches[switch_id] > most_frequent_switch.second) { @@ -1848,7 +1848,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { /* Alloc the lookup table */ for (t_rr_type rr_type : RR_TYPES) { - if (rr_type == CHANX) { + if (rr_type == e_rr_type::CHANX) { rr_graph_builder.node_lookup().resize_nodes(grid_.get_num_layers(), grid_.height(), grid_.width(), rr_type, NUM_2D_SIDES); } else { rr_graph_builder.node_lookup().resize_nodes(grid_.get_num_layers(), grid_.width(), grid_.height(), rr_type, NUM_2D_SIDES); @@ -2007,17 +2007,17 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { t_rr_type from_uxsd_node_type(uxsd::enum_node_type type) { switch (type) { case uxsd::enum_node_type::CHANX: - return CHANX; + return e_rr_type::CHANX; case uxsd::enum_node_type::CHANY: - return CHANY; + return e_rr_type::CHANY; case uxsd::enum_node_type::SOURCE: - return SOURCE; + return e_rr_type::SOURCE; case uxsd::enum_node_type::SINK: - return SINK; + return e_rr_type::SINK; case uxsd::enum_node_type::OPIN: - return OPIN; + return e_rr_type::OPIN; case uxsd::enum_node_type::IPIN: - return IPIN; + return e_rr_type::IPIN; default: report_error( "Invalid node type %d", @@ -2026,17 +2026,17 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { } uxsd::enum_node_type to_uxsd_node_type(t_rr_type type) { switch (type) { - case CHANX: + case e_rr_type::CHANX: return uxsd::enum_node_type::CHANX; - case CHANY: + case e_rr_type::CHANY: return uxsd::enum_node_type::CHANY; - case SOURCE: + case e_rr_type::SOURCE: return uxsd::enum_node_type::SOURCE; - case SINK: + case e_rr_type::SINK: return uxsd::enum_node_type::SINK; - case OPIN: + case e_rr_type::OPIN: return uxsd::enum_node_type::OPIN; - case IPIN: + case e_rr_type::IPIN: return uxsd::enum_node_type::IPIN; default: report_error( diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 1cfdba42f92..0496e605a49 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -198,8 +198,8 @@ std::vector find_ortho_cost_index(const RRGraphView& rr_graph, //if the type is smaller than start index, means destination is not a CHAN type node. - if ((from_node_type == CHANX && to_node_type == CHANY) || (from_node_type == CHANY && to_node_type == CHANX)) { - if (to_node_type == CHANY) { + if ((from_node_type == e_rr_type::CHANX && to_node_type == e_rr_type::CHANY) || (from_node_type == e_rr_type::CHANY && to_node_type == e_rr_type::CHANX)) { + if (to_node_type == e_rr_type::CHANY) { dest_nodes_count[from_node_cost_index - CHANX_COST_INDEX_START][to_node_cost_index - (CHANX_COST_INDEX_START + segment_inf_x.size())]++; } else { dest_nodes_count[from_node_cost_index - CHANX_COST_INDEX_START][to_node_cost_index - CHANX_COST_INDEX_START]++; @@ -430,7 +430,7 @@ static std::vector count_rr_segment_types(const RRGraphView& rr_graph, c std::vector rr_segment_type_counts; for (const RRNodeId& id : rr_graph.nodes()) { - if (rr_graph.node_type(id) != CHANX && rr_graph.node_type(id) != CHANY) continue; + if (rr_graph.node_type(id) != e_rr_type::CHANX && rr_graph.node_type(id) != e_rr_type::CHANY) continue; auto cost_index = rr_graph.node_cost_index(id); @@ -528,7 +528,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, for (const RRNodeId& rr_id : rr_graph.nodes()) { t_rr_type rr_type = rr_graph.node_type(rr_id); - if (rr_type != CHANX && rr_type != CHANY) { + if (rr_type != e_rr_type::CHANX && rr_type != e_rr_type::CHANY) { continue; } @@ -647,7 +647,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou buffered = UNDEFINED; for (const auto& edge : fan_in_list[node]) { /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */ - if (rr_graph.node_type(node) == CHANX || rr_graph.node_type(node) == CHANY) { + if (rr_graph.node_type(node) == e_rr_type::CHANX || rr_graph.node_type(node) == e_rr_type::CHANY) { int switch_index = rr_graph.rr_nodes().edge_switch(edge); if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type() == SwitchType::SHORT) { diff --git a/libs/librrgraph/src/utils/describe_rr_node.cpp b/libs/librrgraph/src/utils/describe_rr_node.cpp index 6383e3489cc..3c00748f6d8 100644 --- a/libs/librrgraph/src/utils/describe_rr_node.cpp +++ b/libs/librrgraph/src/utils/describe_rr_node.cpp @@ -11,7 +11,7 @@ std::string describe_rr_node(const RRGraphView& rr_graph, bool is_flat) { std::string msg = vtr::string_fmt("RR node: %d", inode); - if (rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) { + if (rr_graph.node_type(inode) == e_rr_type::CHANX || rr_graph.node_type(inode) == e_rr_type::CHANY) { auto cost_index = rr_graph.node_cost_index(inode); int seg_index = rr_indexed_data[cost_index].seg_index; @@ -26,7 +26,7 @@ std::string describe_rr_node(const RRGraphView& rr_graph, rr_graph.node_track_num(inode), seg_index); } - } else if (rr_graph.node_type(inode) == IPIN || rr_graph.node_type(inode) == OPIN) { + } else if (rr_graph.node_type(inode) == e_rr_type::IPIN || rr_graph.node_type(inode) == e_rr_type::OPIN) { auto type = grid.get_physical_type({rr_graph.node_xlow(inode), rr_graph.node_ylow(inode), rr_graph.node_layer(inode)}); @@ -37,7 +37,7 @@ std::string describe_rr_node(const RRGraphView& rr_graph, rr_graph.node_pin_num(inode), pin_name.c_str()); } else { - VTR_ASSERT(rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK); msg += vtr::string_fmt(" class: %d", rr_graph.node_class_num(inode)); } diff --git a/utils/fasm/test/test_fasm.cpp b/utils/fasm/test/test_fasm.cpp index 9ee9a142b48..6411dd97f06 100644 --- a/utils/fasm/test/test_fasm.cpp +++ b/utils/fasm/test/test_fasm.cpp @@ -7,13 +7,11 @@ #include "rr_metadata.h" #include "fasm.h" #include "fasm_utils.h" -#include "arch_util.h" #include "rr_graph_writer.h" #include #include #include #include -#include #include "post_routing_pb_pin_fixup.h" #include "sync_netlists_to_routing_flat.h" @@ -77,7 +75,7 @@ TEST_CASE("substitute_tags_correct", "[fasm]") { auto result = fasm::substitute_tags(feature, tags); - REQUIRE(result.compare("LCLB_X7Y8_SLICE") == 0); + REQUIRE(result == "LCLB_X7Y8_SLICE"); } TEST_CASE("substitute_tags_undef", "[fasm]") { @@ -270,7 +268,7 @@ TEST_CASE("fasm_integration_test", "[fasm]") { // Add additional features to edges that go to CLB.I[11:0] pins // to correlate them with features of CLB input mux later. auto sink_type = rr_graph.node_type(RRNodeId(sink_inode)); - if (sink_type == IPIN) { + if (sink_type == e_rr_type::IPIN) { auto pin_feature = get_pin_feature(sink_inode); value = value + "\n" + pin_feature; } @@ -368,8 +366,8 @@ TEST_CASE("fasm_integration_test", "[fasm]") { continue; } - if (line.find("#") != std::string::npos) { - auto init_pos = line.find("#"); + if (line.find('#') != std::string::npos) { + auto init_pos = line.find('#'); lut_def = line.substr(init_pos+2); continue; } diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index 5074d79cc09..da911554a42 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -185,7 +185,7 @@ static void profile_source(const Netlist<>& net_list, VTR_ASSERT(sink_ptc != OPEN); //TODO: should pass layer_num instead of 0 to node_lookup once the multi-die FPGAs support is completed - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(0, sink_x, sink_y, SINK, sink_ptc); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(0, sink_x, sink_y, e_rr_type::SINK, sink_ptc); if (directconnect_exists(source_rr_node, sink_rr_node)) { //Skip if we shouldn't measure direct connects and a direct connect exists diff --git a/vpr/src/base/old_traceback.cpp b/vpr/src/base/old_traceback.cpp index a1bb21be232..7d00bdaaaf0 100644 --- a/vpr/src/base/old_traceback.cpp +++ b/vpr/src/base/old_traceback.cpp @@ -36,13 +36,13 @@ void TracebackCompat::traceback_to_route_tree_x(t_trace* trace, RouteTree& tree, new_node->R_upstream = std::numeric_limits::quiet_NaN(); new_node->C_downstream = std::numeric_limits::quiet_NaN(); new_node->Tdel = std::numeric_limits::quiet_NaN(); - auto node_type = rr_graph.node_type(inode); - if (node_type == IPIN || node_type == SINK) + e_rr_type node_type = rr_graph.node_type(inode); + if (node_type == e_rr_type::IPIN || node_type == e_rr_type::SINK) new_node->re_expand = false; else new_node->re_expand = true; - if (rr_graph.node_type(inode) == SINK) { + if (rr_graph.node_type(inode) == e_rr_type::SINK) { /* The traceback returns to the previous branch point if there is more than one SINK, otherwise we are at the last SINK */ if (trace->next) { RRNodeId next_rr_node = RRNodeId(trace->next->index); @@ -120,7 +120,7 @@ void print_traceback(const t_trace* trace) { const t_trace* prev = nullptr; while (trace) { RRNodeId inode(trace->index); - VTR_LOG("%d (%s)", inode, rr_node_typename[rr_graph.node_type(inode)]); + VTR_LOG("%d (%s)", inode, rr_node_typename[(size_t)rr_graph.node_type(inode)]); if (trace->iswitch == OPEN) { VTR_LOG(" !"); //End of branch diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index e06726fe817..fc354a90c9e 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -13,11 +13,8 @@ * other file's information */ -#include #include #include -#include -#include #include #include @@ -47,7 +44,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN static void process_nets(const Netlist<>& net_list, std::ifstream& fp, ClusterNetId inet, std::string name, std::vector input_tokens, const char* filename, int& lineno, bool is_flat); static void process_global_blocks(const Netlist<>& net_list, std::ifstream& fp, ClusterNetId inet, const char* filename, int& lineno, bool is_flat); static void format_coordinates(int& layer_num, int& x, int& y, std::string coord, ClusterNetId net, const char* filename, const int lineno); -static void format_pin_info(std::string& pb_name, std::string& port_name, int& pb_pin_num, std::string input); +static void format_pin_info(std::string& pb_name, std::string& port_name, int& pb_pin_num, const std::string& input); static std::string format_name(std::string name); static bool check_rr_graph_connectivity(RRNodeId prev_node, RRNodeId node); void print_route(const Netlist<>& net_list, FILE* fp, bool is_flat); @@ -497,7 +494,7 @@ static void format_coordinates(int& layer_num, int& x, int& y, std::string coord * @brief Parse the pin info in the form of pb_name.port_name[pb_pin_num] * into its appropriate variables */ -static void format_pin_info(std::string& pb_name, std::string& port_name, int& pb_pin_num, std::string input) { +static void format_pin_info(std::string& pb_name, std::string& port_name, int& pb_pin_num, const std::string& input) { std::stringstream pb_info(input); std::getline(pb_info, pb_name, '.'); std::getline(pb_info, port_name, '['); @@ -519,7 +516,7 @@ static std::string format_name(std::string name) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "%s should be enclosed by parenthesis", name.c_str()); - return nullptr; + return {}; } } @@ -536,7 +533,7 @@ static bool check_rr_graph_connectivity(RRNodeId prev_node, RRNodeId node) { auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; // If it's starting a new sub branch this is ok - if (rr_graph.node_type(prev_node) == SINK) return true; + if (rr_graph.node_type(prev_node) == e_rr_type::SINK) return true; for (RREdgeId edge : rr_graph.edge_range(prev_node)) { //If the sink node is reachable by previous node return true @@ -596,8 +593,8 @@ void print_route(const Netlist<>& net_list, rr_graph.node_yhigh(inode), layer_num); switch (rr_type) { - case IPIN: - case OPIN: + case e_rr_type::IPIN: + case e_rr_type::OPIN: if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) { fprintf(fp, " Pad: "); } else { /* IO Pad. */ @@ -605,13 +602,13 @@ void print_route(const Netlist<>& net_list, } break; - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: fprintf(fp, " Track: "); break; - case SOURCE: - case SINK: + case e_rr_type::SOURCE: + case e_rr_type::SINK: if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) { fprintf(fp, " Pad: "); } else { /* IO Pad. */ @@ -629,7 +626,7 @@ void print_route(const Netlist<>& net_list, fprintf(fp, "%d ", rr_graph.node_ptc_num(inode)); auto physical_tile = device_ctx.grid.get_physical_type({ilow, jlow, layer_num}); - if (!is_io_type(physical_tile) && (rr_type == IPIN || rr_type == OPIN)) { + if (!is_io_type(physical_tile) && (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN)) { int pin_num = rr_graph.node_pin_num(inode); int xoffset = device_ctx.grid.get_width_offset({ilow, jlow, layer_num}); int yoffset = device_ctx.grid.get_height_offset({ilow, jlow, layer_num}); @@ -654,7 +651,7 @@ void print_route(const Netlist<>& net_list, fprintf(fp, "Switch: %d", int(tptr->iswitch)); //Save net pin index for sinks - if (rr_type == SINK) { + if (rr_type == e_rr_type::SINK) { fprintf(fp, " Net_pin_index: %d", tptr->net_pin_index); } diff --git a/vpr/src/base/read_route.h b/vpr/src/base/read_route.h index 226a104a0b3..4758b0cf646 100644 --- a/vpr/src/base/read_route.h +++ b/vpr/src/base/read_route.h @@ -5,13 +5,10 @@ * This is used to perform --analysis only */ -#ifndef READ_ROUTE_H -#define READ_ROUTE_H +#pragma once #include "netlist.h" #include "vpr_types.h" bool read_route(const char* route_file, const t_router_opts& RouterOpts, bool verify_file_digests, bool is_flat); void print_route(const Netlist<>& net_list, const char* placement_file, const char* route_file, bool is_flat); - -#endif /* READ_ROUTE_H */ diff --git a/vpr/src/base/stats.cpp b/vpr/src/base/stats.cpp index 774235bf2cc..e2959ae6633 100644 --- a/vpr/src/base/stats.cpp +++ b/vpr/src/base/stats.cpp @@ -312,11 +312,11 @@ static void load_channel_occupancies(const Netlist<>& net_list, RRNodeId inode = rt_node.inode; t_rr_type rr_type = rr_graph.node_type(inode); - if (rr_type == CHANX) { + if (rr_type == t_rr_type::CHANX) { int j = rr_graph.node_ylow(inode); for (int i = rr_graph.node_xlow(inode); i <= rr_graph.node_xhigh(inode); i++) chanx_occ[i][j]++; - } else if (rr_type == CHANY) { + } else if (rr_type == t_rr_type::CHANY) { int i = rr_graph.node_xlow(inode); for (int j = rr_graph.node_ylow(inode); j <= rr_graph.node_yhigh(inode); j++) chany_occ[i][j]++; @@ -354,16 +354,16 @@ void get_num_bends_and_length(ParentNetId inet, int* bends_ptr, int* len_ptr, in RRNodeId inode = rt_node.inode; t_rr_type curr_type = rr_graph.node_type(inode); - if (curr_type == CHANX || curr_type == CHANY) { + if (curr_type == t_rr_type::CHANX || curr_type == t_rr_type::CHANY) { segments++; length += rr_graph.node_length(inode); - if (curr_type != prev_type && (prev_type == CHANX || prev_type == CHANY)) + if (curr_type != prev_type && (prev_type == t_rr_type::CHANX || prev_type == t_rr_type::CHANY)) bends++; } /* The all_nodes iterator walks all nodes in the tree. If we are at a leaf and going back to the top, prev_type is invalid: just set it to SINK */ - prev_type = rt_node.is_leaf() ? SINK : curr_type; + prev_type = rt_node.is_leaf() ? t_rr_type::SINK : curr_type; } *bends_ptr = bends; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index ddbcb59b08e..c2ca97e73fe 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -21,8 +21,7 @@ * The t_pb hierarchy follows what is described by t_pb_graph_node */ -#ifndef VPR_TYPES_H -#define VPR_TYPES_H +#pragma once #include #include @@ -1361,9 +1360,9 @@ struct t_det_routing_arch { std::string read_rr_edge_override_filename; }; -constexpr bool is_pin(e_rr_type type) { return (type == IPIN || type == OPIN); } -constexpr bool is_chan(e_rr_type type) { return (type == CHANX || type == CHANY); } -constexpr bool is_src_sink(e_rr_type type) { return (type == SOURCE || type == SINK); } +constexpr bool is_pin(e_rr_type type) { return (type == t_rr_type::IPIN || type == t_rr_type::OPIN); } +constexpr bool is_chan(e_rr_type type) { return (type == t_rr_type::CHANX || type == t_rr_type::CHANY); } +constexpr bool is_src_sink(e_rr_type type) { return (type == t_rr_type::SOURCE || type == t_rr_type::SINK); } /** * @brief Extra information about each rr_node needed only during routing @@ -1552,11 +1551,3 @@ class RouteStatus { typedef vtr::vector>> t_clb_opins_used; //[0..num_blocks-1][0..class-1][0..used_pins-1] typedef std::vector> t_arch_switch_fanin; - -struct pair_hash { - std::size_t operator()(const std::pair& p) const noexcept { - return std::hash()(p.first) ^ (std::hash()(p.second) << 1); - } -}; - -#endif diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index 5dc0c09523e..fe984f275d0 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -638,10 +638,10 @@ int get_track_num(int inode, const vtr::OffsetMatrix& chanx_track, const vt j = rr_graph.node_ylow(rr_node); /* length channel segments. */ switch (rr_type) { - case CHANX: + case t_rr_type::CHANX: return (chanx_track[i][j]); - case CHANY: + case t_rr_type::CHANY: return (chany_track[i][j]); default: diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index 2981dd308aa..770c8532115 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -351,13 +351,13 @@ void draw_congestion(ezgl::renderer* g) { color.alpha = transparency_factor; switch (rr_graph.node_type(inode)) { - case CHANX: //fallthrough - case CHANY: + case t_rr_type::CHANX: //fallthrough + case t_rr_type::CHANY: draw_rr_chan(inode, color, g); break; - case IPIN: //fallthrough - case OPIN: + case t_rr_type::IPIN: //fallthrough + case t_rr_type::OPIN: draw_rr_pin(inode, color, g); break; default: @@ -651,15 +651,15 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren ezgl::color color = draw_state->draw_rr_node[inode].color; switch (rr_type) { - case OPIN: { + case t_rr_type::OPIN: { draw_rr_pin(inode, color, g); break; } - case IPIN: { + case t_rr_type::IPIN: { draw_rr_pin(inode, color, g); if (edge_visibility.visible) { g->set_color(color, edge_visibility.alpha); - if (rr_graph.node_type(prev_node) == OPIN) { + if (rr_graph.node_type(prev_node) == t_rr_type::OPIN) { draw_pin_to_pin(prev_node, inode, g); } else { draw_pin_to_chan_edge(inode, prev_node, g); @@ -667,7 +667,7 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren } break; } - case CHANX: { + case t_rr_type::CHANX: { if (draw_state->draw_route_type == GLOBAL) chanx_track[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)]++; @@ -675,15 +675,15 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren if (edge_visibility.visible) { g->set_color(color, edge_visibility.alpha); switch (prev_type) { - case CHANX: { + case t_rr_type::CHANX: { draw_chanx_to_chanx_edge(prev_node, inode, switch_type, g); break; } - case CHANY: { + case t_rr_type::CHANY: { draw_chanx_to_chany_edge(inode, prev_node, FROM_Y_TO_X, switch_type, g); break; } - case OPIN: { + case t_rr_type::OPIN: { draw_pin_to_chan_edge(prev_node, inode, g); break; } @@ -697,7 +697,7 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren break; } - case CHANY: { + case t_rr_type::CHANY: { if (draw_state->draw_route_type == GLOBAL) chany_track[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)]++; @@ -706,17 +706,17 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren if (edge_visibility.visible) { g->set_color(color, edge_visibility.alpha); switch (prev_type) { - case CHANX: { + case t_rr_type::CHANX: { draw_chanx_to_chany_edge(prev_node, inode, FROM_X_TO_Y, switch_type, g); break; } - case CHANY: { + case t_rr_type::CHANY: { draw_chany_to_chany_edge(RRNodeId(prev_node), RRNodeId(inode), switch_type, g); break; } - case OPIN: { + case t_rr_type::OPIN: { draw_pin_to_chan_edge(prev_node, inode, g); break; @@ -839,11 +839,11 @@ void draw_routing_util(ezgl::renderer* g) { t_draw_coords* draw_coords = get_draw_coords_vars(); auto& device_ctx = g_vpr_ctx.device(); - auto chanx_usage = calculate_routing_usage(CHANX, draw_state->is_flat, false); - auto chany_usage = calculate_routing_usage(CHANY, draw_state->is_flat, false); + auto chanx_usage = calculate_routing_usage(t_rr_type::CHANX, draw_state->is_flat, false); + auto chany_usage = calculate_routing_usage(t_rr_type::CHANY, draw_state->is_flat, false); - auto chanx_avail = calculate_routing_avail(CHANX); - auto chany_avail = calculate_routing_avail(CHANY); + auto chanx_avail = calculate_routing_avail(t_rr_type::CHANX); + auto chany_avail = calculate_routing_avail(t_rr_type::CHANY); float min_util = 0.; float max_util = -std::numeric_limits::infinity(); diff --git a/vpr/src/draw/draw_rr.cpp b/vpr/src/draw/draw_rr.cpp index a47c76d3032..ad9e8e38cfb 100644 --- a/vpr/src/draw/draw_rr.cpp +++ b/vpr/src/draw/draw_rr.cpp @@ -62,20 +62,20 @@ void draw_rr(ezgl::renderer* g) { if (!draw_state->draw_rr_node[inode].node_highlighted) { /* If not highlighted node, assign color based on type. */ switch (rr_graph.node_type(inode)) { - case CHANX: - case CHANY: + case t_rr_type::CHANX: + case t_rr_type::CHANY: draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR; break; - case OPIN: + case t_rr_type::OPIN: draw_state->draw_rr_node[inode].color = ezgl::PINK; break; - case IPIN: + case t_rr_type::IPIN: draw_state->draw_rr_node[inode].color = blk_LIGHTSKYBLUE; break; - case SOURCE: + case t_rr_type::SOURCE: draw_state->draw_rr_node[inode].color = ezgl::PLUM; break; - case SINK: + case t_rr_type::SINK: draw_state->draw_rr_node[inode].color = ezgl::DARK_SLATE_BLUE; break; default: @@ -90,30 +90,30 @@ void draw_rr(ezgl::renderer* g) { /* Now call drawing routines to draw the node. */ switch (rr_graph.node_type(inode)) { - case SINK: + case t_rr_type::SINK: draw_rr_src_sink(inode, draw_state->draw_rr_node[inode].color, g); break; - case SOURCE: + case t_rr_type::SOURCE: draw_rr_edges(inode, g); draw_rr_src_sink(inode, draw_state->draw_rr_node[inode].color, g); break; - case CHANX: + case t_rr_type::CHANX: draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; - case CHANY: + case t_rr_type::CHANY: draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; - case IPIN: + case t_rr_type::IPIN: draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; - case OPIN: + case t_rr_type::OPIN: draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; @@ -135,7 +135,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { t_rr_type type = rr_graph.node_type(inode); - VTR_ASSERT(type == CHANX || type == CHANY); + VTR_ASSERT(type == t_rr_type::CHANX || type == t_rr_type::CHANY); ezgl::rectangle bound_box = draw_get_rr_chan_bbox(inode); Direction dir = rr_graph.node_direction(inode); @@ -163,7 +163,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { e_side mux_dir = TOP; int coord_min = -1; int coord_max = -1; - if (type == CHANX) { + if (type == t_rr_type::CHANX) { coord_min = rr_graph.node_xlow(inode); coord_max = rr_graph.node_xhigh(inode); if (dir == Direction::INC) { @@ -172,7 +172,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { mux_dir = LEFT; } } else { - VTR_ASSERT(type == CHANY); + VTR_ASSERT(type == t_rr_type::CHANY); coord_min = rr_graph.node_ylow(inode); coord_max = rr_graph.node_yhigh(inode); if (dir == Direction::INC) { @@ -201,7 +201,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { ezgl::point2d arrow_loc_min(0, 0); ezgl::point2d arrow_loc_max(0, 0); - if (type == CHANX) { + if (type == t_rr_type::CHANX) { float sb_xmin = draw_coords->tile_x[k]; arrow_loc_min = {sb_xmin + arrow_offset, start.y}; @@ -287,8 +287,8 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { from_type = rr_graph.node_type(rr_node); if ((draw_state->draw_rr_toggle == DRAW_NODES_RR) - || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == OPIN || from_type == SOURCE || from_type == IPIN)) - || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_CBOX_RR && (from_type == SOURCE || from_type == IPIN))) { + || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == t_rr_type::OPIN || from_type == t_rr_type::SOURCE || from_type == t_rr_type::IPIN)) + || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_CBOX_RR && (from_type == t_rr_type::SOURCE || from_type == t_rr_type::IPIN))) { return; /* Nothing to draw. */ } @@ -301,10 +301,10 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { continue; // skip drawing if edge is not valid to draw switch (from_type) { - case OPIN: + case t_rr_type::OPIN: switch (to_type) { - case CHANX: - case CHANY: + case t_rr_type::CHANX: + case t_rr_type::CHANY: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { // If OPIN was clicked on, set color to fan-out ezgl::color color = draw_state->draw_rr_node[to_node].color; @@ -318,7 +318,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { } draw_pin_to_chan_edge(inode, to_node, g); break; - case IPIN: + case t_rr_type::IPIN: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -338,9 +338,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { } break; - case CHANX: /* from_type */ + case t_rr_type::CHANX: /* from_type */ switch (to_type) { - case IPIN: + case t_rr_type::IPIN: if (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR) { break; } @@ -365,7 +365,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { draw_pin_to_chan_edge(to_node, inode, g); break; - case CHANX: + case t_rr_type::CHANX: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -383,7 +383,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { switch_type, g); break; - case CHANY: + case t_rr_type::CHANY: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -408,9 +408,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { } break; - case CHANY: /* from_type */ + case t_rr_type::CHANY: /* from_type */ switch (to_type) { - case IPIN: + case t_rr_type::IPIN: if (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR) { break; } @@ -435,7 +435,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { draw_pin_to_chan_edge(to_node, inode, g); break; - case CHANX: + case t_rr_type::CHANX: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -453,7 +453,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { FROM_Y_TO_X, switch_type, g); break; - case CHANY: + case t_rr_type::CHANY: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -478,9 +478,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { break; } break; - case IPIN: // from_type + case t_rr_type::IPIN: // from_type switch (to_type) { - case SINK: + case t_rr_type::SINK: g->set_color(ezgl::DARK_SLATE_BLUE, transparency_factor); draw_pin_to_sink(inode, to_node, g); break; @@ -492,9 +492,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { break; } break; - case SOURCE: // from_type + case t_rr_type::SOURCE: // from_type switch (to_type) { - case OPIN: + case t_rr_type::OPIN: g->set_color(ezgl::PLUM, transparency_factor); draw_source_to_pin(inode, to_node, g); break; @@ -686,8 +686,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { continue; /* Don't check RR nodes on currently invisible layers*/ } switch (rr_graph.node_type(inode)) { - case IPIN: - case OPIN: { + case t_rr_type::IPIN: + case t_rr_type::OPIN: { int i = rr_graph.node_xlow(inode); int j = rr_graph.node_ylow(inode); t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({i, j, layer_num}); @@ -709,8 +709,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { } break; } - case SOURCE: - case SINK: { + case t_rr_type::SOURCE: + case t_rr_type::SINK: { float xcen, ycen; draw_get_rr_src_sink_coords(rr_graph.rr_nodes()[size_t(inode)], &xcen, &ycen); @@ -721,8 +721,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { } break; } - case CHANX: - case CHANY: { + case t_rr_type::CHANX: + case t_rr_type::CHANY: { bound_box = draw_get_rr_chan_bbox(inode); // Check if we clicked on this wire, with 30% @@ -815,22 +815,22 @@ void draw_rr_costs(ezgl::renderer* g, const vtr::vector& rr_cos color.alpha = transparency_factor; switch (rr_graph.node_type(inode)) { - case CHANX: //fallthrough - case CHANY: + case t_rr_type::CHANX: //fallthrough + case t_rr_type::CHANY: draw_rr_chan(inode, color, g); if (with_edges) draw_rr_edges(inode, g); break; - case IPIN: //fallthrough + case t_rr_type::IPIN: //fallthrough draw_rr_pin(inode, color, g); if (with_edges) draw_rr_edges(inode, g); break; - case OPIN: + case t_rr_type::OPIN: draw_rr_pin(inode, color, g); if (with_edges) draw_rr_edges(inode, g); break; - case SOURCE: - case SINK: + case t_rr_type::SOURCE: + case t_rr_type::SINK: color.alpha *= 0.8; draw_rr_src_sink(inode, color, g); if (with_edges) draw_rr_edges(inode, g); diff --git a/vpr/src/draw/draw_rr_edges.cpp b/vpr/src/draw/draw_rr_edges.cpp index 793487d04ab..b61be53b1db 100644 --- a/vpr/src/draw/draw_rr_edges.cpp +++ b/vpr/src/draw/draw_rr_edges.cpp @@ -281,10 +281,10 @@ void draw_chanx_to_chany_edge(RRNodeId chanx_node, RRNodeId chany_node, enum e_e void draw_pin_to_pin(RRNodeId opin_node, RRNodeId ipin_node, ezgl::renderer* g) { /* This routine draws an edge from the opin rr node to the ipin rr node */ - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - VTR_ASSERT(rr_graph.node_type(opin_node) == OPIN); - VTR_ASSERT(rr_graph.node_type(ipin_node) == IPIN); + VTR_ASSERT(rr_graph.node_type(opin_node) == e_rr_type::OPIN); + VTR_ASSERT(rr_graph.node_type(ipin_node) == e_rr_type::IPIN); /* FIXME: May use a smarter strategy * Currently, we use the last side found for both OPIN and IPIN @@ -439,13 +439,13 @@ void draw_pin_to_chan_edge(RRNodeId pin_node, RRNodeId chan_node, ezgl::renderer pin_side = pin_candidate_sides[0]; } else { VTR_ASSERT(1 < pin_candidate_sides.size()); - if (CHANX == channel_type && rr_graph.node_ylow(pin_node) <= rr_graph.node_ylow(chan_node)) { + if (e_rr_type::CHANX == channel_type && rr_graph.node_ylow(pin_node) <= rr_graph.node_ylow(chan_node)) { pin_side = TOP; - } else if (CHANX == channel_type && rr_graph.node_ylow(pin_node) - 1 >= rr_graph.node_ylow(chan_node)) { + } else if (e_rr_type::CHANX == channel_type && rr_graph.node_ylow(pin_node) - 1 >= rr_graph.node_ylow(chan_node)) { pin_side = BOTTOM; - } else if (CHANY == channel_type && rr_graph.node_xlow(pin_node) <= rr_graph.node_xlow(chan_node)) { + } else if (e_rr_type::CHANY == channel_type && rr_graph.node_xlow(pin_node) <= rr_graph.node_xlow(chan_node)) { pin_side = RIGHT; - } else if (CHANY == channel_type && rr_graph.node_xlow(pin_node) - 1 >= rr_graph.node_xlow(chan_node)) { + } else if (e_rr_type::CHANY == channel_type && rr_graph.node_xlow(pin_node) - 1 >= rr_graph.node_xlow(chan_node)) { pin_side = LEFT; } /* The inferred side must be in the list of sides of the pin rr_node!!! */ @@ -494,7 +494,7 @@ void draw_pin_to_chan_edge(RRNodeId pin_node, RRNodeId chan_node, ezgl::renderer float x2 = 0, y2 = 0; const Direction chan_rr_direction = rr_graph.node_direction(chan_node); switch (channel_type) { - case CHANX: { + case e_rr_type::CHANX: { y1 += draw_pin_offset; y2 = chan_bbox.bottom(); x2 = x1; @@ -507,7 +507,7 @@ void draw_pin_to_chan_edge(RRNodeId pin_node, RRNodeId chan_node, ezgl::renderer } break; } - case CHANY: { + case e_rr_type::CHANY: { x1 += draw_pin_offset; x2 = chan_bbox.left(); y2 = y1; diff --git a/vpr/src/draw/draw_searchbar.cpp b/vpr/src/draw/draw_searchbar.cpp index 270435fe04f..28f174a50dd 100644 --- a/vpr/src/draw/draw_searchbar.cpp +++ b/vpr/src/draw/draw_searchbar.cpp @@ -38,7 +38,7 @@ ezgl::rectangle draw_get_rr_chan_bbox(RRNodeId inode) { const auto& rr_graph = device_ctx.rr_graph; switch (rr_graph.node_type(inode)) { - case CHANX: + case e_rr_type::CHANX: left = draw_coords->tile_x[rr_graph.node_xlow(inode)]; right = draw_coords->tile_x[rr_graph.node_xhigh(inode)] + draw_coords->get_tile_width(); @@ -49,7 +49,7 @@ ezgl::rectangle draw_get_rr_chan_bbox(RRNodeId inode) { + draw_coords->get_tile_width() + (1. + rr_graph.node_track_num(inode)); break; - case CHANY: + case e_rr_type::CHANY: left = draw_coords->tile_x[rr_graph.node_xlow(inode)] + draw_coords->get_tile_width() + (1. + rr_graph.node_track_num(inode)); diff --git a/vpr/src/draw/search_bar.cpp b/vpr/src/draw/search_bar.cpp index 9a93be2274d..46261da44d5 100644 --- a/vpr/src/draw/search_bar.cpp +++ b/vpr/src/draw/search_bar.cpp @@ -231,8 +231,8 @@ void auto_zoom_rr_node(RRNodeId rr_node_id) { // find the location of the node switch (rr_graph.node_type(rr_node_id)) { - case IPIN: - case OPIN: { + case e_rr_type::IPIN: + case e_rr_type::OPIN: { t_physical_tile_loc tile_loc = { rr_graph.node_xlow(rr_node_id), rr_graph.node_ylow(rr_node_id), @@ -253,8 +253,8 @@ void auto_zoom_rr_node(RRNodeId rr_node_id) { } break; } - case CHANX: - case CHANY: { + case e_rr_type::CHANX: + case e_rr_type::CHANY: { rr_node = draw_get_rr_chan_bbox(rr_node_id); break; } diff --git a/vpr/src/pack/post_routing_pb_pin_fixup.cpp b/vpr/src/pack/post_routing_pb_pin_fixup.cpp index d217f07a83d..e66958e1d44 100644 --- a/vpr/src/pack/post_routing_pb_pin_fixup.cpp +++ b/vpr/src/pack/post_routing_pb_pin_fixup.cpp @@ -126,15 +126,15 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li t_rr_type rr_node_type; if (pin_type == DRIVER) { - rr_node_type = OPIN; + rr_node_type = e_rr_type::OPIN; } else { VTR_ASSERT(pin_type == RECEIVER); - rr_node_type = IPIN; + rr_node_type = e_rr_type::IPIN; } std::vector pinloc_sides = find_physical_tile_pin_side(physical_tile, physical_pin); /* As some grid has height/width offset, we may not have the pin on any side */ - if (0 == pinloc_sides.size()) { + if (pinloc_sides.empty()) { continue; } @@ -752,7 +752,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom t_pb_graph_pin* new_sink_pb_pin_to_add = sink_pb_pin_to_add; VTR_ASSERT(is_single_fanout_pb_pin(const_cast(new_sink_pb_pin_to_add))); int new_driver_pb_pin = pb_graph_pin->pin_count_in_cluster; - while (1) { + while (true) { int new_sink_pb_route_id = new_sink_pb_pin_to_add->pin_count_in_cluster; new_pb_routes.insert(std::make_pair(new_sink_pb_route_id, t_pb_route())); new_pb_routes[new_sink_pb_route_id].atom_net_id = remapped_net; diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 0e6be438300..cbde73d230a 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -100,7 +100,7 @@ static void get_intra_cluster_connections(const RouteTree& tree, std::vectorinode); - if ((type == IPIN || type == OPIN) && (parent_type == IPIN || parent_type == OPIN)) { + if ((type == t_rr_type::IPIN || type == t_rr_type::OPIN) && (parent_type == t_rr_type::IPIN || parent_type == t_rr_type::OPIN)) { auto clb = get_cluster_block_from_rr_node(node.inode); auto parent_clb = get_cluster_block_from_rr_node(parent->inode); if (clb == parent_clb) @@ -336,7 +336,7 @@ static void sync_clustered_netlist_to_routing(void) { int clb_nets_so_far = 0; for (auto& rt_node : tree->all_nodes()) { auto node_type = rr_graph.node_type(rt_node.inode); - if (node_type != IPIN && node_type != OPIN) + if (node_type != t_rr_type::IPIN && node_type != t_rr_type::OPIN) continue; auto physical_tile = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rt_node.inode), @@ -353,7 +353,7 @@ static void sync_clustered_netlist_to_routing(void) { /* OPIN on the tile: create a new clb_net_id and add all ports & pins into here * Due to how the route tree is traversed, all nodes until the next OPIN on the tile will * be under this OPIN, so this is valid (we don't need to get the branch explicitly) */ - if (node_type == OPIN) { + if (node_type == t_rr_type::OPIN) { std::string net_name; net_name = atom_ctx.netlist().net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); clb_net_id = clb_netlist.create_net(net_name); @@ -376,7 +376,7 @@ static void sync_clustered_netlist_to_routing(void) { VTR_ASSERT_MSG(false, "Unsupported port type"); port_id = clb_netlist.create_port(clb, pb_graph_pin->port->name, pb_graph_pin->port->num_pins, port_type); } - PinType pin_type = node_type == OPIN ? PinType::DRIVER : PinType::SINK; + PinType pin_type = node_type == t_rr_type::OPIN ? PinType::DRIVER : PinType::SINK; ClusterPinId new_pin = clb_netlist.create_pin(port_id, pb_graph_pin->pin_number, clb_net_id, pin_type, pb_graph_pin->pin_count_in_cluster); clb_netlist.set_pin_net(new_pin, pin_type, clb_net_id); diff --git a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp index bb1232d2778..f75ac77bc42 100644 --- a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp +++ b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp @@ -532,7 +532,7 @@ static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& /*rou auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); for (int driver_ptc : best_driver_ptcs) { VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, SOURCE, driver_ptc); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, t_rr_type::SOURCE, driver_ptc); VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); auto delays = calculate_all_path_delays_from_rr_node(source_rr_node, router_opts, is_flat); @@ -566,7 +566,7 @@ static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& /*rou auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); for (int sink_ptc : best_sink_ptcs) { VTR_ASSERT(sink_ptc != OPEN); - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, SINK, sink_ptc); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, e_rr_type::SINK, sink_ptc); if (sink_rr_node == RRNodeId::INVALID()) continue; @@ -651,13 +651,13 @@ static float route_connection_delay(RouterDelayProfiler& route_profiler, for (int driver_ptc : best_driver_ptcs) { VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(source_layer, source_x, source_y, SOURCE, driver_ptc); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(source_layer, source_x, source_y, t_rr_type::SOURCE, driver_ptc); VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); for (int sink_ptc : best_sink_ptcs) { VTR_ASSERT(sink_ptc != OPEN); - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(sink_layer, sink_x, sink_y, SINK, sink_ptc); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(sink_layer, sink_x, sink_y, e_rr_type::SINK, sink_ptc); if (sink_rr_node == RRNodeId::INVALID()) continue; @@ -846,10 +846,10 @@ bool find_direct_connect_sample_locations(const t_direct_inf* direct, //(with multi-width/height blocks pins may not exist at all locations) bool from_pin_found = false; if (direct->from_side != NUM_2D_SIDES) { - RRNodeId from_pin_rr = node_lookup.find_node(layer_num, x, y, OPIN, from_pin, direct->from_side); + RRNodeId from_pin_rr = node_lookup.find_node(layer_num, x, y, e_rr_type::OPIN, from_pin, direct->from_side); from_pin_found = from_pin_rr.is_valid(); } else { - from_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, x, y, OPIN, from_pin).empty()); + from_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, x, y, e_rr_type::OPIN, from_pin).empty()); } if (!from_pin_found) continue; @@ -862,10 +862,10 @@ bool find_direct_connect_sample_locations(const t_direct_inf* direct, //(with multi-width/height blocks pins may not exist at all locations) bool to_pin_found = false; if (direct->to_side != NUM_2D_SIDES) { - RRNodeId to_pin_rr = node_lookup.find_node(layer_num, to_x, to_y, IPIN, to_pin, direct->to_side); + RRNodeId to_pin_rr = node_lookup.find_node(layer_num, to_x, to_y, e_rr_type::IPIN, to_pin, direct->to_side); to_pin_found = (to_pin_rr != RRNodeId::INVALID()); } else { - to_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, to_x, to_y, IPIN, to_pin).empty()); + to_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, to_x, to_y, e_rr_type::IPIN, to_pin).empty()); } if (!to_pin_found) continue; @@ -903,13 +903,13 @@ bool find_direct_connect_sample_locations(const t_direct_inf* direct, // Find a source/sink RR node associated with the pins of the direct { - RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, SOURCE, from_pin_class); + RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, t_rr_type::SOURCE, from_pin_class); VTR_ASSERT(src_rr_candidate); out_src_node = src_rr_candidate; } { - RRNodeId sink_rr_candidate = node_lookup.find_node(found_layer_num, to_x, to_y, SINK, to_pin_class); + RRNodeId sink_rr_candidate = node_lookup.find_node(found_layer_num, to_x, to_y, e_rr_type::SINK, to_pin_class); VTR_ASSERT(sink_rr_candidate); out_sink_node = sink_rr_candidate; } diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index 4a8ccb62666..a52865bf918 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -211,7 +211,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // Note that the restriction that constant nets are not driven from another direct ensures that // blocks in the middle of a chain with internal constant signals are not detected as potential // head blocks. - if (to_src_or_sink == SINK && to_idirect != OPEN + if (to_src_or_sink == (int)e_rr_type::SINK && to_idirect != OPEN && (to_net_id == ClusterNetId::INVALID() || (is_constant_clb_net(to_net_id, atom_lookup, atom_nlist) && !net_is_driven_by_direct_(to_net_id, clb_nlist)))) { for (int from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin); @@ -224,7 +224,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // // The output SOURCE (from_pin) of a true head macro will: // * drive another block with the same direct connection - if (from_src_or_sink == SOURCE && to_idirect == from_idirect && from_net_id != ClusterNetId::INVALID()) { + if (from_src_or_sink == (int)e_rr_type::SOURCE && to_idirect == from_idirect && from_net_id != ClusterNetId::INVALID()) { // Mark down that this is the first block in the macro pl_macro_member_blk_num_of_this_blk[0] = blk_id; pl_macro_idirect[num_macro] = to_idirect; @@ -249,7 +249,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // Assume that the from_iblk_pin index is the same for the next block VTR_ASSERT(idirect_from_blk_pin_[physical_tile->index][from_physical_pin] == from_idirect - && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == SOURCE); + && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == (int)e_rr_type::SOURCE); next_net_id = clb_nlist.block_net(next_blk_id, from_iblk_pin); // Mark down this block as a member of the macro @@ -448,7 +448,7 @@ void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vectornet_num == node_power->net_num) { next_node_power->selected_input = next_node_power->num_inputs; } @@ -875,12 +875,12 @@ static void power_usage_routing(t_power_usage* power_usage, const t_edge_size node_fan_in = rr_graph.node_fan_in(rr_id); switch (rr_graph.node_type(rr_id)) { - case SOURCE: - case SINK: - case OPIN: + case e_rr_type::SOURCE: + case e_rr_type::SINK: + case e_rr_type::OPIN: /* No power usage for these types */ break; - case IPIN: + case e_rr_type::IPIN: /* This is part of the connectionbox. The connection box is comprised of: * - Driver (accounted for at end of CHANX/Y - see below) * - Multiplexor */ @@ -901,8 +901,8 @@ static void power_usage_routing(t_power_usage* power_usage, POWER_COMPONENT_ROUTE_CB); } break; - case CHANX: - case CHANY: { + case e_rr_type::CHANX: + case e_rr_type::CHANY: { /* This is a wire driven by a switchbox, which includes: * - The Multiplexor at the beginning of the wire * - A buffer, after the mux to drive the wire @@ -912,9 +912,9 @@ static void power_usage_routing(t_power_usage* power_usage, VTR_ASSERT(node_power->in_prob); wire_length = 0; - if (rr_graph.node_type(rr_id) == CHANX) { + if (rr_graph.node_type(rr_id) == e_rr_type::CHANX) { wire_length = rr_graph.node_xhigh(rr_id) - rr_graph.node_xlow(rr_id) + 1; - } else if (rr_graph.node_type(rr_id) == CHANY) { + } else if (rr_graph.node_type(rr_id) == e_rr_type::CHANY) { wire_length = rr_graph.node_yhigh(rr_id) - rr_graph.node_ylow(rr_id) + 1; } int seg_index = device_ctx.rr_indexed_data[rr_graph.node_cost_index(rr_id)].seg_index; @@ -1219,7 +1219,7 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { const t_edge_size node_fan_in = rr_graph.node_fan_in(rr_node_idx); switch (rr_graph.node_type(rr_node_idx)) { - case IPIN: + case e_rr_type::IPIN: max_IPIN_fanin = std::max(max_IPIN_fanin, node_fan_in); max_fanin = std::max(max_fanin, node_fan_in); @@ -1231,8 +1231,8 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { } break; - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_node_idx); iedge++) { if (rr_graph.edge_switch(rr_node_idx, iedge) == routing_arch->wire_to_rr_ipin_switch) { fanout_to_IPIN++; @@ -1284,8 +1284,8 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) { switch (rr_graph.node_type(rr_node_idx)) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: if (rr_graph.num_edges(rr_node_idx) > max_seg_fanout) { max_seg_fanout = rr_graph.num_edges(rr_node_idx); } @@ -1372,9 +1372,9 @@ bool power_uninit() { t_rr_node_power* node_power = &rr_node_power[(size_t)rr_id]; switch (rr_graph.node_type(rr_id)) { - case CHANX: - case CHANY: - case IPIN: + case e_rr_type::CHANX: + case e_rr_type::CHANY: + case e_rr_type::IPIN: delete[] node_power->in_dens; delete[] node_power->in_prob; break; diff --git a/vpr/src/route/annotate_routing.cpp b/vpr/src/route/annotate_routing.cpp index 6f20d2e873d..6a11000e0da 100644 --- a/vpr/src/route/annotate_routing.cpp +++ b/vpr/src/route/annotate_routing.cpp @@ -41,8 +41,8 @@ vtr::vector annotate_rr_node_nets(const ClusteringContex for (auto& rt_node : tree->all_nodes()) { const RRNodeId rr_node = rt_node.inode; /* Ignore source and sink nodes, they are the common node multiple starting and ending points */ - if ((SOURCE != rr_graph.node_type(rr_node)) - && (SINK != rr_graph.node_type(rr_node))) { + if ((t_rr_type::SOURCE != rr_graph.node_type(rr_node)) + && (t_rr_type::SINK != rr_graph.node_type(rr_node))) { /* Sanity check: ensure we do not revoke any net mapping * In some routing architectures, node capacity is more than 1 * which allows a node to be mapped by multiple nets diff --git a/vpr/src/route/build_switchblocks.cpp b/vpr/src/route/build_switchblocks.cpp index a0dbe35bb1c..487f3f6d640 100644 --- a/vpr/src/route/build_switchblocks.cpp +++ b/vpr/src/route/build_switchblocks.cpp @@ -680,7 +680,7 @@ static void get_switchpoint_wires( std::vector& collected_wire_switchpoints = *scratch_wires; int seg_coord = x; - if (chan_type == CHANY) { + if (chan_type == e_rr_type::CHANY) { seg_coord = y; } @@ -807,10 +807,10 @@ static void compute_wire_connections(int x_coord, const t_wire_type_sizes* wire_type_sizes_from = wire_type_sizes_x; const t_wire_type_sizes* wire_type_sizes_to = wire_type_sizes_x; - if (from_chan_type == CHANY) { + if (from_chan_type == e_rr_type::CHANY) { wire_type_sizes_from = wire_type_sizes_y; } - if (to_chan_type == CHANY) { + if (to_chan_type == e_rr_type::CHANY) { wire_type_sizes_to = wire_type_sizes_y; } @@ -1025,7 +1025,7 @@ static int evaluate_num_conns_formula(t_wireconn_scratchpad* scratchpad, std::st } static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int tile_layer, enum e_side src_side, enum e_side dest_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, int& chan_x, int& chan_y, int& chan_layer, t_rr_type& chan_type) { - chan_type = CHANX; + chan_type = e_rr_type::CHANX; /* here we use the VPR convention that a tile 'owns' the channels directly to the right * and above it */ switch (src_side) { @@ -1034,7 +1034,7 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int chan_x = tile_x; chan_y = tile_y + 1; chan_layer = tile_layer; - chan_type = CHANY; + chan_type = e_rr_type::CHANY; return chan_details_y; break; case RIGHT: @@ -1042,14 +1042,14 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int chan_x = tile_x + 1; chan_y = tile_y; chan_layer = tile_layer; - chan_type = CHANX; + chan_type = e_rr_type::CHANX; return chan_details_x; break; case BOTTOM: /* this is y-channel on the right of the tile in the same layer */ chan_x = tile_x; chan_y = tile_y; - chan_type = CHANY; + chan_type = e_rr_type::CHANY; chan_layer = tile_layer; return chan_details_y; break; @@ -1057,7 +1057,7 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int /* this is x-channel on top of the tile in the same layer*/ chan_x = tile_x; chan_y = tile_y; - chan_type = CHANX; + chan_type = e_rr_type::CHANX; chan_layer = tile_layer; return chan_details_x; break; @@ -1066,7 +1066,7 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int chan_x = tile_x; chan_y = tile_y; chan_layer = tile_layer + 1; - chan_type = (dest_side == RIGHT || dest_side == LEFT) ? CHANX : CHANY; + chan_type = (dest_side == RIGHT || dest_side == LEFT) ? e_rr_type::CHANX : e_rr_type::CHANY; return (dest_side == RIGHT || dest_side == LEFT) ? chan_details_x : chan_details_y; break; case UNDER: @@ -1074,7 +1074,7 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int chan_x = tile_x; chan_y = tile_y; chan_layer = tile_layer - 1; - chan_type = (dest_side == RIGHT || dest_side == LEFT) ? CHANX : CHANY; + chan_type = (dest_side == RIGHT || dest_side == LEFT) ? e_rr_type::CHANX : e_rr_type::CHANY; return (dest_side == RIGHT || dest_side == LEFT) ? chan_details_x : chan_details_y; break; default: @@ -1093,14 +1093,14 @@ static bool coords_out_of_bounds(const DeviceGrid& grid, int x_coord, int y_coor return result; } - if (CHANX == chan_type) { + if (e_rr_type::CHANX == chan_type) { /* there is no x-channel at x=0 */ if (x_coord <= 0 || x_coord >= int(grid.width()) - 1 || y_coord < 0 || y_coord >= int(grid.height()) - 1) { result = true; } else { result = false; } - } else if (CHANY == chan_type) { + } else if (e_rr_type::CHANY == chan_type) { /* there is no y-channel at y=0 */ if (x_coord < 0 || x_coord >= int(grid.width()) - 1 || y_coord <= 0 || y_coord >= int(grid.height()) - 1) { result = true; @@ -1161,7 +1161,7 @@ int get_wire_segment_length(const DeviceGrid& grid, e_rr_type chan_type, const t int min_seg = 1; int max_seg = grid.width() - 2; //-2 for no perim channels - if (chan_type == CHANY) { + if (chan_type == e_rr_type::CHANY) { max_seg = grid.height() - 2; //-2 for no perim channels } @@ -1194,7 +1194,7 @@ static int get_switchpoint_of_wire(const DeviceGrid& grid, e_rr_type chan_type, /* get the minimum and maximum segment coordinate which a wire in this channel type can take */ int min_seg = 1; int max_seg = grid.width() - 2; //-2 for no perim channels - if (chan_type == CHANY) { + if (chan_type == e_rr_type::CHANY) { max_seg = grid.height() - 2; //-2 for no perim channels } diff --git a/vpr/src/route/channel_stats.cpp b/vpr/src/route/channel_stats.cpp index f95275db9f4..e0f1483d456 100644 --- a/vpr/src/route/channel_stats.cpp +++ b/vpr/src/route/channel_stats.cpp @@ -4,9 +4,9 @@ #include "globals.h" void print_channel_stats(bool is_flat) { - std::vector histogram; + const auto& device_ctx = g_vpr_ctx.device(); - auto& device_ctx = g_vpr_ctx.device(); + std::vector histogram; //Bins by 10%, with final > 1 bin histogram.emplace_back(0., 0.1); @@ -20,11 +20,11 @@ void print_channel_stats(bool is_flat) { histogram.emplace_back(0.9, 1.0); histogram.emplace_back(1.0, std::numeric_limits::infinity()); - auto chanx_usage = calculate_routing_usage(CHANX, is_flat, true); - auto chany_usage = calculate_routing_usage(CHANY, is_flat, true); + auto chanx_usage = calculate_routing_usage(e_rr_type::CHANX, is_flat, true); + auto chany_usage = calculate_routing_usage(e_rr_type::CHANY, is_flat, true); - auto chanx_avail = calculate_routing_avail(CHANX); - auto chany_avail = calculate_routing_avail(CHANY); + auto chanx_avail = calculate_routing_avail(e_rr_type::CHANX); + auto chany_avail = calculate_routing_avail(e_rr_type::CHANY); auto comp = [](const HistogramBucket& bucket, float value) { return bucket.max_value < value; diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index 096a87c787d..4cd58651181 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -100,7 +100,7 @@ void check_route(const Netlist<>& net_list, recompute_occupancy_from_scratch(net_list, is_flat); const bool valid = feasible_routing(); - if (valid == false) { + if (!valid) { VPR_ERROR(VPR_ERROR_ROUTE, "Error in check_route -- routing resources are overused.\n"); } @@ -157,7 +157,7 @@ void check_route(const Netlist<>& net_list, } } - if (rr_graph.node_type(inode) == SINK) { + if (rr_graph.node_type(inode) == t_rr_type::SINK) { check_sink(net_list, inode, net_pin_index, net_id, pin_done.get()); num_sinks += 1; } @@ -171,7 +171,7 @@ void check_route(const Netlist<>& net_list, } for (size_t ipin = 0; ipin < net_list.net_pins(net_id).size(); ipin++) { - if (pin_done[ipin] == false) { + if (!pin_done[ipin]) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_route: net %zu does not connect to pin %d.\n", size_t(net_id), ipin); } @@ -200,7 +200,7 @@ static void check_sink(const Netlist<>& net_list, auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - VTR_ASSERT(rr_graph.node_type(inode) == SINK); + VTR_ASSERT(rr_graph.node_type(inode) == t_rr_type::SINK); if (net_pin_index == OPEN) { /* If there is no legal net pin index associated with this sink node */ VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -223,7 +223,7 @@ static void check_source(const Netlist<>& net_list, const auto& rr_graph = device_ctx.rr_graph; t_rr_type rr_type = rr_graph.node_type(inode); - if (rr_type != SOURCE) { + if (rr_type != t_rr_type::SOURCE) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_source: net %d begins with a node of type %d.\n", size_t(net_id), rr_type); } @@ -319,7 +319,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { // If to_node is a SINK, it could be anywhere within its containing device grid tile, and it is reasonable for // any input pins or within-cluster pins to reach it. Hence, treat its size as that of its containing tile. - if (to_type == SINK) { + if (to_type == t_rr_type::SINK) { vtr::Rect tile_bb = device_ctx.grid.get_tile_bb({to_xlow, to_ylow, to_layer}); to_xlow = tile_bb.xmin(); @@ -331,8 +331,8 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { // Layer numbers are should not be more than one layer apart for connected nodes VTR_ASSERT(abs(from_layer - to_layer) <= 1); switch (from_type) { - case SOURCE: - VTR_ASSERT(to_type == OPIN); + case t_rr_type::SOURCE: + VTR_ASSERT(to_type == t_rr_type::OPIN); //The OPIN should be contained within the bounding box of it's connected source if (from_xlow <= to_xlow @@ -349,34 +349,34 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case SINK: + case t_rr_type::SINK: /* SINKS are adjacent to not connected */ break; - case OPIN: + case t_rr_type::OPIN: from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); - if (to_type == CHANX || to_type == CHANY) { + if (to_type == t_rr_type::CHANX || to_type == t_rr_type::CHANY) { num_adj += 1; //adjacent } else if (is_flat) { - VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster + VTR_ASSERT(to_type == t_rr_type::OPIN || to_type == t_rr_type::IPIN); // If pin is located inside a cluster return true; } else { - VTR_ASSERT(to_type == IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */ - return true; /* Special case, direct OPIN to IPIN connections need not be adjacent */ + VTR_ASSERT(to_type == t_rr_type::IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */ + return true; /* Special case, direct OPIN to IPIN connections need not be adjacent */ } break; - case IPIN: + case t_rr_type::IPIN: from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); if (is_flat) { - VTR_ASSERT(to_type == OPIN || to_type == IPIN || to_type == SINK); + VTR_ASSERT(to_type == t_rr_type::OPIN || to_type == t_rr_type::IPIN || to_type == t_rr_type::SINK); } else { - VTR_ASSERT(to_type == SINK); + VTR_ASSERT(to_type == t_rr_type::SINK); } //An IPIN should be contained within the bounding box of its connected sink's tile - if (to_type == SINK) { + if (to_type == t_rr_type::SINK) { if (from_xlow >= to_xlow && from_ylow >= to_ylow && from_xhigh <= to_xhigh @@ -403,10 +403,10 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case CHANX: - if (to_type == IPIN) { + case t_rr_type::CHANX: + if (to_type == e_rr_type::IPIN) { num_adj += 1; //adjacent - } else if (to_type == CHANX) { + } else if (to_type == t_rr_type::CHANX) { from_xhigh = rr_graph.node_xhigh(from_node); to_xhigh = rr_graph.node_xhigh(to_node); if (from_ylow == to_ylow) { @@ -428,7 +428,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } /* UDSD Modification by WMF End */ } - } else if (to_type == CHANY) { + } else if (to_type == t_rr_type::CHANY) { num_adj += chanx_chany_adjacent(from_node, to_node); } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -436,10 +436,10 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case CHANY: - if (to_type == IPIN) { + case t_rr_type::CHANY: + if (to_type == e_rr_type::IPIN) { num_adj += 1; //adjacent - } else if (to_type == CHANY) { + } else if (to_type == t_rr_type::CHANY) { from_yhigh = rr_graph.node_yhigh(from_node); to_yhigh = rr_graph.node_yhigh(to_node); if (from_xlow == to_xlow) { @@ -460,7 +460,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } /* UDSD Modification by WMF End */ } - } else if (to_type == CHANX) { + } else if (to_type == t_rr_type::CHANX) { num_adj += chanx_chany_adjacent(to_node, from_node); } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -571,7 +571,7 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_ /* Now check that node is an OPIN of the right type. */ rr_type = rr_graph.node_type(RRNodeId(inode)); - if (rr_type != OPIN) { + if (rr_type != t_rr_type::OPIN) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_locally_used_opins: block #%lu (%s)\n" "\tClass %d local OPIN is wrong rr_type -- rr_node #%d of type %d.\n", @@ -883,7 +883,7 @@ bool StubFinder::RecurseTree(const RouteTreeNode& rt_node) { if (rt_node.is_leaf()) { //If a leaf of the route tree is not a SINK, then it is a stub - if (rr_graph.node_type(rt_node.inode) != SINK) { + if (rr_graph.node_type(rt_node.inode) != t_rr_type::SINK) { return true; //It is the current root of this stub } else { return false; diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp index 5a193a159ad..5a2455bdaa1 100644 --- a/vpr/src/route/clock_connection_builders.cpp +++ b/vpr/src/route/clock_connection_builders.cpp @@ -5,18 +5,19 @@ #include "rr_rc_data.h" #include -#include +#include +#include /* * RoutingToClockConnection (setters) */ void RoutingToClockConnection::set_clock_name_to_connect_to(std::string clock_name) { - clock_to_connect_to = clock_name; + clock_to_connect_to = std::move(clock_name); } void RoutingToClockConnection::set_clock_switch_point_name(std::string clock_switch_point_name) { - switch_point_name = clock_switch_point_name; + switch_point_name = std::move(clock_switch_point_name); } void RoutingToClockConnection::set_switch_location(int x, int y, int layer /* =0 */) { @@ -57,8 +58,8 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_ rr_graph_builder.set_virtual_clock_network_root_idx(virtual_clock_network_root_idx); // rr_node indices for x and y channel routing wires and clock wires to connect to - auto x_wire_indices = node_lookup.find_channel_nodes(switch_location.layer, switch_location.x, switch_location.y, CHANX); - auto y_wire_indices = node_lookup.find_channel_nodes(switch_location.layer, switch_location.x, switch_location.y, CHANY); + auto x_wire_indices = node_lookup.find_channel_nodes(switch_location.layer, switch_location.x, switch_location.y, e_rr_type::CHANX); + auto y_wire_indices = node_lookup.find_channel_nodes(switch_location.layer, switch_location.x, switch_location.y, e_rr_type::CHANY); auto clock_indices = clock_graph.get_rr_node_indices_at_switch_location( clock_to_connect_to, switch_point_name, switch_location.x, switch_location.y); @@ -96,7 +97,7 @@ RRNodeId RoutingToClockConnection::create_virtual_clock_network_sink_node(int la RRNodeId node_index = RRNodeId(rr_graph.num_nodes() - 1); //Determine a valid PTC - std::vector nodes_at_loc = node_lookup.find_grid_nodes_at_all_sides(layer, x, y, SINK); + std::vector nodes_at_loc = node_lookup.find_grid_nodes_at_all_sides(layer, x, y, e_rr_type::SINK); int max_ptc = 0; for (RRNodeId inode : nodes_at_loc) { @@ -104,7 +105,7 @@ RRNodeId RoutingToClockConnection::create_virtual_clock_network_sink_node(int la } int ptc = max_ptc + 1; - rr_graph_builder.set_node_type(node_index, SINK); + rr_graph_builder.set_node_type(node_index, e_rr_type::SINK); rr_graph_builder.set_node_name(node_index, arch->default_clock_network_name); rr_graph_builder.set_node_class_num(node_index, ptc); rr_graph_builder.set_node_coordinates(node_index, x, y, x, y); @@ -309,7 +310,7 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra auto clock_pin_node_idx = node_lookup.find_node(layer_num, x, y, - IPIN, + e_rr_type::IPIN, clock_pin_idx, side); diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/clock_network_builders.cpp index 34dccc4ff29..9347cf28cd4 100644 --- a/vpr/src/route/clock_network_builders.cpp +++ b/vpr/src/route/clock_network_builders.cpp @@ -340,7 +340,7 @@ int ClockRib::create_chanx_wire(int layer, auto node_index = rr_nodes->size() - 1; RRNodeId chanx_node = RRNodeId(node_index); - rr_graph_builder.set_node_type(chanx_node, CHANX); + rr_graph_builder.set_node_type(chanx_node, e_rr_type::CHANX); rr_graph_builder.set_node_coordinates(chanx_node, x_start, y, x_end, y); rr_graph_builder.set_node_layer(chanx_node, layer); rr_graph_builder.set_node_capacity(chanx_node, 1); @@ -682,7 +682,7 @@ int ClockSpine::create_chany_wire(int layer, auto node_index = rr_nodes->size() - 1; RRNodeId chany_node = RRNodeId(node_index); - rr_graph_builder.set_node_type(chany_node, CHANY); + rr_graph_builder.set_node_type(chany_node, e_rr_type::CHANY); rr_graph_builder.set_node_coordinates(chany_node, x, y_start, x, y_end); rr_graph_builder.set_node_layer(chany_node, layer); rr_graph_builder.set_node_capacity(chany_node, 1); diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp index ee80073c3c6..76ec6e85a54 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/connection_router.cpp @@ -196,7 +196,7 @@ void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId s VTR_ASSERT_SAFE(sink_node != RRNodeId::INVALID()); t_bb target_bb; - if (rr_graph_->node_type(sink_node) == SINK) { // We need to get a bounding box for the sink's entire tile + if (rr_graph_->node_type(sink_node) == t_rr_type::SINK) { // We need to get a bounding box for the sink's entire tile vtr::Rect tile_bb = grid_.get_tile_bb({rr_graph_->node_xlow(sink_node), rr_graph_->node_ylow(sink_node), rr_graph_->node_layer(sink_node)}); @@ -477,7 +477,7 @@ void ConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode * Change this if you want to investigate route-throughs. */ if (target_node != RRNodeId::INVALID()) { t_rr_type to_type = rr_graph_->node_type(to_node); - if (to_type == IPIN) { + if (to_type == t_rr_type::IPIN) { // Check if this IPIN leads to the target block // IPIN's of the target block should be contained within it's bounding box int to_xlow = rr_graph_->node_xlow(to_node); @@ -758,7 +758,7 @@ void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* t //cost. cong_cost = 0.; } - if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == IPIN) { + if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == t_rr_type::IPIN) { auto find_res = conn_params_->connection_choking_spots_.find(to->index); if (find_res != conn_params_->connection_choking_spots_.end()) { cong_cost = cong_cost / pow(2, (float)find_res->second); @@ -772,7 +772,7 @@ void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* t if (cost_params.bend_cost != 0.) { t_rr_type from_type = rr_graph_->node_type(from_node); t_rr_type to_type = rr_graph_->node_type(to->index); - if ((from_type == CHANX && to_type == CHANY) || (from_type == CHANY && to_type == CHANX)) { + if ((from_type == t_rr_type::CHANX && to_type == t_rr_type::CHANY) || (from_type == t_rr_type::CHANY && to_type == t_rr_type::CHANX)) { to->backward_path_cost += cost_params.bend_cost; //Bend cost } } @@ -911,7 +911,7 @@ void ConnectionRouter::add_route_tree_node_to_heap( rr_graph_); if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - router_stats_->rt_node_pushes[rr_graph_->node_type(inode)]++; + router_stats_->rt_node_pushes[(size_t)rr_graph_->node_type(inode)]++; } } @@ -1012,7 +1012,7 @@ t_bb ConnectionRouter::add_high_fanout_route_tree_to_heap( // Expand HF BB to include the node (clip by original BB) expand_highfanout_bounding_box(highfanout_bb, net_bounding_box, rr_node_to_add, rr_graph_); - if (rr_graph_->node_type(rr_node_to_add) == CHANY || rr_graph_->node_type(rr_node_to_add) == CHANX) { + if (rr_graph_->node_type(rr_node_to_add) == t_rr_type::CHANY || rr_graph_->node_type(rr_node_to_add) == t_rr_type::CHANX) { chan_nodes_added++; } } @@ -1047,7 +1047,7 @@ static inline bool relevant_node_to_target(const RRGraphView* rr_graph, RRNodeId target_node) { VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == t_rr_type::SINK); auto node_to_add_type = rr_graph->node_type(node_to_add); - return node_to_add_type != t_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); + return node_to_add_type != e_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); } static inline void update_router_stats(RouterStats* router_stats, @@ -1062,23 +1062,23 @@ static inline void update_router_stats(RouterStats* router_stats, if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { auto node_type = rr_graph->node_type(rr_node_id); - VTR_ASSERT(node_type != NUM_RR_TYPES); + VTR_ASSERT(node_type != t_rr_type::NUM_RR_TYPES); if (is_inter_cluster_node(*rr_graph, rr_node_id)) { if (is_push) { router_stats->inter_cluster_node_pushes++; - router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; + router_stats->inter_cluster_node_type_cnt_pushes[(size_t)node_type]++; } else { router_stats->inter_cluster_node_pops++; - router_stats->inter_cluster_node_type_cnt_pops[node_type]++; + router_stats->inter_cluster_node_type_cnt_pops[(size_t)node_type]++; } } else { if (is_push) { router_stats->intra_cluster_node_pushes++; - router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; + router_stats->intra_cluster_node_type_cnt_pushes[(size_t)node_type]++; } else { router_stats->intra_cluster_node_pops++; - router_stats->intra_cluster_node_type_cnt_pops[node_type]++; + router_stats->intra_cluster_node_type_cnt_pops[(size_t)node_type]++; } } } diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 92c421eccbd..86773a32445 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -130,8 +130,8 @@ void report_overused_nodes(const Netlist<>& net_list, int y = rr_graph.node_ylow(node_id); int layer_num = rr_graph.node_layer(node_id); switch (node_type) { - case IPIN: - case OPIN: + case t_rr_type::IPIN: + case e_rr_type::OPIN: report_overused_ipin_opin(os, node_id, rr_node_to_net_map); @@ -139,12 +139,12 @@ void report_overused_nodes(const Netlist<>& net_list, x -= g_vpr_ctx.device().grid.get_physical_type({x, y, layer_num})->width; y -= g_vpr_ctx.device().grid.get_physical_type({x, y, layer_num})->width; break; - case CHANX: - case CHANY: + case t_rr_type::CHANX: + case t_rr_type::CHANY: report_overused_chanx_chany(os, node_id); break; - case SOURCE: - case SINK: + case t_rr_type::SOURCE: + case t_rr_type::SINK: report_overused_source_sink(os, node_id); report_sinks = true; break; diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index 2c077f0c8a8..0712bb1f738 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -618,7 +618,7 @@ bool route(const Netlist<>& net_list, "total_internal_heap_pushes: %zu total_internal_heap_pops: %zu total_external_heap_pushes: %zu total_external_heap_pops: %zu ", router_stats.intra_cluster_node_pushes, router_stats.intra_cluster_node_pops, router_stats.inter_cluster_node_pushes, router_stats.inter_cluster_node_pops); - for (int node_type_idx = 0; node_type_idx < t_rr_type::NUM_RR_TYPES; node_type_idx++) { + for (int node_type_idx = 0; node_type_idx < (int)t_rr_type::NUM_RR_TYPES; node_type_idx++) { VTR_LOG("total_external_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.inter_cluster_node_type_cnt_pushes[node_type_idx]); VTR_LOG("total_external_%s_pops: %zu ", rr_node_typename[node_type_idx], router_stats.inter_cluster_node_type_cnt_pops[node_type_idx]); VTR_LOG("total_internal_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.intra_cluster_node_type_cnt_pushes[node_type_idx]); diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 3b720c5d76f..038b6aee6f2 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -98,13 +98,11 @@ void restore_routing(vtr::vector>& best_ro * Use this number as a routing serial number to ensure that programming * * changes do not break the router. */ void get_serial_num(const Netlist<>& net_list) { - int serial_num; - - auto& route_ctx = g_vpr_ctx.routing(); - auto& device_ctx = g_vpr_ctx.device(); + const auto& route_ctx = g_vpr_ctx.routing(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - serial_num = 0; + int serial_num = 0; for (auto net_id : net_list.nets()) { if (!route_ctx.route_trees[net_id]) @@ -117,7 +115,7 @@ void get_serial_num(const Netlist<>& net_list) { serial_num -= rr_graph.node_ptc_num(inode) * (size_t(net_id) + 1) * 10; - serial_num -= rr_graph.node_type(inode) * (size_t(net_id) + 1) * 100; + serial_num -= (size_t)rr_graph.node_type(inode) * (size_t(net_id) + 1) * 100; serial_num %= 2000000000; /* Prevent overflow */ } } @@ -465,7 +463,7 @@ static vtr::vector> load_net_rr_terminals(con inode = rr_graph.node_lookup().find_node(blk_loc.loc.layer, blk_loc.loc.x, blk_loc.loc.y, - SOURCE, + e_rr_type::SOURCE, iclass); } else { vtr::Rect tile_bb = grid.get_tile_bb({blk_loc.loc.x, @@ -476,7 +474,7 @@ static vtr::vector> load_net_rr_terminals(con tile_bb.ymin(), tile_bb.xmax(), tile_bb.ymax(), - SINK, + t_rr_type::SINK, iclass); VTR_ASSERT_SAFE(sink_nodes.size() == 1); inode = sink_nodes[0]; @@ -583,10 +581,10 @@ static vtr::vector> load_rr_clb_sources(con blk_loc = get_block_loc(blk_id, is_flat); auto class_type = get_class_type_from_class_physical_num(type, iclass); if (class_type == DRIVER) { - rr_type = SOURCE; + rr_type = e_rr_type::SOURCE; } else { VTR_ASSERT(class_type == RECEIVER); - rr_type = SINK; + rr_type = e_rr_type::SINK; } RRNodeId inode = rr_graph.node_lookup().find_node(blk_loc.loc.layer, @@ -706,7 +704,7 @@ t_bb load_net_route_bb(const Netlist<>& net_list, bb_factor = std::min(bb_factor, max_dim); RRNodeId driver_rr = RRNodeId(route_ctx.net_rr_terminals[net_id][0]); - VTR_ASSERT(rr_graph.node_type(driver_rr) == SOURCE); + VTR_ASSERT(rr_graph.node_type(driver_rr) == e_rr_type::SOURCE); VTR_ASSERT(rr_graph.node_xlow(driver_rr) <= rr_graph.node_xhigh(driver_rr)); VTR_ASSERT(rr_graph.node_ylow(driver_rr) <= rr_graph.node_yhigh(driver_rr)); @@ -721,7 +719,7 @@ t_bb load_net_route_bb(const Netlist<>& net_list, auto net_sinks = net_list.net_sinks(net_id); for (size_t ipin = 1; ipin < net_sinks.size() + 1; ++ipin) { //Start at 1 since looping through sinks RRNodeId sink_rr = RRNodeId(route_ctx.net_rr_terminals[net_id][ipin]); - VTR_ASSERT(rr_graph.node_type(sink_rr) == SINK); + VTR_ASSERT(rr_graph.node_type(sink_rr) == e_rr_type::SINK); VTR_ASSERT(rr_graph.node_xlow(sink_rr) <= rr_graph.node_xhigh(sink_rr)); VTR_ASSERT(rr_graph.node_ylow(sink_rr) <= rr_graph.node_yhigh(sink_rr)); @@ -842,7 +840,7 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f for (iconn = 0; iconn < num_edges; iconn++) { RRNodeId to_node = rr_graph.edge_sink_node(RRNodeId(from_node), iconn); - VTR_ASSERT(rr_graph.node_type(RRNodeId(to_node)) == OPIN); + VTR_ASSERT(rr_graph.node_type(RRNodeId(to_node)) == e_rr_type::OPIN); //Add the OPIN to the heap according to it's congestion cost cost = get_rr_cong_cost(to_node, pres_fac); @@ -857,7 +855,7 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f VTR_ASSERT(heap->try_pop(heap_head_node)); const RRNodeId& inode = heap_head_node.node; - VTR_ASSERT(rr_graph.node_type(inode) == OPIN); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::OPIN); adjust_one_rr_occ_and_acc_cost(inode, 1, acc_fac); route_ctx.clb_opins_used_locally[blk_id][iclass][ipin] = inode; diff --git a/vpr/src/route/route_net.cpp b/vpr/src/route/route_net.cpp index b8ba1227322..7f032b0dcca 100644 --- a/vpr/src/route/route_net.cpp +++ b/vpr/src/route/route_net.cpp @@ -229,7 +229,7 @@ size_t calculate_wirelength_available() { // But really what's happening is that this for loop iterates over every node and determines the available wirelength for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { const t_rr_type channel_type = rr_graph.node_type(rr_id); - if (channel_type == CHANX || channel_type == CHANY) { + if (channel_type == e_rr_type::CHANX || channel_type == e_rr_type::CHANY) { available_wirelength += rr_graph.node_capacity(rr_id) * rr_graph.node_length(rr_id); } } diff --git a/vpr/src/route/route_profiling.cpp b/vpr/src/route/route_profiling.cpp index 7ae6f7c813e..dffa3f59446 100644 --- a/vpr/src/route/route_profiling.cpp +++ b/vpr/src/route/route_profiling.cpp @@ -148,7 +148,7 @@ struct Congested_node_types { void congestion_analysis() { #if 0 // each type indexes into array which holds the congestion for that type - std::vector congestion_per_type((size_t)NUM_RR_TYPES, 0); + std::vector congestion_per_type((size_t)t_rr_type::NUM_RR_TYPES, 0); // print out specific node information if congestion for type is low enough int total_congestion = 0; @@ -164,7 +164,7 @@ void congestion_analysis() { constexpr int specific_node_print_threshold = 5; Congested_node_types congested; - for (int type = SOURCE; type < NUM_RR_TYPES; ++type) { + for (int type = SOURCE; type < t_rr_type::NUM_RR_TYPES; ++type) { float congestion_percentage = (float)congestion_per_type[type] / (float) total_congestion * 100; VTR_LOG(" %6s: %10.6f %\n", node_typename[type], congestion_percentage); // nodes of that type need specific printing diff --git a/vpr/src/route/route_tree.cpp b/vpr/src/route/route_tree.cpp index 799fa185fbd..cc8f5a8fee3 100644 --- a/vpr/src/route/route_tree.cpp +++ b/vpr/src/route/route_tree.cpp @@ -29,7 +29,7 @@ RouteTreeNode::RouteTreeNode(RRNodeId _inode, RRSwitchId _parent_switch, RouteTr } /** Print information about this subtree to stdout. */ -void RouteTreeNode::print(void) const { +void RouteTreeNode::print() const { print_x(0); } @@ -360,7 +360,7 @@ vtr::optional RouteTree::find_by_rr_id(RRNodeId rr_node) c * - invalid timing values * - congested SINKs * Returns true if OK. */ -bool RouteTree::is_valid(void) const { +bool RouteTree::is_valid() const { return is_valid_x(*_root); } @@ -396,7 +396,7 @@ bool RouteTree::is_valid_x(const RouteTreeNode& rt_node) const { return false; } - if (rr_graph.node_type(inode) == SINK) { // sink, must not be congested and must not have fanouts + if (rr_graph.node_type(inode) == e_rr_type::SINK) { // sink, must not be congested and must not have fanouts int occ = route_ctx.rr_node_route_inf[inode].occ(); int capacity = rr_graph.node_capacity(inode); if (rt_node._next != nullptr && rt_node._next->_parent == &rt_node) { @@ -563,9 +563,9 @@ RouteTree::add_subtree_from_heap(RTExploredNode* hptr, int target_net_pin_index, e_rr_type node_type = rr_graph.node_type(new_branch_inodes[i]); // If is_flat is enabled, IPINs should be added, since they are used for intra-cluster routing - if (node_type == IPIN && !is_flat) { + if (node_type == e_rr_type::IPIN && !is_flat) { new_node->re_expand = false; - } else if (node_type == SINK) { + } else if (node_type == e_rr_type::SINK) { new_node->re_expand = false; new_node->net_pin_index = target_net_pin_index; // net pin index is invalid for non-SINK nodes } else { @@ -626,7 +626,7 @@ void RouteTree::add_non_configurable_nodes(RouteTreeNode* rt_node, add_node(rt_node, new_node); new_node->net_pin_index = OPEN; - if (rr_graph.node_type(to_rr_node) == IPIN && !is_flat) { + if (rr_graph.node_type(to_rr_node) == e_rr_type::IPIN && !is_flat) { new_node->re_expand = false; } else { new_node->re_expand = true; @@ -650,7 +650,7 @@ RouteTree::prune(CBRR& connections_inf, std::vector* non_config_node_set_us std::unique_lock write_lock(_write_mutex); - VTR_ASSERT_MSG(rr_graph.node_type(root().inode) == SOURCE, "Root of route tree must be SOURCE"); + VTR_ASSERT_MSG(rr_graph.node_type(root().inode) == e_rr_type::SOURCE, "Root of route tree must be SOURCE"); VTR_ASSERT_MSG(_net_id, "RouteTree must be constructed using a ParentNetId"); @@ -709,7 +709,7 @@ RouteTree::prune_x(RouteTreeNode& rt_node, CBRR& connections_inf, bool force_pru } }); - if (rr_graph.node_type(rt_node.inode) == SINK) { + if (rr_graph.node_type(rt_node.inode) == e_rr_type::SINK) { if (!force_prune) { //Valid path to sink @@ -824,7 +824,7 @@ RouteTree::prune_x(RouteTreeNode& rt_node, CBRR& connections_inf, bool force_pru /** Remove all sinks and mark the remaining nodes as un-expandable. * This is used after routing a clock net. * TODO: is this function doing anything? Try running without it */ -void RouteTree::freeze(void) { +void RouteTree::freeze() { std::unique_lock write_lock(_write_mutex); return freeze_x(*_root); } @@ -835,7 +835,7 @@ void RouteTree::freeze_x(RouteTreeNode& rt_node) { const auto& rr_graph = device_ctx.rr_graph; remove_child_if(rt_node, [&](RouteTreeNode& child) { - if (rr_graph.node_type(child.inode) == SINK) { + if (rr_graph.node_type(child.inode) == e_rr_type::SINK) { VTR_LOGV_DEBUG(f_router_debug, "Removing sink %d from route tree\n", child.inode); return true; @@ -860,7 +860,7 @@ void RouteTree::freeze_x(RouteTreeNode& rt_node) { * "to" a sink is a usage of the set, but the code used to check if the * edge "from" the SINK, which shouldn't exist, was "configurable". This * might be some faulty code / unnecessary check carried over.) */ -std::vector RouteTree::get_non_config_node_set_usage(void) const { +std::vector RouteTree::get_non_config_node_set_usage() const { auto& device_ctx = g_vpr_ctx.device(); std::vector usage(device_ctx.rr_non_config_node_sets.size(), 0); @@ -871,7 +871,7 @@ std::vector RouteTree::get_non_config_node_set_usage(void) const { if (it == rr_to_nonconf.end()) continue; - if (device_ctx.rr_graph.node_type(rt_node.inode) == SINK) { + if (device_ctx.rr_graph.node_type(rt_node.inode) == e_rr_type::SINK) { if (device_ctx.rr_graph.rr_switch_inf(rt_node.parent_switch).configurable()) { usage[it->second] += 1; } diff --git a/vpr/src/route/route_utilization.cpp b/vpr/src/route/route_utilization.cpp index 66b03751451..c2aeb155ab2 100644 --- a/vpr/src/route/route_utilization.cpp +++ b/vpr/src/route/route_utilization.cpp @@ -4,12 +4,12 @@ #include "draw_global.h" vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool is_print) { - VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); + VTR_ASSERT(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& route_ctx = g_vpr_ctx.routing(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& route_ctx = g_vpr_ctx.routing(); vtr::Matrix usage({{device_ctx.grid.width(), device_ctx.grid.height()}}, 0.); @@ -41,8 +41,8 @@ vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool (void)is_print; #endif - if (rr_type == CHANX) { - VTR_ASSERT(rr_graph.node_type(rr_node) == CHANX); + if (rr_type == e_rr_type::CHANX) { + VTR_ASSERT(rr_graph.node_type(rr_node) == e_rr_type::CHANX); VTR_ASSERT(rr_graph.node_ylow(rr_node) == rr_graph.node_yhigh(rr_node)); int y = rr_graph.node_ylow(rr_node); @@ -50,8 +50,8 @@ vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool usage[x][y] += route_ctx.rr_node_route_inf[rr_node].occ(); } } else { - VTR_ASSERT(rr_type == CHANY); - VTR_ASSERT(rr_graph.node_type(rr_node) == CHANY); + VTR_ASSERT(rr_type == e_rr_type::CHANY); + VTR_ASSERT(rr_graph.node_type(rr_node) == e_rr_type::CHANY); VTR_ASSERT(rr_graph.node_xlow(rr_node) == rr_graph.node_xhigh(rr_node)); int x = rr_graph.node_xlow(rr_node); @@ -65,7 +65,7 @@ vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool vtr::Matrix calculate_routing_avail(t_rr_type rr_type) { //Calculate the number of available resources in each x/y channel - VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); + VTR_ASSERT(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; @@ -74,16 +74,16 @@ vtr::Matrix calculate_routing_avail(t_rr_type rr_type) { for (const RRNodeId& rr_node : rr_graph.nodes()) { const short& rr_node_capacity = rr_graph.node_capacity(rr_node); - if (rr_graph.node_type(rr_node) == CHANX && rr_type == CHANX) { - VTR_ASSERT(rr_graph.node_type(rr_node) == CHANX); + if (rr_graph.node_type(rr_node) == e_rr_type::CHANX && rr_type == e_rr_type::CHANX) { + VTR_ASSERT(rr_graph.node_type(rr_node) == e_rr_type::CHANX); VTR_ASSERT(rr_graph.node_ylow(rr_node) == rr_graph.node_yhigh(rr_node)); int y = rr_graph.node_ylow(rr_node); for (int x = rr_graph.node_xlow(rr_node); x <= rr_graph.node_xhigh(rr_node); ++x) { avail[x][y] += rr_node_capacity; } - } else if (rr_graph.node_type(rr_node) == CHANY && rr_type == CHANY) { - VTR_ASSERT(rr_graph.node_type(rr_node) == CHANY); + } else if (rr_graph.node_type(rr_node) == e_rr_type::CHANY && rr_type == e_rr_type::CHANY) { + VTR_ASSERT(rr_graph.node_type(rr_node) == e_rr_type::CHANY); VTR_ASSERT(rr_graph.node_xlow(rr_node) == rr_graph.node_xhigh(rr_node)); int x = rr_graph.node_xlow(rr_node); diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead.cpp index 240aeafbd61..17bb64a7b4e 100644 --- a/vpr/src/route/router_lookahead.cpp +++ b/vpr/src/route/router_lookahead.cpp @@ -73,7 +73,7 @@ std::pair ClassicLookahead::get_expected_delay_and_cong(RRNodeId n t_rr_type rr_type = rr_graph.node_type(node); - if (rr_type == CHANX || rr_type == CHANY) { + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { auto [num_segs_same_dir, num_segs_ortho_dir] = get_expected_segs_to_target(node, target_node); auto cost_index = rr_graph.node_cost_index(node); @@ -97,7 +97,7 @@ std::pair ClassicLookahead::get_expected_delay_and_cong(RRNodeId n + ipin_data.T_linear; return std::make_pair(params.criticality * Tdel, (1 - params.criticality) * cong_cost); - } else if (rr_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (rr_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ return std::make_pair(0., device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost); } else { /* Change this if you want to investigate route-throughs */ @@ -141,7 +141,7 @@ static std::pair get_expected_segs_to_target(RRNodeId inode, RRNodeId float ortho_inv_length = device_ctx.rr_indexed_data[RRIndexedDataId(ortho_cost_index)].inv_length; t_rr_type rr_type = rr_graph.node_type(inode); - if (rr_type == CHANX) { + if (rr_type == e_rr_type::CHANX) { ylow = rr_graph.node_ylow(inode); xhigh = rr_graph.node_xhigh(inode); xlow = rr_graph.node_xlow(inode); diff --git a/vpr/src/route/router_lookahead_compressed_map.cpp b/vpr/src/route/router_lookahead_compressed_map.cpp index 4c50beb175e..0b7ea09a62c 100644 --- a/vpr/src/route/router_lookahead_compressed_map.cpp +++ b/vpr/src/route/router_lookahead_compressed_map.cpp @@ -149,11 +149,11 @@ static void compute_router_wire_compressed_lookahead(const std::vector> sample_nodes; std::vector chan_types; if (segment_inf.parallel_axis == X_AXIS) - chan_types.push_back(CHANX); + chan_types.push_back(t_rr_type::CHANX); else if (segment_inf.parallel_axis == Y_AXIS) - chan_types.push_back(CHANY); + chan_types.push_back(t_rr_type::CHANY); else //Both for BOTH_AXIS segments and special segments such as clock_networks we want to search in both directions. - chan_types.insert(chan_types.end(), {CHANX, CHANY}); + chan_types.insert(chan_types.end(), {t_rr_type::CHANX, t_rr_type::CHANY}); for (e_rr_type chan_type : chan_types) { util::t_routing_cost_map routing_cost_map = util::get_routing_cost_map(longest_seg_length, @@ -180,7 +180,7 @@ static void compute_router_wire_compressed_lookahead(const std::vector CompressedMapLookahead::get_expected_delay_and_cong(RRNo float expected_cong_cost = std::numeric_limits::infinity(); e_rr_type from_type = rr_graph.node_type(from_node); - if (from_type == SOURCE || from_type == OPIN) { + if (from_type == t_rr_type::SOURCE || from_type == t_rr_type::OPIN) { //When estimating costs from a SOURCE/OPIN we look-up to find which wire types (and the //cost to reach them) in src_opin_delays. Once we know what wire types are //reachable, we query the f_wire_cost_map (i.e. the wire lookahead) to get the final @@ -472,7 +472,7 @@ std::pair CompressedMapLookahead::get_expected_delay_and_cong(RRNo .c_str()) .c_str()); - } else if (from_type == CHANX || from_type == CHANY) { + } else if (from_type == t_rr_type::CHANX || from_type == t_rr_type::CHANY) { //When estimating costs from a wire, we directly look-up the result in the wire lookahead (f_wire_cost_map) auto from_cost_index = rr_graph.node_cost_index(from_node); @@ -502,7 +502,7 @@ std::pair CompressedMapLookahead::get_expected_delay_and_cong(RRNo .c_str()); expected_delay_cost = cost_entry.delay * params.criticality; expected_cong_cost = cost_entry.congestion * (1 - params.criticality); - } else if (from_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (from_type == t_rr_type::IPIN) { /* Change if you're allowing route-throughs */ return std::make_pair(0., device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost); } else { /* Change this if you want to investigate route-throughs */ return std::make_pair(0., 0.); diff --git a/vpr/src/route/router_lookahead_extended_map.cpp b/vpr/src/route/router_lookahead_extended_map.cpp index 2f3964b47b5..e7d774e49cd 100644 --- a/vpr/src/route/router_lookahead_extended_map.cpp +++ b/vpr/src/route/router_lookahead_extended_map.cpp @@ -2,7 +2,6 @@ #include #include -#include #include "connection_router_interface.h" #include "rr_node.h" @@ -113,7 +112,7 @@ std::pair ExtendedMapLookahead::get_src_opin_cost(RRNodeId from_no const util::t_reachable_wire_inf& reachable_wire_inf = kv.second; util::Cost_Entry cost_entry; - if (reachable_wire_inf.wire_rr_type == SINK) { + if (reachable_wire_inf.wire_rr_type == e_rr_type::SINK) { //Some pins maybe reachable via a direct (OPIN -> IPIN) connection. //In the lookahead, we treat such connections as 'special' wire types //with no delay/congestion cost @@ -153,7 +152,7 @@ float ExtendedMapLookahead::get_chan_ipin_delays(RRNodeId to_node) const { auto& rr_graph = device_ctx.rr_graph; e_rr_type to_type = rr_graph.node_type(to_node); - VTR_ASSERT(to_type == SINK || to_type == IPIN); + VTR_ASSERT(to_type == e_rr_type::SINK || to_type == e_rr_type::IPIN); auto to_tile_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(to_node), rr_graph.node_ylow(to_node), @@ -202,9 +201,9 @@ std::pair ExtendedMapLookahead::get_expected_delay_and_cong(RRNode dy = to_y - from_y; e_rr_type from_type = rr_graph.node_type(from_node); - if (from_type == SOURCE || from_type == OPIN) { + if (from_type == e_rr_type::SOURCE || from_type == e_rr_type::OPIN) { return this->get_src_opin_cost(from_node, dx, dy, to_layer_num, params); - } else if (from_type == IPIN) { + } else if (from_type == e_rr_type::IPIN) { return std::make_pair(0., 0.); } @@ -406,7 +405,7 @@ std::pair ExtendedMapLookahead::run_dijkstra(RRNodeId start_node, } /* if this node is an ipin record its congestion/delay in the routing_cost_map */ - if (rr_graph.node_type(node) == IPIN) { + if (rr_graph.node_type(node) == e_rr_type::IPIN) { // the last cost should be the highest max_cost = current.cost(); @@ -589,13 +588,13 @@ float ExtendedMapLookahead::get_expected_cost( t_rr_type rr_type = rr_graph.node_type(current_node); - if (rr_type == CHANX || rr_type == CHANY || rr_type == SOURCE || rr_type == OPIN) { + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY || rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::OPIN) { float delay_cost, cong_cost; // Get the total cost using the combined delay and congestion costs std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); return delay_cost + cong_cost; - } else if (rr_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (rr_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ // This is to return only the cost between the IPIN and SINK. No need to // query the cost map, as the routing of this connection is almost done. return device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost; diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 621690f3bac..2d5972acabe 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -174,11 +174,11 @@ float MapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId target_nod if (is_flat_) { return get_expected_cost_flat_router(current_node, target_node, params, R_upstream); } else { - if (from_rr_type == CHANX || from_rr_type == CHANY || from_rr_type == SOURCE || from_rr_type == OPIN) { + if (from_rr_type == e_rr_type::CHANX || from_rr_type == e_rr_type::CHANY || from_rr_type == e_rr_type::SOURCE || from_rr_type == e_rr_type::OPIN) { // Get the total cost using the combined delay and congestion costs auto [delay_cost, cong_cost] = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); return delay_cost + cong_cost; - } else if (from_rr_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (from_rr_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ return (device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost); } else { /* Change this if you want to investigate route-throughs */ return (0.); @@ -210,7 +210,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI int to_layer_num = rr_graph.node_layer(target_node); // We have not checked the multi-layer FPGA for flat routing VTR_ASSERT(rr_graph.node_layer(current_node) == rr_graph.node_layer(target_node)); - if (from_rr_type == CHANX || from_rr_type == CHANY) { + if (from_rr_type == e_rr_type::CHANX || from_rr_type == e_rr_type::CHANY) { std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); // delay_cost and cong_cost only represent the cost to get to the root-level pins. The below offsets are used to represent the intra-cluster cost @@ -219,7 +219,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion; return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; - } else if (from_rr_type == OPIN) { + } else if (from_rr_type == e_rr_type::OPIN) { if (is_inter_cluster_node(rr_graph, current_node)) { // Similar to CHANX and CHANY std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); @@ -259,7 +259,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI } return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } - } else if (from_rr_type == IPIN) { + } else if (from_rr_type == e_rr_type::IPIN) { // we assume that route-through is not enabled. VTR_ASSERT(node_in_same_physical_tile(current_node, target_node)); const auto& pin_delays = intra_tile_pin_primitive_pin_delay.at(from_physical_type->index)[from_node_ptc_num]; @@ -272,7 +272,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI cong_cost = (1. - params.criticality) * pin_delay_itr->second.congestion; } return delay_cost + cong_cost; - } else if (from_rr_type == SOURCE) { + } else if (from_rr_type == e_rr_type::SOURCE) { if (node_in_same_physical_tile(current_node, target_node)) { delay_cost = 0.; cong_cost = 0.; @@ -290,7 +290,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI } return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } else { - VTR_ASSERT(from_rr_type == SINK); + VTR_ASSERT(from_rr_type == e_rr_type::SINK); return (0.); } } @@ -312,7 +312,7 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ float expected_cong_cost = std::numeric_limits::infinity(); e_rr_type from_type = rr_graph.node_type(from_node); - if (from_type == SOURCE || from_type == OPIN) { + if (from_type == e_rr_type::SOURCE || from_type == e_rr_type::OPIN) { //When estimating costs from a SOURCE/OPIN we look-up to find which wire types (and the //cost to reach them) in src_opin_delays. Once we know what wire types are //reachable, we query the f_wire_cost_map (i.e. the wire lookahead) to get the final @@ -358,7 +358,7 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ .c_str()) .c_str()); - } else if (from_type == CHANX || from_type == CHANY) { + } else if (from_type == e_rr_type::CHANX || from_type == e_rr_type::CHANY) { //When estimating costs from a wire, we directly look-up the result in the wire lookahead (f_wire_cost_map) auto from_cost_index = rr_graph.node_cost_index(from_node); @@ -388,7 +388,7 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ .c_str()); expected_delay_cost = cost_entry.delay * params.criticality; expected_cong_cost = cost_entry.congestion * (1 - params.criticality); - } else if (from_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (from_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ return std::make_pair(0., device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost); } else { /* Change this if you want to investigate route-throughs */ return std::make_pair(0., 0.); @@ -479,10 +479,10 @@ float MapLookahead::get_opin_distance_min_delay(int physical_tile_idx, int from_ /******** Function Definitions ********/ static util::Cost_Entry get_wire_cost_entry(e_rr_type rr_type, int seg_index, int from_layer_num, int delta_x, int delta_y, int to_layer_num) { - VTR_ASSERT_SAFE(rr_type == CHANX || rr_type == CHANY); + VTR_ASSERT_SAFE(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); int chan_index = 0; - if (rr_type == CHANY) { + if (rr_type == e_rr_type::CHANY) { chan_index = 1; } @@ -520,11 +520,11 @@ static void compute_router_wire_lookahead(const std::vector& segm for (const auto& segment_inf : segment_inf_vec) { std::vector chan_types; if (segment_inf.parallel_axis == X_AXIS) - chan_types.push_back(CHANX); + chan_types.push_back(e_rr_type::CHANX); else if (segment_inf.parallel_axis == Y_AXIS) - chan_types.push_back(CHANY); + chan_types.push_back(e_rr_type::CHANY); else //Both for BOTH_AXIS segments and special segments such as clock_networks we want to search in both directions. - chan_types.insert(chan_types.end(), {CHANX, CHANY}); + chan_types.insert(chan_types.end(), {e_rr_type::CHANX, e_rr_type::CHANY}); for (e_rr_type chan_type : chan_types) { util::t_routing_cost_map routing_cost_map = util::get_routing_cost_map(longest_seg_length, @@ -551,7 +551,7 @@ static void compute_router_wire_lookahead(const std::vector& segm /* sets the lookahead cost map entries based on representative cost entries from routing_cost_map */ static void set_lookahead_map_costs(int from_layer_num, int segment_index, e_rr_type chan_type, util::t_routing_cost_map& routing_cost_map) { - int chan_index = (chan_type == CHANX) ? 0 : 1; + int chan_index = (chan_type == e_rr_type::CHANX) ? 0 : 1; /* set the lookahead cost map entries with a representative cost entry from routing_cost_map */ for (unsigned to_layer = 0; to_layer < routing_cost_map.dim_size(0); to_layer++) { @@ -567,7 +567,7 @@ static void set_lookahead_map_costs(int from_layer_num, int segment_index, e_rr_ /* fills in missing lookahead map entries by copying the cost of the closest valid entry */ static void fill_in_missing_lookahead_entries(int segment_index, e_rr_type chan_type) { - int chan_index = (chan_type == CHANX) ? 0 : 1; + int chan_index = (chan_type == e_rr_type::CHANX) ? 0 : 1; auto& device_ctx = g_vpr_ctx.device(); @@ -842,7 +842,7 @@ static void min_opin_distance_cost_map(const util::t_src_opin_delays& src_opin_d } else { for (const auto& kv : layer_src_opin_delay_map) { const util::t_reachable_wire_inf& reachable_wire_inf = kv.second; - if (reachable_wire_inf.wire_rr_type == SINK) { + if (reachable_wire_inf.wire_rr_type == e_rr_type::SINK) { continue; } util::Cost_Entry wire_cost_entry; diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 6e1b2013ee4..6c626d7df1a 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -395,7 +395,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { if (device_ctx.grid.num_instances(&device_ctx.physical_tile_types[itile], from_layer_num) == 0) { continue; } - for (e_rr_type rr_type : {SOURCE, OPIN}) { + for (e_rr_type rr_type : {e_rr_type::SOURCE, e_rr_type::OPIN}) { t_physical_tile_loc sample_loc(OPEN, OPEN, OPEN); size_t num_sampled_locs = 0; @@ -411,7 +411,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { //No untried instances of the current tile type left VTR_LOG_WARN("Found no %ssample locations for %s in %s\n", (num_sampled_locs == 0) ? "" : "more ", - rr_node_typename[rr_type], + rr_node_typename[(size_t)rr_type], device_ctx.physical_tile_types[itile].name.c_str()); break; } @@ -442,7 +442,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { } if (reachable_wire_found) { VTR_LOGV_DEBUG(f_router_debug, "Found no reachable wires from %s (%s) at (%d,%d,%d)\n", - rr_node_typename[rr_type], + rr_node_typename[(size_t)rr_type], rr_node_arch_name(node_id, is_flat).c_str(), sample_loc.x, sample_loc.y, @@ -502,7 +502,7 @@ t_chan_ipins_delays compute_router_chan_ipin_lookahead() { for (int ix = min_x; ix < max_x; ix++) { for (int iy = min_y; iy < max_y; iy++) { - for (auto rr_type : {CHANX, CHANY}) { + for (auto rr_type : {e_rr_type::CHANX, e_rr_type::CHANY}) { for (const RRNodeId& node_id : node_lookup.find_channel_nodes(sample_loc.layer_num, ix, iy, rr_type)) { //Find the IPINs which are reachable from the wires within the bounding box //around the selected tile location @@ -551,13 +551,13 @@ RRNodeId get_start_node(int layer, int start_x, int start_y, int target_x, int t RRNodeId result = RRNodeId::INVALID(); - if (rr_type != CHANX && rr_type != CHANY) { + if (rr_type != e_rr_type::CHANX && rr_type != e_rr_type::CHANY) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Must start lookahead routing from CHANX or CHANY node\n"); } /* determine which direction the wire should go in based on the start & target coordinates */ Direction direction = Direction::INC; - if ((rr_type == CHANX && target_x < start_x) || (rr_type == CHANY && target_y < start_y)) { + if ((rr_type == e_rr_type::CHANX && target_x < start_x) || (rr_type == e_rr_type::CHANY && target_y < start_y)) { direction = Direction::DEC; } @@ -611,7 +611,7 @@ std::pair get_xy_deltas(RRNodeId from_node, RRNodeId to_node) { int from_chan; int to_seg; int to_chan; - if (from_type == CHANY) { + if (from_type == e_rr_type::CHANY) { from_seg_low = rr_graph.node_ylow(from_node); from_seg_high = rr_graph.node_yhigh(from_node); from_chan = rr_graph.node_xlow(from_node); @@ -664,7 +664,7 @@ std::pair get_xy_deltas(RRNodeId from_node, RRNodeId to_node) { delta_seg++; } - if (from_type == CHANY) { + if (from_type == e_rr_type::CHANY) { delta_x = delta_chan; delta_y = delta_seg; } else { @@ -721,11 +721,11 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length, std::vector sample_nodes; std::vector chan_types; if (segment_inf.parallel_axis == X_AXIS) - chan_types.push_back(CHANX); + chan_types.push_back(e_rr_type::CHANX); else if (segment_inf.parallel_axis == Y_AXIS) - chan_types.push_back(CHANY); + chan_types.push_back(e_rr_type::CHANY); else //Both for BOTH_AXIS segments and special segments such as clock_networks we want to search in both directions. - chan_types.insert(chan_types.end(), {CHANX, CHANY}); + chan_types.insert(chan_types.end(), {e_rr_type::CHANX, e_rr_type::CHANY}); for (int ref_inc : ref_increments) { int sample_x = ref_x + ref_inc; @@ -783,7 +783,7 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length, if (sample_nodes.empty()) { VTR_LOG_WARN("Unable to find any sample location for segment %s type '%s' (length %d)\n", - rr_node_typename[chan_type], + rr_node_typename[(size_t)chan_type], segment_inf.name.c_str(), segment_inf.length); } else { @@ -850,7 +850,7 @@ std::pair get_cost_from_src_opin(const std::map IPIN) connection. //In the lookahead, we treat such connections as 'special' wire types //with no delay/congestion cost @@ -907,14 +907,14 @@ void dump_readable_router_lookahead_map(const std::string& file_name, const std: for (int from_layer_num = 0; from_layer_num < num_layers; from_layer_num++) { for (int to_layer_num = 0; to_layer_num < num_layers; to_layer_num++) { - for (e_rr_type chan_type : {CHANX, CHANY}) { + for (e_rr_type chan_type : {e_rr_type::CHANX, e_rr_type::CHANY}) { for (int seg_index = 0; seg_index < dim_sizes[3]; seg_index++) { for (int dx = 0; dx < grid_width; dx++) { for (int dy = 0; dy < grid_height; dy++) { auto cost = wire_cost_func(chan_type, seg_index, from_layer_num, dx, dy, to_layer_num); ofs << from_layer_num << "," << to_layer_num << "," - << rr_node_typename[chan_type] << "," + << rr_node_typename[(size_t)chan_type] << "," << seg_index << "," << dx << "," << dy << "," @@ -983,10 +983,10 @@ static void dijkstra_flood_to_wires(int itile, e_rr_type curr_rr_type = rr_graph.node_type(curr.node); int curr_layer_num = rr_graph.node_layer(curr.node); - if (curr_rr_type == CHANX || curr_rr_type == CHANY || curr_rr_type == SINK) { + if (curr_rr_type == e_rr_type::CHANX || curr_rr_type == e_rr_type::CHANY || curr_rr_type == e_rr_type::SINK) { //We stop expansion at any CHANX/CHANY/SINK int seg_index; - if (curr_rr_type != SINK) { + if (curr_rr_type != e_rr_type::SINK) { //It's a wire, figure out its type auto cost_index = rr_graph.node_cost_index(curr.node); seg_index = device_ctx.rr_indexed_data[cost_index].seg_index; @@ -1011,7 +1011,7 @@ static void dijkstra_flood_to_wires(int itile, src_opin_delays[root_layer_num][itile][ptc][curr_layer_num][seg_index].congestion = curr.congestion; } - } else if (curr_rr_type == SOURCE || curr_rr_type == OPIN || curr_rr_type == IPIN) { + } else if (curr_rr_type == e_rr_type::SOURCE || curr_rr_type == e_rr_type::OPIN || curr_rr_type == e_rr_type::IPIN) { //We allow expansion through SOURCE/OPIN/IPIN types auto cost_index = rr_graph.node_cost_index(curr.node); float incr_cong = device_ctx.rr_indexed_data[cost_index].base_cost; //Current nodes congestion cost @@ -1091,7 +1091,7 @@ static void dijkstra_flood_to_ipins(RRNodeId node, util::t_chan_ipins_delays& ch pq.pop(); e_rr_type curr_rr_type = rr_graph.node_type(curr.node); - if (curr_rr_type == IPIN) { + if (curr_rr_type == e_rr_type::IPIN) { int node_x = rr_graph.node_xlow(curr.node); int node_y = rr_graph.node_ylow(curr.node); int node_layer = rr_graph.node_layer(curr.node); @@ -1110,7 +1110,7 @@ static void dijkstra_flood_to_ipins(RRNodeId node, util::t_chan_ipins_delays& ch chan_ipins_delays[root_layer][itile][ptc].wire_rr_type = curr_rr_type; chan_ipins_delays[root_layer][itile][ptc].delay = site_pin_delay; chan_ipins_delays[root_layer][itile][ptc].congestion = curr.congestion; - } else if (curr_rr_type == CHANX || curr_rr_type == CHANY) { + } else if (curr_rr_type == e_rr_type::CHANX || curr_rr_type == e_rr_type::CHANY) { if (curr.level >= MAX_EXPANSION_LEVEL) { continue; } @@ -1255,7 +1255,7 @@ static void run_intra_tile_dijkstra(const RRGraphView& rr_graph, } auto curr_type = rr_graph.node_type(curr.node); VTR_ASSERT(curr_type != t_rr_type::CHANX && curr_type != t_rr_type::CHANY); - if (curr_type != SINK) { + if (curr_type != e_rr_type::SINK) { for (RREdgeId edge : rr_graph.edge_range(curr.node)) { RRNodeId next_node = rr_graph.rr_nodes().edge_sink_node(edge); auto cost_index = rr_graph.node_cost_index(next_node); @@ -1329,7 +1329,7 @@ static void run_dijkstra(RRNodeId start_node, //VTR_LOG("Expanding with delay=%10.3g cong=%10.3g (%s)\n", current.delay, current.congestion_upstream, describe_rr_node(rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, curr_node).c_str()); /* if this node is an ipin record its congestion/delay in the routing_cost_map */ - if (rr_graph.node_type(curr_node) == IPIN) { + if (rr_graph.node_type(curr_node) == e_rr_type::IPIN) { VTR_ASSERT_SAFE(rr_graph.node_xlow(curr_node) == rr_graph.node_xhigh(curr_node)); VTR_ASSERT_SAFE(rr_graph.node_ylow(curr_node) == rr_graph.node_yhigh(curr_node)); int ipin_x = rr_graph.node_xlow(curr_node); @@ -1384,7 +1384,7 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, } int switch_ind = size_t(rr_graph.edge_switch(parent, edge)); - if (rr_graph.node_type(child_node) == SINK) return; + if (rr_graph.node_type(child_node) == e_rr_type::SINK) return; /* skip this child if it has already been expanded from */ if (node_expanded[child_node]) { diff --git a/vpr/src/route/router_lookahead_sampling.cpp b/vpr/src/route/router_lookahead_sampling.cpp index a8ad7dc2f15..c8e71ad6267 100644 --- a/vpr/src/route/router_lookahead_sampling.cpp +++ b/vpr/src/route/router_lookahead_sampling.cpp @@ -130,7 +130,7 @@ static std::tuple get_node_info(const t_rr_node& node, int num_se const auto& rr_graph = device_ctx.rr_graph; RRNodeId rr_node = node.id(); - if (rr_graph.node_type(rr_node) != CHANX && rr_graph.node_type(rr_node) != CHANY) { + if (rr_graph.node_type(rr_node) != e_rr_type::CHANX && rr_graph.node_type(rr_node) != e_rr_type::CHANY) { return std::tuple(OPEN, OPEN, OPEN); } @@ -203,7 +203,7 @@ std::vector find_sample_regions(int num_segments) { // compute bounding boxes for each segment type std::vector> bounding_box_for_segment(num_segments, vtr::Rect()); for (auto& node : rr_graph.rr_nodes()) { - if (rr_graph.node_type(node.id()) != CHANX && rr_graph.node_type(node.id()) != CHANY) continue; + if (rr_graph.node_type(node.id()) != e_rr_type::CHANX && rr_graph.node_type(node.id()) != e_rr_type::CHANY) continue; if (rr_graph.node_capacity(node.id()) == 0 || rr_graph.num_edges(node.id()) == 0) continue; int seg_index = device_ctx.rr_indexed_data[rr_graph.node_cost_index(node.id())].seg_index; diff --git a/vpr/src/route/router_stats.h b/vpr/src/route/router_stats.h index 4336d419083..176455c80e6 100644 --- a/vpr/src/route/router_stats.h +++ b/vpr/src/route/router_stats.h @@ -38,13 +38,13 @@ struct RouterStats { size_t inter_cluster_node_pops = 0; size_t intra_cluster_node_pushes = 0; size_t intra_cluster_node_pops = 0; - size_t inter_cluster_node_type_cnt_pushes[t_rr_type::NUM_RR_TYPES] = {0}; - size_t inter_cluster_node_type_cnt_pops[t_rr_type::NUM_RR_TYPES] = {0}; - size_t intra_cluster_node_type_cnt_pushes[t_rr_type::NUM_RR_TYPES] = {0}; - size_t intra_cluster_node_type_cnt_pops[t_rr_type::NUM_RR_TYPES] = {0}; + size_t inter_cluster_node_type_cnt_pushes[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; + size_t inter_cluster_node_type_cnt_pops[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; + size_t intra_cluster_node_type_cnt_pushes[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; + size_t intra_cluster_node_type_cnt_pops[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; // For debugging purposes - size_t rt_node_pushes[t_rr_type::NUM_RR_TYPES] = {0}; + size_t rt_node_pushes[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; /** Add rhs's stats to mine */ void combine(RouterStats& rhs) { @@ -56,7 +56,7 @@ struct RouterStats { heap_pops += rhs.heap_pops; inter_cluster_node_pops += rhs.inter_cluster_node_pops; intra_cluster_node_pops += rhs.intra_cluster_node_pops; - for (int node_type_idx = 0; node_type_idx < t_rr_type::NUM_RR_TYPES; node_type_idx++) { + for (size_t node_type_idx = 0; node_type_idx < (size_t)t_rr_type::NUM_RR_TYPES; node_type_idx++) { inter_cluster_node_type_cnt_pushes[node_type_idx] += rhs.inter_cluster_node_type_cnt_pushes[node_type_idx]; inter_cluster_node_type_cnt_pops[node_type_idx] += rhs.inter_cluster_node_type_cnt_pops[node_type_idx]; intra_cluster_node_type_cnt_pushes[node_type_idx] += rhs.intra_cluster_node_type_cnt_pushes[node_type_idx]; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 072b62c1c98..cbb24825014 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1462,11 +1462,11 @@ static void build_rr_graph(e_graph_type graph_type, // clock_modeling::DEDICATED_NETWORK will append some rr nodes after // the regular graph. for (int i = 0; i < num_rr_nodes; i++) { - if (rr_graph.node_type(RRNodeId(i)) == CHANX) { + if (rr_graph.node_type(RRNodeId(i)) == t_rr_type::CHANX) { int ylow = rr_graph.node_ylow(RRNodeId(i)); device_ctx.rr_graph_builder.set_node_capacity(RRNodeId(i), nodes_per_chan.x_list[ylow]); } - if (rr_graph.node_type(RRNodeId(i)) == CHANY) { + if (rr_graph.node_type(RRNodeId(i)) == t_rr_type::CHANY) { int xlow = rr_graph.node_xlow(RRNodeId(i)); device_ctx.rr_graph_builder.set_node_capacity(RRNodeId(i), nodes_per_chan.y_list[xlow]); } @@ -1479,7 +1479,7 @@ static void build_rr_graph(e_graph_type graph_type, for (int rr_node_id = 0; rr_node_id < num_rr_nodes; rr_node_id++) { auto node_type = rr_graph.node_type(RRNodeId(rr_node_id)); auto node_dir = rr_graph.node_direction(RRNodeId(rr_node_id)); - if (node_type != CHANX && node_type != CHANY) { //SRC/SINK/IPIN/OPIN + if (node_type != t_rr_type::CHANX && node_type != t_rr_type::CHANY) { //SRC/SINK/IPIN/OPIN device_ctx.rr_graph_builder.set_node_ptc_twist_incr(RRNodeId(rr_node_id), 0); } else { //The current ptc twist increment number in UNDIR TILEABLE RRGraph is 2 and -2 @@ -2246,7 +2246,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder if (i > 0) { int tracks_per_chan = ((is_global_graph) ? 1 : chan_width.x_list[j]); - build_rr_chan(rr_graph_builder, layer, i, j, CHANX, track_to_pin_lookup_x, sb_conn_map, + build_rr_chan(rr_graph_builder, layer, i, j, t_rr_type::CHANX, track_to_pin_lookup_x, sb_conn_map, switch_block_conn, num_of_3d_conns_custom_SB, CHANX_COST_INDEX_START, chan_width, grid, tracks_per_chan, @@ -2267,7 +2267,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } if (j > 0) { int tracks_per_chan = ((is_global_graph) ? 1 : chan_width.y_list[i]); - build_rr_chan(rr_graph_builder, layer, i, j, CHANY, track_to_pin_lookup_y, sb_conn_map, + build_rr_chan(rr_graph_builder, layer, i, j, t_rr_type::CHANY, track_to_pin_lookup_y, sb_conn_map, switch_block_conn, num_of_3d_conns_custom_SB, CHANX_COST_INDEX_START + num_seg_types_x, chan_width, grid, tracks_per_chan, @@ -2456,12 +2456,12 @@ static void add_classes_rr_graph(RRGraphBuilder& rr_graph_builder, int class_num_pins = get_class_num_pins_from_class_physical_num(physical_type, class_num); if (class_type == DRIVER) { rr_graph_builder.set_node_cost_index(class_inode, RRIndexedDataId(SOURCE_COST_INDEX)); - rr_graph_builder.set_node_type(class_inode, SOURCE); + rr_graph_builder.set_node_type(class_inode, t_rr_type::SOURCE); } else { VTR_ASSERT(class_type == RECEIVER); rr_graph_builder.set_node_cost_index(class_inode, RRIndexedDataId(SINK_COST_INDEX)); - rr_graph_builder.set_node_type(class_inode, SINK); + rr_graph_builder.set_node_type(class_inode, t_rr_type::SINK); } VTR_ASSERT(class_num_pins <= std::numeric_limits::max()); rr_graph_builder.set_node_capacity(class_inode, (short)class_num_pins); @@ -2496,7 +2496,7 @@ static void add_pins_rr_graph(RRGraphBuilder& rr_graph_builder, int x_offset = x_offset_vec[pin_coord]; int y_offset = y_offset_vec[pin_coord]; e_side pin_side = pin_sides_vec[pin_coord]; - auto node_type = (pin_type == DRIVER) ? OPIN : IPIN; + auto node_type = (pin_type == DRIVER) ? t_rr_type::OPIN : t_rr_type::IPIN; RRNodeId node_id = node_lookup.find_node(layer, i + x_offset, j + y_offset, @@ -2717,7 +2717,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, total_pin_Fc += Fc[pin_index][iseg]; } - RRNodeId node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, OPIN, pin_index, side); + RRNodeId node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, t_rr_type::OPIN, pin_index, side); VTR_ASSERT(node_index); for (auto connected_layer : get_layers_pin_is_connected_to(type, layer, pin_index)) { @@ -3165,14 +3165,14 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, int chan_coord = y_coord; //The absolute coordinate of this channel within the device int seg_dimension = device_ctx.grid.width() - 2; //-2 for no perim channels int chan_dimension = device_ctx.grid.height() - 2; //-2 for no perim channels - const t_chan_details& from_chan_details = (chan_type == CHANX) ? chan_details_x : chan_details_y; - const t_chan_details& opposite_chan_details = (chan_type == CHANX) ? chan_details_y : chan_details_x; - t_rr_type opposite_chan_type = CHANY; - if (chan_type == CHANY) { + const t_chan_details& from_chan_details = (chan_type == t_rr_type::CHANX) ? chan_details_x : chan_details_y; + const t_chan_details& opposite_chan_details = (chan_type == t_rr_type::CHANX) ? chan_details_y : chan_details_x; + t_rr_type opposite_chan_type = t_rr_type::CHANY; + if (chan_type == t_rr_type::CHANY) { //Swap values since CHANX was assumed above std::swap(seg_coord, chan_coord); std::swap(seg_dimension, chan_dimension); - opposite_chan_type = CHANX; + opposite_chan_type = t_rr_type::CHANX; } const t_chan_seg_details* seg_details = from_chan_details[x_coord][y_coord].data(); @@ -3201,7 +3201,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(seg_coord == start); const t_chan_seg_details* from_seg_details = nullptr; - if (chan_type == CHANY) { + if (chan_type == t_rr_type::CHANY) { from_seg_details = chan_details_y[x_coord][start].data(); } else { from_seg_details = chan_details_x[start][y_coord].data(); @@ -3222,11 +3222,11 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, if (chan_coord > 0) { const t_chan_seg_details* to_seg_details; int max_opposite_chan_width; - if (chan_type == CHANX) { + if (chan_type == t_rr_type::CHANX) { to_seg_details = chan_details_y[start][y_coord].data(); max_opposite_chan_width = nodes_per_chan.y_max; } else { - VTR_ASSERT(chan_type == CHANY); + VTR_ASSERT(chan_type == t_rr_type::CHANY); to_seg_details = chan_details_x[x_coord][start].data(); max_opposite_chan_width = nodes_per_chan.x_max; } @@ -3242,11 +3242,11 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, if (chan_coord < chan_dimension) { const t_chan_seg_details* to_seg_details; int max_opposite_chan_width = 0; - if (chan_type == CHANX) { + if (chan_type == e_rr_type::CHANX) { to_seg_details = chan_details_y[start][y_coord + 1].data(); max_opposite_chan_width = nodes_per_chan.y_max; } else { - VTR_ASSERT(chan_type == CHANY); + VTR_ASSERT(chan_type == t_rr_type::CHANY); to_seg_details = chan_details_x[x_coord + 1][start].data(); max_opposite_chan_width = nodes_per_chan.x_max; } @@ -3274,11 +3274,11 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, const t_chan_seg_details* to_seg_details; /* AA: Same channel width for straight through connections assuming uniform width distributions along the axis*/ int max_chan_width = 0; - if (chan_type == CHANX) { + if (chan_type == e_rr_type::CHANX) { to_seg_details = chan_details_x[target_seg][y_coord].data(); max_chan_width = nodes_per_chan.x_max; } else { - VTR_ASSERT(chan_type == CHANY); + VTR_ASSERT(chan_type == t_rr_type::CHANY); to_seg_details = chan_details_y[x_coord][target_seg].data(); max_chan_width = nodes_per_chan.y_max; } @@ -3302,10 +3302,10 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_details[track].index())); rr_graph_builder.set_node_capacity(node, 1); /* GLOBAL routing handled elsewhere */ - if (chan_type == CHANX) { + if (chan_type == e_rr_type::CHANX) { rr_graph_builder.set_node_coordinates(node, start, y_coord, end, y_coord); } else { - VTR_ASSERT(chan_type == CHANY); + VTR_ASSERT(chan_type == t_rr_type::CHANY); rr_graph_builder.set_node_coordinates(node, x_coord, start, x_coord, end); } @@ -3348,7 +3348,7 @@ static void build_inter_die_custom_sb_rr_chan(RRGraphBuilder& rr_graph_builder, int offset = 0; while (true) { //going through allocated nodes until no nodes are found within the RRGraph builder - RRNodeId node = rr_graph_builder.node_lookup().find_node(layer, x_coord, y_coord, CHANX, start_track + offset); + RRNodeId node = rr_graph_builder.node_lookup().find_node(layer, x_coord, y_coord, e_rr_type::CHANX, start_track + offset); if (node) { rr_graph_builder.set_node_layer(node, layer); rr_graph_builder.set_node_coordinates(node, x_coord, y_coord, x_coord, y_coord); @@ -3360,7 +3360,7 @@ static void build_inter_die_custom_sb_rr_chan(RRGraphBuilder& rr_graph_builder, rr_graph_builder.set_node_rc_index(node, NodeRCIndex( find_create_rr_rc_data(R, C, mutable_device_ctx.rr_rc_data))); - rr_graph_builder.set_node_type(node, CHANX); + rr_graph_builder.set_node_type(node, e_rr_type::CHANX); rr_graph_builder.set_node_track_num(node, start_track + offset); rr_graph_builder.set_node_direction(node, Direction::NONE); @@ -4210,7 +4210,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, continue; } - RRNodeId opin_node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, OPIN, pin_index, side); + RRNodeId opin_node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, t_rr_type::OPIN, pin_index, side); if (!opin_node_index) continue; //No valid from node for (int iseg = 0; iseg < num_seg_types; iseg++) { @@ -4230,11 +4230,11 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, * side is the side of the logic or io block. */ bool vert = ((side == TOP) || (side == BOTTOM)); bool pos_dir = ((side == TOP) || (side == RIGHT)); - t_rr_type chan_type = (vert ? CHANX : CHANY); + t_rr_type chan_type = (vert ? e_rr_type::CHANX : t_rr_type::CHANY); int chan = (vert ? (j) : (i)); int seg = (vert ? (i) : (j)); int max_len = (vert ? grid.width() : grid.height()); - e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + e_parallel_axis wanted_axis = chan_type == e_rr_type::CHANX ? X_AXIS : Y_AXIS; int seg_index = get_parallel_seg_index(iseg, seg_index_map, wanted_axis); /*The segment at index iseg doesn't have the proper adjacency so skip building Fc_out conenctions for it*/ @@ -4260,7 +4260,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, continue; } - const t_chan_seg_details* seg_details = (chan_type == CHANX ? chan_details_x[seg][chan] : chan_details_y[chan][seg]).data(); + const t_chan_seg_details* seg_details = (chan_type == e_rr_type::CHANX ? chan_details_x[seg][chan] : chan_details_y[chan][seg]).data(); if (seg_details[0].length() == 0) continue; @@ -4485,13 +4485,13 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, if (directs[i].to_side != NUM_2D_SIDES) { //Explicit side specified, only create if pin exists on that side - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x + directs[i].x_offset, y + directs[i].y_offset, IPIN, ipin, directs[i].to_side); + RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x + directs[i].x_offset, y + directs[i].y_offset, e_rr_type::IPIN, ipin, directs[i].to_side); if (inode) { inodes.push_back(inode); } } else { //No side specified, get all candidates - inodes = rr_graph_builder.node_lookup().find_nodes_at_all_sides(layer, x + directs[i].x_offset, y + directs[i].y_offset, IPIN, ipin); + inodes = rr_graph_builder.node_lookup().find_nodes_at_all_sides(layer, x + directs[i].x_offset, y + directs[i].y_offset, e_rr_type::IPIN, ipin); } if (inodes.size() > 0) { @@ -4623,7 +4623,7 @@ static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_gr //candidate would be picked (i.e. to minimize the drawn edge length). // //This function attempts to pick the 'best/closest' of the candidates. - VTR_ASSERT(rr_graph.node_type(from_rr) == OPIN); + VTR_ASSERT(rr_graph.node_type(from_rr) == t_rr_type::OPIN); float best_dist = std::numeric_limits::infinity(); RRNodeId best_rr = RRNodeId::INVALID(); @@ -4635,7 +4635,7 @@ static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_gr } for (RRNodeId to_rr : candidate_rr_nodes) { - VTR_ASSERT(rr_graph.node_type(to_rr) == IPIN); + VTR_ASSERT(rr_graph.node_type(to_rr) == e_rr_type::IPIN); float to_dist = std::abs(rr_graph.node_xlow(from_rr) - rr_graph.node_xlow(to_rr)) + std::abs(rr_graph.node_ylow(from_rr) - rr_graph.node_ylow(to_rr)); diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 76a71af29a5..a4ccb673440 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -709,10 +709,10 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, tr_i = ((side == LEFT) ? (i - 1) : i); tr_j = ((side == BOTTOM) ? (j - 1) : j); - to_type = ((side == LEFT) || (side == RIGHT)) ? CHANY : CHANX; + to_type = ((side == LEFT) || (side == RIGHT)) ? e_rr_type::CHANY : e_rr_type::CHANX; - chan = ((to_type == CHANX) ? tr_j : tr_i); - seg = ((to_type == CHANX) ? tr_i : tr_j); + chan = ((to_type == e_rr_type::CHANX) ? tr_j : tr_i); + seg = ((to_type == e_rr_type::CHANX) ? tr_i : tr_j); bool vert = !((side == TOP) || (side == BOTTOM)); @@ -723,10 +723,10 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, if ((tr_j < 0) || (tr_j > int(device_ctx.grid.height() - 2))) { //-2 for no perimeter channels continue; } - if ((CHANX == to_type) && (tr_i < 1)) { + if ((e_rr_type::CHANX == to_type) && (tr_i < 1)) { continue; } - if ((CHANY == to_type) && (tr_j < 1)) { + if ((e_rr_type::CHANY == to_type) && (tr_j < 1)) { continue; } if (opin_to_track_map[type->index].empty()) { @@ -804,15 +804,15 @@ int get_unidir_opin_connections(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(Fc % 2 == 0); /* get_rr_node_indices needs x and y coords. */ - x = ((CHANX == chan_type) ? seg : chan); - y = ((CHANX == chan_type) ? chan : seg); + x = ((e_rr_type::CHANX == chan_type) ? seg : chan); + y = ((e_rr_type::CHANX == chan_type) ? chan : seg); /* Get the lists of possible muxes. */ int dummy; std::vector inc_muxes; std::vector dec_muxes; /* AA: Determine the channel width instead of using max channels to not create hanging nodes*/ - int max_chan_width = (CHANX == chan_type) ? nodes_per_chan.x_list[y] : nodes_per_chan.y_list[x]; + int max_chan_width = (e_rr_type::CHANX == chan_type) ? nodes_per_chan.x_list[y] : nodes_per_chan.y_list[x]; label_wire_muxes(chan, seg, seg_details, seg_type_index, max_len, Direction::INC, max_chan_width, true, inc_muxes, &num_inc_muxes, &dummy); @@ -1097,8 +1097,8 @@ static void load_chan_rr_indices(const int max_chan_width, for (int chan = 0; chan < num_chans - 1; ++chan) { for (int seg = 1; seg < chan_len - 1; ++seg) { /* Assign an inode to the starts of tracks */ - int x = (type == CHANX ? seg : chan); - int y = (type == CHANX ? chan : seg); + int x = (type == e_rr_type::CHANX ? seg : chan); + int y = (type == e_rr_type::CHANX ? chan : seg); const t_chan_seg_details* seg_details = chan_details[x][y].data(); /* Reserve nodes in lookup to save memory */ @@ -1114,7 +1114,7 @@ static void load_chan_rr_indices(const int max_chan_width, /* TODO: Now we still use the (y, x) convention here for CHANX. Should rework later */ int node_x = chan; int node_y = start; - if (CHANX == type) { + if (e_rr_type::CHANX == type) { std::swap(node_x, node_y); } @@ -1181,16 +1181,16 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m //check if both from_node and to_node exists in the rr-graph //CHANY -> CHANX connection if (check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, - conn_vector[iconn].from_wire_layer, CHANY, + conn_vector[iconn].from_wire_layer, e_rr_type::CHANY, conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, - CHANX)) { + e_rr_type::CHANX)) { num_of_3d_conn++; } //CHANX -> CHANY connection if (check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, - conn_vector[iconn].from_wire_layer, CHANX, + conn_vector[iconn].from_wire_layer, e_rr_type::CHANX, conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, - CHANY)) { + e_rr_type::CHANY)) { num_of_3d_conn++; } } @@ -1237,13 +1237,13 @@ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, } //reserve extra nodes for inter-die track-to-track connection - rr_graph_builder.node_lookup().reserve_nodes(layer, y, x, CHANX, conn_count + nodes_per_chan->max); + rr_graph_builder.node_lookup().reserve_nodes(layer, y, x, e_rr_type::CHANX, conn_count + nodes_per_chan->max); for (int rr_node_offset = 0; rr_node_offset < conn_count; rr_node_offset++) { - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x, y, CHANX, nodes_per_chan->max + rr_node_offset); + RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x, y, e_rr_type::CHANX, nodes_per_chan->max + rr_node_offset); if (!inode) { inode = RRNodeId(*index); ++(*index); - rr_graph_builder.node_lookup().add_node(inode, layer, y, x, CHANX, nodes_per_chan->max + rr_node_offset); + rr_graph_builder.node_lookup().add_node(inode, layer, y, x, e_rr_type::CHANX, nodes_per_chan->max + rr_node_offset); } } } @@ -1361,8 +1361,8 @@ static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, for (int height_offset = 0; height_offset < physical_type_ptr->height; ++height_offset) { int y_tile = root_y + height_offset; //only nodes on the tile may be located in a location other than the root-location - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, OPIN, physical_type_ptr->num_pins, side); - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, IPIN, physical_type_ptr->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::OPIN, physical_type_ptr->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::IPIN, physical_type_ptr->num_pins, side); } } } @@ -1376,11 +1376,11 @@ static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, int y_tile = root_y + y_offset[pin_coord_idx]; e_side side = pin_sides[pin_coord_idx]; if (pin_type == DRIVER) { - rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, OPIN, pin_num, side); + rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::OPIN, pin_num, side); assigned_to_rr_node = true; } else { VTR_ASSERT(pin_type == RECEIVER); - rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, IPIN, pin_num, side); + rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::IPIN, pin_num, side); assigned_to_rr_node = true; } } @@ -1412,16 +1412,16 @@ static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, int* index) { for (int x_tile = root_x; x_tile < (root_x + block_width); x_tile++) { for (int y_tile = root_y; y_tile < (root_y + block_height); y_tile++) { - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, SOURCE, class_num_vec.size(), TOTAL_2D_SIDES[0]); - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, SINK, class_num_vec.size(), TOTAL_2D_SIDES[0]); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::SOURCE, class_num_vec.size(), TOTAL_2D_SIDES[0]); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::SINK, class_num_vec.size(), TOTAL_2D_SIDES[0]); } } for (const int class_num : class_num_vec) { e_pin_type class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); - e_rr_type node_type = SINK; + e_rr_type node_type = e_rr_type::SINK; if (class_type == DRIVER) { - node_type = SOURCE; + node_type = e_rr_type::SOURCE; } else { VTR_ASSERT(class_type == RECEIVER); } @@ -1447,13 +1447,13 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, bool is_flat) { - /* Allocates and loads all the structures needed for fast lookups of the * - * index of an rr_node. rr_node_indices is a matrix containing the index * - * of the *first* rr_node at a given (i,j) location. */ + /* Allocates and loads all the structures needed for fast lookups of the + * index of an rr_node. rr_node_indices is a matrix containing the index + * of the *first* rr_node at a given (i,j) location. */ /* Alloc the lookup table */ for (t_rr_type rr_type : RR_TYPES) { - if (rr_type == CHANX) { + if (rr_type == e_rr_type::CHANX) { rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.height(), grid.width(), rr_type, NUM_2D_SIDES); } else { rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.width(), grid.height(), rr_type, NUM_2D_SIDES); @@ -1465,9 +1465,9 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, /* Load the data for x and y channels */ load_chan_rr_indices(nodes_per_chan->x_max, grid, grid.width(), grid.height(), - CHANX, chan_details_x, rr_graph_builder, index); + e_rr_type::CHANX, chan_details_x, rr_graph_builder, index); load_chan_rr_indices(nodes_per_chan->y_max, grid, grid.height(), grid.width(), - CHANY, chan_details_y, rr_graph_builder, index); + e_rr_type::CHANY, chan_details_y, rr_graph_builder, index); } void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_builder, @@ -1544,7 +1544,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, for (t_rr_type rr_type : RR_TYPES) { /* Get the list of nodes at a specific location (x, y) */ std::vector nodes_from_lookup; - if (rr_type == CHANX || rr_type == CHANY) { + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { nodes_from_lookup = rr_graph.node_lookup().find_channel_nodes(l, x, y, rr_type); } else { nodes_from_lookup = rr_graph.node_lookup().find_grid_nodes_at_all_sides(l, x, y, rr_type); @@ -1554,12 +1554,12 @@ bool verify_rr_node_indices(const DeviceGrid& grid, if (rr_graph.node_type(inode) != rr_type) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node type does not match between rr_nodes and rr_node_indices (%s/%s): %s", - rr_node_typename[rr_graph.node_type(inode)], - rr_node_typename[rr_type], + rr_node_typename[(size_t)rr_graph.node_type(inode)], + rr_node_typename[(size_t)rr_type], describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } - if (rr_graph.node_type(inode) == CHANX) { + if (rr_graph.node_type(inode) == e_rr_type::CHANX) { VTR_ASSERT_MSG(rr_graph.node_ylow(inode) == rr_graph.node_yhigh(inode), "CHANX should be horizontal"); if (y != rr_graph.node_ylow(inode)) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node y position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", @@ -1575,8 +1575,8 @@ bool verify_rr_node_indices(const DeviceGrid& grid, x, describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } - } else if (rr_graph.node_type(inode) == CHANY) { - VTR_ASSERT_MSG(rr_graph.node_xlow(inode) == rr_graph.node_xhigh(inode), "CHANY should be veritcal"); + } else if (rr_graph.node_type(inode) == e_rr_type::CHANY) { + VTR_ASSERT_MSG(rr_graph.node_xlow(inode) == rr_graph.node_xhigh(inode), "CHANY should be vertical"); if (x != rr_graph.node_xlow(inode)) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node x position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", @@ -1592,7 +1592,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, y, describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } - } else if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK) { + } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { // Sources have co-ordinates covering the entire block they are in, but not sinks if (!rr_graph.x_in_node_range(x, inode)) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", @@ -1610,7 +1610,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } } else { - VTR_ASSERT(rr_graph.node_type(inode) == IPIN || rr_graph.node_type(inode) == OPIN); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::IPIN || rr_graph.node_type(inode) == e_rr_type::OPIN); /* As we allow a pin to be indexable on multiple sides, * This check code should be invalid * if (rr_node.xlow() != x) { @@ -1629,7 +1629,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, */ } - if (rr_type == IPIN || rr_type == OPIN) { + if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { /* As we allow a pin to be indexable on multiple sides, * This check code should be invalid * if (rr_node.side() != side) { @@ -1660,7 +1660,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, auto& rr_node = rr_nodes[size_t(inode)]; - if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK) { + if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { int rr_width = (rr_graph.node_xhigh(rr_node.id()) - rr_graph.node_xlow(rr_node.id()) + 1); int rr_height = (rr_graph.node_yhigh(rr_node.id()) - rr_graph.node_ylow(rr_node.id()) + 1); int rr_area = rr_width * rr_height; @@ -1674,7 +1674,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, /* As we allow a pin to be indexable on multiple sides, * This check code should not be applied to input and output pins */ - } else if ((OPIN != rr_graph.node_type(inode)) && (IPIN != rr_graph.node_type(inode))) { + } else if ((e_rr_type::OPIN != rr_graph.node_type(inode)) && (e_rr_type::IPIN != rr_graph.node_type(inode))) { if (count != rr_node.length() + 1) { VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node length (%d) and count within rr_node_indices (%d, should be length + 1): %s", rr_node.length(), @@ -1720,12 +1720,12 @@ int get_track_to_pins(RRGraphBuilder& rr_graph_builder, if (is_cblock(chan, j, track, seg_details)) { for (pass = 0; pass < 2; ++pass) { //pass == 0 => TOP/RIGHT, pass == 1 => BOTTOM/LEFT e_side side; - if (CHANX == chan_type) { + if (e_rr_type::CHANX == chan_type) { x = j; y = chan + pass; side = (0 == pass ? TOP : BOTTOM); } else { - VTR_ASSERT(CHANY == chan_type); + VTR_ASSERT(e_rr_type::CHANY == chan_type); x = chan + pass; y = j; side = (0 == pass ? RIGHT : LEFT); @@ -1757,7 +1757,7 @@ int get_track_to_pins(RRGraphBuilder& rr_graph_builder, } /* Check there is a connection and Fc map isn't wrong */ - RRNodeId to_node = rr_graph_builder.node_lookup().find_node(layer_index, x, y, IPIN, ipin, side); + RRNodeId to_node = rr_graph_builder.node_lookup().find_node(layer_index, x, y, e_rr_type::IPIN, ipin, side); int switch_type = (layer_index == layer) ? wire_to_ipin_switch : wire_to_pin_between_dice_switch; if (to_node) { rr_edges_to_create.emplace_back(from_rr_node, to_node, switch_type, false); @@ -1840,11 +1840,11 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, int end_sb_seg = get_seg_end(from_seg_details, from_track, from_seg, from_chan, chan_len); /* Figure out the sides of SB the from_wire will use */ - if (CHANX == from_type) { + if (e_rr_type::CHANX == from_type) { from_side_a = RIGHT; from_side_b = LEFT; } else { - VTR_ASSERT(CHANY == from_type); + VTR_ASSERT(e_rr_type::CHANY == from_type); from_side_a = TOP; from_side_b = BOTTOM; } @@ -1899,7 +1899,7 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, /* to_chan_details may correspond to an x-directed or y-directed channel, depending on which * channel type this function is used; so coordinates are reversed as necessary */ - if (to_type == CHANX) { + if (to_type == e_rr_type::CHANX) { to_seg_details = to_chan_details[to_seg][to_chan].data(); } else { to_seg_details = to_chan_details[to_chan][to_seg].data(); @@ -1925,10 +1925,10 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, } /* Figure out which side of the SB the destination segment lies on */ - if (CHANX == to_type) { + if (e_rr_type::CHANX == to_type) { to_side = (is_behind ? RIGHT : LEFT); } else { - VTR_ASSERT(CHANY == to_type); + VTR_ASSERT(e_rr_type::CHANY == to_type); to_side = (is_behind ? TOP : BOTTOM); } @@ -2070,11 +2070,11 @@ static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, short switch_types[2]; /* x, y coords for get_rr_node lookups */ - if (CHANX == to_type) { + if (e_rr_type::CHANX == to_type) { to_x = to_seg; to_y = to_chan; } else { - VTR_ASSERT(CHANY == to_type); + VTR_ASSERT(e_rr_type::CHANY == to_type); to_x = to_chan; to_y = to_seg; } @@ -2198,8 +2198,8 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder, * * */ int offset = num_of_3d_conns_custom_SB[tile_x][tile_y] / custom_3d_sb_fanin_fanout; - RRNodeId track_to_chanx_node = rr_graph_builder.node_lookup().find_node(layer, tile_x, tile_y, CHANX, max_chan_width + offset); - RRNodeId diff_layer_chanx_node = rr_graph_builder.node_lookup().find_node(to_layer, tile_x, tile_y, CHANX, max_chan_width + offset); + RRNodeId track_to_chanx_node = rr_graph_builder.node_lookup().find_node(layer, tile_x, tile_y, e_rr_type::CHANX, max_chan_width + offset); + RRNodeId diff_layer_chanx_node = rr_graph_builder.node_lookup().find_node(to_layer, tile_x, tile_y, e_rr_type::CHANX, max_chan_width + offset); RRNodeId chanx_to_track_node = rr_graph_builder.node_lookup().find_node(to_layer, to_x, to_y, to_chan_type, to_wire); if (!track_to_chanx_node || !diff_layer_chanx_node || !chanx_to_track_node) { @@ -2254,14 +2254,14 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, int tile_x, tile_y; /* get x/y coordinates from seg/chan coordinates */ - if (CHANX == to_chan_type) { + if (e_rr_type::CHANX == to_chan_type) { to_x = tile_x = to_seg; to_y = tile_y = to_chan; if (RIGHT == to_side) { tile_x--; } } else { - VTR_ASSERT(CHANY == to_chan_type); + VTR_ASSERT(e_rr_type::CHANY == to_chan_type); to_x = tile_x = to_chan; to_y = tile_y = to_seg; if (TOP == to_side) { @@ -2338,11 +2338,11 @@ static int get_unidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, std::vector mux_labels; /* x, y coords for get_rr_node lookups */ - int to_x = (CHANX == to_type ? to_seg : to_chan); - int to_y = (CHANX == to_type ? to_chan : to_seg); - int sb_x = (CHANX == to_type ? to_sb : to_chan); - int sb_y = (CHANX == to_type ? to_chan : to_sb); - int max_len = (CHANX == to_type ? grid.width() : grid.height()) - 2; //-2 for no perimeter channels + int to_x = (e_rr_type::CHANX == to_type ? to_seg : to_chan); + int to_y = (e_rr_type::CHANX == to_type ? to_chan : to_seg); + int sb_x = (e_rr_type::CHANX == to_type ? to_sb : to_chan); + int sb_y = (e_rr_type::CHANX == to_type ? to_chan : to_sb); + int max_len = (e_rr_type::CHANX == to_type ? grid.width() : grid.height()) - 2; //-2 for no perimeter channels enum Direction to_dir = Direction::DEC; if (to_sb < to_seg) { @@ -3003,11 +3003,11 @@ static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int //Convert the chan/seg indices to real x/y coordinates int y_coord; int x_coord; - if (from_chan_type == CHANX) { + if (from_chan_type == e_rr_type::CHANX) { y_coord = from_chan_coord; x_coord = from_seg_coord; } else { - VTR_ASSERT(from_chan_type == CHANY); + VTR_ASSERT(from_chan_type == e_rr_type::CHANY); y_coord = from_seg_coord; x_coord = from_chan_coord; } @@ -3025,9 +3025,9 @@ static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int return switch_override; } else if (sb_type == e_sb_type::TURNS && from_chan_type != to_chan_type) { return switch_override; - } else if (sb_type == e_sb_type::HORIZONTAL && from_chan_type == CHANX && to_chan_type == CHANX) { + } else if (sb_type == e_sb_type::HORIZONTAL && from_chan_type == e_rr_type::CHANX && to_chan_type == e_rr_type::CHANX) { return switch_override; - } else if (sb_type == e_sb_type::VERTICAL && from_chan_type == CHANY && to_chan_type == CHANY) { + } else if (sb_type == e_sb_type::VERTICAL && from_chan_type == e_rr_type::CHANY && to_chan_type == e_rr_type::CHANY) { return switch_override; } diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp index 110f056c906..ed5a8f351cc 100644 --- a/vpr/src/route/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_area.cpp @@ -175,8 +175,8 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl from_rr_type = rr_graph.node_type(from_rr_node); switch (from_rr_type) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: num_edges = rr_graph.num_edges(RRNodeId(from_node)); for (iedge = 0; iedge < num_edges; iedge++) { @@ -189,8 +189,8 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl } switch (to_rr_type) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: iswitch = rr_graph.edge_switch(RRNodeId(from_node), iedge); if (rr_graph.rr_switch_inf(RRSwitchId(iswitch)).buffered()) { @@ -210,7 +210,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl } break; - case IPIN: + case e_rr_type::IPIN: num_inputs_to_cblock[size_t(to_node)]++; max_inputs_to_cblock = std::max(max_inputs_to_cblock, num_inputs_to_cblock[size_t(to_node)]); @@ -228,7 +228,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl VPR_ERROR(VPR_ERROR_ROUTE, "in count_routing_transistors:\n" "\tUnexpected connection from node %d (type %s) to node %d (type %s).\n", - from_node, rr_node_typename[from_rr_type], size_t(to_node), rr_node_typename[to_rr_type]); + from_node, rr_node_typename[(size_t)from_rr_type], size_t(to_node), rr_node_typename[(size_t)to_rr_type]); break; } /* End switch on to_rr_type. */ @@ -237,7 +237,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl /* Now add in the shared buffer transistors, and reset some flags. */ - if (from_rr_type == CHANX) { + if (from_rr_type == e_rr_type::CHANX) { for (i = rr_graph.node_xlow(from_rr_node) - 1; i <= rr_graph.node_xhigh(from_rr_node); i++) { ntrans_sharing += shared_buffer_trans[i]; @@ -261,7 +261,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl } break; - case OPIN: + case e_rr_type::OPIN: num_edges = rr_graph.num_edges(RRNodeId(from_node)); shared_opin_buffer_trans = 0.; @@ -377,8 +377,8 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* from_rr_type = rr_graph.node_type(from_rr_node); switch (from_rr_type) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: num_edges = rr_graph.num_edges(RRNodeId(from_node)); /* Increment number of inputs per cblock if IPIN */ @@ -392,8 +392,8 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* } switch (to_rr_type) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: if (!chan_node_switch_done[size_t(to_node)]) { int switch_index = rr_graph.edge_switch(RRNodeId(from_node), iedge); auto switch_type = rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type(); @@ -434,7 +434,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* break; - case IPIN: + case e_rr_type::IPIN: num_inputs_to_cblock[size_t(to_node)]++; max_inputs_to_cblock = std::max(max_inputs_to_cblock, num_inputs_to_cblock[size_t(to_node)]); @@ -446,7 +446,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* } break; - case SINK: + case e_rr_type::SINK: break; //ignore virtual sinks default: @@ -461,7 +461,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* } /* End for each edge. */ /* Reset some flags */ - if (from_rr_type == CHANX) { + if (from_rr_type == e_rr_type::CHANX) { for (i = rr_graph.node_xlow(from_rr_node); i <= rr_graph.node_xhigh(from_rr_node); i++) cblock_counted[i] = false; @@ -471,7 +471,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* cblock_counted[j] = false; } break; - case OPIN: + case e_rr_type::OPIN: break; default: diff --git a/vpr/src/route/rr_graph_timing_params.cpp b/vpr/src/route/rr_graph_timing_params.cpp index d2c478dffe6..754848fae74 100644 --- a/vpr/src/route/rr_graph_timing_params.cpp +++ b/vpr/src/route/rr_graph_timing_params.cpp @@ -53,12 +53,12 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { from_rr_type = rr_graph.node_type(rr_id); - if ((from_rr_type == CHANX || from_rr_type == CHANY)) { + if ((from_rr_type == t_rr_type::CHANX || from_rr_type == t_rr_type::CHANY)) { for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) { to_node = size_t(rr_graph.edge_sink_node(rr_id, iedge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type == CHANX || to_rr_type == CHANY) { + if (to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY) { switch_index = rr_graph.edge_switch(rr_id, iedge); Cin = rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cin; Cout = rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cout; @@ -99,7 +99,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { } /* End edge to CHANX or CHANY node. */ - else if (to_rr_type == IPIN) { + else if (to_rr_type == t_rr_type::IPIN) { if (INCLUDE_TRACK_BUFFERS) { /* Implements sharing of the track to connection box buffer. * Such a buffer exists at every segment of the wire at which @@ -129,7 +129,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { * } * } */ - if (from_rr_type == CHANX) { + if (from_rr_type == t_rr_type::CHANX) { iseg_low = rr_graph.node_xlow(rr_id); iseg_high = rr_graph.node_xhigh(rr_id); } else { /* CHANY */ @@ -148,13 +148,13 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { } /* End node is CHANX or CHANY */ - else if (from_rr_type == OPIN) { + else if (from_rr_type == t_rr_type::OPIN) { for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) { switch_index = rr_graph.edge_switch(rr_id, iedge); to_node = size_t(rr_graph.edge_sink_node(rr_id, iedge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type != CHANX && to_rr_type != CHANY) + if (to_rr_type != t_rr_type::CHANX && to_rr_type != t_rr_type::CHANY) continue; if (rr_graph.node_direction(RRNodeId(to_node)) == Direction::BIDIR) { @@ -179,7 +179,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { switch_index = rr_graph.edge_switch(inode, iedge); to_node = size_t(rr_graph.edge_sink_node(inode, iedge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type == CHANX || to_rr_type == CHANY) { + if (to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY) { if (rr_graph.node_direction(RRNodeId(to_node)) != Direction::BIDIR) { /* Cout was not added in these cases */ Couts_to_add[to_node] = std::max(Couts_to_add[to_node], rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cout); diff --git a/vpr/src/route/segment_stats.cpp b/vpr/src/route/segment_stats.cpp index f05e0874cdb..3d7de733ce3 100644 --- a/vpr/src/route/segment_stats.cpp +++ b/vpr/src/route/segment_stats.cpp @@ -1,4 +1,3 @@ -#include #include "vtr_log.h" #include "vtr_memory.h" @@ -60,14 +59,14 @@ void get_segment_usage_stats(std::vector& segment_inf) { for (RRNodeId inode : device_ctx.rr_graph.nodes()) { auto node_type = rr_graph.node_type(inode); - if (node_type == CHANX || node_type == CHANY) { + if (node_type == e_rr_type::CHANX || node_type == e_rr_type::CHANY) { cost_index = rr_graph.node_cost_index(inode); size_t seg_type = device_ctx.rr_indexed_data[cost_index].seg_index; int length = segment_inf[seg_type].longline ? LONGLINE : segment_inf[seg_type].length; const short& inode_capacity = rr_graph.node_capacity(inode); int occ = route_ctx.rr_node_route_inf[inode].occ(); - auto ax = (node_type == CHANX) ? X_AXIS : Y_AXIS; + auto ax = (node_type == e_rr_type::CHANX) ? X_AXIS : Y_AXIS; directed_occ_by_length[ax][length] += occ; directed_cap_by_length[ax][length] += inode_capacity; diff --git a/vpr/src/timing/VprTimingGraphResolver.cpp b/vpr/src/timing/VprTimingGraphResolver.cpp index 791615e5585..81fbef6db39 100644 --- a/vpr/src/timing/VprTimingGraphResolver.cpp +++ b/vpr/src/timing/VprTimingGraphResolver.cpp @@ -342,11 +342,11 @@ void VprTimingGraphResolver::get_detailed_interconnect_components_helper(std::ve // Process the current interconnect component if it is of type OPIN, CHANX, CHANY, IPIN // Only process SOURCE, SINK in debug report mode auto rr_type = rr_graph.node_type(RRNodeId(current_node->inode)); - if (rr_type == OPIN - || rr_type == IPIN - || rr_type == CHANX - || rr_type == CHANY - || ((rr_type == SOURCE || rr_type == SINK) && (detail_level() == e_timing_report_detail::DEBUG))) { + if (rr_type == t_rr_type::OPIN + || rr_type == t_rr_type::IPIN + || rr_type == t_rr_type::CHANX + || rr_type == t_rr_type::CHANY + || ((rr_type == t_rr_type::SOURCE || rr_type == t_rr_type::SINK) && (detail_level() == e_timing_report_detail::DEBUG))) { tatum::DelayComponent net_component; // declare a new instance of DelayComponent net_component.type_name = rr_graph.node_coordinate_to_string(RRNodeId(current_node->inode)); diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 853725c5bb9..f86a56328a6 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -93,13 +93,13 @@ std::string rr_node_arch_name(RRNodeId inode, bool is_flat) { auto rr_node = inode; std::string rr_node_arch_name; - if (rr_graph.node_type(inode) == OPIN || rr_graph.node_type(inode) == IPIN) { + if (rr_graph.node_type(inode) == e_rr_type::OPIN || rr_graph.node_type(inode) == e_rr_type::IPIN) { //Pin names auto type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), rr_graph.node_layer(rr_node)}); rr_node_arch_name += block_type_pin_index_to_name(type, rr_graph.node_pin_num(rr_node), is_flat); - } else if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK) { + } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { //Set of pins associated with SOURCE/SINK auto type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), @@ -115,7 +115,7 @@ std::string rr_node_arch_name(RRNodeId inode, bool is_flat) { rr_node_arch_name += pin_names[0]; } } else { - VTR_ASSERT(rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANX || rr_graph.node_type(inode) == e_rr_type::CHANY); //Wire segment name auto cost_index = rr_graph.node_cost_index(inode); int seg_index = device_ctx.rr_indexed_data[cost_index].seg_index; @@ -1737,7 +1737,7 @@ std::vector get_all_pb_graph_node_primitives(const t_pb_ bool is_inter_cluster_node(const RRGraphView& rr_graph_view, RRNodeId node_id) { auto node_type = rr_graph_view.node_type(node_id); - if (node_type == CHANX || node_type == CHANY) { + if (node_type == e_rr_type::CHANX || node_type == e_rr_type::CHANY) { return true; } else { int x_low = rr_graph_view.node_xlow(node_id); @@ -1745,10 +1745,10 @@ bool is_inter_cluster_node(const RRGraphView& rr_graph_view, int layer = rr_graph_view.node_layer(node_id); int node_ptc = rr_graph_view.node_ptc_num(node_id); const t_physical_tile_type_ptr physical_tile = g_vpr_ctx.device().grid.get_physical_type({x_low, y_low, layer}); - if (node_type == IPIN || node_type == OPIN) { + if (node_type == e_rr_type::IPIN || node_type == e_rr_type::OPIN) { return is_pin_on_tile(physical_tile, node_ptc); } else { - VTR_ASSERT_DEBUG(node_type == SINK || node_type == SOURCE); + VTR_ASSERT_DEBUG(node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE); return is_class_on_tile(physical_tile, node_ptc); } } @@ -1759,14 +1759,14 @@ int get_rr_node_max_ptc(const RRGraphView& rr_graph_view, bool is_flat) { auto node_type = rr_graph_view.node_type(node_id); - VTR_ASSERT(node_type == IPIN || node_type == OPIN || node_type == SINK || node_type == SOURCE); + VTR_ASSERT(node_type == e_rr_type::IPIN || node_type == e_rr_type::OPIN || node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE); const DeviceContext& device_ctx = g_vpr_ctx.device(); auto physical_type = device_ctx.grid.get_physical_type({rr_graph_view.node_xlow(node_id), rr_graph_view.node_ylow(node_id), rr_graph_view.node_layer(node_id)}); - if (node_type == SINK || node_type == SOURCE) { + if (node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE) { return get_tile_class_max_ptc(physical_type, is_flat); } else { return get_tile_pin_max_ptc(physical_type, is_flat); @@ -1850,18 +1850,18 @@ bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node) { const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - VTR_ASSERT(rr_graph.node_type(src_rr_node) == SOURCE && rr_graph.node_type(sink_rr_node) == SINK); + VTR_ASSERT(rr_graph.node_type(src_rr_node) == e_rr_type::SOURCE && rr_graph.node_type(sink_rr_node) == e_rr_type::SINK); // A direct connection is defined as a specific path: `SOURCE -> OPIN -> IPIN -> SINK`. //TODO: This is a constant depth search, but still may be too slow for (t_edge_size i_src_edge = 0; i_src_edge < rr_graph.num_edges(src_rr_node); ++i_src_edge) { RRNodeId opin_rr_node = rr_graph.edge_sink_node(src_rr_node, i_src_edge); - if (rr_graph.node_type(opin_rr_node) != OPIN) continue; + if (rr_graph.node_type(opin_rr_node) != e_rr_type::OPIN) continue; for (t_edge_size i_opin_edge = 0; i_opin_edge < rr_graph.num_edges(opin_rr_node); ++i_opin_edge) { RRNodeId ipin_rr_node = rr_graph.edge_sink_node(opin_rr_node, i_opin_edge); - if (rr_graph.node_type(ipin_rr_node) != IPIN) continue; + if (rr_graph.node_type(ipin_rr_node) != e_rr_type::IPIN) continue; for (t_edge_size i_ipin_edge = 0; i_ipin_edge < rr_graph.num_edges(ipin_rr_node); ++i_ipin_edge) { if (sink_rr_node == rr_graph.edge_sink_node(ipin_rr_node, i_ipin_edge)) { diff --git a/vpr/test/test_vpr.cpp b/vpr/test/test_vpr.cpp index c05d33e54f9..99651bfe5cd 100644 --- a/vpr/test/test_vpr.cpp +++ b/vpr/test/test_vpr.cpp @@ -142,7 +142,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { - if ((rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) && rr_graph.num_edges(inode) > 0) { + if ((rr_graph.node_type(inode) == e_rr_type::CHANX || rr_graph.node_type(inode) == e_rr_type::CHANY) && rr_graph.num_edges(inode) > 0) { src_inode = size_t(inode); break; } @@ -267,7 +267,7 @@ TEST_CASE("read_rr_edge_override", "[vpr]") { const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); for (const RRNodeId inode : device_ctx.rr_graph.nodes()) { - if ((rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) && rr_graph.num_edges(inode) > 0) { + if ((rr_graph.node_type(inode) == e_rr_type::CHANX || rr_graph.node_type(inode) == e_rr_type::CHANY) && rr_graph.num_edges(inode) > 0) { src_inode = inode; break; } From 46d6c2c4663da400f956c0b19f98076c301c19da Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Fri, 25 Apr 2025 01:03:05 -0400 Subject: [PATCH 028/176] [Router] Finally fixed the weird bug in parallel connection router Fixed the weird bug in parallel connection router as mentioned in commit f73212c. The bug occurred because two function parameters 'num_threads' and 'num_queues' have been misplaced when instantiating the MQ_IO. This took two weeks to figure out exactly. The VTR benchmark (`vtr_reg_qor_chain` task) has been tested/passed for different cases (1) 'serial mode' 1T+2Q (1 thread, 2 queues), (2) 2T+4Q, and (3) 4T+2Q. The determinism has also been verified for the VTR benchmark. --- vpr/src/route/multi_queue_d_ary_heap.h | 5 +++-- vpr/src/route/parallel_connection_router.h | 8 ++------ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h index 8df6cacb5ac..8b559580559 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.h +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -41,7 +41,7 @@ class MultiQueueDAryHeap { using MQ_IO = MultiQueueIO; MultiQueueDAryHeap() { - set_num_threads_and_queues(2, 1); // Serial (#threads=1, #queues=2) by default + set_num_threads_and_queues(1, 2); // Serial (#threads=1, #queues=2) by default } MultiQueueDAryHeap(size_t num_threads, size_t num_queues) { @@ -52,7 +52,8 @@ class MultiQueueDAryHeap { void set_num_threads_and_queues(size_t num_threads, size_t num_queues) { pq_.reset(); - pq_ = std::make_unique(num_threads, num_queues, 0 /*Dont care (batch size for only popBatch)*/); + // Note: BE AWARE that in MQ_IO interface, `num_queues` comes first, then `num_threads`! + pq_ = std::make_unique(num_queues, num_threads, 0 /*Dont care (batch size for only popBatch)*/); } void init_heap(const DeviceGrid& grid) { diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h index 45a469be24f..18d873e0c6e 100644 --- a/vpr/src/route/parallel_connection_router.h +++ b/vpr/src/route/parallel_connection_router.h @@ -207,13 +207,9 @@ class ParallelConnectionRouter : public ConnectionRoutermodified_rr_node_inf_) { - for (const auto node : thread_visited_rr_nodes) { - route_ctx.rr_node_route_inf[node].path_cost = std::numeric_limits::infinity(); - route_ctx.rr_node_route_inf[node].backward_path_cost = std::numeric_limits::infinity(); - route_ctx.rr_node_route_inf[node].prev_edge = RREdgeId::INVALID(); - } + ::reset_path_costs(thread_visited_rr_nodes); } } From cdda01bb52568382344c1827470865a9f996e970 Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Fri, 25 Apr 2025 02:29:57 -0400 Subject: [PATCH 029/176] [Router] Fixed Code Review Comments and Cleanup Codebase Added more explanation to the command-line options messages and code comments. Cleaned up ParallelConnectionRouter-related codebase. --- doc/src/vpr/command_line_usage.rst | 10 ++++++++-- utils/route_diag/src/main.cpp | 1 - vpr/src/route/NestedNetlistRouter.h | 12 ++++++------ vpr/src/route/NestedNetlistRouter.tpp | 2 +- vpr/src/route/multi_queue_d_ary_heap.h | 16 +++++++++------- vpr/src/route/parallel_connection_router.cpp | 6 +++--- 6 files changed, 27 insertions(+), 20 deletions(-) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index ab67fd1de0b..35be3118b40 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1576,8 +1576,14 @@ The following options are only valid when the router is in timing-driven mode (t Controls whether to enable queue draining optimization for MultiQueue-based parallel connection router. - When enabled, queues can be emptied quickly by draining all elements if no further solutions need to be explored in the - path search to guarantee optimality or determinism after reaching the target. + When enabled, queues can be emptied quickly by draining all elements if no further solutions need to be explored after + the target is reached in the path search. + + Note: For this optimization to maintain optimality and deterministic results, the 'ordering heuristic' (calculated by + :option:`--astar_fac` and :option:`--astar_offset`) must be admissible to ensure emptying queues of entries with higher + costs does not prune possibly superior solutions. However, you can still enable this optimization regardless of whether + optimality and determinism are required for your specific use case (in such cases, the 'ordering heuristic' can be + inadmissible). This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index 1fd0323ea2e..7d4edbe603a 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -97,7 +97,6 @@ static void do_one_route(const Netlist<>& net_list, segment_inf, is_flat); - // TODO: adding tests for parallel connection router SerialConnectionRouter router( device_ctx.grid, *router_lookahead, diff --git a/vpr/src/route/NestedNetlistRouter.h b/vpr/src/route/NestedNetlistRouter.h index 9aa2a675e62..e776d0a42da 100644 --- a/vpr/src/route/NestedNetlistRouter.h +++ b/vpr/src/route/NestedNetlistRouter.h @@ -70,7 +70,7 @@ class NestedNetlistRouter : public NetlistRouter { /** Route all nets in a PartitionTree node and add its children to the task queue. */ void route_partition_tree_node(PartitionTreeNode& node); - std::shared_ptr _make_router(const RouterLookahead* router_lookahead, + std::unique_ptr _make_router(const RouterLookahead* router_lookahead, const t_router_opts& router_opts, bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); @@ -78,7 +78,7 @@ class NestedNetlistRouter : public NetlistRouter { if (!router_opts.enable_parallel_connection_router) { // Serial Connection Router - return std::make_shared>( + return std::make_unique>( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -89,7 +89,7 @@ class NestedNetlistRouter : public NetlistRouter { is_flat); } else { // Parallel Connection Router - return std::make_shared>( + return std::make_unique>( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -131,19 +131,19 @@ class NestedNetlistRouter : public NetlistRouter { /* Thread-local storage. * These are maps because thread::id is a random integer instead of 1, 2, ... */ - std::unordered_map> _routers_th; + std::unordered_map> _routers_th; std::unordered_map _results_th; std::mutex _storage_mutex; /** Get a thread-local ConnectionRouter. We lock the id->router lookup, but this is * accessed once per partition so the overhead should be small */ - std::shared_ptr get_thread_router() { + ConnectionRouterInterface& get_thread_router() { auto id = std::this_thread::get_id(); std::lock_guard lock(_storage_mutex); if (!_routers_th.count(id)) { _routers_th.emplace(id, _make_router(_router_lookahead, _router_opts, _is_flat)); } - return _routers_th.at(id); + return *_routers_th.at(id); } RouteIterResults& get_thread_results() { diff --git a/vpr/src/route/NestedNetlistRouter.tpp b/vpr/src/route/NestedNetlistRouter.tpp index 9a7aa91a3f3..ec4b1fe0aa6 100644 --- a/vpr/src/route/NestedNetlistRouter.tpp +++ b/vpr/src/route/NestedNetlistRouter.tpp @@ -68,7 +68,7 @@ void NestedNetlistRouter::route_partition_tree_node(PartitionTreeNode& auto& results = get_thread_results(); auto flags = route_net( - *get_thread_router(), + get_thread_router(), _net_list, net_id, _itry, diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h index 8b559580559..5a49dadae50 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.h +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -26,10 +26,12 @@ #include #include -using MQHeapNode = std::tuple; +// FIXME: Use unified heap node struct (HeapNodeId) and comparator (HeapNodeComparator) +// defined in heap_type.h. Currently, the MQ_IO is not compatible with them. Need a lot +// of refactoring in MQ_IO to make it work, which is left for another PR to clean it up. +using MQHeapNode = std::tuple; -// FIXME: use unified heap node struct and comparator in heap_type.h -struct MQHeapNodeTupleComparator { +struct MQHeapNodeTupleComparator /* FIXME: Use HeapNodeComparator */ { bool operator()(const MQHeapNode& u, const MQHeapNode& v) { return std::get<0>(u) > std::get<0>(v); } @@ -102,15 +104,15 @@ class MultiQueueDAryHeap { return (bool)(pq_->empty()); } - uint64_t getNumPushes() const { + uint64_t get_num_pushes() const { return pq_->getNumPushes(); } - uint64_t getNumPops() const { + uint64_t get_num_pops() const { return pq_->getNumPops(); } - uint64_t getHeapOccupancy() const { + uint64_t get_heap_occupancy() const { return pq_->getQueueOccupancy(); } @@ -119,7 +121,7 @@ class MultiQueueDAryHeap { } #ifdef MQ_IO_ENABLE_CLEAR_FOR_POP - void setMinPrioForPop(const HeapNodePriority& minPrio) { + void set_min_priority_for_pop(const HeapNodePriority& minPrio) { pq_->setMinPrioForPop(minPrio); } #endif diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp index c0d6db96547..59889204c23 100644 --- a/vpr/src/route/parallel_connection_router.cpp +++ b/vpr/src/route/parallel_connection_router.cpp @@ -181,8 +181,8 @@ void ParallelConnectionRouter::timing_driven_find_single_shortest_path_fro this->thread_barrier_.wait(); // Collect the number of heap pushes and pops - this->router_stats_->heap_pushes += this->heap_.getNumPushes(); - this->router_stats_->heap_pops += this->heap_.getNumPops(); + this->router_stats_->heap_pushes += this->heap_.get_num_pushes(); + this->router_stats_->heap_pops += this->heap_.get_num_pops(); // Reset the heap for the next connection this->heap_.reset(); @@ -394,7 +394,7 @@ void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost if (to_node == target_node) { #ifdef MQ_IO_ENABLE_CLEAR_FOR_POP if (multi_queue_direct_draining_) { - this->heap_.setMinPrioForPop(new_total_cost); + this->heap_.set_min_priority_for_pop(new_total_cost); } #endif return; From 7cdf4334d799f50e8a13093e22ac0d58701a9ff1 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Fri, 25 Apr 2025 06:59:12 -0700 Subject: [PATCH 030/176] [doc] clarify that clang-format is not required to build VPR --- doc/src/quickstart/index.rst | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/doc/src/quickstart/index.rst b/doc/src/quickstart/index.rst index c2dd8512824..f69eb39b077 100644 --- a/doc/src/quickstart/index.rst +++ b/doc/src/quickstart/index.rst @@ -24,15 +24,9 @@ If you cloned the repository, you will need to set up the git submodules (if you > git submodule init > git submodule update -VTR requires several system and Python packages to build and run the flow. -Ubuntu users can install the required system packages using the provided script or -the command below. This setup works on Ubuntu 18.04, 20.04, 22.04, and 24.04, but note -that some packages (such as ``clang-format-18``) are only available by default on Ubuntu 24.04. -On older versions, this package will not be installed unless you manually add the appropriate -LLVM APT repository. - -To install ``clang-format-18`` on older Ubuntu versions (e.g., 20.04 or 22.04), you must add the -LLVM repository manually: +VTR requires several system and Python packages to build and run the flow. Ubuntu users can install the required system packages using the provided script or the command below. This setup works on Ubuntu 18.04, 20.04, 22.04, and 24.04, but note that some packages (such as ``clang-format-18``) are only available by default on Ubuntu 24.04. On older versions, this package will not be installed unless you manually add the appropriate LLVM APT repository. + +To install ``clang-format-18`` on older Ubuntu versions (e.g., 20.04 or 22.04), you must add the LLVM repository manually. Note that this tool is only required if you want to run ``make format`` to automatically fix formatting issues in the code. It is not necessary for building or running VPR. .. code-block:: bash From 161f605833889bab4530fa310866b825ff4b0ceb Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 12:40:55 -0400 Subject: [PATCH 031/176] remove typedef t_rr_type --- libs/librrgraph/src/base/check_rr_graph.cpp | 78 +++++++-------- .../src/base/check_rr_graph_obj.cpp | 4 +- libs/librrgraph/src/base/rr_graph_builder.cpp | 14 +-- libs/librrgraph/src/base/rr_graph_builder.h | 2 +- libs/librrgraph/src/base/rr_graph_obj.cpp | 8 +- libs/librrgraph/src/base/rr_graph_obj.h | 14 +-- libs/librrgraph/src/base/rr_graph_storage.cpp | 8 +- libs/librrgraph/src/base/rr_graph_storage.h | 8 +- libs/librrgraph/src/base/rr_graph_utils.cpp | 24 ++--- libs/librrgraph/src/base/rr_graph_utils.h | 2 +- libs/librrgraph/src/base/rr_graph_view.h | 4 +- libs/librrgraph/src/base/rr_node_types.h | 10 +- .../librrgraph/src/base/rr_spatial_lookup.cpp | 24 ++--- libs/librrgraph/src/base/rr_spatial_lookup.h | 22 ++--- .../src/io/rr_graph_uxsdcxx_serializer.h | 6 +- .../utils/alloc_and_load_rr_indexed_data.cpp | 6 +- vpr/src/base/read_route.cpp | 2 +- vpr/src/base/stats.cpp | 16 ++-- vpr/src/base/vpr_types.h | 6 +- vpr/src/draw/draw.cpp | 6 +- vpr/src/draw/draw_basic.cpp | 38 ++++---- vpr/src/draw/draw_rr.cpp | 96 +++++++++---------- vpr/src/draw/draw_rr_edges.cpp | 2 +- vpr/src/pack/post_routing_pb_pin_fixup.cpp | 2 +- .../pack/sync_netlists_to_routing_flat.cpp | 8 +- .../compute_delta_delays_utils.cpp | 6 +- vpr/src/route/annotate_routing.cpp | 4 +- vpr/src/route/build_switchblocks.cpp | 18 ++-- vpr/src/route/check_route.cpp | 52 +++++----- vpr/src/route/connection_router.cpp | 20 ++-- vpr/src/route/overuse_report.cpp | 16 ++-- vpr/src/route/route.cpp | 2 +- vpr/src/route/route_common.cpp | 4 +- vpr/src/route/route_net.cpp | 2 +- vpr/src/route/route_profiling.cpp | 4 +- vpr/src/route/route_utilization.cpp | 4 +- vpr/src/route/route_utilization.h | 4 +- vpr/src/route/router_lookahead.cpp | 4 +- .../route/router_lookahead_compressed_map.cpp | 28 +++--- .../route/router_lookahead_extended_map.cpp | 2 +- vpr/src/route/router_lookahead_map.cpp | 8 +- vpr/src/route/router_lookahead_map_utils.cpp | 4 +- vpr/src/route/router_lookahead_map_utils.h | 2 +- vpr/src/route/router_stats.h | 12 +-- vpr/src/route/rr_graph.cpp | 50 +++++----- vpr/src/route/rr_graph2.cpp | 36 +++---- vpr/src/route/rr_graph2.h | 6 +- vpr/src/route/rr_graph_area.cpp | 4 +- vpr/src/route/rr_graph_sbox.h | 4 +- vpr/src/route/rr_graph_timing_params.cpp | 16 ++-- vpr/src/timing/VprTimingGraphResolver.cpp | 10 +- vpr/src/util/vpr_utils.cpp | 12 +-- 52 files changed, 372 insertions(+), 372 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index f74995aeff9..72ab0966645 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -80,7 +80,7 @@ void check_rr_graph(const RRGraphView& rr_graph, continue; } - t_rr_type rr_type = rr_graph.node_type(rr_node); + e_rr_type rr_type = rr_graph.node_type(rr_node); int num_edges = rr_graph.num_edges(RRNodeId(inode)); check_rr_node(rr_graph, rr_indexed_data, grid, chan_width, route_type, inode, is_flat); @@ -137,7 +137,7 @@ void check_rr_graph(const RRGraphView& rr_graph, VTR_ASSERT_MSG(num_edges_to_node > 1, "Expect multiple edges"); - t_rr_type to_rr_type = rr_graph.node_type(RRNodeId(to_node)); + e_rr_type to_rr_type = rr_graph.node_type(RRNodeId(to_node)); /* It is unusual to have more than one programmable switch (in the same direction) between a from_node and a to_node, * as the duplicate switch doesn't add more routing flexibility. @@ -154,12 +154,12 @@ void check_rr_graph(const RRGraphView& rr_graph, * - CHAN -> IPIN connections (unique rr_node for IPIN nodes on multiple sides) * - OPIN -> CHAN connections (unique rr_node for OPIN nodes on multiple sides) */ - bool is_chan_to_chan = (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY) && (to_rr_type == t_rr_type::CHANY || to_rr_type == t_rr_type::CHANX); - bool is_chan_to_ipin = (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY) && to_rr_type == t_rr_type::IPIN; - bool is_opin_to_chan = rr_type == t_rr_type::OPIN && (to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY); + bool is_chan_to_chan = (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) && (to_rr_type == e_rr_type::CHANY || to_rr_type == e_rr_type::CHANX); + bool is_chan_to_ipin = (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) && to_rr_type == e_rr_type::IPIN; + bool is_opin_to_chan = rr_type == e_rr_type::OPIN && (to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY); bool is_internal_edge = false; if (is_flat) { - is_internal_edge = (rr_type == t_rr_type::IPIN && to_rr_type == t_rr_type::IPIN) || (rr_type == t_rr_type::OPIN && to_rr_type == t_rr_type::OPIN); + is_internal_edge = (rr_type == e_rr_type::IPIN && to_rr_type == e_rr_type::IPIN) || (rr_type == e_rr_type::OPIN && to_rr_type == e_rr_type::OPIN); } if (!(is_chan_to_chan || is_chan_to_ipin || is_opin_to_chan || is_internal_edge)) { VPR_ERROR(VPR_ERROR_ROUTE, @@ -168,8 +168,8 @@ void check_rr_graph(const RRGraphView& rr_graph, } //Between two wire segments - VTR_ASSERT_MSG(to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY || to_rr_type == t_rr_type::IPIN, "Expect channel type or input pin type"); - VTR_ASSERT_MSG(rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY || rr_type == t_rr_type::OPIN, "Expect channel type or output pin type"); + VTR_ASSERT_MSG(to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY || to_rr_type == e_rr_type::IPIN, "Expect channel type or input pin type"); + VTR_ASSERT_MSG(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY || rr_type == e_rr_type::OPIN, "Expect channel type or output pin type"); //While multiple connections between the same wires can be electrically legal, //they are redundant if they are of the same switch type. @@ -190,8 +190,8 @@ void check_rr_graph(const RRGraphView& rr_graph, /* Redundant edges are not allowed for chan <-> chan connections * but allowed for input pin <-> chan or output pin <-> chan connections */ - if ((to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY) - && (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY)) { + if ((to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY) + && (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY)) { auto switch_type = rr_graph.rr_switch_inf(RRSwitchId(kv.first)).type(); VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)", @@ -232,7 +232,7 @@ void check_rr_graph(const RRGraphView& rr_graph, for (const RRNodeId& rr_node : rr_graph.nodes()) { size_t inode = (size_t)rr_node; - t_rr_type rr_type = rr_graph.node_type(rr_node); + e_rr_type rr_type = rr_graph.node_type(rr_node); int ptc_num = rr_graph.node_ptc_num(rr_node); int layer_num = rr_graph.node_layer(rr_node); int xlow = rr_graph.node_xlow(rr_node); @@ -240,7 +240,7 @@ void check_rr_graph(const RRGraphView& rr_graph, t_physical_tile_type_ptr type = grid.get_physical_type({xlow, ylow, layer_num}); - if (rr_type == t_rr_type::IPIN || rr_type == t_rr_type::OPIN) { + if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { // #TODO: No edges are added for internal pins. However, they need to be checked somehow! if (ptc_num >= type->num_pins) { VTR_LOG_ERROR("in check_rr_graph: node %d (%s) type: %s is internal node.\n", @@ -248,14 +248,14 @@ void check_rr_graph(const RRGraphView& rr_graph, } } - if (rr_type != t_rr_type::SOURCE) { + if (rr_type != e_rr_type::SOURCE) { if (total_edges_to_node[inode] < 1 && !rr_node_is_global_clb_ipin(rr_graph, grid, rr_node)) { /* A global CLB input pin will not have any edges, and neither will * * a SOURCE or the start of a carry-chain. Anything else is an error. * For simplicity, carry-chain input pin are entirely ignored in this test */ bool is_chain = false; - if (rr_type == t_rr_type::IPIN) { + if (rr_type == e_rr_type::IPIN) { for (const t_fc_specification& fc_spec : types[type->index].fc_specs) { if (fc_spec.fc_value == 0 && fc_spec.seg_index == 0) { is_chain = true; @@ -269,11 +269,11 @@ void check_rr_graph(const RRGraphView& rr_graph, || (rr_graph.node_ylow(rr_node) == 1) || (rr_graph.node_xhigh(rr_node) == int(grid.width()) - 2) || (rr_graph.node_yhigh(rr_node) == int(grid.height()) - 2)); - bool is_wire = (rr_graph.node_type(rr_node) == t_rr_type::CHANX - || rr_graph.node_type(rr_node) == t_rr_type::CHANY); + bool is_wire = (rr_graph.node_type(rr_node) == e_rr_type::CHANX + || rr_graph.node_type(rr_node) == e_rr_type::CHANY); if (!is_chain && !is_fringe && !is_wire) { - if (rr_graph.node_type(rr_node) == t_rr_type::IPIN || rr_graph.node_type(rr_node) == t_rr_type::OPIN) { + if (rr_graph.node_type(rr_node) == e_rr_type::IPIN || rr_graph.node_type(rr_node) == e_rr_type::OPIN) { if (has_adjacent_channel(rr_graph, grid, node)) { auto block_type = grid.get_physical_type({rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), @@ -320,7 +320,7 @@ static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const Device rr_graph.node_ylow(inode), rr_graph.node_layer(inode)}); - if (rr_graph.node_type(inode) != t_rr_type::IPIN) + if (rr_graph.node_type(inode) != e_rr_type::IPIN) return (false); ipin = rr_graph.node_pin_num(inode); @@ -342,7 +342,7 @@ void check_rr_node(const RRGraphView& rr_graph, //Make sure over-flow doesn't happen VTR_ASSERT(inode >= 0); int xlow, ylow, xhigh, yhigh, layer_num, ptc_num, capacity; - t_rr_type rr_type; + e_rr_type rr_type; t_physical_tile_type_ptr type; int nodes_per_chan, tracks_per_node; RRIndexedDataId cost_index; @@ -389,7 +389,7 @@ void check_rr_node(const RRGraphView& rr_graph, type = grid.get_physical_type({xlow, ylow, layer_num}); switch (rr_type) { - case t_rr_type::SOURCE: + case e_rr_type::SOURCE: if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow); @@ -400,7 +400,7 @@ void check_rr_node(const RRGraphView& rr_graph, "in check_rr_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d)\n", inode, rr_type, xlow, ylow, xhigh, yhigh); } break; - case t_rr_type::SINK: { + case e_rr_type::SINK: { if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow); @@ -413,8 +413,8 @@ void check_rr_node(const RRGraphView& rr_graph, } break; } - case t_rr_type::IPIN: - case t_rr_type::OPIN: + case e_rr_type::IPIN: + case e_rr_type::OPIN: if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow); @@ -425,7 +425,7 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case t_rr_type::CHANX: + case e_rr_type::CHANX: if (xlow < 1 || xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 2 || yhigh != ylow) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); @@ -436,7 +436,7 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case t_rr_type::CHANY: + case e_rr_type::CHANY: if (xhigh > int(grid.width()) - 2 || ylow < 1 || yhigh > int(grid.height()) - 2 || xlow != xhigh) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Error in check_rr_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); @@ -459,12 +459,12 @@ void check_rr_node(const RRGraphView& rr_graph, e_pin_type class_type = OPEN; int class_num_pins = -1; switch (rr_type) { - case t_rr_type::SOURCE: - case t_rr_type::SINK: + case e_rr_type::SOURCE: + case e_rr_type::SINK: class_type = get_class_type_from_class_physical_num(type, ptc_num); class_num_pins = get_class_num_pins_from_class_physical_num(type, ptc_num); if (ptc_num >= class_max_ptc - || class_type != ((rr_type == t_rr_type::SOURCE) ? DRIVER : RECEIVER)) { + || class_type != ((rr_type == e_rr_type::SOURCE) ? DRIVER : RECEIVER)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); } @@ -474,11 +474,11 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case t_rr_type::OPIN: - case t_rr_type::IPIN: + case e_rr_type::OPIN: + case e_rr_type::IPIN: class_type = get_pin_type_from_pin_physical_num(type, ptc_num); if (ptc_num >= pin_max_ptc - || class_type != ((rr_type == t_rr_type::OPIN) ? DRIVER : RECEIVER)) { + || class_type != ((rr_type == e_rr_type::OPIN) ? DRIVER : RECEIVER)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); } @@ -488,14 +488,14 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case t_rr_type::CHANX: - case t_rr_type::CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: if (route_type == DETAILED) { nodes_per_chan = chan_width.max; tracks_per_node = 1; } else { nodes_per_chan = 1; - tracks_per_node = ((rr_type == t_rr_type::CHANX) ? chan_width.x_list[ylow] : chan_width.y_list[xlow]); + tracks_per_node = ((rr_type == e_rr_type::CHANX) ? chan_width.x_list[ylow] : chan_width.y_list[xlow]); } //if a chanx/chany has length 0, it means it is used to connect different dice together @@ -522,7 +522,7 @@ void check_rr_node(const RRGraphView& rr_graph, C = rr_graph.node_C(rr_node); R = rr_graph.node_R(rr_node); - if (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY) { + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { if (C < 0. || R < 0.) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d of type %d has R = %g and C = %g.\n", inode, rr_type, R, C); @@ -540,12 +540,12 @@ static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node) { * bidirectional. It may be a slow check, so don't use it all the time. */ int from_edge, to_node, to_edge, from_num_edges, to_num_edges; - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; short from_switch_type; bool trans_matched; from_rr_type = rr_graph.node_type(RRNodeId(from_node)); - if (from_rr_type != t_rr_type::CHANX && from_rr_type != t_rr_type::CHANY) + if (from_rr_type != e_rr_type::CHANX && from_rr_type != e_rr_type::CHANY) return; from_num_edges = rr_graph.num_edges(RRNodeId(from_node)); @@ -554,7 +554,7 @@ static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node) { to_node = size_t(rr_graph.edge_sink_node(RRNodeId(from_node), from_edge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type != t_rr_type::CHANX && to_rr_type != t_rr_type::CHANY) + if (to_rr_type != e_rr_type::CHANX && to_rr_type != e_rr_type::CHANY) continue; from_switch_type = rr_graph.edge_switch(RRNodeId(from_node), from_edge); @@ -592,7 +592,7 @@ static bool has_adjacent_channel(const RRGraphView& rr_graph, const DeviceGrid& /* TODO: this function should be reworked later to adapt RRGraphView interface * once xlow(), ylow(), side() APIs are implemented */ - VTR_ASSERT(rr_graph.node_type(node.id()) == t_rr_type::IPIN || rr_graph.node_type(node.id()) == e_rr_type::OPIN); + VTR_ASSERT(rr_graph.node_type(node.id()) == e_rr_type::IPIN || rr_graph.node_type(node.id()) == e_rr_type::OPIN); if ((rr_graph.node_xlow(node.id()) == 0 && !rr_graph.is_node_on_specific_side(node.id(), RIGHT)) //left device edge connects only along block's right side || (rr_graph.node_ylow(node.id()) == int(grid.height() - 1) && !rr_graph.is_node_on_specific_side(node.id(), BOTTOM)) //top device edge connects only along block's bottom side diff --git a/libs/librrgraph/src/base/check_rr_graph_obj.cpp b/libs/librrgraph/src/base/check_rr_graph_obj.cpp index 300b2dd9515..9ab1d7f2a3d 100644 --- a/libs/librrgraph/src/base/check_rr_graph_obj.cpp +++ b/libs/librrgraph/src/base/check_rr_graph_obj.cpp @@ -94,7 +94,7 @@ static bool check_rr_graph_source_nodes(const RRGraph& rr_graph) { */ for (auto node : rr_graph.nodes()) { /* Pass nodes whose types are not SOURCE */ - if (t_rr_type::SOURCE != rr_graph.node_type(node)) { + if (e_rr_type::SOURCE != rr_graph.node_type(node)) { continue; } if ((0 != rr_graph.node_fan_in(node)) @@ -123,7 +123,7 @@ static bool check_rr_graph_sink_nodes(const RRGraph& rr_graph) { */ for (auto node : rr_graph.nodes()) { /* Pass nodes whose types are not SINK */ - if (t_rr_type::SINK != rr_graph.node_type(node)) { + if (e_rr_type::SINK != rr_graph.node_type(node)) { continue; } if ((0 == rr_graph.node_fan_in(node)) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 9233639a9ab..48852706c52 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -26,7 +26,7 @@ MetadataStorage>& RRGraphBuilder::rr_edge_metadata() } void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { - t_rr_type node_type = node_storage_.node_type(node); + e_rr_type node_type = node_storage_.node_type(node); short node_ptc_num = node_storage_.node_ptc_num(node); short node_layer = node_storage_.node_layer(node); short node_twist = node_storage_.node_ptc_twist(node); @@ -36,20 +36,20 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { node_ptc_num += node_twist * node_offset; node_offset++; switch (node_type) { - case t_rr_type::SOURCE: - case t_rr_type::SINK: - case t_rr_type::CHANY: + case e_rr_type::SOURCE: + case e_rr_type::SINK: + case e_rr_type::CHANY: node_lookup_.add_node(node, node_layer, ix, iy, node_type, node_ptc_num, TOTAL_2D_SIDES[0]); break; - case t_rr_type::CHANX: + case e_rr_type::CHANX: /* Currently need to swap x and y for CHANX because of chan, seg convention * TODO: Once the builders is reworked for use consistent (x, y) convention, * the following swapping can be removed */ node_lookup_.add_node(node, node_layer, iy, ix, node_type, node_ptc_num, TOTAL_2D_SIDES[0]); break; - case t_rr_type::OPIN: - case t_rr_type::IPIN: + case e_rr_type::OPIN: + case e_rr_type::IPIN: for (const e_side& side : TOTAL_2D_SIDES) { if (node_storage_.is_node_on_specific_side(node, side)) { node_lookup_.add_node(node,node_layer, ix, iy, node_type, node_ptc_num, side); diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 4844a785d70..487457e7bc5 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -119,7 +119,7 @@ class RRGraphBuilder { } /** @brief Set the type of a node with a given valid id */ - inline void set_node_type(RRNodeId id, t_rr_type type) { + inline void set_node_type(RRNodeId id, e_rr_type type) { node_storage_.set_node_type(id, type); } diff --git a/libs/librrgraph/src/base/rr_graph_obj.cpp b/libs/librrgraph/src/base/rr_graph_obj.cpp index 91c18e9cb4c..9f52f523eb7 100644 --- a/libs/librrgraph/src/base/rr_graph_obj.cpp +++ b/libs/librrgraph/src/base/rr_graph_obj.cpp @@ -32,7 +32,7 @@ RRGraph::segment_range RRGraph::segments() const { } //Node attributes -t_rr_type RRGraph::node_type(const RRNodeId& node) const { +e_rr_type RRGraph::node_type(const RRNodeId& node) const { VTR_ASSERT_SAFE(valid_node_id(node)); return node_types_[node]; } @@ -372,7 +372,7 @@ std::vector RRGraph::find_edges(const RRNodeId& src_node, const RRNode return matching_edges; } -RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type type, const int& ptc, const e_side& side) const { +RRNodeId RRGraph::find_node(const short& x, const short& y, const e_rr_type type, const int& ptc, const e_side& side) const { initialize_fast_node_lookup(); const size_t itype = (size_t)type; @@ -417,7 +417,7 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type type } /* Find the channel width (number of tracks) of a channel [x][y] */ -short RRGraph::chan_num_tracks(const short& x, const short& y, const t_rr_type& type) const { +short RRGraph::chan_num_tracks(const short& x, const short& y, const e_rr_type& type) const { /* Must be CHANX or CHANY */ VTR_ASSERT_MSG(e_rr_type::CHANX == type || e_rr_type::CHANY == type, "Required node_type to be CHANX or CHANY!"); @@ -798,7 +798,7 @@ void RRGraph::reserve_segments(const int& num_segments) { } /* Mutators */ -RRNodeId RRGraph::create_node(const t_rr_type& type) { +RRNodeId RRGraph::create_node(const e_rr_type& type) { //Allocate an ID RRNodeId node_id = RRNodeId(node_ids_.size()); diff --git a/libs/librrgraph/src/base/rr_graph_obj.h b/libs/librrgraph/src/base/rr_graph_obj.h index bd4e781046e..f3a3f8c8477 100644 --- a/libs/librrgraph/src/base/rr_graph_obj.h +++ b/libs/librrgraph/src/base/rr_graph_obj.h @@ -60,7 +60,7 @@ * // Get the unique node id that you may get * // from other data structures or functions * RRNodeId node_id; - * t_rr_type node_type = rr_graph.node_type(node_id); + * e_rr_type node_type = rr_graph.node_type(node_id); * * // Access all the fan-out edges from a given node * for (const RREdgeId& out_edge_id : rr_graph.node_out_edges(node_id)) { @@ -257,9 +257,9 @@ class RRGraph { /* get the type of a RRGraph node : types of each node, can be channel wires (CHANX or CHANY) or * logic block pins(OPIN or IPIN) or virtual nodes (SOURCE or SINK) - * see t_rr_type definition for more details + * see e_rr_type definition for more details */ - t_rr_type node_type(const RRNodeId& node) const; + e_rr_type node_type(const RRNodeId& node) const; /* Get coordinate of a node. (xlow, xhigh, ylow, yhigh): * For OPIN/IPIN/SOURCE/SINK, xlow = xhigh and ylow = yhigh @@ -510,9 +510,9 @@ class RRGraph { /* Find the edges connecting two nodes */ std::vector find_edges(const RRNodeId& src_node, const RRNodeId& sink_node) const; /* Find a node with given features from internal fast look-up */ - RRNodeId find_node(const short& x, const short& y, const t_rr_type type, const int& ptc, const e_side& side = NUM_2D_SIDES) const; + RRNodeId find_node(const short& x, const short& y, const e_rr_type type, const int& ptc, const e_side& side = NUM_2D_SIDES) const; /* Find the number of routing tracks in a routing channel with a given coordinate */ - short chan_num_tracks(const short& x, const short& y, const t_rr_type& type) const; + short chan_num_tracks(const short& x, const short& y, const e_rr_type& type) const; /* This flag is raised when the RRgraph contains invalid nodes/edges etc. * Invalid nodes/edges exist when users remove nodes/edges from RRGraph @@ -589,7 +589,7 @@ class RRGraph { * RRNodeId node = create_node(); * set_node_xlow(node, 0); */ - RRNodeId create_node(const t_rr_type& type); + RRNodeId create_node(const e_rr_type& type); /* Add a edge to the RRGraph, by providing the source and sink node * This function will automatically create a node and * configure the nodes and edges in connection @@ -782,7 +782,7 @@ class RRGraph { private: /* Internal Data */ /* Node related data */ vtr::vector node_ids_; /* Unique identifiers for the nodes */ - vtr::vector node_types_; + vtr::vector node_types_; vtr::vector> node_bounding_boxes_; diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 89afcaeeba4..787ec67098e 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -673,7 +673,7 @@ static int get_node_pin_num( vtr::array_view_id node_storage, vtr::array_view_id node_ptc, RRNodeId id) { - t_rr_type node_type = node_storage[id].type_; + e_rr_type node_type = node_storage[id].type_; if (node_type != e_rr_type::IPIN && node_type != e_rr_type::OPIN) { VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'", rr_node_typename[(size_t)node_type]); } @@ -684,7 +684,7 @@ static int get_node_track_num( vtr::array_view_id node_storage, vtr::array_view_id node_ptc, RRNodeId id) { - t_rr_type node_type = node_storage[id].type_; + e_rr_type node_type = node_storage[id].type_; if (node_type != e_rr_type::CHANX && node_type != e_rr_type::CHANY) { VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'", rr_node_typename[(size_t)node_type]); } @@ -695,7 +695,7 @@ static int get_node_class_num( vtr::array_view_id node_storage, vtr::array_view_id node_ptc, RRNodeId id) { - t_rr_type node_type = node_storage[id].type_; + e_rr_type node_type = node_storage[id].type_; if (node_type != e_rr_type::SOURCE && node_type != e_rr_type::SINK) { VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'", rr_node_typename[(size_t)node_type]); } @@ -721,7 +721,7 @@ int t_rr_graph_storage::node_class_num(RRNodeId id) const { id); } -void t_rr_graph_storage::set_node_type(RRNodeId id, t_rr_type new_type) { +void t_rr_graph_storage::set_node_type(RRNodeId id, e_rr_type new_type) { node_storage_[id].type_ = new_type; } diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 3bb930f55b2..a76e57fe731 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -63,7 +63,7 @@ struct alignas(16) t_rr_node_data { int16_t xhigh_ = -1; int16_t yhigh_ = -1; - t_rr_type type_ = t_rr_type::NUM_RR_TYPES; + e_rr_type type_ = e_rr_type::NUM_RR_TYPES; /* The character is a hex number which is a 4-bit truth table for node sides * The 4-bits in serial represent 4 sides on which a node could appear @@ -164,7 +164,7 @@ class t_rr_graph_storage { * Node methods * ****************/ - t_rr_type node_type(RRNodeId id) const { + e_rr_type node_type(RRNodeId id) const { return node_storage_[id].type_; } const char* node_type_string(RRNodeId id) const; @@ -619,7 +619,7 @@ class t_rr_graph_storage { void set_node_track_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_class_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent - void set_node_type(RRNodeId id, t_rr_type new_type); + void set_node_type(RRNodeId id, e_rr_type new_type); void set_node_name(RRNodeId id, const std::string& new_name); void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2); void set_node_layer(RRNodeId id, short layer); @@ -982,7 +982,7 @@ class t_rr_graph_view { return node_storage_.size(); } - t_rr_type node_type(RRNodeId id) const { + e_rr_type node_type(RRNodeId id) const { return node_storage_[id].type_; } const char* node_type_string(RRNodeId id) const; diff --git a/libs/librrgraph/src/base/rr_graph_utils.cpp b/libs/librrgraph/src/base/rr_graph_utils.cpp index 215ef5cc9d8..6a76ac6bac2 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.cpp +++ b/libs/librrgraph/src/base/rr_graph_utils.cpp @@ -75,8 +75,8 @@ std::vector find_rr_graph_switches(const RRGraph& rr_graph, return switches; } -int seg_index_of_cblock(const RRGraphView& rr_graph, t_rr_type from_rr_type, int to_node) { - if (from_rr_type == t_rr_type::CHANX) +int seg_index_of_cblock(const RRGraphView& rr_graph, e_rr_type from_rr_type, int to_node) { + if (from_rr_type == e_rr_type::CHANX) return (rr_graph.node_xlow(RRNodeId(to_node))); else /* CHANY */ @@ -84,15 +84,15 @@ int seg_index_of_cblock(const RRGraphView& rr_graph, t_rr_type from_rr_type, int } int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) { - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; from_rr_type = rr_graph.node_type(RRNodeId(from_node)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (from_rr_type == t_rr_type::CHANX) { - if (to_rr_type == t_rr_type::CHANY) { + if (from_rr_type == e_rr_type::CHANX) { + if (to_rr_type == e_rr_type::CHANY) { return (rr_graph.node_xlow(RRNodeId(to_node))); - } else if (to_rr_type == t_rr_type::CHANX) { + } else if (to_rr_type == e_rr_type::CHANX) { if (rr_graph.node_xlow(RRNodeId(to_node)) > rr_graph.node_xlow(RRNodeId(from_node))) { /* Going right */ return (rr_graph.node_xhigh(RRNodeId(from_node))); } else { /* Going left */ @@ -106,10 +106,10 @@ int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) } } /* End from_rr_type is CHANX */ - else if (from_rr_type == t_rr_type::CHANY) { - if (to_rr_type == t_rr_type::CHANX) { + else if (from_rr_type == e_rr_type::CHANY) { + if (to_rr_type == e_rr_type::CHANX) { return (rr_graph.node_ylow(RRNodeId(to_node))); - } else if (to_rr_type == t_rr_type::CHANY) { + } else if (to_rr_type == e_rr_type::CHANY) { if (rr_graph.node_ylow(RRNodeId(to_node)) > rr_graph.node_ylow(RRNodeId(from_node))) { /* Going up */ return (rr_graph.node_yhigh(RRNodeId(from_node))); } else { /* Going down */ @@ -218,17 +218,17 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil } // Remove old locations from lookup - VTR_ASSERT(rr_graph_builder.node_lookup().find_node(node_layer, new_loc.x(), new_loc.y(), t_rr_type::SINK, node_ptc) != RRNodeId::INVALID()); + VTR_ASSERT(rr_graph_builder.node_lookup().find_node(node_layer, new_loc.x(), new_loc.y(), e_rr_type::SINK, node_ptc) != RRNodeId::INVALID()); for (int x = tile_bb.xmin(); x <= tile_bb.xmax(); ++x) { for (int y = tile_bb.ymin(); y <= tile_bb.ymax(); ++y) { if (x == new_loc.x() && y == new_loc.y()) /* The new sink location */ continue; - if (rr_graph_builder.node_lookup().find_node(node_layer, x, y, t_rr_type::SINK, node_ptc) == RRNodeId::INVALID()) /* Already removed */ + if (rr_graph_builder.node_lookup().find_node(node_layer, x, y, e_rr_type::SINK, node_ptc) == RRNodeId::INVALID()) /* Already removed */ continue; - bool removed_successfully = rr_graph_builder.node_lookup().remove_node(node_id, node_layer, x, y, t_rr_type::SINK, node_ptc); + bool removed_successfully = rr_graph_builder.node_lookup().remove_node(node_id, node_layer, x, y, e_rr_type::SINK, node_ptc); VTR_ASSERT(removed_successfully); } } diff --git a/libs/librrgraph/src/base/rr_graph_utils.h b/libs/librrgraph/src/base/rr_graph_utils.h index c7fb3fd66c8..7ede4baafb9 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.h +++ b/libs/librrgraph/src/base/rr_graph_utils.h @@ -76,7 +76,7 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil * @brief Returns the segment number (distance along the channel) of the connection box from from_rr_type (CHANX or * CHANY) to to_node (IPIN). */ -int seg_index_of_cblock(const RRGraphView& rr_graph, t_rr_type from_rr_type, int to_node); +int seg_index_of_cblock(const RRGraphView& rr_graph, e_rr_type from_rr_type, int to_node); /** * @brief Returns the segment number (distance along the channel) of the switch box from from_node (CHANX or CHANY) to diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 83668e05d08..e420e46ddd8 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -123,7 +123,7 @@ class RRGraphView { /** @brief Return the type of a specified node. */ - inline t_rr_type node_type(RRNodeId node) const { + inline e_rr_type node_type(RRNodeId node) const { return node_storage_.node_type(node); } @@ -256,7 +256,7 @@ class RRGraphView { /** @brief Check if a routing resource node is initialized. */ inline bool node_is_initialized(RRNodeId node) const { - return !((node_type(node) == t_rr_type::NUM_RR_TYPES) + return !((node_type(node) == e_rr_type::NUM_RR_TYPES) && (node_xlow(node) == -1) && (node_ylow(node) == -1) && (node_xhigh(node) == -1) && (node_yhigh(node) == -1)); } diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index 3895861e3d0..6b4fd306e48 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -20,7 +20,7 @@ * - SOURCE * - SINK */ -typedef enum class e_rr_type : unsigned char { +enum class e_rr_type : unsigned char { SOURCE = 0, /// RR_TYPES = {{e_rr_type::SOURCE, e_rr_type::SINK, e_rr_type::IPIN, +constexpr std::array RR_TYPES = {{e_rr_type::SOURCE, e_rr_type::SINK, e_rr_type::IPIN, e_rr_type::OPIN, e_rr_type::CHANX, e_rr_type::CHANY}}; -constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; +constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; /* * Direction::INC: wire driver is positioned at the low-coordinate end of the wire. @@ -124,4 +124,4 @@ struct t_rr_rc_data { // This is the data type of fast lookups of an rr-node given an (rr_type, layer, x, y, and the side) //[0..num_rr_types-1][0..num_layer-1][0..grid_width-1][0..grid_height-1][0..NUM_2D_SIDES-1][0..max_ptc-1] -typedef std::array, 4>, (size_t)t_rr_type::NUM_RR_TYPES> t_rr_node_indices; +typedef std::array, 4>, (size_t)e_rr_type::NUM_RR_TYPES> t_rr_node_indices; diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 00db875b932..de5fdfdebef 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -7,7 +7,7 @@ RRSpatialLookup::RRSpatialLookup() { RRNodeId RRSpatialLookup::find_node(int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side) const { /* Find actual side to be used @@ -83,7 +83,7 @@ std::vector RRSpatialLookup::find_nodes_in_range(int layer, int ylow, int xhigh, int yhigh, - t_rr_type type, + e_rr_type type, int ptc, e_side side) const { std::set nodes; @@ -102,7 +102,7 @@ std::vector RRSpatialLookup::find_nodes_in_range(int layer, std::vector RRSpatialLookup::find_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, e_side side) const { /* TODO: The implementation of this API should be worked * when rr_node_indices adapts RRNodeId natively! @@ -173,7 +173,7 @@ std::vector RRSpatialLookup::find_nodes(int layer, std::vector RRSpatialLookup::find_channel_nodes(int layer, int x, int y, - t_rr_type type) const { + e_rr_type type) const { /* Pre-check: node type should be routing tracks! */ if (type != e_rr_type::CHANX && type != e_rr_type::CHANY) { return std::vector(); @@ -185,7 +185,7 @@ std::vector RRSpatialLookup::find_channel_nodes(int layer, std::vector RRSpatialLookup::find_nodes_at_all_sides(int layer, int x, int y, - t_rr_type rr_type, + e_rr_type rr_type, int ptc) const { std::vector indices; @@ -214,7 +214,7 @@ std::vector RRSpatialLookup::find_nodes_at_all_sides(int layer, std::vector RRSpatialLookup::find_grid_nodes_at_all_sides(int layer, int x, int y, - t_rr_type rr_type) const { + e_rr_type rr_type) const { VTR_ASSERT(rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::OPIN || rr_type == e_rr_type::IPIN || rr_type == e_rr_type::SINK); if (rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::SINK) { return find_nodes(layer,x, y, rr_type); @@ -238,7 +238,7 @@ std::vector RRSpatialLookup::find_grid_nodes_at_all_sides(int layer, void RRSpatialLookup::reserve_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, int num_nodes, e_side side) { VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); @@ -257,7 +257,7 @@ void RRSpatialLookup::add_node(RRNodeId node, int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side) { VTR_ASSERT(node.is_valid()); /* Must have a valid node id to be added */ @@ -283,7 +283,7 @@ bool RRSpatialLookup::remove_node(RRNodeId node, int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side) { VTR_ASSERT(node.is_valid()); @@ -291,7 +291,7 @@ bool RRSpatialLookup::remove_node(RRNodeId node, VTR_ASSERT_SAFE(layer >= 0); VTR_ASSERT_SAFE(x >= 0); VTR_ASSERT_SAFE(y >= 0); - VTR_ASSERT_SAFE(type != t_rr_type::NUM_RR_TYPES); + VTR_ASSERT_SAFE(type != e_rr_type::NUM_RR_TYPES); VTR_ASSERT_SAFE(ptc >= 0); VTR_ASSERT_SAFE(side != NUM_2D_SIDES); @@ -313,7 +313,7 @@ bool RRSpatialLookup::remove_node(RRNodeId node, void RRSpatialLookup::mirror_nodes(const int layer, const vtr::Point& src_coord, const vtr::Point& des_coord, - t_rr_type type, + e_rr_type type, e_side side) { VTR_ASSERT(e_rr_type::SOURCE == type); resize_nodes(layer, des_coord.x(), des_coord.y(), type, side); @@ -323,7 +323,7 @@ void RRSpatialLookup::mirror_nodes(const int layer, void RRSpatialLookup::resize_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, e_side side) { /* Expand the fast look-up if the new node is out-of-range * This may seldom happen because the rr_graph building function diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.h b/libs/librrgraph/src/base/rr_spatial_lookup.h index 049175e587c..1af0b6652af 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.h +++ b/libs/librrgraph/src/base/rr_spatial_lookup.h @@ -71,7 +71,7 @@ class RRSpatialLookup { RRNodeId find_node(int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side = NUM_2D_SIDES) const; @@ -94,7 +94,7 @@ class RRSpatialLookup { int ylow, int xhigh, int yhigh, - t_rr_type type, + e_rr_type type, int ptc, e_side side = e_side::NUM_2D_SIDES) const; @@ -116,7 +116,7 @@ class RRSpatialLookup { std::vector find_channel_nodes(int layer, int x, int y, - t_rr_type type) const; + e_rr_type type) const; /** * @brief Like find_node() but returns all matching nodes on all the sides. @@ -127,7 +127,7 @@ class RRSpatialLookup { std::vector find_nodes_at_all_sides(int layer, int x, int y, - t_rr_type rr_type, + e_rr_type rr_type, int ptc) const; /** @@ -138,7 +138,7 @@ class RRSpatialLookup { std::vector find_grid_nodes_at_all_sides(int layer, int x, int y, - t_rr_type rr_type) const; + e_rr_type rr_type) const; /* -- Mutators -- */ public: @@ -146,7 +146,7 @@ class RRSpatialLookup { void reserve_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, int num_nodes, e_side side = TOTAL_2D_SIDES[0]); @@ -179,7 +179,7 @@ class RRSpatialLookup { int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side = TOTAL_2D_SIDES[0]); @@ -203,7 +203,7 @@ class RRSpatialLookup { int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side = TOTAL_2D_SIDES[0]); @@ -249,7 +249,7 @@ class RRSpatialLookup { void mirror_nodes(const int layer, const vtr::Point& src_coord, const vtr::Point& des_coord, - t_rr_type type, + e_rr_type type, e_side side); /** @@ -266,7 +266,7 @@ class RRSpatialLookup { void resize_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, e_side side); /** @brief Reorder the internal look up to be more memory efficient */ @@ -285,7 +285,7 @@ class RRSpatialLookup { std::vector find_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, e_side side = TOTAL_2D_SIDES[0]) const; /* -- Internal data storage -- */ diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index ad23948815d..1ee3676dda4 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1847,7 +1847,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { auto& rr_graph_builder = (*rr_graph_builder_); /* Alloc the lookup table */ - for (t_rr_type rr_type : RR_TYPES) { + for (e_rr_type rr_type : RR_TYPES) { if (rr_type == e_rr_type::CHANX) { rr_graph_builder.node_lookup().resize_nodes(grid_.get_num_layers(), grid_.height(), grid_.width(), rr_type, NUM_2D_SIDES); } else { @@ -2004,7 +2004,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { } } - t_rr_type from_uxsd_node_type(uxsd::enum_node_type type) { + e_rr_type from_uxsd_node_type(uxsd::enum_node_type type) { switch (type) { case uxsd::enum_node_type::CHANX: return e_rr_type::CHANX; @@ -2024,7 +2024,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { type); } } - uxsd::enum_node_type to_uxsd_node_type(t_rr_type type) { + uxsd::enum_node_type to_uxsd_node_type(e_rr_type type) { switch (type) { case e_rr_type::CHANX: return uxsd::enum_node_type::CHANX; diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 0496e605a49..a3d4a554f90 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -190,8 +190,8 @@ std::vector find_ortho_cost_index(const RRGraphView& rr_graph, for (const RRNodeId& rr_node : rr_graph.nodes()) { for (size_t iedge = 0; iedge < rr_graph.num_edges(rr_node); ++iedge) { RRNodeId to_node = rr_graph.edge_sink_node(rr_node, iedge); - t_rr_type from_node_type = rr_graph.node_type(rr_node); - t_rr_type to_node_type = rr_graph.node_type(to_node); + e_rr_type from_node_type = rr_graph.node_type(rr_node); + e_rr_type to_node_type = rr_graph.node_type(to_node); size_t from_node_cost_index = (size_t)rr_graph.node_cost_index(rr_node); size_t to_node_cost_index = (size_t)rr_graph.node_cost_index(to_node); @@ -526,7 +526,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, * data. */ for (const RRNodeId& rr_id : rr_graph.nodes()) { - t_rr_type rr_type = rr_graph.node_type(rr_id); + e_rr_type rr_type = rr_graph.node_type(rr_id); if (rr_type != e_rr_type::CHANX && rr_type != e_rr_type::CHANY) { continue; diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index fc354a90c9e..0b8231925e7 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -579,7 +579,7 @@ void print_route(const Netlist<>& net_list, while (tptr != nullptr) { RRNodeId inode = RRNodeId(tptr->index); - t_rr_type rr_type = rr_graph.node_type(inode); + e_rr_type rr_type = rr_graph.node_type(inode); int ilow = rr_graph.node_xlow(inode); int jlow = rr_graph.node_ylow(inode); int layer_num = rr_graph.node_layer(inode); diff --git a/vpr/src/base/stats.cpp b/vpr/src/base/stats.cpp index e2959ae6633..dbd88cebb0b 100644 --- a/vpr/src/base/stats.cpp +++ b/vpr/src/base/stats.cpp @@ -310,13 +310,13 @@ static void load_channel_occupancies(const Netlist<>& net_list, for (const RouteTreeNode& rt_node : tree.value().all_nodes()) { RRNodeId inode = rt_node.inode; - t_rr_type rr_type = rr_graph.node_type(inode); + e_rr_type rr_type = rr_graph.node_type(inode); - if (rr_type == t_rr_type::CHANX) { + if (rr_type == e_rr_type::CHANX) { int j = rr_graph.node_ylow(inode); for (int i = rr_graph.node_xlow(inode); i <= rr_graph.node_xhigh(inode); i++) chanx_occ[i][j]++; - } else if (rr_type == t_rr_type::CHANY) { + } else if (rr_type == e_rr_type::CHANY) { int i = rr_graph.node_xlow(inode); for (int j = rr_graph.node_ylow(inode); j <= rr_graph.node_yhigh(inode); j++) chany_occ[i][j]++; @@ -344,7 +344,7 @@ void get_num_bends_and_length(ParentNetId inet, int* bends_ptr, int* len_ptr, in "in get_num_bends_and_length: net #%lu has no routing.\n", size_t(inet)); } - t_rr_type prev_type = rr_graph.node_type(tree->root().inode); + e_rr_type prev_type = rr_graph.node_type(tree->root().inode); RouteTree::iterator it = tree->all_nodes().begin(); RouteTree::iterator end = tree->all_nodes().end(); ++it; /* start from the next node after source */ @@ -352,18 +352,18 @@ void get_num_bends_and_length(ParentNetId inet, int* bends_ptr, int* len_ptr, in for (; it != end; ++it) { const RouteTreeNode& rt_node = *it; RRNodeId inode = rt_node.inode; - t_rr_type curr_type = rr_graph.node_type(inode); + e_rr_type curr_type = rr_graph.node_type(inode); - if (curr_type == t_rr_type::CHANX || curr_type == t_rr_type::CHANY) { + if (curr_type == e_rr_type::CHANX || curr_type == e_rr_type::CHANY) { segments++; length += rr_graph.node_length(inode); - if (curr_type != prev_type && (prev_type == t_rr_type::CHANX || prev_type == t_rr_type::CHANY)) + if (curr_type != prev_type && (prev_type == e_rr_type::CHANX || prev_type == e_rr_type::CHANY)) bends++; } /* The all_nodes iterator walks all nodes in the tree. If we are at a leaf and going back to the top, prev_type is invalid: just set it to SINK */ - prev_type = rt_node.is_leaf() ? t_rr_type::SINK : curr_type; + prev_type = rt_node.is_leaf() ? e_rr_type::SINK : curr_type; } *bends_ptr = bends; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index c2ca97e73fe..64e2a24ba24 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1360,9 +1360,9 @@ struct t_det_routing_arch { std::string read_rr_edge_override_filename; }; -constexpr bool is_pin(e_rr_type type) { return (type == t_rr_type::IPIN || type == t_rr_type::OPIN); } -constexpr bool is_chan(e_rr_type type) { return (type == t_rr_type::CHANX || type == t_rr_type::CHANY); } -constexpr bool is_src_sink(e_rr_type type) { return (type == t_rr_type::SOURCE || type == t_rr_type::SINK); } +constexpr bool is_pin(e_rr_type type) { return (type == e_rr_type::IPIN || type == e_rr_type::OPIN); } +constexpr bool is_chan(e_rr_type type) { return (type == e_rr_type::CHANX || type == e_rr_type::CHANY); } +constexpr bool is_src_sink(e_rr_type type) { return (type == e_rr_type::SOURCE || type == e_rr_type::SINK); } /** * @brief Extra information about each rr_node needed only during routing diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index fe984f275d0..0f3ec5902fe 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -623,7 +623,7 @@ int get_track_num(int inode, const vtr::OffsetMatrix& chanx_track, const vt /* Returns the track number of this routing resource node. */ int i, j; - t_rr_type rr_type; + e_rr_type rr_type; auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; RRNodeId rr_node = RRNodeId(inode); @@ -638,10 +638,10 @@ int get_track_num(int inode, const vtr::OffsetMatrix& chanx_track, const vt j = rr_graph.node_ylow(rr_node); /* length channel segments. */ switch (rr_type) { - case t_rr_type::CHANX: + case e_rr_type::CHANX: return (chanx_track[i][j]); - case t_rr_type::CHANY: + case e_rr_type::CHANY: return (chany_track[i][j]); default: diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index 770c8532115..82e0fa134ca 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -351,13 +351,13 @@ void draw_congestion(ezgl::renderer* g) { color.alpha = transparency_factor; switch (rr_graph.node_type(inode)) { - case t_rr_type::CHANX: //fallthrough - case t_rr_type::CHANY: + case e_rr_type::CHANX: //fallthrough + case e_rr_type::CHANY: draw_rr_chan(inode, color, g); break; - case t_rr_type::IPIN: //fallthrough - case t_rr_type::OPIN: + case e_rr_type::IPIN: //fallthrough + case e_rr_type::OPIN: draw_rr_pin(inode, color, g); break; default: @@ -651,15 +651,15 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren ezgl::color color = draw_state->draw_rr_node[inode].color; switch (rr_type) { - case t_rr_type::OPIN: { + case e_rr_type::OPIN: { draw_rr_pin(inode, color, g); break; } - case t_rr_type::IPIN: { + case e_rr_type::IPIN: { draw_rr_pin(inode, color, g); if (edge_visibility.visible) { g->set_color(color, edge_visibility.alpha); - if (rr_graph.node_type(prev_node) == t_rr_type::OPIN) { + if (rr_graph.node_type(prev_node) == e_rr_type::OPIN) { draw_pin_to_pin(prev_node, inode, g); } else { draw_pin_to_chan_edge(inode, prev_node, g); @@ -667,7 +667,7 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren } break; } - case t_rr_type::CHANX: { + case e_rr_type::CHANX: { if (draw_state->draw_route_type == GLOBAL) chanx_track[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)]++; @@ -675,15 +675,15 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren if (edge_visibility.visible) { g->set_color(color, edge_visibility.alpha); switch (prev_type) { - case t_rr_type::CHANX: { + case e_rr_type::CHANX: { draw_chanx_to_chanx_edge(prev_node, inode, switch_type, g); break; } - case t_rr_type::CHANY: { + case e_rr_type::CHANY: { draw_chanx_to_chany_edge(inode, prev_node, FROM_Y_TO_X, switch_type, g); break; } - case t_rr_type::OPIN: { + case e_rr_type::OPIN: { draw_pin_to_chan_edge(prev_node, inode, g); break; } @@ -697,7 +697,7 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren break; } - case t_rr_type::CHANY: { + case e_rr_type::CHANY: { if (draw_state->draw_route_type == GLOBAL) chany_track[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)]++; @@ -706,17 +706,17 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren if (edge_visibility.visible) { g->set_color(color, edge_visibility.alpha); switch (prev_type) { - case t_rr_type::CHANX: { + case e_rr_type::CHANX: { draw_chanx_to_chany_edge(prev_node, inode, FROM_X_TO_Y, switch_type, g); break; } - case t_rr_type::CHANY: { + case e_rr_type::CHANY: { draw_chany_to_chany_edge(RRNodeId(prev_node), RRNodeId(inode), switch_type, g); break; } - case t_rr_type::OPIN: { + case e_rr_type::OPIN: { draw_pin_to_chan_edge(prev_node, inode, g); break; @@ -839,11 +839,11 @@ void draw_routing_util(ezgl::renderer* g) { t_draw_coords* draw_coords = get_draw_coords_vars(); auto& device_ctx = g_vpr_ctx.device(); - auto chanx_usage = calculate_routing_usage(t_rr_type::CHANX, draw_state->is_flat, false); - auto chany_usage = calculate_routing_usage(t_rr_type::CHANY, draw_state->is_flat, false); + auto chanx_usage = calculate_routing_usage(e_rr_type::CHANX, draw_state->is_flat, false); + auto chany_usage = calculate_routing_usage(e_rr_type::CHANY, draw_state->is_flat, false); - auto chanx_avail = calculate_routing_avail(t_rr_type::CHANX); - auto chany_avail = calculate_routing_avail(t_rr_type::CHANY); + auto chanx_avail = calculate_routing_avail(e_rr_type::CHANX); + auto chany_avail = calculate_routing_avail(e_rr_type::CHANY); float min_util = 0.; float max_util = -std::numeric_limits::infinity(); diff --git a/vpr/src/draw/draw_rr.cpp b/vpr/src/draw/draw_rr.cpp index ad9e8e38cfb..d9c6c71c5f3 100644 --- a/vpr/src/draw/draw_rr.cpp +++ b/vpr/src/draw/draw_rr.cpp @@ -62,20 +62,20 @@ void draw_rr(ezgl::renderer* g) { if (!draw_state->draw_rr_node[inode].node_highlighted) { /* If not highlighted node, assign color based on type. */ switch (rr_graph.node_type(inode)) { - case t_rr_type::CHANX: - case t_rr_type::CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR; break; - case t_rr_type::OPIN: + case e_rr_type::OPIN: draw_state->draw_rr_node[inode].color = ezgl::PINK; break; - case t_rr_type::IPIN: + case e_rr_type::IPIN: draw_state->draw_rr_node[inode].color = blk_LIGHTSKYBLUE; break; - case t_rr_type::SOURCE: + case e_rr_type::SOURCE: draw_state->draw_rr_node[inode].color = ezgl::PLUM; break; - case t_rr_type::SINK: + case e_rr_type::SINK: draw_state->draw_rr_node[inode].color = ezgl::DARK_SLATE_BLUE; break; default: @@ -90,30 +90,30 @@ void draw_rr(ezgl::renderer* g) { /* Now call drawing routines to draw the node. */ switch (rr_graph.node_type(inode)) { - case t_rr_type::SINK: + case e_rr_type::SINK: draw_rr_src_sink(inode, draw_state->draw_rr_node[inode].color, g); break; - case t_rr_type::SOURCE: + case e_rr_type::SOURCE: draw_rr_edges(inode, g); draw_rr_src_sink(inode, draw_state->draw_rr_node[inode].color, g); break; - case t_rr_type::CHANX: + case e_rr_type::CHANX: draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; - case t_rr_type::CHANY: + case e_rr_type::CHANY: draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; - case t_rr_type::IPIN: + case e_rr_type::IPIN: draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; - case t_rr_type::OPIN: + case e_rr_type::OPIN: draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; @@ -133,9 +133,9 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { int transparency_factor = get_rr_node_transparency(inode); - t_rr_type type = rr_graph.node_type(inode); + e_rr_type type = rr_graph.node_type(inode); - VTR_ASSERT(type == t_rr_type::CHANX || type == t_rr_type::CHANY); + VTR_ASSERT(type == e_rr_type::CHANX || type == e_rr_type::CHANY); ezgl::rectangle bound_box = draw_get_rr_chan_bbox(inode); Direction dir = rr_graph.node_direction(inode); @@ -163,7 +163,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { e_side mux_dir = TOP; int coord_min = -1; int coord_max = -1; - if (type == t_rr_type::CHANX) { + if (type == e_rr_type::CHANX) { coord_min = rr_graph.node_xlow(inode); coord_max = rr_graph.node_xhigh(inode); if (dir == Direction::INC) { @@ -172,7 +172,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { mux_dir = LEFT; } } else { - VTR_ASSERT(type == t_rr_type::CHANY); + VTR_ASSERT(type == e_rr_type::CHANY); coord_min = rr_graph.node_ylow(inode); coord_max = rr_graph.node_yhigh(inode); if (dir == Direction::INC) { @@ -201,7 +201,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { ezgl::point2d arrow_loc_min(0, 0); ezgl::point2d arrow_loc_max(0, 0); - if (type == t_rr_type::CHANX) { + if (type == e_rr_type::CHANX) { float sb_xmin = draw_coords->tile_x[k]; arrow_loc_min = {sb_xmin + arrow_offset, start.y}; @@ -281,14 +281,14 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { int transparency_factor = get_rr_node_transparency(rr_node); - t_rr_type from_type, to_type; + e_rr_type from_type, to_type; short switch_type; from_type = rr_graph.node_type(rr_node); if ((draw_state->draw_rr_toggle == DRAW_NODES_RR) - || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == t_rr_type::OPIN || from_type == t_rr_type::SOURCE || from_type == t_rr_type::IPIN)) - || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_CBOX_RR && (from_type == t_rr_type::SOURCE || from_type == t_rr_type::IPIN))) { + || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == e_rr_type::OPIN || from_type == e_rr_type::SOURCE || from_type == e_rr_type::IPIN)) + || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_CBOX_RR && (from_type == e_rr_type::SOURCE || from_type == e_rr_type::IPIN))) { return; /* Nothing to draw. */ } @@ -301,10 +301,10 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { continue; // skip drawing if edge is not valid to draw switch (from_type) { - case t_rr_type::OPIN: + case e_rr_type::OPIN: switch (to_type) { - case t_rr_type::CHANX: - case t_rr_type::CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { // If OPIN was clicked on, set color to fan-out ezgl::color color = draw_state->draw_rr_node[to_node].color; @@ -318,7 +318,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { } draw_pin_to_chan_edge(inode, to_node, g); break; - case t_rr_type::IPIN: + case e_rr_type::IPIN: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -338,9 +338,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { } break; - case t_rr_type::CHANX: /* from_type */ + case e_rr_type::CHANX: /* from_type */ switch (to_type) { - case t_rr_type::IPIN: + case e_rr_type::IPIN: if (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR) { break; } @@ -365,7 +365,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { draw_pin_to_chan_edge(to_node, inode, g); break; - case t_rr_type::CHANX: + case e_rr_type::CHANX: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -383,7 +383,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { switch_type, g); break; - case t_rr_type::CHANY: + case e_rr_type::CHANY: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -408,9 +408,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { } break; - case t_rr_type::CHANY: /* from_type */ + case e_rr_type::CHANY: /* from_type */ switch (to_type) { - case t_rr_type::IPIN: + case e_rr_type::IPIN: if (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR) { break; } @@ -435,7 +435,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { draw_pin_to_chan_edge(to_node, inode, g); break; - case t_rr_type::CHANX: + case e_rr_type::CHANX: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -453,7 +453,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { FROM_Y_TO_X, switch_type, g); break; - case t_rr_type::CHANY: + case e_rr_type::CHANY: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -478,9 +478,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { break; } break; - case t_rr_type::IPIN: // from_type + case e_rr_type::IPIN: // from_type switch (to_type) { - case t_rr_type::SINK: + case e_rr_type::SINK: g->set_color(ezgl::DARK_SLATE_BLUE, transparency_factor); draw_pin_to_sink(inode, to_node, g); break; @@ -492,9 +492,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { break; } break; - case t_rr_type::SOURCE: // from_type + case e_rr_type::SOURCE: // from_type switch (to_type) { - case t_rr_type::OPIN: + case e_rr_type::OPIN: g->set_color(ezgl::PLUM, transparency_factor); draw_source_to_pin(inode, to_node, g); break; @@ -686,8 +686,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { continue; /* Don't check RR nodes on currently invisible layers*/ } switch (rr_graph.node_type(inode)) { - case t_rr_type::IPIN: - case t_rr_type::OPIN: { + case e_rr_type::IPIN: + case e_rr_type::OPIN: { int i = rr_graph.node_xlow(inode); int j = rr_graph.node_ylow(inode); t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({i, j, layer_num}); @@ -709,8 +709,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { } break; } - case t_rr_type::SOURCE: - case t_rr_type::SINK: { + case e_rr_type::SOURCE: + case e_rr_type::SINK: { float xcen, ycen; draw_get_rr_src_sink_coords(rr_graph.rr_nodes()[size_t(inode)], &xcen, &ycen); @@ -721,8 +721,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { } break; } - case t_rr_type::CHANX: - case t_rr_type::CHANY: { + case e_rr_type::CHANX: + case e_rr_type::CHANY: { bound_box = draw_get_rr_chan_bbox(inode); // Check if we clicked on this wire, with 30% @@ -815,22 +815,22 @@ void draw_rr_costs(ezgl::renderer* g, const vtr::vector& rr_cos color.alpha = transparency_factor; switch (rr_graph.node_type(inode)) { - case t_rr_type::CHANX: //fallthrough - case t_rr_type::CHANY: + case e_rr_type::CHANX: //fallthrough + case e_rr_type::CHANY: draw_rr_chan(inode, color, g); if (with_edges) draw_rr_edges(inode, g); break; - case t_rr_type::IPIN: //fallthrough + case e_rr_type::IPIN: //fallthrough draw_rr_pin(inode, color, g); if (with_edges) draw_rr_edges(inode, g); break; - case t_rr_type::OPIN: + case e_rr_type::OPIN: draw_rr_pin(inode, color, g); if (with_edges) draw_rr_edges(inode, g); break; - case t_rr_type::SOURCE: - case t_rr_type::SINK: + case e_rr_type::SOURCE: + case e_rr_type::SINK: color.alpha *= 0.8; draw_rr_src_sink(inode, color, g); if (with_edges) draw_rr_edges(inode, g); diff --git a/vpr/src/draw/draw_rr_edges.cpp b/vpr/src/draw/draw_rr_edges.cpp index b61be53b1db..2aff5c3d35c 100644 --- a/vpr/src/draw/draw_rr_edges.cpp +++ b/vpr/src/draw/draw_rr_edges.cpp @@ -434,7 +434,7 @@ void draw_pin_to_chan_edge(RRNodeId pin_node, RRNodeId chan_node, ezgl::renderer * Any rr_node of a grid should have at least 1 side!!! */ e_side pin_side = NUM_2D_SIDES; - const t_rr_type channel_type = rr_graph.node_type(chan_node); + const e_rr_type channel_type = rr_graph.node_type(chan_node); if (1 == pin_candidate_sides.size()) { pin_side = pin_candidate_sides[0]; } else { diff --git a/vpr/src/pack/post_routing_pb_pin_fixup.cpp b/vpr/src/pack/post_routing_pb_pin_fixup.cpp index e66958e1d44..3cffcc3b56c 100644 --- a/vpr/src/pack/post_routing_pb_pin_fixup.cpp +++ b/vpr/src/pack/post_routing_pb_pin_fixup.cpp @@ -124,7 +124,7 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li auto pin_type = get_pin_type_from_pin_physical_num(physical_tile, physical_pin); - t_rr_type rr_node_type; + e_rr_type rr_node_type; if (pin_type == DRIVER) { rr_node_type = e_rr_type::OPIN; } else { diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index cbde73d230a..354f58f932b 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -100,7 +100,7 @@ static void get_intra_cluster_connections(const RouteTree& tree, std::vectorinode); - if ((type == t_rr_type::IPIN || type == t_rr_type::OPIN) && (parent_type == t_rr_type::IPIN || parent_type == t_rr_type::OPIN)) { + if ((type == e_rr_type::IPIN || type == e_rr_type::OPIN) && (parent_type == e_rr_type::IPIN || parent_type == e_rr_type::OPIN)) { auto clb = get_cluster_block_from_rr_node(node.inode); auto parent_clb = get_cluster_block_from_rr_node(parent->inode); if (clb == parent_clb) @@ -336,7 +336,7 @@ static void sync_clustered_netlist_to_routing(void) { int clb_nets_so_far = 0; for (auto& rt_node : tree->all_nodes()) { auto node_type = rr_graph.node_type(rt_node.inode); - if (node_type != t_rr_type::IPIN && node_type != t_rr_type::OPIN) + if (node_type != e_rr_type::IPIN && node_type != e_rr_type::OPIN) continue; auto physical_tile = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rt_node.inode), @@ -353,7 +353,7 @@ static void sync_clustered_netlist_to_routing(void) { /* OPIN on the tile: create a new clb_net_id and add all ports & pins into here * Due to how the route tree is traversed, all nodes until the next OPIN on the tile will * be under this OPIN, so this is valid (we don't need to get the branch explicitly) */ - if (node_type == t_rr_type::OPIN) { + if (node_type == e_rr_type::OPIN) { std::string net_name; net_name = atom_ctx.netlist().net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); clb_net_id = clb_netlist.create_net(net_name); @@ -376,7 +376,7 @@ static void sync_clustered_netlist_to_routing(void) { VTR_ASSERT_MSG(false, "Unsupported port type"); port_id = clb_netlist.create_port(clb, pb_graph_pin->port->name, pb_graph_pin->port->num_pins, port_type); } - PinType pin_type = node_type == t_rr_type::OPIN ? PinType::DRIVER : PinType::SINK; + PinType pin_type = node_type == e_rr_type::OPIN ? PinType::DRIVER : PinType::SINK; ClusterPinId new_pin = clb_netlist.create_pin(port_id, pb_graph_pin->pin_number, clb_net_id, pin_type, pb_graph_pin->pin_count_in_cluster); clb_netlist.set_pin_net(new_pin, pin_type, clb_net_id); diff --git a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp index f75ac77bc42..17b866c6330 100644 --- a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp +++ b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp @@ -532,7 +532,7 @@ static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& /*rou auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); for (int driver_ptc : best_driver_ptcs) { VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, t_rr_type::SOURCE, driver_ptc); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, e_rr_type::SOURCE, driver_ptc); VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); auto delays = calculate_all_path_delays_from_rr_node(source_rr_node, router_opts, is_flat); @@ -651,7 +651,7 @@ static float route_connection_delay(RouterDelayProfiler& route_profiler, for (int driver_ptc : best_driver_ptcs) { VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(source_layer, source_x, source_y, t_rr_type::SOURCE, driver_ptc); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(source_layer, source_x, source_y, e_rr_type::SOURCE, driver_ptc); VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); @@ -903,7 +903,7 @@ bool find_direct_connect_sample_locations(const t_direct_inf* direct, // Find a source/sink RR node associated with the pins of the direct { - RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, t_rr_type::SOURCE, from_pin_class); + RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, e_rr_type::SOURCE, from_pin_class); VTR_ASSERT(src_rr_candidate); out_src_node = src_rr_candidate; } diff --git a/vpr/src/route/annotate_routing.cpp b/vpr/src/route/annotate_routing.cpp index 6a11000e0da..13eccea0fee 100644 --- a/vpr/src/route/annotate_routing.cpp +++ b/vpr/src/route/annotate_routing.cpp @@ -41,8 +41,8 @@ vtr::vector annotate_rr_node_nets(const ClusteringContex for (auto& rt_node : tree->all_nodes()) { const RRNodeId rr_node = rt_node.inode; /* Ignore source and sink nodes, they are the common node multiple starting and ending points */ - if ((t_rr_type::SOURCE != rr_graph.node_type(rr_node)) - && (t_rr_type::SINK != rr_graph.node_type(rr_node))) { + if ((e_rr_type::SOURCE != rr_graph.node_type(rr_node)) + && (e_rr_type::SINK != rr_graph.node_type(rr_node))) { /* Sanity check: ensure we do not revoke any net mapping * In some routing architectures, node capacity is more than 1 * which allows a node to be mapped by multiple nets diff --git a/vpr/src/route/build_switchblocks.cpp b/vpr/src/route/build_switchblocks.cpp index 487f3f6d640..b9bf8b819cc 100644 --- a/vpr/src/route/build_switchblocks.cpp +++ b/vpr/src/route/build_switchblocks.cpp @@ -229,8 +229,8 @@ static void compute_wireconn_connections( int to_x, int to_y, int to_layer, - t_rr_type from_chan_type, - t_rr_type to_chan_type, + e_rr_type from_chan_type, + e_rr_type to_chan_type, const t_wire_type_sizes* wire_type_sizes_x, const t_wire_type_sizes* wire_type_sizes_y, const t_switchblock_inf* sb, @@ -262,7 +262,7 @@ static int evaluate_num_conns_formula(t_wireconn_scratchpad* scratchpad, std::st static void get_switchpoint_wires( const DeviceGrid& grid, const t_chan_seg_details* chan_details, - t_rr_type chan_type, + e_rr_type chan_type, int x, int y, e_side side, @@ -292,7 +292,7 @@ static void get_switchpoint_wires( * * @return returns the type of channel that we are indexing into (ie, CHANX or CHANY) and channel coordinates and type */ -static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int tile_layer, enum e_side src_side, enum e_side dest_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, int& chan_x, int& chan_y, int& chan_layer, t_rr_type& chan_type); +static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int tile_layer, enum e_side src_side, enum e_side dest_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, int& chan_x, int& chan_y, int& chan_layer, e_rr_type& chan_type); /** * @brief check whether a specific track location is valid within the device grid @@ -663,7 +663,7 @@ static void count_wire_type_sizes(const t_chan_seg_details* channel, int nodes_p static void get_switchpoint_wires( const DeviceGrid& grid, const t_chan_seg_details* chan_details, - t_rr_type chan_type, + e_rr_type chan_type, int x, int y, e_side side, @@ -773,7 +773,7 @@ static void compute_wire_connections(int x_coord, t_wireconn_scratchpad* scratchpad) { int from_x, from_y, from_layer; /* index into source channel */ int to_x, to_y, to_layer; /* index into destination channel */ - t_rr_type from_chan_type, to_chan_type; /* the type of channel - i.e. CHANX or CHANY */ + e_rr_type from_chan_type, to_chan_type; /* the type of channel - i.e. CHANX or CHANY */ from_x = from_y = to_x = to_y = from_layer = to_layer = UNDEFINED; SB_Side_Connection side_conn(from_side, to_side); /* for indexing into this switchblock's permutation funcs */ @@ -843,8 +843,8 @@ static void compute_wireconn_connections( int to_x, int to_y, int to_layer, - t_rr_type from_chan_type, - t_rr_type to_chan_type, + e_rr_type from_chan_type, + e_rr_type to_chan_type, const t_wire_type_sizes* wire_type_sizes_from, const t_wire_type_sizes* wire_type_sizes_to, const t_switchblock_inf* sb, @@ -1024,7 +1024,7 @@ static int evaluate_num_conns_formula(t_wireconn_scratchpad* scratchpad, std::st return scratchpad->formula_parser.parse_formula(num_conns_formula, vars); } -static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int tile_layer, enum e_side src_side, enum e_side dest_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, int& chan_x, int& chan_y, int& chan_layer, t_rr_type& chan_type) { +static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int tile_layer, enum e_side src_side, enum e_side dest_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, int& chan_x, int& chan_y, int& chan_layer, e_rr_type& chan_type) { chan_type = e_rr_type::CHANX; /* here we use the VPR convention that a tile 'owns' the channels directly to the right * and above it */ diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index 4cd58651181..0eeae4e86cc 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -157,7 +157,7 @@ void check_route(const Netlist<>& net_list, } } - if (rr_graph.node_type(inode) == t_rr_type::SINK) { + if (rr_graph.node_type(inode) == e_rr_type::SINK) { check_sink(net_list, inode, net_pin_index, net_id, pin_done.get()); num_sinks += 1; } @@ -200,7 +200,7 @@ static void check_sink(const Netlist<>& net_list, auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - VTR_ASSERT(rr_graph.node_type(inode) == t_rr_type::SINK); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::SINK); if (net_pin_index == OPEN) { /* If there is no legal net pin index associated with this sink node */ VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -222,8 +222,8 @@ static void check_source(const Netlist<>& net_list, auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type rr_type = rr_graph.node_type(inode); - if (rr_type != t_rr_type::SOURCE) { + e_rr_type rr_type = rr_graph.node_type(inode); + if (rr_type != e_rr_type::SOURCE) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_source: net %d begins with a node of type %d.\n", size_t(net_id), rr_type); } @@ -276,7 +276,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { int from_layer, from_xlow, from_ylow, to_layer, to_xlow, to_ylow, from_ptc, to_ptc, iclass; int num_adj, to_xhigh, to_yhigh, from_xhigh, from_yhigh; bool reached; - t_rr_type from_type, to_type; + e_rr_type from_type, to_type; t_physical_tile_type_ptr from_grid_type, to_grid_type; auto& device_ctx = g_vpr_ctx.device(); @@ -319,7 +319,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { // If to_node is a SINK, it could be anywhere within its containing device grid tile, and it is reasonable for // any input pins or within-cluster pins to reach it. Hence, treat its size as that of its containing tile. - if (to_type == t_rr_type::SINK) { + if (to_type == e_rr_type::SINK) { vtr::Rect tile_bb = device_ctx.grid.get_tile_bb({to_xlow, to_ylow, to_layer}); to_xlow = tile_bb.xmin(); @@ -331,8 +331,8 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { // Layer numbers are should not be more than one layer apart for connected nodes VTR_ASSERT(abs(from_layer - to_layer) <= 1); switch (from_type) { - case t_rr_type::SOURCE: - VTR_ASSERT(to_type == t_rr_type::OPIN); + case e_rr_type::SOURCE: + VTR_ASSERT(to_type == e_rr_type::OPIN); //The OPIN should be contained within the bounding box of it's connected source if (from_xlow <= to_xlow @@ -349,34 +349,34 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case t_rr_type::SINK: + case e_rr_type::SINK: /* SINKS are adjacent to not connected */ break; - case t_rr_type::OPIN: + case e_rr_type::OPIN: from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); - if (to_type == t_rr_type::CHANX || to_type == t_rr_type::CHANY) { + if (to_type == e_rr_type::CHANX || to_type == e_rr_type::CHANY) { num_adj += 1; //adjacent } else if (is_flat) { - VTR_ASSERT(to_type == t_rr_type::OPIN || to_type == t_rr_type::IPIN); // If pin is located inside a cluster + VTR_ASSERT(to_type == e_rr_type::OPIN || to_type == e_rr_type::IPIN); // If pin is located inside a cluster return true; } else { - VTR_ASSERT(to_type == t_rr_type::IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */ + VTR_ASSERT(to_type == e_rr_type::IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */ return true; /* Special case, direct OPIN to IPIN connections need not be adjacent */ } break; - case t_rr_type::IPIN: + case e_rr_type::IPIN: from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); if (is_flat) { - VTR_ASSERT(to_type == t_rr_type::OPIN || to_type == t_rr_type::IPIN || to_type == t_rr_type::SINK); + VTR_ASSERT(to_type == e_rr_type::OPIN || to_type == e_rr_type::IPIN || to_type == e_rr_type::SINK); } else { - VTR_ASSERT(to_type == t_rr_type::SINK); + VTR_ASSERT(to_type == e_rr_type::SINK); } //An IPIN should be contained within the bounding box of its connected sink's tile - if (to_type == t_rr_type::SINK) { + if (to_type == e_rr_type::SINK) { if (from_xlow >= to_xlow && from_ylow >= to_ylow && from_xhigh <= to_xhigh @@ -403,10 +403,10 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case t_rr_type::CHANX: + case e_rr_type::CHANX: if (to_type == e_rr_type::IPIN) { num_adj += 1; //adjacent - } else if (to_type == t_rr_type::CHANX) { + } else if (to_type == e_rr_type::CHANX) { from_xhigh = rr_graph.node_xhigh(from_node); to_xhigh = rr_graph.node_xhigh(to_node); if (from_ylow == to_ylow) { @@ -428,7 +428,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } /* UDSD Modification by WMF End */ } - } else if (to_type == t_rr_type::CHANY) { + } else if (to_type == e_rr_type::CHANY) { num_adj += chanx_chany_adjacent(from_node, to_node); } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -436,10 +436,10 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case t_rr_type::CHANY: + case e_rr_type::CHANY: if (to_type == e_rr_type::IPIN) { num_adj += 1; //adjacent - } else if (to_type == t_rr_type::CHANY) { + } else if (to_type == e_rr_type::CHANY) { from_yhigh = rr_graph.node_yhigh(from_node); to_yhigh = rr_graph.node_yhigh(to_node); if (from_xlow == to_xlow) { @@ -460,7 +460,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } /* UDSD Modification by WMF End */ } - } else if (to_type == t_rr_type::CHANX) { + } else if (to_type == e_rr_type::CHANX) { num_adj += chanx_chany_adjacent(to_node, from_node); } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -551,7 +551,7 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_ bool is_flat) { /* Checks that enough OPINs on CLBs have been set aside (used up) to make a * * legal routing if subblocks connect to OPINs directly. */ - t_rr_type rr_type; + e_rr_type rr_type; auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.device(); @@ -571,7 +571,7 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_ /* Now check that node is an OPIN of the right type. */ rr_type = rr_graph.node_type(RRNodeId(inode)); - if (rr_type != t_rr_type::OPIN) { + if (rr_type != e_rr_type::OPIN) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_locally_used_opins: block #%lu (%s)\n" "\tClass %d local OPIN is wrong rr_type -- rr_node #%d of type %d.\n", @@ -883,7 +883,7 @@ bool StubFinder::RecurseTree(const RouteTreeNode& rt_node) { if (rt_node.is_leaf()) { //If a leaf of the route tree is not a SINK, then it is a stub - if (rr_graph.node_type(rt_node.inode) != t_rr_type::SINK) { + if (rr_graph.node_type(rt_node.inode) != e_rr_type::SINK) { return true; //It is the current root of this stub } else { return false; diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp index 76ec6e85a54..5e50fa25fb8 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/connection_router.cpp @@ -196,7 +196,7 @@ void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId s VTR_ASSERT_SAFE(sink_node != RRNodeId::INVALID()); t_bb target_bb; - if (rr_graph_->node_type(sink_node) == t_rr_type::SINK) { // We need to get a bounding box for the sink's entire tile + if (rr_graph_->node_type(sink_node) == e_rr_type::SINK) { // We need to get a bounding box for the sink's entire tile vtr::Rect tile_bb = grid_.get_tile_bb({rr_graph_->node_xlow(sink_node), rr_graph_->node_ylow(sink_node), rr_graph_->node_layer(sink_node)}); @@ -476,8 +476,8 @@ void ConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode * more promising routes, but makes route-through (via CLBs) impossible. * * Change this if you want to investigate route-throughs. */ if (target_node != RRNodeId::INVALID()) { - t_rr_type to_type = rr_graph_->node_type(to_node); - if (to_type == t_rr_type::IPIN) { + e_rr_type to_type = rr_graph_->node_type(to_node); + if (to_type == e_rr_type::IPIN) { // Check if this IPIN leads to the target block // IPIN's of the target block should be contained within it's bounding box int to_xlow = rr_graph_->node_xlow(to_node); @@ -758,7 +758,7 @@ void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* t //cost. cong_cost = 0.; } - if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == t_rr_type::IPIN) { + if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == e_rr_type::IPIN) { auto find_res = conn_params_->connection_choking_spots_.find(to->index); if (find_res != conn_params_->connection_choking_spots_.end()) { cong_cost = cong_cost / pow(2, (float)find_res->second); @@ -770,9 +770,9 @@ void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* t to->backward_path_cost += cost_params.criticality * Tdel; //Delay cost if (cost_params.bend_cost != 0.) { - t_rr_type from_type = rr_graph_->node_type(from_node); - t_rr_type to_type = rr_graph_->node_type(to->index); - if ((from_type == t_rr_type::CHANX && to_type == t_rr_type::CHANY) || (from_type == t_rr_type::CHANY && to_type == t_rr_type::CHANX)) { + e_rr_type from_type = rr_graph_->node_type(from_node); + e_rr_type to_type = rr_graph_->node_type(to->index); + if ((from_type == e_rr_type::CHANX && to_type == e_rr_type::CHANY) || (from_type == e_rr_type::CHANY && to_type == e_rr_type::CHANX)) { to->backward_path_cost += cost_params.bend_cost; //Bend cost } } @@ -1012,7 +1012,7 @@ t_bb ConnectionRouter::add_high_fanout_route_tree_to_heap( // Expand HF BB to include the node (clip by original BB) expand_highfanout_bounding_box(highfanout_bb, net_bounding_box, rr_node_to_add, rr_graph_); - if (rr_graph_->node_type(rr_node_to_add) == t_rr_type::CHANY || rr_graph_->node_type(rr_node_to_add) == t_rr_type::CHANX) { + if (rr_graph_->node_type(rr_node_to_add) == e_rr_type::CHANY || rr_graph_->node_type(rr_node_to_add) == e_rr_type::CHANX) { chan_nodes_added++; } } @@ -1045,7 +1045,7 @@ t_bb ConnectionRouter::add_high_fanout_route_tree_to_heap( static inline bool relevant_node_to_target(const RRGraphView* rr_graph, RRNodeId node_to_add, RRNodeId target_node) { - VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == t_rr_type::SINK); + VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == e_rr_type::SINK); auto node_to_add_type = rr_graph->node_type(node_to_add); return node_to_add_type != e_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); } @@ -1062,7 +1062,7 @@ static inline void update_router_stats(RouterStats* router_stats, if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { auto node_type = rr_graph->node_type(rr_node_id); - VTR_ASSERT(node_type != t_rr_type::NUM_RR_TYPES); + VTR_ASSERT(node_type != e_rr_type::NUM_RR_TYPES); if (is_inter_cluster_node(*rr_graph, rr_node_id)) { if (is_push) { diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 86773a32445..028a4e85e70 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -130,7 +130,7 @@ void report_overused_nodes(const Netlist<>& net_list, int y = rr_graph.node_ylow(node_id); int layer_num = rr_graph.node_layer(node_id); switch (node_type) { - case t_rr_type::IPIN: + case e_rr_type::IPIN: case e_rr_type::OPIN: report_overused_ipin_opin(os, node_id, @@ -139,12 +139,12 @@ void report_overused_nodes(const Netlist<>& net_list, x -= g_vpr_ctx.device().grid.get_physical_type({x, y, layer_num})->width; y -= g_vpr_ctx.device().grid.get_physical_type({x, y, layer_num})->width; break; - case t_rr_type::CHANX: - case t_rr_type::CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: report_overused_chanx_chany(os, node_id); break; - case t_rr_type::SOURCE: - case t_rr_type::SINK: + case e_rr_type::SOURCE: + case e_rr_type::SINK: report_overused_source_sink(os, node_id); report_sinks = true; break; @@ -484,7 +484,7 @@ static void print_block_pins_nets(std::ostream& os, } for (int pin = pin_num_range.low; pin <= pin_num_range.high; pin++) { - t_rr_type rr_type = (get_pin_type_from_pin_physical_num(physical_type, pin) == DRIVER) ? t_rr_type::OPIN : t_rr_type::IPIN; + e_rr_type rr_type = (get_pin_type_from_pin_physical_num(physical_type, pin) == DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; RRNodeId node_id = get_pin_rr_node_id(rr_graph.node_lookup(), physical_type, layer, root_x, root_y, pin); // When flat router is enabled, RR Node chains collapse into a single node. Thus, when // looking up the RR Node ID, it may return an invalid node ID. In this case, we skip @@ -494,10 +494,10 @@ static void print_block_pins_nets(std::ostream& os, } VTR_ASSERT(node_id.is_valid()); auto search_result = rr_node_to_net_map.find(node_id); - if (rr_type == t_rr_type::OPIN) { + if (rr_type == e_rr_type::OPIN) { os << " OPIN - "; } else { - VTR_ASSERT(rr_type == t_rr_type::IPIN); + VTR_ASSERT(rr_type == e_rr_type::IPIN); os << " IPIN - "; } os << "RRNodeId: " << size_t(node_id) << " - Physical Num: " << pin << "\n"; diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index 0712bb1f738..fc240344163 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -618,7 +618,7 @@ bool route(const Netlist<>& net_list, "total_internal_heap_pushes: %zu total_internal_heap_pops: %zu total_external_heap_pushes: %zu total_external_heap_pops: %zu ", router_stats.intra_cluster_node_pushes, router_stats.intra_cluster_node_pops, router_stats.inter_cluster_node_pushes, router_stats.inter_cluster_node_pops); - for (int node_type_idx = 0; node_type_idx < (int)t_rr_type::NUM_RR_TYPES; node_type_idx++) { + for (int node_type_idx = 0; node_type_idx < (int)e_rr_type::NUM_RR_TYPES; node_type_idx++) { VTR_LOG("total_external_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.inter_cluster_node_type_cnt_pushes[node_type_idx]); VTR_LOG("total_external_%s_pops: %zu ", rr_node_typename[node_type_idx], router_stats.inter_cluster_node_type_cnt_pops[node_type_idx]); VTR_LOG("total_internal_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.intra_cluster_node_type_cnt_pushes[node_type_idx]); diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 038b6aee6f2..68701b46731 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -474,7 +474,7 @@ static vtr::vector> load_net_rr_terminals(con tile_bb.ymin(), tile_bb.xmax(), tile_bb.ymax(), - t_rr_type::SINK, + e_rr_type::SINK, iclass); VTR_ASSERT_SAFE(sink_nodes.size() == 1); inode = sink_nodes[0]; @@ -566,7 +566,7 @@ static vtr::vector> load_rr_clb_sources(con bool is_flat) { vtr::vector> rr_blk_source; - t_rr_type rr_type; + e_rr_type rr_type; rr_blk_source.resize(net_list.blocks().size()); diff --git a/vpr/src/route/route_net.cpp b/vpr/src/route/route_net.cpp index 7f032b0dcca..4d89ae04cfe 100644 --- a/vpr/src/route/route_net.cpp +++ b/vpr/src/route/route_net.cpp @@ -228,7 +228,7 @@ size_t calculate_wirelength_available() { size_t available_wirelength = 0; // But really what's happening is that this for loop iterates over every node and determines the available wirelength for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { - const t_rr_type channel_type = rr_graph.node_type(rr_id); + const e_rr_type channel_type = rr_graph.node_type(rr_id); if (channel_type == e_rr_type::CHANX || channel_type == e_rr_type::CHANY) { available_wirelength += rr_graph.node_capacity(rr_id) * rr_graph.node_length(rr_id); } diff --git a/vpr/src/route/route_profiling.cpp b/vpr/src/route/route_profiling.cpp index dffa3f59446..dd87ee57e28 100644 --- a/vpr/src/route/route_profiling.cpp +++ b/vpr/src/route/route_profiling.cpp @@ -148,7 +148,7 @@ struct Congested_node_types { void congestion_analysis() { #if 0 // each type indexes into array which holds the congestion for that type - std::vector congestion_per_type((size_t)t_rr_type::NUM_RR_TYPES, 0); + std::vector congestion_per_type((size_t)e_rr_type::NUM_RR_TYPES, 0); // print out specific node information if congestion for type is low enough int total_congestion = 0; @@ -164,7 +164,7 @@ void congestion_analysis() { constexpr int specific_node_print_threshold = 5; Congested_node_types congested; - for (int type = SOURCE; type < t_rr_type::NUM_RR_TYPES; ++type) { + for (int type = SOURCE; type < e_rr_type::NUM_RR_TYPES; ++type) { float congestion_percentage = (float)congestion_per_type[type] / (float) total_congestion * 100; VTR_LOG(" %6s: %10.6f %\n", node_typename[type], congestion_percentage); // nodes of that type need specific printing diff --git a/vpr/src/route/route_utilization.cpp b/vpr/src/route/route_utilization.cpp index c2aeb155ab2..53badb9297c 100644 --- a/vpr/src/route/route_utilization.cpp +++ b/vpr/src/route/route_utilization.cpp @@ -3,7 +3,7 @@ #include "draw_types.h" #include "draw_global.h" -vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool is_print) { +vtr::Matrix calculate_routing_usage(e_rr_type rr_type, bool is_flat, bool is_print) { VTR_ASSERT(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); const auto& device_ctx = g_vpr_ctx.device(); @@ -63,7 +63,7 @@ vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool return usage; } -vtr::Matrix calculate_routing_avail(t_rr_type rr_type) { +vtr::Matrix calculate_routing_avail(e_rr_type rr_type) { //Calculate the number of available resources in each x/y channel VTR_ASSERT(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); diff --git a/vpr/src/route/route_utilization.h b/vpr/src/route/route_utilization.h index ba8d6995738..194df6deb14 100644 --- a/vpr/src/route/route_utilization.h +++ b/vpr/src/route/route_utilization.h @@ -4,7 +4,7 @@ #include "draw_types.h" #include "draw_global.h" -vtr::Matrix calculate_routing_avail(t_rr_type rr_type); +vtr::Matrix calculate_routing_avail(e_rr_type rr_type); /** * @brief: Calculates and returns the usage over the entire grid for the specified @@ -15,7 +15,7 @@ vtr::Matrix calculate_routing_avail(t_rr_type rr_type); * @param only_visible: If true, only record the usage of rr_nodes on layers that are visible according to the current * drawing settings. */ -vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool is_print); +vtr::Matrix calculate_routing_usage(e_rr_type rr_type, bool is_flat, bool is_print); float routing_util(float used, float avail); #endif diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead.cpp index 17bb64a7b4e..fb2849cecf6 100644 --- a/vpr/src/route/router_lookahead.cpp +++ b/vpr/src/route/router_lookahead.cpp @@ -71,7 +71,7 @@ std::pair ClassicLookahead::get_expected_delay_and_cong(RRNodeId n auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type rr_type = rr_graph.node_type(node); + e_rr_type rr_type = rr_graph.node_type(node); if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { auto [num_segs_same_dir, num_segs_ortho_dir] = get_expected_segs_to_target(node, target_node); @@ -139,7 +139,7 @@ static std::pair get_expected_segs_to_target(RRNodeId inode, RRNodeId float inv_length = device_ctx.rr_indexed_data[cost_index].inv_length; int ortho_cost_index = device_ctx.rr_indexed_data[cost_index].ortho_cost_index; float ortho_inv_length = device_ctx.rr_indexed_data[RRIndexedDataId(ortho_cost_index)].inv_length; - t_rr_type rr_type = rr_graph.node_type(inode); + e_rr_type rr_type = rr_graph.node_type(inode); if (rr_type == e_rr_type::CHANX) { ylow = rr_graph.node_ylow(inode); diff --git a/vpr/src/route/router_lookahead_compressed_map.cpp b/vpr/src/route/router_lookahead_compressed_map.cpp index 0b7ea09a62c..e45593f68e8 100644 --- a/vpr/src/route/router_lookahead_compressed_map.cpp +++ b/vpr/src/route/router_lookahead_compressed_map.cpp @@ -146,14 +146,14 @@ static void compute_router_wire_compressed_lookahead(const std::vector> sample_nodes; + std::map> sample_nodes; std::vector chan_types; if (segment_inf.parallel_axis == X_AXIS) - chan_types.push_back(t_rr_type::CHANX); + chan_types.push_back(e_rr_type::CHANX); else if (segment_inf.parallel_axis == Y_AXIS) - chan_types.push_back(t_rr_type::CHANY); + chan_types.push_back(e_rr_type::CHANY); else //Both for BOTH_AXIS segments and special segments such as clock_networks we want to search in both directions. - chan_types.insert(chan_types.end(), {t_rr_type::CHANX, t_rr_type::CHANY}); + chan_types.insert(chan_types.end(), {e_rr_type::CHANX, e_rr_type::CHANY}); for (e_rr_type chan_type : chan_types) { util::t_routing_cost_map routing_cost_map = util::get_routing_cost_map(longest_seg_length, @@ -180,7 +180,7 @@ static void compute_router_wire_compressed_lookahead(const std::vector CompressedMapLookahead::get_expected_delay_and_cong(RRNo float expected_cong_cost = std::numeric_limits::infinity(); e_rr_type from_type = rr_graph.node_type(from_node); - if (from_type == t_rr_type::SOURCE || from_type == t_rr_type::OPIN) { + if (from_type == e_rr_type::SOURCE || from_type == e_rr_type::OPIN) { //When estimating costs from a SOURCE/OPIN we look-up to find which wire types (and the //cost to reach them) in src_opin_delays. Once we know what wire types are //reachable, we query the f_wire_cost_map (i.e. the wire lookahead) to get the final @@ -472,7 +472,7 @@ std::pair CompressedMapLookahead::get_expected_delay_and_cong(RRNo .c_str()) .c_str()); - } else if (from_type == t_rr_type::CHANX || from_type == t_rr_type::CHANY) { + } else if (from_type == e_rr_type::CHANX || from_type == e_rr_type::CHANY) { //When estimating costs from a wire, we directly look-up the result in the wire lookahead (f_wire_cost_map) auto from_cost_index = rr_graph.node_cost_index(from_node); @@ -502,7 +502,7 @@ std::pair CompressedMapLookahead::get_expected_delay_and_cong(RRNo .c_str()); expected_delay_cost = cost_entry.delay * params.criticality; expected_cong_cost = cost_entry.congestion * (1 - params.criticality); - } else if (from_type == t_rr_type::IPIN) { /* Change if you're allowing route-throughs */ + } else if (from_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ return std::make_pair(0., device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost); } else { /* Change this if you want to investigate route-throughs */ return std::make_pair(0., 0.); diff --git a/vpr/src/route/router_lookahead_extended_map.cpp b/vpr/src/route/router_lookahead_extended_map.cpp index e7d774e49cd..8ae1c02f708 100644 --- a/vpr/src/route/router_lookahead_extended_map.cpp +++ b/vpr/src/route/router_lookahead_extended_map.cpp @@ -586,7 +586,7 @@ float ExtendedMapLookahead::get_expected_cost( auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type rr_type = rr_graph.node_type(current_node); + e_rr_type rr_type = rr_graph.node_type(current_node); if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY || rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::OPIN) { float delay_cost, cong_cost; diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 2d5972acabe..b8782a45c5a 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -167,9 +167,9 @@ float MapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId target_nod auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type from_rr_type = rr_graph.node_type(current_node); + e_rr_type from_rr_type = rr_graph.node_type(current_node); - VTR_ASSERT_SAFE(rr_graph.node_type(target_node) == t_rr_type::SINK); + VTR_ASSERT_SAFE(rr_graph.node_type(target_node) == e_rr_type::SINK); if (is_flat_) { return get_expected_cost_flat_router(current_node, target_node, params, R_upstream); @@ -190,9 +190,9 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type from_rr_type = rr_graph.node_type(current_node); + e_rr_type from_rr_type = rr_graph.node_type(current_node); - VTR_ASSERT_SAFE(rr_graph.node_type(target_node) == t_rr_type::SINK); + VTR_ASSERT_SAFE(rr_graph.node_type(target_node) == e_rr_type::SINK); float delay_cost = 0.; float cong_cost = 0.; diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 6c626d7df1a..7d1ed4889fb 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -544,7 +544,7 @@ t_ipin_primitive_sink_delays compute_intra_tile_dijkstra(const RRGraphView& rr_g } /* returns index of a node from which to start routing */ -RRNodeId get_start_node(int layer, int start_x, int start_y, int target_x, int target_y, t_rr_type rr_type, int seg_index, int track_offset) { +RRNodeId get_start_node(int layer, int start_x, int start_y, int target_x, int target_y, e_rr_type rr_type, int seg_index, int track_offset) { auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; const auto& node_lookup = rr_graph.node_lookup(); @@ -1254,7 +1254,7 @@ static void run_intra_tile_dijkstra(const RRGraphView& rr_graph, node_expanded[curr.node] = true; } auto curr_type = rr_graph.node_type(curr.node); - VTR_ASSERT(curr_type != t_rr_type::CHANX && curr_type != t_rr_type::CHANY); + VTR_ASSERT(curr_type != e_rr_type::CHANX && curr_type != e_rr_type::CHANY); if (curr_type != e_rr_type::SINK) { for (RREdgeId edge : rr_graph.edge_range(curr.node)) { RRNodeId next_node = rr_graph.rr_nodes().edge_sink_node(edge); diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index 217bd0d2206..6222a71967f 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -325,7 +325,7 @@ t_ipin_primitive_sink_delays compute_intra_tile_dijkstra(const RRGraphView& rr_g int y); /* returns index of a node from which to start routing */ -RRNodeId get_start_node(int layer, int start_x, int start_y, int target_x, int target_y, t_rr_type rr_type, int seg_index, int track_offset); +RRNodeId get_start_node(int layer, int start_x, int start_y, int target_x, int target_y, e_rr_type rr_type, int seg_index, int track_offset); /** * @brief Computes the absolute delta_x and delta_y offset diff --git a/vpr/src/route/router_stats.h b/vpr/src/route/router_stats.h index 176455c80e6..01b9ee03ee0 100644 --- a/vpr/src/route/router_stats.h +++ b/vpr/src/route/router_stats.h @@ -38,13 +38,13 @@ struct RouterStats { size_t inter_cluster_node_pops = 0; size_t intra_cluster_node_pushes = 0; size_t intra_cluster_node_pops = 0; - size_t inter_cluster_node_type_cnt_pushes[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; - size_t inter_cluster_node_type_cnt_pops[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; - size_t intra_cluster_node_type_cnt_pushes[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; - size_t intra_cluster_node_type_cnt_pops[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; + size_t inter_cluster_node_type_cnt_pushes[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; + size_t inter_cluster_node_type_cnt_pops[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; + size_t intra_cluster_node_type_cnt_pushes[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; + size_t intra_cluster_node_type_cnt_pops[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; // For debugging purposes - size_t rt_node_pushes[(size_t)t_rr_type::NUM_RR_TYPES] = {0}; + size_t rt_node_pushes[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; /** Add rhs's stats to mine */ void combine(RouterStats& rhs) { @@ -56,7 +56,7 @@ struct RouterStats { heap_pops += rhs.heap_pops; inter_cluster_node_pops += rhs.inter_cluster_node_pops; intra_cluster_node_pops += rhs.intra_cluster_node_pops; - for (size_t node_type_idx = 0; node_type_idx < (size_t)t_rr_type::NUM_RR_TYPES; node_type_idx++) { + for (size_t node_type_idx = 0; node_type_idx < (size_t)e_rr_type::NUM_RR_TYPES; node_type_idx++) { inter_cluster_node_type_cnt_pushes[node_type_idx] += rhs.inter_cluster_node_type_cnt_pushes[node_type_idx]; inter_cluster_node_type_cnt_pops[node_type_idx] += rhs.inter_cluster_node_type_cnt_pops[node_type_idx]; intra_cluster_node_type_cnt_pushes[node_type_idx] += rhs.intra_cluster_node_type_cnt_pushes[node_type_idx]; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index cbb24825014..a6219c5b896 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -518,7 +518,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, const int layer, const int x_coord, const int y_coord, - const t_rr_type chan_type, + const e_rr_type chan_type, const t_track_to_pin_lookup& track_to_pin_lookup, t_sb_connection_map* sb_conn_map, const vtr::NdMatrix, 3>& switch_block_conn, @@ -1462,11 +1462,11 @@ static void build_rr_graph(e_graph_type graph_type, // clock_modeling::DEDICATED_NETWORK will append some rr nodes after // the regular graph. for (int i = 0; i < num_rr_nodes; i++) { - if (rr_graph.node_type(RRNodeId(i)) == t_rr_type::CHANX) { + if (rr_graph.node_type(RRNodeId(i)) == e_rr_type::CHANX) { int ylow = rr_graph.node_ylow(RRNodeId(i)); device_ctx.rr_graph_builder.set_node_capacity(RRNodeId(i), nodes_per_chan.x_list[ylow]); } - if (rr_graph.node_type(RRNodeId(i)) == t_rr_type::CHANY) { + if (rr_graph.node_type(RRNodeId(i)) == e_rr_type::CHANY) { int xlow = rr_graph.node_xlow(RRNodeId(i)); device_ctx.rr_graph_builder.set_node_capacity(RRNodeId(i), nodes_per_chan.y_list[xlow]); } @@ -1479,7 +1479,7 @@ static void build_rr_graph(e_graph_type graph_type, for (int rr_node_id = 0; rr_node_id < num_rr_nodes; rr_node_id++) { auto node_type = rr_graph.node_type(RRNodeId(rr_node_id)); auto node_dir = rr_graph.node_direction(RRNodeId(rr_node_id)); - if (node_type != t_rr_type::CHANX && node_type != t_rr_type::CHANY) { //SRC/SINK/IPIN/OPIN + if (node_type != e_rr_type::CHANX && node_type != e_rr_type::CHANY) { //SRC/SINK/IPIN/OPIN device_ctx.rr_graph_builder.set_node_ptc_twist_incr(RRNodeId(rr_node_id), 0); } else { //The current ptc twist increment number in UNDIR TILEABLE RRGraph is 2 and -2 @@ -2246,7 +2246,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder if (i > 0) { int tracks_per_chan = ((is_global_graph) ? 1 : chan_width.x_list[j]); - build_rr_chan(rr_graph_builder, layer, i, j, t_rr_type::CHANX, track_to_pin_lookup_x, sb_conn_map, + build_rr_chan(rr_graph_builder, layer, i, j, e_rr_type::CHANX, track_to_pin_lookup_x, sb_conn_map, switch_block_conn, num_of_3d_conns_custom_SB, CHANX_COST_INDEX_START, chan_width, grid, tracks_per_chan, @@ -2267,7 +2267,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } if (j > 0) { int tracks_per_chan = ((is_global_graph) ? 1 : chan_width.y_list[i]); - build_rr_chan(rr_graph_builder, layer, i, j, t_rr_type::CHANY, track_to_pin_lookup_y, sb_conn_map, + build_rr_chan(rr_graph_builder, layer, i, j, e_rr_type::CHANY, track_to_pin_lookup_y, sb_conn_map, switch_block_conn, num_of_3d_conns_custom_SB, CHANX_COST_INDEX_START + num_seg_types_x, chan_width, grid, tracks_per_chan, @@ -2456,12 +2456,12 @@ static void add_classes_rr_graph(RRGraphBuilder& rr_graph_builder, int class_num_pins = get_class_num_pins_from_class_physical_num(physical_type, class_num); if (class_type == DRIVER) { rr_graph_builder.set_node_cost_index(class_inode, RRIndexedDataId(SOURCE_COST_INDEX)); - rr_graph_builder.set_node_type(class_inode, t_rr_type::SOURCE); + rr_graph_builder.set_node_type(class_inode, e_rr_type::SOURCE); } else { VTR_ASSERT(class_type == RECEIVER); rr_graph_builder.set_node_cost_index(class_inode, RRIndexedDataId(SINK_COST_INDEX)); - rr_graph_builder.set_node_type(class_inode, t_rr_type::SINK); + rr_graph_builder.set_node_type(class_inode, e_rr_type::SINK); } VTR_ASSERT(class_num_pins <= std::numeric_limits::max()); rr_graph_builder.set_node_capacity(class_inode, (short)class_num_pins); @@ -2496,7 +2496,7 @@ static void add_pins_rr_graph(RRGraphBuilder& rr_graph_builder, int x_offset = x_offset_vec[pin_coord]; int y_offset = y_offset_vec[pin_coord]; e_side pin_side = pin_sides_vec[pin_coord]; - auto node_type = (pin_type == DRIVER) ? t_rr_type::OPIN : t_rr_type::IPIN; + auto node_type = (pin_type == DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; RRNodeId node_id = node_lookup.find_node(layer, i + x_offset, j + y_offset, @@ -2717,7 +2717,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, total_pin_Fc += Fc[pin_index][iseg]; } - RRNodeId node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, t_rr_type::OPIN, pin_index, side); + RRNodeId node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, e_rr_type::OPIN, pin_index, side); VTR_ASSERT(node_index); for (auto connected_layer : get_layers_pin_is_connected_to(type, layer, pin_index)) { @@ -3134,7 +3134,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, const int layer, const int x_coord, const int y_coord, - const t_rr_type chan_type, + const e_rr_type chan_type, const t_track_to_pin_lookup& track_to_pin_lookup, t_sb_connection_map* sb_conn_map, const vtr::NdMatrix, 3>& switch_block_conn, @@ -3165,14 +3165,14 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, int chan_coord = y_coord; //The absolute coordinate of this channel within the device int seg_dimension = device_ctx.grid.width() - 2; //-2 for no perim channels int chan_dimension = device_ctx.grid.height() - 2; //-2 for no perim channels - const t_chan_details& from_chan_details = (chan_type == t_rr_type::CHANX) ? chan_details_x : chan_details_y; - const t_chan_details& opposite_chan_details = (chan_type == t_rr_type::CHANX) ? chan_details_y : chan_details_x; - t_rr_type opposite_chan_type = t_rr_type::CHANY; - if (chan_type == t_rr_type::CHANY) { + const t_chan_details& from_chan_details = (chan_type == e_rr_type::CHANX) ? chan_details_x : chan_details_y; + const t_chan_details& opposite_chan_details = (chan_type == e_rr_type::CHANX) ? chan_details_y : chan_details_x; + e_rr_type opposite_chan_type = e_rr_type::CHANY; + if (chan_type == e_rr_type::CHANY) { //Swap values since CHANX was assumed above std::swap(seg_coord, chan_coord); std::swap(seg_dimension, chan_dimension); - opposite_chan_type = t_rr_type::CHANX; + opposite_chan_type = e_rr_type::CHANX; } const t_chan_seg_details* seg_details = from_chan_details[x_coord][y_coord].data(); @@ -3201,7 +3201,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(seg_coord == start); const t_chan_seg_details* from_seg_details = nullptr; - if (chan_type == t_rr_type::CHANY) { + if (chan_type == e_rr_type::CHANY) { from_seg_details = chan_details_y[x_coord][start].data(); } else { from_seg_details = chan_details_x[start][y_coord].data(); @@ -3222,11 +3222,11 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, if (chan_coord > 0) { const t_chan_seg_details* to_seg_details; int max_opposite_chan_width; - if (chan_type == t_rr_type::CHANX) { + if (chan_type == e_rr_type::CHANX) { to_seg_details = chan_details_y[start][y_coord].data(); max_opposite_chan_width = nodes_per_chan.y_max; } else { - VTR_ASSERT(chan_type == t_rr_type::CHANY); + VTR_ASSERT(chan_type == e_rr_type::CHANY); to_seg_details = chan_details_x[x_coord][start].data(); max_opposite_chan_width = nodes_per_chan.x_max; } @@ -3246,7 +3246,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, to_seg_details = chan_details_y[start][y_coord + 1].data(); max_opposite_chan_width = nodes_per_chan.y_max; } else { - VTR_ASSERT(chan_type == t_rr_type::CHANY); + VTR_ASSERT(chan_type == e_rr_type::CHANY); to_seg_details = chan_details_x[x_coord + 1][start].data(); max_opposite_chan_width = nodes_per_chan.x_max; } @@ -3278,7 +3278,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, to_seg_details = chan_details_x[target_seg][y_coord].data(); max_chan_width = nodes_per_chan.x_max; } else { - VTR_ASSERT(chan_type == t_rr_type::CHANY); + VTR_ASSERT(chan_type == e_rr_type::CHANY); to_seg_details = chan_details_y[x_coord][target_seg].data(); max_chan_width = nodes_per_chan.y_max; } @@ -3305,7 +3305,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, if (chan_type == e_rr_type::CHANX) { rr_graph_builder.set_node_coordinates(node, start, y_coord, end, y_coord); } else { - VTR_ASSERT(chan_type == t_rr_type::CHANY); + VTR_ASSERT(chan_type == e_rr_type::CHANY); rr_graph_builder.set_node_coordinates(node, x_coord, start, x_coord, end); } @@ -4210,7 +4210,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, continue; } - RRNodeId opin_node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, t_rr_type::OPIN, pin_index, side); + RRNodeId opin_node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, e_rr_type::OPIN, pin_index, side); if (!opin_node_index) continue; //No valid from node for (int iseg = 0; iseg < num_seg_types; iseg++) { @@ -4230,7 +4230,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, * side is the side of the logic or io block. */ bool vert = ((side == TOP) || (side == BOTTOM)); bool pos_dir = ((side == TOP) || (side == RIGHT)); - t_rr_type chan_type = (vert ? e_rr_type::CHANX : t_rr_type::CHANY); + e_rr_type chan_type = (vert ? e_rr_type::CHANX : e_rr_type::CHANY); int chan = (vert ? (j) : (i)); int seg = (vert ? (i) : (j)); int max_len = (vert ? grid.width() : grid.height()); @@ -4623,7 +4623,7 @@ static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_gr //candidate would be picked (i.e. to minimize the drawn edge length). // //This function attempts to pick the 'best/closest' of the candidates. - VTR_ASSERT(rr_graph.node_type(from_rr) == t_rr_type::OPIN); + VTR_ASSERT(rr_graph.node_type(from_rr) == e_rr_type::OPIN); float best_dist = std::numeric_limits::infinity(); RRNodeId best_rr = RRNodeId::INVALID(); diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index a4ccb673440..a166276c021 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -28,7 +28,7 @@ static void load_chan_rr_indices(const int max_chan_width, const DeviceGrid& grid, const int chan_len, const int num_chans, - const t_rr_type type, + const e_rr_type type, const t_chan_details& chan_details, RRGraphBuilder& rr_graph_builder, int* index); @@ -63,7 +63,7 @@ static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int to_chan, const int to_seg, const int to_sb, - const t_rr_type to_type, + const e_rr_type to_type, const t_chan_seg_details* seg_details, const bool from_is_sblock, const int from_switch, @@ -78,7 +78,7 @@ static int get_unidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int to_chan, const int to_seg, const int to_sb, - const t_rr_type to_type, + const e_rr_type to_type, const int max_chan_width, const DeviceGrid& grid, const enum e_side from_side, @@ -122,7 +122,7 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder, const e_side to_side, const int to_x, const int to_y, - const t_rr_type to_chan_type, + const e_rr_type to_chan_type, const int switch_override, const int custom_3d_sb_fanin_fanout, const int delayless_switch, @@ -158,7 +158,7 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int from_track, const int to_chan, const int to_seg, - const t_rr_type to_chan_type, + const e_rr_type to_chan_type, const e_side from_side, const e_side to_side, const int swtich_override, @@ -249,7 +249,7 @@ void dump_seg_details(t_seg_details* seg_details, // from_seg_coord: The horizontal or vertical location along the channel (i.e. y-coord for CHANY, x-coord for CHANX) // from_chan_type: The from channel type // to_chan_type: The to channel type -static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int from_chan_coord, int from_seg_coord, t_rr_type from_chan_type, t_rr_type to_chan_type); +static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int from_chan_coord, int from_seg_coord, e_rr_type from_chan_type, e_rr_type to_chan_type); static bool should_apply_switch_override(int switch_override); @@ -693,7 +693,7 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, int to_switch; int is_connected_track; t_physical_tile_type_ptr type; - t_rr_type to_type; + e_rr_type to_type; auto& device_ctx = g_vpr_ctx.device(); @@ -781,7 +781,7 @@ int get_unidir_opin_connections(RRGraphBuilder& rr_graph_builder, const int seg, int Fc, const int seg_type_index, - const t_rr_type chan_type, + const e_rr_type chan_type, const t_chan_seg_details* seg_details, RRNodeId from_rr_node, t_rr_edge_info_set& rr_edges_to_create, @@ -1083,7 +1083,7 @@ static void load_chan_rr_indices(const int max_chan_width, const DeviceGrid& grid, const int chan_len, const int num_chans, - const t_rr_type type, + const e_rr_type type, const t_chan_details& chan_details, RRGraphBuilder& rr_graph_builder, int* index) { @@ -1452,7 +1452,7 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, * of the *first* rr_node at a given (i,j) location. */ /* Alloc the lookup table */ - for (t_rr_type rr_type : RR_TYPES) { + for (e_rr_type rr_type : RR_TYPES) { if (rr_type == e_rr_type::CHANX) { rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.height(), grid.width(), rr_type, NUM_2D_SIDES); } else { @@ -1541,7 +1541,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, for (int l = 0; l < layer; ++l) { for (int x = 0; x < width; ++x) { for (int y = 0; y < height; ++y) { - for (t_rr_type rr_type : RR_TYPES) { + for (e_rr_type rr_type : RR_TYPES) { /* Get the list of nodes at a specific location (x, y) */ std::vector nodes_from_lookup; if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { @@ -1794,9 +1794,9 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, const int from_chan, const int from_seg, const int from_track, - const t_rr_type from_type, + const e_rr_type from_type, const int to_seg, - const t_rr_type to_type, + const e_rr_type to_type, const int chan_len, const int max_chan_width, const DeviceGrid& grid, @@ -2056,7 +2056,7 @@ static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int to_chan, const int to_seg, const int to_sb, - const t_rr_type to_type, + const e_rr_type to_type, const t_chan_seg_details* seg_details, const bool from_is_sblock, const int from_switch, @@ -2125,7 +2125,7 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder, const e_side to_side, const int to_x, const int to_y, - const t_rr_type to_chan_type, + const e_rr_type to_chan_type, const int switch_override, const int custom_3d_sb_fanin_fanout, const int delayless_switch, @@ -2238,7 +2238,7 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int from_wire, const int to_chan, const int to_seg, - const t_rr_type to_chan_type, + const e_rr_type to_chan_type, const e_side from_side, const e_side to_side, const int switch_override, @@ -2322,7 +2322,7 @@ static int get_unidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int to_chan, const int to_seg, const int to_sb, - const t_rr_type to_type, + const e_rr_type to_type, const int max_chan_width, const DeviceGrid& grid, const enum e_side from_side, @@ -2999,7 +2999,7 @@ static int find_label_of_track(const std::vector& wire_mux_on_track, return i_label; } -static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int from_chan_coord, int from_seg_coord, t_rr_type from_chan_type, t_rr_type to_chan_type) { +static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int from_chan_coord, int from_seg_coord, e_rr_type from_chan_type, e_rr_type to_chan_type) { //Convert the chan/seg indices to real x/y coordinates int y_coord; int x_coord; diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h index 71b7004197f..b783e993d6b 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph2.h @@ -139,7 +139,7 @@ int get_unidir_opin_connections(RRGraphBuilder& rr_graph_builder, const int seg, int Fc, const int seg_type_index, - const t_rr_type chan_type, + const e_rr_type chan_type, const t_chan_seg_details* seg_details, RRNodeId from_rr_node, t_rr_edge_info_set& rr_edges_to_create, @@ -169,9 +169,9 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, const int from_chan, const int from_seg, const int from_track, - const t_rr_type from_type, + const e_rr_type from_type, const int to_seg, - const t_rr_type to_type, + const e_rr_type to_type, const int chan_len, const int max_chan_width, const DeviceGrid& grid, diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp index ed5a8f351cc..c026d12a1a1 100644 --- a/vpr/src/route/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_area.cpp @@ -117,7 +117,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl float* shared_buffer_trans; /* [0..max(device_ctx.grid.width(),device_ctx.grid.height())] */ float *unsharable_switch_trans, *sharable_switch_trans; /* [0..num_switch-1] */ - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; int iedge, num_edges, maxlen; int iswitch, i, j, iseg, max_inputs_to_cblock; float input_cblock_trans, shared_opin_buffer_trans; @@ -322,7 +322,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* /* corresponding to IPINs will be 0. */ - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; int i, j, iseg, iedge, num_edges, maxlen; int max_inputs_to_cblock; float input_cblock_trans; diff --git a/vpr/src/route/rr_graph_sbox.h b/vpr/src/route/rr_graph_sbox.h index 87843f57a1a..d50d9a50edb 100644 --- a/vpr/src/route/rr_graph_sbox.h +++ b/vpr/src/route/rr_graph_sbox.h @@ -6,10 +6,10 @@ std::vector get_switch_box_tracks(const int from_i, const int from_j, const int from_track, - const t_rr_type from_type, + const e_rr_type from_type, const int to_i, const int to_j, - const t_rr_type to_type, + const e_rr_type to_type, const std::vector*** switch_block_conn); vtr::NdMatrix, 3> alloc_and_load_switch_block_conn(t_chan_width* nodes_per_chan, diff --git a/vpr/src/route/rr_graph_timing_params.cpp b/vpr/src/route/rr_graph_timing_params.cpp index 754848fae74..71316392626 100644 --- a/vpr/src/route/rr_graph_timing_params.cpp +++ b/vpr/src/route/rr_graph_timing_params.cpp @@ -26,7 +26,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { size_t to_node; int icblock, isblock, iseg_low, iseg_high; float Cin, Cout; - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; bool* cblock_counted; /* [0..maxlen-1] -- 0th element unused. */ float* buffer_Cin; /* [0..maxlen-1] */ bool buffered; @@ -53,12 +53,12 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { from_rr_type = rr_graph.node_type(rr_id); - if ((from_rr_type == t_rr_type::CHANX || from_rr_type == t_rr_type::CHANY)) { + if ((from_rr_type == e_rr_type::CHANX || from_rr_type == e_rr_type::CHANY)) { for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) { to_node = size_t(rr_graph.edge_sink_node(rr_id, iedge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY) { + if (to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY) { switch_index = rr_graph.edge_switch(rr_id, iedge); Cin = rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cin; Cout = rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cout; @@ -99,7 +99,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { } /* End edge to CHANX or CHANY node. */ - else if (to_rr_type == t_rr_type::IPIN) { + else if (to_rr_type == e_rr_type::IPIN) { if (INCLUDE_TRACK_BUFFERS) { /* Implements sharing of the track to connection box buffer. * Such a buffer exists at every segment of the wire at which @@ -129,7 +129,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { * } * } */ - if (from_rr_type == t_rr_type::CHANX) { + if (from_rr_type == e_rr_type::CHANX) { iseg_low = rr_graph.node_xlow(rr_id); iseg_high = rr_graph.node_xhigh(rr_id); } else { /* CHANY */ @@ -148,13 +148,13 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { } /* End node is CHANX or CHANY */ - else if (from_rr_type == t_rr_type::OPIN) { + else if (from_rr_type == e_rr_type::OPIN) { for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) { switch_index = rr_graph.edge_switch(rr_id, iedge); to_node = size_t(rr_graph.edge_sink_node(rr_id, iedge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type != t_rr_type::CHANX && to_rr_type != t_rr_type::CHANY) + if (to_rr_type != e_rr_type::CHANX && to_rr_type != e_rr_type::CHANY) continue; if (rr_graph.node_direction(RRNodeId(to_node)) == Direction::BIDIR) { @@ -179,7 +179,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { switch_index = rr_graph.edge_switch(inode, iedge); to_node = size_t(rr_graph.edge_sink_node(inode, iedge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY) { + if (to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY) { if (rr_graph.node_direction(RRNodeId(to_node)) != Direction::BIDIR) { /* Cout was not added in these cases */ Couts_to_add[to_node] = std::max(Couts_to_add[to_node], rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cout); diff --git a/vpr/src/timing/VprTimingGraphResolver.cpp b/vpr/src/timing/VprTimingGraphResolver.cpp index 81fbef6db39..33ea251d52d 100644 --- a/vpr/src/timing/VprTimingGraphResolver.cpp +++ b/vpr/src/timing/VprTimingGraphResolver.cpp @@ -342,11 +342,11 @@ void VprTimingGraphResolver::get_detailed_interconnect_components_helper(std::ve // Process the current interconnect component if it is of type OPIN, CHANX, CHANY, IPIN // Only process SOURCE, SINK in debug report mode auto rr_type = rr_graph.node_type(RRNodeId(current_node->inode)); - if (rr_type == t_rr_type::OPIN - || rr_type == t_rr_type::IPIN - || rr_type == t_rr_type::CHANX - || rr_type == t_rr_type::CHANY - || ((rr_type == t_rr_type::SOURCE || rr_type == t_rr_type::SINK) && (detail_level() == e_timing_report_detail::DEBUG))) { + if (rr_type == e_rr_type::OPIN + || rr_type == e_rr_type::IPIN + || rr_type == e_rr_type::CHANX + || rr_type == e_rr_type::CHANY + || ((rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::SINK) && (detail_level() == e_timing_report_detail::DEBUG))) { tatum::DelayComponent net_component; // declare a new instance of DelayComponent net_component.type_name = rr_graph.node_coordinate_to_string(RRNodeId(current_node->inode)); diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index f86a56328a6..2574c505b57 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -1780,7 +1780,7 @@ RRNodeId get_pin_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, const int root_j, int pin_physical_num) { auto pin_type = get_pin_type_from_pin_physical_num(physical_tile, pin_physical_num); - t_rr_type node_type = (pin_type == e_pin_type::DRIVER) ? t_rr_type::OPIN : t_rr_type::IPIN; + e_rr_type node_type = (pin_type == e_pin_type::DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; std::vector x_offset; std::vector y_offset; std::vector pin_sides; @@ -1808,22 +1808,22 @@ RRNodeId get_class_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, int class_physical_num) { auto class_type = get_class_type_from_class_physical_num(physical_tile, class_physical_num); VTR_ASSERT(class_type == DRIVER || class_type == RECEIVER); - t_rr_type node_type = (class_type == e_pin_type::DRIVER) ? t_rr_type::SOURCE : t_rr_type::SINK; + e_rr_type node_type = (class_type == e_pin_type::DRIVER) ? e_rr_type::SOURCE : e_rr_type::SINK; return rr_spatial_lookup.find_node(layer, i, j, node_type, class_physical_num); } bool node_in_same_physical_tile(RRNodeId node_first, RRNodeId node_second) { const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - auto first_rr_type = rr_graph.node_type(node_first); + auto firse_rr_type = rr_graph.node_type(node_first); auto second_rr_type = rr_graph.node_type(node_second); // If one of the given node's type is CHANX/Y nodes are definitely not in the same physical tile - if (first_rr_type == t_rr_type::CHANX || first_rr_type == t_rr_type::CHANY || second_rr_type == t_rr_type::CHANX || second_rr_type == t_rr_type::CHANY) { + if (firse_rr_type == e_rr_type::CHANX || firse_rr_type == e_rr_type::CHANY || second_rr_type == e_rr_type::CHANX || second_rr_type == e_rr_type::CHANY) { return false; } else { - VTR_ASSERT(first_rr_type == t_rr_type::IPIN || first_rr_type == t_rr_type::OPIN || first_rr_type == t_rr_type::SINK || first_rr_type == t_rr_type::SOURCE); - VTR_ASSERT(second_rr_type == t_rr_type::IPIN || second_rr_type == t_rr_type::OPIN || second_rr_type == t_rr_type::SINK || second_rr_type == t_rr_type::SOURCE); + VTR_ASSERT(firse_rr_type == e_rr_type::IPIN || firse_rr_type == e_rr_type::OPIN || firse_rr_type == e_rr_type::SINK || firse_rr_type == e_rr_type::SOURCE); + VTR_ASSERT(second_rr_type == e_rr_type::IPIN || second_rr_type == e_rr_type::OPIN || second_rr_type == e_rr_type::SINK || second_rr_type == e_rr_type::SOURCE); int first_layer = rr_graph.node_layer(node_first); int first_x = rr_graph.node_xlow(node_first); int first_y = rr_graph.node_ylow(node_first); From a6fe3fafc96bf9d20959ef3d08fea0e10e51792b Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 12:44:37 -0400 Subject: [PATCH 032/176] doxygen comment for Direction --- libs/librrgraph/src/base/rr_node_types.h | 25 ++++++++++++------------ 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index 6b4fd306e48..c92e546d488 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -23,10 +23,10 @@ enum class e_rr_type : unsigned char { SOURCE = 0, /// RR_TYPES = {{e_ e_rr_type::OPIN, e_rr_type::CHANX, e_rr_type::CHANY}}; constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; -/* - * Direction::INC: wire driver is positioned at the low-coordinate end of the wire. - * Direction::DEC: wire_driver is positioned at the high-coordinate end of the wire. - * Direction::BIDIR: wire has multiple drivers, so signals can travel either way along the wire - * Direction::NONE: node does not have a direction, such as IPIN/OPIN +/** + * @enum Direction + * @brief Represents the wire direction for a routing resource node. */ enum class Direction : unsigned char { - INC = 0, - DEC = 1, - BIDIR = 2, - NONE = 3, + INC = 0, ///< wire driver is positioned at the low-coordinate end of the wire. + DEC = 1, ///< wire_driver is positioned at the high-coordinate end of the wire. + BIDIR = 2, ///< wire has multiple drivers, so signals can travel either way along the wire + NONE = 3, ///< node does not have a direction, such as IPIN/OPIN NUM_DIRECTIONS }; + constexpr std::array(Direction::NUM_DIRECTIONS)> DIRECTION_STRING = {{"INC_DIRECTION", "DEC_DIRECTION", "BI_DIRECTION", "NONE"}}; //this array is used in rr_graph_storage.cpp so that node_direction_string() can return a const std::string& From 6291e162f2fcfec12ed208543a293bf5f019b135 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 13:12:23 -0400 Subject: [PATCH 033/176] add vtr::array class --- libs/libvtrutil/src/vtr_array.h | 105 +++++++++++++++++++++++++++ libs/libvtrutil/src/vtr_array_view.h | 5 +- libs/libvtrutil/src/vtr_vector.h | 5 +- 3 files changed, 108 insertions(+), 7 deletions(-) create mode 100644 libs/libvtrutil/src/vtr_array.h diff --git a/libs/libvtrutil/src/vtr_array.h b/libs/libvtrutil/src/vtr_array.h new file mode 100644 index 00000000000..0f1bea88ca0 --- /dev/null +++ b/libs/libvtrutil/src/vtr_array.h @@ -0,0 +1,105 @@ +#pragma once + +#include +#include +#include + +namespace vtr { + +/** + * @brief A std::array wrapper that can be indexed by a vtr::StrongId. + * + * @tparam K Key type (e.g., vtr::StrongId) + * @tparam V Value type + * @tparam N Number of elements + */ +template +class array { + public: + using key_type = K; + using value_type = V; + using size_type = std::size_t; + using reference = V&; + using const_reference = const V&; + using iterator = typename std::array::iterator; + using const_iterator = typename std::array::const_iterator; + + /** + * @brief Construct a vtr::array from a list of values. + * + * This constructor allows direct brace-initialization of the array: + * @code + * vtr::array arr{1, 2, 3}; + * @endcode + * + * @tparam Args Types of the values being passed. All must be convertible to V. + * @param args The values to initialize the array with. Must match the array size. + *//** + * @brief Construct a vtr::array from a list of values. + * + * This constructor allows direct brace-initialization of the array: + * @code + * vtr::array arr{1, 2, 3}; + * @endcode + * + * @tparam Args Types of the values being passed. All must be convertible to V. + * @param args The values to initialize the array with. Must match the array size. + */ + template...>>> + constexpr array(Args&&... args) + : data_{ { std::forward(args)... } } {} + + + + ///@brief Access element with strong ID + reference operator[](K id) { + return data_[static_cast(id)]; + } + + ///@brief Access element with strong ID (const) + const_reference operator[](K id) const { + return data_[static_cast(id)]; + } + + ///@brief Access element with bounds checking + reference at(K id) { + return data_.at(static_cast(id)); + } + + ///@brief Access element with bounds checking (const) + const_reference at(K id) const { + return data_.at(static_cast(id)); + } + + // Iterators + iterator begin() { return data_.begin(); } + iterator end() { return data_.end(); } + const_iterator begin() const { return data_.begin(); } + const_iterator end() const { return data_.end(); } + const_iterator cbegin() const { return data_.cbegin(); } + const_iterator cend() const { return data_.cend(); } + + // Size + constexpr size_type size() const { return N; } + constexpr bool empty() const { return N == 0; } + + // Data + V* data() { return data_.data(); } + const V* data() const { return data_.data(); } + + // Front/Back + reference front() { return data_.front(); } + const_reference front() const { return data_.front(); } + reference back() { return data_.back(); } + const_reference back() const { return data_.back(); } + + // Fill + void fill(const V& value) { data_.fill(value); } + + private: + std::array data_; +}; + +} // namespace vtr diff --git a/libs/libvtrutil/src/vtr_array_view.h b/libs/libvtrutil/src/vtr_array_view.h index 0bb48f65eec..4f1ca034fac 100644 --- a/libs/libvtrutil/src/vtr_array_view.h +++ b/libs/libvtrutil/src/vtr_array_view.h @@ -1,5 +1,4 @@ -#ifndef _VTR_ARRAY_VIEW_H -#define _VTR_ARRAY_VIEW_H +#pragma once #include #include @@ -263,5 +262,3 @@ array_view_id #include #include @@ -250,4 +250,3 @@ class vector : private std::vector { key_iterator key_end() const { return key_iterator(key_type(size())); } }; } // namespace vtr -#endif From 57d1006f9bcbec767d9568a47edf66c6a83bc33a Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 13:13:43 -0400 Subject: [PATCH 034/176] make rr_node_typename of type vtr::array to index it only with e_rr_type --- libs/librrgraph/src/base/check_rr_graph.cpp | 4 ++-- libs/librrgraph/src/base/rr_graph_obj.cpp | 2 +- libs/librrgraph/src/base/rr_graph_storage.cpp | 10 +++++----- libs/librrgraph/src/base/rr_graph_storage.h | 2 +- libs/librrgraph/src/base/rr_node_types.h | 7 +++++-- vpr/src/base/old_traceback.cpp | 2 +- vpr/src/route/router_lookahead_map_utils.cpp | 8 ++++---- vpr/src/route/rr_graph2.cpp | 4 ++-- vpr/src/route/rr_graph_area.cpp | 2 +- 9 files changed, 22 insertions(+), 19 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 72ab0966645..59dc5638d7a 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -164,7 +164,7 @@ void check_rr_graph(const RRGraphView& rr_graph, if (!(is_chan_to_chan || is_chan_to_ipin || is_opin_to_chan || is_internal_edge)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d (%s) connects to node %d (%s) %zu times - multi-connections only expected for CHAN<->CHAN, CHAN->IPIN, OPIN->CHAN.\n", - inode, rr_node_typename[(size_t)rr_type], to_node, rr_node_typename[(size_t)to_rr_type], num_edges_to_node); + inode, rr_node_typename[rr_type], to_node, rr_node_typename[to_rr_type], num_edges_to_node); } //Between two wire segments @@ -244,7 +244,7 @@ void check_rr_graph(const RRGraphView& rr_graph, // #TODO: No edges are added for internal pins. However, they need to be checked somehow! if (ptc_num >= type->num_pins) { VTR_LOG_ERROR("in check_rr_graph: node %d (%s) type: %s is internal node.\n", - inode, rr_graph.node_type_string(rr_node), rr_node_typename[(size_t)rr_type]); + inode, rr_graph.node_type_string(rr_node), rr_node_typename[rr_type]); } } diff --git a/libs/librrgraph/src/base/rr_graph_obj.cpp b/libs/librrgraph/src/base/rr_graph_obj.cpp index 9f52f523eb7..211c49990bf 100644 --- a/libs/librrgraph/src/base/rr_graph_obj.cpp +++ b/libs/librrgraph/src/base/rr_graph_obj.cpp @@ -451,7 +451,7 @@ short RRGraph::chan_num_tracks(const short& x, const short& y, const e_rr_type& /* This function aims to print basic information about a node */ void RRGraph::print_node(const RRNodeId& node) const { VTR_LOG("Node id: %d\n", node_index(node)); - VTR_LOG("Node type: %s\n", rr_node_typename[(size_t)node_type(node)]); + VTR_LOG("Node type: %s\n", rr_node_typename[node_type(node)]); VTR_LOG("Node xlow: %d\n", node_xlow(node)); VTR_LOG("Node ylow: %d\n", node_ylow(node)); VTR_LOG("Node xhigh: %d\n", node_xhigh(node)); diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 787ec67098e..28da321cc1f 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -608,10 +608,10 @@ bool t_rr_graph_storage::validate(const vtr::vector } const char* t_rr_graph_storage::node_type_string(RRNodeId id) const { - return rr_node_typename[(size_t)node_type(id)]; + return rr_node_typename[node_type(id)]; } const char* t_rr_graph_view::node_type_string(RRNodeId id) const { - return rr_node_typename[(size_t)node_type(id)]; + return rr_node_typename[node_type(id)]; } const std::string& t_rr_graph_storage::node_direction_string(RRNodeId id) const { @@ -675,7 +675,7 @@ static int get_node_pin_num( RRNodeId id) { e_rr_type node_type = node_storage[id].type_; if (node_type != e_rr_type::IPIN && node_type != e_rr_type::OPIN) { - VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'", rr_node_typename[(size_t)node_type]); + VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'", rr_node_typename[node_type]); } return node_ptc[id].ptc_.pin_num; } @@ -686,7 +686,7 @@ static int get_node_track_num( RRNodeId id) { e_rr_type node_type = node_storage[id].type_; if (node_type != e_rr_type::CHANX && node_type != e_rr_type::CHANY) { - VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'", rr_node_typename[(size_t)node_type]); + VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'", rr_node_typename[node_type]); } return node_ptc[id].ptc_.track_num; } @@ -697,7 +697,7 @@ static int get_node_class_num( RRNodeId id) { e_rr_type node_type = node_storage[id].type_; if (node_type != e_rr_type::SOURCE && node_type != e_rr_type::SINK) { - VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'", rr_node_typename[(size_t)node_type]); + VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'", rr_node_typename[node_type]); } return node_ptc[id].ptc_.class_num; } diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index a76e57fe731..2f6702f24f3 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -783,7 +783,7 @@ class t_rr_graph_storage { auto& node_data = node_storage[id]; if (node_data.type_ != e_rr_type::IPIN && node_data.type_ != e_rr_type::OPIN) { VTR_LOG_ERROR("Attempted to access RR node 'side' for non-IPIN/OPIN type '%s'", - rr_node_typename[(size_t)node_data.type_]); + rr_node_typename[node_data.type_]); } // Return a vector showing only the sides that the node appears std::bitset side_tt = node_storage[id].dir_side_.sides; diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index c92e546d488..a03c8aa304a 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -7,7 +7,9 @@ #include #include #include + #include "vtr_range.h" +#include "vtr_array.h" #include "vtr_ndmatrix.h" #include "rr_graph_fwd.h" @@ -32,7 +34,8 @@ enum class e_rr_type : unsigned char { constexpr std::array RR_TYPES = {{e_rr_type::SOURCE, e_rr_type::SINK, e_rr_type::IPIN, e_rr_type::OPIN, e_rr_type::CHANX, e_rr_type::CHANY}}; -constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; + +vtr::array rr_node_typename {"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}; /** * @enum Direction @@ -123,4 +126,4 @@ struct t_rr_rc_data { // This is the data type of fast lookups of an rr-node given an (rr_type, layer, x, y, and the side) //[0..num_rr_types-1][0..num_layer-1][0..grid_width-1][0..grid_height-1][0..NUM_2D_SIDES-1][0..max_ptc-1] -typedef std::array, 4>, (size_t)e_rr_type::NUM_RR_TYPES> t_rr_node_indices; +typedef vtr::array, 4>, (size_t)e_rr_type::NUM_RR_TYPES> t_rr_node_indices; diff --git a/vpr/src/base/old_traceback.cpp b/vpr/src/base/old_traceback.cpp index 7d00bdaaaf0..29531cb29dc 100644 --- a/vpr/src/base/old_traceback.cpp +++ b/vpr/src/base/old_traceback.cpp @@ -120,7 +120,7 @@ void print_traceback(const t_trace* trace) { const t_trace* prev = nullptr; while (trace) { RRNodeId inode(trace->index); - VTR_LOG("%d (%s)", inode, rr_node_typename[(size_t)rr_graph.node_type(inode)]); + VTR_LOG("%d (%s)", inode, rr_node_typename[rr_graph.node_type(inode)]); if (trace->iswitch == OPEN) { VTR_LOG(" !"); //End of branch diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 7d1ed4889fb..ce3e484f90a 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -411,7 +411,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { //No untried instances of the current tile type left VTR_LOG_WARN("Found no %ssample locations for %s in %s\n", (num_sampled_locs == 0) ? "" : "more ", - rr_node_typename[(size_t)rr_type], + rr_node_typename[rr_type], device_ctx.physical_tile_types[itile].name.c_str()); break; } @@ -442,7 +442,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { } if (reachable_wire_found) { VTR_LOGV_DEBUG(f_router_debug, "Found no reachable wires from %s (%s) at (%d,%d,%d)\n", - rr_node_typename[(size_t)rr_type], + rr_node_typename[rr_type], rr_node_arch_name(node_id, is_flat).c_str(), sample_loc.x, sample_loc.y, @@ -783,7 +783,7 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length, if (sample_nodes.empty()) { VTR_LOG_WARN("Unable to find any sample location for segment %s type '%s' (length %d)\n", - rr_node_typename[(size_t)chan_type], + rr_node_typename[chan_type], segment_inf.name.c_str(), segment_inf.length); } else { @@ -914,7 +914,7 @@ void dump_readable_router_lookahead_map(const std::string& file_name, const std: auto cost = wire_cost_func(chan_type, seg_index, from_layer_num, dx, dy, to_layer_num); ofs << from_layer_num << "," << to_layer_num << "," - << rr_node_typename[(size_t)chan_type] << "," + << rr_node_typename[chan_type] << "," << seg_index << "," << dx << "," << dy << "," diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index a166276c021..0c716b8dc3b 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1554,8 +1554,8 @@ bool verify_rr_node_indices(const DeviceGrid& grid, if (rr_graph.node_type(inode) != rr_type) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node type does not match between rr_nodes and rr_node_indices (%s/%s): %s", - rr_node_typename[(size_t)rr_graph.node_type(inode)], - rr_node_typename[(size_t)rr_type], + rr_node_typename[rr_graph.node_type(inode)], + rr_node_typename[rr_type], describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp index c026d12a1a1..1941805b22f 100644 --- a/vpr/src/route/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_area.cpp @@ -228,7 +228,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl VPR_ERROR(VPR_ERROR_ROUTE, "in count_routing_transistors:\n" "\tUnexpected connection from node %d (type %s) to node %d (type %s).\n", - from_node, rr_node_typename[(size_t)from_rr_type], size_t(to_node), rr_node_typename[(size_t)to_rr_type]); + from_node, rr_node_typename[from_rr_type], size_t(to_node), rr_node_typename[to_rr_type]); break; } /* End switch on to_rr_type. */ From 971f4322cccec8a7de87f69b3b290690be07beec Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 13:22:51 -0400 Subject: [PATCH 035/176] add default constructor to vtr::array --- libs/libvtrutil/src/vtr_array.h | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/libs/libvtrutil/src/vtr_array.h b/libs/libvtrutil/src/vtr_array.h index 0f1bea88ca0..d544c6a2c5b 100644 --- a/libs/libvtrutil/src/vtr_array.h +++ b/libs/libvtrutil/src/vtr_array.h @@ -35,22 +35,23 @@ class array { * @tparam Args Types of the values being passed. All must be convertible to V. * @param args The values to initialize the array with. Must match the array size. *//** - * @brief Construct a vtr::array from a list of values. - * - * This constructor allows direct brace-initialization of the array: - * @code - * vtr::array arr{1, 2, 3}; - * @endcode - * - * @tparam Args Types of the values being passed. All must be convertible to V. - * @param args The values to initialize the array with. Must match the array size. - */ + * @brief Construct a vtr::array from a list of values. + * + * This constructor allows direct brace-initialization of the array: + * @code + * vtr::array arr{1, 2, 3}; + * @endcode + * + * @tparam Args Types of the values being passed. All must be convertible to V. + * @param args The values to initialize the array with. Must match the array size. + */ template...>>> constexpr array(Args&&... args) : data_{ { std::forward(args)... } } {} + array() = default; ///@brief Access element with strong ID From 1e192c929335fc44c93917604572b4772c61609a Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 13:24:15 -0400 Subject: [PATCH 036/176] access rr_node_indices_ with e_rr_type instead of casting to size_t --- .../librrgraph/src/base/rr_spatial_lookup.cpp | 74 +++++++++---------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index de5fdfdebef..aa9e17a1d5b 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -45,7 +45,7 @@ RRNodeId RRSpatialLookup::find_node(int layer, std::swap(node_x, node_y); } - VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* Sanity check to ensure the layer, x, y, side and ptc are in range * - Return an valid id by searching in look-up when all the parameters are in range @@ -55,27 +55,27 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - if (size_t(layer) >= rr_node_indices_[(size_t)type].dim_size(0)) { + if (size_t(layer) >= rr_node_indices_[type].dim_size(0)) { return RRNodeId::INVALID(); } - if (node_x >= rr_node_indices_[(size_t)type].dim_size(1)) { + if (node_x >= rr_node_indices_[type].dim_size(1)) { return RRNodeId::INVALID(); } - if(node_y >= rr_node_indices_[(size_t)type].dim_size(2)){ + if(node_y >= rr_node_indices_[type].dim_size(2)){ return RRNodeId::INVALID(); } - if (node_side >= rr_node_indices_[(size_t)type].dim_size(3)) { + if (node_side >= rr_node_indices_[type].dim_size(3)) { return RRNodeId::INVALID(); } - if (size_t(ptc) >= rr_node_indices_[(size_t)type][layer][node_x][node_y][node_side].size()) { + if (size_t(ptc) >= rr_node_indices_[type][layer][node_x][node_y][node_side].size()) { return RRNodeId::INVALID(); } - return rr_node_indices_[(size_t)type][layer][node_x][node_y][node_side][ptc]; + return rr_node_indices_[type][layer][node_x][node_y][node_side][ptc]; } std::vector RRSpatialLookup::find_nodes_in_range(int layer, @@ -126,7 +126,7 @@ std::vector RRSpatialLookup::find_nodes(int layer, std::swap(node_x, node_y); } - VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* Sanity check to ensure the x, y, side are in range * - Return a list of valid ids by searching in look-up when all the parameters are in range @@ -136,32 +136,32 @@ std::vector RRSpatialLookup::find_nodes(int layer, return nodes; } - if (size_t(layer) >= rr_node_indices_[(size_t)type].dim_size(0)) { + if (size_t(layer) >= rr_node_indices_[type].dim_size(0)) { return nodes; } - if (node_x >= rr_node_indices_[(size_t)type].dim_size(1)) { + if (node_x >= rr_node_indices_[type].dim_size(1)) { return nodes; } - if(node_y >= rr_node_indices_[(size_t)type].dim_size(2)){ + if(node_y >= rr_node_indices_[type].dim_size(2)){ return nodes; } - if (side >= rr_node_indices_[(size_t)type].dim_size(3)) { + if (side >= rr_node_indices_[type].dim_size(3)) { return nodes; } /* Reserve space to avoid memory fragmentation */ size_t num_nodes = 0; - for (const auto& node : rr_node_indices_[(size_t)type][layer][node_x][node_y][side]) { + for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { if (node.is_valid()) { num_nodes++; } } nodes.reserve(num_nodes); - for (const auto& node : rr_node_indices_[(size_t)type][layer][node_x][node_y][side]) { + for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { if (node.is_valid()) { nodes.emplace_back(node); } @@ -241,7 +241,7 @@ void RRSpatialLookup::reserve_nodes(int layer, e_rr_type type, int num_nodes, e_side side) { - VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* For non-IPIN/OPIN nodes, the side should always be the TOP side which follows the convention in find_node() API! */ if (type != e_rr_type::IPIN && type != e_rr_type::OPIN) { @@ -250,7 +250,7 @@ void RRSpatialLookup::reserve_nodes(int layer, resize_nodes(layer, x, y, type, side); - rr_node_indices_[(size_t)type][layer][x][y][side].reserve(num_nodes); + rr_node_indices_[type][layer][x][y][side].reserve(num_nodes); } void RRSpatialLookup::add_node(RRNodeId node, @@ -261,7 +261,7 @@ void RRSpatialLookup::add_node(RRNodeId node, int ptc, e_side side) { VTR_ASSERT(node.is_valid()); /* Must have a valid node id to be added */ - VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* For non-IPIN/OPIN nodes, the side should always be the TOP side which follows the convention in find_node() API! */ if (type != e_rr_type::IPIN && type != e_rr_type::OPIN) { @@ -270,13 +270,13 @@ void RRSpatialLookup::add_node(RRNodeId node, resize_nodes(layer, x, y, type, side); - if (size_t(ptc) >= rr_node_indices_[(size_t)type][layer][x][y][side].size()) { + if (size_t(ptc) >= rr_node_indices_[type][layer][x][y][side].size()) { /* Deposit invalid ids to newly allocated elements while original elements are untouched */ - rr_node_indices_[(size_t)type][layer][x][y][side].resize(ptc + 1, RRNodeId::INVALID()); + rr_node_indices_[type][layer][x][y][side].resize(ptc + 1, RRNodeId::INVALID()); } /* Resize on demand finished; Register the node */ - rr_node_indices_[(size_t)type][layer][x][y][side][ptc] = node; + rr_node_indices_[type][layer][x][y][side][ptc] = node; } bool RRSpatialLookup::remove_node(RRNodeId node, @@ -287,7 +287,7 @@ bool RRSpatialLookup::remove_node(RRNodeId node, int ptc, e_side side) { VTR_ASSERT(node.is_valid()); - VTR_ASSERT_SAFE(4 == rr_node_indices_[(size_t)type].ndims()); + VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); VTR_ASSERT_SAFE(layer >= 0); VTR_ASSERT_SAFE(x >= 0); VTR_ASSERT_SAFE(y >= 0); @@ -297,16 +297,16 @@ bool RRSpatialLookup::remove_node(RRNodeId node, // Check if the node given is in the spatial lookup at the given indices if ((size_t)type >= rr_node_indices_.size()) return false; - if ((size_t)layer >= rr_node_indices_[(size_t)type].dim_size(0)) return false; - if ((size_t)x >= rr_node_indices_[(size_t)type].dim_size(1)) return false; - if ((size_t)y >= rr_node_indices_[(size_t)type].dim_size(2)) return false; - if (side >= rr_node_indices_[(size_t)type].dim_size(3)) return false; - if ((size_t)ptc >= rr_node_indices_[(size_t)type][layer][x][y][side].size()) return false; - if (rr_node_indices_[(size_t)type][layer][x][y][side][ptc] != node) return false; + if ((size_t)layer >= rr_node_indices_[type].dim_size(0)) return false; + if ((size_t)x >= rr_node_indices_[type].dim_size(1)) return false; + if ((size_t)y >= rr_node_indices_[type].dim_size(2)) return false; + if (side >= rr_node_indices_[type].dim_size(3)) return false; + if ((size_t)ptc >= rr_node_indices_[type][layer][x][y][side].size()) return false; + if (rr_node_indices_[type][layer][x][y][side][ptc] != node) return false; // The node was in the spatial lookup; remove it. -1 corresponds to an invalid node id, // and so is treated as absent in the spatial lookup - rr_node_indices_[(size_t)type][layer][x][y][side][ptc] = RRNodeId::INVALID(); + rr_node_indices_[type][layer][x][y][side][ptc] = RRNodeId::INVALID(); return true; } @@ -317,7 +317,7 @@ void RRSpatialLookup::mirror_nodes(const int layer, e_side side) { VTR_ASSERT(e_rr_type::SOURCE == type); resize_nodes(layer, des_coord.x(), des_coord.y(), type, side); - rr_node_indices_[(size_t)type][layer][des_coord.x()][des_coord.y()][side] = rr_node_indices_[(size_t)type][layer][src_coord.x()][src_coord.y()][side]; + rr_node_indices_[type][layer][des_coord.x()][des_coord.y()][side] = rr_node_indices_[type][layer][src_coord.x()][src_coord.y()][side]; } void RRSpatialLookup::resize_nodes(int layer, @@ -334,14 +334,14 @@ void RRSpatialLookup::resize_nodes(int layer, VTR_ASSERT(y >= 0); VTR_ASSERT(layer >= 0); - if ((layer >= int(rr_node_indices_[(size_t)type].dim_size(0))) - || (x >= int(rr_node_indices_[(size_t)type].dim_size(1))) - || (y >= int(rr_node_indices_[(size_t)type].dim_size(2))) - || (size_t(side) >= rr_node_indices_[(size_t)type].dim_size(3))) { - rr_node_indices_[(size_t)type].resize({std::max(rr_node_indices_[(size_t)type].dim_size(0),size_t(layer)+1), - std::max(rr_node_indices_[(size_t)type].dim_size(1), size_t(x) + 1), - std::max(rr_node_indices_[(size_t)type].dim_size(2), size_t(y) + 1), - std::max(rr_node_indices_[(size_t)type].dim_size(3), size_t(side) + 1)}); + if ((layer >= int(rr_node_indices_[type].dim_size(0))) + || (x >= int(rr_node_indices_[type].dim_size(1))) + || (y >= int(rr_node_indices_[type].dim_size(2))) + || (size_t(side) >= rr_node_indices_[type].dim_size(3))) { + rr_node_indices_[type].resize({std::max(rr_node_indices_[type].dim_size(0),size_t(layer)+1), + std::max(rr_node_indices_[type].dim_size(1), size_t(x) + 1), + std::max(rr_node_indices_[type].dim_size(2), size_t(y) + 1), + std::max(rr_node_indices_[type].dim_size(3), size_t(side) + 1)}); } } From c2d7545b742b3c0814707feafb9a1af56213ac63 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 13:48:10 -0400 Subject: [PATCH 037/176] add single argument constructor to vtr::array --- libs/libvtrutil/src/vtr_array.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/libs/libvtrutil/src/vtr_array.h b/libs/libvtrutil/src/vtr_array.h index d544c6a2c5b..4a8876570f0 100644 --- a/libs/libvtrutil/src/vtr_array.h +++ b/libs/libvtrutil/src/vtr_array.h @@ -51,6 +51,17 @@ class array { constexpr array(Args&&... args) : data_{ { std::forward(args)... } } {} + /** + * @brief Fill the array with a single value + * + * This constructor initializes all elements to the given value. + * + * @param value The value to assign to all elements + */ + constexpr explicit array(const V& value) { + data_.fill(value); + } + array() = default; From 2029463cce70f72a0de36dab04b8831f60f9fcaf Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Fri, 25 Apr 2025 13:49:45 -0400 Subject: [PATCH 038/176] [Router] Updated Golden Results for Parallel Connection Router CI Tests Updated the golden results for CI tests for parallel connection router: - `vtr_reg_strong/koios_test` - `vtr_reg_strong/strong_flat_router` - `vtr_reg_strong/strong_multiclock` - `vtr_reg_strong/strong_timing` --- .../vtr_reg_strong/koios_test/config/golden_results.txt | 9 ++++++--- .../strong_flat_router/config/golden_results.txt | 9 ++++++--- .../strong_multiclock/config/golden_results.txt | 9 ++++++--- .../strong_timing/config/golden_results.txt | 9 ++++++--- 4 files changed, 24 insertions(+), 12 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt index 39aa722daca..fa43c27af55 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt @@ -1,3 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.38 vpr 77.35 MiB -1 -1 0.36 22280 1 0.10 -1 -1 35580 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79208 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.18 1862 38583 13232 21153 4198 77.4 MiB 0.24 0.00 5.12303 -624.562 -5.12303 5.12303 0.45 0.00115671 0.00104931 0.13445 0.124537 -1 -1 -1 -1 64 3969 9 4.93594e+06 1.0962e+06 976140. 4980.31 5.77 0.971386 0.907233 31408 195022 -1 3606 8 821 857 201107 78801 4.57723 4.57723 -666.876 -4.57723 0 0 1.23909e+06 6321.90 0.06 0.12 0.38 -1 -1 0.06 0.0628918 0.0600921 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 7.77 vpr 77.61 MiB -1 -1 0.36 22212 1 0.08 -1 -1 35140 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79472 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.6 MiB 0.18 1862 38583 13232 21153 4198 77.6 MiB 0.37 0.00 5.12303 -624.562 -5.12303 5.12303 0.55 0.00210597 0.00194049 0.204405 0.191731 -1 -1 -1 -1 64 3993 10 4.93594e+06 1.0962e+06 976140. 4980.31 3.98 0.785401 0.735059 31408 195022 -1 3592 9 794 830 166912 64369 4.57723 4.57723 -658.916 -4.57723 0 0 1.23909e+06 6321.90 0.07 0.13 0.32 -1 -1 0.07 0.068841 0.0645644 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 4.41 vpr 75.36 MiB -1 -1 0.19 17940 1 0.05 -1 -1 31600 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77168 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000974867 0.000904716 0.077352 0.0718699 -1 -1 -1 -1 82 3601 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.25 0.377802 0.348243 33448 250998 -1 3687 9 800 863 234820 89374 4.57723 4.57723 -726.049 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.07 0.22 -1 -1 0.04 0.0332833 0.0315356 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 4.54 vpr 75.36 MiB -1 -1 0.19 17936 1 0.05 -1 -1 31376 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77168 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.1 MiB 0.11 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.23 0.000981081 0.000906865 0.0786348 0.0731135 -1 -1 -1 -1 82 3585 15 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.38 0.403967 0.372656 33448 250998 -1 3715 9 792 819 214644 81314 4.57723 4.57723 -685.291 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.06 0.21 -1 -1 0.04 0.0307442 0.0291164 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on 4.52 vpr 75.37 MiB -1 -1 0.20 17940 1 0.05 -1 -1 31712 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77176 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000979303 0.00090991 0.077946 0.0724613 -1 -1 -1 -1 82 3581 10 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.36 0.375357 0.346115 33448 250998 -1 3699 9 747 819 220831 220831 4.57723 4.57723 -679.037 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.08 0.21 -1 -1 0.04 0.0313828 0.0297241 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16 5.06 vpr 74.98 MiB -1 -1 0.19 17956 1 0.05 -1 -1 31380 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 76780 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.0 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000974681 0.00090508 0.0774429 0.0719617 -1 -1 -1 -1 82 3638 20 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.83 0.404389 0.372638 33448 250998 -1 3485 9 735 762 269282 269282 4.57723 4.57723 -660.925 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.14 0.21 -1 -1 0.04 0.0317757 0.0300764 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on 5.20 vpr 74.15 MiB -1 -1 0.22 17572 1 0.06 -1 -1 31392 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 75932 130 40 596 562 1 356 185 14 14 196 dsp_top auto 35.1 MiB 0.11 3253 1906 39109 13750 20961 4398 74.2 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.23 0.000986009 0.000916173 0.0784056 0.0728838 -1 -1 -1 -1 82 3602 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.86 0.418875 0.386466 33448 250998 -1 3679 10 722 785 234800 89746 4.57723 4.57723 -676.631 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.12 0.21 -1 -1 0.04 0.0325316 0.0307593 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index e37401667f7..d308c81afd1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,3 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.85 vpr 79.08 MiB -1 -1 3.58 35500 16 0.65 -1 -1 38580 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80980 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.0 MiB 3.23 6742 28689 8224 17037 3428 79.1 MiB 0.65 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00310914 0.00279648 0.314019 0.270375 -1 -1 -1 -1 -1 10349 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.50 0.423776 0.367585 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 12.82 vpr 78.98 MiB -1 -1 3.48 35500 16 0.73 -1 -1 38088 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80880 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.1 MiB 3.28 6742 28689 8224 17037 3428 79.0 MiB 0.59 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00230907 0.0018852 0.209392 0.171163 -1 -1 -1 -1 -1 10313 15 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.42 0.342057 0.287674 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 7.09 vpr 77.94 MiB -1 -1 1.87 32304 16 0.41 -1 -1 34724 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79808 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.5 MiB 1.86 9794 6883 28689 8164 16986 3539 77.9 MiB 0.45 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00305795 0.00281495 0.226764 0.201621 -1 -1 -1 -1 -1 10585 12 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.17 0.283544 0.251205 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 7.22 vpr 77.26 MiB -1 -1 2.04 31928 16 0.39 -1 -1 33776 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79116 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.2 MiB 1.74 9794 6883 28689 8164 16986 3539 77.3 MiB 0.44 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00285411 0.002454 0.233988 0.206778 -1 -1 -1 -1 -1 10620 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.24 0.301013 0.263687 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on 7.01 vpr 77.55 MiB -1 -1 1.84 32308 16 0.38 -1 -1 34724 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79412 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.2 MiB 1.77 9794 6883 28689 8164 16986 3539 77.6 MiB 0.41 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00217684 0.0019326 0.199185 0.177858 -1 -1 -1 -1 -1 10546 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.30 0.25973 0.230708 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16 8.02 vpr 77.44 MiB -1 -1 1.84 31552 16 0.39 -1 -1 34440 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79296 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.1 MiB 1.70 9794 6883 28689 8164 16986 3539 77.4 MiB 0.36 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00187804 0.00164622 0.167362 0.14756 -1 -1 -1 -1 -1 10692 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.43 0.218922 0.192418 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on 7.25 vpr 77.56 MiB -1 -1 1.84 32324 16 0.39 -1 -1 34576 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79424 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.2 MiB 1.70 9794 6883 28689 8164 16986 3539 77.6 MiB 0.36 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00188091 0.00164873 0.16884 0.149107 -1 -1 -1 -1 -1 10708 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.64 0.225256 0.197955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 7e566048732..2f7e01b0b8e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,3 +1,6 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index b003134057c..5cbe4ea049b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,3 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.63 vpr 68.02 MiB -1 -1 0.39 22168 3 0.11 -1 -1 36800 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69656 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.23 0.00 1.86472 -118.834 -1.86472 1.86472 0.15 0.000594963 0.000540506 0.0732034 0.0668337 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.54 0.213559 0.195205 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.08 -1 -1 0.02 0.0300207 0.027912 - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 2.86 vpr 68.12 MiB -1 -1 0.35 22168 3 0.11 -1 -1 36740 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69760 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.1 MiB 0.27 0.00 1.86472 -118.834 -1.86472 1.86472 0.21 0.000644886 0.000574461 0.100184 0.0946805 -1 -1 -1 -1 38 1379 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.64 0.202724 0.187418 12522 62564 -1 1115 10 390 630 21561 6939 1.90702 1.90702 -131.117 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.021384 0.0193317 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.80 vpr 66.19 MiB -1 -1 0.22 18464 3 0.07 -1 -1 32740 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67776 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000573836 0.000534893 0.0449119 0.0418379 -1 -1 -1 -1 38 1437 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.35 0.164006 0.149599 12522 62564 -1 1141 11 437 710 29360 10219 1.94502 1.94502 -130.926 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0193638 0.0180814 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 1.78 vpr 66.56 MiB -1 -1 0.22 18460 3 0.07 -1 -1 33112 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68160 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.6 MiB 0.14 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000665545 0.000617009 0.0528489 0.0485457 -1 -1 -1 -1 38 1420 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.32 0.145628 0.130364 12522 62564 -1 1150 9 446 701 30426 10498 1.94502 1.94502 -131.108 -1.94502 -0.67939 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0162708 0.0148159 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on 1.83 vpr 65.93 MiB -1 -1 0.22 18452 3 0.07 -1 -1 32968 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67512 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.11 1695 684 72933 23047 34243 15643 65.9 MiB 0.14 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.00057601 0.000537702 0.0453956 0.0423047 -1 -1 -1 -1 38 1417 9 5.66058e+06 4.21279e+06 319130. 2216.18 0.35 0.161904 0.148079 12522 62564 -1 1152 9 438 706 28653 28653 1.94502 1.94502 -129.801 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0178252 0.0167004 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16 1.93 vpr 65.91 MiB -1 -1 0.23 18864 3 0.07 -1 -1 32740 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67492 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.11 1695 684 72933 23047 34243 15643 65.9 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000571739 0.000533473 0.0449704 0.0418885 -1 -1 -1 -1 38 1403 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.44 0.164243 0.150129 12522 62564 -1 1126 9 422 667 50272 50272 1.94502 1.94502 -131.371 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.05 0.04 -1 -1 0.01 0.0176487 0.0165339 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on 1.95 vpr 66.02 MiB -1 -1 0.22 18476 3 0.07 -1 -1 32744 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67608 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.15 1695 684 72933 23047 34243 15643 66.0 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000573161 0.000534076 0.0449252 0.0418347 -1 -1 -1 -1 38 1408 11 5.66058e+06 4.21279e+06 319130. 2216.18 0.40 0.162733 0.14864 12522 62564 -1 1155 11 436 701 33997 11289 1.94502 1.94502 -131.251 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.05 0.05 -1 -1 0.01 0.022968 0.0212952 From 0f8a76a811f36509b1bcd5cf63d986b2f48a6ffd Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 14:45:21 -0400 Subject: [PATCH 039/176] use vtr::array to index some arrays using e_rr_type --- libs/librrgraph/src/base/check_rr_graph.cpp | 40 +++++++++------------ libs/librrgraph/src/base/rr_node_types.h | 3 +- vpr/src/route/connection_router.cpp | 10 +++--- vpr/src/route/route.cpp | 13 +++---- vpr/src/route/router_stats.h | 23 ++++++------ 5 files changed, 42 insertions(+), 47 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 59dc5638d7a..027806f6cc2 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -230,7 +230,7 @@ void check_rr_graph(const RRGraphView& rr_graph, * now I check that everything is reachable. */ bool is_fringe_warning_sent = false; - for (const RRNodeId& rr_node : rr_graph.nodes()) { + for (const RRNodeId rr_node : rr_graph.nodes()) { size_t inode = (size_t)rr_node; e_rr_type rr_type = rr_graph.node_type(rr_node); int ptc_num = rr_graph.node_ptc_num(rr_node); @@ -263,7 +263,7 @@ void check_rr_graph(const RRGraphView& rr_graph, } } - const auto& node = rr_graph.rr_nodes()[inode]; + const t_rr_node& node = rr_graph.rr_nodes()[inode]; bool is_fringe = ((rr_graph.node_xlow(rr_node) == 1) || (rr_graph.node_ylow(rr_node) == 1) @@ -312,18 +312,14 @@ void check_rr_graph(const RRGraphView& rr_graph, static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const DeviceGrid& grid, RRNodeId inode) { /* Returns true if inode refers to a global CLB input pin node. */ - - int ipin; - t_physical_tile_type_ptr type; - - type = grid.get_physical_type({rr_graph.node_xlow(inode), - rr_graph.node_ylow(inode), - rr_graph.node_layer(inode)}); + t_physical_tile_type_ptr type = grid.get_physical_type({rr_graph.node_xlow(inode), + rr_graph.node_ylow(inode), + rr_graph.node_layer(inode)}); if (rr_graph.node_type(inode) != e_rr_type::IPIN) return (false); - ipin = rr_graph.node_pin_num(inode); + int ipin = rr_graph.node_pin_num(inode); return type->is_ignored_pin[ipin]; } @@ -341,24 +337,20 @@ void check_rr_node(const RRGraphView& rr_graph, //Make sure over-flow doesn't happen VTR_ASSERT(inode >= 0); - int xlow, ylow, xhigh, yhigh, layer_num, ptc_num, capacity; - e_rr_type rr_type; - t_physical_tile_type_ptr type; int nodes_per_chan, tracks_per_node; - RRIndexedDataId cost_index; float C, R; RRNodeId rr_node = RRNodeId(inode); - rr_type = rr_graph.node_type(rr_node); - xlow = rr_graph.node_xlow(rr_node); - xhigh = rr_graph.node_xhigh(rr_node); - ylow = rr_graph.node_ylow(rr_node); - yhigh = rr_graph.node_yhigh(rr_node); - layer_num = rr_graph.node_layer(rr_node); - ptc_num = rr_graph.node_ptc_num(rr_node); - capacity = rr_graph.node_capacity(rr_node); - cost_index = rr_graph.node_cost_index(rr_node); - type = nullptr; + e_rr_type rr_type = rr_graph.node_type(rr_node); + int xlow = rr_graph.node_xlow(rr_node); + int xhigh = rr_graph.node_xhigh(rr_node); + int ylow = rr_graph.node_ylow(rr_node); + int yhigh = rr_graph.node_yhigh(rr_node); + int layer_num = rr_graph.node_layer(rr_node); + int ptc_num = rr_graph.node_ptc_num(rr_node); + int capacity = rr_graph.node_capacity(rr_node); + RRIndexedDataId cost_index = rr_graph.node_cost_index(rr_node); + t_physical_tile_type_ptr type = nullptr; if (xlow > xhigh || ylow > yhigh) { VPR_ERROR(VPR_ERROR_ROUTE, diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index a03c8aa304a..a30cb16e481 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -32,10 +32,11 @@ enum class e_rr_type : unsigned char { NUM_RR_TYPES }; +/// Used to iterate for different e_rr_type values in range-based for loops. constexpr std::array RR_TYPES = {{e_rr_type::SOURCE, e_rr_type::SINK, e_rr_type::IPIN, e_rr_type::OPIN, e_rr_type::CHANX, e_rr_type::CHANY}}; -vtr::array rr_node_typename {"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}; +constexpr vtr::array rr_node_typename {"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}; /** * @enum Direction diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp index 5e50fa25fb8..4e2672e9c97 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/connection_router.cpp @@ -911,7 +911,7 @@ void ConnectionRouter::add_route_tree_node_to_heap( rr_graph_); if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - router_stats_->rt_node_pushes[(size_t)rr_graph_->node_type(inode)]++; + router_stats_->rt_node_pushes[rr_graph_->node_type(inode)]++; } } @@ -1067,18 +1067,18 @@ static inline void update_router_stats(RouterStats* router_stats, if (is_inter_cluster_node(*rr_graph, rr_node_id)) { if (is_push) { router_stats->inter_cluster_node_pushes++; - router_stats->inter_cluster_node_type_cnt_pushes[(size_t)node_type]++; + router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; } else { router_stats->inter_cluster_node_pops++; - router_stats->inter_cluster_node_type_cnt_pops[(size_t)node_type]++; + router_stats->inter_cluster_node_type_cnt_pops[node_type]++; } } else { if (is_push) { router_stats->intra_cluster_node_pushes++; - router_stats->intra_cluster_node_type_cnt_pushes[(size_t)node_type]++; + router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; } else { router_stats->intra_cluster_node_pops++; - router_stats->intra_cluster_node_type_cnt_pops[(size_t)node_type]++; + router_stats->intra_cluster_node_type_cnt_pops[node_type]++; } } } diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index fc240344163..cad0cf1b7aa 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -618,12 +618,13 @@ bool route(const Netlist<>& net_list, "total_internal_heap_pushes: %zu total_internal_heap_pops: %zu total_external_heap_pushes: %zu total_external_heap_pops: %zu ", router_stats.intra_cluster_node_pushes, router_stats.intra_cluster_node_pops, router_stats.inter_cluster_node_pushes, router_stats.inter_cluster_node_pops); - for (int node_type_idx = 0; node_type_idx < (int)e_rr_type::NUM_RR_TYPES; node_type_idx++) { - VTR_LOG("total_external_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.inter_cluster_node_type_cnt_pushes[node_type_idx]); - VTR_LOG("total_external_%s_pops: %zu ", rr_node_typename[node_type_idx], router_stats.inter_cluster_node_type_cnt_pops[node_type_idx]); - VTR_LOG("total_internal_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.intra_cluster_node_type_cnt_pushes[node_type_idx]); - VTR_LOG("total_internal_%s_pops: %zu ", rr_node_typename[node_type_idx], router_stats.intra_cluster_node_type_cnt_pops[node_type_idx]); - VTR_LOG("rt_node_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.rt_node_pushes[node_type_idx]); + + for (e_rr_type rr_type : RR_TYPES) { + VTR_LOG("total_external_%s_pushes: %zu ", rr_node_typename[rr_type], router_stats.inter_cluster_node_type_cnt_pushes[rr_type]); + VTR_LOG("total_external_%s_pops: %zu ", rr_node_typename[rr_type], router_stats.inter_cluster_node_type_cnt_pops[rr_type]); + VTR_LOG("total_internal_%s_pushes: %zu ", rr_node_typename[rr_type], router_stats.intra_cluster_node_type_cnt_pushes[rr_type]); + VTR_LOG("total_internal_%s_pops: %zu ", rr_node_typename[rr_type], router_stats.intra_cluster_node_type_cnt_pops[rr_type]); + VTR_LOG("rt_node_%s_pushes: %zu ", rr_node_typename[rr_type], router_stats.rt_node_pushes[rr_type]); } } VTR_LOG("\n"); diff --git a/vpr/src/route/router_stats.h b/vpr/src/route/router_stats.h index 01b9ee03ee0..32339a98192 100644 --- a/vpr/src/route/router_stats.h +++ b/vpr/src/route/router_stats.h @@ -4,6 +4,7 @@ #include "rr_graph_fwd.h" #include "rr_node_types.h" #include "vtr_assert.h" +#include "vtr_array.h" // This struct instructs the router on how to route the given connection struct ConnectionParameters { @@ -38,13 +39,13 @@ struct RouterStats { size_t inter_cluster_node_pops = 0; size_t intra_cluster_node_pushes = 0; size_t intra_cluster_node_pops = 0; - size_t inter_cluster_node_type_cnt_pushes[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; - size_t inter_cluster_node_type_cnt_pops[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; - size_t intra_cluster_node_type_cnt_pushes[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; - size_t intra_cluster_node_type_cnt_pops[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; + vtr::array inter_cluster_node_type_cnt_pushes{0}; + vtr::array inter_cluster_node_type_cnt_pops{0}; + vtr::array intra_cluster_node_type_cnt_pushes{0}; + vtr::array intra_cluster_node_type_cnt_pops{0}; // For debugging purposes - size_t rt_node_pushes[(size_t)e_rr_type::NUM_RR_TYPES] = {0}; + vtr::array rt_node_pushes{0}; /** Add rhs's stats to mine */ void combine(RouterStats& rhs) { @@ -56,12 +57,12 @@ struct RouterStats { heap_pops += rhs.heap_pops; inter_cluster_node_pops += rhs.inter_cluster_node_pops; intra_cluster_node_pops += rhs.intra_cluster_node_pops; - for (size_t node_type_idx = 0; node_type_idx < (size_t)e_rr_type::NUM_RR_TYPES; node_type_idx++) { - inter_cluster_node_type_cnt_pushes[node_type_idx] += rhs.inter_cluster_node_type_cnt_pushes[node_type_idx]; - inter_cluster_node_type_cnt_pops[node_type_idx] += rhs.inter_cluster_node_type_cnt_pops[node_type_idx]; - intra_cluster_node_type_cnt_pushes[node_type_idx] += rhs.intra_cluster_node_type_cnt_pushes[node_type_idx]; - intra_cluster_node_type_cnt_pops[node_type_idx] += rhs.intra_cluster_node_type_cnt_pops[node_type_idx]; - rt_node_pushes[node_type_idx] += rhs.rt_node_pushes[node_type_idx]; + for (e_rr_type rr_type : RR_TYPES) { + inter_cluster_node_type_cnt_pushes[rr_type] += rhs.inter_cluster_node_type_cnt_pushes[rr_type]; + inter_cluster_node_type_cnt_pops[rr_type] += rhs.inter_cluster_node_type_cnt_pops[rr_type]; + intra_cluster_node_type_cnt_pushes[rr_type] += rhs.intra_cluster_node_type_cnt_pushes[rr_type]; + intra_cluster_node_type_cnt_pops[rr_type] += rhs.intra_cluster_node_type_cnt_pops[rr_type]; + rt_node_pushes[rr_type] += rhs.rt_node_pushes[rr_type]; } } }; From a126801420a4933bed0840b8a49eb3ae2344d381 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 14:48:21 -0400 Subject: [PATCH 040/176] make format --- libs/libvtrutil/src/vtr_array.h | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/libs/libvtrutil/src/vtr_array.h b/libs/libvtrutil/src/vtr_array.h index 4a8876570f0..7866bd07c41 100644 --- a/libs/libvtrutil/src/vtr_array.h +++ b/libs/libvtrutil/src/vtr_array.h @@ -25,16 +25,6 @@ class array { using const_iterator = typename std::array::const_iterator; /** - * @brief Construct a vtr::array from a list of values. - * - * This constructor allows direct brace-initialization of the array: - * @code - * vtr::array arr{1, 2, 3}; - * @endcode - * - * @tparam Args Types of the values being passed. All must be convertible to V. - * @param args The values to initialize the array with. Must match the array size. - *//** * @brief Construct a vtr::array from a list of values. * * This constructor allows direct brace-initialization of the array: @@ -46,10 +36,9 @@ class array { * @param args The values to initialize the array with. Must match the array size. */ template...>>> + typename = std::enable_if_t...>>> constexpr array(Args&&... args) - : data_{ { std::forward(args)... } } {} + : data_{{std::forward(args)...}} {} /** * @brief Fill the array with a single value @@ -64,7 +53,6 @@ class array { array() = default; - ///@brief Access element with strong ID reference operator[](K id) { return data_[static_cast(id)]; From 27fbe983aa2c345753cb89711a5792f054c78a22 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Fri, 25 Apr 2025 15:58:11 -0400 Subject: [PATCH 041/176] avoid using e_rr_type and casting it in place_macro --- vpr/src/place/place_macro.cpp | 34 +++++++++++++++++----------------- vpr/src/place/place_macro.h | 6 +++--- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index a52865bf918..b4ddc01c247 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -59,7 +59,7 @@ static bool try_combine_macros(std::vector>& pl_macr * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * * Otherwise, mark down all the pins in that port. */ static void mark_direct_of_ports(int idirect, - int direct_type, + e_pin_type direct_type, std::string_view pb_type_name, std::string_view port_name, int end_pin_index, @@ -67,7 +67,7 @@ static void mark_direct_of_ports(int idirect, std::string_view src_string, int line, std::vector>& idirect_from_blk_pin, - std::vector>& direct_type_from_blk_pin, + std::vector>& direct_type_from_blk_pin, const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin); @@ -82,8 +82,8 @@ static void mark_direct_of_pins(int start_pin_index, int iport, std::vector>& idirect_from_blk_pin, int idirect, - std::vector>& direct_type_from_blk_pin, - int direct_type, + std::vector>& direct_type_from_blk_pin, + e_pin_type direct_type, int line, std::string_view src_string, const std::vector& physical_tile_types, @@ -200,7 +200,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, ClusterNetId to_net_id = clb_nlist.block_net(blk_id, to_iblk_pin); int to_idirect = idirect_from_blk_pin_[physical_tile->index][to_physical_pin]; - int to_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][to_physical_pin]; + e_pin_type to_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][to_physical_pin]; // Identify potential macro head blocks (i.e. start of a macro) // @@ -211,20 +211,20 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // Note that the restriction that constant nets are not driven from another direct ensures that // blocks in the middle of a chain with internal constant signals are not detected as potential // head blocks. - if (to_src_or_sink == (int)e_rr_type::SINK && to_idirect != OPEN + if (to_src_or_sink == RECEIVER && to_idirect != OPEN && (to_net_id == ClusterNetId::INVALID() || (is_constant_clb_net(to_net_id, atom_lookup, atom_nlist) && !net_is_driven_by_direct_(to_net_id, clb_nlist)))) { for (int from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin); ClusterNetId from_net_id = clb_nlist.block_net(blk_id, from_iblk_pin); int from_idirect = idirect_from_blk_pin_[physical_tile->index][from_physical_pin]; - int from_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][from_physical_pin]; + e_pin_type from_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][from_physical_pin]; // Confirm whether this is a head macro // // The output SOURCE (from_pin) of a true head macro will: // * drive another block with the same direct connection - if (from_src_or_sink == (int)e_rr_type::SOURCE && to_idirect == from_idirect && from_net_id != ClusterNetId::INVALID()) { + if (from_src_or_sink == DRIVER && to_idirect == from_idirect && from_net_id != ClusterNetId::INVALID()) { // Mark down that this is the first block in the macro pl_macro_member_blk_num_of_this_blk[0] = blk_id; pl_macro_idirect[num_macro] = to_idirect; @@ -249,7 +249,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // Assume that the from_iblk_pin index is the same for the next block VTR_ASSERT(idirect_from_blk_pin_[physical_tile->index][from_physical_pin] == from_idirect - && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == (int)e_rr_type::SOURCE); + && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == DRIVER); next_net_id = clb_nlist.block_net(next_blk_id, from_iblk_pin); // Mark down this block as a member of the macro @@ -448,7 +448,7 @@ void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector>& idirect_from_blk_pin, - std::vector>& direct_type_from_blk_pin, + std::vector>& direct_type_from_blk_pin, const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin) { /* Go through all the ports in all the blocks to find the port that has the same * @@ -536,8 +536,8 @@ static void mark_direct_of_pins(int start_pin_index, int iport, std::vector>& idirect_from_blk_pin, int idirect, - std::vector>& direct_type_from_blk_pin, - int direct_type, + std::vector>& direct_type_from_blk_pin, + e_pin_type direct_type, int line, std::string_view src_string, const std::vector& physical_tile_types, @@ -630,10 +630,10 @@ void PlaceMacros::write_place_macros_(std::string filename, int itype = type.index; for (int ipin = 0; ipin < type.num_pins; ++ipin) { if (idirect_from_blk_pin_[itype][ipin] != OPEN) { - if (direct_type_from_blk_pin_[itype][ipin] == (int)e_rr_type::SOURCE) { + if (direct_type_from_blk_pin_[itype][ipin] == DRIVER) { fprintf(f, "%-9s %-9d true SOURCE \n", type.name.c_str(), ipin); } else { - VTR_ASSERT(direct_type_from_blk_pin_[itype][ipin] == (int)e_rr_type::SINK); + VTR_ASSERT(direct_type_from_blk_pin_[itype][ipin] == RECEIVER); fprintf(f, "%-9s %-9d true SINK \n", type.name.c_str(), ipin); } } else { diff --git a/vpr/src/place/place_macro.h b/vpr/src/place/place_macro.h index 0b5988c7c61..188fbbdab46 100644 --- a/vpr/src/place/place_macro.h +++ b/vpr/src/place/place_macro.h @@ -208,12 +208,12 @@ class PlaceMacros { std::vector> idirect_from_blk_pin_; /** - * @brief This array stores the value SOURCE if the pin is the from_pin, - * SINK if the pin is the to_pin in the direct connection as specified in the arch file, + * @brief This array stores the value DRIVER if the pin is the from_pin, + * RECEIVER if the pin is the to_pin in the direct connection as specified in the arch file, * OPEN (-1) is stored for pins that could not be part of a direct chain connection. * [0...device_ctx.num_block_types-1][0...num_pins-1] */ - std::vector> direct_type_from_blk_pin_; + std::vector> direct_type_from_blk_pin_; /** * @brief Maps a blk_num to the corresponding macro index. From ae07129ae239666f9be3d00b743fbaa9457bc323 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 25 Apr 2025 16:25:20 -0400 Subject: [PATCH 042/176] [vpr][base] fix assigned pb_graph_pin when graph node is not primitive --- vpr/src/base/read_netlist.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index 9c648607cae..5a39ccfef37 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -823,7 +823,7 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route, //Why does this not use the output pin used to deterimine the rr node index? pb_route.insert(std::make_pair(rr_node_index, t_pb_route())); pb_route[rr_node_index].driver_pb_pin_id = pin_node[0][0]->pin_count_in_cluster; - pb_route[rr_node_index].pb_graph_pin = pin_node[0][0]; + pb_route[rr_node_index].pb_graph_pin = &pb->pb_graph_node->output_pins[out_port][i]; found = false; for (j = 0; j < pin_node[0][0]->num_output_edges; j++) { From b78b3eb42e9ff86acff4b0599f2505a4fea554cd Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 25 Apr 2025 16:28:03 -0400 Subject: [PATCH 043/176] [vpr][pack] pass logical type to alloc_and_laod_pb_route --- vpr/src/pack/cluster_legalizer.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vpr/src/pack/cluster_legalizer.cpp b/vpr/src/pack/cluster_legalizer.cpp index 282b0fe8d1c..1840514a62e 100644 --- a/vpr/src/pack/cluster_legalizer.cpp +++ b/vpr/src/pack/cluster_legalizer.cpp @@ -1571,8 +1571,7 @@ void ClusterLegalizer::clean_cluster(LegalizationClusterId cluster_id) { // Load the pb_route so we can free the cluster router data. // The pb_route is used when creating a netlist from the legalized clusters. std::vector* saved_lb_nets = cluster.router_data->saved_lb_nets; - t_pb_graph_node* pb_graph_node = cluster.pb->pb_graph_node; - cluster.pb->pb_route = alloc_and_load_pb_route(saved_lb_nets, pb_graph_node); + cluster.pb->pb_route = alloc_and_load_pb_route(saved_lb_nets, cluster.type); // Free the router data. free_router_data(cluster.router_data); cluster.router_data = nullptr; From b0d7afc32d938e748da28c27d603eb27332af671 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 25 Apr 2025 16:52:18 -0400 Subject: [PATCH 044/176] [vpr][pack] update alloc_and_load_pb_route header file --- vpr/src/pack/cluster_router.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index 0b40f84c627..717f971f95e 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -23,7 +23,7 @@ bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_sel void reset_intra_lb_route(t_lb_router_data* router_data); /* Accessor Functions */ -t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_pb_graph_node* pb_graph_head); +t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_logical_block_type_ptr logic_block_type); void free_pb_route(t_pb_route* free_pb_route); #endif From 250329ba5baa5bb9d316a845f02c807604b369a4 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 25 Apr 2025 16:55:25 -0400 Subject: [PATCH 045/176] [vpr][pack] fix pb_graph_pin assignment in load_trace_to_pb_route --- vpr/src/pack/cluster_router.cpp | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index 92d4b183dc5..3b4d8ddde7a 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -108,7 +108,12 @@ static bool is_route_success(t_lb_router_data* router_data); static t_lb_trace* find_node_in_rt(t_lb_trace* rt, int rt_index); static void reset_explored_node_tb(t_lb_router_data* router_data); static void save_and_reset_lb_route(t_lb_router_data* router_data); -static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace); +static void load_trace_to_pb_route(t_pb_routes& pb_route, + const int total_pins, + const AtomNetId net_id, + const int prev_pin_id, + const t_lb_trace* trace, + t_logical_block_type_ptr logic_block_type); static std::string describe_lb_type_rr_node(int inode, const t_lb_router_data* router_data); @@ -545,13 +550,14 @@ bool try_intra_lb_route(t_lb_router_data* router_data, /* Creates an array [0..num_pb_graph_pins-1] lookup for intra-logic block routing. Given pb_graph_pin id for clb, lookup atom net that uses that pin. * If pin is not used, stores OPEN at that pin location */ -t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_pb_graph_node* pb_graph_head) { +t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, + t_logical_block_type_ptr logic_block_type) { const std::vector& lb_nets = *intra_lb_nets; - int total_pins = pb_graph_head->total_pb_pins; + int total_pins = logic_block_type->pb_graph_head->total_pb_pins; t_pb_routes pb_route; for (int inet = 0; inet < (int)lb_nets.size(); inet++) { - load_trace_to_pb_route(pb_route, total_pins, lb_nets[inet].atom_net_id, OPEN, lb_nets[inet].rt_tree); + load_trace_to_pb_route(pb_route, total_pins, lb_nets[inet].atom_net_id, OPEN, lb_nets[inet].rt_tree, logic_block_type); } return pb_route; @@ -582,7 +588,12 @@ void free_intra_lb_nets(std::vector* intra_lb_nets) { ****************************************************************************/ /* Recurse through route tree trace to populate pb pin to atom net lookup array */ -static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace) { +static void load_trace_to_pb_route(t_pb_routes& pb_route, + const int total_pins, + const AtomNetId net_id, + const int prev_pin_id, + const t_lb_trace* trace, + t_logical_block_type_ptr logic_block_type) { int ipin = trace->current_node; int driver_pb_pin_id = prev_pin_id; int cur_pin_id = OPEN; @@ -593,12 +604,14 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, pb_route.insert(std::make_pair(cur_pin_id, t_pb_route())); pb_route[cur_pin_id].atom_net_id = net_id; pb_route[cur_pin_id].driver_pb_pin_id = driver_pb_pin_id; + auto pb_graph_pin = logic_block_type->pin_logical_num_to_pb_pin_mapping.at(cur_pin_id); + pb_route[cur_pin_id].pb_graph_pin = pb_graph_pin; } else { VTR_ASSERT(pb_route[cur_pin_id].atom_net_id == net_id); } } for (int itrace = 0; itrace < (int)trace->next_nodes.size(); itrace++) { - load_trace_to_pb_route(pb_route, total_pins, net_id, cur_pin_id, &trace->next_nodes[itrace]); + load_trace_to_pb_route(pb_route, total_pins, net_id, cur_pin_id, &trace->next_nodes[itrace], logic_block_type); } } From bdc234cb00e737a859426dd025f6dc2862208beb Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Sat, 26 Apr 2025 07:27:23 -0700 Subject: [PATCH 046/176] [test] keep 3d sb and cb tests --- .../strong_3d/{ => 3d_cb}/config/config.txt | 4 --- .../strong_3d/3d_cb/config/golden_results.txt | 2 ++ .../strong_3d/3d_sb/config/config.txt | 31 +++++++++++++++++++ .../strong_3d/3d_sb/config/golden_results.txt | 2 ++ .../strong_3d/config/golden_results.txt | 7 ----- .../vtr_reg_strong/task_list.txt | 3 +- 6 files changed, 37 insertions(+), 12 deletions(-) rename vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/{ => 3d_cb}/config/config.txt (79%) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/config.txt similarity index 79% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/config.txt index 245fb466a3d..54744e0cc01 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/config.txt @@ -16,7 +16,6 @@ archs_dir=arch/multi_die/stratixiv_3d circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif # Add architectures to list to sweep -arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml arch_list_add=3d_full_OPIN_inter_die_stratixiv_arch.timing.xml # Parse info and how to parse @@ -29,7 +28,4 @@ qor_parse_file=qor_vpr_titan.txt pass_requirements_file=pass_requirements_vpr_titan.txt script_params=-starting_stage vpr -track_memory_usage --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -script_params_list_add = --place_bounding_box_mode auto_bb -script_params_list_add = --place_bounding_box_mode cube_bb -script_params_list_add = --place_bounding_box_mode per_layer_bb diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt new file mode 100644 index 00000000000..b1825addf7b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 48.72 vpr 1.18 GiB 42 758 0 0 0 0 success v8.0.0-12506-gd5dc5f7b8 release IPO VTR_ASSERT_LEVEL=2 GNU 11.5.0 on Linux-5.4.0-171-generic x86_64 2025-04-26T07:14:03 qlsof01.quicklogic.com /home/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 1240720 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1075.1 MiB 12.14 186170 63157 219808 34278 166444 19086 1191.3 MiB 7.46 0.11 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.02 0.0246574 0.0210761 1.78411 1.4367 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 7.54 -1 -1 1191.3 MiB 4.03 3.22991 2.72734 1191.3 MiB -1 1.82 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/config.txt new file mode 100644 index 00000000000..1640c383443 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/config.txt @@ -0,0 +1,31 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of SDC files to use +sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/multi_die/stratixiv_3d + +# Add circuits to list to sweep +circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +script_params=-starting_stage vpr -track_memory_usage --route_chan_width 300 --max_router_iterations 400 --router_lookahead map + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt new file mode 100644 index 00000000000..2ba28851792 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 73.49 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12506-gd5dc5f7b8 release IPO VTR_ASSERT_LEVEL=2 GNU 11.5.0 on Linux-5.4.0-171-generic x86_64 2025-04-26T07:14:03 qlsof01.quicklogic.com /home/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 1423216 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1074.8 MiB 12.24 180137 58272 230944 40790 173771 16383 1389.9 MiB 7.97 0.12 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.02551 0.0218529 1.92289 1.55523 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 9.53 -1 -1 1389.9 MiB 9.59 3.30445 2.79009 1389.9 MiB -1 17.61 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt deleted file mode 100644 index 22cc148a91e..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt +++ /dev/null @@ -1,7 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 83.45 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421664 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.4 MiB 12.25 180137 58272 230944 40790 173771 16383 1388.3 MiB 10.48 0.15 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0444933 0.0387879 3.15031 2.6241 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 12.21 -1 -1 1388.3 MiB 10.28 4.91142 4.17713 1388.3 MiB -1 16.75 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 85.51 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421424 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 12.33 180137 58272 230944 40790 173771 16383 1388.1 MiB 10.48 0.14 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0434223 0.0377288 3.13504 2.6098 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 13.53 -1 -1 1388.1 MiB 10.72 4.93468 4.19984 1388.1 MiB -1 17.21 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 86.05 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421572 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 12.02 186170 63595 242080 43083 181450 17547 1388.3 MiB 12.05 0.17 5.04678 4.86192 -4242.28 -3.86192 2.41884 0.05 0.051916 0.0457829 3.35985 2.75261 103428 8.31615 32795 2.63689 27768 38066 44034475 9785894 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 5.18643 2.65983 -5392.13 -4.18642 0 0 13.06 -1 -1 1388.3 MiB 9.86 5.14157 4.32891 1388.3 MiB -1 18.69 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 57.03 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245688 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.9 MiB 11.85 186170 63157 219808 34278 166444 19086 1216.5 MiB 10.07 0.18 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0545904 0.0489007 2.99902 2.51676 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.46 -1 -1 1216.5 MiB 4.58 4.95133 4.23051 1216.5 MiB -1 1.96 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 56.04 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245528 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 11.88 180137 61714 223520 36703 169137 17680 1216.3 MiB 10.63 0.16 5.41016 4.96403 -5546.44 -3.96403 2.84288 0.01 0.0440263 0.0385965 3.36781 2.8222 75346 6.05821 18897 1.51942 26061 36573 12725206 1711712 0 0 2.60031e+07 21349.0 14 354380 4692432 -1 5.08769 2.56235 -5100.1 -4.08769 0 0 7.77 -1 -1 1216.3 MiB 4.84 5.1781 4.41964 1216.3 MiB -1 1.92 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 58.79 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245324 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 11.84 186170 63157 219808 34278 166444 19086 1216.1 MiB 10.25 0.14 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0422071 0.0368357 2.98723 2.48631 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.89 -1 -1 1216.1 MiB 4.79 4.83395 4.11932 1216.1 MiB -1 1.80 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index ab6f93e0e56..443a41856f0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -102,4 +102,5 @@ regression_tests/vtr_reg_strong/strong_timing_no_fail regression_tests/vtr_reg_strong/strong_noc regression_tests/vtr_reg_strong/strong_flat_router regression_tests/vtr_reg_strong/strong_routing_constraints -regression_tests/vtr_reg_strong/strong_3d +regression_tests/vtr_reg_strong/strong_3d/3d_cb +regression_tests/vtr_reg_strong/strong_3d/3d_sb From a839dc2710e822a8d3c044555c30dde2f5e3ca28 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 10:55:17 -0400 Subject: [PATCH 047/176] [vpr][pack] add intra_lb_pb_pin_lookup_ to cluster legalizer --- vpr/src/pack/cluster_legalizer.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/vpr/src/pack/cluster_legalizer.h b/vpr/src/pack/cluster_legalizer.h index 67bc00a95ec..418bff73d95 100644 --- a/vpr/src/pack/cluster_legalizer.h +++ b/vpr/src/pack/cluster_legalizer.h @@ -23,6 +23,7 @@ #include "vtr_vector.h" #include "vtr_vector_map.h" #include "atom_pb_bimap.h" +#include "vpr_utils.h" // Forward declarations class Prepacker; @@ -524,6 +525,8 @@ class ClusterLegalizer { inline const AtomPBBimap& atom_pb_lookup() const { return atom_pb_lookup_; } inline AtomPBBimap& mutable_atom_pb_lookup() { return atom_pb_lookup_; } + inline const IntraLbPbPinLookup& intra_lb_pb_pin_lookup() const { return intra_lb_pb_pin_lookup_; } + /// @brief Destructor of the class. Frees allocated data. ~ClusterLegalizer(); @@ -595,4 +598,7 @@ class ClusterLegalizer { /// @brief A two way map between AtomBlockIds and pb types. This is a copy /// of the AtomPBBimap in the global context's AtomLookup AtomPBBimap atom_pb_lookup_; + + /// @brief A lookup table for the pin mapping of the intra-lb pb pins. + IntraLbPbPinLookup intra_lb_pb_pin_lookup_; }; From de84b8a82d135da6d01faea351a6cd2a2e968920 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 10:56:27 -0400 Subject: [PATCH 048/176] [vpr][pack] initializer intra_lb_pb_pin_lookup and pass it to alloc_and_load_pb_route --- vpr/src/pack/cluster_legalizer.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vpr/src/pack/cluster_legalizer.cpp b/vpr/src/pack/cluster_legalizer.cpp index 1840514a62e..947fbed2fbd 100644 --- a/vpr/src/pack/cluster_legalizer.cpp +++ b/vpr/src/pack/cluster_legalizer.cpp @@ -1571,7 +1571,7 @@ void ClusterLegalizer::clean_cluster(LegalizationClusterId cluster_id) { // Load the pb_route so we can free the cluster router data. // The pb_route is used when creating a netlist from the legalized clusters. std::vector* saved_lb_nets = cluster.router_data->saved_lb_nets; - cluster.pb->pb_route = alloc_and_load_pb_route(saved_lb_nets, cluster.type); + cluster.pb->pb_route = alloc_and_load_pb_route(saved_lb_nets, cluster.type, intra_lb_pb_pin_lookup_); // Free the router data. free_router_data(cluster.router_data); cluster.router_data = nullptr; @@ -1631,6 +1631,7 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, log_verbosity_ = log_verbosity; VTR_ASSERT(g_vpr_ctx.atom().lookup().atom_pb_bimap().is_empty()); atom_pb_lookup_ = AtomPBBimap(); + intra_lb_pb_pin_lookup_ = IntraLbPbPinLookup(g_vpr_ctx.device().logical_block_types); } void ClusterLegalizer::reset() { From 8902090e363b9fb5c8b0ab273b505dc4fa39a202 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 10:58:23 -0400 Subject: [PATCH 049/176] [vpr][pack] use intra_lb_pb_pin_lookup to get pb_pin from pin number --- vpr/src/pack/cluster_router.cpp | 15 +++++++++------ vpr/src/pack/cluster_router.h | 4 +++- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index 3b4d8ddde7a..41685a141f6 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -113,7 +113,8 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace, - t_logical_block_type_ptr logic_block_type); + t_logical_block_type_ptr logic_block_type, + const IntraLbPbPinLookup& intra_lb_pb_pin_lookup); static std::string describe_lb_type_rr_node(int inode, const t_lb_router_data* router_data); @@ -551,13 +552,14 @@ bool try_intra_lb_route(t_lb_router_data* router_data, /* Creates an array [0..num_pb_graph_pins-1] lookup for intra-logic block routing. Given pb_graph_pin id for clb, lookup atom net that uses that pin. * If pin is not used, stores OPEN at that pin location */ t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, - t_logical_block_type_ptr logic_block_type) { + t_logical_block_type_ptr logic_block_type, + const IntraLbPbPinLookup& intra_lb_pb_pin_lookup) { const std::vector& lb_nets = *intra_lb_nets; int total_pins = logic_block_type->pb_graph_head->total_pb_pins; t_pb_routes pb_route; for (int inet = 0; inet < (int)lb_nets.size(); inet++) { - load_trace_to_pb_route(pb_route, total_pins, lb_nets[inet].atom_net_id, OPEN, lb_nets[inet].rt_tree, logic_block_type); + load_trace_to_pb_route(pb_route, total_pins, lb_nets[inet].atom_net_id, OPEN, lb_nets[inet].rt_tree, logic_block_type, intra_lb_pb_pin_lookup); } return pb_route; @@ -593,7 +595,8 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace, - t_logical_block_type_ptr logic_block_type) { + t_logical_block_type_ptr logic_block_type, + const IntraLbPbPinLookup& intra_lb_pb_pin_lookup) { int ipin = trace->current_node; int driver_pb_pin_id = prev_pin_id; int cur_pin_id = OPEN; @@ -604,14 +607,14 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, pb_route.insert(std::make_pair(cur_pin_id, t_pb_route())); pb_route[cur_pin_id].atom_net_id = net_id; pb_route[cur_pin_id].driver_pb_pin_id = driver_pb_pin_id; - auto pb_graph_pin = logic_block_type->pin_logical_num_to_pb_pin_mapping.at(cur_pin_id); + auto pb_graph_pin = intra_lb_pb_pin_lookup.pb_gpin(logic_block_type->index, cur_pin_id); pb_route[cur_pin_id].pb_graph_pin = pb_graph_pin; } else { VTR_ASSERT(pb_route[cur_pin_id].atom_net_id == net_id); } } for (int itrace = 0; itrace < (int)trace->next_nodes.size(); itrace++) { - load_trace_to_pb_route(pb_route, total_pins, net_id, cur_pin_id, &trace->next_nodes[itrace], logic_block_type); + load_trace_to_pb_route(pb_route, total_pins, net_id, cur_pin_id, &trace->next_nodes[itrace], logic_block_type, intra_lb_pb_pin_lookup); } } diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index 717f971f95e..a97067c1e76 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -23,7 +23,9 @@ bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_sel void reset_intra_lb_route(t_lb_router_data* router_data); /* Accessor Functions */ -t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_logical_block_type_ptr logic_block_type); +t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, + t_logical_block_type_ptr logic_block_type, + const IntraLbPbPinLookup& intra_lb_pb_pin_lookup); void free_pb_route(t_pb_route* free_pb_route); #endif From 35941246da403c60074d316d9a95b075121335d8 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Sat, 26 Apr 2025 11:05:06 -0400 Subject: [PATCH 050/176] make format --- vpr/src/pack/cluster_router.cpp | 12 ++++++------ vpr/src/pack/cluster_router.h | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index 41685a141f6..d94a697ee5f 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -108,11 +108,11 @@ static bool is_route_success(t_lb_router_data* router_data); static t_lb_trace* find_node_in_rt(t_lb_trace* rt, int rt_index); static void reset_explored_node_tb(t_lb_router_data* router_data); static void save_and_reset_lb_route(t_lb_router_data* router_data); -static void load_trace_to_pb_route(t_pb_routes& pb_route, - const int total_pins, - const AtomNetId net_id, - const int prev_pin_id, - const t_lb_trace* trace, +static void load_trace_to_pb_route(t_pb_routes& pb_route, + const int total_pins, + const AtomNetId net_id, + const int prev_pin_id, + const t_lb_trace* trace, t_logical_block_type_ptr logic_block_type, const IntraLbPbPinLookup& intra_lb_pb_pin_lookup); @@ -551,7 +551,7 @@ bool try_intra_lb_route(t_lb_router_data* router_data, /* Creates an array [0..num_pb_graph_pins-1] lookup for intra-logic block routing. Given pb_graph_pin id for clb, lookup atom net that uses that pin. * If pin is not used, stores OPEN at that pin location */ -t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, +t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_logical_block_type_ptr logic_block_type, const IntraLbPbPinLookup& intra_lb_pb_pin_lookup) { const std::vector& lb_nets = *intra_lb_nets; diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index a97067c1e76..b1fd31c2415 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -23,7 +23,7 @@ bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_sel void reset_intra_lb_route(t_lb_router_data* router_data); /* Accessor Functions */ -t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, +t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_logical_block_type_ptr logic_block_type, const IntraLbPbPinLookup& intra_lb_pb_pin_lookup); void free_pb_route(t_pb_route* free_pb_route); From 2322aa63d7c18842c07f21ae461f35ca8fc6630f Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sun, 27 Apr 2025 16:31:02 -0400 Subject: [PATCH 051/176] add vtr::array to docs --- doc/src/api/vtrutil/containers.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/src/api/vtrutil/containers.rst b/doc/src/api/vtrutil/containers.rst index 879e01a4ca2..b0eb95ec2cc 100644 --- a/doc/src/api/vtrutil/containers.rst +++ b/doc/src/api/vtrutil/containers.rst @@ -8,6 +8,12 @@ vtr_vector :project: vtr :sections: briefdescription detaileddescription innernamespace innerclass public-func typedef func +vtr_array +---------- +.. doxygenfile:: vtr_array.h + :project: vtr + :sections: briefdescription detaileddescription innernamespace innerclass public-func typedef func + vtr_small_vector ---------------- .. doxygenclass:: vtr::small_vector From 623132ee3924a8b4cd5934fdb1d5dcf4cf7e3e50 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 28 Apr 2025 08:56:46 -0400 Subject: [PATCH 052/176] [vpr][pack] remove casting net id --- vpr/src/pack/sync_netlists_to_routing_flat.cpp | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 9a8f584b966..6318fb274c8 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -172,11 +172,17 @@ static void sync_pb_routes_to_routing(void) { for (ClusterBlockId clb_blk_id : cluster_ctx.clb_nlist.blocks()) { /* Don't erase entries for nets without routing in place (clocks, globals...) */ std::vector pins_to_erase; - auto& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; + t_pb_routes& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; for (auto& [pin, pb_route] : pb_routes) { - /* No route tree: no routing in place, it is global or clock */ - if (!route_ctx.route_trees[ParentNetId(int(pb_route.atom_net_id))]) + /* + * Given that this function is called when flat routing is enabled, + * we can safely assume that the net IDs to index into route_ctx.route_trees + * correspond to the atom net IDs. + */ + if (!route_ctx.route_trees[pb_route.atom_net_id]) { + /* No route tree: no routing in place, it is global or clock */ continue; + } pins_to_erase.push_back(pin); } @@ -266,7 +272,7 @@ static void sync_clustered_netlist_to_routing(void) { for (auto net_id : clb_netlist.nets()) { auto atom_net_id = atom_lookup.atom_net(net_id); - if (!route_ctx.route_trees[ParentNetId(int(atom_net_id))]) + if (!route_ctx.route_trees[atom_net_id]) continue; nets_to_remove.push_back(net_id); @@ -279,7 +285,7 @@ static void sync_clustered_netlist_to_routing(void) { for (auto pin_id : clb_netlist.port_pins(port_id)) { ClusterNetId clb_net_id = clb_netlist.pin_net(pin_id); auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if (atom_net_id && !route_ctx.route_trees[ParentNetId(int(atom_net_id))]) { + if (atom_net_id && !route_ctx.route_trees[atom_net_id]) { skipped_pins++; } else { pins_to_remove.push_back(pin_id); From 2468e8a92595fcc38a3f67247ff6d870e741665a Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 28 Apr 2025 08:59:48 -0400 Subject: [PATCH 053/176] [vpr][pack] add doxygen comment for alloc_and_load_pb_route --- vpr/src/pack/cluster_router.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index b1fd31c2415..ff7f19bca14 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -23,6 +23,16 @@ bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_sel void reset_intra_lb_route(t_lb_router_data* router_data); /* Accessor Functions */ +/** + * @brief Creates an array [0..num_pb_graph_pins-1] for intra-logic block routing lookup. + * Given a pb_graph_pin ID for a CLB, this lookup returns t_pb_route corresponding to that + * pin. + * + * @param intra_lb_nets Vector of intra-logic block nets. + * @param logic_block_type Logic block type of the current cluster. + * @param intra_lb_pb_pin_lookup Intra-logic block pin lookup to get t_pb_graph_pin from a pin ID. + * @return t_pb_routes An array [0..num_pb_graph_pins-1] for intra-logic block routing lookup. + */ t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_logical_block_type_ptr logic_block_type, const IntraLbPbPinLookup& intra_lb_pb_pin_lookup); From 86491fd56f06052bd28cf05951c827f30766e583 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 28 Apr 2025 09:01:15 -0400 Subject: [PATCH 054/176] [vpr][pack] remove redundant parameters --- vpr/src/pack/cluster_router.cpp | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index d94a697ee5f..f971b1919f7 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -109,7 +109,6 @@ static t_lb_trace* find_node_in_rt(t_lb_trace* rt, int rt_index); static void reset_explored_node_tb(t_lb_router_data* router_data); static void save_and_reset_lb_route(t_lb_router_data* router_data); static void load_trace_to_pb_route(t_pb_routes& pb_route, - const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace, @@ -549,17 +548,14 @@ bool try_intra_lb_route(t_lb_router_data* router_data, * Accessor Functions ******************************************************************************************/ -/* Creates an array [0..num_pb_graph_pins-1] lookup for intra-logic block routing. Given pb_graph_pin id for clb, lookup atom net that uses that pin. - * If pin is not used, stores OPEN at that pin location */ t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_logical_block_type_ptr logic_block_type, const IntraLbPbPinLookup& intra_lb_pb_pin_lookup) { const std::vector& lb_nets = *intra_lb_nets; - int total_pins = logic_block_type->pb_graph_head->total_pb_pins; t_pb_routes pb_route; - for (int inet = 0; inet < (int)lb_nets.size(); inet++) { - load_trace_to_pb_route(pb_route, total_pins, lb_nets[inet].atom_net_id, OPEN, lb_nets[inet].rt_tree, logic_block_type, intra_lb_pb_pin_lookup); + for (const auto& lb_net : lb_nets) { + load_trace_to_pb_route(pb_route, lb_net.atom_net_id, OPEN, lb_net.rt_tree, logic_block_type, intra_lb_pb_pin_lookup); } return pb_route; @@ -591,7 +587,6 @@ void free_intra_lb_nets(std::vector* intra_lb_nets) { /* Recurse through route tree trace to populate pb pin to atom net lookup array */ static void load_trace_to_pb_route(t_pb_routes& pb_route, - const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace, @@ -600,6 +595,7 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, int ipin = trace->current_node; int driver_pb_pin_id = prev_pin_id; int cur_pin_id = OPEN; + const int total_pins = logic_block_type->pb_graph_head->total_pb_pins; if (ipin < total_pins) { /* This routing node corresponds with a pin. This node is virtual (ie. sink or source node) */ cur_pin_id = ipin; @@ -607,14 +603,14 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, pb_route.insert(std::make_pair(cur_pin_id, t_pb_route())); pb_route[cur_pin_id].atom_net_id = net_id; pb_route[cur_pin_id].driver_pb_pin_id = driver_pb_pin_id; - auto pb_graph_pin = intra_lb_pb_pin_lookup.pb_gpin(logic_block_type->index, cur_pin_id); + const t_pb_graph_pin* pb_graph_pin = intra_lb_pb_pin_lookup.pb_gpin(logic_block_type->index, cur_pin_id); pb_route[cur_pin_id].pb_graph_pin = pb_graph_pin; } else { VTR_ASSERT(pb_route[cur_pin_id].atom_net_id == net_id); } } for (int itrace = 0; itrace < (int)trace->next_nodes.size(); itrace++) { - load_trace_to_pb_route(pb_route, total_pins, net_id, cur_pin_id, &trace->next_nodes[itrace], logic_block_type, intra_lb_pb_pin_lookup); + load_trace_to_pb_route(pb_route, net_id, cur_pin_id, &trace->next_nodes[itrace], logic_block_type, intra_lb_pb_pin_lookup); } } From 798055c0df86bf7f188d7c054b42e04c48e1c183 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 28 Apr 2025 09:08:07 -0400 Subject: [PATCH 055/176] [vpr][pack] polish load_trace_to_pb_route --- vpr/src/pack/cluster_router.cpp | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index f971b1919f7..068fd4b3391 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -108,6 +108,17 @@ static bool is_route_success(t_lb_router_data* router_data); static t_lb_trace* find_node_in_rt(t_lb_trace* rt, int rt_index); static void reset_explored_node_tb(t_lb_router_data* router_data); static void save_and_reset_lb_route(t_lb_router_data* router_data); + +/** + * @brief Recurse through route tree trace to populate pb pin to atom net lookup array. + * + * @param pb_route Array of pb pin to atom net lookup to be populated in this routine. + * @param net_id Atom net ID of the current net. + * @param prev_pin_id ID of the previous pin in the route tree trace. + * @param trace Current trace node in the route tree. + * @param logic_block_type Logic block type of the current cluster. + * @param intra_lb_pb_pin_lookup Intra-logic block pin lookup to get t_pb_graph_pin from a pin ID. + */ static void load_trace_to_pb_route(t_pb_routes& pb_route, const AtomNetId net_id, const int prev_pin_id, @@ -585,7 +596,6 @@ void free_intra_lb_nets(std::vector* intra_lb_nets) { * Internal Functions ****************************************************************************/ -/* Recurse through route tree trace to populate pb pin to atom net lookup array */ static void load_trace_to_pb_route(t_pb_routes& pb_route, const AtomNetId net_id, const int prev_pin_id, @@ -609,8 +619,8 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, VTR_ASSERT(pb_route[cur_pin_id].atom_net_id == net_id); } } - for (int itrace = 0; itrace < (int)trace->next_nodes.size(); itrace++) { - load_trace_to_pb_route(pb_route, net_id, cur_pin_id, &trace->next_nodes[itrace], logic_block_type, intra_lb_pb_pin_lookup); + for (const auto& trace : trace->next_nodes) { + load_trace_to_pb_route(pb_route, net_id, cur_pin_id, &trace, logic_block_type, intra_lb_pb_pin_lookup); } } From 241589b9f4a9b2d135952e5b243e63d9c9c65e21 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 28 Apr 2025 09:14:11 -0400 Subject: [PATCH 056/176] make format --- vpr/src/pack/cluster_router.h | 1 - vpr/src/pack/sync_netlists_to_routing_flat.cpp | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index ff7f19bca14..cd68f7eea38 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -22,7 +22,6 @@ void set_reset_pb_modes(t_lb_router_data* router_data, const t_pb* pb, const boo bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_selection_status* mode_status); void reset_intra_lb_route(t_lb_router_data* router_data); -/* Accessor Functions */ /** * @brief Creates an array [0..num_pb_graph_pins-1] for intra-logic block routing lookup. * Given a pb_graph_pin ID for a CLB, this lookup returns t_pb_route corresponding to that diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 6318fb274c8..2339f9d2863 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -180,7 +180,7 @@ static void sync_pb_routes_to_routing(void) { * correspond to the atom net IDs. */ if (!route_ctx.route_trees[pb_route.atom_net_id]) { - /* No route tree: no routing in place, it is global or clock */ + /* No route tree: no routing in place, it is global or clock */ continue; } pins_to_erase.push_back(pin); @@ -365,7 +365,7 @@ static void sync_clustered_netlist_to_routing(void) { } PinType pin_type = node_type == OPIN ? PinType::DRIVER : PinType::SINK; - /* Pin already exists. This means a global was connected to here. */ + /* Pin already exists. This means a global net that was not routed (i.e. 'ideal' mode). */ if (clb_netlist.port_pin(port_id, pb_graph_pin->pin_number)) { VTR_LOG_WARN("Pin %s of block %s has a global or clock net" " connected and it has a routing clash with the flat router." From f5bb0eb0913b6401de0b000e8bc7f37b7d22eea7 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 28 Apr 2025 10:23:28 -0400 Subject: [PATCH 057/176] [vpr][pack] fix parameter shadowing --- vpr/src/pack/cluster_router.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index 068fd4b3391..db2c58d6da9 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -619,8 +619,8 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, VTR_ASSERT(pb_route[cur_pin_id].atom_net_id == net_id); } } - for (const auto& trace : trace->next_nodes) { - load_trace_to_pb_route(pb_route, net_id, cur_pin_id, &trace, logic_block_type, intra_lb_pb_pin_lookup); + for (const auto& nxt_trace : trace->next_nodes) { + load_trace_to_pb_route(pb_route, net_id, cur_pin_id, &nxt_trace, logic_block_type, intra_lb_pb_pin_lookup); } } From c14996f50cba03b5c88aadb0b3ec1fc1889cc78f Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Mon, 28 Apr 2025 11:18:27 -0400 Subject: [PATCH 058/176] [AP][HotFix] Fixed Bug With Solver Putting Blocks Off-Device After moving fixed blocks to the center of tiles, there is a very small chance that blocks go off the device due to rounding. This is such a small effect that it does not show up locally on my machine, but it shows up on CI. Clamping the positions of blocks after solving to be just within the device region. --- .../analytical_place/analytical_solver.cpp | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/vpr/src/analytical_place/analytical_solver.cpp b/vpr/src/analytical_place/analytical_solver.cpp index 22a846d43ea..2bc1ec19565 100644 --- a/vpr/src/analytical_place/analytical_solver.cpp +++ b/vpr/src/analytical_place/analytical_solver.cpp @@ -819,13 +819,22 @@ void B2BSolver::store_solution_into_placement(Eigen::VectorXd& x_soln, for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { // Since we are capping the number of iterations, the solver may not // have enough time to converge on a solution that is on the device. - // We just clamp the solution to zero for now. + // Set the solution to be within the device grid. To prevent round-off + // errors causing the position to move outside of the device, we add a + // small buffer (epsilon) to the position. + // TODO: Create a helper method to clamp a position to just within the + // device grid. // TODO: Should handle this better. If the solution is very negative // it may indicate a bug. - if (x_soln[row_id_idx] < 0.0) - x_soln[row_id_idx] = 0.0; - if (y_soln[row_id_idx] < 0.0) - y_soln[row_id_idx] = 0.0; + double epsilon = 0.0001; + if (x_soln[row_id_idx] < epsilon) + x_soln[row_id_idx] = epsilon; + if (x_soln[row_id_idx] >= device_grid_width_) + x_soln[row_id_idx] = device_grid_width_ - epsilon; + if (y_soln[row_id_idx] < epsilon) + y_soln[row_id_idx] = epsilon; + if (y_soln[row_id_idx] >= device_grid_height_) + y_soln[row_id_idx] = device_grid_height_ - epsilon; APRowId row_id = APRowId(row_id_idx); APBlockId blk_id = row_id_to_blk_id_[row_id]; From 896f59b96b7a3fcae201d88a7a98d22f69296c01 Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Mon, 28 Apr 2025 15:48:01 -0400 Subject: [PATCH 059/176] Increase the daily stale issue action API call limit --- .github/workflows/stale.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/stale.yml b/.github/workflows/stale.yml index 5f6e9fd9088..a8db7f5883d 100644 --- a/.github/workflows/stale.yml +++ b/.github/workflows/stale.yml @@ -20,6 +20,11 @@ jobs: # Start from the oldest issues ascending: true + # Upper limit for number of API calls per day + # This worklfow does 2-3 API calls per issue + # including issues that have been marked stale + operations-per-run: 300 + # The configuration below can be used to allow the same behaviour with PRs. # Since we currently don't want to close old PRs, it is commented out but # left here in case we change our mind. From e636d439b9a3fd1fb932e74a923d197456507996 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 28 Apr 2025 16:56:04 -0400 Subject: [PATCH 060/176] [vpr][pack] add a method to get root_ipin --- vpr/src/pack/prepack.cpp | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 6f80d5927a5..c9875af7ff6 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -114,6 +114,8 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, const AtomNetlist& atom_nlist); +static t_pb_graph_pin* get_compatible_chain_root_pin(const t_pack_patterns* chain_pattern, const AtomBlockId blk_id); + static void print_chain_starting_points(t_pack_patterns* chain_pattern); /*****************************************/ @@ -1163,6 +1165,17 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, return AtomBlockId::INVALID(); } +static t_pb_graph_pin* get_compatible_chain_root_pin(const t_pack_patterns* chain_pattern, const AtomBlockId blk_id) { + for (const auto& chain : chain_pattern->chain_root_pins) { + for (const auto& tie_off : chain) { + if (primitive_type_feasible(blk_id, tie_off->parent_node->pb_type)) { + return tie_off; + } + } + } + return nullptr; +} + static void print_pack_molecules(const char* fname, const std::vector& list_of_pack_patterns, const int num_pack_patterns, @@ -1324,10 +1337,9 @@ static AtomBlockId find_new_root_atom_for_chain(const AtomBlockId blk_id, VTR_ASSERT(list_of_pack_patterns->is_chain == true); VTR_ASSERT(list_of_pack_patterns->chain_root_pins.size()); - root_ipin = list_of_pack_patterns->chain_root_pins[0][0]; - root_pb_graph_node = root_ipin->parent_node; + root_ipin = get_compatible_chain_root_pin(list_of_pack_patterns, blk_id); - if (primitive_type_feasible(blk_id, root_pb_graph_node->pb_type) == false) { + if (root_ipin == nullptr) { return AtomBlockId::INVALID(); } @@ -1622,7 +1634,7 @@ static void init_molecule_chain_info(const AtomBlockId blk_id, // pattern assigned to it and the input block should be valid VTR_ASSERT(molecule.pack_pattern && blk_id); - auto root_ipin = molecule.pack_pattern->chain_root_pins[0][0]; + auto root_ipin = get_compatible_chain_root_pin(molecule.pack_pattern, blk_id); auto model_pin = root_ipin->port->model_port; auto pin_bit = root_ipin->pin_number; From e8edbaa55a7ce0c7811107141ee9cc373f670fa2 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 28 Apr 2025 17:47:34 -0400 Subject: [PATCH 061/176] [vpr][pack] remove unused var --- vpr/src/pack/prepack.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index c9875af7ff6..31e1a8b4d1c 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -1332,7 +1332,6 @@ static AtomBlockId find_new_root_atom_for_chain(const AtomBlockId blk_id, const AtomNetlist& atom_nlist) { AtomBlockId new_root_blk_id; t_pb_graph_pin* root_ipin; - t_pb_graph_node* root_pb_graph_node; t_model_ports* model_port; VTR_ASSERT(list_of_pack_patterns->is_chain == true); From 2a5e12e9fcb31bd8561c8becac2fc1797e7f314a Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Tue, 29 Apr 2025 12:26:05 -0400 Subject: [PATCH 062/176] [Router] Added Assert for MQ_IO numQueues and Updated Golden Results Added assert for MultiQueueIO numQueues to ensure it must be greater than two. Updated CI test tasks to ensure the parallel connection router runs in Dijkstra mode to ensure determinism and avoid hanging in CI runs. --- vpr/src/route/multi_queue_d_ary_heap.tpp | 4 +++- .../koios_test/config/config.txt | 6 +++--- .../koios_test/config/golden_results.txt | 10 +++++----- .../strong_flat_router/config/config.txt | 6 +++--- .../config/golden_results.txt | 10 +++++----- .../strong_multiclock/config/config.txt | 6 +++--- .../config/golden_results.txt | 6 +++--- .../strong_timing/config/config.txt | 6 +++--- .../strong_timing/config/golden_results.txt | 10 +++++----- .../config/config.txt | 12 +++++------ .../config/golden_results.txt | 20 ++++++++++++------- 11 files changed, 52 insertions(+), 44 deletions(-) diff --git a/vpr/src/route/multi_queue_d_ary_heap.tpp b/vpr/src/route/multi_queue_d_ary_heap.tpp index e7ed202a7e4..7168762577e 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.tpp +++ b/vpr/src/route/multi_queue_d_ary_heap.tpp @@ -94,7 +94,9 @@ class MultiQueueIO { , NUM_QUEUES(numQueues) , threadNum(numThreads) , numEmpty(numQueues) - , batchSize(batch) {} + , batchSize(batch) { + assert((numQueues >= 2) && "numQueues must be set >= 2"); + } #ifdef PERF uint64_t __attribute__((noinline)) ThreadLocalRandom() { diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt index 3ca35cef4c4..3c7faa4d0f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt @@ -38,6 +38,6 @@ pass_requirements_file=pass_requirements.txt script_params_common=-track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel -script_params_list_add = --enable_parallel_connection_router on -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on +script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt index fa43c27af55..db8e790d221 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 4.41 vpr 75.36 MiB -1 -1 0.19 17940 1 0.05 -1 -1 31600 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77168 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000974867 0.000904716 0.077352 0.0718699 -1 -1 -1 -1 82 3601 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.25 0.377802 0.348243 33448 250998 -1 3687 9 800 863 234820 89374 4.57723 4.57723 -726.049 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.07 0.22 -1 -1 0.04 0.0332833 0.0315356 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 4.54 vpr 75.36 MiB -1 -1 0.19 17936 1 0.05 -1 -1 31376 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77168 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.1 MiB 0.11 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.23 0.000981081 0.000906865 0.0786348 0.0731135 -1 -1 -1 -1 82 3585 15 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.38 0.403967 0.372656 33448 250998 -1 3715 9 792 819 214644 81314 4.57723 4.57723 -685.291 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.06 0.21 -1 -1 0.04 0.0307442 0.0291164 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on 4.52 vpr 75.37 MiB -1 -1 0.20 17940 1 0.05 -1 -1 31712 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77176 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000979303 0.00090991 0.077946 0.0724613 -1 -1 -1 -1 82 3581 10 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.36 0.375357 0.346115 33448 250998 -1 3699 9 747 819 220831 220831 4.57723 4.57723 -679.037 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.08 0.21 -1 -1 0.04 0.0313828 0.0297241 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16 5.06 vpr 74.98 MiB -1 -1 0.19 17956 1 0.05 -1 -1 31380 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 76780 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.0 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000974681 0.00090508 0.0774429 0.0719617 -1 -1 -1 -1 82 3638 20 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.83 0.404389 0.372638 33448 250998 -1 3485 9 735 762 269282 269282 4.57723 4.57723 -660.925 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.14 0.21 -1 -1 0.04 0.0317757 0.0300764 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on 5.20 vpr 74.15 MiB -1 -1 0.22 17572 1 0.06 -1 -1 31392 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 75932 130 40 596 562 1 356 185 14 14 196 dsp_top auto 35.1 MiB 0.11 3253 1906 39109 13750 20961 4398 74.2 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.23 0.000986009 0.000916173 0.0784056 0.0728838 -1 -1 -1 -1 82 3602 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.86 0.418875 0.386466 33448 250998 -1 3679 10 722 785 234800 89746 4.57723 4.57723 -676.631 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.12 0.21 -1 -1 0.04 0.0325316 0.0307593 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 3.48 vpr 75.41 MiB -1 -1 0.19 18324 1 0.06 -1 -1 31768 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77216 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.21 0.000959753 0.000891145 0.0766671 0.0712909 -1 -1 -1 -1 82 3601 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.37 0.355125 0.327648 33448 250998 -1 3687 9 800 863 234820 89374 4.57723 4.57723 -726.049 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.06 0.21 -1 -1 0.04 0.0293975 0.0278224 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 3.89 vpr 75.53 MiB -1 -1 0.23 18320 1 0.05 -1 -1 31776 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77340 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.7 MiB 0.11 3253 1906 39109 13750 20961 4398 75.5 MiB 0.17 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.24 0.00102819 0.000958054 0.0952184 0.0886972 -1 -1 -1 -1 82 3585 15 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.58 0.448941 0.416021 33448 250998 -1 3715 9 792 819 214644 81314 4.57723 4.57723 -685.291 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.07 0.23 -1 -1 0.04 0.0342816 0.0320854 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.44 vpr 76.07 MiB -1 -1 0.24 17952 1 0.05 -1 -1 31776 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77900 130 40 596 562 1 356 185 14 14 196 dsp_top auto 37.0 MiB 0.10 3253 1906 39109 13750 20961 4398 76.1 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000977261 0.000906881 0.0777213 0.0722525 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.15 0.365923 0.337593 33448 250998 -1 3424 10 688 706 802567 802567 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.21 0.21 -1 -1 0.04 0.0310482 0.0293918 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.66 vpr 76.11 MiB -1 -1 0.19 18336 1 0.05 -1 -1 31752 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77936 130 40 596 562 1 356 185 14 14 196 dsp_top auto 37.0 MiB 0.10 3253 1906 39109 13750 20961 4398 76.1 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.21 0.000953879 0.00088635 0.076401 0.0709941 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.35 0.375353 0.346219 33448 250998 -1 3424 10 688 706 784337 784337 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.28 0.21 -1 -1 0.04 0.0314543 0.0297544 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.47 vpr 76.11 MiB -1 -1 0.19 18336 1 0.05 -1 -1 31764 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77936 130 40 596 562 1 356 185 14 14 196 dsp_top auto 37.0 MiB 0.10 3253 1906 39109 13750 20961 4398 76.1 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000953407 0.000885151 0.0766354 0.0712962 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.12 0.360483 0.332708 33448 250998 -1 3424 10 688 706 797445 321701 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.32 0.21 -1 -1 0.04 0.0323769 0.0306371 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt index 122e16a14a2..a9d53562104 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt @@ -27,6 +27,6 @@ pass_requirements_file=pass_requirements.txt script_params_common=-track_memory_usage --route_chan_width 100 --max_router_iterations 100 --router_lookahead map --flat_routing on script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 -script_params_list_add = --enable_parallel_connection_router on -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on +script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index d308c81afd1..385635c2f12 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 7.09 vpr 77.94 MiB -1 -1 1.87 32304 16 0.41 -1 -1 34724 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79808 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.5 MiB 1.86 9794 6883 28689 8164 16986 3539 77.9 MiB 0.45 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00305795 0.00281495 0.226764 0.201621 -1 -1 -1 -1 -1 10585 12 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.17 0.283544 0.251205 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 7.22 vpr 77.26 MiB -1 -1 2.04 31928 16 0.39 -1 -1 33776 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79116 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.2 MiB 1.74 9794 6883 28689 8164 16986 3539 77.3 MiB 0.44 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00285411 0.002454 0.233988 0.206778 -1 -1 -1 -1 -1 10620 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.24 0.301013 0.263687 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on 7.01 vpr 77.55 MiB -1 -1 1.84 32308 16 0.38 -1 -1 34724 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79412 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.2 MiB 1.77 9794 6883 28689 8164 16986 3539 77.6 MiB 0.41 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00217684 0.0019326 0.199185 0.177858 -1 -1 -1 -1 -1 10546 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.30 0.25973 0.230708 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16 8.02 vpr 77.44 MiB -1 -1 1.84 31552 16 0.39 -1 -1 34440 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79296 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.1 MiB 1.70 9794 6883 28689 8164 16986 3539 77.4 MiB 0.36 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00187804 0.00164622 0.167362 0.14756 -1 -1 -1 -1 -1 10692 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.43 0.218922 0.192418 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on 7.25 vpr 77.56 MiB -1 -1 1.84 32324 16 0.39 -1 -1 34576 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79424 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.2 MiB 1.70 9794 6883 28689 8164 16986 3539 77.6 MiB 0.36 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00188091 0.00164873 0.16884 0.149107 -1 -1 -1 -1 -1 10708 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.64 0.225256 0.197955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 6.40 vpr 78.31 MiB -1 -1 1.74 32308 16 0.37 -1 -1 34716 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80192 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.9 MiB 1.66 9794 6883 28689 8164 16986 3539 78.3 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00181398 0.00159035 0.162885 0.143678 -1 -1 -1 -1 -1 10585 12 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.06 0.211804 0.186281 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 6.68 vpr 78.27 MiB -1 -1 1.75 32308 16 0.38 -1 -1 34724 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80152 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.2 MiB 1.66 9794 6883 28689 8164 16986 3539 78.3 MiB 0.40 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.0025167 0.00230357 0.197326 0.174372 -1 -1 -1 -1 -1 10620 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.20 0.253737 0.222606 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 10.02 vpr 78.31 MiB -1 -1 1.72 32320 16 0.38 -1 -1 34724 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80188 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.9 MiB 1.64 9794 6883 28689 8164 16986 3539 78.3 MiB 0.34 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00179584 0.0015676 0.161529 0.142039 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 4.69 0.209219 0.183788 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 10.89 vpr 78.57 MiB -1 -1 1.76 31720 16 0.37 -1 -1 34324 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80456 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.3 MiB 1.71 9794 6883 28689 8164 16986 3539 78.6 MiB 0.36 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00187306 0.00163416 0.165658 0.145989 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 5.43 0.216342 0.190382 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 9.29 vpr 78.70 MiB -1 -1 1.96 32320 16 0.40 -1 -1 34556 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80592 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.5 MiB 1.65 9794 6883 28689 8164 16986 3539 78.7 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00185537 0.00163023 0.165615 0.146041 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 3.65 0.215249 0.189458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt index 09855147b8b..3a66d472e2d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt @@ -27,6 +27,6 @@ pass_requirements_file=pass_requirements_multiclock.txt script_params_common=-starting_stage vpr -sdc_file tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/multiclock.sdc script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 -script_params_list_add = --enable_parallel_connection_router on -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on +script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 2f7e01b0b8e..dce7634e482 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt index 1ec5bc88ec3..8e1af6295c1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt @@ -27,6 +27,6 @@ pass_requirements_file=pass_requirements.txt script_params_common = -track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 -script_params_list_add = --enable_parallel_connection_router on -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on +script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index 5cbe4ea049b..e6295ec48fe 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.80 vpr 66.19 MiB -1 -1 0.22 18464 3 0.07 -1 -1 32740 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67776 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000573836 0.000534893 0.0449119 0.0418379 -1 -1 -1 -1 38 1437 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.35 0.164006 0.149599 12522 62564 -1 1141 11 437 710 29360 10219 1.94502 1.94502 -130.926 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0193638 0.0180814 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 1.78 vpr 66.56 MiB -1 -1 0.22 18460 3 0.07 -1 -1 33112 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68160 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.6 MiB 0.14 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000665545 0.000617009 0.0528489 0.0485457 -1 -1 -1 -1 38 1420 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.32 0.145628 0.130364 12522 62564 -1 1150 9 446 701 30426 10498 1.94502 1.94502 -131.108 -1.94502 -0.67939 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0162708 0.0148159 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on 1.83 vpr 65.93 MiB -1 -1 0.22 18452 3 0.07 -1 -1 32968 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67512 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.11 1695 684 72933 23047 34243 15643 65.9 MiB 0.14 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.00057601 0.000537702 0.0453956 0.0423047 -1 -1 -1 -1 38 1417 9 5.66058e+06 4.21279e+06 319130. 2216.18 0.35 0.161904 0.148079 12522 62564 -1 1152 9 438 706 28653 28653 1.94502 1.94502 -129.801 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0178252 0.0167004 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16 1.93 vpr 65.91 MiB -1 -1 0.23 18864 3 0.07 -1 -1 32740 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67492 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.11 1695 684 72933 23047 34243 15643 65.9 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000571739 0.000533473 0.0449704 0.0418885 -1 -1 -1 -1 38 1403 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.44 0.164243 0.150129 12522 62564 -1 1126 9 422 667 50272 50272 1.94502 1.94502 -131.371 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.05 0.04 -1 -1 0.01 0.0176487 0.0165339 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on 1.95 vpr 66.02 MiB -1 -1 0.22 18476 3 0.07 -1 -1 32744 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67608 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.15 1695 684 72933 23047 34243 15643 66.0 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000573161 0.000534076 0.0449252 0.0418347 -1 -1 -1 -1 38 1408 11 5.66058e+06 4.21279e+06 319130. 2216.18 0.40 0.162733 0.14864 12522 62564 -1 1155 11 436 701 33997 11289 1.94502 1.94502 -131.251 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.05 0.05 -1 -1 0.01 0.022968 0.0212952 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.84 vpr 66.93 MiB -1 -1 0.27 18116 3 0.11 -1 -1 32740 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68536 99 130 344 474 1 227 298 12 12 144 clb auto 27.2 MiB 0.11 1695 684 72933 23047 34243 15643 66.9 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.00056171 0.000523958 0.0439825 0.040974 -1 -1 -1 -1 38 1437 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.33 0.159159 0.145356 12522 62564 -1 1141 11 437 710 29360 10219 1.94502 1.94502 -130.926 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.018542 0.0172924 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 1.73 vpr 66.80 MiB -1 -1 0.22 18460 3 0.07 -1 -1 33108 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68400 99 130 344 474 1 227 298 12 12 144 clb auto 27.0 MiB 0.11 1695 684 72933 23047 34243 15643 66.8 MiB 0.15 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000728205 0.000689323 0.0537866 0.0492926 -1 -1 -1 -1 38 1420 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.32 0.142488 0.127075 12522 62564 -1 1150 9 446 701 30426 10498 1.94502 1.94502 -131.108 -1.94502 -0.67939 -0.29768 406292. 2821.48 0.01 0.02 0.04 -1 -1 0.01 0.0139845 0.0127141 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.79 vpr 66.67 MiB -1 -1 0.21 18864 3 0.07 -1 -1 32736 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68272 99 130 344 474 1 227 298 12 12 144 clb auto 26.9 MiB 0.11 1695 684 72933 23047 34243 15643 66.7 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000564139 0.000525059 0.0443486 0.0412882 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.40 0.155724 0.142204 12522 62564 -1 1128 9 408 669 127433 127433 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.04 0.04 -1 -1 0.01 0.0168763 0.0158171 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.93 vpr 66.61 MiB -1 -1 0.22 18860 3 0.07 -1 -1 32736 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68208 99 130 344 474 1 227 298 12 12 144 clb auto 26.9 MiB 0.11 1695 684 72933 23047 34243 15643 66.6 MiB 0.14 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000575717 0.000533107 0.0463823 0.0432761 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.48 0.159837 0.146027 12522 62564 -1 1128 9 408 669 124672 124672 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.07 0.04 -1 -1 0.01 0.0167421 0.0156627 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 2.03 vpr 66.94 MiB -1 -1 0.22 18476 3 0.07 -1 -1 33096 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68544 99 130 344 474 1 227 298 12 12 144 clb auto 27.6 MiB 0.11 1695 684 72933 23047 34243 15643 66.9 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.00057061 0.000532262 0.0451549 0.042097 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.58 0.198386 0.181634 12522 62564 -1 1128 9 408 669 125594 43231 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.05 0.04 -1 -1 0.01 0.016725 0.0156512 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt index 6af15346384..68cc1e4a51d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt @@ -31,9 +31,9 @@ script_params_list_add = --timing_update_type incremental script_params_list_add = --timing_update_type incremental --quench_recompute_divider 999999999 #Do post-move incremental STA during quench script_params_list_add = --timing_update_type incremental --router_algorithm parallel --num_workers 4 # rarely exercised code path script_params_list_add = --timing_update_type full --router_algorithm parallel --num_workers 4 -script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on -script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on -script_params_list_add = --timing_update_type full --enable_parallel_connection_router on -script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 -script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt index e65df342f6a..8cd97555576 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt @@ -1,7 +1,13 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.06 vpr 65.94 MiB -1 -1 0.49 27024 5 0.12 -1 -1 36972 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67520 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000242517 0.000210755 0.00440565 0.00392683 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0164282 0.0146736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.57 vpr 66.14 MiB -1 -1 0.70 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000439525 0.000384869 0.00748551 0.00667971 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.02 0.0256815 0.0230005 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.67 vpr 66.16 MiB -1 -1 0.82 27152 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 3.5959e-05 2.737e-05 0.00308117 0.00275747 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0135928 0.0105523 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.25 vpr 66.16 MiB -1 -1 0.65 27036 5 0.12 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000221863 9.7941e-05 0.00222519 0.00187901 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.00928043 0.00694563 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.74 vpr 66.05 MiB -1 -1 0.84 26784 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67632 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 5.1198e-05 3.2395e-05 0.002938 0.00248994 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.02 0.0136494 0.00987341 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 2.01 vpr 66.03 MiB -1 -1 0.85 27040 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67616 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00150082 0.00142957 0.0169996 0.0159511 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.07 0.0553928 0.0438556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.13 vpr 64.25 MiB -1 -1 0.41 23444 5 0.11 -1 -1 32264 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65796 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.02 198 153 432 69 336 27 64.3 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000226854 0.000206508 0.00419594 0.00386458 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.0138664 0.0124915 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.21 vpr 64.64 MiB -1 -1 0.47 23444 5 0.11 -1 -1 32816 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66192 10 2 181 183 1 35 24 6 6 36 clb auto 25.7 MiB 0.02 198 153 432 69 336 27 64.6 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000225754 0.000204889 0.00418926 0.0038596 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.0139128 0.0125426 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.14 vpr 64.00 MiB -1 -1 0.41 23444 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65540 10 2 181 183 1 35 24 6 6 36 clb auto 25.0 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 6.276e-06 2.373e-06 0.00173917 0.00155594 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.00773399 0.0057366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.15 vpr 64.67 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66224 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.02 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000115076 2.5133e-05 0.00166669 0.00142568 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.00749984 0.00567704 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.14 vpr 64.68 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66228 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.03 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 5.327e-06 1.22e-06 0.00176541 0.00146867 -1 -1 -1 -1 -1 142 18 646728 646728 138825. 3856.24 0.01 0.00817779 0.00569878 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 1.15 vpr 64.64 MiB -1 -1 0.42 23460 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66196 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.03 198 153 432 69 336 27 64.6 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000402289 0.000380879 0.00640867 0.00586659 -1 -1 -1 -1 -1 142 18 646728 646728 138825. 3856.24 0.02 0.0190248 0.0169558 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.18 vpr 64.67 MiB -1 -1 0.45 23464 5 0.11 -1 -1 32824 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66220 10 2 181 183 1 35 24 6 6 36 clb auto 25.6 MiB 0.02 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.939e-06 1.304e-06 0.002185 0.00196709 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.00872826 0.00675842 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.19 vpr 64.66 MiB -1 -1 0.42 23460 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66216 10 2 181 183 1 35 24 6 6 36 clb auto 25.6 MiB 0.02 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.081e-06 1.044e-06 0.0015854 0.00142828 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.05 0.00824227 0.00621395 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.15 vpr 64.67 MiB -1 -1 0.41 23464 5 0.11 -1 -1 32816 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66220 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.02 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.271e-06 1.168e-06 0.00157844 0.00142246 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.00783423 0.00592468 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.15 vpr 64.64 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32816 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66196 10 2 181 183 1 35 24 6 6 36 clb auto 25.6 MiB 0.02 198 153 432 69 336 27 64.6 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000225699 0.000205384 0.0041722 0.00384118 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.0146306 0.0131119 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.17 vpr 64.15 MiB -1 -1 0.41 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65688 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 64.1 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.00024202 0.000220962 0.00489645 0.0045329 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.06 0.0155069 0.0139264 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.20 vpr 64.65 MiB -1 -1 0.41 23464 5 0.12 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66200 10 2 181 183 1 35 24 6 6 36 clb auto 25.6 MiB 0.02 198 153 432 69 336 27 64.6 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000234309 0.000213247 0.00431784 0.00397848 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.06 0.0150147 0.0134424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From 8197dcb2993b44eb7f3119d6bb26c2cb066315b8 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Mon, 28 Apr 2025 16:24:58 -0400 Subject: [PATCH 063/176] [AP][HotFix] Placed Fixed Blocks First During IP The cost terms in the AP initial placer were not placing fixed blocks early enough, causing other blocks to take their place and causing the initial placer to not return a solution. Blocks which have region constraints are now placed first based on how constrained they are. More constrained blocks (can only be placed in a smaller region) will be placed first. Also found that macros that contained fixed blocks were not observing these constraints when calculating the centroid position of the macro. For constrained macros, projected the centroid position onto the partition region to get the closest point in the partition region to the calculated centroid. This new centroid is used to then perform the placement. --- vpr/src/place/initial_placement.cpp | 65 ++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index aac91e0fd65..a84d005e2f6 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -579,6 +580,43 @@ static t_flat_pl_loc find_centroid_loc_from_flat_placement(const t_pl_macro& pl_ if (acc_weight > 0.f) { centroid /= acc_weight; } + + // If the root cluster is constrained, project the centroid onto its + // partition region. This will move the centroid position to the closest + // position within the partition region. + ClusterBlockId head_cluster_id = pl_macro.members[0].blk_index; + if (is_cluster_constrained(head_cluster_id)) { + // Get the partition region of the head. This is the partition region + // that affects the entire macro. + const PartitionRegion& head_pr = g_vpr_ctx.floorplanning().cluster_constraints[head_cluster_id]; + // For each region, find the closest point in that region to the centroid + // and save the closest of all regions. + t_flat_pl_loc best_projected_pos = centroid; + float best_distance = std::numeric_limits::max(); + VTR_ASSERT_MSG(centroid.layer == 0, + "3D FPGAs not supported for this part of the code yet"); + for (const Region& region : head_pr.get_regions()) { + const vtr::Rect& rect = region.get_rect(); + // Note: We add 0.999 here since the partition region is in grid + // space, so it treats tile positions as having size 0x0 when + // they really are 1x1. + float proj_x = std::clamp(centroid.x, rect.xmin(), rect.xmax() + 0.999); + float proj_y = std::clamp(centroid.y, rect.ymin(), rect.ymax() + 0.999); + float dx = std::abs(proj_x - centroid.x); + float dy = std::abs(proj_y - centroid.y); + float dist = dx + dy; + if (dist < best_distance) { + best_projected_pos.x = proj_x; + best_projected_pos.y = proj_y; + best_distance = dist; + } + } + VTR_ASSERT_SAFE(best_distance != std::numeric_limits::max()); + // Return the point within the partition region that is closest to the + // original centroid. + return best_projected_pos; + } + return centroid; } @@ -1594,6 +1632,7 @@ static inline void place_all_blocks_ap(enum e_pad_loc_type pad_loc_type, const FlatPlacementInfo& flat_placement_info) { const ClusteredNetlist& cluster_netlist = g_vpr_ctx.clustering().clb_nlist; const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + const auto& cluster_constraints = g_vpr_ctx.floorplanning().cluster_constraints; // Create a list of clusters to place. std::vector clusters_to_place; @@ -1615,6 +1654,7 @@ static inline void place_all_blocks_ap(enum e_pad_loc_type pad_loc_type, constexpr float macro_size_weight = 1.0f; constexpr float std_dev_weight = 4.0f; vtr::vector cluster_score(cluster_netlist.blocks().size(), 0.0f); + vtr::vector cluster_constr_area(cluster_netlist.blocks().size(), std::numeric_limits::max()); for (ClusterBlockId blk_id : cluster_netlist.blocks()) { // Compute the standard deviation of the positions of all atoms in the // given macro. This is a measure of how much the atoms "want" to be @@ -1642,9 +1682,32 @@ static inline void place_all_blocks_ap(enum e_pad_loc_type pad_loc_type, // should be placed first. cluster_score[blk_id] = (macro_size_weight * normalized_macro_size) + (std_dev_weight * (1.0f - normalized_std_dev)); + + // If the cluster is constrained, compute how much area its constrained + // region takes up. This will be used to place "more constrained" blocks + // first. + // TODO: The cluster constrained area can be incorperated into the cost + // somehow. + if (is_cluster_constrained(blk_id)) { + const PartitionRegion& pr = cluster_constraints[blk_id]; + float area = 0.0f; + for (const Region& region : pr.get_regions()) { + const vtr::Rect region_rect = region.get_rect(); + // Note: Add 1 here since the width is in grid space (i.e. width + // of 0 means it can only be placed in 1 x coordinate). + area += (region_rect.width() + 1) * (region_rect.height() + 1); + } + cluster_constr_area[blk_id] = area; + } } std::stable_sort(clusters_to_place.begin(), clusters_to_place.end(), [&](ClusterBlockId lhs, ClusterBlockId rhs) { - // Sort list such that higher score clusters are placed first. + // Sort the list such that: + // 1) Clusters that are constrained to less area on the device are placed + // first. + if (cluster_constr_area[lhs] != cluster_constr_area[rhs]) { + return cluster_constr_area[lhs] < cluster_constr_area[rhs]; + } + // 2) Higher score clusters are placed first. return cluster_score[lhs] > cluster_score[rhs]; }); From 26d4221052bce54c780aaaa7525d1eb3523a8bbf Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Wed, 23 Apr 2025 16:29:56 -0400 Subject: [PATCH 064/176] [STA] Added Option to Remove Parameters from Post-Implementation Netlist When performing post-implementation timing analysis using OpenSTA, the generated netlist cannot use parameters since each module needs to correspond with a cell in a liberty file. Added a command-line option which tells the netlist writer to not use parameters when generating the netlist. If a primitive cannot be generated without using parameters, it will error out. --- doc/src/vpr/command_line_usage.rst | 10 ++ vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/ShowSetup.cpp | 1 + vpr/src/base/netlist_writer.cpp | 124 ++++++++++++------ vpr/src/base/read_options.cpp | 10 ++ vpr/src/base/read_options.h | 1 + vpr/src/base/vpr_types.h | 1 + ..._post_verilog_i_gnd_o_unconnected.golden.v | 3 +- ...post_verilog_i_nets_o_unconnected.golden.v | 3 +- ...post_verilog_i_unconnected_o_nets.golden.v | 3 +- ...rilog_i_unconnected_o_unconnected.golden.v | 3 +- ..._post_verilog_i_vcc_o_unconnected.golden.v | 3 +- 12 files changed, 112 insertions(+), 51 deletions(-) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index f21ee85f1eb..77eb679ca6f 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1730,6 +1730,16 @@ Analysis Options **Default:** ``unconnected`` +.. option:: --post_synth_netlist_module_parameters { on | off } + + Controls whether the post-synthesis netlist output by VTR can use Verilog parameters + or not. When using the post-synthesis netlist for external timing analysis, + some tools cannot accept the netlist if it contains parameters. By setting + this option to ``off``, VPR will try to represent the netlist using non-parameterized + modules. + + **Default:** ``on`` + .. option:: --timing_report_npaths Controls how many timing paths are reported. diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index e645b35e538..f08d79518c5 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -714,6 +714,7 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.post_synth_netlist_unconn_input_handling = Options.post_synth_netlist_unconn_input_handling; analysis_opts.post_synth_netlist_unconn_output_handling = Options.post_synth_netlist_unconn_output_handling; + analysis_opts.post_synth_netlist_module_parameters = Options.post_synth_netlist_module_parameters.value(); analysis_opts.timing_update_type = Options.timing_update_type; analysis_opts.write_timing_summary = Options.write_timing_summary; diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index f21200e97ee..fba46d4818c 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -717,6 +717,7 @@ static void ShowAnalysisOpts(const t_analysis_opts& AnalysisOpts) { VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown post_synth_netlist_unconn_handling\n"); } } + VTR_LOG("AnalysisOpts.post_synth_netlist_module_parameters: %s\n", AnalysisOpts.post_synth_netlist_module_parameters ? "on" : "off"); VTR_LOG("\n"); } diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp index 9b4765967fc..968d39c626a 100644 --- a/vpr/src/base/netlist_writer.cpp +++ b/vpr/src/base/netlist_writer.cpp @@ -275,7 +275,7 @@ class LutInst : public Instance { std::map> port_conns, /// timing_arc_values, /// port_conns, ///first << "(" << escape_verilog_identifier(iter->second) << ")"; @@ -607,6 +630,7 @@ class LatchInst : public Instance { DelayTriple tcq_delay_triple_; ///second)) { - prefix << iter->second.length() << "'b"; - } + os << indent(depth) << type_name_; + + // Print the parameters if any are provided. + if (params_.size() > 0) { + if (opts_.post_synth_netlist_module_parameters) { + os << " #(\n"; + + //Verilog parameters + for (auto iter = params_.begin(); iter != params_.end(); ++iter) { + /* Prepend a prefix if needed */ + std::stringstream prefix; + if (is_binary_param(iter->second)) { + prefix << iter->second.length() << "'b"; + } - os << indent(depth + 1) << "." << iter->first << "(" << prefix.str() << iter->second << ")"; - if (iter != --params_.end()) { - os << ","; + os << indent(depth + 1) << "." << iter->first << "(" << prefix.str() << iter->second << ")"; + if (iter != --params_.end()) { + os << ","; + } + os << "\n"; + } + os << indent(depth) << ")"; + } else { + // TODO: RAMs are considered black box instructions. These can + // probably be handled similar to LUTs. + VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER, + "Cannot generate black box instruction of type %s " + "without using parameters.", + type_name_.c_str()); } - os << "\n"; } //Instance name - os << indent(depth) << ") " << escape_verilog_identifier(inst_name_) << " (\n"; + os << " " << escape_verilog_identifier(inst_name_) << " (\n"; //Input Port connections for (auto iter = input_port_conns_.begin(); iter != input_port_conns_.end(); ++iter) { @@ -1328,6 +1367,9 @@ class NetlistWriterVisitor : public NetlistVisitor { double tsu = pb_graph_node->input_pins[0][0].tsu; DelayTriple tsu_triple(tsu, tsu, tsu); + double thld = pb_graph_node->input_pins[0][0].thld; + DelayTriple thld_triple(thld, thld, thld); + //Output (Q) int output_cluster_pin_idx = pb_graph_node->output_pins[0][0].pin_count_in_cluster; //Unique pin index in cluster VTR_ASSERT(top_pb_route.count(output_cluster_pin_idx)); @@ -1349,7 +1391,7 @@ class NetlistWriterVisitor : public NetlistVisitor { LatchInst::Type type = LatchInst::Type::RISING_EDGE; vtr::LogicValue init_value = vtr::LogicValue::FALSE; - return std::make_shared(inst_name, port_conns, type, init_value, tcq_triple, tsu_triple); + return std::make_shared(inst_name, port_conns, type, init_value, tcq_triple, tsu_triple, thld_triple, opts_); } /** diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 4451dd720cd..41d1af33800 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -2997,6 +2997,16 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("unconnected") .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.post_synth_netlist_module_parameters, "--post_synth_netlist_module_parameters") + .help( + "Controls whether the post-synthesis netlist output by VTR can use Verilog parameters " + "or not. When using the post-synthesis netlist for external timing analysis, " + "some tools cannot accept the netlist if it contains parameters. By setting " + "this option to off, VPR will try to represent the netlist using non-parameterized " + "modules\n") + .default_value("on") + .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.write_timing_summary, "--write_timing_summary") .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index a71ba63428a..13c0d93f3fe 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -265,6 +265,7 @@ struct t_options { argparse::ArgValue echo_dot_timing_graph_node; argparse::ArgValue post_synth_netlist_unconn_input_handling; argparse::ArgValue post_synth_netlist_unconn_output_handling; + argparse::ArgValue post_synth_netlist_module_parameters; argparse::ArgValue write_timing_summary; }; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 64e2a24ba24..f71720325a5 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1278,6 +1278,7 @@ struct t_analysis_opts { bool gen_post_implementation_merged_netlist; e_post_synth_netlist_unconn_handling post_synth_netlist_unconn_input_handling; e_post_synth_netlist_unconn_handling post_synth_netlist_unconn_output_handling; + bool post_synth_netlist_module_parameters; int timing_report_npaths; e_timing_report_detail timing_report_detail; diff --git a/vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v b/vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v index 05035b1c749..8bb35ebbcda 100644 --- a/vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v +++ b/vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v @@ -199,8 +199,7 @@ module unconnected ( wire \__vpr__unconn7 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ 1'b0, 1'b0, diff --git a/vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v b/vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v index 4c306642088..f977b09acc4 100644 --- a/vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v +++ b/vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v @@ -204,8 +204,7 @@ module unconnected ( wire \__vpr__unconn12 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ __vpr__unconn0, __vpr__unconn1, diff --git a/vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v b/vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v index 7245c3c9e73..4af549ca9c4 100644 --- a/vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v +++ b/vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v @@ -200,8 +200,7 @@ module unconnected ( wire \__vpr__unconn8 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ 1'bX, 1'bX, diff --git a/vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v b/vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v index 5e8d8202562..595917b0d16 100644 --- a/vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v +++ b/vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v @@ -199,8 +199,7 @@ module unconnected ( wire \__vpr__unconn7 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ 1'bX, 1'bX, diff --git a/vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v b/vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v index 75004405927..c9a6fc5e2d0 100644 --- a/vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v +++ b/vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v @@ -199,8 +199,7 @@ module unconnected ( wire \__vpr__unconn7 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ 1'b1, 1'b1, From ceb2ec74d5787d53a3bf8ee8cf114262b89b4632 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Tue, 29 Apr 2025 17:11:18 -0400 Subject: [PATCH 065/176] [Tatum][Parse] Fixed Extraneous Warning With get_clocks The get_clocks command is used in an SDC file to reference a set of clocks by name using a regex string. The code to do this tries to produce a warning if get_clocks is used on a regex string and no clocks could be found. The issue is that the code to do this was mistakenly producing this warning for each clock in the circuit. For example, if we had {clk1, clk2, clk3} and we wanted to do "get_clocks {clk3}", we will get two warnings since clk1 and clk2 did not match. Fixed this by moving the warning out of one loop nest. --- vpr/src/timing/read_sdc.cpp | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/vpr/src/timing/read_sdc.cpp b/vpr/src/timing/read_sdc.cpp index e8db27b9a28..df35c6c0c63 100644 --- a/vpr/src/timing/read_sdc.cpp +++ b/vpr/src/timing/read_sdc.cpp @@ -946,12 +946,11 @@ class SdcParseCallback : public sdcparse::Callback { } } } - - if (!found) { - VTR_LOGF_WARN(fname_.c_str(), lineno_, - "get_clocks target name or pattern '%s' matched no clocks\n", - clock_glob_pattern.c_str()); - } + } + if (!found) { + VTR_LOGF_WARN(fname_.c_str(), lineno_, + "get_clocks target name or pattern '%s' matched no clocks\n", + clock_glob_pattern.c_str()); } } From cac5297d0e781b0dcd240a2dd3adfae94d933f78 Mon Sep 17 00:00:00 2001 From: Amirhossein Poolad Date: Tue, 29 Apr 2025 12:17:05 -0400 Subject: [PATCH 066/176] Remove PR staling This commit sets the number of days before marking issues or PRs as stale to 100 years. This number is overriden for issues to be 1 years but stays 100 years for PRs. This means that PR effectively do not get marked as stale. --- .github/workflows/stale.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/stale.yml b/.github/workflows/stale.yml index a8db7f5883d..fb4a487b2e8 100644 --- a/.github/workflows/stale.yml +++ b/.github/workflows/stale.yml @@ -10,6 +10,11 @@ jobs: steps: - uses: actions/stale@v9 with: + # Set default number of days before being marked stale to 100 years + # This will be overriden by "days-before-issue-stale" and "days-before-pr-stale" + # This is done to avoid marking PRs as stale, as it is not something + # we want to do. + days-before-stale: 36500 # The message to be shown for stale issues stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.' close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.' From ccf8c1a3d1aa36507033197953a7c0bacdc3d4bc Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Thu, 24 Apr 2025 12:57:12 -0400 Subject: [PATCH 067/176] [LibArchFPGA] Updating Model Data Structures The logical models (the technology-mapped logical blocks) for an architecture were stored using two independent linked lists. One for the library models (the models that all architectures have, such as luts and ffs) and one of the user models. This linked lists were hard to traverse and were injecting pointers all across VPR. Created a new class to store and manage the logical models. This class maintains a unique ID for each logical model (similar to the netlist data structures in VPR). It also contains helper methods to make working with the logical models easier. --- libs/libarchfpga/src/arch_check.cpp | 95 +- libs/libarchfpga/src/arch_check.h | 6 +- libs/libarchfpga/src/arch_types.h | 9 - libs/libarchfpga/src/arch_util.cpp | 252 +--- libs/libarchfpga/src/arch_util.h | 8 - libs/libarchfpga/src/echo_arch.cpp | 97 +- libs/libarchfpga/src/logic_types.cpp | 171 +++ libs/libarchfpga/src/logic_types.h | 233 +++- libs/libarchfpga/src/physical_types.h | 5 +- .../src/read_fpga_interchange_arch.cpp | 116 +- libs/libarchfpga/src/read_xml_arch_file.cpp | 62 +- libs/libarchfpga/src/write_models_bb.cpp | 60 +- odin_ii/src/core/adders.cpp | 8 +- odin_ii/src/core/hard_blocks.cpp | 26 +- odin_ii/src/core/multipliers.cpp | 8 +- odin_ii/src/verilog/verilog_writer.cpp | 8 +- parmys/parmys-plugin/core/adder.cc | 10 +- parmys/parmys-plugin/core/hard_block.cc | 40 +- parmys/parmys-plugin/core/multiplier.cc | 8 +- parmys/parmys-plugin/parmys.cc | 5 +- parmys/parmys-plugin/parmys_arch.cc | 12 +- utils/fasm/src/fasm.cpp | 6 +- utils/vqm2blif/src/base/hard_block_recog.cpp | 19 +- utils/vqm2blif/src/base/preprocess.cpp | 41 +- utils/vqm2blif/src/base/vqm2blif.h | 3 +- utils/vqm2blif/src/base/vqm2blif_util.cpp | 60 +- utils/vqm2blif/src/base/vqm2blif_util.h | 18 +- utils/vqm2blif/src/main.cpp | 284 ++-- .../carpat/carpat_stratixiv_arch_timing.blif | 1190 ++++++++--------- .../murax/murax_stratixiv_arch_timing.blif | 104 +- ...csb_152_tap_fir_stratixiv_arch_timing.blif | 38 +- vpr/src/analysis/timing_reports.cpp | 8 +- .../analytical_placement_flow.cpp | 2 +- .../flat_placement_mass_calculator.cpp | 55 +- vpr/src/analytical_place/full_legalizer.cpp | 13 +- vpr/src/analytical_place/model_grouper.cpp | 77 +- vpr/src/analytical_place/model_grouper.h | 17 +- .../analytical_place/partial_legalizer.cpp | 112 +- vpr/src/analytical_place/partial_legalizer.h | 14 +- vpr/src/base/SetupVPR.cpp | 9 +- vpr/src/base/SetupVPR.h | 3 - vpr/src/base/atom_netlist.cpp | 28 +- vpr/src/base/atom_netlist.h | 12 +- vpr/src/base/atom_netlist_utils.cpp | 181 ++- vpr/src/base/atom_netlist_utils.h | 27 +- vpr/src/base/check_netlist.cpp | 6 +- vpr/src/base/clustered_netlist.cpp | 11 +- vpr/src/base/clustered_netlist.h | 4 +- vpr/src/base/netlist_writer.cpp | 69 +- vpr/src/base/netlist_writer.h | 6 +- vpr/src/base/read_blif.cpp | 151 +-- vpr/src/base/read_blif.h | 8 +- vpr/src/base/read_circuit.cpp | 33 +- vpr/src/base/read_circuit.h | 6 +- vpr/src/base/read_interchange_netlist.cpp | 72 +- vpr/src/base/read_interchange_netlist.h | 5 +- vpr/src/base/read_netlist.cpp | 4 +- vpr/src/base/vpr_api.cpp | 20 +- vpr/src/base/vpr_api.h | 2 - vpr/src/base/vpr_types.cpp | 9 +- vpr/src/base/vpr_types.h | 4 +- vpr/src/draw/intra_logic_block.cpp | 5 +- vpr/src/pack/cluster_legalizer.cpp | 15 +- vpr/src/pack/cluster_legalizer.h | 3 + vpr/src/pack/cluster_util.cpp | 35 +- vpr/src/pack/cluster_util.h | 6 +- vpr/src/pack/greedy_candidate_selector.cpp | 21 +- vpr/src/pack/greedy_candidate_selector.h | 11 +- vpr/src/pack/greedy_clusterer.cpp | 26 +- vpr/src/pack/greedy_clusterer.h | 4 +- vpr/src/pack/greedy_seed_selector.cpp | 31 +- vpr/src/pack/greedy_seed_selector.h | 2 + vpr/src/pack/noc_aware_cluster_util.cpp | 9 +- vpr/src/pack/noc_aware_cluster_util.h | 3 +- vpr/src/pack/pack.cpp | 1 + vpr/src/pack/pb_type_graph.cpp | 5 +- vpr/src/pack/prepack.cpp | 45 +- vpr/src/pack/prepack.h | 13 +- vpr/src/place/placement_log_printer.cpp | 3 +- vpr/src/power/power.cpp | 4 +- vpr/src/power/power_sizing.cpp | 5 +- vpr/src/route/route_common.cpp | 8 +- vpr/src/route/route_utils.cpp | 3 +- vpr/src/server/pathhelper.cpp | 3 +- vpr/src/timing/PreClusterDelayCalculator.h | 10 +- .../timing/PreClusterTimingGraphResolver.cpp | 6 +- .../timing/PreClusterTimingGraphResolver.h | 4 + vpr/src/timing/PreClusterTimingManager.cpp | 2 + vpr/src/timing/VprTimingGraphResolver.cpp | 7 +- vpr/src/timing/VprTimingGraphResolver.h | 3 + vpr/src/timing/read_sdc.cpp | 18 +- vpr/src/timing/read_sdc.h | 3 + vpr/src/timing/timing_graph_builder.cpp | 8 +- vpr/src/timing/timing_graph_builder.h | 5 +- vpr/src/util/vpr_utils.cpp | 36 +- vpr/src/util/vpr_utils.h | 3 - vpr/test/test_interchange_device.cpp | 24 +- vpr/test/test_interchange_netlist.cpp | 7 +- 98 files changed, 2192 insertions(+), 2175 deletions(-) create mode 100644 libs/libarchfpga/src/logic_types.cpp diff --git a/libs/libarchfpga/src/arch_check.cpp b/libs/libarchfpga/src/arch_check.cpp index 5360d6e4c02..75c96aa3cfb 100644 --- a/libs/libarchfpga/src/arch_check.cpp +++ b/libs/libarchfpga/src/arch_check.cpp @@ -1,14 +1,14 @@ #include -#include +#include "logic_types.h" #include "vtr_log.h" #include "arch_error.h" #include "arch_check.h" -bool check_model_clocks(t_model* model, const char* file, uint32_t line) { +bool check_model_clocks(const t_model& model, const char* file, uint32_t line) { //Collect the ports identified as clocks std::set clocks; - for (t_model_ports* ports : {model->inputs, model->outputs}) { + for (t_model_ports* ports : {model.inputs, model.outputs}) { for (t_model_ports* port = ports; port != nullptr; port = port->next) { if (port->is_clock) { clocks.insert(port->name); @@ -17,41 +17,41 @@ bool check_model_clocks(t_model* model, const char* file, uint32_t line) { } //Check that any clock references on the ports are to identified clock ports - for (t_model_ports* ports : {model->inputs, model->outputs}) { + for (t_model_ports* ports : {model.inputs, model.outputs}) { for (t_model_ports* port = ports; port != nullptr; port = port->next) { if (!port->clock.empty() && !clocks.count(port->clock)) { archfpga_throw(file, line, "No matching clock port '%s' on model '%s', required for port '%s'", - port->clock.c_str(), model->name, port->name); + port->clock.c_str(), model.name, port->name); } } } return true; } -bool check_model_combinational_sinks(const t_model* model, const char* file, uint32_t line) { +bool check_model_combinational_sinks(const t_model& model, const char* file, uint32_t line) { //Outputs should have no combinational sinks - for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.outputs; port != nullptr; port = port->next) { if (!port->combinational_sink_ports.empty()) { archfpga_throw(file, line, "Model '%s' output port '%s' can not have combinational sink ports", - model->name, port->name); + model.name, port->name); } } //Record the output ports std::map output_ports; - for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.outputs; port != nullptr; port = port->next) { output_ports.insert({port->name, port}); } - for (t_model_ports* port = model->inputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.inputs; port != nullptr; port = port->next) { for (const std::string& sink_port_name : port->combinational_sink_ports) { //Check that the input port combinational sinks are all outputs if (!output_ports.count(sink_port_name)) { archfpga_throw(file, line, "Model '%s' input port '%s' can not be combinationally connected to '%s' (not an output port of the model)", - model->name, port->name, sink_port_name.c_str()); + model.name, port->name, sink_port_name.c_str()); } //Check that any output combinational sinks are not clocks @@ -61,7 +61,7 @@ bool check_model_combinational_sinks(const t_model* model, const char* file, uin archfpga_throw(file, line, "Model '%s' output port '%s' can not be both: a clock source (is_clock=\"%d\")," " and combinationally connected to input port '%s' (acting as a clock buffer).", - model->name, sink_port->name, sink_port->is_clock, port->name); + model.name, sink_port->name, sink_port->is_clock, port->name); } } } @@ -69,28 +69,28 @@ bool check_model_combinational_sinks(const t_model* model, const char* file, uin return true; } -void warn_model_missing_timing(const t_model* model, const char* file, uint32_t line) { +void warn_model_missing_timing(const t_model& model, const char* file, uint32_t line) { //Check whether there are missing edges and warn the user std::set comb_connected_outputs; - for (t_model_ports* port = model->inputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.inputs; port != nullptr; port = port->next) { if (port->clock.empty() //Not sequential && port->combinational_sink_ports.empty() //Doesn't drive any combinational outputs && !port->is_clock //Not an input clock ) { VTR_LOGF_WARN(file, line, - "Model '%s' input port '%s' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\n", model->name, port->name); + "Model '%s' input port '%s' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\n", model.name, port->name); } comb_connected_outputs.insert(port->combinational_sink_ports.begin(), port->combinational_sink_ports.end()); } - for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.outputs; port != nullptr; port = port->next) { if (port->clock.empty() //Not sequential && !comb_connected_outputs.count(port->name) //Not combinationally driven && !port->is_clock //Not an output clock ) { VTR_LOGF_WARN(file, line, - "Model '%s' output port '%s' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)\n", model->name, port->name); + "Model '%s' output port '%s' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)\n", model.name, port->name); } } } @@ -144,23 +144,13 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar } //Find the matching model - const t_model* model = nullptr; - - for (const t_model* models : {arch.models, arch.model_library}) { - for (model = models; model != nullptr; model = model->next) { - if (std::string(model->name) == blif_model) { - break; - } - } - if (model != nullptr) { - break; - } - } - if (model == nullptr) { + LogicalModelId blif_model_id = arch.models.get_model_by_name(blif_model); + if (!blif_model_id.is_valid()) { archfpga_throw(get_arch_file_name(), -1, "Unable to find model for blif_model '%s' found on pb_type '%s'", blif_model.c_str(), pb_type->name); } + const t_model& model = arch.models.get_model(blif_model_id); //Now that we have the model we can compare the timing annotations @@ -185,7 +175,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar //Find the model port const t_model_ports* model_port = nullptr; - for (const t_model_ports* ports : {model->inputs, model->outputs}) { + for (const t_model_ports* ports : {model.inputs, model.outputs}) { for (const t_model_ports* port = ports; port != nullptr; port = port->next) { if (port->name == annot_port.port_name()) { model_port = port; @@ -206,13 +196,13 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar archfpga_throw(get_arch_file_name(), annot->line_num, " timing-annotation/ mismatch on port '%s' of model '%s', model specifies" " no clock but timing annotation specifies '%s'", - annot_port.port_name().c_str(), model->name, annot_clock.port_name().c_str()); + annot_port.port_name().c_str(), model.name, annot_clock.port_name().c_str()); } if (model_port->clock != annot_clock.port_name()) { archfpga_throw(get_arch_file_name(), annot->line_num, " timing-annotation/ mismatch on port '%s' of model '%s', model specifies" " clock as '%s' but timing annotation specifies '%s'", - annot_port.port_name().c_str(), model->name, model_clock.c_str(), annot_clock.port_name().c_str()); + annot_port.port_name().c_str(), model.name, model_clock.c_str(), annot_clock.port_name().c_str()); } } } @@ -227,7 +217,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar //Find the input model port const t_model_ports* model_port = nullptr; - for (const t_model_ports* port = model->inputs; port != nullptr; port = port->next) { + for (const t_model_ports* port = model.inputs; port != nullptr; port = port->next) { if (port->name == annot_in.port_name()) { model_port = port; break; @@ -248,7 +238,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar archfpga_throw(get_arch_file_name(), annot->line_num, " timing-annotation/ mismatch on port '%s' of model '%s', timing annotation" " specifies combinational connection to port '%s' but the connection does not exist in the model", - model_port->name, model->name, annot_out.port_name().c_str()); + model_port->name, model.name, annot_out.port_name().c_str()); } } } @@ -260,7 +250,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar //Build a list of combinationally connected sinks std::set comb_connected_outputs; - for (t_model_ports* model_ports : {model->inputs, model->outputs}) { + for (t_model_ports* model_ports : {model.inputs, model.outputs}) { for (t_model_ports* model_port = model_ports; model_port != nullptr; model_port = model_port->next) { comb_connected_outputs.insert(model_port->combinational_sink_ports.begin(), model_port->combinational_sink_ports.end()); } @@ -270,7 +260,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar // // This ensures that the pb_type has annotations for all delays/values // required by the model - for (t_model_ports* model_ports : {model->inputs, model->outputs}) { + for (t_model_ports* model_ports : {model.inputs, model.outputs}) { for (t_model_ports* model_port = model_ports; model_port != nullptr; model_port = model_port->next) { //If the model port has no timing specification don't check anything (e.g. architectures with no timing info) if (model_port->clock.empty() @@ -288,10 +278,10 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " port is a sequential input but has neither T_setup nor T_hold specified"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -305,11 +295,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " port is a sequential input with internal combinational connects but has neither"; msg << " min nor max T_clock_to_Q specified"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -325,10 +315,10 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " port is a sequential output but has neither min nor max T_clock_to_Q specified"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -342,11 +332,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " port is a sequential output with internal combinational connections but has"; msg << " neither T_setup nor T_hold specified"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -363,11 +353,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar if (find_combinational_annotation(pb_type, model_port->name, sink_port) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " input port '" << model_port->name << "' has combinational connections to"; msg << " port '" << sink_port.c_str() << "'; specified in model, but no combinational delays found on pb_type"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -383,15 +373,16 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar } void check_models(t_arch* arch) { - for (t_model* model = arch->models; model != nullptr; model = model->next) { - if (model->pb_types == nullptr) { + for (LogicalModelId model_id : arch->models.user_models()) { + const t_model& model = arch->models.get_model(model_id); + if (model.pb_types == nullptr) { archfpga_throw(get_arch_file_name(), 0, - "No pb_type found for model %s\n", model->name); + "No pb_type found for model %s\n", model.name); } int clk_count, input_count, output_count; clk_count = input_count = output_count = 0; - for (auto ports : {model->inputs, model->outputs}) { + for (auto ports : {model.inputs, model.outputs}) { for (auto port = ports; port != nullptr; port = port->next) { int index; switch (port->dir) { @@ -403,7 +394,7 @@ void check_models(t_arch* arch) { break; default: archfpga_throw(get_arch_file_name(), 0, - "Port %s of model %s, has an unrecognized type %s\n", port->name, model->name); + "Port %s of model %s, has an unrecognized type %s\n", port->name, model.name); } port->index = index; diff --git a/libs/libarchfpga/src/arch_check.h b/libs/libarchfpga/src/arch_check.h index 20b3ad30d4b..b057cbde347 100644 --- a/libs/libarchfpga/src/arch_check.h +++ b/libs/libarchfpga/src/arch_check.h @@ -26,7 +26,7 @@ extern "C" { * @param file architecture file * @param line line in the architecture file that generates the failure */ -bool check_model_clocks(t_model* model, const char* file, uint32_t line); +bool check_model_clocks(const t_model& model, const char* file, uint32_t line); /** * @brief Checks the correctness of the combinational sinks in the model inputs to outputs connections @@ -35,7 +35,7 @@ bool check_model_clocks(t_model* model, const char* file, uint32_t line); * @param file architecture file * @param line line in the architecture file that generates the failure */ -bool check_model_combinational_sinks(const t_model* model, const char* file, uint32_t line); +bool check_model_combinational_sinks(const t_model& model, const char* file, uint32_t line); /** * @brief Checks whether the I/O ports can have timing specifications based on their connectivity. @@ -47,7 +47,7 @@ bool check_model_combinational_sinks(const t_model* model, const char* file, uin * @param file architecture file * @param line line in the architecture file that generates the failure */ -void warn_model_missing_timing(const t_model* model, const char* file, uint32_t line); +void warn_model_missing_timing(const t_model& model, const char* file, uint32_t line); /** * @brief Checks the consistency of the mappings between a logical block and the corresponding physical tile. diff --git a/libs/libarchfpga/src/arch_types.h b/libs/libarchfpga/src/arch_types.h index 69ac28ae479..8ea9c44b67f 100644 --- a/libs/libarchfpga/src/arch_types.h +++ b/libs/libarchfpga/src/arch_types.h @@ -18,18 +18,9 @@ /* Value for UNDEFINED data */ constexpr int UNDEFINED = -1; -/** The total number of predefined blif models */ -constexpr int NUM_MODELS_IN_LIBRARY = 4; - /* Maximum value for minimum channel width to avoid overflows of short data type. */ constexpr int MAX_CHANNEL_WIDTH = 8000; -/* Built-in library models */ -constexpr const char* MODEL_NAMES = ".names"; -constexpr const char* MODEL_LATCH = ".latch"; -constexpr const char* MODEL_INPUT = ".input"; -constexpr const char* MODEL_OUTPUT = ".output"; - enum class e_arch_format { VTR, /// #include +#include +#include "logic_types.h" #include "vtr_assert.h" +#include "vtr_list.h" #include "vtr_memory.h" #include "vtr_util.h" @@ -10,7 +13,6 @@ #include "arch_error.h" #include "read_xml_arch_file.h" -#include "read_xml_util.h" /******************** Subroutine declarations ********************************/ @@ -152,7 +154,7 @@ void free_arch(t_arch* arch) { return; } - free_arch_models(arch->models); + arch->models.clear_models(); vtr::release_memory(arch->switches); @@ -160,36 +162,6 @@ void free_arch(t_arch* arch) { vtr::free(arch->architecture_id); - if (arch->model_library) { - for (int i = 0; i < 4; ++i) { - vtr::t_linked_vptr* vptr = arch->model_library[i].pb_types; - while (vptr) { - vtr::t_linked_vptr* vptr_prev = vptr; - vptr = vptr->next; - vtr::free(vptr_prev); - } - } - - vtr::free(arch->model_library[0].name); - vtr::free(arch->model_library[0].outputs->name); - delete[] arch->model_library[0].outputs; - vtr::free(arch->model_library[1].inputs->name); - delete[] arch->model_library[1].inputs; - vtr::free(arch->model_library[1].name); - vtr::free(arch->model_library[2].name); - vtr::free(arch->model_library[2].inputs[0].name); - vtr::free(arch->model_library[2].inputs[1].name); - delete[] arch->model_library[2].inputs; - vtr::free(arch->model_library[2].outputs->name); - delete[] arch->model_library[2].outputs; - vtr::free(arch->model_library[3].name); - vtr::free(arch->model_library[3].inputs->name); - delete[] arch->model_library[3].inputs; - vtr::free(arch->model_library[3].outputs->name); - delete[] arch->model_library[3].outputs; - delete[] arch->model_library; - } - if (arch->clocks) { vtr::free(arch->clocks->clock_inf); } @@ -197,58 +169,6 @@ void free_arch(t_arch* arch) { delete (arch->noc); } -//Frees all models in the linked list -void free_arch_models(t_model* models) { - t_model* model = models; - while (model) { - model = free_arch_model(model); - } -} - -//Frees the specified model, and returns the next model (if any) in the linked list -t_model* free_arch_model(t_model* model) { - if (!model) return nullptr; - - t_model* next_model = model->next; - - free_arch_model_ports(model->inputs); - free_arch_model_ports(model->outputs); - - vtr::t_linked_vptr* vptr = model->pb_types; - while (vptr) { - vtr::t_linked_vptr* vptr_prev = vptr; - vptr = vptr->next; - vtr::free(vptr_prev); - } - - if (model->instances) - vtr::free(model->instances); - vtr::free(model->name); - delete model; - - return next_model; -} - -//Frees all the model ports in a linked list -void free_arch_model_ports(t_model_ports* model_ports) { - t_model_ports* model_port = model_ports; - while (model_port) { - model_port = free_arch_model_port(model_port); - } -} - -//Frees the specified model_port, and returns the next model_port (if any) in the linked list -t_model_ports* free_arch_model_port(t_model_ports* model_port) { - if (!model_port) return nullptr; - - t_model_ports* next_port = model_port->next; - - vtr::free(model_port->name); - delete model_port; - - return next_port; -} - void free_type_descriptors(std::vector& type_descriptors) { for (t_physical_tile_type& type : type_descriptors) { vtr::release_memory(type.name); @@ -565,7 +485,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->blif_model = vtr::strdup(pb_type->blif_model); copy->class_type = pb_type->class_type; copy->depth = pb_type->depth; - copy->model = pb_type->model; + copy->model_id = pb_type->model_id; copy->modes = nullptr; copy->num_modes = 0; copy->num_clock_pins = pb_type->num_clock_pins; @@ -799,7 +719,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { free(lut_pb_type->blif_model); lut_pb_type->blif_model = nullptr; - lut_pb_type->model = nullptr; + lut_pb_type->model_id = LogicalModelId::INVALID(); } /* populate special memory class */ @@ -848,7 +768,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { free(mem_pb_type->blif_model); mem_pb_type->blif_model = nullptr; - mem_pb_type->model = nullptr; + mem_pb_type->model_id = LogicalModelId::INVALID(); mem_pb_type->modes[0].num_interconnect = mem_pb_type->num_ports * num_pb; mem_pb_type->modes[0].interconnect = new t_interconnect[mem_pb_type->modes[0].num_interconnect]; @@ -989,105 +909,6 @@ e_power_estimation_method power_method_inherited(e_power_estimation_method paren } } -void CreateModelLibrary(t_arch* arch) { - t_model* model_library; - - model_library = new t_model[4]; - - //INPAD - model_library[0].name = vtr::strdup(MODEL_INPUT); - model_library[0].index = 0; - model_library[0].inputs = nullptr; - model_library[0].instances = nullptr; - model_library[0].next = &model_library[1]; - model_library[0].outputs = new t_model_ports[1]; - model_library[0].outputs->dir = OUT_PORT; - model_library[0].outputs->name = vtr::strdup("inpad"); - model_library[0].outputs->next = nullptr; - model_library[0].outputs->size = 1; - model_library[0].outputs->min_size = 1; - model_library[0].outputs->index = 0; - model_library[0].outputs->is_clock = false; - - //OUTPAD - model_library[1].name = vtr::strdup(MODEL_OUTPUT); - model_library[1].index = 1; - model_library[1].inputs = new t_model_ports[1]; - model_library[1].inputs->dir = IN_PORT; - model_library[1].inputs->name = vtr::strdup("outpad"); - model_library[1].inputs->next = nullptr; - model_library[1].inputs->size = 1; - model_library[1].inputs->min_size = 1; - model_library[1].inputs->index = 0; - model_library[1].inputs->is_clock = false; - model_library[1].instances = nullptr; - model_library[1].next = &model_library[2]; - model_library[1].outputs = nullptr; - - //LATCH - model_library[2].name = vtr::strdup(MODEL_LATCH); - model_library[2].index = 2; - model_library[2].inputs = new t_model_ports[2]; - - model_library[2].inputs[0].dir = IN_PORT; - model_library[2].inputs[0].name = vtr::strdup("D"); - model_library[2].inputs[0].next = &model_library[2].inputs[1]; - model_library[2].inputs[0].size = 1; - model_library[2].inputs[0].min_size = 1; - model_library[2].inputs[0].index = 0; - model_library[2].inputs[0].is_clock = false; - model_library[2].inputs[0].clock = "clk"; - - model_library[2].inputs[1].dir = IN_PORT; - model_library[2].inputs[1].name = vtr::strdup("clk"); - model_library[2].inputs[1].next = nullptr; - model_library[2].inputs[1].size = 1; - model_library[2].inputs[1].min_size = 1; - model_library[2].inputs[1].index = 0; - model_library[2].inputs[1].is_clock = true; - - model_library[2].instances = nullptr; - model_library[2].next = &model_library[3]; - - model_library[2].outputs = new t_model_ports[1]; - model_library[2].outputs[0].dir = OUT_PORT; - model_library[2].outputs[0].name = vtr::strdup("Q"); - model_library[2].outputs[0].next = nullptr; - model_library[2].outputs[0].size = 1; - model_library[2].outputs[0].min_size = 1; - model_library[2].outputs[0].index = 0; - model_library[2].outputs[0].is_clock = false; - model_library[2].outputs[0].clock = "clk"; - - //NAMES - model_library[3].name = vtr::strdup(MODEL_NAMES); - model_library[3].index = 3; - - model_library[3].inputs = new t_model_ports[1]; - model_library[3].inputs[0].dir = IN_PORT; - model_library[3].inputs[0].name = vtr::strdup("in"); - model_library[3].inputs[0].next = nullptr; - model_library[3].inputs[0].size = 1; - model_library[3].inputs[0].min_size = 1; - model_library[3].inputs[0].index = 0; - model_library[3].inputs[0].is_clock = false; - model_library[3].inputs[0].combinational_sink_ports = {"out"}; - - model_library[3].instances = nullptr; - model_library[3].next = nullptr; - - model_library[3].outputs = new t_model_ports[1]; - model_library[3].outputs[0].dir = OUT_PORT; - model_library[3].outputs[0].name = vtr::strdup("out"); - model_library[3].outputs[0].next = nullptr; - model_library[3].outputs[0].size = 1; - model_library[3].outputs[0].min_size = 1; - model_library[3].outputs[0].index = 0; - model_library[3].outputs[0].is_clock = false; - - arch->model_library = model_library; -} - void SyncModelsPbTypes(t_arch* arch, const std::vector& Types) { for (auto& Type : Types) { @@ -1099,16 +920,10 @@ void SyncModelsPbTypes(t_arch* arch, void SyncModelsPbTypes_rec(t_arch* arch, t_pb_type* pb_type) { - t_model *model_match_prim, *cur_model; - t_model_ports* model_port; - vtr::t_linked_vptr* old; - char* blif_model_name = nullptr; - - bool found; if (pb_type->blif_model != nullptr) { /* get actual name of subckt */ - blif_model_name = pb_type->blif_model; + char* blif_model_name = pb_type->blif_model; if (strstr(blif_model_name, ".subckt ") == blif_model_name) { blif_model_name = strchr(blif_model_name, ' '); ++blif_model_name; //Advance past space @@ -1119,39 +934,24 @@ void SyncModelsPbTypes_rec(t_arch* arch, pb_type->blif_model, pb_type->name); } - /* There are two sets of models to consider, the standard library of models and the user defined models */ - if (is_library_model(blif_model_name)) { - cur_model = arch->model_library; - } else { - cur_model = arch->models; - } - /* Determine the logical model to use */ - found = false; - model_match_prim = nullptr; - while (cur_model && !found) { - /* blif model always starts with .subckt so need to skip first 8 characters */ - if (strcmp(blif_model_name, cur_model->name) == 0) { - found = true; - model_match_prim = cur_model; - } - cur_model = cur_model->next; - } - if (!found) { + LogicalModelId model_match_prim_id = arch->models.get_model_by_name(blif_model_name); + if (!model_match_prim_id.is_valid()) { archfpga_throw(get_arch_file_name(), 0, "No matching model for pb_type %s\n", pb_type->blif_model); } + t_model& model_match_prim = arch->models.get_model(model_match_prim_id); - pb_type->model = model_match_prim; - old = model_match_prim->pb_types; - model_match_prim->pb_types = (vtr::t_linked_vptr*)vtr::malloc(sizeof(vtr::t_linked_vptr)); - model_match_prim->pb_types->next = old; - model_match_prim->pb_types->data_vptr = pb_type; + pb_type->model_id = model_match_prim_id; + vtr::t_linked_vptr* old = model_match_prim.pb_types; + model_match_prim.pb_types = (vtr::t_linked_vptr*)vtr::malloc(sizeof(vtr::t_linked_vptr)); + model_match_prim.pb_types->next = old; + model_match_prim.pb_types->data_vptr = pb_type; for (int p = 0; p < pb_type->num_ports; p++) { - found = false; + bool found = false; /* TODO: Parse error checking - check if INPUT matches INPUT and OUTPUT matches OUTPUT (not yet done) */ - model_port = model_match_prim->inputs; + t_model_ports* model_port = model_match_prim.inputs; while (model_port && !found) { if (strcmp(model_port->name, pb_type->ports[p].name) == 0) { if (model_port->size < pb_type->ports[p].num_pins) { @@ -1176,7 +976,7 @@ void SyncModelsPbTypes_rec(t_arch* arch, } model_port = model_port->next; } - model_port = model_match_prim->outputs; + model_port = model_match_prim.outputs; while (model_port && !found) { if (strcmp(model_port->name, pb_type->ports[p].name) == 0) { if (model_port->size < pb_type->ports[p].num_pins) { @@ -1260,20 +1060,6 @@ bool segment_exists(const t_arch* arch, std::string_view name) { return find_segment(arch, name) != nullptr; } -bool is_library_model(const char* model_name) { - if (model_name == std::string(MODEL_NAMES) - || model_name == std::string(MODEL_LATCH) - || model_name == std::string(MODEL_INPUT) - || model_name == std::string(MODEL_OUTPUT)) { - return true; - } - return false; -} - -bool is_library_model(const t_model* model) { - return is_library_model(model->name); -} - //Returns true if the specified block type contains the specified blif model name // // TODO: Remove block_type_contains_blif_model / pb_type_contains_blif_model diff --git a/libs/libarchfpga/src/arch_util.h b/libs/libarchfpga/src/arch_util.h index fb251bffe10..fb87262878c 100644 --- a/libs/libarchfpga/src/arch_util.h +++ b/libs/libarchfpga/src/arch_util.h @@ -52,10 +52,6 @@ class InstPort { }; void free_arch(t_arch* arch); -void free_arch_models(t_model* models); -t_model* free_arch_model(t_model* model); -void free_arch_model_ports(t_model_ports* model_ports); -t_model_ports* free_arch_model_port(t_model_ports* model_port); void free_type_descriptors(std::vector& type_descriptors); void free_type_descriptors(std::vector& type_descriptors); @@ -84,8 +80,6 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type); e_power_estimation_method power_method_inherited(e_power_estimation_method parent_power_method); -void CreateModelLibrary(t_arch* arch); - void SyncModelsPbTypes(t_arch* arch, const std::vector& Types); @@ -97,8 +91,6 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, bool segment_exists(const t_arch* arch, std::string_view name); const t_segment_inf* find_segment(const t_arch* arch, std::string_view name); -bool is_library_model(const char* model_name); -bool is_library_model(const t_model* model); //Returns true if the specified block type contains the specified blif model name bool block_type_contains_blif_model(t_logical_block_type_ptr type, const std::string& blif_model_name); diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index edceeb748fb..2e08c196946 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -1,24 +1,22 @@ #include #include #include -#include #include "echo_arch.h" -#include "arch_types.h" #include "arch_util.h" +#include "logic_types.h" #include "vtr_list.h" #include "vtr_util.h" #include "vtr_memory.h" #include "vtr_assert.h" -using vtr::t_linked_vptr; - /// @brief indices to lookup IPIN connection block switch name constexpr int ipin_cblock_switch_index_within_die = 0; constexpr int ipin_cblock_switch_index_between_dice = 1; void PrintArchInfo(FILE* Echo, const t_arch* arch); -static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level); +static void print_model(FILE* echo, const t_model& model); +static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models); static void PrintPb_types_recPower(FILE* Echo, const t_pb_type* pb_type, const char* tabs); @@ -29,55 +27,21 @@ void EchoArch(const char* EchoFile, const std::vector& PhysicalTileTypes, const std::vector& LogicalBlockTypes, const t_arch* arch) { - int i, j; - FILE* Echo; - t_model* cur_model; - t_model_ports* model_port; - t_linked_vptr* cur_vptr; - Echo = vtr::fopen(EchoFile, "w"); - cur_model = nullptr; + FILE* Echo = vtr::fopen(EchoFile, "w"); //Print all layout device switch/segment list info first PrintArchInfo(Echo, arch); //Models fprintf(Echo, "*************************************************\n"); - for (j = 0; j < 2; j++) { - if (j == 0) { - fprintf(Echo, "Printing user models \n"); - cur_model = arch->models; - } else if (j == 1) { - fprintf(Echo, "Printing library models \n"); - cur_model = arch->model_library; - } - while (cur_model) { - fprintf(Echo, "Model: \"%s\"\n", cur_model->name); - model_port = cur_model->inputs; - while (model_port) { - fprintf(Echo, "\tInput Ports: \"%s\" \"%d\" min_size=\"%d\"\n", - model_port->name, model_port->size, - model_port->min_size); - model_port = model_port->next; - } - model_port = cur_model->outputs; - while (model_port) { - fprintf(Echo, "\tOutput Ports: \"%s\" \"%d\" min_size=\"%d\"\n", - model_port->name, model_port->size, - model_port->min_size); - model_port = model_port->next; - } - cur_vptr = cur_model->pb_types; - i = 0; - while (cur_vptr != nullptr) { - fprintf(Echo, "\tpb_type %d: \"%s\"\n", i, - ((t_pb_type*)cur_vptr->data_vptr)->name); - cur_vptr = cur_vptr->next; - i++; - } - - cur_model = cur_model->next; - } + fprintf(Echo, "Printing library models \n"); + for (LogicalModelId model_id : arch->models.library_models()) { + print_model(Echo, arch->models.get_model(model_id)); + } + fprintf(Echo, "Printing user models \n"); + for (LogicalModelId model_id : arch->models.user_models()) { + print_model(Echo, arch->models.get_model(model_id)); } fprintf(Echo, "*************************************************\n\n"); fprintf(Echo, "*************************************************\n"); @@ -122,7 +86,7 @@ void EchoArch(const char* EchoFile, for (auto& LogicalBlock : LogicalBlockTypes) { if (LogicalBlock.pb_type) { - PrintPb_types_rec(Echo, LogicalBlock.pb_type, 2); + PrintPb_types_rec(Echo, LogicalBlock.pb_type, 2, arch->models); } fprintf(Echo, "\n"); } @@ -390,7 +354,33 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { fprintf(Echo, "*************************************************\n\n"); } -static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level) { +static void print_model(FILE* echo, const t_model& model) { + fprintf(echo, "Model: \"%s\"\n", model.name); + t_model_ports* input_model_port = model.inputs; + while (input_model_port) { + fprintf(echo, "\tInput Ports: \"%s\" \"%d\" min_size=\"%d\"\n", + input_model_port->name, input_model_port->size, + input_model_port->min_size); + input_model_port = input_model_port->next; + } + t_model_ports* output_model_port = model.outputs; + while (output_model_port) { + fprintf(echo, "\tOutput Ports: \"%s\" \"%d\" min_size=\"%d\"\n", + output_model_port->name, output_model_port->size, + output_model_port->min_size); + output_model_port = output_model_port->next; + } + vtr::t_linked_vptr* cur_vptr = model.pb_types; + int i = 0; + while (cur_vptr != nullptr) { + fprintf(echo, "\tpb_type %d: \"%s\"\n", i, + ((t_pb_type*)cur_vptr->data_vptr)->name); + cur_vptr = cur_vptr->next; + i++; + } +} + +static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models) { char* tabs; tabs = (char*)vtr::malloc((level + 1) * sizeof(char)); @@ -415,7 +405,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level) { fprintf(Echo, "%s\tmode %s:\n", tabs, pb_type->modes[i].name); for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { PrintPb_types_rec(Echo, &pb_type->modes[i].pb_type_children[j], - level + 2); + level + 2, models); } for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) { fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs, @@ -447,9 +437,10 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level) { * I/O has no annotations to be displayed * All other library or user models may have delays specificied, e.g. Tsetup and Tcq * Display the additional information*/ - if (strcmp(pb_type->model->name, MODEL_NAMES) - && strcmp(pb_type->model->name, MODEL_INPUT) - && strcmp(pb_type->model->name, MODEL_OUTPUT)) { + std::string pb_type_model_name = models.get_model(pb_type->model_id).name; + if (pb_type_model_name != LogicalModels::MODEL_NAMES + && pb_type_model_name != LogicalModels::MODEL_INPUT + && pb_type_model_name != LogicalModels::MODEL_OUTPUT) { for (int k = 0; k < pb_type->num_annotations; k++) { fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs, pb_type->annotations[k].clock, diff --git a/libs/libarchfpga/src/logic_types.cpp b/libs/libarchfpga/src/logic_types.cpp new file mode 100644 index 00000000000..dc4801d3347 --- /dev/null +++ b/libs/libarchfpga/src/logic_types.cpp @@ -0,0 +1,171 @@ +/** + * @file + * @author Alex Singer + * @date April 2025 + * @brief Implementation of the LogicalModels data structure. + */ + +#include "logic_types.h" +#include "vtr_assert.h" +#include "vtr_util.h" + +/** + * @brief Frees all the model ports in a linked list + */ +static void free_arch_model_ports(t_model_ports* model_ports); + +/** + * @brief Frees the specified model_port, and returns the next model_port (if + * any) in the linked list + */ +static t_model_ports* free_arch_model_port(t_model_ports* model_port); + +LogicalModels::LogicalModels() { + // Create the logical models. These must be created first and stored at the + // start of the list of models. + VTR_ASSERT_MSG(all_models().size() == 0, + "The first models created must be the library models"); + //INPAD + { + LogicalModelId inpad_model_id = create_logical_model(MODEL_INPUT); + t_model& inpad_model = get_model(inpad_model_id); + + inpad_model.inputs = nullptr; + + inpad_model.instances = nullptr; + + inpad_model.outputs = new t_model_ports; + inpad_model.outputs->dir = OUT_PORT; + inpad_model.outputs->name = vtr::strdup("inpad"); + inpad_model.outputs->next = nullptr; + inpad_model.outputs->size = 1; + inpad_model.outputs->min_size = 1; + inpad_model.outputs->index = 0; + inpad_model.outputs->is_clock = false; + } + + //OUTPAD + { + LogicalModelId outpad_model_id = create_logical_model(MODEL_OUTPUT); + t_model& outpad_model = get_model(outpad_model_id); + + outpad_model.inputs = new t_model_ports; + outpad_model.inputs->dir = IN_PORT; + outpad_model.inputs->name = vtr::strdup("outpad"); + outpad_model.inputs->next = nullptr; + outpad_model.inputs->size = 1; + outpad_model.inputs->min_size = 1; + outpad_model.inputs->index = 0; + outpad_model.inputs->is_clock = false; + + outpad_model.instances = nullptr; + + outpad_model.outputs = nullptr; + } + + //LATCH + { + LogicalModelId latch_model_id = create_logical_model(MODEL_LATCH); + t_model& latch_model = get_model(latch_model_id); + t_model_ports* latch_model_input_port_1 = new t_model_ports; + t_model_ports* latch_model_input_port_2 = new t_model_ports; + + latch_model.inputs = latch_model_input_port_1; + latch_model_input_port_1->dir = IN_PORT; + latch_model_input_port_1->name = vtr::strdup("D"); + latch_model_input_port_1->next = latch_model_input_port_2; + latch_model_input_port_1->size = 1; + latch_model_input_port_1->min_size = 1; + latch_model_input_port_1->index = 0; + latch_model_input_port_1->is_clock = false; + latch_model_input_port_1->clock = "clk"; + + latch_model_input_port_2->dir = IN_PORT; + latch_model_input_port_2->name = vtr::strdup("clk"); + latch_model_input_port_2->next = nullptr; + latch_model_input_port_2->size = 1; + latch_model_input_port_2->min_size = 1; + latch_model_input_port_2->index = 0; + latch_model_input_port_2->is_clock = true; + + latch_model.instances = nullptr; + + latch_model.outputs = new t_model_ports; + latch_model.outputs->dir = OUT_PORT; + latch_model.outputs->name = vtr::strdup("Q"); + latch_model.outputs->next = nullptr; + latch_model.outputs->size = 1; + latch_model.outputs->min_size = 1; + latch_model.outputs->index = 0; + latch_model.outputs->is_clock = false; + latch_model.outputs->clock = "clk"; + } + + //NAMES + { + LogicalModelId names_model_id = create_logical_model(MODEL_NAMES); + t_model& names_model = get_model(names_model_id); + + names_model.inputs = new t_model_ports; + names_model.inputs->dir = IN_PORT; + names_model.inputs->name = vtr::strdup("in"); + names_model.inputs->next = nullptr; + names_model.inputs->size = 1; + names_model.inputs->min_size = 1; + names_model.inputs->index = 0; + names_model.inputs->is_clock = false; + names_model.inputs->combinational_sink_ports = {"out"}; + + names_model.instances = nullptr; + + names_model.outputs = new t_model_ports; + names_model.outputs->dir = OUT_PORT; + names_model.outputs->name = vtr::strdup("out"); + names_model.outputs->next = nullptr; + names_model.outputs->size = 1; + names_model.outputs->min_size = 1; + names_model.outputs->index = 0; + names_model.outputs->is_clock = false; + } + + // Checks to ensure that all library models have been successfully created + // and the number of library models matches the NUM_MODELS_IN_LIBRARY variable. + VTR_ASSERT_MSG(all_models().size() == library_models().size(), + "The only models that have been created should be the library models"); + VTR_ASSERT_MSG(library_models().size() == NUM_MODELS_IN_LIBRARY, + "The number of models in the library must be the expected number"); +} + +void LogicalModels::free_model_data(t_model& model) { + free_arch_model_ports(model.inputs); + free_arch_model_ports(model.outputs); + + vtr::t_linked_vptr* vptr = model.pb_types; + while (vptr) { + vtr::t_linked_vptr* vptr_prev = vptr; + vptr = vptr->next; + vtr::free(vptr_prev); + } + + if (model.instances) + vtr::free(model.instances); + vtr::free(model.name); +} + +static void free_arch_model_ports(t_model_ports* model_ports) { + t_model_ports* model_port = model_ports; + while (model_port) { + model_port = free_arch_model_port(model_port); + } +} + +static t_model_ports* free_arch_model_port(t_model_ports* model_port) { + if (!model_port) return nullptr; + + t_model_ports* next_port = model_port->next; + + vtr::free(model_port->name); + delete model_port; + + return next_port; +} diff --git a/libs/libarchfpga/src/logic_types.h b/libs/libarchfpga/src/logic_types.h index 4427b85016f..0a23b23d8e9 100644 --- a/libs/libarchfpga/src/logic_types.h +++ b/libs/libarchfpga/src/logic_types.h @@ -5,12 +5,22 @@ * * Date: February 19, 2009 * Authors: Jason Luu and Kenneth Kent + * + * Updated with the LogicalModels data structure by Alex Singer + * Date: April, 2025 */ #ifndef LOGIC_TYPES_H #define LOGIC_TYPES_H +#include "vtr_assert.h" #include "vtr_list.h" +#include "vtr_memory.h" +#include "vtr_range.h" +#include "vtr_strong_id.h" +#include "vtr_util.h" +#include "vtr_vector_map.h" +#include #include #include @@ -40,18 +50,223 @@ struct t_model_ports { int index = -1; /* indexing for array look-up */ }; +/** + * @brief Struct containing the information stored for a logical model in the + * LogicalModels storage class below. + */ struct t_model { - char* name = nullptr; /* name of this logic model */ - t_model_ports* inputs = nullptr; /* linked list of input/clock ports */ - t_model_ports* outputs = nullptr; /* linked list of output ports */ - void* instances = nullptr; - int used = 0; - vtr::t_linked_vptr* pb_types = nullptr; /* Physical block types that implement this model */ - t_model* next = nullptr; /* next model (linked list) */ + char* name = nullptr; ///< name of this logic model + t_model_ports* inputs = nullptr; ///< linked list of input/clock ports + t_model_ports* outputs = nullptr; ///< linked list of output ports + void* instances = nullptr; ///< TODO: Remove this. This is only used in the Parmys plugin and should be moved into there. + int used = 0; ///< TODO: Remove this. This is only used in the Parmys plugin and should be moved into there. + vtr::t_linked_vptr* pb_types = nullptr; ///< Physical block types that implement this model + bool never_prune = false; ///< Don't remove from the netlist even if a block of this type has no output ports used and, therefore, unconnected to the rest of the netlist +}; + +// Tag for the logical model ID +struct logical_model_id_tag; +// A unique ID that represents a logical model in the architecture. +typedef vtr::StrongId LogicalModelId; + +/** + * @brief A storage class containing all of the logical models in an FPGA + * architecture. + * + * This class manages creating, storing, and destroying logical models. It also + * contains helper methods to parse the logical models. + * + * A logical model is the definition of a type of primitive block that can occur + * in the atom netlist for a given FPGA architecture; it stores data that all + * block instances of that type share. + * + * There are two types of logical models: + * 1) Library Models: These are models that all architectures share. These are + * created in the construtor of this class. + * 2) User Models: These are models defined by the user and are created outside + * of this class (usually by parsing an architecture file). + */ +class LogicalModels { + public: + // The total number of predefined blif models. + static constexpr size_t NUM_MODELS_IN_LIBRARY = 4; + + // Built-in library model names. + static constexpr const char* MODEL_NAMES = ".names"; + static constexpr const char* MODEL_LATCH = ".latch"; + static constexpr const char* MODEL_INPUT = ".input"; + static constexpr const char* MODEL_OUTPUT = ".output"; + + // Iterator for the logical model IDs array. + typedef typename vtr::vector_map::const_iterator model_iterator; + + // A range of model IDs within the logical model IDs array. + typedef typename vtr::Range model_range; + + public: + // Since this class maintaines pointers and these pointers are freed upon + // destruction, this class cannot (and should not) be copied. + LogicalModels(const LogicalModels&) = delete; + LogicalModels& operator=(const LogicalModels&) = delete; + + /** + * @brief The constructor of the LogicalModels class. + * + * This populates the library models. + */ + LogicalModels(); + + ~LogicalModels() { + // Free the data of all models. + clear_models(); + } + + /** + * @brief Returns a range of logical model IDs representing all models in + * the architecture (both library and user models). + */ + inline model_range all_models() const { + return vtr::make_range(logical_model_ids_.begin(), logical_model_ids_.end()); + } + + /** + * @brief Returns a range of logical model IDs representing all library + * models in the architecture. + */ + inline model_range library_models() const { + VTR_ASSERT_SAFE_MSG(logical_model_ids_.size() >= NUM_MODELS_IN_LIBRARY, + "Library models missing"); + // The library models are created in the constructor, thus they must be + // the first L models in the IDs (where L is the number of library models). + return vtr::make_range(logical_model_ids_.begin(), + logical_model_ids_.begin() + NUM_MODELS_IN_LIBRARY); + } + + /** + * @brief Returns a range of logical model IDs representing all user models + * in the architecture. + */ + inline model_range user_models() const { + VTR_ASSERT_SAFE_MSG(logical_model_ids_.size() >= NUM_MODELS_IN_LIBRARY, + "Library models missing"); + + // The user models will always be located after the library models since + // the library models were added in the constructor. + return vtr::make_range(logical_model_ids_.begin() + NUM_MODELS_IN_LIBRARY, + logical_model_ids_.end()); + } + + /** + * @brief Returns true if the given model ID represents a library model. + */ + inline bool is_library_model(LogicalModelId model_id) const { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Invalid model ID"); + // The first L model IDs must be the library models. Where L is the + // number of models in the library + if ((size_t)model_id < NUM_MODELS_IN_LIBRARY) + return true; + + return false; + } + + /** + * @brief Create a logical model with the given name. + * + * This method will construct a t_model object with the given name. This + * object can be accessed and modified using the get_model method. + * + * @return The ID of the newly created model. + */ + inline LogicalModelId create_logical_model(const std::string& model_name) { + VTR_ASSERT_MSG(model_name_to_logical_model_id_.count(model_name) == 0, + "A model with the given name already exists"); + // Create the new model. + t_model new_model; + new_model.name = vtr::strdup(model_name.c_str()); + + // Create the new model's ID + LogicalModelId new_model_id = LogicalModelId(logical_model_ids_.size()); + + // Update the internal state. + logical_models_.push_back(std::move(new_model)); + logical_model_ids_.push_back(new_model_id); + model_name_to_logical_model_id_[model_name] = new_model_id; + + return new_model_id; + } + + /** + * @brief Immutable accessor to the underlying model data structure for the + * given model ID. + */ + inline const t_model& get_model(LogicalModelId model_id) const { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Cannot get model of invalid model ID"); + return logical_models_[model_id]; + } + + /** + * @brief Mutable accessor to the underlying model data structure for the + * given model ID. + */ + inline t_model& get_model(LogicalModelId model_id) { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Cannot get model of invalid model ID"); + return logical_models_[model_id]; + } + + /** + * @brief Returns the name of the given model. + */ + inline std::string model_name(LogicalModelId model_id) const { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Cannot get name of invalid model ID"); + return logical_models_[model_id].name; + } + + /** + * @brief Returns the ID of the model with the given name. If no model has + * the given name, the invalid model ID will be returned. + * + * This method has O(1) time complexity. + */ + inline LogicalModelId get_model_by_name(std::string model_name) const { + auto itr = model_name_to_logical_model_id_.find(model_name); + if (itr == model_name_to_logical_model_id_.end()) + return LogicalModelId::INVALID(); + return itr->second; + } + + /** + * @brief Destroys all of the models. This frees all internal model data. + */ + void clear_models() { + // Free the model data of all models. + for (LogicalModelId model_id : all_models()) { + free_model_data(logical_models_[model_id]); + } + // Clear all data structures. + logical_model_ids_.clear(); + logical_models_.clear(); + model_name_to_logical_model_id_.clear(); + } + + private: + /** + * @brief Helper method for freeing the internal data of the given model. + */ + void free_model_data(t_model& model); + + private: + /// @brief A list of all logical model IDs. + vtr::vector_map logical_model_ids_; - bool never_prune = false; /* Don't remove from the netlist even if a block of this type has no output ports used and, therefore, unconnected to the rest of the netlist */ + /// @brief A list of a logical models. + vtr::vector_map logical_models_; - int index = -1; + /// @brief A lookup between the name of a logical model and its ID. + std::unordered_map model_name_to_logical_model_id_; }; #endif diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index b3550e83d01..ace0f5be509 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1042,7 +1042,7 @@ struct t_pb_type { char* name = nullptr; int num_pb = 0; char* blif_model = nullptr; - t_model* model = nullptr; + LogicalModelId model_id; enum e_pb_type_class class_type = UNKNOWN_CLASS; t_mode* modes = nullptr; /* [0..num_modes-1] */ @@ -2180,8 +2180,7 @@ struct t_arch { /// Contains information about all direct chain connections in the architecture std::vector directs; - t_model* models = nullptr; - t_model* model_library = nullptr; + LogicalModels models; t_power_arch* power = nullptr; t_clock_arch* clocks = nullptr; diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 50840cbb948..265991c23f2 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -1,7 +1,7 @@ #include "read_fpga_interchange_arch.h" -#include "vtr_error.h" +#include "logic_types.h" #ifdef VTR_ENABLE_CAPNPROTO @@ -19,14 +19,12 @@ #include "vtr_assert.h" #include "vtr_digest.h" -#include "vtr_log.h" #include "vtr_memory.h" #include "vtr_util.h" #include "arch_check.h" #include "arch_error.h" #include "arch_util.h" -#include "arch_types.h" /* * FPGA Interchange Device frontend @@ -161,32 +159,28 @@ static float get_corner_value(Device::CornerModel::Reader model, const char* spe } /** @brief Returns the port corresponding to the given model in the architecture */ -static t_model_ports* get_model_port(t_arch* arch, std::string model, std::string port, bool fail = true) { - for (t_model* m : {arch->models, arch->model_library}) { - for (; m != nullptr; m = m->next) { - if (std::string(m->name) != model) - continue; - - for (t_model_ports* p : {m->inputs, m->outputs}) - for (; p != nullptr; p = p->next) - if (std::string(p->name) == port) - return p; - } +static t_model_ports* get_model_port(t_arch* arch, std::string model_name, std::string port, bool fail = true) { + LogicalModelId model_id = arch->models.get_model_by_name(model_name); + if (model_id.is_valid()) { + const t_model& model = arch->models.get_model(model_id); + for (t_model_ports* p : {model.inputs, model.outputs}) + for (; p != nullptr; p = p->next) + if (std::string(p->name) == port) + return p; } if (fail) archfpga_throw(__FILE__, __LINE__, - "Could not find model port: %s (%s)\n", port.c_str(), model.c_str()); + "Could not find model port: %s (%s)\n", port.c_str(), model_name.c_str()); return nullptr; } /** @brief Returns the specified architecture model */ -static t_model* get_model(t_arch* arch, std::string model) { - for (t_model* m : {arch->models, arch->model_library}) - for (; m != nullptr; m = m->next) - if (std::string(m->name) == model) - return m; +static LogicalModelId get_model(t_arch* arch, std::string model) { + LogicalModelId model_id = arch->models.get_model_by_name(model); + if (model_id.is_valid()) + return model_id; archfpga_throw(__FILE__, __LINE__, "Could not find model: %s\n", model.c_str()); @@ -914,16 +908,9 @@ struct ArchReader { // Model processing void process_models() { - // Populate the common library, namely .inputs, .outputs, .names, .latches - CreateModelLibrary(arch_); - - t_model* temp = nullptr; std::map model_name_map; std::pair::iterator, bool> ret_map_name; - int model_index = NUM_MODELS_IN_LIBRARY; - arch_->models = nullptr; - auto primLib = ar_.getPrimLibs(); for (auto primitive : primLib.getCellDecls()) { if (str(primitive.getLib()) == std::string("primitives")) { @@ -951,38 +938,31 @@ struct ArchReader { continue; try { - temp = new t_model; - temp->index = model_index++; - - temp->never_prune = true; - temp->name = vtr::strdup(prim_name.c_str()); - - ret_map_name = model_name_map.insert(std::pair(temp->name, 0)); + ret_map_name = model_name_map.insert(std::pair(prim_name, 0)); if (!ret_map_name.second) { archfpga_throw(arch_file_, __LINE__, - "Duplicate model name: '%s'.\n", temp->name); + "Duplicate model name: '%s'.\n", prim_name.c_str()); } - if (!process_model_ports(temp, primitive)) { - free_arch_model(temp); + LogicalModelId new_model_id = arch_->models.create_logical_model(prim_name); + t_model& new_model = arch_->models.get_model(new_model_id); + new_model.never_prune = true; + + if (!process_model_ports(new_model, primitive)) { continue; } - check_model_clocks(temp, arch_file_, __LINE__); - check_model_combinational_sinks(temp, arch_file_, __LINE__); - warn_model_missing_timing(temp, arch_file_, __LINE__); - + check_model_clocks(new_model, arch_file_, __LINE__); + check_model_combinational_sinks(new_model, arch_file_, __LINE__); + warn_model_missing_timing(new_model, arch_file_, __LINE__); } catch (ArchFpgaError& e) { - free_arch_model(temp); throw; } - temp->next = arch_->models; - arch_->models = temp; } } } - bool process_model_ports(t_model* model, Netlist::CellDeclaration::Reader primitive) { + bool process_model_ports(t_model& model, Netlist::CellDeclaration::Reader primitive) { auto primLib = ar_.getPrimLibs(); auto portList = primLib.getPortList(); @@ -1040,12 +1020,12 @@ struct ArchReader { port_names.insert(std::pair(model_port->name, dir)); //Add the port if (dir == IN_PORT) { - model_port->next = model->inputs; - model->inputs = model_port; + model_port->next = model.inputs; + model.inputs = model_port; } else if (dir == OUT_PORT) { - model_port->next = model->outputs; - model->outputs = model_port; + model_port->next = model.outputs; + model.outputs = model_port; } } @@ -1309,13 +1289,13 @@ struct ArchReader { lut->num_pb = 1; lut->parent_mode = mode; - lut->blif_model = vtr::strdup(MODEL_NAMES); - lut->model = get_model(arch_, std::string(MODEL_NAMES)); + lut->blif_model = vtr::strdup(LogicalModels::MODEL_NAMES); + lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES); lut->num_ports = 2; lut->ports = (t_port*)vtr::calloc(lut->num_ports, sizeof(t_port)); - lut->ports[0] = get_generic_port(arch_, lut, IN_PORT, "in", MODEL_NAMES, width); - lut->ports[1] = get_generic_port(arch_, lut, OUT_PORT, "out", MODEL_NAMES); + lut->ports[0] = get_generic_port(arch_, lut, IN_PORT, "in", LogicalModels::MODEL_NAMES, width); + lut->ports[1] = get_generic_port(arch_, lut, OUT_PORT, "out", LogicalModels::MODEL_NAMES); lut->ports[0].equivalent = PortEquivalence::FULL; @@ -1416,10 +1396,10 @@ struct ArchReader { num_ports = 1; opad->num_ports = num_ports; opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); - opad->blif_model = vtr::strdup(MODEL_OUTPUT); - opad->model = get_model(arch_, std::string(MODEL_OUTPUT)); + opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT); + opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT); - opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", MODEL_OUTPUT); + opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", LogicalModels::MODEL_OUTPUT); omode->pb_type_children[0] = *opad; // IPAD mode @@ -1438,10 +1418,10 @@ struct ArchReader { num_ports = 1; ipad->num_ports = num_ports; ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); - ipad->blif_model = vtr::strdup(MODEL_INPUT); - ipad->model = get_model(arch_, std::string(MODEL_INPUT)); + ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT); + ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT); - ipad->ports[0] = get_generic_port(arch_, ipad, OUT_PORT, "inpad", MODEL_INPUT); + ipad->ports[0] = get_generic_port(arch_, ipad, OUT_PORT, "inpad", LogicalModels::MODEL_INPUT); imode->pb_type_children[0] = *ipad; // Handle interconnects @@ -1566,7 +1546,7 @@ struct ArchReader { leaf->num_ports = num_ports; leaf->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); leaf->blif_model = vtr::strdup((std::string(".subckt ") + name).c_str()); - leaf->model = get_model(arch_, name); + leaf->model_id = get_model(arch_, name); mode->num_interconnect = num_ports; mode->interconnect = new t_interconnect[num_ports]; @@ -2140,7 +2120,7 @@ struct ArchReader { leaf_pb_type->num_ports = num_ports; leaf_pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); leaf_pb_type->blif_model = vtr::strdup(const_cell.first.c_str()); - leaf_pb_type->model = get_model(arch_, const_cell.first); + leaf_pb_type->model_id = get_model(arch_, const_cell.first); leaf_pb_type->ports[0] = get_generic_port(arch_, leaf_pb_type, OUT_PORT, const_cell.second, const_cell.first); pb_type->ports[count] = get_generic_port(arch_, leaf_pb_type, OUT_PORT, const_cell.first + "_" + const_cell.second); @@ -2170,11 +2150,10 @@ struct ArchReader { // Create constant models for (auto const_cell : const_cells) { - t_model* model = new t_model; - model->index = arch_->models->index + 1; + LogicalModelId new_model_id = arch_->models.create_logical_model(const_cell.first); + t_model& new_model = arch_->models.get_model(new_model_id); - model->never_prune = true; - model->name = vtr::strdup(const_cell.first.c_str()); + new_model.never_prune = true; t_model_ports* model_port = new t_model_ports; model_port->dir = OUT_PORT; @@ -2182,11 +2161,8 @@ struct ArchReader { model_port->min_size = 1; model_port->size = 1; - model_port->next = model->outputs; - model->outputs = model_port; - - model->next = arch_->models; - arch_->models = model; + model_port->next = new_model.outputs; + new_model.outputs = model_port; } } diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 5ac6acf6b9a..9d54b9e2a41 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -43,6 +43,7 @@ #include #include +#include "logic_types.h" #include "pugixml.hpp" #include "pugixml_util.hpp" @@ -295,7 +296,7 @@ static void ProcessChanWidthDistr(pugi::xml_node Node, const pugiutil::loc_data& loc_data); static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pugiutil::loc_data& loc_data); static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data); -static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::set& port_names, const pugiutil::loc_data& loc_data); +static void ProcessModelPorts(pugi::xml_node port_group, t_model& model, std::set& port_names, const pugiutil::loc_data& loc_data); static void ProcessLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data, int& num_of_avail_layer); static t_grid_def ProcessGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); static void ProcessBlockTypeLocs(t_grid_def& grid_def, int die_number, vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data); @@ -434,7 +435,6 @@ void XmlReadArch(const char* ArchFile, /* Process models */ Next = get_single_child(architecture, "models", loc_data); ProcessModels(Next, arch, loc_data); - CreateModelLibrary(arch); /* Process layout */ int num_of_avail_layers = 0; @@ -2245,15 +2245,9 @@ static void ProcessSwitchblockLocations(pugi::xml_node switchblock_locations, * child type objects. */ static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data) { pugi::xml_node p; - t_model* temp = nullptr; - int L_index; /* std::maps for checking duplicates */ std::map model_name_map; - std::pair::iterator, bool> ret_map_name; - L_index = NUM_MODELS_IN_LIBRARY; - - arch->models = nullptr; for (pugi::xml_node model : Node.children()) { //Process each model if (model.name() != std::string("model")) { @@ -2261,27 +2255,25 @@ static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc } try { - temp = new t_model; - temp->index = L_index; - L_index++; - //Process the tag attributes + bool new_model_never_prune = false; + std::string new_model_name; for (pugi::xml_attribute attr : model.attributes()) { if (attr.name() == std::string("never_prune")) { auto model_type_str = vtr::strdup(attr.value()); if (std::strcmp(model_type_str, "true") == 0) { - temp->never_prune = true; + new_model_never_prune = true; } else if (std::strcmp(model_type_str, "false") == 0) { - temp->never_prune = false; + new_model_never_prune = false; } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(model), "Unsupported never prune attribute value."); } } else if (attr.name() == std::string("name")) { - if (!temp->name) { + if (new_model_name.empty()) { //First name attr. seen - temp->name = vtr::strdup(attr.value()); + new_model_name = attr.value(); } else { //Duplicate name archfpga_throw(loc_data.filename_c_str(), loc_data.line(model), @@ -2293,41 +2285,41 @@ static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc } /* Try insert new model, check if already exist at the same time */ - ret_map_name = model_name_map.insert(std::pair(temp->name, 0)); + auto ret_map_name = model_name_map.insert(std::pair(new_model_name, 0)); if (!ret_map_name.second) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(model), - "Duplicate model name: '%s'.\n", temp->name); + "Duplicate model name: '%s'.\n", new_model_name.c_str()); } + // Create the model in the model storage class + LogicalModelId new_model_id = arch->models.create_logical_model(new_model_name); + t_model& new_model = arch->models.get_model(new_model_id); + new_model.never_prune = new_model_never_prune; + //Process the ports std::set port_names; for (pugi::xml_node port_group : model.children()) { if (port_group.name() == std::string("input_ports")) { - ProcessModelPorts(port_group, temp, port_names, loc_data); + ProcessModelPorts(port_group, new_model, port_names, loc_data); } else if (port_group.name() == std::string("output_ports")) { - ProcessModelPorts(port_group, temp, port_names, loc_data); + ProcessModelPorts(port_group, new_model, port_names, loc_data); } else { bad_tag(port_group, loc_data, model, {"input_ports", "output_ports"}); } } //Sanity check the model - check_model_clocks(temp, loc_data.filename_c_str(), loc_data.line(model)); - check_model_combinational_sinks(temp, loc_data.filename_c_str(), loc_data.line(model)); - warn_model_missing_timing(temp, loc_data.filename_c_str(), loc_data.line(model)); + check_model_clocks(new_model, loc_data.filename_c_str(), loc_data.line(model)); + check_model_combinational_sinks(new_model, loc_data.filename_c_str(), loc_data.line(model)); + warn_model_missing_timing(new_model, loc_data.filename_c_str(), loc_data.line(model)); } catch (ArchFpgaError& e) { - free_arch_model(temp); throw; } - - //Add the model - temp->next = arch->models; - arch->models = temp; } return; } -static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::set& port_names, const pugiutil::loc_data& loc_data) { +static void ProcessModelPorts(pugi::xml_node port_group, t_model& model, std::set& port_names, const pugiutil::loc_data& loc_data) { for (pugi::xml_attribute attr : port_group.attributes()) { bad_attribute(attr, port_group, loc_data); } @@ -2401,14 +2393,14 @@ static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::se //Add the port if (dir == IN_PORT) { - model_port->next = model->inputs; - model->inputs = model_port; + model_port->next = model.inputs; + model.inputs = model_port; } else { VTR_ASSERT(dir == OUT_PORT); - model_port->next = model->outputs; - model->outputs = model_port; + model_port->next = model.outputs; + model.outputs = model_port; } } } @@ -2975,14 +2967,14 @@ static void MarkIoTypes(std::vector& PhysicalTileTypes) { auto equivalent_sites = get_equivalent_sites_set(&type); for (const auto& equivalent_site : equivalent_sites) { - if (block_type_contains_blif_model(equivalent_site, MODEL_INPUT)) { + if (block_type_contains_blif_model(equivalent_site, LogicalModels::MODEL_INPUT)) { type.is_input_type = true; break; } } for (const auto& equivalent_site : equivalent_sites) { - if (block_type_contains_blif_model(equivalent_site, MODEL_OUTPUT)) { + if (block_type_contains_blif_model(equivalent_site, LogicalModels::MODEL_OUTPUT)) { type.is_output_type = true; break; } diff --git a/libs/libarchfpga/src/write_models_bb.cpp b/libs/libarchfpga/src/write_models_bb.cpp index a48c0b1ab9f..0ea43f3ebc5 100644 --- a/libs/libarchfpga/src/write_models_bb.cpp +++ b/libs/libarchfpga/src/write_models_bb.cpp @@ -1,12 +1,12 @@ -#include // std::all_of +#include +#include +#include "logic_types.h" #include "vtr_util.h" // vtr::fopen #include "vtr_assert.h" // VTR ASSERT #include "write_models_bb.h" -using vtr::t_linked_vptr; - /* the output file description */ #define OUTPUT_HEADER_COMMENT(Echo, ArchFile) \ { \ @@ -26,20 +26,9 @@ using vtr::t_linked_vptr; /* a comment for the body of black box modules */ const char* HARD_BLOCK_COMMENT = "/* the body of the complex block module is empty since it should be seen as a black box */"; -/* list of vtr primitives blocks */ -static constexpr short num_vtr_primitives = 8; -static constexpr const char* vtr_primitives[num_vtr_primitives] = { - "LUT_K", - "DFF", - "fpga_interconnect", - "mux", - "adder", - "multiply", - "single_port_ram", - "dual_port_ram"}; /* declarations */ -void DeclareModel_bb(FILE* Echo, const t_model* model); +void DeclareModel_bb(FILE* Echo, const t_model& model); /** * (function: WriteModels_bb) @@ -58,21 +47,35 @@ void WriteModels_bb(const char* ArchFile, VTR_ASSERT(arch); FILE* Echo = vtr::fopen(VEchoFile, "w"); - t_model* cur_model = arch->models; /* the output file description */ OUTPUT_HEADER_COMMENT(Echo, ArchFile) + // Collect the model IDs of all the vtr primitives. + std::set vtr_primitives; + std::vector vtr_primitive_names = { + "LUT_K", + "DFF", + "fpga_interconnect", + "mux", + "adder", + "multiply", + "single_port_ram", + "dual_port_ram"}; + for (const std::string& primitive_name : vtr_primitive_names) { + LogicalModelId primitive_model_id = arch->models.get_model_by_name(primitive_name); + if (!primitive_model_id.is_valid()) + continue; + vtr_primitives.insert(primitive_model_id); + } + // iterate over models - while (cur_model) { + for (LogicalModelId model_id : arch->models.all_models()) { // avoid printing vtr primitives - if (std::all_of(vtr_primitives, - vtr_primitives + num_vtr_primitives, - [&](const auto& e) { return strcmp(e, cur_model->name); })) - DeclareModel_bb(Echo, cur_model); + if (vtr_primitives.count(model_id) != 0) + continue; - // moving forward with the next complex block - cur_model = cur_model->next; + DeclareModel_bb(Echo, arch->models.get_model(model_id)); } // CLEAN UP @@ -88,22 +91,19 @@ void WriteModels_bb(const char* ArchFile, * @param Echo pointer output file * @param model pointer to the complex block t_model */ -void DeclareModel_bb(FILE* Echo, const t_model* model) { - // validate the blackbox name - VTR_ASSERT(model); - +void DeclareModel_bb(FILE* Echo, const t_model& model) { // module - fprintf(Echo, "module %s(\n", model->name); + fprintf(Echo, "module %s(\n", model.name); // input/output ports - t_model_ports* input_port = model->inputs; + t_model_ports* input_port = model.inputs; while (input_port) { fprintf(Echo, "\tinput\t[%d:0]\t%s,\n", input_port->size - 1, input_port->name); // move forward until the end of input ports' list input_port = input_port->next; } - t_model_ports* output_port = model->outputs; + t_model_ports* output_port = model.outputs; while (output_port) { fprintf(Echo, "\toutput\t[%d:0]\t%s,\n", output_port->size - 1, output_port->name); // move forward until the end of output ports' list diff --git a/odin_ii/src/core/adders.cpp b/odin_ii/src/core/adders.cpp index ed6ecdb3f1c..4dce94d3758 100644 --- a/odin_ii/src/core/adders.cpp +++ b/odin_ii/src/core/adders.cpp @@ -26,6 +26,7 @@ #include #include +#include "logic_types.h" #include "odin_types.h" #include "odin_util.h" #include "node_creation_library.h" @@ -107,17 +108,18 @@ void report_add_distribution() { * (function: find_hard_adders) *-------------------------------------------------------------------------*/ void find_hard_adders() { - hard_adders = Arch.models; //Disable the size in configuration file.(The threshold for the extra bits). //min_add = configuration.min_hard_adder; min_threshold_adder = configuration.min_threshold_adder; - while (hard_adders != NULL) { + hard_adders = NULL; + for (LogicalModelId model_id : Arch.models.user_models()) { + hard_adders = &Arch.models.get_model(model_id); if (strcmp(hard_adders->name, "adder") == 0) { init_add_distribution(); return; } else { - hard_adders = hard_adders->next; + hard_adders = NULL; } } diff --git a/odin_ii/src/core/hard_blocks.cpp b/odin_ii/src/core/hard_blocks.cpp index ebdd39e4401..e920d54fead 100644 --- a/odin_ii/src/core/hard_blocks.cpp +++ b/odin_ii/src/core/hard_blocks.cpp @@ -26,6 +26,7 @@ #include #include +#include "logic_types.h" #include "odin_types.h" #include "odin_util.h" #include "odin_globals.h" @@ -55,14 +56,11 @@ t_model_ports* get_model_port(t_model_ports* ports, const char* name) { } void cache_hard_block_names() { - t_model* hard_blocks = NULL; - - hard_blocks = Arch.models; hard_block_names = sc_new_string_cache(); - while (hard_blocks) { + for (LogicalModelId model_id : Arch.models.user_models()) { + t_model* hard_blocks = &Arch.models.get_model(model_id); int sc_spot = sc_add_string(hard_block_names, hard_blocks->name); hard_block_names->data[sc_spot] = (void*)hard_blocks; - hard_blocks = hard_blocks->next; } } @@ -112,14 +110,9 @@ void deregister_hard_blocks() { } t_model* find_hard_block(const char* name) { - t_model* hard_blocks; - - hard_blocks = Arch.models; - while (hard_blocks) - if (!strcmp(hard_blocks->name, name)) - return hard_blocks; - else - hard_blocks = hard_blocks->next; + LogicalModelId hard_block_model_id = Arch.models.get_model_by_name(name); + if (hard_block_model_id.is_valid()) + return &Arch.models.get_model(hard_block_model_id); return NULL; } @@ -208,19 +201,17 @@ void define_hard_block(nnode_t* node, FILE* out) { void output_hard_blocks(FILE* out) { t_model_ports* hb_ports; - t_model* hard_blocks; char buffer[MAX_BUF]; int count; int i; oassert(out != NULL); - hard_blocks = Arch.models; - while (hard_blocks != NULL) { + for (LogicalModelId model_id : Arch.models.user_models()) { + t_model* hard_blocks = &Arch.models.get_model(model_id); if (hard_blocks->used == 1) /* Hard Block is utilized */ { //IF the hard_blocks is an adder or a multiplier, we ignore it.(Already print out in add_the_blackbox_for_adds and add_the_blackbox_for_mults) if (strcmp(hard_blocks->name, "adder") == 0 || strcmp(hard_blocks->name, "multiply") == 0) { - hard_blocks = hard_blocks->next; break; } @@ -261,7 +252,6 @@ void output_hard_blocks(FILE* out) { fprintf(out, "\n.blackbox\n.end\n\n"); } - hard_blocks = hard_blocks->next; } return; diff --git a/odin_ii/src/core/multipliers.cpp b/odin_ii/src/core/multipliers.cpp index a14eaa86781..6b62c93e751 100644 --- a/odin_ii/src/core/multipliers.cpp +++ b/odin_ii/src/core/multipliers.cpp @@ -29,6 +29,7 @@ #include #include +#include "logic_types.h" #include "odin_types.h" #include "odin_util.h" #include "node_creation_library.h" @@ -297,14 +298,15 @@ void report_mult_distribution() { * (function: find_hard_multipliers) *-------------------------------------------------------------------------*/ void find_hard_multipliers() { - hard_multipliers = Arch.models; + hard_multipliers = NULL; min_mult = configuration.min_hard_multiplier; - while (hard_multipliers != NULL) { + for (LogicalModelId model_id : Arch.models.user_models()) { + hard_multipliers = &Arch.models.get_model(model_id); if (strcmp(hard_multipliers->name, "multiply") == 0) { init_mult_distribution(); return; } else { - hard_multipliers = hard_multipliers->next; + hard_multipliers = NULL; } } diff --git a/odin_ii/src/verilog/verilog_writer.cpp b/odin_ii/src/verilog/verilog_writer.cpp index 623f16de861..51499a20c56 100644 --- a/odin_ii/src/verilog/verilog_writer.cpp +++ b/odin_ii/src/verilog/verilog_writer.cpp @@ -25,6 +25,7 @@ #include //std::stringstream +#include "logic_types.h" #include "verilog.h" #include "odin_globals.h" #include "hard_blocks.h" @@ -59,15 +60,12 @@ void verilog::writer::_write(const netlist_t* netlist) { } // print out the rest od models, including DSPs in the target architecture - t_model* model = Arch.models; - - while (model) { + for (LogicalModelId model_id : Arch.models.user_models()) { int sc_spot; - if ((sc_spot = sc_lookup_string(this->models_declaration, model->name)) != -1) { + if ((sc_spot = sc_lookup_string(this->models_declaration, Arch.models.model_name(model_id).c_str())) != -1) { fprintf(this->output_file, "%s", (char*)this->models_declaration->data[sc_spot]); fflush(this->output_file); } - model = model->next; } } diff --git a/parmys/parmys-plugin/core/adder.cc b/parmys/parmys-plugin/core/adder.cc index fa184b34c54..ae5cc6ef26d 100644 --- a/parmys/parmys-plugin/core/adder.cc +++ b/parmys/parmys-plugin/core/adder.cc @@ -16,6 +16,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "adder.h" +#include "logic_types.h" #include "multiplier.h" #include "netlist_utils.h" #include "node_utils.h" @@ -96,17 +97,18 @@ void report_add_distribution() *-------------------------------------------------------------------------*/ void find_hard_adders() { - hard_adders = Arch.models; // Disable the size in configuration file.(The threshold for the extra bits). // min_add = configuration.min_hard_adder; min_threshold_adder = configuration.min_threshold_adder; - while (hard_adders != NULL) { + hard_adders = NULL; + for (LogicalModelId model_id : Arch.models.user_models()) { + hard_adders = &Arch.models.get_model(model_id); if (strcmp(hard_adders->name, "adder") == 0) { init_add_distribution(); return; } else { - hard_adders = hard_adders->next; + hard_adders = NULL; } } @@ -1405,4 +1407,4 @@ nnode_t *check_missing_ports(nnode_t *node, uintptr_t traverse_mark_number, netl } return new_node; -} \ No newline at end of file +} diff --git a/parmys/parmys-plugin/core/hard_block.cc b/parmys/parmys-plugin/core/hard_block.cc index a7437518f78..cfadd5b0dac 100644 --- a/parmys/parmys-plugin/core/hard_block.cc +++ b/parmys/parmys-plugin/core/hard_block.cc @@ -15,9 +15,11 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include "hard_block.h" +#include "logic_types.h" #include "memory.h" #include "netlist_utils.h" #include "odin_globals.h" @@ -53,14 +55,17 @@ t_model_ports *get_model_port(t_model_ports *ports, const char *name) void cache_hard_block_names() { - t_model *hard_blocks = NULL; - - hard_blocks = Arch.models; hard_block_names = sc_new_string_cache(); - while (hard_blocks) { + // After a change to the construction of the user models, the order was + // reversed, which slightly changed the results. Reversing them back to + // attain the same results, simplifying my testing. + // TODO: Regenerate the golden solutions to use the new model order. + std::vector user_models(Arch.models.user_models().begin(), Arch.models.user_models().end()); + std::reverse(user_models.begin(), user_models.end()); + for (LogicalModelId model_id : user_models) { + t_model* hard_blocks = &Arch.models.get_model(model_id); int sc_spot = sc_add_string(hard_block_names, hard_blocks->name); hard_block_names->data[sc_spot] = (void *)hard_blocks; - hard_blocks = hard_blocks->next; } } @@ -98,14 +103,9 @@ void register_hard_blocks() t_model *find_hard_block(const char *name) { - t_model *hard_blocks; - - hard_blocks = Arch.models; - while (hard_blocks) - if (!strcmp(hard_blocks->name, name)) - return hard_blocks; - else - hard_blocks = hard_blocks->next; + LogicalModelId hard_block_model_id = Arch.models.get_model_by_name(name); + if (hard_block_model_id.is_valid()) + return &Arch.models.get_model(hard_block_model_id); return NULL; } @@ -201,16 +201,20 @@ void cell_hard_block(nnode_t *node, Yosys::Module *module, netlist_t *netlist, Y void output_hard_blocks_yosys(Yosys::Design *design) { t_model_ports *hb_ports; - t_model *hard_blocks; - hard_blocks = Arch.models; - while (hard_blocks != NULL) { + // After a change to the construction of the user models, the order was + // reversed, which slightly changed the results. Reversing them back to + // attain the same results, simplifying my testing. + // TODO: Regenerate the golden solutions to use the new model order. + std::vector user_models(Arch.models.user_models().begin(), Arch.models.user_models().end()); + std::reverse(user_models.begin(), user_models.end()); + for (LogicalModelId model_id : user_models) { + t_model* hard_blocks = &Arch.models.get_model(model_id); if (hard_blocks->used == 1) /* Hard Block is utilized */ { // IF the hard_blocks is an adder or a multiplier, we ignore it.(Already print out in add_the_blackbox_for_adds and // add_the_blackbox_for_mults) if (strcmp(hard_blocks->name, "adder") == 0 || strcmp(hard_blocks->name, "multiply") == 0) { - hard_blocks = hard_blocks->next; break; } @@ -277,8 +281,6 @@ void output_hard_blocks_yosys(Yosys::Design *design) module->attributes[Yosys::ID::blackbox] = Yosys::RTLIL::Const(1); } - - hard_blocks = hard_blocks->next; } return; diff --git a/parmys/parmys-plugin/core/multiplier.cc b/parmys/parmys-plugin/core/multiplier.cc index befb0b337bd..3a411217f25 100644 --- a/parmys/parmys-plugin/core/multiplier.cc +++ b/parmys/parmys-plugin/core/multiplier.cc @@ -16,6 +16,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "multiplier.h" +#include "logic_types.h" #include "netlist_utils.h" #include "node_utils.h" #include "odin_globals.h" @@ -544,14 +545,15 @@ void report_mult_distribution() *-------------------------------------------------------------------------*/ void find_hard_multipliers() { - hard_multipliers = Arch.models; + hard_multipliers = NULL; min_mult = configuration.min_hard_multiplier; - while (hard_multipliers != NULL) { + for (LogicalModelId model_id : Arch.models.user_models()) { + hard_multipliers = &Arch.models.get_model(model_id); if (strcmp(hard_multipliers->name, "multiply") == 0) { init_mult_distribution(); return; } else { - hard_multipliers = hard_multipliers->next; + hard_multipliers = NULL; } } diff --git a/parmys/parmys-plugin/parmys.cc b/parmys/parmys-plugin/parmys.cc index 910f7711dee..158db0253b8 100644 --- a/parmys/parmys-plugin/parmys.cc +++ b/parmys/parmys-plugin/parmys.cc @@ -1159,9 +1159,8 @@ struct ParMYSPass : public Pass { free_netlist(transformed); - if (Arch.models) { + if (!Arch.models.all_models().empty()) { free_arch(&Arch); - Arch.models = nullptr; } free_type_descriptors(logical_block_types); @@ -1183,4 +1182,4 @@ struct ParMYSPass : public Pass { } } ParMYSPass; -PRIVATE_NAMESPACE_END \ No newline at end of file +PRIVATE_NAMESPACE_END diff --git a/parmys/parmys-plugin/parmys_arch.cc b/parmys/parmys-plugin/parmys_arch.cc index 97a8591ab60..995c9356264 100644 --- a/parmys/parmys-plugin/parmys_arch.cc +++ b/parmys/parmys-plugin/parmys_arch.cc @@ -120,15 +120,19 @@ struct ParmysArchPass : public Pass { const char *arch_info_file = "arch.info"; EchoArch(arch_info_file, physical_tile_types, logical_block_types, &arch); - t_model *hb = arch.models; - while (hb) { + // After a change to the construction of the user models, the order was + // reversed, which slightly changed the results. Reversing them back to + // attain the same results. + // TODO: Regenerate the golden solutions to use the new model order. + std::vector user_models(arch.models.user_models().begin(), arch.models.user_models().end()); + std::reverse(user_models.begin(), user_models.end()); + for (LogicalModelId model_id : user_models) { + t_model* hb = &arch.models.get_model(model_id); if (strcmp(hb->name, SINGLE_PORT_RAM_string) && strcmp(hb->name, DUAL_PORT_RAM_string) && strcmp(hb->name, "multiply") && strcmp(hb->name, "adder")) { add_hb_to_design(hb, design); log("Hard block added to the Design ---> `%s`\n", hb->name); } - - hb = hb->next; } // CLEAN UP diff --git a/utils/fasm/src/fasm.cpp b/utils/fasm/src/fasm.cpp index 2785c1149e8..9a10808cdb1 100644 --- a/utils/fasm/src/fasm.cpp +++ b/utils/fasm/src/fasm.cpp @@ -591,14 +591,16 @@ void FasmWriterVisitor::check_for_param(const t_pb *atom) { void FasmWriterVisitor::check_for_lut(const t_pb* atom) { auto& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; auto atom_blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_blk_id == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.netlist().block_model(atom_blk_id); - if (model->name == std::string(MODEL_NAMES)) { + LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); + LogicalModelId model_id = atom_ctx.netlist().block_model(atom_blk_id); + if (model_id == names_model_id) { VTR_ASSERT(atom->pb_graph_node != nullptr); const auto *lut_definition = find_lut(atom->pb_graph_node); VTR_ASSERT(lut_definition->num_inputs == *atom->pb_graph_node->num_input_pins); diff --git a/utils/vqm2blif/src/base/hard_block_recog.cpp b/utils/vqm2blif/src/base/hard_block_recog.cpp index 60be10d9457..f16f8ebfa3d 100644 --- a/utils/vqm2blif/src/base/hard_block_recog.cpp +++ b/utils/vqm2blif/src/base/hard_block_recog.cpp @@ -124,6 +124,7 @@ #include "hard_block_recog.h" +#include "logic_types.h" //============================================================================================ // INTERNAL FUNCTION DECLARATIONS @@ -133,7 +134,7 @@ static void initialize_hard_block_models(t_arch* main_arch, std::vector* hard_block_type_name_list, t_hard_block_recog* module_hard_block_node_refs_and_info); -static bool create_and_initialize_all_hard_block_ports(t_model* hard_block_arch_model, t_hard_block_recog* storage_of_hard_block_info); +static bool create_and_initialize_all_hard_block_ports(const t_model& hard_block_arch_model, t_hard_block_recog* storage_of_hard_block_info); static void create_hard_block_port_info_structure(t_hard_block_recog* storage_of_hard_block_info, std::string hard_block_type_name); @@ -323,7 +324,6 @@ void add_hard_blocks_to_netlist(t_module* main_module, t_arch* main_arch, std::v */ static void initialize_hard_block_models(t_arch* main_arch, std::vector* hard_block_type_names, t_hard_block_recog* storage_of_hard_block_info) { - t_model* hard_block_model = NULL; std::vector::iterator hard_block_type_name_traverser; bool single_hard_block_init_result = false; @@ -331,15 +331,16 @@ static void initialize_hard_block_models(t_arch* main_arch, std::vectorbegin(); hard_block_type_name_traverser != hard_block_type_names->end(); hard_block_type_name_traverser++) { // get the corresponding model for each hard block name - hard_block_model = find_arch_model_by_name(*hard_block_type_name_traverser, main_arch->models); + LogicalModelId hard_block_model_id = main_arch->models.get_model_by_name(*hard_block_type_name_traverser); // a check to see if the model was found within the FPGA architecture - if (hard_block_model == NULL) + if (!hard_block_model_id.is_valid()) { throw vtr::VtrError("The provided hard block model: '" + *hard_block_type_name_traverser + "' was not found within the corresponding FPGA architecture."); } else - { + { + const t_model& hard_block_model = main_arch->models.get_model(hard_block_model_id); // store the port information for the current hard block model single_hard_block_init_result = create_and_initialize_all_hard_block_ports(hard_block_model, storage_of_hard_block_info); @@ -478,15 +479,15 @@ static void process_module_nodes_and_create_hard_blocks(t_module* main_module, s * the FPGA had any ports. * */ -static bool create_and_initialize_all_hard_block_ports(t_model* hard_block_arch_model, t_hard_block_recog* storage_of_hard_block_info) +static bool create_and_initialize_all_hard_block_ports(const t_model& hard_block_arch_model, t_hard_block_recog* storage_of_hard_block_info) { int hard_block_port_index = 0; - std::string hard_block_arch_model_name = hard_block_arch_model->name; + std::string hard_block_arch_model_name = hard_block_arch_model.name; bool result = true; // get the hard block ports - t_model_ports* input_ports = hard_block_arch_model->inputs; - t_model_ports* output_ports = hard_block_arch_model->outputs; + t_model_ports* input_ports = hard_block_arch_model.inputs; + t_model_ports* output_ports = hard_block_arch_model.outputs; //initialize a hard block node port array create_hard_block_port_info_structure(storage_of_hard_block_info,hard_block_arch_model_name); diff --git a/utils/vqm2blif/src/base/preprocess.cpp b/utils/vqm2blif/src/base/preprocess.cpp index 8ae41297d23..092d8a67180 100644 --- a/utils/vqm2blif/src/base/preprocess.cpp +++ b/utils/vqm2blif/src/base/preprocess.cpp @@ -2,6 +2,7 @@ // INCLUDES //============================================================================================ #include "preprocess.h" +#include "logic_types.h" #include "vqm_common.h" #include "lut_stats.h" #include "vtr_memory.h" @@ -9,7 +10,6 @@ #include "vtr_assert.h" #include "vqm2blif_util.h" #include "physical_types.h" -#include //============================================================================================ @@ -19,9 +19,9 @@ //Functions to identify and decompose inout pins void decompose_inout_pins(t_module* module, t_arch* arch, string device); -t_model* find_model_in_architecture(t_model* arch_models, t_node* node, string device); +LogicalModelId find_model_in_architecture(const LogicalModels& arch_models, t_node* node, string device); -t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_association* node_port); +t_model_ports* find_port_in_architecture_model(const t_model& arch_model, t_node_port_association* node_port); char* prefix_string(const char* prefix, const char* base); @@ -314,11 +314,11 @@ void decompose_inout_pins(t_module* module, t_arch* arch, string device){ */ //Architecture pointers - t_model* arch_model; t_model_ports* arch_model_port; //Find the model - arch_model = find_model_in_architecture(arch->models, node, device); + LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); + const t_model& arch_model = arch->models.get_model(arch_model_id); //Find the architecure model port arch_model_port = find_port_in_architecture_model(arch_model, node_port); @@ -372,7 +372,7 @@ void decompose_inout_pins(t_module* module, t_arch* arch, string device){ cout << "\t>> Decomposed " << number_of_inout_pins_found << " 'inout' pin(s), moving " << number_of_nets_moved << " net(s)" << endl; } -t_model* find_model_in_architecture(t_model* arch_models, t_node* node, string device) { +LogicalModelId find_model_in_architecture(const LogicalModels& arch_models, t_node* node, string device) { /* * Finds the archtecture module corresponding to the node type * @@ -387,20 +387,15 @@ t_model* find_model_in_architecture(t_model* arch_models, t_node* node, string d string elaborated_name = generate_opname(node, arch_models, device); //Find the correct model, by name matching - t_model* arch_model = arch_models; - while((arch_model) && (strcmp(elaborated_name.c_str(), arch_model->name) != 0)) { - //Move to the next model - arch_model = arch_model->next; - } + LogicalModelId arch_model_id = arch_models.get_model_by_name(elaborated_name); //The model must be in the arch file - if (arch_model == NULL) { + if (!arch_model_id.is_valid()) { cout << "Error: could not find model in architecture file for '" << node->type << "'\n"; exit(1); } - VTR_ASSERT(arch_model != NULL); - return arch_model; + return arch_model_id; } char* prefix_string(const char* prefix, const char* base) { @@ -416,7 +411,7 @@ char* prefix_string(const char* prefix, const char* base) { return new_string; } -t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_association* node_port) { +t_model_ports* find_port_in_architecture_model(const t_model& arch_model, t_node_port_association* node_port) { /* * Finds the module port corresponding to the port name * @@ -435,7 +430,7 @@ t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_ //Check inputs //Find the correct port, by name matching - t_model_ports* arch_model_port = arch_model->inputs; + t_model_ports* arch_model_port = arch_model.inputs; //Until NULL or a matching port name while ((arch_model_port) && (strcmp(arch_model_port->name, node_port->port_name) != 0)) { @@ -451,7 +446,7 @@ t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_ //Not an input should be an output //Check outputs - arch_model_port = arch_model->outputs; + arch_model_port = arch_model.outputs; //Until NULL or a matching port name while ((arch_model_port) && (strcmp(arch_model_port->name, node_port->port_name) != 0)) { @@ -465,7 +460,7 @@ t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_ //arch_model_port must be either an input or an output, // hence it should never be NULL at this point if (arch_model_port == NULL) { - cout << "Error: could not find port '" << node_port->port_name << "' on model '" << arch_model->name << "' in architecture file\n"; + cout << "Error: could not find port '" << node_port->port_name << "' on model '" << arch_model.name << "' in architecture file\n"; exit(1); } } @@ -1496,7 +1491,8 @@ void check_and_fix_clock_to_normal_port_connections(t_module* module, t_arch* ar //check whether it is the driver //Find the model - t_model* arch_model = find_model_in_architecture(arch->models, node, device); + LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); + const t_model& arch_model = arch->models.get_model(arch_model_id); //Look-up the arch model port t_model_ports* arch_model_port = find_port_in_architecture_model(arch_model, node_port); @@ -1618,7 +1614,8 @@ void check_and_fix_clock_to_normal_port_connections(t_module* module, t_arch* ar t_node_port_association* node_port = node->array_of_ports[j]; //Find the model - t_model* arch_model = find_model_in_architecture(arch->models, node, device); + LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); + const t_model& arch_model = arch->models.get_model(arch_model_id); //Look-up the arch model port t_model_ports* arch_model_port = find_port_in_architecture_model(arch_model, node_port); @@ -2516,11 +2513,11 @@ t_net_driver_map identify_net_drivers(t_module* module, t_arch* arch, t_global_p */ //Architecture pointers - t_model* arch_model; t_model_ports* arch_model_port; //Find the model - arch_model = find_model_in_architecture(arch->models, node, device); + LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); + const t_model& arch_model = arch->models.get_model(arch_model_id); //Find the architecure model port arch_model_port = find_port_in_architecture_model(arch_model, node_port); diff --git a/utils/vqm2blif/src/base/vqm2blif.h b/utils/vqm2blif/src/base/vqm2blif.h index e206ba11d7c..c855dc7b200 100644 --- a/utils/vqm2blif/src/base/vqm2blif.h +++ b/utils/vqm2blif/src/base/vqm2blif.h @@ -56,6 +56,7 @@ // INCLUDES //============================================================================================ +#include "logic_types.h" #include "vqm2blif_util.h" #include "lutmask.h" #include "cleanup.h" @@ -74,7 +75,7 @@ struct t_subckt_param_attr { typedef struct s_blif_subckt{ string inst_name; - t_model* model_type; + LogicalModelId model_type; portmap input_cnxns; diff --git a/utils/vqm2blif/src/base/vqm2blif_util.cpp b/utils/vqm2blif/src/base/vqm2blif_util.cpp index dbee284a5f7..d2bd322c5a2 100644 --- a/utils/vqm2blif/src/base/vqm2blif_util.cpp +++ b/utils/vqm2blif/src/base/vqm2blif_util.cpp @@ -1,6 +1,6 @@ #include "vqm2blif_util.h" +#include "logic_types.h" #include "vtr_util.h" -#include "vtr_memory.h" #include "vtr_assert.h" #define dsp_clock_count 15 @@ -215,7 +215,7 @@ string get_wire_name(t_pin_def* net, int index){ //============================================================================================ //============================================================================================ -string generate_opname (t_node* vqm_node, t_model* arch_models, string device){ +string generate_opname (t_node* vqm_node, const LogicalModels& arch_models, string device){ //Add support for different architectures here. // Currently only support Stratix IV and Stratix 10 string mode_hash; @@ -225,7 +225,8 @@ string generate_opname (t_node* vqm_node, t_model* arch_models, string device){ mode_hash = generate_opname_stratixiv(vqm_node, arch_models); //Final sanity check - if (NULL == find_arch_model_by_name(mode_hash, arch_models)){ + LogicalModelId arch_model_id = arch_models.get_model_by_name(mode_hash); + if (!arch_model_id.is_valid()) { cout << "Error: could not find primitive '" << mode_hash << "' in architecture file" << endl; exit(1); } @@ -234,7 +235,7 @@ string generate_opname (t_node* vqm_node, t_model* arch_models, string device){ } -string generate_opname_stratixiv (t_node* vqm_node, t_model* arch_models){ +string generate_opname_stratixiv (t_node* vqm_node, const LogicalModels& arch_models){ /* Generates a mode-hash string based on a node's name and parameter set * * ARGUMENTS @@ -281,16 +282,14 @@ string generate_opname_stratixiv (t_node* vqm_node, t_model* arch_models){ * DSP Block Multipliers */ if(strcmp(vqm_node->type, "stratixiv_mac_mult") == 0) { - generate_opname_stratixiv_dsp_mult(vqm_node, arch_models, mode_hash); - + generate_opname_stratixiv_dsp_mult(vqm_node, mode_hash); } /* * DSP Block Output (MAC) */ if(strcmp(vqm_node->type, "stratixiv_mac_out") == 0) { - generate_opname_stratixiv_dsp_out(vqm_node, arch_models, mode_hash); - + generate_opname_stratixiv_dsp_out(vqm_node, mode_hash); } /* @@ -303,7 +302,7 @@ string generate_opname_stratixiv (t_node* vqm_node, t_model* arch_models){ return mode_hash; } -void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, t_model* /*arch_models*/, string& mode_hash) { +void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, string& mode_hash) { //We check for all mac_mult's input ports to see if any use a clock // if so, we set ALL input ports to be registered. While this is an approximation, // it would be very unusually to have only some of the ports registered. @@ -413,7 +412,7 @@ void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, t_model* /*arch_model } } -void generate_opname_stratixiv_dsp_out (t_node* vqm_node, t_model* /*arch_models*/, string& mode_hash) { +void generate_opname_stratixiv_dsp_out (t_node* vqm_node, string& mode_hash) { //It is not practical to model all of the internal registers of the mac_out block, as this // would significantly increase the size of the architecture description. As a result, we // only identify whether the input or output registers are used. @@ -525,7 +524,7 @@ void generate_opname_stratixiv_dsp_out (t_node* vqm_node, t_model* /*arch_models } -void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_hash, string device) { +void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, string& mode_hash, string device) { if(device == "stratixiv") VTR_ASSERT(strcmp(vqm_node->type, "stratixiv_ram_block") == 0); @@ -607,7 +606,8 @@ void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_h //Only print the address width, the data widths are handled by the VPR memory class mode_hash.append(".port_a_address_width{" + std::to_string(ram_info.port_a_addr_width) + "}"); - if (find_arch_model_by_name(mode_hash, arch_models) == NULL){ + LogicalModelId arch_model_id = arch_models.get_model_by_name(mode_hash); + if (!arch_model_id.is_valid()) { cout << "Error: could not find single port memory primitive '" << mode_hash << "' in architecture file" << endl; exit(1); } @@ -623,7 +623,8 @@ void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_h mode_hash.append(".port_a_address_width{" + std::to_string(ram_info.port_a_addr_width) + "}"); mode_hash.append(".port_b_address_width{" + std::to_string(ram_info.port_b_addr_width) + "}"); - if (find_arch_model_by_name(mode_hash, arch_models) == NULL){ + LogicalModelId arch_model_id = arch_models.get_model_by_name(mode_hash); + if (!arch_model_id.is_valid()) { cout << "Error: could not find dual port (non-mixed_width) memory primitive '" << mode_hash << "' in architecture file"; exit(1); } @@ -644,7 +645,8 @@ void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_h tmp_mode_hash.append(".port_a_data_width{" + std::to_string(ram_info.port_a_data_width) + "}"); tmp_mode_hash.append(".port_b_data_width{" + std::to_string(ram_info.port_b_data_width) + "}"); - if (find_arch_model_by_name(tmp_mode_hash, arch_models) == NULL){ + LogicalModelId arch_model_id = arch_models.get_model_by_name(tmp_mode_hash); + if (!arch_model_id.is_valid()) { //3a) Not found, use the default name (no specific address/data widths) ; // do nothing } else { @@ -655,7 +657,7 @@ void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_h } } -string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models){ +string generate_opname_stratix10 (t_node* vqm_node, const LogicalModels& arch_models){ /* Generates a mode-hash string based on a node's name and parameter set * * ARGUMENTS @@ -707,7 +709,7 @@ string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models){ * DSP Block - fixed point */ if(strcmp(vqm_node->type, "fourteennm_mac") == 0) { - generate_opname_stratix10_dsp(vqm_node, arch_models, mode_hash, 0); + generate_opname_stratix10_dsp(vqm_node, mode_hash, 0); } @@ -715,7 +717,7 @@ string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models){ * DSP Block - floating point */ if(strcmp(vqm_node->type, "fourteennm_fp_mac") == 0) { - generate_opname_stratix10_dsp(vqm_node, arch_models, mode_hash, 1); + generate_opname_stratix10_dsp(vqm_node, mode_hash, 1); } @@ -729,7 +731,7 @@ string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models){ return mode_hash; } -void generate_opname_stratix10_dsp (t_node* vqm_node, t_model* /*arch_models*/, string& mode_hash, bool dsp_mode) { +void generate_opname_stratix10_dsp (t_node* vqm_node, string& mode_hash, bool dsp_mode) { // // It is not practical to model all of the internal registers of the mac block, as this // would significantly increase the size of the architecture description. As a result, we @@ -904,28 +906,6 @@ void clean_name(char* name) { } } -//============================================================================================ -//============================================================================================ -t_model* find_arch_model_by_name(string model_name, t_model* arch_models) { - /* - * Finds the archtecture module corresponding to the model_name string - * - * model_name : the model name to match - * arch_models: the head of the linked list of architecture models - * - * Returns: A pointer to the corresponding model (or NULL if not found) - */ - - //Find the correct model, by name matching - t_model* arch_model = arch_models; - while((arch_model) && (strcmp(model_name.c_str(), arch_model->name) != 0)) { - //Move to the next model - arch_model = arch_model->next; - } - - return arch_model; -} - //============================================================================================ //============================================================================================ diff --git a/utils/vqm2blif/src/base/vqm2blif_util.h b/utils/vqm2blif/src/base/vqm2blif_util.h index 314724e6226..45cc5adedf4 100644 --- a/utils/vqm2blif/src/base/vqm2blif_util.h +++ b/utils/vqm2blif/src/base/vqm2blif_util.h @@ -13,6 +13,7 @@ //these assignments are not observed. Buses in a VQM File are flattened into 1-bit wide assigns. //NOTE: The functionality of this option is untested. +#include "logic_types.h" #define MAX_LEN 350 //maximum length of a port/net name #define MAX_PPL 10 //maximum number of ports that can be put into one line of a BLIF @@ -175,22 +176,19 @@ void construct_filename (char* filename, const char* path, const char* ext); //c //Naming Conventions -string generate_opname (t_node* vqm_node, t_model* arch_models, string device); //generates a mode-hashed name for a subcircuit instance +string generate_opname (t_node* vqm_node, const LogicalModels& arch_models, string device); //generates a mode-hashed name for a subcircuit instance -void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_hash, string device); //mode-hash for RAM blocks +void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, string& mode_hash, string device); //mode-hash for RAM blocks -string generate_opname_stratixiv (t_node* vqm_node, t_model* arch_models); //mode-hash for Stratix IV -void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, t_model* arch_models, string& mode_hash); //mode-hash for Stratix IV DSP Multiplers -void generate_opname_stratixiv_dsp_out (t_node* vqm_node, t_model* arch_models, string& mode_hash); //mode-hash for Stratix IV DSP Output (MAC) +string generate_opname_stratixiv (t_node* vqm_node, const LogicalModels& arch_models); //mode-hash for Stratix IV +void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix IV DSP Multiplers +void generate_opname_stratixiv_dsp_out (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix IV DSP Output (MAC) -string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models); //mode-hash for Stratix 10 -void generate_opname_stratix10_ram (t_node* vqm_node, t_model* arch_models, string& mode_hash); //mode-hash for Stratix 10 RAM blocks -void generate_opname_stratix10_dsp (t_node* vqm_node, t_model* arch_models, string& mode_hash, bool dsp_mode); //mode-hash for Stratix 10 DSP fixed point Multiplers +string generate_opname_stratix10 (t_node* vqm_node, const LogicalModels& arch_models); //mode-hash for Stratix 10 +void generate_opname_stratix10_dsp (t_node* vqm_node, string& mode_hash, bool dsp_mode); //mode-hash for Stratix 10 DSP fixed point Multiplers void generate_opname_stratix10_lut (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix 10 LUTs void remap_lut_ports(t_node* vqm_node); // remaps the input ports of the LUT atom to the ports [dataa-datae] -t_model* find_arch_model_by_name(string model_name, t_model* arch_models); //returns the pointer to a module from the arch file, searches by name - string get_wire_name(t_pin_def* net, int index); //returns a string with the appropriate wire name string append_index_to_str (string busname, int index); //appends an integer index to the end of a string diff --git a/utils/vqm2blif/src/main.cpp b/utils/vqm2blif/src/main.cpp index 36c30b57e07..20e82c0ac2f 100644 --- a/utils/vqm2blif/src/main.cpp +++ b/utils/vqm2blif/src/main.cpp @@ -77,11 +77,13 @@ * For more, see "logic_types.h", "read_xml_arch_file.h" and "read_xml_arch_file.c" in libvpr *********************************************************************************************/ +#include "logic_types.h" #include "vqm2blif.h" #include "lut_stats.h" #include "vtr_error.h" #include "physical_types.h" #include "hard_block_recog.h" +#include "vtr_vector.h" #include @@ -97,8 +99,8 @@ lut_support_map supported_luts; //map structure for verifying a VQM primitive ag //LUT configurations (see lut_regoc.h & lut_recog.cpp) -int* model_count; //array of flags indicating whether a model read from - //the architecture was instantiated in the .vqm file. +vtr::vector model_count; //array of flags indicating whether a model read from + //the architecture was instantiated in the .vqm file. t_boolean debug_mode; //user-set flag causing the creation of intermediate files //with debug information. @@ -157,19 +159,19 @@ void cmd_line_parse (int argc, char** argv, string* sourcefile, string* archfile //Execution Functions void init_blif_models(t_blif_model* my_model, t_module* my_module, t_arch* arch, string device); - void subckt_prep(t_model* cur_model); + void subckt_prep(const LogicalModels& models); void init_blif_subckts (t_node **vqm_nodes, int number_of_vqm_nodes, - t_model *arch_models, t_blif_model* my_model, string device); + const LogicalModels& models, t_blif_model* my_model, string device); //1-to-1 Subcircuit Function //Translates one VQM Node into one BLIF Subcircuit, appends a mode-hash based on //parameters if elab_mode is MODES or MODES_TIMING. - void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_subckts, string device); + void push_node_1_to_1 (t_node* vqm_node, const LogicalModels& models, scktvec* blif_subckts, string device); //Atomize Subcircuit Function //Uses select parameters and a dictionary to atomize each block and //name it as the dictionary says. - void push_node_atomize (t_node* vqm_node, t_model* arch_models, scktvec* blif_subckts); + void push_node_atomize (t_node* vqm_node, const LogicalModels& models, scktvec* blif_subckts); //General Subcircuit Initialization //No matter the translation, models from the architecture get turned into @@ -187,7 +189,7 @@ void init_blif_models(t_blif_model* my_model, t_module* my_module, t_arch* arch, void dump_blif (char* blif_file, t_blif_model* main_model, t_arch* arch, t_boolean print_unused_subckt_pins); -void dump_main_model(t_blif_model* model, ofstream& outfile, t_boolean print_unused_subckt_pins, t_boolean eblif_format, t_boolean debug); +void dump_main_model(t_blif_model* model, ofstream& outfile, const LogicalModels& models, t_boolean print_unused_subckt_pins, t_boolean eblif_format, t_boolean debug); void dump_portlist (ofstream& outfile, pinvec ports, t_boolean debug); void dump_assignments(ofstream& outfile, t_blif_model* model, t_boolean eblif_format, t_boolean debug); @@ -208,7 +210,7 @@ void dump_wire_assign(ofstream& outfile, string target_name, void dump_luts (ofstream& outfile, lutvec* blif_luts, t_boolean eblif_format, t_boolean debug); -void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pins, t_boolean eblif_format, t_boolean debug); +void dump_subckts(ofstream& outfile, scktvec* subckts, const LogicalModels& models, t_boolean print_unused_pins, t_boolean eblif_format, t_boolean debug); void dump_subckt_map (ofstream& outfile, portmap* map, t_model_ports* temp_port, const char* inst_name, const char* maptype, int s_index, t_boolean print_unused_pins, t_boolean debug, bool last); @@ -216,7 +218,7 @@ size_t count_print_pins(t_model_ports* temp_port, portmap* map, t_boolean print_ void dump_subckt_portlist(ofstream& outfile, t_model_ports* port, string indent, t_boolean debug); -void dump_subckt_models(t_model* temp_model, ofstream& outfile, t_boolean debug); +void dump_subckt_models(const LogicalModels& models, ofstream& outfile, t_boolean debug); //Debug functions void echo_module (char* echo_file, const char* vqm_filename, t_module* my_module); @@ -224,7 +226,7 @@ void echo_module_pins (ofstream& outfile, t_module* module); void echo_module_assigns (ofstream& outfile, t_module* module); void echo_module_nodes (ofstream& outfile, t_module* module); void echo_blif_model (char* echo_file, const char* vqm_filename, - t_blif_model* my_model, t_model* temp_model); + t_blif_model* my_model, const LogicalModels& models); //Other Functions @@ -335,7 +337,7 @@ int main(int argc, char* argv[]) numTypes = logical_block_types.size(); VTR_ASSERT((types) && (numTypes > 0)); - VTR_ASSERT(arch.models != NULL); + VTR_ASSERT(!arch.models.user_models().empty()); //Pre-process the netlist // Currently this just 'cleans up' bi-directional inout pins @@ -858,7 +860,7 @@ void init_blif_models(t_blif_model* my_model, t_module* my_module, t_arch* arch, //============================================================================================ void init_blif_subckts ( t_node **vqm_nodes, int number_of_vqm_nodes, - t_model *arch_models, + const LogicalModels& models, t_blif_model* my_model, string device){ /* Initializes the subcircuits vector within a t_blif_model based on a t_node array. * @@ -876,8 +878,7 @@ void init_blif_subckts ( t_node **vqm_nodes, t_node* temp_node; //from vqm_dll.h //Preparations before the subcircuits can be assigned. - VTR_ASSERT(arch_models != NULL); - subckt_prep(arch_models); + subckt_prep(models); VTR_ASSERT((vqm_nodes != NULL)&&(vqm_nodes[0] != NULL)&&(number_of_vqm_nodes >= 0)); @@ -896,9 +897,9 @@ void init_blif_subckts ( t_node **vqm_nodes, if ((lut_mode == BLIF)&&(is_lut(temp_node))){ push_lut ( temp_node, &(my_model->luts) ); } else if ((elab_mode == NONE)||(elab_mode == MODES)||(elab_mode == MODES_TIMING)){ - push_node_1_to_1 (temp_node, arch_models, &(my_model->subckts), device); + push_node_1_to_1 (temp_node, models, &(my_model->subckts), device); } else if (elab_mode == ATOMS){ - push_node_atomize (temp_node, arch_models, &(my_model->subckts)); + push_node_atomize (temp_node, models, &(my_model->subckts)); } else { //Should never get here; a bad elab_mode should be rejected at parse-time cout << "\nERROR: Corrupted Elaboration Mode.\n" ; @@ -910,7 +911,7 @@ void init_blif_subckts ( t_node **vqm_nodes, //============================================================================================ //============================================================================================ -void subckt_prep(t_model* cur_model){ +void subckt_prep(const LogicalModels& models){ /* Accomplishes preparatory tasks before the subcircuits of a blif_model can be initialized. * * ARGUMENTS @@ -918,24 +919,10 @@ void subckt_prep(t_model* cur_model){ * Linked list containing all model information from the Architecture file. */ -//TASK 1: Find the maximum index among the models in the Architecture. - int max_model_index; - max_model_index = cur_model->index; - while(cur_model){ - //Cycle through the list, save the highest index. - if (cur_model->index > max_model_index){ - max_model_index = cur_model->index; - } - cur_model = cur_model->next; - } +//TASK 1: Allocate and initialize the model_count array (global). + model_count = vtr::vector(models.all_models().size(), 0); -//TASK 2: Allocate and initialize the model_count array (global). - model_count = (int*)malloc((max_model_index + 1)*sizeof(int)); - for (int i = 0; i <= max_model_index; i++){ - model_count[i] = 0; - } - -//TASK 3: Initialize the unconn and open_port structures. +//TASK 2: Initialize the unconn and open_port structures. unconn.name = strdup("unconn"); unconn.indexed = T_FALSE; unconn.type = PIN_WIRE; @@ -951,7 +938,7 @@ void subckt_prep(t_model* cur_model){ //============================================================================================ //============================================================================================ -void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_subckts, string device){ +void push_node_1_to_1 (t_node* vqm_node, const LogicalModels& models, scktvec* blif_subckts, string device){ /* Interprets each VQM block as a single instance of a BLIF subcircuit. Depending on * the global elab_mode, the Architecture will be searched either for the VQM block name as-is * or a name appended with a special mode-hash, generated from parameters of the VQM block. @@ -967,16 +954,12 @@ void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_sub //temporary process variables t_blif_subckt temp_subckt; //from vqm2blif.h - t_model* cur_model; //from physical_types.h boolvec vqm_ports_found; //verification flags indicating that all ports //found in the VQM were mapped. string search; //temporary variable to construct a desired block name within. - cur_model = arch_models; //search for the corresponding model in the list from the architecture. - VTR_ASSERT(cur_model != NULL); - temp_subckt.inst_name = (string)vqm_node->name; //copy the instance name VTR_ASSERT( !temp_subckt.inst_name.empty() ); @@ -987,7 +970,7 @@ void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_sub } else if (elab_mode == MODES || elab_mode == MODES_TIMING){ //search for an Architecture model based on the block name and the parameters - search = generate_opname(vqm_node, arch_models, device); //generate the simple mode-hashed name based on parameters. + search = generate_opname(vqm_node, models, device); //generate the simple mode-hashed name based on parameters. } else { //should never get here, based on condition in init_blif_subckts() @@ -1008,100 +991,100 @@ void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_sub cout << "\n\t\t>> Blackbox Identified." ; cout << "\n\t\t>> Searching Architecture for Model Data \""<< search << "\"" ; } - while ((cur_model)&&(strcmp(cur_model->name, search.c_str()) != 0)){ - cur_model = cur_model->next; - } + LogicalModelId model_id = models.get_model_by_name(search); //cur_model now points to either NULL or the appropriate Architecture model. - if (!cur_model){ + if (!model_id.is_valid()){ //cur_model == NULL if the end of the model list was reached without success. cout << "\n\nERROR: Model name " << search << " was not found in the architecture.\n" ; exit(1); - } else { - if (verbose_mode){ - cout << "\n\t\t>> Model " << search << " identified.\n" ; - } - temp_subckt.model_type = cur_model; //initialize model_type - model_count[cur_model->index]++; //increment the instance count of the model - temp_subckt.input_cnxns.clear(); //reset the input and output maps - temp_subckt.output_cnxns.clear(); - - //map the input ports of the model read from the architecture - //to the corresponding external pin as per the vqm - init_subckt_map( &(temp_subckt.input_cnxns), - temp_subckt.model_type->inputs, - vqm_node, &vqm_ports_found); - //vqm_ports_found entries are set as ports are mapped - - VTR_ASSERT(!temp_subckt.input_cnxns.empty()); //all blocks must have an input - - //now map the output ports - init_subckt_map( &(temp_subckt.output_cnxns), - temp_subckt.model_type->outputs, - vqm_node, &vqm_ports_found); - //vqm_ports_found entries are set as ports are mapped - - VTR_ASSERT(!temp_subckt.output_cnxns.empty()); //all blocks must have an output - - //Pass through parameters - for (int iparam = 0; iparam < vqm_node->number_of_params; ++iparam) { - t_subckt_param_attr param; - t_node_parameter* vqm_param = vqm_node->array_of_params[iparam]; - param.name = vqm_param->name; - - if (vqm_param->type == NODE_PARAMETER_STRING) { - param.value = vqm_param->value.string_value; - } else { - VTR_ASSERT(vqm_param->type == NODE_PARAMETER_INTEGER); - param.value = std::to_string(vqm_param->value.integer_value); - } - temp_subckt.params.push_back(param); + } + + if (verbose_mode){ + cout << "\n\t\t>> Model " << search << " identified.\n" ; + } + temp_subckt.model_type = model_id; //initialize model_type + model_count[model_id]++; //increment the instance count of the model + temp_subckt.input_cnxns.clear(); //reset the input and output maps + temp_subckt.output_cnxns.clear(); + + const t_model& model = models.get_model(model_id); + + //map the input ports of the model read from the architecture + //to the corresponding external pin as per the vqm + init_subckt_map( &(temp_subckt.input_cnxns), + model.inputs, + vqm_node, &vqm_ports_found); + //vqm_ports_found entries are set as ports are mapped + + VTR_ASSERT(!temp_subckt.input_cnxns.empty()); //all blocks must have an input + + //now map the output ports + init_subckt_map( &(temp_subckt.output_cnxns), + model.outputs, + vqm_node, &vqm_ports_found); + //vqm_ports_found entries are set as ports are mapped + + VTR_ASSERT(!temp_subckt.output_cnxns.empty()); //all blocks must have an output + + //Pass through parameters + for (int iparam = 0; iparam < vqm_node->number_of_params; ++iparam) { + t_subckt_param_attr param; + t_node_parameter* vqm_param = vqm_node->array_of_params[iparam]; + param.name = vqm_param->name; + + if (vqm_param->type == NODE_PARAMETER_STRING) { + param.value = vqm_param->value.string_value; + } else { + VTR_ASSERT(vqm_param->type == NODE_PARAMETER_INTEGER); + param.value = std::to_string(vqm_param->value.integer_value); } + temp_subckt.params.push_back(param); + } - //Verify that all ports specified in the VQM node were successfully mapped before - //committing the subcircuit to the BLIF structure. + //Verify that all ports specified in the VQM node were successfully mapped before + //committing the subcircuit to the BLIF structure. + if (verbose_mode){ + cout << "\t\tVQM Port Verification:\n" ; + } + for (int i = 0; i < vqm_node->number_of_ports; i++){ + /* The mapping process maps all ports of the architecture either to the open port or + * a port in the VQM. If a port appeared in the VQM and not in the + * architecture, the association's corresponding entry in vqm_ports_found would + * remain T_FALSE through the mapping process. + */ if (verbose_mode){ - cout << "\t\tVQM Port Verification:\n" ; - } - for (int i = 0; i < vqm_node->number_of_ports; i++){ - /* The mapping process maps all ports of the architecture either to the open port or - * a port in the VQM. If a port appeared in the VQM and not in the - * architecture, the association's corresponding entry in vqm_ports_found would - * remain T_FALSE through the mapping process. - */ - if (verbose_mode){ - //Print whether the port was mapped explicitly - //Prints "Port (port)[index] = [ mapped | unmapped ]" - cout << "\t\t\tPort " << vqm_node->array_of_ports[i]->port_name ; - - if (vqm_node->array_of_ports[i]->port_index >= 0){ - cout << "[" << vqm_node->array_of_ports[i]->port_index << "]" ; - } + //Print whether the port was mapped explicitly + //Prints "Port (port)[index] = [ mapped | unmapped ]" + cout << "\t\t\tPort " << vqm_node->array_of_ports[i]->port_name ; - cout <<"= " << ((vqm_ports_found[i])? "mapped":"unmapped") << endl; + if (vqm_node->array_of_ports[i]->port_index >= 0){ + cout << "[" << vqm_node->array_of_ports[i]->port_index << "]" ; } - if (vqm_ports_found[i] == T_FALSE){ - cout << "\n\nERROR: Port " << vqm_node->array_of_ports[i]->port_name ; - if (vqm_node->array_of_ports[i]->port_index >= 0){ - cout << "[" << vqm_node->array_of_ports[i]->port_index << "]" ; - } - cout << " not found in architecture for " << search << endl ; - exit(1); - } + cout <<"= " << ((vqm_ports_found[i])? "mapped":"unmapped") << endl; } - if (verbose_mode){ - cout << endl ; + + if (vqm_ports_found[i] == T_FALSE){ + cout << "\n\nERROR: Port " << vqm_node->array_of_ports[i]->port_name ; + if (vqm_node->array_of_ports[i]->port_index >= 0){ + cout << "[" << vqm_node->array_of_ports[i]->port_index << "]" ; + } + cout << " not found in architecture for " << search << endl ; + exit(1); } - //push the temp_subckt into the subckt vector - blif_subckts->push_back(temp_subckt); } + if (verbose_mode){ + cout << endl ; + } + //push the temp_subckt into the subckt vector + blif_subckts->push_back(temp_subckt); } //============================================================================================ //============================================================================================ -void push_node_atomize (t_node* /*vqm_node*/, t_model* /*arch_models*/, scktvec* /*blif_subckts*/ /*, FILE* dict*/){ +void push_node_atomize (t_node* /*vqm_node*/, const LogicalModels& /*models*/, scktvec* /*blif_subckts*/ /*, FILE* dict*/){ /* Interprets each VQM block and its parameter set, then expands that block into its smaller * atomic constituents based on a "Dictionary" document. * @@ -1336,7 +1319,7 @@ void dump_blif (char* blif_file, t_blif_model* main_model, t_arch* arch, t_boole blif_out << "\n#MAIN MODEL\n" ; //completely dump the top-level model - dump_main_model(main_model, blif_out, print_unused_subckt_pins_local, eblif_format, T_FALSE); + dump_main_model(main_model, blif_out, arch->models, print_unused_subckt_pins_local, eblif_format, T_FALSE); //now dump the subckt models from the architecture //that were used in the vqm @@ -1352,7 +1335,7 @@ void dump_blif (char* blif_file, t_blif_model* main_model, t_arch* arch, t_boole //============================================================================================ //============================================================================================ -void dump_main_model(t_blif_model* model, ofstream& outfile, t_boolean print_unused_subckt_pins_local, t_boolean eblif_format_local, t_boolean debug){ +void dump_main_model(t_blif_model* model, ofstream& outfile, const LogicalModels& models, t_boolean print_unused_subckt_pins_local, t_boolean eblif_format_local, t_boolean debug){ /* Dumps information stored in a model structure in proper BLIF syntax. * * ARGUMENTS @@ -1408,7 +1391,7 @@ void dump_main_model(t_blif_model* model, ofstream& outfile, t_boolean print_unu //Print Subcircuit Variable information if (model->subckts.size() > 0){ - dump_subckts(outfile, &(model->subckts), print_unused_subckt_pins_local, eblif_format_local, debug); + dump_subckts(outfile, &(model->subckts), models, print_unused_subckt_pins_local, eblif_format_local, debug); } //Printing the model data is complete. @@ -1718,7 +1701,7 @@ void dump_luts (ofstream& outfile, lutvec* blif_luts, t_boolean eblif_format_loc //============================================================================================ //============================================================================================ -void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pins, t_boolean eblif_format_local, t_boolean debug){ +void dump_subckts(ofstream& outfile, scktvec* subckts, const LogicalModels& models, t_boolean print_unused_pins, t_boolean eblif_format_local, t_boolean debug){ /* Traverse the subcircuit vector, printing the names and connections * of each instantiated subcircuit in the main model. * @@ -1738,15 +1721,16 @@ void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pi for(int i = 0; i < limit; i++){ //print each subcircuit's name, port, and connectivity information temp_subckt = &(subckts->at(i)); + const t_model& model_type = models.get_model(temp_subckt->model_type); if (debug){ outfile << "\nSubcircuit Number: " << i << endl; outfile << "Instance Name: " << temp_subckt->inst_name << endl; - outfile << "Type: " << temp_subckt->model_type->name << endl ; + outfile << "Type: " << model_type.name << endl ; } else { if (!eblif_format_local) { outfile << "\n# Subckt " << i << ": " << temp_subckt->inst_name << " \n"; } - outfile << ".subckt " << temp_subckt->model_type->name << " \\\n" ; + outfile << ".subckt " << model_type.name << " \\\n" ; } @@ -1754,13 +1738,13 @@ void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pi outfile << "Input Map:\n" ; } - size_t num_print_output_pins = count_print_pins(temp_subckt->model_type->outputs, &(temp_subckt->output_cnxns), print_unused_pins); + size_t num_print_output_pins = count_print_pins(model_type.outputs, &(temp_subckt->output_cnxns), print_unused_pins); //dump the input map containing connectivity data bool last = (num_print_output_pins == 0); dump_subckt_map(outfile, &(temp_subckt->input_cnxns), - temp_subckt->model_type->inputs, + model_type.inputs, temp_subckt->inst_name.c_str(), "input", i, print_unused_pins, @@ -1775,7 +1759,7 @@ void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pi last = true; dump_subckt_map(outfile, &(temp_subckt->output_cnxns), - temp_subckt->model_type->outputs, + model_type.outputs, temp_subckt->inst_name.c_str(), "output", i, print_unused_pins, @@ -1925,7 +1909,7 @@ size_t count_print_pins(t_model_ports* temp_port, portmap* map, t_boolean print_ //============================================================================================ //============================================================================================ -void dump_subckt_models(t_model* temp_model, ofstream& outfile, t_boolean debug){ +void dump_subckt_models(const LogicalModels& models, ofstream& outfile, t_boolean debug){ /* Cycles through all models declared in the architecture * and dumps the ones used by the VQM as blackbox models * at the end of the .blif file @@ -1938,27 +1922,29 @@ void dump_subckt_models(t_model* temp_model, ofstream& outfile, t_boolean debug) * flag to indicate whether to print in DEBUG or BLIF format. */ unsigned long total_block_count = 0; - while(temp_model){ - if (model_count[temp_model->index] > 0){ - //Count the number of blocks - total_block_count += model_count[temp_model->index]; - - //dump all .subckt models declared in the architecture - //Use the model_count array to only output the models that were used. - if (!debug){ - cout << "\t>> Introduced " << model_count[temp_model->index] << " instances of blackbox " << temp_model->name << endl; - } - outfile << ((debug)? "\n Model: " : "\n.model ") << temp_model->name << endl ; - - outfile << ((debug)? "Inputs:\n" : ".inputs \\\n") ; //cycle through all inputs - dump_subckt_portlist(outfile, temp_model->inputs, " ", debug); + for (LogicalModelId model_id : models.user_models()) { + if (model_count[model_id] == 0) + continue; + + //Count the number of blocks + total_block_count += model_count[model_id]; + + const t_model& model = models.get_model(model_id); - outfile << ((debug)? "Outputs:\n" : ".outputs \\\n") ; //cycle through all outputs - dump_subckt_portlist(outfile, temp_model->outputs, " ", debug); + //dump all .subckt models declared in the architecture + //Use the model_count array to only output the models that were used. + if (!debug){ + cout << "\t>> Introduced " << model_count[model_id] << " instances of blackbox " << model.name << endl; + } + outfile << ((debug)? "\n Model: " : "\n.model ") << model.name << endl ; + + outfile << ((debug)? "Inputs:\n" : ".inputs \\\n") ; //cycle through all inputs + dump_subckt_portlist(outfile, model.inputs, " ", debug); + + outfile << ((debug)? "Outputs:\n" : ".outputs \\\n") ; //cycle through all outputs + dump_subckt_portlist(outfile, model.outputs, " ", debug); - outfile << ((debug)? "\nEND MODEL\n" : ".blackbox\n.end\n") ; - } - temp_model = temp_model->next; + outfile << ((debug)? "\nEND MODEL\n" : ".blackbox\n.end\n") ; } cout << "\t>> Total Block Count: " << total_block_count; } @@ -2013,8 +1999,8 @@ void all_data_cleanup(){ */ vqm_data_cleanup();//found in ../LIB/vqm_dll.h, frees parser-allocated memory - free(model_count); - + model_count.clear(); + return; } @@ -2253,7 +2239,7 @@ void echo_module_nodes (ofstream& outfile, t_module* module){ //============================================================================================ void echo_blif_model (char* echo_file, const char* vqm_filename, - t_blif_model* my_model, t_model* temp_model) { + t_blif_model* my_model, const LogicalModels& models) { /* Prints all model data into a .txt for debugging * Used to ensure correct population of the parser data into the model. * @@ -2278,14 +2264,14 @@ void echo_blif_model (char* echo_file, const char* vqm_filename, model_out << "\n\tMAIN MODEL\n" ; //completely dump the top-level model in DEBUG format - dump_main_model(my_model, model_out, T_TRUE, T_TRUE, T_TRUE); + dump_main_model(my_model, model_out, models, T_TRUE, T_TRUE, T_TRUE); model_out << "\n\tSUBCKT MODELS\n"; //now dump the subckt models from the architecture //that were used in the VQM file, in DEBUG format. if (my_model->subckts.size() > 0){ - dump_subckt_models(temp_model, model_out, T_TRUE); + dump_subckt_models(models, model_out, T_TRUE); } // Close file. diff --git a/utils/vqm2blif/test/netlists/carpat/carpat_stratixiv_arch_timing.blif b/utils/vqm2blif/test/netlists/carpat/carpat_stratixiv_arch_timing.blif index 90a7e92bcfa..190d8cf395b 100644 --- a/utils/vqm2blif/test/netlists/carpat/carpat_stratixiv_arch_timing.blif +++ b/utils/vqm2blif/test/netlists/carpat/carpat_stratixiv_arch_timing.blif @@ -1,4 +1,4 @@ -#BLIF OUTPUT: titan_release_dev/benchmarks/other_benchmarks/carpat/netlists/carpat_stratixiv_arch_timing.blif +#BLIF OUTPUT: ./utils/vqm2blif/test/scripts/../netlists/carpat/carpat_stratixiv.golden.blif #MAIN MODEL @@ -264730,87 +264730,497 @@ #SUBCKT MODELS -.model stratixiv_pll.opmode{normal} +.model stratixiv_lcell_comb .inputs \ - scandata \ - scanclkena \ - scanclk \ - phaseupdown \ - phasestep \ - phasecounterselect[0] \ - phasecounterselect[1] \ - phasecounterselect[2] \ - phasecounterselect[3] \ - pfdena \ - inclk \ - fbin \ - configupdate \ - clkswitch \ - areset + sharein \ + cin \ + datag \ + dataf \ + datae \ + datad \ + datac \ + datab \ + dataa .outputs \ - vcounderrange \ - vcooverrange \ - scandone \ - scandataout \ - phasedone \ - locked \ - fbout \ - clkbad[0] \ - clkbad[1] \ - clk[0] \ - clk[1] \ - clk[2] \ - clk[3] \ - clk[4] \ - clk[5] \ - clk[6] \ - clk[7] \ - clk[8] \ - clk[9] \ - activeclock + shareout \ + cout \ + sumout \ + combout .blackbox .end -.model stratixiv_io_obuf +.model dffeas .inputs \ - parallelterminationcontrol[0] \ - parallelterminationcontrol[1] \ - parallelterminationcontrol[2] \ - parallelterminationcontrol[3] \ - parallelterminationcontrol[4] \ - parallelterminationcontrol[5] \ - parallelterminationcontrol[6] \ - parallelterminationcontrol[7] \ - parallelterminationcontrol[8] \ - parallelterminationcontrol[9] \ - parallelterminationcontrol[10] \ - parallelterminationcontrol[11] \ - parallelterminationcontrol[12] \ - parallelterminationcontrol[13] \ - seriesterminationcontrol[0] \ - seriesterminationcontrol[1] \ - seriesterminationcontrol[2] \ - seriesterminationcontrol[3] \ - seriesterminationcontrol[4] \ - seriesterminationcontrol[5] \ - seriesterminationcontrol[6] \ - seriesterminationcontrol[7] \ - seriesterminationcontrol[8] \ - seriesterminationcontrol[9] \ - seriesterminationcontrol[10] \ - seriesterminationcontrol[11] \ - seriesterminationcontrol[12] \ - seriesterminationcontrol[13] \ - dynamicterminationcontrol \ - oe \ - i + devpor \ + devclrn \ + d \ + sclr \ + sload \ + aload \ + asdata \ + clrn \ + prn \ + ena \ + clk .outputs \ - obar \ - o + q .blackbox .end -.model stratixiv_mac_out.opmode{double}.input_type{reg}.output_type{comb} +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddr[3] \ + portbaddr[4] \ + portbaddr[5] \ + portbaddr[6] \ + portbaddr[7] \ + portbaddr[8] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddr[6] \ + portaaddr[7] \ + portaaddr[8] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddr[3] \ + portbaddr[4] \ + portbaddr[5] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddr[3] \ + portbaddr[4] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddr[3] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{10} +.inputs \ + clk_portaout \ + clk_portain \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddr[6] \ + portaaddr[7] \ + portaaddr[8] \ + portaaddr[9] \ + portaaddrstall \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + portare \ + clr0 \ + clr1 +.outputs \ + portadataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{9} +.inputs \ + clk_portaout \ + clk_portain \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddr[6] \ + portaaddr[7] \ + portaaddr[8] \ + portaaddrstall \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + portare \ + clr0 \ + clr1 +.outputs \ + portadataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{1} +.inputs \ + clk_portaout \ + clk_portain \ + portaaddr \ + portaaddrstall \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + portare \ + clr0 \ + clr1 +.outputs \ + portadataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{0} +.inputs \ + clk_portaout \ + clk_portain \ + portaaddr \ + portaaddrstall \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + portare \ + clr0 \ + clr1 +.outputs \ + portadataout +.blackbox +.end + +.model stratixiv_mac_mult.input_type{comb} +.inputs \ + devpor \ + devclrn \ + aclr[0] \ + aclr[1] \ + aclr[2] \ + aclr[3] \ + ena[0] \ + ena[1] \ + ena[2] \ + ena[3] \ + signb \ + signa \ + datab[0] \ + datab[1] \ + datab[2] \ + datab[3] \ + datab[4] \ + datab[5] \ + datab[6] \ + datab[7] \ + datab[8] \ + datab[9] \ + datab[10] \ + datab[11] \ + datab[12] \ + datab[13] \ + datab[14] \ + datab[15] \ + datab[16] \ + datab[17] \ + dataa[0] \ + dataa[1] \ + dataa[2] \ + dataa[3] \ + dataa[4] \ + dataa[5] \ + dataa[6] \ + dataa[7] \ + dataa[8] \ + dataa[9] \ + dataa[10] \ + dataa[11] \ + dataa[12] \ + dataa[13] \ + dataa[14] \ + dataa[15] \ + dataa[16] \ + dataa[17] +.outputs \ + dataout[0] \ + dataout[1] \ + dataout[2] \ + dataout[3] \ + dataout[4] \ + dataout[5] \ + dataout[6] \ + dataout[7] \ + dataout[8] \ + dataout[9] \ + dataout[10] \ + dataout[11] \ + dataout[12] \ + dataout[13] \ + dataout[14] \ + dataout[15] \ + dataout[16] \ + dataout[17] \ + dataout[18] \ + dataout[19] \ + dataout[20] \ + dataout[21] \ + dataout[22] \ + dataout[23] \ + dataout[24] \ + dataout[25] \ + dataout[26] \ + dataout[27] \ + dataout[28] \ + dataout[29] \ + dataout[30] \ + dataout[31] \ + dataout[32] \ + dataout[33] \ + dataout[34] \ + dataout[35] \ + scanouta[0] \ + scanouta[1] \ + scanouta[2] \ + scanouta[3] \ + scanouta[4] \ + scanouta[5] \ + scanouta[6] \ + scanouta[7] \ + scanouta[8] \ + scanouta[9] \ + scanouta[10] \ + scanouta[11] \ + scanouta[12] \ + scanouta[13] \ + scanouta[14] \ + scanouta[15] \ + scanouta[16] \ + scanouta[17] +.blackbox +.end + +.model stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{comb} .inputs \ devpor \ devclrn \ @@ -264818,7 +265228,6 @@ aclr[1] \ aclr[2] \ aclr[3] \ - clk \ ena[0] \ ena[1] \ ena[2] \ @@ -265025,11 +265434,28 @@ dataout[51] \ dataout[52] \ dataout[53] \ - dataout[54] + dataout[54] \ + dataout[55] \ + dataout[56] \ + dataout[57] \ + dataout[58] \ + dataout[59] \ + dataout[60] \ + dataout[61] \ + dataout[62] \ + dataout[63] \ + dataout[64] \ + dataout[65] \ + dataout[66] \ + dataout[67] \ + dataout[68] \ + dataout[69] \ + dataout[70] \ + dataout[71] .blackbox .end -.model stratixiv_mac_out.opmode{double}.input_type{comb}.output_type{comb} +.model stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{reg} .inputs \ devpor \ devclrn \ @@ -265037,6 +265463,7 @@ aclr[1] \ aclr[2] \ aclr[3] \ + clk \ ena[0] \ ena[1] \ ena[2] \ @@ -265243,11 +265670,28 @@ dataout[51] \ dataout[52] \ dataout[53] \ - dataout[54] + dataout[54] \ + dataout[55] \ + dataout[56] \ + dataout[57] \ + dataout[58] \ + dataout[59] \ + dataout[60] \ + dataout[61] \ + dataout[62] \ + dataout[63] \ + dataout[64] \ + dataout[65] \ + dataout[66] \ + dataout[67] \ + dataout[68] \ + dataout[69] \ + dataout[70] \ + dataout[71] .blackbox .end -.model stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{reg} +.model stratixiv_mac_out.opmode{double}.input_type{comb}.output_type{comb} .inputs \ devpor \ devclrn \ @@ -265255,7 +265699,6 @@ aclr[1] \ aclr[2] \ aclr[3] \ - clk \ ena[0] \ ena[1] \ ena[2] \ @@ -265462,28 +265905,11 @@ dataout[51] \ dataout[52] \ dataout[53] \ - dataout[54] \ - dataout[55] \ - dataout[56] \ - dataout[57] \ - dataout[58] \ - dataout[59] \ - dataout[60] \ - dataout[61] \ - dataout[62] \ - dataout[63] \ - dataout[64] \ - dataout[65] \ - dataout[66] \ - dataout[67] \ - dataout[68] \ - dataout[69] \ - dataout[70] \ - dataout[71] + dataout[54] .blackbox .end -.model stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{comb} +.model stratixiv_mac_out.opmode{double}.input_type{reg}.output_type{comb} .inputs \ devpor \ devclrn \ @@ -265491,6 +265917,7 @@ aclr[1] \ aclr[2] \ aclr[3] \ + clk \ ena[0] \ ena[1] \ ena[2] \ @@ -265697,513 +266124,86 @@ dataout[51] \ dataout[52] \ dataout[53] \ - dataout[54] \ - dataout[55] \ - dataout[56] \ - dataout[57] \ - dataout[58] \ - dataout[59] \ - dataout[60] \ - dataout[61] \ - dataout[62] \ - dataout[63] \ - dataout[64] \ - dataout[65] \ - dataout[66] \ - dataout[67] \ - dataout[68] \ - dataout[69] \ - dataout[70] \ - dataout[71] -.blackbox -.end - -.model stratixiv_mac_mult.input_type{comb} -.inputs \ - devpor \ - devclrn \ - aclr[0] \ - aclr[1] \ - aclr[2] \ - aclr[3] \ - ena[0] \ - ena[1] \ - ena[2] \ - ena[3] \ - signb \ - signa \ - datab[0] \ - datab[1] \ - datab[2] \ - datab[3] \ - datab[4] \ - datab[5] \ - datab[6] \ - datab[7] \ - datab[8] \ - datab[9] \ - datab[10] \ - datab[11] \ - datab[12] \ - datab[13] \ - datab[14] \ - datab[15] \ - datab[16] \ - datab[17] \ - dataa[0] \ - dataa[1] \ - dataa[2] \ - dataa[3] \ - dataa[4] \ - dataa[5] \ - dataa[6] \ - dataa[7] \ - dataa[8] \ - dataa[9] \ - dataa[10] \ - dataa[11] \ - dataa[12] \ - dataa[13] \ - dataa[14] \ - dataa[15] \ - dataa[16] \ - dataa[17] -.outputs \ - dataout[0] \ - dataout[1] \ - dataout[2] \ - dataout[3] \ - dataout[4] \ - dataout[5] \ - dataout[6] \ - dataout[7] \ - dataout[8] \ - dataout[9] \ - dataout[10] \ - dataout[11] \ - dataout[12] \ - dataout[13] \ - dataout[14] \ - dataout[15] \ - dataout[16] \ - dataout[17] \ - dataout[18] \ - dataout[19] \ - dataout[20] \ - dataout[21] \ - dataout[22] \ - dataout[23] \ - dataout[24] \ - dataout[25] \ - dataout[26] \ - dataout[27] \ - dataout[28] \ - dataout[29] \ - dataout[30] \ - dataout[31] \ - dataout[32] \ - dataout[33] \ - dataout[34] \ - dataout[35] \ - scanouta[0] \ - scanouta[1] \ - scanouta[2] \ - scanouta[3] \ - scanouta[4] \ - scanouta[5] \ - scanouta[6] \ - scanouta[7] \ - scanouta[8] \ - scanouta[9] \ - scanouta[10] \ - scanouta[11] \ - scanouta[12] \ - scanouta[13] \ - scanouta[14] \ - scanouta[15] \ - scanouta[16] \ - scanouta[17] -.blackbox -.end - -.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{0} -.inputs \ - clk_portaout \ - clk_portain \ - portaaddr \ - portaaddrstall \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - portare \ - clr0 \ - clr1 -.outputs \ - portadataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{1} -.inputs \ - clk_portaout \ - clk_portain \ - portaaddr \ - portaaddrstall \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - portare \ - clr0 \ - clr1 -.outputs \ - portadataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{9} -.inputs \ - clk_portaout \ - clk_portain \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddr[6] \ - portaaddr[7] \ - portaaddr[8] \ - portaaddrstall \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - portare \ - clr0 \ - clr1 -.outputs \ - portadataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{10} -.inputs \ - clk_portaout \ - clk_portain \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddr[6] \ - portaaddr[7] \ - portaaddr[8] \ - portaaddr[9] \ - portaaddrstall \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - portare \ - clr0 \ - clr1 -.outputs \ - portadataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddr[3] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddr[3] \ - portbaddr[4] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddr[3] \ - portbaddr[4] \ - portbaddr[5] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddr[3] \ - portbaddr[4] \ - portbaddr[5] \ - portbaddr[6] \ - portbaddr[7] \ - portbaddr[8] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddr[6] \ - portaaddr[7] \ - portaaddr[8] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout + dataout[54] .blackbox .end -.model dffeas +.model stratixiv_io_obuf .inputs \ - devpor \ - devclrn \ - d \ - sclr \ - sload \ - aload \ - asdata \ - clrn \ - prn \ - ena \ - clk + parallelterminationcontrol[0] \ + parallelterminationcontrol[1] \ + parallelterminationcontrol[2] \ + parallelterminationcontrol[3] \ + parallelterminationcontrol[4] \ + parallelterminationcontrol[5] \ + parallelterminationcontrol[6] \ + parallelterminationcontrol[7] \ + parallelterminationcontrol[8] \ + parallelterminationcontrol[9] \ + parallelterminationcontrol[10] \ + parallelterminationcontrol[11] \ + parallelterminationcontrol[12] \ + parallelterminationcontrol[13] \ + seriesterminationcontrol[0] \ + seriesterminationcontrol[1] \ + seriesterminationcontrol[2] \ + seriesterminationcontrol[3] \ + seriesterminationcontrol[4] \ + seriesterminationcontrol[5] \ + seriesterminationcontrol[6] \ + seriesterminationcontrol[7] \ + seriesterminationcontrol[8] \ + seriesterminationcontrol[9] \ + seriesterminationcontrol[10] \ + seriesterminationcontrol[11] \ + seriesterminationcontrol[12] \ + seriesterminationcontrol[13] \ + dynamicterminationcontrol \ + oe \ + i .outputs \ - q + obar \ + o .blackbox .end -.model stratixiv_lcell_comb +.model stratixiv_pll.opmode{normal} .inputs \ - sharein \ - cin \ - datag \ - dataf \ - datae \ - datad \ - datac \ - datab \ - dataa + scandata \ + scanclkena \ + scanclk \ + phaseupdown \ + phasestep \ + phasecounterselect[0] \ + phasecounterselect[1] \ + phasecounterselect[2] \ + phasecounterselect[3] \ + pfdena \ + inclk \ + fbin \ + configupdate \ + clkswitch \ + areset .outputs \ - shareout \ - cout \ - sumout \ - combout + vcounderrange \ + vcooverrange \ + scandone \ + scandataout \ + phasedone \ + locked \ + fbout \ + clkbad[0] \ + clkbad[1] \ + clk[0] \ + clk[1] \ + clk[2] \ + clk[3] \ + clk[4] \ + clk[5] \ + clk[6] \ + clk[7] \ + clk[8] \ + clk[9] \ + activeclock .blackbox .end diff --git a/utils/vqm2blif/test/netlists/murax/murax_stratixiv_arch_timing.blif b/utils/vqm2blif/test/netlists/murax/murax_stratixiv_arch_timing.blif index 8ae3d5e3def..5d4fad42dde 100644 --- a/utils/vqm2blif/test/netlists/murax/murax_stratixiv_arch_timing.blif +++ b/utils/vqm2blif/test/netlists/murax/murax_stratixiv_arch_timing.blif @@ -1,4 +1,4 @@ -#BLIF OUTPUT: titan_release_dev/benchmarks/other_benchmarks/murax/netlists/murax_stratixiv_arch_timing.blif +#BLIF OUTPUT: ./utils/vqm2blif/test/scripts/../netlists/murax/murax_stratixiv.golden.blif #MAIN MODEL @@ -18187,12 +18187,55 @@ #SUBCKT MODELS -.model stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4} +.model stratixiv_lcell_comb +.inputs \ + sharein \ + cin \ + datag \ + dataf \ + datae \ + datad \ + datac \ + datab \ + dataa +.outputs \ + shareout \ + cout \ + sumout \ + combout +.blackbox +.end + +.model dffeas +.inputs \ + devpor \ + devclrn \ + d \ + sclr \ + sload \ + aload \ + asdata \ + clrn \ + prn \ + ena \ + clk +.outputs \ + q +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10} .inputs \ portbaddr[0] \ portbaddr[1] \ portbaddr[2] \ portbaddr[3] \ + portbaddr[4] \ + portbaddr[5] \ + portbaddr[6] \ + portbaddr[7] \ + portbaddr[8] \ + portbaddr[9] \ portbaddrstall \ portawe \ clk_portbout \ @@ -18201,6 +18244,12 @@ portaaddr[1] \ portaaddr[2] \ portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddr[6] \ + portaaddr[7] \ + portaaddr[8] \ + portaaddr[9] \ portaaddrstall \ clk_portaout \ ena1 \ @@ -18271,18 +18320,12 @@ .blackbox .end -.model stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10} +.model stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4} .inputs \ portbaddr[0] \ portbaddr[1] \ portbaddr[2] \ portbaddr[3] \ - portbaddr[4] \ - portbaddr[5] \ - portbaddr[6] \ - portbaddr[7] \ - portbaddr[8] \ - portbaddr[9] \ portbaddrstall \ portawe \ clk_portbout \ @@ -18291,12 +18334,6 @@ portaaddr[1] \ portaaddr[2] \ portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddr[6] \ - portaaddr[7] \ - portaaddr[8] \ - portaaddr[9] \ portaaddrstall \ clk_portaout \ ena1 \ @@ -18323,40 +18360,3 @@ portbdataout .blackbox .end - -.model dffeas -.inputs \ - devpor \ - devclrn \ - d \ - sclr \ - sload \ - aload \ - asdata \ - clrn \ - prn \ - ena \ - clk -.outputs \ - q -.blackbox -.end - -.model stratixiv_lcell_comb -.inputs \ - sharein \ - cin \ - datag \ - dataf \ - datae \ - datad \ - datac \ - datab \ - dataa -.outputs \ - shareout \ - cout \ - sumout \ - combout -.blackbox -.end diff --git a/utils/vqm2blif/test/netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv_arch_timing.blif b/utils/vqm2blif/test/netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv_arch_timing.blif index a7ed3f84596..cab3e1222dc 100644 --- a/utils/vqm2blif/test/netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv_arch_timing.blif +++ b/utils/vqm2blif/test/netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv_arch_timing.blif @@ -1,4 +1,4 @@ -#BLIF OUTPUT: titan_release_dev/benchmarks/other_benchmarks/ucsb_152_tap_fir/netlists/ucsb_152_tap_fir_stratixiv_arch_timing.blif +#BLIF OUTPUT: ./utils/vqm2blif/test/scripts/../netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv.golden.blif #MAIN MODEL @@ -132420,24 +132420,6 @@ #SUBCKT MODELS -.model dffeas -.inputs \ - devpor \ - devclrn \ - d \ - sclr \ - sload \ - aload \ - asdata \ - clrn \ - prn \ - ena \ - clk -.outputs \ - q -.blackbox -.end - .model stratixiv_lcell_comb .inputs \ sharein \ @@ -132456,3 +132438,21 @@ combout .blackbox .end + +.model dffeas +.inputs \ + devpor \ + devclrn \ + d \ + sclr \ + sload \ + aload \ + asdata \ + clrn \ + prn \ + ena \ + clk +.outputs \ + q +.blackbox +.end diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 542269395c5..281a40b67a0 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -1,7 +1,5 @@ #include "timing_reports.h" -#include "vtr_log.h" - #include "tatum/TimingReporter.hpp" #include "vpr_types.h" @@ -20,10 +18,11 @@ void generate_setup_timing_stats(const std::string& prefix, const BlkLocRegistry& blk_loc_registry) { auto& timing_ctx = g_vpr_ctx.timing(); auto& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; print_setup_timing_summary(*timing_ctx.constraints, *timing_info.setup_analyzer(), "Final ", analysis_opts.write_timing_summary); - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); @@ -45,10 +44,11 @@ void generate_hold_timing_stats(const std::string& prefix, const BlkLocRegistry& blk_loc_registry) { auto& timing_ctx = g_vpr_ctx.timing(); auto& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; print_hold_timing_summary(*timing_ctx.constraints, *timing_info.hold_analyzer(), "Final "); - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); diff --git a/vpr/src/analytical_place/analytical_placement_flow.cpp b/vpr/src/analytical_place/analytical_placement_flow.cpp index 853f4cb2f02..1b0f3885559 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.cpp +++ b/vpr/src/analytical_place/analytical_placement_flow.cpp @@ -159,7 +159,7 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { const UserPlaceConstraints& constraints = g_vpr_ctx.floorplanning().constraints; // Run the prepacker - const Prepacker prepacker(atom_nlist, device_ctx.logical_block_types); + const Prepacker prepacker(atom_nlist, device_ctx.arch->models, device_ctx.logical_block_types); // Create the ap netlist from the atom netlist using the result from the // prepacker. diff --git a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp index c99aaf29339..d9978cdad82 100644 --- a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp +++ b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp @@ -25,9 +25,9 @@ * TODO: This will be made more complicated later. Models may be weighted based * on some factors. */ -static float get_model_mass(const t_model* model) { +static float get_model_mass(LogicalModelId model_id) { // Currently, all models have a mass of one. - (void)model; + (void)model_id; return 1.f; } @@ -69,10 +69,9 @@ static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type) { PrimitiveVector capacity; // If this is a leaf / primitive, create the base PrimitiveVector capacity. if (pb_type->num_modes == 0) { - const t_model* model = pb_type->model; - VTR_ASSERT(model != nullptr); - VTR_ASSERT_DEBUG(model->index >= 0); - capacity.add_val_to_dim(get_model_mass(model), model->index); + LogicalModelId model_id = pb_type->model_id; + VTR_ASSERT(model_id.is_valid()); + capacity.add_val_to_dim(get_model_mass(model_id), (size_t)model_id); return capacity; } // For now, we simply mix the capacities of modes by taking the max of each @@ -167,9 +166,9 @@ static PrimitiveVector calc_block_mass(APBlockId blk_id, // safely be ignored. if (!atom_blk_id.is_valid()) continue; - const t_model* model = atom_netlist.block_model(atom_blk_id); - VTR_ASSERT_DEBUG(model->index >= 0); - mass.add_val_to_dim(get_model_mass(model), model->index); + LogicalModelId model_id = atom_netlist.block_model(atom_blk_id); + VTR_ASSERT(model_id.is_valid()); + mass.add_val_to_dim(get_model_mass(model_id), (size_t)model_id); } return mass; } @@ -182,38 +181,22 @@ static void print_capacities(const std::vector& logical_block_t const std::vector& physical_tile_type_capacities, const std::vector& logical_block_types, const std::vector& physical_tile_types) { - // Get a linear list of all models. - // TODO: I do not like using the global context here, but these models - // should be stable in VTR. If they were stored better, we may be - // able to pass them in. - std::vector all_models; - t_model* curr_model = g_vpr_ctx.device().arch->models; - while (curr_model != nullptr) { - if (curr_model->index >= (int)all_models.size()) - all_models.resize(curr_model->index + 1); - all_models[curr_model->index] = curr_model; - curr_model = curr_model->next; - } - curr_model = g_vpr_ctx.device().arch->model_library; - while (curr_model != nullptr) { - if (curr_model->index >= (int)all_models.size()) - all_models.resize(curr_model->index + 1); - all_models[curr_model->index] = curr_model; - curr_model = curr_model->next; - } + // TODO: Pass these into this function. + const LogicalModels& models = g_vpr_ctx.device().arch->models; + // Print the capacities. VTR_LOG("Logical Block Type Capacities:\n"); VTR_LOG("------------------------------\n"); VTR_LOG("name\t"); - for (t_model* model : all_models) { - VTR_LOG("%s\t", model->name); + for (LogicalModelId model_id : models.all_models()) { + VTR_LOG("%s\t", models.get_model(model_id).name); } VTR_LOG("\n"); for (const t_logical_block_type& block_type : logical_block_types) { const PrimitiveVector& capacity = logical_block_type_capacities[block_type.index]; VTR_LOG("%s\t", block_type.name.c_str()); - for (t_model* model : all_models) { - VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); + for (LogicalModelId model_id : models.all_models()) { + VTR_LOG("%.2f\t", capacity.get_dim_val((size_t)model_id)); } VTR_LOG("\n"); } @@ -221,15 +204,15 @@ static void print_capacities(const std::vector& logical_block_t VTR_LOG("Physical Tile Type Capacities:\n"); VTR_LOG("------------------------------\n"); VTR_LOG("name\t"); - for (t_model* model : all_models) { - VTR_LOG("%s\t", model->name); + for (LogicalModelId model_id : models.all_models()) { + VTR_LOG("%s\t", models.get_model(model_id).name); } VTR_LOG("\n"); for (const t_physical_tile_type& tile_type : physical_tile_types) { const PrimitiveVector& capacity = physical_tile_type_capacities[tile_type.index]; VTR_LOG("%s\t", tile_type.name.c_str()); - for (t_model* model : all_models) { - VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); + for (LogicalModelId model_id : models.all_models()) { + VTR_LOG("%.2f\t", capacity.get_dim_val((size_t)model_id)); } VTR_LOG("\n"); } diff --git a/vpr/src/analytical_place/full_legalizer.cpp b/vpr/src/analytical_place/full_legalizer.cpp index 767ac67e3d9..7b7cc9cfb39 100644 --- a/vpr/src/analytical_place/full_legalizer.cpp +++ b/vpr/src/analytical_place/full_legalizer.cpp @@ -249,7 +249,7 @@ class APClusterPlacer { static LegalizationClusterId create_new_cluster(PackMoleculeId seed_molecule_id, const Prepacker& prepacker, ClusterLegalizer& cluster_legalizer, - const std::map>& primitive_candidate_block_types) { + const vtr::vector>& primitive_candidate_block_types) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); // This was stolen from pack/cluster_util.cpp:start_new_cluster // It tries to find a block type and mode for the given molecule. @@ -260,11 +260,11 @@ static LegalizationClusterId create_new_cluster(PackMoleculeId seed_molecule_id, VTR_ASSERT(seed_molecule_id.is_valid()); const t_pack_molecule& seed_molecule = prepacker.get_molecule(seed_molecule_id); AtomBlockId root_atom = seed_molecule.atom_block_ids[seed_molecule.root]; - const t_model* root_model = atom_ctx.netlist().block_model(root_atom); + LogicalModelId root_model_id = atom_ctx.netlist().block_model(root_atom); - auto itr = primitive_candidate_block_types.find(root_model); - VTR_ASSERT(itr != primitive_candidate_block_types.end()); - const std::vector& candidate_types = itr->second; + VTR_ASSERT(root_model_id.is_valid()); + VTR_ASSERT(!primitive_candidate_block_types[root_model_id].empty()); + const std::vector& candidate_types = primitive_candidate_block_types[root_model_id]; for (t_logical_block_type_ptr type : candidate_types) { int num_modes = type->pb_graph_head->pb_type->num_modes; @@ -295,6 +295,7 @@ void NaiveFullLegalizer::create_clusters(const PartialPlacement& p_placement) { high_fanout_thresholds, ClusterLegalizationStrategy::FULL, vpr_setup_.PackerOpts.enable_pin_feasibility_filter, + arch_.models, vpr_setup_.PackerOpts.pack_verbosity); // Create clusters for each tile. // Start by giving each root tile a unique ID. @@ -328,7 +329,7 @@ void NaiveFullLegalizer::create_clusters(const PartialPlacement& p_placement) { blocks_in_tiles[tile_id].push_back(ap_blk_id); } // Create the legalized clusters per tile. - std::map> + vtr::vector> primitive_candidate_block_types = identify_primitive_candidate_block_types(); for (size_t tile_id_idx = 0; tile_id_idx < num_device_tiles; tile_id_idx++) { DeviceTileId tile_id = DeviceTileId(tile_id_idx); diff --git a/vpr/src/analytical_place/model_grouper.cpp b/vpr/src/analytical_place/model_grouper.cpp index 0aca963c96a..1c74c7cdac3 100644 --- a/vpr/src/analytical_place/model_grouper.cpp +++ b/vpr/src/analytical_place/model_grouper.cpp @@ -8,7 +8,6 @@ #include "model_grouper.h" #include -#include #include #include #include "cad_types.h" @@ -16,6 +15,7 @@ #include "prepack.h" #include "vtr_assert.h" #include "vtr_log.h" +#include "vtr_vector.h" /** * @brief Recursive helper function which gets the models in the given pattern @@ -30,7 +30,7 @@ * been visited. */ static void get_pattern_models_recurr(t_pack_pattern_block* pattern_block, - std::unordered_set& models, + std::unordered_set& models, std::vector& block_visited) { // If the pattern block is invalid or this block has been visited, return. if (pattern_block == nullptr || block_visited[pattern_block->block_id]) { @@ -39,7 +39,7 @@ static void get_pattern_models_recurr(t_pack_pattern_block* pattern_block, // Mark this block as visited and insert its model into the models vector. block_visited[pattern_block->block_id] = true; - models.insert(pattern_block->pb_type->model->index); + models.insert(pattern_block->pb_type->model_id); // Go through this block's connections and get their pattern models. t_pack_pattern_connections* connection = pattern_block->connections; @@ -54,8 +54,8 @@ static void get_pattern_models_recurr(t_pack_pattern_block* pattern_block, * @brief Entry point into the recursive function above. Gets the models in * the given pack pattern. */ -static std::unordered_set get_pattern_models(const t_pack_patterns& pack_pattern) { - std::unordered_set models_in_pattern; +static std::unordered_set get_pattern_models(const t_pack_patterns& pack_pattern) { + std::unordered_set models_in_pattern; // Initialize the visited flags for each block to false. std::vector block_visited(pack_pattern.num_blocks, false); @@ -66,8 +66,7 @@ static std::unordered_set get_pattern_models(const t_pack_patterns& pack_pa } ModelGrouper::ModelGrouper(const Prepacker& prepacker, - t_model* user_models, - t_model* library_models, + const LogicalModels& models, int log_verbosity) { /** * Group the models together based on their pack patterns. If model A and @@ -80,26 +79,10 @@ ModelGrouper::ModelGrouper(const Prepacker& prepacker, * the connected sub-graphs which will be the groups. */ - // Get the number of models - // TODO: Clean up the models vectors in VTR. - std::unordered_map model_name; - unsigned num_models = 0; - t_model* model = library_models; - while (model != nullptr) { - model_name[model->index] = model->name; - num_models++; - model = model->next; - } - model = user_models; - while (model != nullptr) { - model_name[model->index] = model->name; - num_models++; - model = model->next; - } - // Create an adjacency list for the edges. An edge is formed where two // models share a pack pattern together. - std::vector> adj_list(num_models); + size_t num_models = models.all_models().size(); + vtr::vector> adj_list(num_models); for (const t_pack_patterns& pack_pattern : prepacker.get_all_pack_patterns()) { // Get the models within this pattern. auto models_in_pattern = get_pattern_models(pack_pattern); @@ -108,8 +91,8 @@ ModelGrouper::ModelGrouper(const Prepacker& prepacker, // Debug print the models within the pattern. if (log_verbosity >= 20) { VTR_LOG("Pattern: %s\n\t", pack_pattern.name); - for (int model_idx : models_in_pattern) { - VTR_LOG("%s ", model_name[model_idx]); + for (LogicalModelId model_id : models_in_pattern) { + VTR_LOG("%s ", models.model_name(model_id).c_str()); } VTR_LOG("\n"); } @@ -117,8 +100,8 @@ ModelGrouper::ModelGrouper(const Prepacker& prepacker, // Connect each of the models to the first model in the pattern. Since // we only care if there exist a path from each model to another, we do // not need to connect the models in a clique. - int first_model_idx = *models_in_pattern.begin(); - for (int model_idx : models_in_pattern) { + LogicalModelId first_model_idx = *models_in_pattern.begin(); + for (LogicalModelId model_idx : models_in_pattern) { adj_list[model_idx].insert(first_model_idx); adj_list[first_model_idx].insert(model_idx); } @@ -127,57 +110,57 @@ ModelGrouper::ModelGrouper(const Prepacker& prepacker, // Perform BFS to group the models. VTR_LOGV(log_verbosity >= 20, "Finding model groups...\n"); - std::queue node_queue; + std::queue node_queue; model_group_id_.resize(num_models, ModelGroupId::INVALID()); - for (int model_idx = 0; model_idx < (int)num_models; model_idx++) { + for (LogicalModelId model_id : models.all_models()) { // If this model is already in a group, skip it. - if (model_group_id_[model_idx].is_valid()) { + if (model_group_id_[model_id].is_valid()) { VTR_LOGV(log_verbosity >= 20, - "\t(%d -> %d)\n", model_idx, model_group_id_[model_idx]); + "\t(%zu -> %zu)\n", model_id, model_group_id_[model_id]); continue; } ModelGroupId group_id = ModelGroupId(group_ids_.size()); // Put the model in this group and push to the queue. - model_group_id_[model_idx] = group_id; - node_queue.push(model_idx); + model_group_id_[model_id] = group_id; + node_queue.push(model_id); while (!node_queue.empty()) { // Pop a node from the queue, and explore its neighbors. - int node_model_idx = node_queue.front(); + LogicalModelId node_model_id = node_queue.front(); node_queue.pop(); - for (int neighbor_model_idx : adj_list[node_model_idx]) { + for (LogicalModelId neighbor_model_id : adj_list[node_model_id]) { // If this neighbor is already in this group, skip it. - if (model_group_id_[neighbor_model_idx].is_valid()) { - VTR_ASSERT_SAFE(model_group_id_[neighbor_model_idx] == group_id); + if (model_group_id_[neighbor_model_id].is_valid()) { + VTR_ASSERT_SAFE(model_group_id_[neighbor_model_id] == group_id); continue; } // Put the neighbor in this group and push it to the queue. - model_group_id_[neighbor_model_idx] = group_id; - node_queue.push(neighbor_model_idx); + model_group_id_[neighbor_model_id] = group_id; + node_queue.push(neighbor_model_id); } } VTR_LOGV(log_verbosity >= 20, - "\t(%d -> %d)\n", model_idx, model_group_id_[model_idx]); + "\t(%zu -> %zu)\n", model_id, model_group_id_[model_id]); group_ids_.push_back(group_id); } // Create a lookup between each group and the models it contains. groups_.resize(groups().size()); - for (int model_idx = 0; model_idx < (int)num_models; model_idx++) { - groups_[model_group_id_[model_idx]].push_back(model_idx); + for (LogicalModelId model_id : models.all_models()) { + groups_[model_group_id_[model_id]].push_back(model_id); } // Debug printing for each group. if (log_verbosity >= 20) { for (ModelGroupId group_id : groups()) { - const std::vector& group = groups_[group_id]; + const std::vector& group = groups_[group_id]; VTR_LOG("Group %zu:\n", group_id); VTR_LOG("\tSize = %zu\n", group.size()); VTR_LOG("\tContained models:\n"); - for (int model_idx : group) { - VTR_LOG("\t\t%s\n", model_name[model_idx]); + for (LogicalModelId model_id : group) { + VTR_LOG("\t\t%s\n", models.model_name(model_id).c_str()); } } } diff --git a/vpr/src/analytical_place/model_grouper.h b/vpr/src/analytical_place/model_grouper.h index d5a9113d6c1..6e9e56ce03a 100644 --- a/vpr/src/analytical_place/model_grouper.h +++ b/vpr/src/analytical_place/model_grouper.h @@ -9,6 +9,7 @@ #pragma once #include +#include "logic_types.h" #include "vtr_assert.h" #include "vtr_range.h" #include "vtr_strong_id.h" @@ -17,7 +18,6 @@ // Forward declarations. class Prepacker; -struct t_model; /// @brief Tag for the ModelGroupId struct model_group_id_tag; @@ -69,8 +69,7 @@ class ModelGrouper { * The verbosity of log messages in the grouper class. */ ModelGrouper(const Prepacker& prepacker, - t_model* user_models, - t_model* library_models, + const LogicalModels& models, int log_verbosity); /** @@ -83,10 +82,10 @@ class ModelGrouper { /** * @brief Gets the group ID of the given model. */ - inline ModelGroupId get_model_group_id(int model_index) const { - VTR_ASSERT_SAFE_MSG(model_index < (int)model_group_id_.size(), + inline ModelGroupId get_model_group_id(LogicalModelId model_id) const { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), "Model index outside of range for model_group_id_"); - ModelGroupId group_id = model_group_id_[model_index]; + ModelGroupId group_id = model_group_id_[model_id]; VTR_ASSERT_SAFE_MSG(group_id.is_valid(), "Model is not in a group"); return group_id; @@ -95,7 +94,7 @@ class ModelGrouper { /** * @brief Gets the models in the given group. */ - inline const std::vector& get_models_in_group(ModelGroupId group_id) const { + inline const std::vector& get_models_in_group(ModelGroupId group_id) const { VTR_ASSERT_SAFE_MSG(group_id.is_valid(), "Invalid group id"); VTR_ASSERT_SAFE_MSG(groups_[group_id].size() != 0, @@ -108,8 +107,8 @@ class ModelGrouper { vtr::vector_map group_ids_; /// @brief A lookup between models and the group ID that contains them. - std::vector model_group_id_; + vtr::vector model_group_id_; /// @brief A lookup between each group ID and the models in that group. - vtr::vector> groups_; + vtr::vector> groups_; }; diff --git a/vpr/src/analytical_place/partial_legalizer.cpp b/vpr/src/analytical_place/partial_legalizer.cpp index 1f5103ba02b..38e585ae1b1 100644 --- a/vpr/src/analytical_place/partial_legalizer.cpp +++ b/vpr/src/analytical_place/partial_legalizer.cpp @@ -66,27 +66,6 @@ std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer return nullptr; } -/** - * @brief Get the number of models in the device architecture. - * - * FIXME: These are stored in such an annoying way. It should be much easier - * to get this information! - */ -static inline size_t get_num_models() { - size_t num_models = 0; - t_model* curr_model = g_vpr_ctx.device().arch->models; - while (curr_model != nullptr) { - num_models++; - curr_model = curr_model->next; - } - curr_model = g_vpr_ctx.device().arch->model_library; - while (curr_model != nullptr) { - num_models++; - curr_model = curr_model->next; - } - return num_models; -} - /** * @brief Helper method to get the direct neighbors of the given bin. * @@ -142,7 +121,7 @@ static inline vtr::Point get_center_of_rect(vtr::Rect rect) { return rect.bottom_left() + vtr::Point(rect.width() / 2.0, rect.height() / 2.0); } -void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, size_t num_models) { +void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, const LogicalModels& models) { // Make sure that this bin does not already have neighbors. VTR_ASSERT_DEBUG(bin_neighbors_.size() == 0); @@ -165,10 +144,11 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, // Flags to check if a specific model has been found in the given direction. // In this case, direction is the direction of the largest component of the // manhattan distance between the source bin and the target bin. - std::vector up_found(num_models, false); - std::vector down_found(num_models, false); - std::vector left_found(num_models, false); - std::vector right_found(num_models, false); + size_t num_models = models.all_models().size(); + vtr::vector up_found(num_models, false); + vtr::vector down_found(num_models, false); + vtr::vector left_found(num_models, false); + vtr::vector right_found(num_models, false); // Flags to check if all models have been found in a given direction. bool all_up_found = false; bool all_down_found = false; @@ -186,17 +166,17 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, // type. This method returns true if every model has been found in the given // direction (i.e. dir_found is now all true). auto add_neighbor_if_new_dir = [&](FlatPlacementBinId target_bin_id, - std::vector& dir_found) { + vtr::vector& dir_found) { bool all_found = true; // Go through all possible models - for (size_t i = 0; i < num_models; i++) { + for (LogicalModelId model_id : models.all_models()) { // If this model has been found in this direction, continue. - if (dir_found[i]) + if (dir_found[model_id]) continue; // If this bin has this model in its capacity, we found a neighbor! const PrimitiveVector& target_bin_capacity = density_manager_->get_bin_capacity(target_bin_id); - if (target_bin_capacity.get_dim_val(i) > 0) { - dir_found[i] = true; + if (target_bin_capacity.get_dim_val((size_t)model_id) > 0) { + dir_found[model_id] = true; neighbors.insert(target_bin_id); } else { all_found = false; @@ -271,9 +251,9 @@ FlowBasedLegalizer::FlowBasedLegalizer(const APNetlist& netlist, , bin_neighbors_(density_manager_->flat_placement_bins().bins().size()) { // Connect the bins. - size_t num_models = get_num_models(); for (FlatPlacementBinId bin_id : density_manager_->flat_placement_bins().bins()) { - compute_neighbors_of_bin(bin_id, num_models); + // TODO: Pass the models in. + compute_neighbors_of_bin(bin_id, g_vpr_ctx.device().arch->models); } } @@ -703,42 +683,27 @@ void FlowBasedLegalizer::legalize(PartialPlacement& p_placement) { } PerModelPrefixSum2D::PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, - t_model* user_models, - t_model* library_models, - std::function lookup) { - // Get the number of models in the architecture. - // TODO: We really need to clean up how models are stored in VPR... - t_model* cur = user_models; - int num_models = 0; - while (cur != nullptr) { - num_models++; - cur = cur->next; - } - cur = library_models; - while (cur != nullptr) { - num_models++; - cur = cur->next; - } - + const LogicalModels& models, + std::function lookup) { // Get the size that the prefix sums should be. size_t width, height, layers; std::tie(width, height, layers) = density_manager.get_overall_placeable_region_size(); // Create each of the prefix sums. - model_prefix_sum_.resize(num_models); - for (int model_index = 0; model_index < num_models; model_index++) { - model_prefix_sum_[model_index] = vtr::PrefixSum2D( + model_prefix_sum_.resize(models.all_models().size()); + for (LogicalModelId model_id : models.all_models()) { + model_prefix_sum_[model_id] = vtr::PrefixSum2D( width, height, [&](size_t x, size_t y) { - return lookup(model_index, x, y); + return lookup(model_id, x, y); }); } } -float PerModelPrefixSum2D::get_model_sum(int model_index, +float PerModelPrefixSum2D::get_model_sum(LogicalModelId model_index, const vtr::Rect& region) const { - VTR_ASSERT_SAFE(model_index < (int)model_prefix_sum_.size() && model_index >= 0); + VTR_ASSERT_SAFE(model_index.is_valid()); // Get the sum over the given region. return model_prefix_sum_[model_index].get_sum(region.xmin(), region.ymin(), @@ -746,12 +711,12 @@ float PerModelPrefixSum2D::get_model_sum(int model_index, region.ymax() - 1); } -PrimitiveVector PerModelPrefixSum2D::get_sum(const std::vector& model_indices, +PrimitiveVector PerModelPrefixSum2D::get_sum(const std::vector& model_indices, const vtr::Rect& region) const { PrimitiveVector res; - for (int model_index : model_indices) { - VTR_ASSERT_SAFE(res.get_dim_val(model_index) == 0.0f); - res.set_dim_val(model_index, get_model_sum(model_index, region)); + for (LogicalModelId model_index : model_indices) { + VTR_ASSERT_SAFE(res.get_dim_val((size_t)model_index) == 0.0f); + res.set_dim_val((size_t)model_index, get_model_sum(model_index, region)); } return res; } @@ -765,19 +730,17 @@ BiPartitioningPartialLegalizer::BiPartitioningPartialLegalizer( , density_manager_(density_manager) , model_grouper_(prepacker, g_vpr_ctx.device().arch->models, - g_vpr_ctx.device().arch->model_library, log_verbosity) { // Compute the capacity prefix sum. Capacity is assumed to not change // between iterations of the partial legalizer. capacity_prefix_sum_ = PerModelPrefixSum2D( *density_manager, g_vpr_ctx.device().arch->models, - g_vpr_ctx.device().arch->model_library, - [&](int model_index, size_t x, size_t y) { + [&](LogicalModelId model_index, size_t x, size_t y) { // Get the bin at this grid location. FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); // Get the capacity of the bin for this model. - float cap = density_manager_->get_bin_capacity(bin_id).get_dim_val(model_index); + float cap = density_manager_->get_bin_capacity(bin_id).get_dim_val((size_t)model_index); VTR_ASSERT_SAFE(cap >= 0.0f); // Bins may be large, but the prefix sum assumes a 1x1 grid of // values. Normalize by the area of the bin to turn this into @@ -831,7 +794,7 @@ void BiPartitioningPartialLegalizer::legalize(PartialPlacement& p_placement) { std::vector overfilled_models = overfill.get_non_zero_dims(); // For each model, insert its group into the set. Set will handle dupes. for (int model_index : overfilled_models) { - groups_to_spread.insert(model_grouper_.get_model_group_id(model_index)); + groups_to_spread.insert(model_grouper_.get_model_group_id((LogicalModelId)model_index)); } } @@ -905,9 +868,9 @@ static bool is_vector_in_group(const PrimitiveVector& vec, ModelGroupId group_id, const ModelGrouper& model_grouper) { VTR_ASSERT_SAFE(vec.is_non_negative()); - const std::vector& models_in_group = model_grouper.get_models_in_group(group_id); - for (int model_index : models_in_group) { - float dim_val = vec.get_dim_val(model_index); + const std::vector& models_in_group = model_grouper.get_models_in_group(group_id); + for (LogicalModelId model_index : models_in_group) { + float dim_val = vec.get_dim_val((size_t)model_index); if (dim_val != 0.0f) return true; } @@ -1010,9 +973,9 @@ std::vector BiPartitioningPartialLegalizer::get_overfil static bool is_region_overfilled(const vtr::Rect& region, const PerModelPrefixSum2D& capacity_prefix_sum, const PerModelPrefixSum2D& utilization_prefix_sum, - const std::vector& model_indices) { + const std::vector& model_indices) { // Go through each model in the model group we are interested in. - for (int model_index : model_indices) { + for (LogicalModelId model_index : model_indices) { // Get the capacity of this region for this model. float region_model_capacity = capacity_prefix_sum.get_model_sum(model_index, region); @@ -1052,13 +1015,12 @@ std::vector BiPartitioningPartialLegalizer::get_min_windows_aro PerModelPrefixSum2D utilization_prefix_sum( *density_manager_, g_vpr_ctx.device().arch->models, - g_vpr_ctx.device().arch->model_library, - [&](int model_index, size_t x, size_t y) { + [&](LogicalModelId model_index, size_t x, size_t y) { FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); // This is computed the same way as the capacity prefix sum above. const vtr::Rect& bin_region = density_manager_->flat_placement_bins().bin_region(bin_id); float bin_area = bin_region.width() * bin_region.height(); - float util = density_manager_->get_bin_utilization(bin_id).get_dim_val(model_index); + float util = density_manager_->get_bin_utilization(bin_id).get_dim_val((size_t)model_index); VTR_ASSERT_SAFE(util >= 0.0f); return util / bin_area; }); @@ -1329,7 +1291,7 @@ PartitionedWindow BiPartitioningPartialLegalizer::partition_window( // the two partitions are perfectly balanced (equal on both sides). float best_score = -1.0f; PartitionedWindow partitioned_window; - const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); + const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); // First, try all of the vertical partitions. double min_pivot_x = std::floor(window.region.xmin()) + 1.0; @@ -1429,7 +1391,7 @@ void BiPartitioningPartialLegalizer::partition_blocks_in_window( SpreadingWindow& upper_window = partitioned_window.upper_window; // Get the capacity of each window partition. - const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); + const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); PrimitiveVector lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, lower_window.region); PrimitiveVector upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, diff --git a/vpr/src/analytical_place/partial_legalizer.h b/vpr/src/analytical_place/partial_legalizer.h index 5f82c787724..3920194eee0 100644 --- a/vpr/src/analytical_place/partial_legalizer.h +++ b/vpr/src/analytical_place/partial_legalizer.h @@ -20,6 +20,7 @@ #include "ap_flow_enums.h" #include "flat_placement_bins.h" #include "flat_placement_density_manager.h" +#include "logic_types.h" #include "model_grouper.h" #include "primitive_vector.h" #include "vtr_geometry.h" @@ -181,7 +182,7 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param src_bin_id The bin to compute the neighbors for. * @param num_models The number of models in the architecture. */ - void compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, size_t num_models); + void compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, const LogicalModels& models); /** * @brief Debugging method which verifies that all the bins are valid. @@ -316,26 +317,25 @@ class PerModelPrefixSum2D { * the model index, x, and y to be populated. */ PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, - t_model* user_models, - t_model* library_models, - std::function lookup); + const LogicalModels& models, + std::function lookup); /** * @brief Get the sum for a given model over the given region. */ - float get_model_sum(int model_index, + float get_model_sum(LogicalModelId model_index, const vtr::Rect& region) const; /** * @brief Get the multi-dimensional sum over the given model indices over * the given region. */ - PrimitiveVector get_sum(const std::vector& model_indices, + PrimitiveVector get_sum(const std::vector& model_indices, const vtr::Rect& region) const; private: /// @brief Per-Model Prefix Sums - std::vector> model_prefix_sum_; + vtr::vector> model_prefix_sum_; }; /** diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index f08d79518c5..f911039c184 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -1,6 +1,7 @@ #include #include +#include "SetupVPR.h" #include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_util.h" @@ -14,7 +15,6 @@ #include "globals.h" #include "read_xml_arch_file.h" #include "read_fpga_interchange_arch.h" -#include "SetupVPR.h" #include "pb_type_graph.h" #include "pack_types.h" #include "lb_type_rr_graph.h" @@ -89,8 +89,6 @@ void SetupVPR(const t_options* options, const bool readArchFile, t_file_name_opts* fileNameOpts, t_arch* arch, - t_model** user_models, - t_model** library_models, t_netlist_opts* netlistOpts, t_packer_opts* packerOpts, t_placer_opts* placerOpts, @@ -113,6 +111,8 @@ void SetupVPR(const t_options* options, auto& device_ctx = g_vpr_ctx.mutable_device(); + device_ctx.arch = arch; + if (options->CircuitName.value().empty()) { VPR_FATAL_ERROR(VPR_ERROR_BLIF_F, "No blif file found in arguments (did you specify an architecture file?)\n"); @@ -177,9 +177,6 @@ void SetupVPR(const t_options* options, } VTR_LOG("\n"); - *user_models = arch->models; - *library_models = arch->model_library; - device_ctx.EMPTY_PHYSICAL_TILE_TYPE = nullptr; int num_inputs = 0; int num_outputs = 0; diff --git a/vpr/src/base/SetupVPR.h b/vpr/src/base/SetupVPR.h index 45bf510c18c..9492da360d6 100644 --- a/vpr/src/base/SetupVPR.h +++ b/vpr/src/base/SetupVPR.h @@ -1,7 +1,6 @@ #ifndef SETUPVPR_H #define SETUPVPR_H #include -#include "logic_types.h" #include "read_options.h" #include "physical_types.h" #include "vpr_types.h" @@ -11,8 +10,6 @@ void SetupVPR(const t_options* Options, const bool readArchFile, t_file_name_opts* FileNameOpts, t_arch* Arch, - t_model** user_models, - t_model** library_models, t_netlist_opts* NetlistOpts, t_packer_opts* PackerOpts, t_placer_opts* PlacerOpts, diff --git a/vpr/src/base/atom_netlist.cpp b/vpr/src/base/atom_netlist.cpp index 1cbd2232f1f..63132e95500 100644 --- a/vpr/src/base/atom_netlist.cpp +++ b/vpr/src/base/atom_netlist.cpp @@ -1,13 +1,9 @@ -#include #include -#include -#include #include "atom_netlist.h" - -#include "vtr_assert.h" -#include "vtr_log.h" +#include "logic_types.h" #include "vpr_error.h" +#include "vtr_assert.h" /* * @@ -18,27 +14,27 @@ */ AtomNetlist::AtomNetlist(std::string name, std::string id) : Netlist(name, id) - , inpad_model_(nullptr) - , outpad_model_(nullptr) {} + , inpad_model_(LogicalModelId::INVALID()) + , outpad_model_(LogicalModelId::INVALID()) {} /* * * Blocks * */ -void AtomNetlist::set_block_types(const t_model* inpad, const t_model* outpad) { - VTR_ASSERT(inpad != nullptr); - VTR_ASSERT(outpad != nullptr); +void AtomNetlist::set_block_types(LogicalModelId inpad, LogicalModelId outpad) { + VTR_ASSERT(inpad.is_valid()); + VTR_ASSERT(outpad.is_valid()); inpad_model_ = inpad; outpad_model_ = outpad; } AtomBlockType AtomNetlist::block_type(const AtomBlockId id) const { - VTR_ASSERT(inpad_model_ != nullptr); - VTR_ASSERT(outpad_model_ != nullptr); + VTR_ASSERT(inpad_model_.is_valid()); + VTR_ASSERT(outpad_model_.is_valid()); - const t_model* blk_model = block_model(id); + LogicalModelId blk_model = block_model(id); AtomBlockType type = AtomBlockType::BLOCK; if (blk_model == inpad_model_) { @@ -51,7 +47,7 @@ AtomBlockType AtomNetlist::block_type(const AtomBlockId id) const { return type; } -const t_model* AtomNetlist::block_model(const AtomBlockId id) const { +LogicalModelId AtomNetlist::block_model(const AtomBlockId id) const { VTR_ASSERT_SAFE(valid_block_id(id)); return block_models_[id]; @@ -137,7 +133,7 @@ std::unordered_set AtomNetlist::net_aliases(const std::string& net_ * Mutators * */ -AtomBlockId AtomNetlist::create_block(const std::string& name, const t_model* model, const TruthTable& truth_table) { +AtomBlockId AtomNetlist::create_block(const std::string& name, LogicalModelId model, const TruthTable& truth_table) { AtomBlockId blk_id = Netlist::create_block(name); //Initialize the data diff --git a/vpr/src/base/atom_netlist.h b/vpr/src/base/atom_netlist.h index b40e18d2d18..d7c47b13da0 100644 --- a/vpr/src/base/atom_netlist.h +++ b/vpr/src/base/atom_netlist.h @@ -97,13 +97,13 @@ class AtomNetlist : public Netlist block_models_; //Architecture model of each block + vtr::vector_map block_models_; //Architecture model of each block vtr::vector_map block_truth_tables_; //Truth tables of each block // Input IOs and output IOs always exist and have their own architecture @@ -270,8 +270,8 @@ class AtomNetlist : public Netlist port_models_; //Architecture port models of each port diff --git a/vpr/src/base/atom_netlist_utils.cpp b/vpr/src/base/atom_netlist_utils.cpp index 5172db9261a..a56ea9ceb44 100644 --- a/vpr/src/base/atom_netlist_utils.cpp +++ b/vpr/src/base/atom_netlist_utils.cpp @@ -1,16 +1,16 @@ #include "atom_netlist_utils.h" -#include #include #include #include #include #include +#include "logic_types.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vpr_error.h" -#include "vpr_utils.h" +#include "vtr_vector_map.h" /** * @brief Marks primitive output pins constant if all inputs to the block are constant @@ -18,15 +18,15 @@ * Since marking one block constant may cause a downstream block to also be constant, * marking is repated until there is no further change */ -int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, int verbosity); +int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity); ///@brief Marks all primtive output pins which have no combinationally connected inputs as constant pins int mark_undriven_primitive_outputs_as_constant(AtomNetlist& netlist, int verbosity); ///@brief Marks all primtive output pins of blk which have only constant inputs as constant pins -int infer_and_mark_block_pins_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, int verbosity); +int infer_and_mark_block_pins_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity); int infer_and_mark_block_combinational_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, int verbosity); -int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, int verbosity); +int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity); ///@brief Returns the set of input ports which are combinationally connected to output_port std::vector find_combinationally_connected_input_ports(const AtomNetlist& netlist, AtomPortId output_port); @@ -34,27 +34,27 @@ std::vector find_combinationally_connected_input_ports(const AtomNet ///@brief Returns the set of clock ports which are combinationally connected to output_port std::vector find_combinationally_connected_clock_ports(const AtomNetlist& netlist, AtomPortId output_port); -bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk); -bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); -bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); +bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models); +bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr); +bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr); bool is_removable_output(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); /** * @brief Attempts to remove the specified buffer LUT blk from the netlist. * @return true if successful */ -bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity); +bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, const LogicalModels& models, int verbosity); std::string make_unconn(size_t& unconn_count, PinType type); void cube_to_minterms_recurr(std::vector cube, std::vector& minterms); -void print_netlist_as_blif(std::string filename, const AtomNetlist& netlist) { +void print_netlist_as_blif(std::string filename, const AtomNetlist& netlist, const LogicalModels& models) { FILE* f = std::fopen(filename.c_str(), "w"); - print_netlist_as_blif(f, netlist); + print_netlist_as_blif(f, netlist, models); std::fclose(f); } -void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { +void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalModels& models) { constexpr const char* INDENT = " "; size_t unconn_count = 0; @@ -137,10 +137,11 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { } //Latch + LogicalModelId latch_model = models.get_model_by_name(LogicalModels::MODEL_LATCH); for (auto blk_id : netlist.blocks()) { if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) { - const t_model* blk_model = netlist.block_model(blk_id); - if (blk_model->name != std::string(MODEL_LATCH)) continue; + LogicalModelId blk_model = netlist.block_model(blk_id); + if (blk_model != latch_model) continue; //Nets std::string d_net; @@ -224,10 +225,11 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { } //Names + LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES); for (auto blk_id : netlist.blocks()) { if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) { - const t_model* blk_model = netlist.block_model(blk_id); - if (blk_model->name != std::string(MODEL_NAMES)) continue; + LogicalModelId blk_model = netlist.block_model(blk_id); + if (blk_model != names_model) continue; std::vector nets; @@ -290,14 +292,15 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { } //Subckt - - std::set subckt_models; + LogicalModelId input_model = models.get_model_by_name(LogicalModels::MODEL_INPUT); + LogicalModelId output_model = models.get_model_by_name(LogicalModels::MODEL_OUTPUT); + std::set subckt_models; for (auto blk_id : netlist.blocks()) { - const t_model* blk_model = netlist.block_model(blk_id); - if (blk_model->name == std::string(MODEL_LATCH) - || blk_model->name == std::string(MODEL_NAMES) - || blk_model->name == std::string(MODEL_INPUT) - || blk_model->name == std::string(MODEL_OUTPUT)) { + LogicalModelId blk_model = netlist.block_model(blk_id); + if (blk_model == latch_model + || blk_model == names_model + || blk_model == input_model + || blk_model == output_model) { continue; } @@ -363,11 +366,12 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { fprintf(f, "\n"); //The subckt models - for (const t_model* model : subckt_models) { - fprintf(f, ".model %s\n", model->name); + for (LogicalModelId model_id : subckt_models) { + const t_model& model = models.get_model(model_id); + fprintf(f, ".model %s\n", model.name); fprintf(f, ".inputs"); - const t_model_ports* port = model->inputs; + const t_model_ports* port = model.inputs; while (port) { VTR_ASSERT(port->size >= 0); if (port->size == 1) { @@ -384,7 +388,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { fprintf(f, "\n"); fprintf(f, ".outputs"); - port = model->outputs; + port = model.outputs; while (port) { VTR_ASSERT(port->size >= 0); if (port->size == 1) { @@ -407,26 +411,11 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { } } -std::string atom_pin_arch_name(const AtomNetlist& netlist, const AtomPinId pin) { - std::string arch_name; - - AtomBlockId blk = netlist.pin_block(pin); - AtomPortId port = netlist.pin_port(pin); - arch_name += netlist.block_model(blk)->name; - arch_name += "."; - arch_name += netlist.port_model(port)->name; - arch_name += "["; - arch_name += std::to_string(netlist.pin_port_bit(pin)); - arch_name += "]"; - - return arch_name; -} - -int mark_constant_generators(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, int verbosity) { +int mark_constant_generators(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity) { int num_undriven_pins_marked_const = mark_undriven_primitive_outputs_as_constant(netlist, verbosity); VTR_LOGV(verbosity > 0, "Inferred %4d additional primitive pins as constant generators since they have no combinationally connected inputs\n", num_undriven_pins_marked_const); - int num_inferred_pins_marked_const = infer_and_mark_constant_pins(netlist, const_gen_inference_method, verbosity); + int num_inferred_pins_marked_const = infer_and_mark_constant_pins(netlist, const_gen_inference_method, models, verbosity); VTR_LOGV(verbosity > 0, "Inferred %4d additional primitive pins as constant generators due to constant inputs\n", num_inferred_pins_marked_const); return num_undriven_pins_marked_const + num_inferred_pins_marked_const; @@ -489,7 +478,7 @@ int mark_undriven_primitive_outputs_as_constant(AtomNetlist& netlist, int verbos return num_pins_marked_constant; } -int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, int verbosity) { +int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity) { size_t num_pins_inferred_constant = 0; //It is possible that by marking one constant generator @@ -505,7 +494,7 @@ int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference con for (auto blk : netlist.blocks()) { if (!blk) continue; - num_pins_marked += infer_and_mark_block_pins_constant(netlist, blk, const_gen_inference_method, verbosity); + num_pins_marked += infer_and_mark_block_pins_constant(netlist, blk, const_gen_inference_method, models, verbosity); } num_pins_inferred_constant += num_pins_marked; @@ -514,12 +503,12 @@ int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference con return num_pins_inferred_constant; } -int infer_and_mark_block_pins_constant(AtomNetlist& netlist, AtomBlockId block, e_const_gen_inference const_gen_inference_method, int verbosity) { +int infer_and_mark_block_pins_constant(AtomNetlist& netlist, AtomBlockId block, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity) { size_t num_pins_marked_constant = 0; num_pins_marked_constant += infer_and_mark_block_combinational_outputs_constant(netlist, block, const_gen_inference_method, verbosity); - num_pins_marked_constant += infer_and_mark_block_sequential_outputs_constant(netlist, block, const_gen_inference_method, verbosity); + num_pins_marked_constant += infer_and_mark_block_sequential_outputs_constant(netlist, block, const_gen_inference_method, models, verbosity); return num_pins_marked_constant; } @@ -581,7 +570,7 @@ int infer_and_mark_block_combinational_outputs_constant(AtomNetlist& netlist, At return num_pins_marked_constant; } -int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, int verbosity) { +int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity) { //Only if sequential constant generator inference enabled if (const_gen_inference_method != e_const_gen_inference::COMB_SEQ) { return 0; @@ -639,7 +628,7 @@ int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomB VTR_LOGV(verbosity > 1, "Marking sequential pin '%s' as constant since all inputs to block '%s' (%s) are constant\n", netlist.pin_name(output_pin).c_str(), netlist.block_name(blk).c_str(), - netlist.block_model(blk)->name); + models.get_model(netlist.block_model(blk)).name); netlist.set_pin_is_constant(output_pin, true); ++num_pins_marked_constant; } @@ -692,7 +681,7 @@ std::vector find_combinationally_connected_clock_ports(const AtomNet return upstream_ports; } -void absorb_buffer_luts(AtomNetlist& netlist, int verbosity) { +void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int verbosity) { //First we look through the netlist to find LUTs with identity logic functions //we then remove those luts, replacing the net's they drove with the inputs to the //buffer lut @@ -701,8 +690,8 @@ void absorb_buffer_luts(AtomNetlist& netlist, int verbosity) { //Remove the buffer luts for (auto blk : netlist.blocks()) { - if (is_buffer_lut(netlist, blk)) { - if (remove_buffer_lut(netlist, blk, verbosity)) { + if (is_buffer_lut(netlist, blk, models)) { + if (remove_buffer_lut(netlist, blk, models, verbosity)) { ++removed_buffer_count; } } @@ -712,11 +701,10 @@ void absorb_buffer_luts(AtomNetlist& netlist, int verbosity) { //TODO: absorb inverter LUTs? } -bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk) { +bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models) { if (netlist.block_type(blk) == AtomBlockType::BLOCK) { - const t_model* blk_model = netlist.block_model(blk); - - if (blk_model->name != std::string(MODEL_NAMES)) return false; + const LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES); + if (netlist.block_model(blk) != names_model) return false; auto input_ports = netlist.block_input_ports(blk); auto output_ports = netlist.block_output_ports(blk); @@ -773,7 +761,7 @@ bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk) { return false; } -bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity) { +bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, const LogicalModels& models, int verbosity) { //General net connectivity, numbers equal pin ids // // 1 in 2 ----- m+1 out @@ -822,13 +810,23 @@ bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity) { auto input_net = netlist.pin_net(input_pin); auto output_net = netlist.pin_net(output_pin); - VTR_LOGV_WARN(verbosity > 1, "Attempting to remove buffer '%s' (%s) from net '%s' to net '%s'\n", netlist.block_name(blk).c_str(), netlist.block_model(blk)->name, netlist.net_name(input_net).c_str(), netlist.net_name(output_net).c_str()); + VTR_LOGV_WARN(verbosity > 1, + "Attempting to remove buffer '%s' (%s) from net '%s' to net '%s'\n", + netlist.block_name(blk).c_str(), + models.model_name(netlist.block_model(blk)).c_str(), + netlist.net_name(input_net).c_str(), + netlist.net_name(output_net).c_str()); //Collect the new driver and sink pins AtomPinId new_driver = netlist.net_driver(input_net); if (!new_driver) { - VTR_LOGV_WARN(verbosity > 2, "Buffer '%s' has no input and will not be absorbed (left to be swept)\n", netlist.block_name(blk).c_str(), netlist.block_model(blk)->name, netlist.net_name(input_net).c_str(), netlist.net_name(output_net).c_str()); + VTR_LOGV_WARN(verbosity > 2, + "Buffer '%s' has no input and will not be absorbed (left to be swept)\n", + netlist.block_name(blk).c_str(), + models.model_name(netlist.block_model(blk)).c_str(), + netlist.net_name(input_net).c_str(), + netlist.net_name(output_net).c_str()); return false; //Dangling/undriven input, leave buffer to be swept } @@ -909,7 +907,7 @@ bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity) { return true; } -bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk_id, std::string* reason) { +bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk_id, const LogicalModels& models, std::string* reason) { //Any block with no fanout is removable for (AtomPinId pin_id : netlist.block_output_pins(blk_id)) { if (!pin_id) continue; @@ -923,7 +921,7 @@ bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk_id, st //If the model relative to this block is has the never prune flag set //it cannot be removed, even if it does not have a fanout auto blk_model = netlist.block_model(blk_id); - if (blk_model->never_prune == true) { + if (models.get_model(blk_model).never_prune == true) { return false; } @@ -931,13 +929,13 @@ bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk_id, st return true; } -bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk_id, std::string* reason) { +bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk_id, const LogicalModels& models, std::string* reason) { AtomBlockType type = netlist.block_type(blk_id); //Only return true if an INPAD if (type != AtomBlockType::INPAD) return false; - return is_removable_block(netlist, blk_id, reason); + return is_removable_block(netlist, blk_id, models, reason); } bool is_removable_output(const AtomNetlist& netlist, const AtomBlockId blk_id, std::string* reason) { @@ -996,6 +994,7 @@ size_t sweep_iterative(AtomNetlist& netlist, bool should_sweep_blocks, bool should_sweep_constant_primary_outputs, e_const_gen_inference const_gen_inference_method, + const LogicalModels& models, int verbosity) { size_t dangling_nets_swept = 0; size_t dangling_blocks_swept = 0; @@ -1023,12 +1022,12 @@ size_t sweep_iterative(AtomNetlist& netlist, pass_constant_generators_marked = 0; if (should_sweep_ios) { - pass_dangling_inputs_swept += sweep_inputs(netlist, verbosity); + pass_dangling_inputs_swept += sweep_inputs(netlist, models, verbosity); pass_dangling_outputs_swept += sweep_outputs(netlist, verbosity); } if (should_sweep_blocks) { - pass_dangling_blocks_swept += sweep_blocks(netlist, verbosity); + pass_dangling_blocks_swept += sweep_blocks(netlist, models, verbosity); } if (should_sweep_nets) { @@ -1039,7 +1038,7 @@ size_t sweep_iterative(AtomNetlist& netlist, pass_constant_outputs_swept += sweep_constant_primary_outputs(netlist, verbosity); } - pass_constant_generators_marked += mark_constant_generators(netlist, const_gen_inference_method, verbosity); + pass_constant_generators_marked += mark_constant_generators(netlist, const_gen_inference_method, models, verbosity); dangling_nets_swept += pass_dangling_nets_swept; dangling_blocks_swept += pass_dangling_blocks_swept; @@ -1070,7 +1069,7 @@ size_t sweep_iterative(AtomNetlist& netlist, + constant_outputs_swept; } -size_t sweep_blocks(AtomNetlist& netlist, int verbosity) { +size_t sweep_blocks(AtomNetlist& netlist, const LogicalModels& models, int verbosity) { //Identify any blocks (not inputs or outputs) for removal std::unordered_set blocks_to_remove; for (auto blk_id : netlist.blocks()) { @@ -1083,7 +1082,7 @@ size_t sweep_blocks(AtomNetlist& netlist, int verbosity) { //We remove any blocks with no fanout std::string reason; - if (is_removable_block(netlist, blk_id, &reason)) { + if (is_removable_block(netlist, blk_id, models, &reason)) { blocks_to_remove.insert(blk_id); VTR_LOGV_WARN(verbosity > 1, "Block '%s' will be swept (%s)\n", netlist.block_name(blk_id).c_str(), reason.c_str()); @@ -1098,14 +1097,14 @@ size_t sweep_blocks(AtomNetlist& netlist, int verbosity) { return blocks_to_remove.size(); } -size_t sweep_inputs(AtomNetlist& netlist, int verbosity) { +size_t sweep_inputs(AtomNetlist& netlist, const LogicalModels& models, int verbosity) { //Identify any inputs for removal std::unordered_set inputs_to_remove; for (auto blk_id : netlist.blocks()) { if (!blk_id) continue; std::string reason; - if (is_removable_input(netlist, blk_id, &reason)) { + if (is_removable_input(netlist, blk_id, models, &reason)) { inputs_to_remove.insert(blk_id); VTR_LOGV_WARN(verbosity > 1, "Primary input '%s' will be swept (%s)\n", netlist.block_name(blk_id).c_str(), reason.c_str()); @@ -1333,10 +1332,10 @@ void cube_to_minterms_recurr(std::vector cube, std::vector find_netlist_physical_clock_nets(const AtomNetlist& netlist) { +std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist, const LogicalModels& models) { std::set clock_nets; //The clock nets - std::map> clock_gen_ports; //Records info about clock generating ports + vtr::vector_map> clock_gen_ports; //Records info about clock generating ports //Look through all the blocks (except I/Os) to find sink clock pins, or //clock generators @@ -1350,18 +1349,19 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) if (type != AtomBlockType::BLOCK) continue; //Save any clock generating ports on this model type - const t_model* model = netlist.block_model(blk_id); - VTR_ASSERT(model); - if (clock_gen_ports.find(model) == clock_gen_ports.end()) { + LogicalModelId model_id = netlist.block_model(blk_id); + VTR_ASSERT(model_id.is_valid()); + if (clock_gen_ports.find(model_id) == clock_gen_ports.end()) { //First time we've seen this model, initialize it - clock_gen_ports[model] = {}; + clock_gen_ports.insert(model_id, {}); //Look at all the ports to find clock generators - for (const t_model_ports* model_port = model->outputs; model_port; model_port = model_port->next) { + const t_model& model = models.get_model(model_id); + for (const t_model_ports* model_port = model.outputs; model_port; model_port = model_port->next) { VTR_ASSERT(model_port->dir == OUT_PORT); if (model_port->is_clock) { //Clock generator - clock_gen_ports[model].push_back(model_port); + clock_gen_ports[model_id].push_back(model_port); } } } @@ -1377,11 +1377,11 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) } //Look for any generated clocks - if (!clock_gen_ports[model].empty()) { + if (!clock_gen_ports[model_id].empty()) { //This is a clock generator //Check all the clock generating ports - for (const t_model_ports* model_port : clock_gen_ports[model]) { + for (const t_model_ports* model_port : clock_gen_ports[model_id]) { AtomPortId clk_gen_port = netlist.find_atom_port(blk_id, model_port); if (!clk_gen_port) continue; //Port not connected on this block @@ -1402,8 +1402,8 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) } ///@brief Finds all logical clock drivers in the netlist (by back-tracing through logic) -std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist) { - std::set clock_nets = find_netlist_physical_clock_nets(netlist); +std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist, const LogicalModels& models) { + std::set clock_nets = find_netlist_physical_clock_nets(netlist, models); //We now have a set of nets which drive clock pins // @@ -1412,6 +1412,7 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis //to find the true source size_t assumed_buffer_count = 0; std::set prev_clock_nets; + LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); while (prev_clock_nets != clock_nets) { //Still tracing back prev_clock_nets = clock_nets; clock_nets.clear(); @@ -1423,7 +1424,7 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis std::vector upstream_ports; - if (netlist.block_model(driver_blk)->name == std::string(".names")) { + if (netlist.block_model(driver_blk) == names_model_id) { //For .names we allow tracing back through data connections //which allows us to traceback through white-box .names buffers upstream_ports = find_combinationally_connected_input_ports(netlist, driver_port); @@ -1448,7 +1449,7 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis VTR_ASSERT(upstream_net); VTR_LOG_WARN("Assuming clocks may propagate through %s (%s) from pin %s to %s (assuming a non-inverting buffer).\n", - netlist.block_name(driver_blk).c_str(), netlist.block_model(driver_blk)->name, + netlist.block_name(driver_blk).c_str(), models.model_name(netlist.block_model(driver_blk)).c_str(), netlist.pin_name(upstream_pin).c_str(), netlist.pin_name(driver_pin).c_str()); clock_nets.insert(upstream_net); @@ -1483,8 +1484,8 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis } ///@brief Print information about clocks -void print_netlist_clock_info(const AtomNetlist& netlist) { - std::set netlist_clock_drivers = find_netlist_logical_clock_drivers(netlist); +void print_netlist_clock_info(const AtomNetlist& netlist, const LogicalModels& models) { + std::set netlist_clock_drivers = find_netlist_logical_clock_drivers(netlist, models); VTR_LOG("Netlist contains %zu clocks\n", netlist_clock_drivers.size()); //Print out pin/block fanout info for each block @@ -1500,9 +1501,3 @@ void print_netlist_clock_info(const AtomNetlist& netlist) { VTR_LOG(" Netlist Clock '%s' Fanout: %zu pins (%.1f%%), %zu blocks (%.1f%%)\n", netlist.net_name(net_id).c_str(), fanout, 100. * float(fanout) / netlist.pins().size(), clk_blks.size(), 100 * float(clk_blks.size()) / netlist.blocks().size()); } } - -bool is_buffer(const AtomNetlist& netlist, const AtomBlockId blk) { - //For now only support LUT buffers - //TODO: In the future could add support for non-LUT buffers - return is_buffer_lut(netlist, blk); -} diff --git a/vpr/src/base/atom_netlist_utils.h b/vpr/src/base/atom_netlist_utils.h index aaa559d4a73..5bf0791bfad 100644 --- a/vpr/src/base/atom_netlist_utils.h +++ b/vpr/src/base/atom_netlist_utils.h @@ -9,16 +9,18 @@ * @brief Useful utilities for working with the AtomNetlist class */ +class LogicalModels; + /** * @brief Walk through the netlist detecting constant generators * * @note Initial constant generators (e.g. vcc/gnd) should have already * been marked on the netlist. */ -int mark_constant_generators(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, int verbosity); +int mark_constant_generators(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity); ///@brief Modifies the netlist by absorbing buffer LUTs -void absorb_buffer_luts(AtomNetlist& netlist, int verbosity); +void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int verbosity); /* * Modify the netlist by sweeping away unused nets/blocks/inputs @@ -35,16 +37,17 @@ size_t sweep_iterative(AtomNetlist& netlist, bool should_sweep_dangling_nets, bool should_sweep_constant_primary_outputs, e_const_gen_inference const_gen_inference_method, + const LogicalModels& models, int verbosity); ///@brief Sweeps blocks that have no fanout -size_t sweep_blocks(AtomNetlist& netlist, int verbosity); +size_t sweep_blocks(AtomNetlist& netlist, const LogicalModels& models, int verbosity); ///@brief Sweeps nets with no drivers and/or no sinks size_t sweep_nets(AtomNetlist& netlist, int verbosity); ///@brief Sweeps primary-inputs with no fanout -size_t sweep_inputs(AtomNetlist& netlist, int verbosity); +size_t sweep_inputs(AtomNetlist& netlist, const LogicalModels& models, int verbosity); ///@brief Sweeps primary-outputs with no fanin size_t sweep_outputs(AtomNetlist& netlist, int verbosity); @@ -55,9 +58,6 @@ size_t sweep_constant_primary_outputs(AtomNetlist& netlist, int verbosity); * Truth-table operations */ -///@brief Returns true if the specified block is a logical buffer -bool is_buffer(const AtomNetlist& netlist, const AtomBlockId blk); - /** * @brief Deterimine whether a truth table encodes the logic functions 'On' set (returns true) * or 'Off' set (returns false) @@ -96,11 +96,8 @@ std::vector cube_to_minterms(std::vector cube); /* * Print the netlist for debugging */ -void print_netlist_as_blif(std::string filename, const AtomNetlist& netlist); -void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist); - -///@brief Returns a user-friendly architectural identifier for the specified atom pin -std::string atom_pin_arch_name(const AtomNetlist& netlist, const AtomPinId pin); +void print_netlist_as_blif(std::string filename, const AtomNetlist& netlist, const LogicalModels& models); +void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalModels& models); /* * Identify all clock nets @@ -112,7 +109,7 @@ std::string atom_pin_arch_name(const AtomNetlist& netlist, const AtomPinId pin); * @note The returned nets may be logically equivalent (e.g. driven by buffers * connected to a common net) */ -std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist); +std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist, const LogicalModels& models); /** * @brief Returns the set of pins which logically drive unique clocks in the netlist @@ -121,8 +118,8 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) * so logically unique should be viewed as true only to the extent of VPR's * understanding */ -std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist); +std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist, const LogicalModels& models); ///@brief Prints out information about netlist clocks -void print_netlist_clock_info(const AtomNetlist& netlist); +void print_netlist_clock_info(const AtomNetlist& netlist, const LogicalModels& models); #endif diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp index a80e3d7d76c..3d777f3ec4b 100644 --- a/vpr/src/base/check_netlist.cpp +++ b/vpr/src/base/check_netlist.cpp @@ -7,6 +7,7 @@ #include #include +#include "logic_types.h" #include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -128,6 +129,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi static int check_clb_conn(ClusterBlockId iblk, int num_conn) { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& clb_nlist = cluster_ctx.clb_nlist; + const LogicalModels& models = g_vpr_ctx.device().arch->models; int error = 0; t_logical_block_type_ptr type = clb_nlist.block_type(iblk); @@ -136,7 +138,7 @@ static int check_clb_conn(ClusterBlockId iblk, int num_conn) { for (auto pin_id : clb_nlist.block_pins(iblk)) { auto pin_type = clb_nlist.pin_type(pin_id); - if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk)) { + if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk, models)) { //Input only and not a Primary-Output block VTR_LOG_WARN( "Logic block #%d (%s) has only 1 input pin '%s'" @@ -144,7 +146,7 @@ static int check_clb_conn(ClusterBlockId iblk, int num_conn) { iblk, clb_nlist.block_name(iblk).c_str(), clb_nlist.pin_name(pin_id).c_str()); } - if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk)) { + if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk, models)) { //Output only and not a Primary-Input block VTR_LOG_WARN( "Logic block #%d (%s) has only 1 output pin '%s'." diff --git a/vpr/src/base/clustered_netlist.cpp b/vpr/src/base/clustered_netlist.cpp index 2f2fce860a4..8e446d2b4c8 100644 --- a/vpr/src/base/clustered_netlist.cpp +++ b/vpr/src/base/clustered_netlist.cpp @@ -1,5 +1,6 @@ #include "clustered_netlist.h" #include "globals.h" +#include "logic_types.h" #include "physical_types_util.h" #include "vtr_assert.h" @@ -57,16 +58,18 @@ ClusterPinId ClusteredNetlist::block_pin(const ClusterBlockId blk, const int log return block_logical_pins_[blk][logical_pin_index]; } -bool ClusteredNetlist::block_contains_primary_input(const ClusterBlockId blk) const { +bool ClusteredNetlist::block_contains_primary_input(const ClusterBlockId blk, const LogicalModels& models) const { const t_pb* pb = block_pb(blk); - const t_pb* primary_input_pb = pb->find_pb_for_model(".input"); + LogicalModelId input_model_id = models.get_model_by_name(LogicalModels::MODEL_INPUT); + const t_pb* primary_input_pb = pb->find_pb_for_model(input_model_id); return primary_input_pb != nullptr; } ///@brief Returns true if the specified block contains a primary output (e.g. BLIF .output primitive) -bool ClusteredNetlist::block_contains_primary_output(const ClusterBlockId blk) const { +bool ClusteredNetlist::block_contains_primary_output(const ClusterBlockId blk, const LogicalModels& models) const { const t_pb* pb = block_pb(blk); - const t_pb* primary_output_pb = pb->find_pb_for_model(".output"); + LogicalModelId output_model_id = models.get_model_by_name(LogicalModels::MODEL_OUTPUT); + const t_pb* primary_output_pb = pb->find_pb_for_model(output_model_id); return primary_output_pb != nullptr; } diff --git a/vpr/src/base/clustered_netlist.h b/vpr/src/base/clustered_netlist.h index a32e371741c..e8399484adb 100644 --- a/vpr/src/base/clustered_netlist.h +++ b/vpr/src/base/clustered_netlist.h @@ -144,10 +144,10 @@ class ClusteredNetlist : public Netlist delay_calc, + const LogicalModels& models, struct t_analysis_opts opts) : verilog_os_(verilog_os) , blif_os_(blif_os) , sdf_os_(sdf_os) , delay_calc_(delay_calc) + , models_(models) , opts_(opts) { auto& atom_ctx = g_vpr_ctx.atom(); @@ -935,23 +937,24 @@ class NetlistWriterVisitor : public NetlistVisitor { if (atom_pb == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.netlist().block_model(atom_pb); + LogicalModelId model_id = atom_ctx.netlist().block_model(atom_pb); + std::string model_name = models_.model_name(model_id); - if (model->name == std::string(MODEL_INPUT)) { + if (model_name == LogicalModels::MODEL_INPUT) { inputs_.emplace_back(make_io(atom, PortType::INPUT)); - } else if (model->name == std::string(MODEL_OUTPUT)) { + } else if (model_name == LogicalModels::MODEL_OUTPUT) { outputs_.emplace_back(make_io(atom, PortType::OUTPUT)); - } else if (model->name == std::string(MODEL_NAMES)) { + } else if (model_name == LogicalModels::MODEL_NAMES) { cell_instances_.push_back(make_lut_instance(atom)); - } else if (model->name == std::string(MODEL_LATCH)) { + } else if (model_name == LogicalModels::MODEL_LATCH) { cell_instances_.push_back(make_latch_instance(atom)); - } else if (model->name == std::string("single_port_ram")) { + } else if (model_name == std::string("single_port_ram")) { cell_instances_.push_back(make_ram_instance(atom)); - } else if (model->name == std::string("dual_port_ram")) { + } else if (model_name == std::string("dual_port_ram")) { cell_instances_.push_back(make_ram_instance(atom)); - } else if (model->name == std::string("multiply")) { + } else if (model_name == std::string("multiply")) { cell_instances_.push_back(make_multiply_instance(atom)); - } else if (model->name == std::string("adder")) { + } else if (model_name == std::string("adder")) { cell_instances_.push_back(make_adder_instance(atom)); } else { cell_instances_.push_back(make_blackbox_instance(atom)); @@ -1406,7 +1409,7 @@ class NetlistWriterVisitor : public NetlistVisitor { VTR_ASSERT(pb_type->class_type == MEMORY_CLASS); - std::string type = pb_type->model->name; + std::string type = models_.model_name(pb_type->model_id); std::string inst_name = join_identifier(type, atom->name); std::map params; std::map attrs; @@ -1551,7 +1554,7 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb_graph_node* pb_graph_node = atom->pb_graph_node; const t_pb_type* pb_type = pb_graph_node->pb_type; - std::string type_name = pb_type->model->name; + std::string type_name = models_.model_name(pb_type->model_id); std::string inst_name = join_identifier(type_name, atom->name); std::map params; std::map attrs; @@ -1646,7 +1649,7 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb_graph_node* pb_graph_node = atom->pb_graph_node; const t_pb_type* pb_type = pb_graph_node->pb_type; - std::string type_name = pb_type->model->name; + std::string type_name = models_.model_name(pb_type->model_id); std::string inst_name = join_identifier(type_name, atom->name); std::map params; std::map attrs; @@ -1743,7 +1746,7 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb_type* pb_type = pb_graph_node->pb_type; auto& timing_ctx = g_vpr_ctx.timing(); - std::string type_name = pb_type->model->name; + std::string type_name = models_.model_name(pb_type->model_id); std::string inst_name = join_identifier(type_name, atom->name); std::map params; std::map attrs; @@ -1924,8 +1927,9 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb* atom) { //LUT primitive auto& atom_ctx = g_vpr_ctx.atom(); - const t_model* model = atom_ctx.netlist().block_model(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom)); - VTR_ASSERT(model->name == std::string(MODEL_NAMES)); + LogicalModelId model_id = atom_ctx.netlist().block_model(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom)); + std::string model_name = models_.model_name(model_id); + VTR_ASSERT(model_name == LogicalModels::MODEL_NAMES); #ifdef DEBUG_LUT_MASK std::cout << "Loading LUT mask for: " << atom->name << std::endl; @@ -2204,6 +2208,11 @@ class NetlistWriterVisitor : public NetlistVisitor { std::map, tatum::NodeId> pin_id_to_tnode_lookup_; std::shared_ptr delay_calc_; + + protected: + const LogicalModels& models_; + + private: struct t_analysis_opts opts_; }; @@ -2218,8 +2227,9 @@ class MergedNetlistWriterVisitor : public NetlistWriterVisitor { std::ostream& blif_os, /// delay_calc, + const LogicalModels& models, struct t_analysis_opts opts) - : NetlistWriterVisitor(verilog_os, blif_os, sdf_os, delay_calc, opts) {} + : NetlistWriterVisitor(verilog_os, blif_os, sdf_os, delay_calc, models, opts) {} std::map portmap; @@ -2230,27 +2240,28 @@ class MergedNetlistWriterVisitor : public NetlistWriterVisitor { if (atom_pb == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.netlist().block_model(atom_pb); + LogicalModelId model_id = atom_ctx.netlist().block_model(atom_pb); + std::string model_name = models_.model_name(model_id); - if (model->name == std::string(MODEL_INPUT)) { + if (model_name == LogicalModels::MODEL_INPUT) { auto merged_io_name = make_io(atom, PortType::INPUT); if (merged_io_name != "") inputs_.emplace_back(merged_io_name); - } else if (model->name == std::string(MODEL_OUTPUT)) { + } else if (model_name == LogicalModels::MODEL_OUTPUT) { auto merged_io_name = make_io(atom, PortType::OUTPUT); if (merged_io_name != "") outputs_.emplace_back(merged_io_name); - } else if (model->name == std::string(MODEL_NAMES)) { + } else if (model_name == LogicalModels::MODEL_NAMES) { cell_instances_.push_back(make_lut_instance(atom)); - } else if (model->name == std::string(MODEL_LATCH)) { + } else if (model_name == LogicalModels::MODEL_LATCH) { cell_instances_.push_back(make_latch_instance(atom)); - } else if (model->name == std::string("single_port_ram")) { + } else if (model_name == std::string("single_port_ram")) { cell_instances_.push_back(make_ram_instance(atom)); - } else if (model->name == std::string("dual_port_ram")) { + } else if (model_name == std::string("dual_port_ram")) { cell_instances_.push_back(make_ram_instance(atom)); - } else if (model->name == std::string("multiply")) { + } else if (model_name == std::string("multiply")) { cell_instances_.push_back(make_multiply_instance(atom)); - } else if (model->name == std::string("adder")) { + } else if (model_name == std::string("adder")) { cell_instances_.push_back(make_adder_instance(atom)); } else { cell_instances_.push_back(make_blackbox_instance(atom)); @@ -2640,7 +2651,7 @@ std::string join_identifier(std::string lhs, std::string rhs) { // ///@brief Main routine for this file. See netlist_writer.h for details. -void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { +void netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, t_analysis_opts opts) { std::string verilog_filename = basename + "_post_synthesis.v"; std::string blif_filename = basename + "_post_synthesis.blif"; std::string sdf_filename = basename + "_post_synthesis.sdf"; @@ -2653,7 +2664,7 @@ void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { +void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, t_analysis_opts opts) { std::string verilog_filename = basename + "_merged_post_implementation.v"; VTR_LOG("Writing Merged Implementation Netlist: %s\n", verilog_filename.c_str()); @@ -2671,7 +2682,7 @@ void merged_netlist_writer(const std::string basename, std::shared_ptr #include "AnalysisDelayCalculator.h" +class LogicalModels; + /** * @brief Writes out the post-synthesis implementation netlists in BLIF and Verilog formats, * along with an SDF for delay annotations. @@ -14,7 +16,7 @@ * All written filenames end in {basename}_post_synthesis.{fmt} where {basename} is the * basename argument and {fmt} is the file format (e.g. v, blif, sdf) */ -void netlist_writer(const std::string basename, std::shared_ptr delay_calc, t_analysis_opts opts); +void netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, t_analysis_opts opts); /** * @brief Writes out the post implementation netlist in Verilog format. @@ -26,4 +28,4 @@ void netlist_writer(const std::string basename, std::shared_ptr delay_calc, t_analysis_opts opts); +void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, t_analysis_opts opts); diff --git a/vpr/src/base/read_blif.cpp b/vpr/src/base/read_blif.cpp index 807e8c4a8c4..1edda3fa975 100644 --- a/vpr/src/base/read_blif.cpp +++ b/vpr/src/base/read_blif.cpp @@ -18,41 +18,35 @@ #include #include #include -#include #include //std::isdigit #include "blifparse.hpp" #include "atom_netlist.h" +#include "logic_types.h" #include "vtr_assert.h" #include "vtr_util.h" #include "vtr_log.h" #include "vtr_logic.h" -#include "vtr_time.h" #include "vtr_digest.h" -#include "vpr_types.h" #include "vpr_error.h" -#include "globals.h" #include "read_blif.h" -#include "arch_types.h" -#include "echo_files.h" #include "hash.h" vtr::LogicValue to_vtr_logic_value(blifparse::LogicValue); struct BlifAllocCallback : public blifparse::Callback { public: - BlifAllocCallback(e_circuit_format blif_format, AtomNetlist& main_netlist, const std::string netlist_id, const t_model* user_models, const t_model* library_models) + BlifAllocCallback(e_circuit_format blif_format, AtomNetlist& main_netlist, const std::string netlist_id, const LogicalModels& models) : main_netlist_(main_netlist) , netlist_id_(netlist_id) - , user_arch_models_(user_models) - , library_arch_models_(library_models) + , models_(models) , blif_format_(blif_format) { VTR_ASSERT(blif_format_ == e_circuit_format::BLIF || blif_format_ == e_circuit_format::EBLIF); - inpad_model_ = find_model(MODEL_INPUT); - outpad_model_ = find_model(MODEL_OUTPUT); + inpad_model_ = models.get_model_by_name(LogicalModels::MODEL_INPUT); + outpad_model_ = models.get_model_by_name(LogicalModels::MODEL_OUTPUT); main_netlist_.set_block_types(inpad_model_, outpad_model_); } @@ -81,17 +75,18 @@ struct BlifAllocCallback : public blifparse::Callback { } void inputs(std::vector input_names) override { - const t_model* blk_model = find_model(MODEL_INPUT); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_INPUT); + const t_model& blk_model = models_.get_model(blk_model_id); - VTR_ASSERT_MSG(!blk_model->inputs, "Inpad model has an input port"); - VTR_ASSERT_MSG(blk_model->outputs, "Inpad model has no output port"); - VTR_ASSERT_MSG(blk_model->outputs->size == 1, "Inpad model has non-single-bit output port"); - VTR_ASSERT_MSG(!blk_model->outputs->next, "Inpad model has multiple output ports"); + VTR_ASSERT_MSG(!blk_model.inputs, "Inpad model has an input port"); + VTR_ASSERT_MSG(blk_model.outputs, "Inpad model has no output port"); + VTR_ASSERT_MSG(blk_model.outputs->size == 1, "Inpad model has non-single-bit output port"); + VTR_ASSERT_MSG(!blk_model.outputs->next, "Inpad model has multiple output ports"); - std::string pin_name = blk_model->outputs->name; + std::string pin_name = blk_model.outputs->name; for (const auto& input : input_names) { - AtomBlockId blk_id = curr_model().create_block(input, blk_model); - AtomPortId port_id = curr_model().create_port(blk_id, blk_model->outputs); + AtomBlockId blk_id = curr_model().create_block(input, blk_model_id); + AtomPortId port_id = curr_model().create_port(blk_id, blk_model.outputs); AtomNetId net_id = curr_model().create_net(input); curr_model().create_pin(port_id, 0, net_id, PinType::DRIVER); } @@ -99,19 +94,20 @@ struct BlifAllocCallback : public blifparse::Callback { } void outputs(std::vector output_names) override { - const t_model* blk_model = find_model(MODEL_OUTPUT); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_OUTPUT); + const t_model& blk_model = models_.get_model(blk_model_id); - VTR_ASSERT_MSG(!blk_model->outputs, "Outpad model has an output port"); - VTR_ASSERT_MSG(blk_model->inputs, "Outpad model has no input port"); - VTR_ASSERT_MSG(blk_model->inputs->size == 1, "Outpad model has non-single-bit input port"); - VTR_ASSERT_MSG(!blk_model->inputs->next, "Outpad model has multiple input ports"); + VTR_ASSERT_MSG(!blk_model.outputs, "Outpad model has an output port"); + VTR_ASSERT_MSG(blk_model.inputs, "Outpad model has no input port"); + VTR_ASSERT_MSG(blk_model.inputs->size == 1, "Outpad model has non-single-bit input port"); + VTR_ASSERT_MSG(!blk_model.inputs->next, "Outpad model has multiple input ports"); - std::string pin_name = blk_model->inputs->name; + std::string pin_name = blk_model.inputs->name; for (const auto& output : output_names) { //Since we name blocks based on their drivers we need to uniquify outpad names, //which we do with a prefix - AtomBlockId blk_id = curr_model().create_block(OUTPAD_NAME_PREFIX + output, blk_model); - AtomPortId port_id = curr_model().create_port(blk_id, blk_model->inputs); + AtomBlockId blk_id = curr_model().create_block(OUTPAD_NAME_PREFIX + output, blk_model_id); + AtomPortId port_id = curr_model().create_port(blk_id, blk_model.inputs); AtomNetId net_id = curr_model().create_net(output); curr_model().create_pin(port_id, 0, net_id, PinType::SINK); } @@ -119,20 +115,21 @@ struct BlifAllocCallback : public blifparse::Callback { } void names(std::vector nets, std::vector> so_cover) override { - const t_model* blk_model = find_model(MODEL_NAMES); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_NAMES); + const t_model& blk_model = models_.get_model(blk_model_id); VTR_ASSERT_MSG(nets.size() > 0, "BLIF .names has no connections"); - VTR_ASSERT_MSG(blk_model->inputs, ".names model has no input port"); - VTR_ASSERT_MSG(!blk_model->inputs->next, ".names model has multiple input ports"); - if (static_cast(nets.size()) - 1 > blk_model->inputs->size) { + VTR_ASSERT_MSG(blk_model.inputs, ".names model has no input port"); + VTR_ASSERT_MSG(!blk_model.inputs->next, ".names model has multiple input ports"); + if (static_cast(nets.size()) - 1 > blk_model.inputs->size) { vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "BLIF .names input size (%zu) greater than .names model input size (%d)", - nets.size() - 1, blk_model->inputs->size); + nets.size() - 1, blk_model.inputs->size); } - VTR_ASSERT_MSG(blk_model->outputs, ".names has no output port"); - VTR_ASSERT_MSG(!blk_model->outputs->next, ".names model has multiple output ports"); - VTR_ASSERT_MSG(blk_model->outputs->size == 1, ".names model has non-single-bit output"); + VTR_ASSERT_MSG(blk_model.outputs, ".names has no output port"); + VTR_ASSERT_MSG(!blk_model.outputs->next, ".names model has multiple output ports"); + VTR_ASSERT_MSG(blk_model.outputs->size == 1, ".names model has non-single-bit output"); //Convert the single-output cover to a netlist truth table AtomNetlist::TruthTable truth_table; @@ -143,11 +140,11 @@ struct BlifAllocCallback : public blifparse::Callback { } } - AtomBlockId blk_id = curr_model().create_block(nets[nets.size() - 1], blk_model, truth_table); + AtomBlockId blk_id = curr_model().create_block(nets[nets.size() - 1], blk_model_id, truth_table); set_curr_block(blk_id); //Create inputs - AtomPortId input_port_id = curr_model().create_port(blk_id, blk_model->inputs); + AtomPortId input_port_id = curr_model().create_port(blk_id, blk_model.inputs); for (size_t i = 0; i < nets.size() - 1; ++i) { AtomNetId net_id = curr_model().create_net(nets[i]); @@ -187,7 +184,7 @@ struct BlifAllocCallback : public blifparse::Callback { //Create output AtomNetId net_id = curr_model().create_net(nets[nets.size() - 1]); - AtomPortId output_port_id = curr_model().create_port(blk_id, blk_model->outputs); + AtomPortId output_port_id = curr_model().create_port(blk_id, blk_model.outputs); curr_model().create_pin(output_port_id, 0, net_id, PinType::DRIVER, output_is_const); } @@ -202,17 +199,18 @@ struct BlifAllocCallback : public blifparse::Callback { vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Latch must have a clock\n"); } - const t_model* blk_model = find_model(MODEL_LATCH); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_LATCH); + const t_model& blk_model = models_.get_model(blk_model_id); - VTR_ASSERT_MSG(blk_model->inputs, "Has one input port"); - VTR_ASSERT_MSG(blk_model->inputs->next, "Has two input port"); - VTR_ASSERT_MSG(!blk_model->inputs->next->next, "Has no more than two input port"); - VTR_ASSERT_MSG(blk_model->outputs, "Has one output port"); - VTR_ASSERT_MSG(!blk_model->outputs->next, "Has no more than one input port"); + VTR_ASSERT_MSG(blk_model.inputs, "Has one input port"); + VTR_ASSERT_MSG(blk_model.inputs->next, "Has two input port"); + VTR_ASSERT_MSG(!blk_model.inputs->next->next, "Has no more than two input port"); + VTR_ASSERT_MSG(blk_model.outputs, "Has one output port"); + VTR_ASSERT_MSG(!blk_model.outputs->next, "Has no more than one input port"); - const t_model_ports* d_model_port = blk_model->inputs; - const t_model_ports* clk_model_port = blk_model->inputs->next; - const t_model_ports* q_model_port = blk_model->outputs; + const t_model_ports* d_model_port = blk_model.inputs; + const t_model_ports* clk_model_port = blk_model.inputs->next; + const t_model_ports* q_model_port = blk_model.outputs; VTR_ASSERT(d_model_port->name == std::string("D")); VTR_ASSERT(clk_model_port->name == std::string("clk")); @@ -226,7 +224,7 @@ struct BlifAllocCallback : public blifparse::Callback { AtomNetlist::TruthTable truth_table(1); truth_table[0].push_back(to_vtr_logic_value(init)); - AtomBlockId blk_id = curr_model().create_block(output, blk_model, truth_table); + AtomBlockId blk_id = curr_model().create_block(output, blk_model_id, truth_table); set_curr_block(blk_id); //The input @@ -248,7 +246,8 @@ struct BlifAllocCallback : public blifparse::Callback { void subckt(std::string subckt_model, std::vector ports, std::vector nets) override { VTR_ASSERT(ports.size() == nets.size()); - const t_model* blk_model = find_model(subckt_model); + LogicalModelId blk_model_id = models_.get_model_by_name(subckt_model); + const t_model& blk_model = models_.get_model(blk_model_id); //We name the subckt based on the net it's first output pin drives std::string subckt_name; @@ -269,21 +268,21 @@ struct BlifAllocCallback : public blifparse::Callback { //Since this is unusual, warn the user VTR_LOGF_WARN(filename_.c_str(), lineno_, "Subckt of type '%s' at %s:%d has no output pins, and has been named '%s'\n", - blk_model->name, filename_.c_str(), lineno_, subckt_name.c_str()); + blk_model.name, filename_.c_str(), lineno_, subckt_name.c_str()); } //The name for every block should be unique, check that there is no name conflict AtomBlockId blk_id = curr_model().find_block(subckt_name); if (blk_id) { - const t_model* conflicting_model = curr_model().block_model(blk_id); + LogicalModelId conflicting_model = curr_model().block_model(blk_id); vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Duplicate blocks named '%s' found in netlist." " Existing block of type '%s' conflicts with subckt of type '%s'.", - subckt_name.c_str(), conflicting_model->name, subckt_model.c_str()); + subckt_name.c_str(), models_.get_model(conflicting_model).name, subckt_model.c_str()); } //Create the block - blk_id = curr_model().create_block(subckt_name, blk_model); + blk_id = curr_model().create_block(subckt_name, blk_model_id); set_curr_block(blk_id); for (size_t i = 0; i < ports.size(); ++i) { @@ -443,30 +442,7 @@ struct BlifAllocCallback : public blifparse::Callback { } private: - const t_model* find_model(std::string_view name) { - const t_model* arch_model = nullptr; - for (const t_model* arch_models : {user_arch_models_, library_arch_models_}) { - arch_model = arch_models; - while (arch_model) { - if (name == arch_model->name) { - //Found it - break; - } - arch_model = arch_model->next; - } - if (arch_model) { - //Found it - break; - } - } - if (!arch_model) { - vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Failed to find matching architecture model for '%s'\n", - name.data()); - } - return arch_model; - } - - const t_model_ports* find_model_port(const t_model* blk_model, const std::string& port_name) { + const t_model_ports* find_model_port(const t_model& blk_model, const std::string& port_name) { //We need to handle both single, and multi-bit port names // //By convention multi-bit port names have the bit index stored in square brackets @@ -485,7 +461,7 @@ struct BlifAllocCallback : public blifparse::Callback { VTR_ASSERT(bit_index >= 0); //We now look through all the ports on the model looking for the matching port - for (const t_model_ports* ports : {blk_model->inputs, blk_model->outputs}) { + for (const t_model_ports* ports : {blk_model.inputs, blk_model.outputs}) { const t_model_ports* curr_port = ports; while (curr_port) { if (trimmed_port_name == curr_port->name) { @@ -497,7 +473,7 @@ struct BlifAllocCallback : public blifparse::Callback { //Out of range vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Port '%s' on architecture model '%s' exceeds port width (%d bits)\n", - port_name.c_str(), blk_model->name, curr_port->size); + port_name.c_str(), blk_model.name, curr_port->size); } } curr_port = curr_port->next; @@ -507,7 +483,7 @@ struct BlifAllocCallback : public blifparse::Callback { //No match vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Found no matching port '%s' on architecture model '%s'\n", - port_name.c_str(), blk_model->name); + port_name.c_str(), blk_model.name); return nullptr; } @@ -563,7 +539,8 @@ struct BlifAllocCallback : public blifparse::Callback { } bool verify_blackbox_model(AtomNetlist& blif_model) { - const t_model* arch_model = find_model(blif_model.netlist_name()); + LogicalModelId arch_model_id = models_.get_model_by_name(blif_model.netlist_name()); + const t_model& arch_model = models_.get_model(arch_model_id); //Verify each port on the model // @@ -639,10 +616,9 @@ struct BlifAllocCallback : public blifparse::Callback { AtomNetlist& main_netlist_; /// #include "atom_netlist_fwd.h" #include "read_circuit.h" +class LogicalModels; + bool is_string_param(const std::string& param); bool is_binary_param(const std::string& param); bool is_real_param(const std::string& param); AtomNetlist read_blif(e_circuit_format circuit_format, const char* blif_file, - const t_model* user_models, - const t_model* library_models); + const LogicalModels& models); #endif /*READ_BLIF_H*/ diff --git a/vpr/src/base/read_circuit.cpp b/vpr/src/base/read_circuit.cpp index 4d6fab3f25d..f1112d92016 100644 --- a/vpr/src/base/read_circuit.cpp +++ b/vpr/src/base/read_circuit.cpp @@ -1,4 +1,5 @@ #include "read_circuit.h" +#include "logic_types.h" #include "read_blif.h" #include "read_interchange_netlist.h" #include "atom_netlist.h" @@ -16,15 +17,14 @@ static void process_circuit(AtomNetlist& netlist, bool should_sweep_dangling_nets, bool should_sweep_dangling_blocks, bool should_sweep_constant_primary_outputs, + const LogicalModels& models, int verbosity); -static void show_circuit_stats(const AtomNetlist& netlist); +static void show_circuit_stats(const AtomNetlist& netlist, const LogicalModels& models); AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setup& vpr_setup, t_arch& arch) { // Options const char* circuit_file = vpr_setup.PackerOpts.circuit_file_name.c_str(); - const t_model* user_models = vpr_setup.user_models; - const t_model* library_models = vpr_setup.library_models; e_const_gen_inference const_gen_inference = vpr_setup.NetlistOpts.const_gen_inference; bool should_absorb_buffers = vpr_setup.NetlistOpts.absorb_buffer_luts; bool should_sweep_dangling_primary_ios = vpr_setup.NetlistOpts.sweep_dangling_primary_ios; @@ -54,7 +54,7 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu switch (circuit_format) { case e_circuit_format::BLIF: case e_circuit_format::EBLIF: - netlist = read_blif(circuit_format, circuit_file, user_models, library_models); + netlist = read_blif(circuit_format, circuit_file, arch.models); break; case e_circuit_format::FPGA_INTERCHANGE: netlist = read_interchange_netlist(circuit_file, arch); @@ -68,7 +68,7 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu } if (isEchoFileEnabled(E_ECHO_ATOM_NETLIST_ORIG)) { - print_netlist_as_blif(getEchoFileName(E_ECHO_ATOM_NETLIST_ORIG), netlist); + print_netlist_as_blif(getEchoFileName(E_ECHO_ATOM_NETLIST_ORIG), netlist, arch.models); } process_circuit(netlist, @@ -78,13 +78,14 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu should_sweep_dangling_nets, should_sweep_dangling_blocks, should_sweep_constant_primary_outputs, + arch.models, verbosity); if (isEchoFileEnabled(E_ECHO_ATOM_NETLIST_CLEANED)) { - print_netlist_as_blif(getEchoFileName(E_ECHO_ATOM_NETLIST_CLEANED), netlist); + print_netlist_as_blif(getEchoFileName(E_ECHO_ATOM_NETLIST_CLEANED), netlist, arch.models); } - show_circuit_stats(netlist); + show_circuit_stats(netlist, arch.models); return netlist; } @@ -96,13 +97,14 @@ static void process_circuit(AtomNetlist& netlist, bool should_sweep_dangling_nets, bool should_sweep_dangling_blocks, bool should_sweep_constant_primary_outputs, + const LogicalModels& models, int verbosity) { { vtr::ScopedStartFinishTimer t("Clean circuit"); //Clean-up lut buffers if (should_absorb_buffers) { - absorb_buffer_luts(netlist, verbosity); + absorb_buffer_luts(netlist, models, verbosity); } //Remove the special 'unconn' net @@ -126,6 +128,7 @@ static void process_circuit(AtomNetlist& netlist, should_sweep_dangling_blocks, should_sweep_constant_primary_outputs, const_gen_inference_method, + models, verbosity); } @@ -142,17 +145,19 @@ static void process_circuit(AtomNetlist& netlist, } } -static void show_circuit_stats(const AtomNetlist& netlist) { +static void show_circuit_stats(const AtomNetlist& netlist, const LogicalModels& models) { // Count the block statistics std::map block_type_counts; std::map lut_size_counts; + LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); for (auto blk_id : netlist.blocks()) { // For each model, count the number of occurrences in the netlist. - const t_model* blk_model = netlist.block_model(blk_id); - ++block_type_counts[blk_model->name]; + LogicalModelId blk_model_id = netlist.block_model(blk_id); + std::string blk_model_name = models.get_model(blk_model_id).name; + ++block_type_counts[blk_model_name]; // If this block is a LUT, also count the occurences of this size of LUT // for more logging information. - if (blk_model->name == std::string(MODEL_NAMES)) { + if (blk_model_id == names_model_id) { // May have zero (no input LUT) or one input port auto in_ports = netlist.block_input_ports(blk_id); VTR_ASSERT(in_ports.size() <= 1 && "Expected number of input ports for LUT to be 0 or 1"); @@ -205,7 +210,7 @@ static void show_circuit_stats(const AtomNetlist& netlist) { VTR_LOG(" %-*s: %7zu\n", max_block_type_len, kv.first.c_str(), kv.second); // If this block is a LUT, print the different sizes of LUTs in the // design. - if (kv.first == std::string(MODEL_NAMES)) { + if (kv.first == LogicalModels::MODEL_NAMES) { for (const auto& lut_kv : lut_size_counts) { VTR_LOG(" %-*s: %7zu\n", max_lut_size_len, lut_kv.first.c_str(), lut_kv.second); } @@ -215,7 +220,7 @@ static void show_circuit_stats(const AtomNetlist& netlist) { for (const auto& kv : net_stats) { VTR_LOG(" %-*s: %7.1f\n", max_net_type_len, kv.first.c_str(), kv.second); } - VTR_LOG(" Netlist Clocks: %zu\n", find_netlist_logical_clock_drivers(netlist).size()); + VTR_LOG(" Netlist Clocks: %zu\n", find_netlist_logical_clock_drivers(netlist, models).size()); if (netlist.blocks().empty()) { VTR_LOG_WARN("Netlist contains no blocks\n"); diff --git a/vpr/src/base/read_circuit.h b/vpr/src/base/read_circuit.h index 90be01a3891..89f42f7ec61 100644 --- a/vpr/src/base/read_circuit.h +++ b/vpr/src/base/read_circuit.h @@ -1,8 +1,10 @@ #ifndef VPR_READ_CIRCUIT_H #define VPR_READ_CIRCUIT_H -#include "logic_types.h" + #include "atom_netlist_fwd.h" -#include "vpr_types.h" + +struct t_vpr_setup; +struct t_arch; enum class e_circuit_format { AUTO, ///outputs); + blk_id = main_netlist_.create_block(port_name, input_model_id); + port_id = main_netlist_.create_port(blk_id, input_model.outputs); net_id = main_netlist_.create_net(port_name); main_netlist_.create_pin(port_id, 0, net_id, PinType::DRIVER); break; case LogicalNetlist::Netlist::Direction::OUTPUT: - blk_id = main_netlist_.create_block(port_name, output_model); - port_id = main_netlist_.create_port(blk_id, output_model->inputs); + blk_id = main_netlist_.create_block(port_name, output_model_id); + port_id = main_netlist_.create_port(blk_id, output_model.inputs); net_id = main_netlist_.create_net(port_name); main_netlist_.create_pin(port_id, 0, net_id, PinType::SINK); break; @@ -188,13 +187,14 @@ struct NetlistReader { } void read_names() { - const t_model* blk_model = find_model(MODEL_NAMES); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_NAMES); + const t_model& blk_model = models_.get_model(blk_model_id); // Set the max size of the LUT int lut_size = 0; for (auto lut : arch_.lut_cells) lut_size = std::max((int)lut.inputs.size(), lut_size); - blk_model->inputs[0].size = lut_size; + blk_model.inputs[0].size = lut_size; auto top_cell = nr_.getCellList()[nr_.getTopInst().getCell()]; auto decl_list = nr_.getCellDecls(); @@ -317,10 +317,10 @@ struct NetlistReader { VTR_LOG("Found constant-one generator '%s'\n", inst_name.c_str()); } - AtomBlockId blk_id = main_netlist_.create_block(inst_name, blk_model, truth_table); + AtomBlockId blk_id = main_netlist_.create_block(inst_name, blk_model_id, truth_table); - AtomPortId iport_id = main_netlist_.create_port(blk_id, blk_model->inputs); - AtomPortId oport_id = main_netlist_.create_port(blk_id, blk_model->outputs); + AtomPortId iport_id = main_netlist_.create_port(blk_id, blk_model.inputs); + AtomPortId oport_id = main_netlist_.create_port(blk_id, blk_model.outputs); auto cell_lib = decl_list[inst_list[inst_idx].getCell()]; auto port_net_map = port_net_maps_.at(inst_idx); @@ -373,7 +373,8 @@ struct NetlistReader { auto cell_idx = inst_pair.second; auto model_name = str_list[decl_list[cell_idx].getName()]; - const t_model* blk_model = find_model(model_name); + LogicalModelId blk_model_id = models_.get_model_by_name(model_name); + const t_model& blk_model = models_.get_model(blk_model_id); std::string inst_name = str_list[inst_list[inst_idx].getName()]; VTR_ASSERT(inst_name.empty() == 0); @@ -381,11 +382,11 @@ struct NetlistReader { //The name for every block should be unique, check that there is no name conflict AtomBlockId blk_id = main_netlist_.find_block(inst_name); if (blk_id) { - const t_model* conflicting_model = main_netlist_.block_model(blk_id); + LogicalModelId conflicting_model = main_netlist_.block_model(blk_id); vpr_throw(VPR_ERROR_IC_NETLIST_F, netlist_file_, -1, "Duplicate blocks named '%s' found in netlist." " Existing block of type '%s' conflicts with subckt of type '%s'.", - inst_name.c_str(), conflicting_model->name, blk_model->name); + inst_name.c_str(), models_.get_model(conflicting_model).name, blk_model.name); } auto port_net_map = port_net_maps_.at(inst_idx); @@ -400,7 +401,7 @@ struct NetlistReader { continue; //Create the block - blk_id = main_netlist_.create_block(inst_name, blk_model); + blk_id = main_netlist_.create_block(inst_name, blk_model_id); std::unordered_set added_ports; for (auto port_net : port_net_map) { @@ -440,7 +441,7 @@ struct NetlistReader { } // Bind unconnected ports to VCC by default - for (const t_model_ports* ports : {blk_model->inputs, blk_model->outputs}) { + for (const t_model_ports* ports : {blk_model.inputs, blk_model.outputs}) { for (const t_model_ports* port = ports; port != nullptr; port = port->next) { AtomPortId port_id = main_netlist_.create_port(blk_id, port); @@ -465,18 +466,9 @@ struct NetlistReader { // // Utilities // - const t_model* find_model(std::string name) { - for (const auto models : {arch_.models, arch_.model_library}) - for (const t_model* model = models; model != nullptr; model = model->next) - if (name == model->name) - return model; - - vpr_throw(VPR_ERROR_IC_NETLIST_F, netlist_file_, -1, "Failed to find matching architecture model for '%s'\n", name.c_str()); - } - - const t_model_ports* find_model_port(const t_model* blk_model, std::string name) { + const t_model_ports* find_model_port(const t_model& blk_model, std::string name) { //We now look through all the ports on the model looking for the matching port - for (const t_model_ports* ports : {blk_model->inputs, blk_model->outputs}) + for (const t_model_ports* ports : {blk_model.inputs, blk_model.outputs}) for (const t_model_ports* port = ports; port != nullptr; port = port->next) if (name == std::string(port->name)) return port; @@ -484,7 +476,7 @@ struct NetlistReader { //No match vpr_throw(VPR_ERROR_IC_NETLIST_F, netlist_file_, -1, "Found no matching port '%s' on architecture model '%s'\n", - name.c_str(), blk_model->name); + name.c_str(), blk_model.name); return nullptr; } @@ -568,7 +560,7 @@ AtomNetlist read_interchange_netlist(const char* ic_netlist_file, auto netlist_reader = message_reader.getRoot(); - NetlistReader reader(netlist, netlist_reader, netlist_id, ic_netlist_file, arch); + NetlistReader reader(netlist, netlist_reader, netlist_id, ic_netlist_file, arch.models, arch); return netlist; diff --git a/vpr/src/base/read_interchange_netlist.h b/vpr/src/base/read_interchange_netlist.h index 1b17b86ea5d..02a7546c660 100644 --- a/vpr/src/base/read_interchange_netlist.h +++ b/vpr/src/base/read_interchange_netlist.h @@ -1,8 +1,9 @@ #ifndef READ_INTERCHANGE_NETLIST_H #define READ_INTERCHANGE_NETLIST_H -#include "logic_types.h" + #include "atom_netlist_fwd.h" -#include "read_circuit.h" + +struct t_arch; AtomNetlist read_interchange_netlist(const char* ic_netlist_file, t_arch& arch); diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index 5a39ccfef37..b498b8671b2 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -1092,7 +1092,7 @@ static size_t mark_constant_generators_rec(const t_pb* pb, const t_pb_routes& pb } } } - } else if (strcmp(pb->pb_graph_node->pb_type->blif_model, MODEL_INPUT) != 0) { + } else if (strcmp(pb->pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT) != 0) { const_gen = true; for (i = 0; i < pb->pb_graph_node->num_input_ports && const_gen == true; i++) { for (j = 0; j < pb->pb_graph_node->num_input_pins[i] && const_gen == true; j++) { @@ -1184,7 +1184,7 @@ static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { VTR_ASSERT_MSG(pb, "Atom block must have a matching PB"); const t_pb_graph_node* gnode = pb->pb_graph_node; - VTR_ASSERT_MSG(gnode->pb_type->model == atom_ctx.netlist().block_model(blk), + VTR_ASSERT_MSG(gnode->pb_type->model_id == atom_ctx.netlist().block_model(blk), "Atom block PB must match BLIF model"); for (int iport = 0; iport < gnode->num_input_ports; ++iport) { diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 928839410f2..2c84a6a7681 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -285,8 +285,6 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a true, &vpr_setup->FileNameOpts, arch, - &vpr_setup->user_models, - &vpr_setup->library_models, &vpr_setup->NetlistOpts, &vpr_setup->PackerOpts, &vpr_setup->PlacerOpts, @@ -336,17 +334,17 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a auto& timing_ctx = g_vpr_ctx.mutable_timing(); { vtr::ScopedStartFinishTimer t("Build Timing Graph"); - timing_ctx.graph = TimingGraphBuilder(atom_ctx.netlist(), atom_ctx.mutable_lookup()).timing_graph(options->allow_dangling_combinational_nodes); + timing_ctx.graph = TimingGraphBuilder(atom_ctx.netlist(), atom_ctx.mutable_lookup(), arch->models).timing_graph(options->allow_dangling_combinational_nodes); VTR_LOG(" Timing Graph Nodes: %zu\n", timing_ctx.graph->nodes().size()); VTR_LOG(" Timing Graph Edges: %zu\n", timing_ctx.graph->edges().size()); VTR_LOG(" Timing Graph Levels: %zu\n", timing_ctx.graph->levels().size()); } { - print_netlist_clock_info(atom_ctx.netlist()); + print_netlist_clock_info(atom_ctx.netlist(), arch->models); } { vtr::ScopedStartFinishTimer t("Load Timing Constraints"); - timing_ctx.constraints = read_sdc(vpr_setup->Timing, atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph); + timing_ctx.constraints = read_sdc(vpr_setup->Timing, atom_ctx.netlist(), atom_ctx.lookup(), arch->models, *timing_ctx.graph); } { set_terminate_if_timing_fails(options->terminate_if_timing_fails); @@ -512,8 +510,6 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.mutable_device(); - device_ctx.arch = &Arch; - /* *Load the device grid */ @@ -648,6 +644,7 @@ bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch) { // The Prepacker object performs prepacking and stores the pack molecules. // As long as the molecules are used, this object must persist. const Prepacker prepacker(g_vpr_ctx.atom().netlist(), + arch.models, g_vpr_ctx.device().logical_block_types); // Setup pre-clustering timing analysis @@ -732,7 +729,6 @@ bool vpr_load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { // set up the device grid for the legalizer auto& device_ctx = g_vpr_ctx.mutable_device(); - device_ctx.arch = &arch; device_ctx.grid = create_device_grid(vpr_setup.device_layout, arch.grid_layouts); if (device_ctx.grid.get_num_layers() > 1) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Legalizer currently only supports single layer devices.\n"); @@ -1289,8 +1285,6 @@ void vpr_setup_vpr(t_options* Options, const bool readArchFile, t_file_name_opts* FileNameOpts, t_arch* Arch, - t_model** user_models, - t_model** library_models, t_netlist_opts* NetlistOpts, t_packer_opts* PackerOpts, t_placer_opts* PlacerOpts, @@ -1314,8 +1308,6 @@ void vpr_setup_vpr(t_options* Options, readArchFile, FileNameOpts, Arch, - user_models, - library_models, NetlistOpts, PackerOpts, PlacerOpts, @@ -1476,12 +1468,12 @@ void vpr_analysis(const Netlist<>& net_list, //Write the post-synthesis netlist if (vpr_setup.AnalysisOpts.gen_post_synthesis_netlist) { netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, - vpr_setup.AnalysisOpts); + Arch.models, vpr_setup.AnalysisOpts); } //Write the post-implementation merged netlist if (vpr_setup.AnalysisOpts.gen_post_implementation_merged_netlist) { - merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, vpr_setup.AnalysisOpts); + merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, Arch.models, vpr_setup.AnalysisOpts); } //Do power analysis diff --git a/vpr/src/base/vpr_api.h b/vpr/src/base/vpr_api.h index 7eda169ba5e..28324e60da1 100644 --- a/vpr/src/base/vpr_api.h +++ b/vpr/src/base/vpr_api.h @@ -178,8 +178,6 @@ void vpr_setup_vpr(t_options* Options, const bool readArchFile, t_file_name_opts* FileNameOpts, t_arch* Arch, - t_model** user_models, - t_model** library_models, t_netlist_opts* NetlistOpts, t_packer_opts* PackerOpts, t_placer_opts* PlacerOpts, diff --git a/vpr/src/base/vpr_types.cpp b/vpr/src/base/vpr_types.cpp index 22a644a2d07..4d97816558b 100644 --- a/vpr/src/base/vpr_types.cpp +++ b/vpr/src/base/vpr_types.cpp @@ -2,6 +2,7 @@ #include #include "vpr_types.h" #include "globals.h" +#include "logic_types.h" t_ext_pin_util_targets::t_ext_pin_util_targets(float default_in_util, float default_out_util) { defaults_.input_pin_util = default_in_util; @@ -362,10 +363,10 @@ t_pb* t_pb::find_mutable_pb(const t_pb_graph_node* gnode) { return nullptr; //Not found } -const t_pb* t_pb::find_pb_for_model(const std::string& blif_model) const { +const t_pb* t_pb::find_pb_for_model(LogicalModelId blif_model_id) const { //Base case - const t_model* model = pb_graph_node->pb_type->model; - if (model && model->name == blif_model) { + LogicalModelId model_id = pb_graph_node->pb_type->model_id; + if (model_id.is_valid() && model_id == blif_model_id) { return this; } @@ -376,7 +377,7 @@ const t_pb* t_pb::find_pb_for_model(const std::string& blif_model) const { for (int ipb = 0; ipb < get_num_children_of_type(ichild_type); ++ipb) { const t_pb* child_pb = &child_pbs[ichild_type][ipb]; - const t_pb* matching_pb = child_pb->find_pb_for_model(blif_model); + const t_pb* matching_pb = child_pb->find_pb_for_model(blif_model_id); if (matching_pb) { return this; } diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index f71720325a5..106070c4c97 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -311,7 +311,7 @@ class t_pb { */ t_pb* find_mutable_pb(const t_pb_graph_node* gnode); - const t_pb* find_pb_for_model(const std::string& blif_model) const; + const t_pb* find_pb_for_model(LogicalModelId blif_model_id) const; ///@brief Returns the root pb containing this pb const t_pb* root_pb() const; @@ -1502,8 +1502,6 @@ struct t_server_opts { struct t_vpr_setup { bool TimingEnabled; ///models; AtomPortId port_id = atom_ctx.netlist().pin_port(pin_id); const t_model_ports* model_port = atom_ctx.netlist().port_model(port_id); @@ -634,8 +635,8 @@ void find_pin_index_at_model_scope(const AtomPinId pin_id, const AtomBlockId blk // Note that we do this on the model since the atom netlist doesn't include unused ports int pin_cnt = 0; *pin_index = -1; //initialize - const t_model* model = atom_ctx.netlist().block_model(blk_id); - for (const t_model_ports* port : {model->inputs, model->outputs}) { + const t_model& model = models.get_model(atom_ctx.netlist().block_model(blk_id)); + for (const t_model_ports* port : {model.inputs, model.outputs}) { while (port) { if (port == model_port) { //This is the port the pin is associated with, record it's index diff --git a/vpr/src/pack/cluster_legalizer.cpp b/vpr/src/pack/cluster_legalizer.cpp index 947fbed2fbd..0c0040ac3e7 100644 --- a/vpr/src/pack/cluster_legalizer.cpp +++ b/vpr/src/pack/cluster_legalizer.cpp @@ -323,6 +323,7 @@ static enum e_block_pack_status check_chain_root_placement_feasibility(const t_p */ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_type, const AtomBlockId sibling_blk_id) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; VTR_ASSERT(cur_pb_type->class_type == MEMORY_CLASS); @@ -343,8 +344,8 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ //Since the atom netlist stores only in-use ports, we iterate over the model to ensure //all ports are compared - const t_model* model = cur_pb_type->model; - for (t_model_ports* port : {model->inputs, model->outputs}) { + const t_model& model = models.get_model(cur_pb_type->model_id); + for (t_model_ports* port : {model.inputs, model.outputs}) { for (; port; port = port->next) { if (data_ports.count(port)) { //Don't check data ports @@ -441,6 +442,7 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, const vtr::vector_map& clustering_chain_info, AtomPBBimap& atom_to_pb) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; VTR_ASSERT_SAFE(cb != nullptr); e_block_pack_status block_pack_status = e_block_pack_status::BLK_PASSED; @@ -553,7 +555,7 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, VTR_LOGV(verbosity > 4 && block_pack_status == e_block_pack_status::BLK_PASSED, "\t\t\tPlaced atom '%s' (%s) at %s\n", atom_ctx.netlist().block_name(blk_id).c_str(), - atom_ctx.netlist().block_model(blk_id)->name, + models.model_name(atom_ctx.netlist().block_model(blk_id)).c_str(), pb->hierarchical_type_name().c_str()); } @@ -1133,6 +1135,8 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(PackMoleculeId molecule_ // constraints. const FloorplanningContext& floorplanning_ctx = g_vpr_ctx.floorplanning(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; + // Get the molecule object. const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); @@ -1140,7 +1144,7 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(PackMoleculeId molecule_ AtomBlockId root_atom = molecule.atom_block_ids[molecule.root]; VTR_LOG("\t\tTry pack molecule: '%s' (%s)", atom_ctx.netlist().block_name(root_atom).c_str(), - atom_ctx.netlist().block_model(root_atom)->name); + models.model_name(atom_ctx.netlist().block_model(root_atom)).c_str()); VTR_LOGV(molecule.pack_pattern, " molecule_type %s molecule_size %zu", molecule.pack_pattern->name, @@ -1600,6 +1604,7 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, const t_pack_high_fanout_thresholds& high_fanout_thresholds, ClusterLegalizationStrategy cluster_legalization_strategy, bool enable_pin_feasibility_filter, + const LogicalModels& models, int log_verbosity) : prepacker_(prepacker) { // Verify that the inputs are valid. @@ -1620,7 +1625,7 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, // Get a reference to the rr graphs. lb_type_rr_graphs_ = lb_type_rr_graphs; // Find all NoC router atoms. - std::vector noc_atoms = find_noc_router_atoms(atom_netlist); + std::vector noc_atoms = find_noc_router_atoms(atom_netlist, models); update_noc_reachability_partitions(noc_atoms, atom_netlist, high_fanout_thresholds, diff --git a/vpr/src/pack/cluster_legalizer.h b/vpr/src/pack/cluster_legalizer.h index 418bff73d95..8cdd42df298 100644 --- a/vpr/src/pack/cluster_legalizer.h +++ b/vpr/src/pack/cluster_legalizer.h @@ -27,6 +27,7 @@ // Forward declarations class Prepacker; +class LogicalModels; class t_intra_cluster_placement_stats; class t_pb_graph_node; struct t_lb_router_data; @@ -269,6 +270,7 @@ class ClusterLegalizer { * performed. * @param enable_pin_feasibility_filter * A flag to turn on/off the check for pin usage feasibility. + * @param models * @param log_verbosity * Controls how verbose the log messages will be within this class. */ @@ -279,6 +281,7 @@ class ClusterLegalizer { const t_pack_high_fanout_thresholds& high_fanout_thresholds, ClusterLegalizationStrategy cluster_legalization_strategy, bool enable_pin_feasibility_filter, + const LogicalModels& models, int log_verbosity); // This class allocates and deallocates memory within. This class should not diff --git a/vpr/src/pack/cluster_util.cpp b/vpr/src/pack/cluster_util.cpp index dd307168a36..fcb4f88f926 100644 --- a/vpr/src/pack/cluster_util.cpp +++ b/vpr/src/pack/cluster_util.cpp @@ -7,9 +7,12 @@ #include "cluster_legalizer.h" #include "clustered_netlist.h" #include "globals.h" +#include "logic_types.h" #include "output_clustering.h" #include "prepack.h" #include "vpr_context.h" +#include "vtr_vector.h" +#include "vtr_vector_map.h" /*Print the contents of each cluster to an echo file*/ static void echo_clusters(char* filename, const ClusterLegalizer& cluster_legalizer) { @@ -151,26 +154,29 @@ void rebuild_attraction_groups(AttractionInfo& attraction_groups, /*****************************************/ -std::map> identify_primitive_candidate_block_types() { - std::map> model_candidates; +vtr::vector> identify_primitive_candidate_block_types() { const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); const DeviceContext& device_ctx = g_vpr_ctx.device(); + const LogicalModels& models = device_ctx.arch->models; + size_t num_models = models.all_models().size(); + vtr::vector> model_candidates(num_models); - std::set unique_models; + std::set unique_models; // Find all logic models used in the netlist for (auto blk : atom_nlist.blocks()) { - auto model = atom_nlist.block_model(blk); + LogicalModelId model = atom_nlist.block_model(blk); unique_models.insert(model); } /* For each technology-mapped logic model, find logical block types * that can accommodate that logic model */ - for (auto model : unique_models) { - model_candidates[model] = {}; + for (LogicalModelId model : unique_models) { + VTR_ASSERT(model.is_valid()); + VTR_ASSERT(model_candidates[model].empty()); for (auto const& type : device_ctx.logical_block_types) { - if (block_type_contains_blif_model(&type, model->name)) { + if (block_type_contains_blif_model(&type, models.model_name(model))) { model_candidates[model].push_back(&type); } } @@ -268,16 +274,15 @@ void print_pb_type_count(const ClusteredNetlist& clb_nlist) { VTR_LOG("\n"); } -t_logical_block_type_ptr identify_logic_block_type(const std::map>& primitive_candidate_block_types) { - std::string lut_name = ".names"; +t_logical_block_type_ptr identify_logic_block_type(const vtr::vector>& primitive_candidate_block_types, + const LogicalModels& models) { + LogicalModelId lut_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); - for (auto& model : primitive_candidate_block_types) { - std::string model_name(model.first->name); - if (model_name == lut_name) - return model.second[0]; - } + VTR_ASSERT(lut_model_id.is_valid()); + if (primitive_candidate_block_types[lut_model_id].size() == 0) + return nullptr; - return nullptr; + return primitive_candidate_block_types[lut_model_id][0]; } t_pb_type* identify_le_block_type(t_logical_block_type_ptr logic_block_type) { diff --git a/vpr/src/pack/cluster_util.h b/vpr/src/pack/cluster_util.h index 4f4c2b5bec8..82fcf805047 100644 --- a/vpr/src/pack/cluster_util.h +++ b/vpr/src/pack/cluster_util.h @@ -4,6 +4,7 @@ #include #include #include "cluster_legalizer.h" +#include "logic_types.h" #include "vtr_vector.h" class AtomNetId; @@ -54,7 +55,7 @@ void print_pack_status(int tot_num_molecules, void rebuild_attraction_groups(AttractionInfo& attraction_groups, const ClusterLegalizer& cluster_legalizer); -std::map> identify_primitive_candidate_block_types(); +vtr::vector> identify_primitive_candidate_block_types(); /** * @brief Identify which nets in the atom netlist are driven by the same atom @@ -90,7 +91,8 @@ void print_pb_type_count(const ClusteredNetlist& clb_nlist); * @brief This function identifies the logic block type which is defined by the * block type which has a lut primitive. */ -t_logical_block_type_ptr identify_logic_block_type(const std::map>& primitive_candidate_block_types); +t_logical_block_type_ptr identify_logic_block_type(const vtr::vector>& primitive_candidate_block_types, + const LogicalModels& models); /* * @brief This function returns the pb_type that is similar to Logic Element (LE) diff --git a/vpr/src/pack/greedy_candidate_selector.cpp b/vpr/src/pack/greedy_candidate_selector.cpp index b202035ec59..10255890d67 100644 --- a/vpr/src/pack/greedy_candidate_selector.cpp +++ b/vpr/src/pack/greedy_candidate_selector.cpp @@ -19,12 +19,14 @@ #include "cluster_legalizer.h" #include "cluster_placement.h" #include "greedy_clusterer.h" +#include "logic_types.h" #include "prepack.h" #include "timing_info.h" #include "vpr_types.h" #include "vtr_assert.h" #include "vtr_ndmatrix.h" #include "vtr_vector.h" +#include "vtr_vector_map.h" /* * @brief Get gain of packing molecule into current cluster. @@ -86,13 +88,14 @@ GreedyCandidateSelector::GreedyCandidateSelector( const t_packer_opts& packer_opts, bool allow_unrelated_clustering, const t_molecule_stats& max_molecule_stats, - const std::map>& primitive_candidate_block_types, + const vtr::vector>& primitive_candidate_block_types, const t_pack_high_fanout_thresholds& high_fanout_thresholds, const std::unordered_set& is_clock, const std::unordered_set& is_global, const std::unordered_set& net_output_feeds_driving_block_input, const PreClusterTimingManager& pre_cluster_timing_manager, const APPackContext& appack_ctx, + const LogicalModels& models, int log_verbosity) : atom_netlist_(atom_netlist) , prepacker_(prepacker) @@ -110,7 +113,7 @@ GreedyCandidateSelector::GreedyCandidateSelector( // Initialize unrelated clustering data if unrelated clustering is enabled. if (allow_unrelated_clustering_) { - initialize_unrelated_clustering_data(max_molecule_stats); + initialize_unrelated_clustering_data(max_molecule_stats, models); } /* TODO: This is memory inefficient, fix if causes problems */ @@ -119,7 +122,7 @@ GreedyCandidateSelector::GreedyCandidateSelector( clb_inter_blk_nets_.resize(atom_netlist.blocks().size()); } -void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molecule_stats& max_molecule_stats) { +void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molecule_stats& max_molecule_stats, const LogicalModels& models) { // Create a sorted list of molecules, sorted on decreasing molecule base // gain. (Highest gain). std::vector molecules_vector; @@ -177,7 +180,7 @@ void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molec t_flat_pl_loc mol_pos = get_molecule_pos(mol_id, prepacker_, appack_ctx_); //Figure out how many external inputs are used by this molecule - t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_); + t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_, models); int ext_inps = molecule_stats.num_used_ext_inputs; //Insert the molecule into the unclustered lists by number of external inputs @@ -196,7 +199,7 @@ void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molec // molecules for each number of used external inputs. for (PackMoleculeId mol_id : molecules_vector) { //Figure out how many external inputs are used by this molecule - t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_); + t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_, models); int ext_inps = molecule_stats.num_used_ext_inputs; //Insert the molecule into the unclustered lists by number of external inputs @@ -885,10 +888,10 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou AttractionGroup& group = attraction_groups.get_attraction_group_info(grp_id); std::vector available_atoms; for (AtomBlockId atom_id : group.group_atoms) { - const auto& atom_model = atom_netlist_.block_model(atom_id); - auto itr = primitive_candidate_block_types_.find(atom_model); - VTR_ASSERT(itr != primitive_candidate_block_types_.end()); - const std::vector& candidate_types = itr->second; + LogicalModelId atom_model = atom_netlist_.block_model(atom_id); + VTR_ASSERT(atom_model.is_valid()); + VTR_ASSERT(!primitive_candidate_block_types_[atom_model].empty()); + const auto& candidate_types = primitive_candidate_block_types_[atom_model]; //Only consider molecules that are unpacked and of the correct type if (!cluster_legalizer.is_atom_clustered(atom_id) diff --git a/vpr/src/pack/greedy_candidate_selector.h b/vpr/src/pack/greedy_candidate_selector.h index 2b3eb23a1f5..a7af8d448b7 100644 --- a/vpr/src/pack/greedy_candidate_selector.h +++ b/vpr/src/pack/greedy_candidate_selector.h @@ -16,11 +16,13 @@ #include "attraction_groups.h" #include "cluster_legalizer.h" #include "greedy_clusterer.h" +#include "logic_types.h" #include "physical_types.h" #include "prepack.h" #include "vtr_ndmatrix.h" #include "vtr_vector.h" #include "vtr_random.h" +#include "vtr_vector_map.h" // Forward declarations class AtomNetlist; @@ -29,7 +31,6 @@ class FlatPlacementInfo; class PreClusterTimingManager; class Prepacker; class t_pack_high_fanout_thresholds; -struct t_model; struct t_molecule_stats; struct t_packer_opts; @@ -240,13 +241,14 @@ class GreedyCandidateSelector { const t_packer_opts& packer_opts, bool allow_unrelated_clustering, const t_molecule_stats& max_molecule_stats, - const std::map>& primitive_candidate_block_types, + const vtr::vector>& primitive_candidate_block_types, const t_pack_high_fanout_thresholds& high_fanout_thresholds, const std::unordered_set& is_clock, const std::unordered_set& is_global, const std::unordered_set& net_output_feeds_driving_block_input, const PreClusterTimingManager& pre_cluster_timing_manager, const APPackContext& appack_ctx, + const LogicalModels& models, int log_verbosity); /** @@ -375,7 +377,8 @@ class GreedyCandidateSelector { * clustering. */ void initialize_unrelated_clustering_data( - const t_molecule_stats& max_molecule_stats); + const t_molecule_stats& max_molecule_stats, + const LogicalModels& models); // ===================================================================== // // Cluster Gain Stats Updating @@ -547,7 +550,7 @@ class GreedyCandidateSelector { /// @brief Pre-computed vector of logical block types that could implement /// the given model in the architecture. - const std::map>& primitive_candidate_block_types_; + const vtr::vector>& primitive_candidate_block_types_; /// @brief The high-fanout thresholds per logical block type. Used to ignore /// certain nets when calculating the gain for the next candidate diff --git a/vpr/src/pack/greedy_clusterer.cpp b/vpr/src/pack/greedy_clusterer.cpp index 7673005af93..b7845c4f564 100644 --- a/vpr/src/pack/greedy_clusterer.cpp +++ b/vpr/src/pack/greedy_clusterer.cpp @@ -49,11 +49,11 @@ #include "cluster_util.h" #include "greedy_candidate_selector.h" #include "greedy_seed_selector.h" +#include "logic_types.h" #include "physical_types.h" #include "prepack.h" #include "vpr_context.h" #include "vtr_math.h" -#include "vtr_vector.h" namespace { @@ -116,7 +116,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, clustering_stats.num_molecules = prepacker.molecules().size(); // Calculate the max molecule stats, which is used for gain calculation. - const t_molecule_stats max_molecule_stats = prepacker.calc_max_molecule_stats(atom_netlist_); + const t_molecule_stats max_molecule_stats = prepacker.calc_max_molecule_stats(atom_netlist_, arch_.models); // Create the greedy candidate selector. This will be used to select // candidate molecules to add to the clusters. @@ -132,6 +132,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, net_output_feeds_driving_block_input_, pre_cluster_timing_manager_, appack_ctx_, + arch_.models, log_verbosity_); // Create the greedy seed selector. @@ -139,6 +140,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, prepacker, packer_opts_.cluster_seed_type, max_molecule_stats, + arch_.models, pre_cluster_timing_manager_); // Pick the first seed molecule. @@ -366,11 +368,10 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( /* Allocate a dummy initial cluster and load a atom block as a seed and check if it is legal */ AtomBlockId root_atom = seed_mol.atom_block_ids[seed_mol.root]; const std::string& root_atom_name = atom_netlist_.block_name(root_atom); - const t_model* root_model = atom_netlist_.block_model(root_atom); - - auto itr = primitive_candidate_block_types_.find(root_model); - VTR_ASSERT(itr != primitive_candidate_block_types_.end()); - std::vector candidate_types = itr->second; + LogicalModelId root_model_id = atom_netlist_.block_model(root_atom); + VTR_ASSERT(root_model_id.is_valid()); + VTR_ASSERT(!primitive_candidate_block_types_[root_model_id].empty()); + std::vector candidate_types = primitive_candidate_block_types_[root_model_id]; if (balance_block_type_utilization) { //We sort the candidate types in ascending order by their current utilization. @@ -395,7 +396,7 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( } if (log_verbosity_ > 2) { - VTR_LOG("\tSeed: '%s' (%s)", root_atom_name.c_str(), root_model->name); + VTR_LOG("\tSeed: '%s' (%s)", root_atom_name.c_str(), arch_.models.get_model(root_model_id).name); VTR_LOGV(seed_mol.pack_pattern, " molecule_type %s molecule_size %zu", seed_mol.pack_pattern->name, seed_mol.atom_block_ids.size()); VTR_LOG("\n"); @@ -435,7 +436,7 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( VPR_FATAL_ERROR(VPR_ERROR_PACK, "Can not find any logic block that can implement molecule.\n" "\tAtom %s (%s)\n", - root_atom_name.c_str(), root_model->name); + root_atom_name.c_str(), arch_.models.model_name(root_model_id).c_str()); } } @@ -510,8 +511,9 @@ bool GreedyClusterer::try_add_candidate_mol_to_cluster(PackMoleculeId candidate_ AtomBlockId blk_id = candidate_mol.atom_block_ids[candidate_mol.root]; VTR_ASSERT(blk_id.is_valid()); std::string blk_name = atom_netlist_.block_name(blk_id); - const t_model* blk_model = atom_netlist_.block_model(blk_id); - VTR_LOG("'%s' (%s)", blk_name.c_str(), blk_model->name); + LogicalModelId blk_model_id = atom_netlist_.block_model(blk_id); + std::string blk_model_name = arch_.models.model_name(blk_model_id); + VTR_LOG("'%s' (%s)", blk_name.c_str(), blk_model_name.c_str()); VTR_LOGV(candidate_mol.pack_pattern, " molecule %s molecule_size %zu", candidate_mol.pack_pattern->name, candidate_mol.atom_block_ids.size()); @@ -524,7 +526,7 @@ bool GreedyClusterer::try_add_candidate_mol_to_cluster(PackMoleculeId candidate_ void GreedyClusterer::report_le_physical_block_usage(const ClusterLegalizer& cluster_legalizer) { // find the cluster type that has lut primitives - auto logic_block_type = identify_logic_block_type(primitive_candidate_block_types_); + auto logic_block_type = identify_logic_block_type(primitive_candidate_block_types_, arch_.models); // find a LE pb_type within the found logic_block_type auto le_pb_type = identify_le_block_type(logic_block_type); diff --git a/vpr/src/pack/greedy_clusterer.h b/vpr/src/pack/greedy_clusterer.h index 4c805ffa594..cb92a0dbccf 100644 --- a/vpr/src/pack/greedy_clusterer.h +++ b/vpr/src/pack/greedy_clusterer.h @@ -12,8 +12,10 @@ #include #include #include "cluster_legalizer.h" +#include "logic_types.h" #include "physical_types.h" #include "prepack.h" +#include "vtr_vector.h" // Forward declarations class APPackContext; @@ -247,7 +249,7 @@ class GreedyClusterer { const APPackContext& appack_ctx_; /// @brief Pre-computed logical block types for each model in the architecture. - const std::map> primitive_candidate_block_types_; + const vtr::vector> primitive_candidate_block_types_; /// @brief The verbosity of log messages produced by the clusterer. /// diff --git a/vpr/src/pack/greedy_seed_selector.cpp b/vpr/src/pack/greedy_seed_selector.cpp index c9d1b9397c5..9850500400a 100644 --- a/vpr/src/pack/greedy_seed_selector.cpp +++ b/vpr/src/pack/greedy_seed_selector.cpp @@ -10,19 +10,16 @@ #include #include #include "PreClusterTimingManager.h" -#include "flat_placement_types.h" #include "atom_netlist.h" #include "cluster_legalizer.h" -#include "device_grid.h" #include "echo_files.h" -#include "globals.h" #include "greedy_clusterer.h" +#include "logic_types.h" #include "prepack.h" #include "vpr_error.h" #include "vpr_types.h" #include "vtr_assert.h" #include "vtr_math.h" -#include "vtr_ndmatrix.h" #include "vtr_vector.h" /** @@ -34,6 +31,7 @@ static inline float get_seed_gain(AtomBlockId blk_id, const AtomNetlist& atom_netlist, const Prepacker& prepacker, + const LogicalModels& models, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, const vtr::vector& atom_criticality) { @@ -49,7 +47,7 @@ static inline float get_seed_gain(AtomBlockId blk_id, // instead. case e_cluster_seed::MAX_INPUTS: { PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist, models); return molecule_stats.num_used_ext_inputs; } // By blended gain (criticality and inputs used). @@ -60,7 +58,7 @@ static inline float get_seed_gain(AtomBlockId blk_id, float seed_blend_fac = 0.5f; PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist, models); VTR_ASSERT(max_molecule_stats.num_used_ext_inputs > 0); float used_ext_input_pin_ratio = vtr::safe_ratio(molecule_stats.num_used_ext_inputs, max_molecule_stats.num_used_ext_inputs); @@ -74,7 +72,7 @@ static inline float get_seed_gain(AtomBlockId blk_id, // harder to pack. case e_cluster_seed::MAX_PINS: { PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist, models); return molecule_stats.num_pins; } // By input pins per molecule (i.e. available pins on primitives, not pins in use). @@ -82,12 +80,12 @@ static inline float get_seed_gain(AtomBlockId blk_id, // harder to pack. case e_cluster_seed::MAX_INPUT_PINS: { PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist, models); return molecule_stats.num_input_pins; } case e_cluster_seed::BLEND2: { PackMoleculeId mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol_id, atom_netlist, models); float pin_ratio = vtr::safe_ratio(molecule_stats.num_pins, max_molecule_stats.num_pins); float input_pin_ratio = vtr::safe_ratio(molecule_stats.num_input_pins, max_molecule_stats.num_input_pins); @@ -134,7 +132,8 @@ static inline void print_seed_gains(const char* fname, const std::vector& seed_atoms, const vtr::vector& atom_gain, const vtr::vector& atom_criticality, - const AtomNetlist& atom_netlist) { + const AtomNetlist& atom_netlist, + const LogicalModels& models) { FILE* fp = vtr::fopen(fname, "w"); // For pretty formatting determine the maximum name length @@ -143,8 +142,8 @@ static inline void print_seed_gains(const char* fname, for (auto blk_id : atom_netlist.blocks()) { max_name_len = std::max(max_name_len, (int)atom_netlist.block_name(blk_id).size()); - const t_model* model = atom_netlist.block_model(blk_id); - max_type_len = std::max(max_type_len, (int)strlen(model->name)); + std::string model_name = models.model_name(atom_netlist.block_model(blk_id)); + max_type_len = std::max(max_type_len, model_name.size()); } fprintf(fp, "%-*s %-*s %8s %8s\n", max_name_len, "atom_block_name", max_type_len, "atom_block_type", "gain", "criticality"); @@ -153,8 +152,8 @@ static inline void print_seed_gains(const char* fname, std::string name = atom_netlist.block_name(blk_id); fprintf(fp, "%-*s ", max_name_len, name.c_str()); - const t_model* model = atom_netlist.block_model(blk_id); - fprintf(fp, "%-*s ", max_type_len, model->name); + std::string model_name = models.model_name(atom_netlist.block_model(blk_id)); + fprintf(fp, "%-*s ", max_type_len, model_name.c_str()); fprintf(fp, "%*f ", std::max((int)strlen("gain"), 8), atom_gain[blk_id]); fprintf(fp, "%*f ", std::max((int)strlen("criticality"), 8), atom_criticality[blk_id]); @@ -168,6 +167,7 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, const Prepacker& prepacker, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, + const LogicalModels& models, const PreClusterTimingManager& pre_cluster_timing_manager) : seed_atoms_(atom_netlist.blocks().begin(), atom_netlist.blocks().end()) { // Seed atoms list is initialized with all atoms in the atom netlist. @@ -193,6 +193,7 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, atom_gains[blk_id] = get_seed_gain(blk_id, atom_netlist, prepacker, + models, seed_type, max_molecule_stats, atom_criticality); @@ -214,7 +215,7 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, // Print the seed gains if requested. if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES)) { print_seed_gains(getEchoFileName(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES), - seed_atoms_, atom_gains, atom_criticality, atom_netlist); + seed_atoms_, atom_gains, atom_criticality, atom_netlist, models); } // Set the starting seed index (the index of the first molecule to propose). diff --git a/vpr/src/pack/greedy_seed_selector.h b/vpr/src/pack/greedy_seed_selector.h index 5f152f65236..0207949bef1 100644 --- a/vpr/src/pack/greedy_seed_selector.h +++ b/vpr/src/pack/greedy_seed_selector.h @@ -14,6 +14,7 @@ // Forward declarations class AtomNetlist; class ClusterLegalizer; +class LogicalModels; class PreClusterTimingManager; struct t_molecule_stats; @@ -53,6 +54,7 @@ class GreedySeedSelector { const Prepacker& prepacker, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, + const LogicalModels& models, const PreClusterTimingManager& pre_cluster_timing_manager); /** diff --git a/vpr/src/pack/noc_aware_cluster_util.cpp b/vpr/src/pack/noc_aware_cluster_util.cpp index aba034992f2..3b14608d47a 100644 --- a/vpr/src/pack/noc_aware_cluster_util.cpp +++ b/vpr/src/pack/noc_aware_cluster_util.cpp @@ -2,21 +2,22 @@ #include "noc_aware_cluster_util.h" #include "atom_netlist.h" #include "globals.h" +#include "logic_types.h" #include "vpr_types.h" #include -std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist) { +std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist, const LogicalModels& models) { // NoC router atoms are expected to have a specific blif model - const std::string noc_router_blif_model_name = "noc_router_adapter_block"; + LogicalModelId noc_route_blif_model_id = models.get_model_by_name("noc_router_adapter_block"); // stores found NoC router atoms std::vector noc_router_atoms; // iterate over all atoms and find those whose blif model matches for (auto atom_id : atom_netlist.blocks()) { - const t_model* model = atom_netlist.block_model(atom_id); - if (noc_router_blif_model_name == model->name) { + LogicalModelId model_id = atom_netlist.block_model(atom_id); + if (model_id == noc_route_blif_model_id) { noc_router_atoms.push_back(atom_id); } } diff --git a/vpr/src/pack/noc_aware_cluster_util.h b/vpr/src/pack/noc_aware_cluster_util.h index a414d147bcf..dbdb79d5785 100644 --- a/vpr/src/pack/noc_aware_cluster_util.h +++ b/vpr/src/pack/noc_aware_cluster_util.h @@ -22,6 +22,7 @@ class AtomNetlist; class AtomBlockId; +class LogicalModels; class t_pack_high_fanout_thresholds; /** @@ -30,7 +31,7 @@ class t_pack_high_fanout_thresholds; * * @return The atom block IDs of the NoC router blocks in the netlist. */ -std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist); +std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist, const LogicalModels& models); /** * @brief Runs BFS starting from NoC routers to find all connected diff --git a/vpr/src/pack/pack.cpp b/vpr/src/pack/pack.cpp index ec96e7c4d7c..85a21c229e6 100644 --- a/vpr/src/pack/pack.cpp +++ b/vpr/src/pack/pack.cpp @@ -120,6 +120,7 @@ bool try_pack(const t_packer_opts& packer_opts, high_fanout_thresholds, ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE, packer_opts.enable_pin_feasibility_filter, + arch.models, packer_opts.pack_verbosity); VTR_LOG("Packing with pin utilization targets: %s\n", cluster_legalizer.get_target_external_pin_util().to_string().c_str()); VTR_LOG("Packing with high fanout thresholds: %s\n", high_fanout_thresholds.to_string().c_str()); diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 02784e4321a..266f3d38f79 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -25,7 +25,6 @@ #include "vpr_error.h" #include "vpr_types.h" -#include "arch_types.h" #include "physical_types.h" #include "globals.h" #include "vpr_utils.h" @@ -295,7 +294,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node, pb_graph_node->input_pins[i_input][j].parent_node = pb_graph_node; pb_graph_node->input_pins[i_input][j].pin_count_in_cluster = pin_count_in_cluster; if (pb_graph_node->pb_type->blif_model != nullptr) { - if (strcmp(pb_graph_node->pb_type->blif_model, MODEL_OUTPUT) == 0) { + if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_OUTPUT) == 0) { pb_graph_node->input_pins[i_input][j].type = PB_PIN_OUTPAD; } else if (pb_graph_node->num_clock_ports != 0) { pb_graph_node->input_pins[i_input][j].type = PB_PIN_SEQUENTIAL; @@ -315,7 +314,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node, pb_graph_node->output_pins[i_output][j].parent_node = pb_graph_node; pb_graph_node->output_pins[i_output][j].pin_count_in_cluster = pin_count_in_cluster; if (pb_graph_node->pb_type->blif_model != nullptr) { - if (strcmp(pb_graph_node->pb_type->blif_model, MODEL_INPUT) == 0) { + if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT) == 0) { pb_graph_node->output_pins[i_output][j].type = PB_PIN_INPAD; } else if (pb_graph_node->num_clock_ports != 0) { pb_graph_node->output_pins[i_output][j].type = PB_PIN_SEQUENTIAL; diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 6f80d5927a5..344d8184a88 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -21,6 +21,7 @@ #include "atom_netlist.h" #include "echo_files.h" +#include "logic_types.h" #include "physical_types.h" #include "vpr_error.h" #include "vpr_types.h" @@ -70,7 +71,8 @@ static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_ static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, const std::multimap& atom_molecules, - const AtomNetlist& atom_nlist); + const AtomNetlist& atom_nlist, + const LogicalModels& models); static void print_pack_molecules(const char* fname, const std::vector& list_of_pack_patterns, @@ -108,7 +110,8 @@ static void init_molecule_chain_info(const AtomBlockId blk_id, static AtomBlockId get_sink_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, - const AtomNetlist& atom_nlist); + const AtomNetlist& atom_nlist, + const LogicalModels& models); static AtomBlockId get_driving_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, @@ -775,6 +778,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans */ void Prepacker::alloc_and_load_pack_molecules(std::multimap& atom_molecules_multimap, const AtomNetlist& atom_nlist, + const LogicalModels& models, const std::vector& logical_block_types) { std::vector is_used(list_of_pack_patterns.size(), false); @@ -811,7 +815,8 @@ void Prepacker::alloc_and_load_pack_molecules(std::multimapname); + models.get_model(atom_nlist.block_model(blk_id)).name); } VTR_ASSERT_SAFE(nullptr != best); @@ -920,7 +925,8 @@ static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_ PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, AtomBlockId blk_id, std::multimap& atom_molecules_multimap, - const AtomNetlist& atom_nlist) { + const AtomNetlist& atom_nlist, + const LogicalModels& models) { auto pack_pattern = &list_of_pack_patterns[pack_pattern_index]; // Check pack pattern validity @@ -944,7 +950,7 @@ PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, molecule.root = pack_pattern->root_block->block_id; molecule.chain_id = MoleculeChainId::INVALID(); - if (!try_expand_molecule(molecule, blk_id, atom_molecules_multimap, atom_nlist)) { + if (!try_expand_molecule(molecule, blk_id, atom_molecules_multimap, atom_nlist, models)) { // Failed to create molecule return PackMoleculeId::INVALID(); } @@ -988,7 +994,8 @@ PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, const std::multimap& atom_molecules, - const AtomNetlist& atom_nlist) { + const AtomNetlist& atom_nlist, + const LogicalModels& models) { // root block of the pack pattern, which is the starting point of this pattern const auto pattern_root_block = molecule.pack_pattern->root_block; // bool array indicating whether a position in a pack pattern is optional or should @@ -1045,7 +1052,7 @@ static bool try_expand_molecule(t_pack_molecule& molecule, // this block is the driver of this connection if (block_connection->from_block == pattern_block) { // find the block this connection is driving and add it to the queue - auto sink_blk_id = get_sink_block(block_id, *block_connection, atom_nlist); + auto sink_blk_id = get_sink_block(block_id, *block_connection, atom_nlist, models); // add this sink block id with its corresponding pattern block to the queue pattern_block_queue.push(std::make_pair(block_connection->to_block, sink_blk_id)); // this block is being driven by this connection @@ -1077,7 +1084,8 @@ static bool try_expand_molecule(t_pack_molecule& molecule, */ static AtomBlockId get_sink_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, - const AtomNetlist& atom_nlist) { + const AtomNetlist& atom_nlist, + const LogicalModels& models) { const t_model_ports* from_port_model = connections.from_pin->port->model_port; const int from_pin_number = connections.from_pin->pin_number; auto from_port_id = atom_nlist.find_atom_port(block_id, from_port_model); @@ -1099,10 +1107,11 @@ static AtomBlockId get_sink_block(const AtomBlockId block_id, // Iterate through all sink blocks and check whether any of them // is compatible with the block specified in the pack pattern. bool connected_to_latch = false; + LogicalModelId latch_model_id = models.get_model_by_name(LogicalModels::MODEL_LATCH); AtomBlockId pattern_sink_block_id = AtomBlockId::INVALID(); for (const auto& sink_pin_id : net_sinks) { auto sink_block_id = atom_nlist.pin_block(sink_pin_id); - if (atom_nlist.block_model(sink_block_id)->name == std::string(MODEL_LATCH)) { + if (atom_nlist.block_model(sink_block_id) == latch_model_id) { connected_to_latch = true; } if (primitive_type_feasible(sink_block_id, to_pb_type)) { @@ -1680,6 +1689,7 @@ static void print_chain_starting_points(t_pack_patterns* chain_pattern) { } Prepacker::Prepacker(const AtomNetlist& atom_nlist, + const LogicalModels& models, const std::vector& logical_block_types) { vtr::ScopedStartFinishTimer prepacker_timer("Prepacker"); @@ -1690,6 +1700,7 @@ Prepacker::Prepacker(const AtomNetlist& atom_nlist, expected_lowest_cost_pb_gnode.resize(atom_nlist.blocks().size(), nullptr); alloc_and_load_pack_molecules(atom_molecules_multimap, atom_nlist, + models, logical_block_types); // The multimap is a legacy thing. Since blocks can be part of multiple pack @@ -1709,7 +1720,8 @@ Prepacker::Prepacker(const AtomNetlist& atom_nlist, // this information and store it in the prepacker class. This may be // expensive to calculate for large molecules. t_molecule_stats Prepacker::calc_molecule_stats(PackMoleculeId molecule_id, - const AtomNetlist& atom_nlist) const { + const AtomNetlist& atom_nlist, + const LogicalModels& models) const { VTR_ASSERT(molecule_id.is_valid()); t_molecule_stats molecule_stats; @@ -1721,13 +1733,14 @@ t_molecule_stats Prepacker::calc_molecule_stats(PackMoleculeId molecule_id, ++molecule_stats.num_blocks; //Record number of valid blocks in molecule - const t_model* model = atom_nlist.block_model(blk); + LogicalModelId model_id = atom_nlist.block_model(blk); + const t_model& model = models.get_model(model_id); - for (const t_model_ports* input_port = model->inputs; input_port != nullptr; input_port = input_port->next) { + for (const t_model_ports* input_port = model.inputs; input_port != nullptr; input_port = input_port->next) { molecule_stats.num_input_pins += input_port->size; } - for (const t_model_ports* output_port = model->outputs; output_port != nullptr; output_port = output_port->next) { + for (const t_model_ports* output_port = model.outputs; output_port != nullptr; output_port = output_port->next) { molecule_stats.num_output_pins += output_port->size; } } @@ -1780,11 +1793,11 @@ t_molecule_stats Prepacker::calc_molecule_stats(PackMoleculeId molecule_id, return molecule_stats; } -t_molecule_stats Prepacker::calc_max_molecule_stats(const AtomNetlist& atom_nlist) const { +t_molecule_stats Prepacker::calc_max_molecule_stats(const AtomNetlist& atom_nlist, const LogicalModels& models) const { t_molecule_stats max_molecules_stats; for (PackMoleculeId molecule_id : molecules()) { //Calculate per-molecule statistics - t_molecule_stats cur_molecule_stats = calc_molecule_stats(molecule_id, atom_nlist); + t_molecule_stats cur_molecule_stats = calc_molecule_stats(molecule_id, atom_nlist, models); //Record the maximums (member-wise) over all molecules max_molecules_stats.num_blocks = std::max(max_molecules_stats.num_blocks, cur_molecule_stats.num_blocks); diff --git a/vpr/src/pack/prepack.h b/vpr/src/pack/prepack.h index 5222046ddb6..08c960f3105 100644 --- a/vpr/src/pack/prepack.h +++ b/vpr/src/pack/prepack.h @@ -20,6 +20,7 @@ // Forward declarations class t_pack_molecule; +class LogicalModels; struct t_logical_block_type; // A unique ID used to identify a molecule generated by the prepacker. @@ -192,9 +193,11 @@ class Prepacker { * necessary data strucutres. * * @param atom_nlist The atom netlist to prepack. + * @param models * @param logical_block_types A list of the logical block types on the device. */ Prepacker(const AtomNetlist& atom_nlist, + const LogicalModels& models, const std::vector& logical_block_types); /** @@ -236,12 +239,14 @@ class Prepacker { * @brief Calculates molecule statistics for a single molecule. */ t_molecule_stats calc_molecule_stats(PackMoleculeId molecule_id, - const AtomNetlist& atom_netlist) const; + const AtomNetlist& atom_netlist, + const LogicalModels& models) const; /** * @brief Calculates maximum molecule statistics accross all molecules, */ - t_molecule_stats calc_max_molecule_stats(const AtomNetlist& netlist) const; + t_molecule_stats calc_max_molecule_stats(const AtomNetlist& netlist, + const LogicalModels& models) const; /** * @brief Gets the largest number of blocks (atoms) that any molecule contains. @@ -303,6 +308,7 @@ class Prepacker { */ void alloc_and_load_pack_molecules(std::multimap& atom_molecules_multimap, const AtomNetlist& atom_nlist, + const LogicalModels& models, const std::vector& logical_block_types); /** @@ -321,7 +327,8 @@ class Prepacker { PackMoleculeId try_create_molecule(const int pack_pattern_index, AtomBlockId blk_id, std::multimap& atom_molecules_multimap, - const AtomNetlist& atom_nlist); + const AtomNetlist& atom_nlist, + const LogicalModels& models); private: /** diff --git a/vpr/src/place/placement_log_printer.cpp b/vpr/src/place/placement_log_printer.cpp index 1ce8c239dc7..f4fccecbcc1 100644 --- a/vpr/src/place/placement_log_printer.cpp +++ b/vpr/src/place/placement_log_printer.cpp @@ -314,8 +314,9 @@ void generate_post_place_timing_reports(const t_placer_opts& placer_opts, const BlkLocRegistry& blk_loc_registry) { const auto& timing_ctx = g_vpr_ctx.timing(); const auto& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index e049f611331..888507ae804 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -133,7 +133,7 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra auto& device_ctx = g_vpr_ctx.device(); auto& power_ctx = g_vpr_ctx.power(); - if (strcmp(pb_graph_node->pb_type->blif_model, MODEL_NAMES) == 0) { + if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_NAMES) == 0) { /* LUT */ std::string SRAM_values; @@ -174,7 +174,7 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra power_add_usage(power_usage, &sub_power_usage); delete[] input_probabilities; delete[] input_densities; - } else if (strcmp(pb_graph_node->pb_type->blif_model, MODEL_LATCH) == 0) { + } else if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_LATCH) == 0) { /* Flip-Flop */ t_pb_graph_pin* D_pin = &pb_graph_node->input_pins[0][0]; diff --git a/vpr/src/power/power_sizing.cpp b/vpr/src/power/power_sizing.cpp index 914bf13afde..9f35996eb2b 100644 --- a/vpr/src/power/power_sizing.cpp +++ b/vpr/src/power/power_sizing.cpp @@ -24,6 +24,7 @@ #include #include +#include "logic_types.h" #include "vtr_util.h" #include "vtr_assert.h" #include "vtr_memory.h" @@ -404,11 +405,11 @@ static double power_count_transistors_primitive(t_pb_type* pb_type) { auto& power_ctx = g_vpr_ctx.power(); - if (strcmp(pb_type->blif_model, MODEL_NAMES) == 0) { + if (strcmp(pb_type->blif_model, LogicalModels::MODEL_NAMES) == 0) { /* LUT */ transistor_cnt = power_count_transistors_LUT(pb_type->num_input_pins, power_ctx.arch->LUT_transistor_size); - } else if (strcmp(pb_type->blif_model, MODEL_LATCH) == 0) { + } else if (strcmp(pb_type->blif_model, LogicalModels::MODEL_LATCH) == 0) { /* Latch */ transistor_cnt = power_count_transistors_FF(power_ctx.arch->FF_size); } else { diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 68701b46731..43501cd04aa 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -3,8 +3,8 @@ #include "atom_netlist_utils.h" #include "connection_router_interface.h" #include "describe_rr_node.h" -#include "draw_global.h" #include "route_common.h" +#include "logic_types.h" #include "physical_types_util.h" #include "route_export.h" @@ -64,6 +64,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally(); static void adjust_one_rr_occ_and_acc_cost(RRNodeId inode, int add_or_sub, float acc_fac); static vtr::vector load_is_clock_net(const Netlist<>& net_list, + const LogicalModels& models, bool is_flat); static bool classes_in_same_block(ParentBlockId blk_id, int first_class_ptc_num, int second_class_ptc_num, bool is_flat); @@ -266,7 +267,7 @@ void init_route_structs(const Netlist<>& net_list, net_list, is_flat); - route_ctx.is_clock_net = load_is_clock_net(net_list, is_flat); + route_ctx.is_clock_net = load_is_clock_net(net_list, device_ctx.arch->models, is_flat); route_ctx.route_bb = load_route_bb(net_list, bb_factor); route_ctx.rr_blk_source = load_rr_clb_sources(device_ctx.rr_graph, @@ -603,11 +604,12 @@ static vtr::vector> load_rr_clb_sources(con } static vtr::vector load_is_clock_net(const Netlist<>& net_list, + const LogicalModels& models, bool is_flat) { vtr::vector is_clock_net(net_list.nets().size()); auto& atom_ctx = g_vpr_ctx.atom(); - std::set clock_nets = find_netlist_physical_clock_nets(atom_ctx.netlist()); + std::set clock_nets = find_netlist_physical_clock_nets(atom_ctx.netlist(), models); for (auto net_id : net_list.nets()) { std::size_t net_id_num = std::size_t(net_id); diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index aab9e952315..687ca44d063 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -219,8 +219,9 @@ void generate_route_timing_reports(const t_router_opts& router_opts, auto& timing_ctx = g_vpr_ctx.timing(); auto& atom_ctx = g_vpr_ctx.atom(); const auto& blk_loc_registry = g_vpr_ctx.placement().blk_loc_registry(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); diff --git a/vpr/src/server/pathhelper.cpp b/vpr/src/server/pathhelper.cpp index b1f581aa620..aa703f444b0 100644 --- a/vpr/src/server/pathhelper.cpp +++ b/vpr/src/server/pathhelper.cpp @@ -40,12 +40,13 @@ CritPathsResultPtr calc_critical_path(const std::string& report_type, int crit_p auto& timing_ctx = g_vpr_ctx.timing(); auto& atom_ctx = g_vpr_ctx.atom(); const auto& blk_loc_registry = g_vpr_ctx.placement().blk_loc_registry(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; t_analysis_opts analysis_opts; analysis_opts.timing_report_detail = details_level; analysis_opts.timing_report_npaths = crit_path_num; - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, *routing_delay_calc, is_flat_routing, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, *routing_delay_calc, is_flat_routing, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); diff --git a/vpr/src/timing/PreClusterDelayCalculator.h b/vpr/src/timing/PreClusterDelayCalculator.h index 069aaa13530..7b7ee903bbb 100644 --- a/vpr/src/timing/PreClusterDelayCalculator.h +++ b/vpr/src/timing/PreClusterDelayCalculator.h @@ -11,17 +11,22 @@ #include "atom_netlist.h" #include "atom_lookup.h" +#include "logic_types.h" #include "physical_types.h" #include "prepack.h" +class LogicalModels; + class PreClusterDelayCalculator : public tatum::DelayCalculator { public: PreClusterDelayCalculator(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, float intercluster_net_delay, const Prepacker& prepacker) noexcept : netlist_(netlist) , netlist_lookup_(netlist_lookup) + , models_(models) , inter_cluster_net_delay_(intercluster_net_delay) , prepacker_(prepacker) { //nop @@ -153,8 +158,8 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { if (!clock_gpin) { AtomBlockId blk = netlist_.pin_block(io_pin); - const t_model* model = netlist_.block_model(blk); - VPR_FATAL_ERROR(VPR_ERROR_TIMING, "Failed to find clock pin associated with pin '%s' (model '%s')", netlist_.pin_name(io_pin).c_str(), model->name); + std::string model_name = models_.get_model(netlist_.block_model(blk)).name; + VPR_FATAL_ERROR(VPR_ERROR_TIMING, "Failed to find clock pin associated with pin '%s' (model '%s')", netlist_.pin_name(io_pin).c_str(), model_name.c_str()); } return clock_gpin; } @@ -162,6 +167,7 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { private: const AtomNetlist& netlist_; const AtomLookup& netlist_lookup_; + const LogicalModels& models_; const float inter_cluster_net_delay_; const Prepacker& prepacker_; }; diff --git a/vpr/src/timing/PreClusterTimingGraphResolver.cpp b/vpr/src/timing/PreClusterTimingGraphResolver.cpp index d1d8c2d8754..665da067646 100644 --- a/vpr/src/timing/PreClusterTimingGraphResolver.cpp +++ b/vpr/src/timing/PreClusterTimingGraphResolver.cpp @@ -5,10 +5,12 @@ PreClusterTimingGraphResolver::PreClusterTimingGraphResolver( const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, const tatum::TimingGraph& timing_graph, const tatum::DelayCalculator& delay_calc) : netlist_(netlist) , netlist_lookup_(netlist_lookup) + , models_(models) , timing_graph_(timing_graph) , delay_calc_(delay_calc) {} @@ -22,7 +24,7 @@ std::string PreClusterTimingGraphResolver::node_type_name(tatum::NodeId node) co AtomPinId pin = netlist_lookup_.tnode_atom_pin(node); AtomBlockId blk = netlist_.pin_block(pin); - std::string name = netlist_.block_model(blk)->name; + std::string name = models_.model_name(netlist_.block_model(blk)); if (detail_level() == e_timing_report_detail::AGGREGATED) { //Annotate primitive grid location, if known @@ -72,7 +74,7 @@ tatum::EdgeDelayBreakdown PreClusterTimingGraphResolver::edge_delay_breakdown(ta //component.inst_name = netlist_.block_name(atom_blk); component.type_name = "primitive '"; - component.type_name += netlist_.block_model(atom_blk)->name; + component.type_name += models_.model_name(netlist_.block_model(atom_blk)); component.type_name += "'"; if (edge_type == tatum::EdgeType::PRIMITIVE_COMBINATIONAL) { diff --git a/vpr/src/timing/PreClusterTimingGraphResolver.h b/vpr/src/timing/PreClusterTimingGraphResolver.h index ce859c1ecd6..6469c4f8b66 100644 --- a/vpr/src/timing/PreClusterTimingGraphResolver.h +++ b/vpr/src/timing/PreClusterTimingGraphResolver.h @@ -6,11 +6,14 @@ #include "atom_lookup.h" #include "AnalysisDelayCalculator.h" +class LogicalModels; + class PreClusterTimingGraphResolver : public tatum::TimingGraphNameResolver { public: PreClusterTimingGraphResolver( const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, const tatum::TimingGraph& timing_graph, const tatum::DelayCalculator& delay_calc); @@ -26,6 +29,7 @@ class PreClusterTimingGraphResolver : public tatum::TimingGraphNameResolver { const AtomNetlist& netlist_; const AtomLookup& netlist_lookup_; + const LogicalModels& models_; const tatum::TimingGraph& timing_graph_; const tatum::DelayCalculator& delay_calc_; e_timing_report_detail detail_level_ = e_timing_report_detail::NETLIST; diff --git a/vpr/src/timing/PreClusterTimingManager.cpp b/vpr/src/timing/PreClusterTimingManager.cpp index 44407d61522..7e9d7a6a0d1 100644 --- a/vpr/src/timing/PreClusterTimingManager.cpp +++ b/vpr/src/timing/PreClusterTimingManager.cpp @@ -78,6 +78,7 @@ PreClusterTimingManager::PreClusterTimingManager(bool timing_driven, // Initialize the timing analyzer clustering_delay_calc_ = std::make_shared(atom_netlist, atom_lookup, + arch.models, inter_cluster_net_delay, prepacker); timing_info_ = make_setup_timing_info(clustering_delay_calc_, timing_update_type); @@ -101,6 +102,7 @@ PreClusterTimingManager::PreClusterTimingManager(bool timing_driven, auto& timing_ctx = g_vpr_ctx.timing(); PreClusterTimingGraphResolver resolver(atom_netlist, atom_lookup, + arch.models, *timing_ctx.graph, *clustering_delay_calc_); resolver.set_detail_level(analysis_opts.timing_report_detail); diff --git a/vpr/src/timing/VprTimingGraphResolver.cpp b/vpr/src/timing/VprTimingGraphResolver.cpp index 33ea251d52d..d884c3e15ff 100644 --- a/vpr/src/timing/VprTimingGraphResolver.cpp +++ b/vpr/src/timing/VprTimingGraphResolver.cpp @@ -1,15 +1,18 @@ #include "VprTimingGraphResolver.h" #include "atom_netlist.h" #include "atom_lookup.h" +#include "logic_types.h" VprTimingGraphResolver::VprTimingGraphResolver(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, const tatum::TimingGraph& timing_graph, const AnalysisDelayCalculator& delay_calc, bool is_flat, const BlkLocRegistry& blk_loc_registry) : netlist_(netlist) , netlist_lookup_(netlist_lookup) + , models_(models) , timing_graph_(timing_graph) , delay_calc_(delay_calc) , is_flat_(is_flat) @@ -25,7 +28,7 @@ std::string VprTimingGraphResolver::node_type_name(tatum::NodeId node) const { AtomPinId pin = netlist_lookup_.tnode_atom_pin(node); AtomBlockId blk = netlist_.pin_block(pin); - std::string name = netlist_.block_model(blk)->name; + std::string name = models_.model_name(netlist_.block_model(blk)); if (detail_level() == e_timing_report_detail::AGGREGATED || detail_level() == e_timing_report_detail::DETAILED_ROUTING @@ -78,7 +81,7 @@ tatum::EdgeDelayBreakdown VprTimingGraphResolver::edge_delay_breakdown(tatum::Ed //component.inst_name = netlist_.block_name(atom_blk); component.type_name = "primitive '"; - component.type_name += netlist_.block_model(atom_blk)->name; + component.type_name += models_.model_name(netlist_.block_model(atom_blk)); component.type_name += "'"; if (edge_type == tatum::EdgeType::PRIMITIVE_COMBINATIONAL) { diff --git a/vpr/src/timing/VprTimingGraphResolver.h b/vpr/src/timing/VprTimingGraphResolver.h index 7bb9eb3ba6a..0f63c3d9370 100644 --- a/vpr/src/timing/VprTimingGraphResolver.h +++ b/vpr/src/timing/VprTimingGraphResolver.h @@ -7,11 +7,13 @@ #include "AnalysisDelayCalculator.h" class BlkLocRegistry; +class LogicalModels; class VprTimingGraphResolver : public tatum::TimingGraphNameResolver { public: VprTimingGraphResolver(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, const tatum::TimingGraph& timing_graph, const AnalysisDelayCalculator& delay_calc, bool is_flat, @@ -33,6 +35,7 @@ class VprTimingGraphResolver : public tatum::TimingGraphNameResolver { const AtomNetlist& netlist_; const AtomLookup& netlist_lookup_; + const LogicalModels& models_; const tatum::TimingGraph& timing_graph_; const AnalysisDelayCalculator& delay_calc_; e_timing_report_detail detail_level_ = e_timing_report_detail::NETLIST; diff --git a/vpr/src/timing/read_sdc.cpp b/vpr/src/timing/read_sdc.cpp index e8db27b9a28..8c29af538c2 100644 --- a/vpr/src/timing/read_sdc.cpp +++ b/vpr/src/timing/read_sdc.cpp @@ -19,6 +19,7 @@ void apply_default_timing_constraints(const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingConstraints& timing_constraints); void apply_combinational_default_timing_constraints(const AtomNetlist& netlist, @@ -56,17 +57,19 @@ class SdcParseCallback : public sdcparse::Callback { public: SdcParseCallback(const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingConstraints& timing_constraints, tatum::TimingGraph& tg) : netlist_(netlist) , lookup_(lookup) + , models_(models) , tc_(timing_constraints) , tg_(tg) {} public: //sdcparse::Callback interface //Start of parsing void start_parse() override { - netlist_clock_drivers_ = find_netlist_logical_clock_drivers(netlist_); + netlist_clock_drivers_ = find_netlist_logical_clock_drivers(netlist_, models_); netlist_primary_ios_ = find_netlist_primary_ios(netlist_); } @@ -1036,6 +1039,7 @@ class SdcParseCallback : public sdcparse::Callback { private: const AtomNetlist& netlist_; const AtomLookup& lookup_; + const LogicalModels& models_; tatum::TimingConstraints& tc_; tatum::TimingGraph& tg_; @@ -1060,32 +1064,33 @@ class SdcParseCallback : public sdcparse::Callback { std::unique_ptr read_sdc(const t_timing_inf& timing_inf, const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingGraph& timing_graph) { auto timing_constraints = std::make_unique(); if (!timing_inf.timing_analysis_enabled) { VTR_LOG("\n"); VTR_LOG("Timing analysis off\n"); - apply_default_timing_constraints(netlist, lookup, *timing_constraints); + apply_default_timing_constraints(netlist, lookup, models, *timing_constraints); } else { FILE* sdc_file = fopen(timing_inf.SDCFile.c_str(), "r"); if (sdc_file == nullptr) { //No SDC file VTR_LOG("\n"); VTR_LOG("SDC file '%s' not found\n", timing_inf.SDCFile.c_str()); - apply_default_timing_constraints(netlist, lookup, *timing_constraints); + apply_default_timing_constraints(netlist, lookup, models, *timing_constraints); } else { VTR_ASSERT(sdc_file != nullptr); //Parse the file - SdcParseCallback callback(netlist, lookup, *timing_constraints, timing_graph); + SdcParseCallback callback(netlist, lookup, models, *timing_constraints, timing_graph); sdc_parse_file(sdc_file, callback, timing_inf.SDCFile.c_str()); fclose(sdc_file); if (callback.num_commands() == 0) { VTR_LOG("\n"); VTR_LOG("SDC file '%s' contained no SDC commands\n", timing_inf.SDCFile.c_str()); - apply_default_timing_constraints(netlist, lookup, *timing_constraints); + apply_default_timing_constraints(netlist, lookup, models, *timing_constraints); } else { VTR_LOG("\n"); VTR_LOG("Applied %zu SDC commands from '%s'\n", callback.num_commands(), timing_inf.SDCFile.c_str()); @@ -1119,8 +1124,9 @@ std::unique_ptr read_sdc(const t_timing_inf& timing_in //appropriate to the type of circuit. void apply_default_timing_constraints(const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingConstraints& tc) { - std::set netlist_clock_drivers = find_netlist_logical_clock_drivers(netlist); + std::set netlist_clock_drivers = find_netlist_logical_clock_drivers(netlist, models); if (netlist_clock_drivers.size() == 0) { apply_combinational_default_timing_constraints(netlist, lookup, tc); diff --git a/vpr/src/timing/read_sdc.h b/vpr/src/timing/read_sdc.h index 4e759360f15..bae43206952 100644 --- a/vpr/src/timing/read_sdc.h +++ b/vpr/src/timing/read_sdc.h @@ -9,9 +9,12 @@ #include "atom_lookup_fwd.h" #include "vpr_types.h" +class LogicalModels; + std::unique_ptr read_sdc(const t_timing_inf& timing_inf, const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingGraph& timing_graph); #endif diff --git a/vpr/src/timing/timing_graph_builder.cpp b/vpr/src/timing/timing_graph_builder.cpp index 78bbbe63ba2..1e183c81289 100644 --- a/vpr/src/timing/timing_graph_builder.cpp +++ b/vpr/src/timing/timing_graph_builder.cpp @@ -218,12 +218,11 @@ */ #include +#include "logic_types.h" #include "vtr_log.h" -#include "vtr_linear_map.h" #include "timing_graph_builder.h" #include "vpr_error.h" -#include "vpr_utils.h" #include "atom_netlist.h" #include "atom_netlist_utils.h" @@ -251,10 +250,11 @@ tatum::util::linear_map remap_valid(const tatum::util::linear_map& d } TimingGraphBuilder::TimingGraphBuilder(const AtomNetlist& netlist, - AtomLookup& netlist_lookup) + AtomLookup& netlist_lookup, + const LogicalModels& models) : netlist_(netlist) , netlist_lookup_(netlist_lookup) - , netlist_clock_drivers_(find_netlist_logical_clock_drivers(netlist_)) { + , netlist_clock_drivers_(find_netlist_logical_clock_drivers(netlist_, models)) { //pass } diff --git a/vpr/src/timing/timing_graph_builder.h b/vpr/src/timing/timing_graph_builder.h index 1f1624eed81..40b571a8bb1 100644 --- a/vpr/src/timing/timing_graph_builder.h +++ b/vpr/src/timing/timing_graph_builder.h @@ -5,6 +5,8 @@ #include "atom_netlist_fwd.h" #include "atom_lookup.h" +class LogicalModels; + /* * Class for constructing a Timing Graph (a tatum::TimingGraph, for use with the Tatum * STA engine) from the provided AtomNetlist. It also updates the provided AtomLookup @@ -19,7 +21,8 @@ class TimingGraphBuilder { public: TimingGraphBuilder(const AtomNetlist& netlist, - AtomLookup& netlist_lookup); + AtomLookup& netlist_lookup, + const LogicalModels& models); std::unique_ptr timing_graph(bool allow_dangling_combinational_nodes); diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 2574c505b57..c31c7ab08be 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -45,38 +45,6 @@ static void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lo /******************** Subroutine definitions *********************************/ -const t_model* find_model(const t_model* models, const std::string& name, bool required) { - for (const t_model* model = models; model != nullptr; model = model->next) { - if (name == model->name) { - return model; - } - } - - if (required) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find architecture modedl '%s'\n", name.c_str()); - } - - return nullptr; -} - -const t_model_ports* find_model_port(const t_model* model, const std::string& name, bool required) { - VTR_ASSERT(model); - - for (const t_model_ports* model_ports : {model->inputs, model->outputs}) { - for (const t_model_ports* port = model_ports; port != nullptr; port = port->next) { - if (port->name == name) { - return port; - } - } - } - - if (required) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find port '%s; on architecture model '%s'\n", name.c_str(), model->name); - } - - return nullptr; -} - /** * print tabs given number of tabs to file */ @@ -830,7 +798,7 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t } auto& atom_ctx = g_vpr_ctx.atom(); - if (cur_pb_type->model != atom_ctx.netlist().block_model(blk_id)) { + if (cur_pb_type->model_id != atom_ctx.netlist().block_model(blk_id)) { //Primitive and atom do not match return false; } @@ -987,7 +955,7 @@ const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomPB VTR_ASSERT(pb_gnode); //The graph node and pin/block should agree on the model they represent - VTR_ASSERT(netlist.block_model(blk_id) == pb_gnode->pb_type->model); + VTR_ASSERT(netlist.block_model(blk_id) == pb_gnode->pb_type->model_id); //Get the pin index AtomPortId port_id = netlist.pin_port(pin_id); diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index f2b62cfac1c..762efd36c5d 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -15,9 +15,6 @@ class DeviceGrid; class UserRouteConstraints; -const t_model* find_model(const t_model* models, const std::string& name, bool required = true); -const t_model_ports* find_model_port(const t_model* model, const std::string& name, bool required = true); - void print_tabs(FILE* fpout, int num_tab); bool is_clb_external_pin(ClusterBlockId blk_id, int pb_pin_id); diff --git a/vpr/test/test_interchange_device.cpp b/vpr/test/test_interchange_device.cpp index f344adace1b..324d757830a 100644 --- a/vpr/test/test_interchange_device.cpp +++ b/vpr/test/test_interchange_device.cpp @@ -1,8 +1,7 @@ #include "catch2/catch_test_macros.hpp" +#include "logic_types.h" #include "read_fpga_interchange_arch.h" -#include "arch_util.h" -#include "vpr_api.h" #include #include #include @@ -21,21 +20,24 @@ TEST_CASE("read_interchange_models", "[vpr]") { std::unordered_set models = {"IB", "OB", "DFFR", "DFFS", "GND", "VCC"}; // Check that there are exactly the expected models - for (auto* model = arch.models; model != nullptr; model = model->next) { - std::string name = model->name; - REQUIRE(models.find(name) != models.end()); - models.erase(name); + for (LogicalModelId model_id : arch.models.user_models()) { + std::string model_name = arch.models.model_name(model_id); + REQUIRE(models.find(model_name) != models.end()); + models.erase(model_name); } REQUIRE(models.size() == 0); - std::unordered_set lib_models = {MODEL_INPUT, MODEL_OUTPUT, MODEL_LATCH, MODEL_NAMES}; + std::unordered_set lib_models = {LogicalModels::MODEL_INPUT, + LogicalModels::MODEL_OUTPUT, + LogicalModels::MODEL_LATCH, + LogicalModels::MODEL_NAMES}; // Check that there are exactly the expected models - for (auto* model = arch.model_library; model != nullptr; model = model->next) { - std::string name = model->name; - REQUIRE(lib_models.find(name) != lib_models.end()); - lib_models.erase(name); + for (LogicalModelId model_id : arch.models.library_models()) { + std::string model_name = arch.models.model_name(model_id); + REQUIRE(lib_models.find(model_name) != lib_models.end()); + lib_models.erase(model_name); } REQUIRE(lib_models.size() == 0); diff --git a/vpr/test/test_interchange_netlist.cpp b/vpr/test/test_interchange_netlist.cpp index ac1fdfb15f9..1e8804469fb 100644 --- a/vpr/test/test_interchange_netlist.cpp +++ b/vpr/test/test_interchange_netlist.cpp @@ -1,11 +1,10 @@ #include "catch2/catch_test_macros.hpp" +#include "globals.h" #include "read_circuit.h" #include "read_fpga_interchange_arch.h" -#include "arch_util.h" -#include "vpr_api.h" +#include "vpr_types.h" #include -#include #include namespace { @@ -21,8 +20,6 @@ TEST_CASE("read_interchange_netlist", "[vpr]") { FPGAInterchangeReadArch(kArchFile, /*timing_enabled=*/true, &arch, physical_tile_types, logical_block_types); - vpr_setup.user_models = arch.models; - vpr_setup.library_models = arch.model_library; vpr_setup.PackerOpts.circuit_file_name = "lut.netlist"; /* Read blif file and sweep unused components */ From ec8d7d87424a1b934155b7d4e9fbe2cabe891e86 Mon Sep 17 00:00:00 2001 From: Fred Tombs Date: Wed, 30 Apr 2025 11:50:57 -0400 Subject: [PATCH 068/176] fix comments from alex --- vpr/src/place/initial_placement.cpp | 2 -- vpr/src/place/place_util.cpp | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 7f658ccb968..312ba533612 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -1208,9 +1208,7 @@ bool try_place_macro(const t_pl_macro& pl_macro, return macro_placed; } - // called from initial placement if (macro_can_be_placed(pl_macro, head_pos, /*check_all_legality=*/true, blk_loc_registry)) { - // Place down the macromacro_can_be_placed macro_placed = true; VTR_LOGV_DEBUG(f_placer_debug, "\t\t\t\tMacro is placed at the given location\n"); for (const t_pl_macro_member& pl_macro_member : pl_macro.members) { diff --git a/vpr/src/place/place_util.cpp b/vpr/src/place/place_util.cpp index ad201120acb..7fdf3383a06 100644 --- a/vpr/src/place/place_util.cpp +++ b/vpr/src/place/place_util.cpp @@ -191,7 +191,7 @@ bool macro_can_be_placed(const t_pl_macro& pl_macro, * floorplan constraint is not supported by analytical placement yet, * hence, if macro_can_be_placed is called from analytical placer, no further actions are required. */ - if (not check_all_legality) { + if (!check_all_legality) { continue; } From 81c3425c694e34ef5dfb4c9f7aa7f9e9f74cf303 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 30 Apr 2025 12:40:08 -0400 Subject: [PATCH 069/176] revert prepacker changes --- vpr/src/pack/prepack.cpp | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 60a2dffe68e..344d8184a88 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -117,8 +117,6 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, const AtomNetlist& atom_nlist); -static t_pb_graph_pin* get_compatible_chain_root_pin(const t_pack_patterns* chain_pattern, const AtomBlockId blk_id); - static void print_chain_starting_points(t_pack_patterns* chain_pattern); /*****************************************/ @@ -1174,17 +1172,6 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, return AtomBlockId::INVALID(); } -static t_pb_graph_pin* get_compatible_chain_root_pin(const t_pack_patterns* chain_pattern, const AtomBlockId blk_id) { - for (const auto& chain : chain_pattern->chain_root_pins) { - for (const auto& tie_off : chain) { - if (primitive_type_feasible(blk_id, tie_off->parent_node->pb_type)) { - return tie_off; - } - } - } - return nullptr; -} - static void print_pack_molecules(const char* fname, const std::vector& list_of_pack_patterns, const int num_pack_patterns, @@ -1341,13 +1328,15 @@ static AtomBlockId find_new_root_atom_for_chain(const AtomBlockId blk_id, const AtomNetlist& atom_nlist) { AtomBlockId new_root_blk_id; t_pb_graph_pin* root_ipin; + t_pb_graph_node* root_pb_graph_node; t_model_ports* model_port; VTR_ASSERT(list_of_pack_patterns->is_chain == true); VTR_ASSERT(list_of_pack_patterns->chain_root_pins.size()); - root_ipin = get_compatible_chain_root_pin(list_of_pack_patterns, blk_id); + root_ipin = list_of_pack_patterns->chain_root_pins[0][0]; + root_pb_graph_node = root_ipin->parent_node; - if (root_ipin == nullptr) { + if (primitive_type_feasible(blk_id, root_pb_graph_node->pb_type) == false) { return AtomBlockId::INVALID(); } @@ -1642,7 +1631,7 @@ static void init_molecule_chain_info(const AtomBlockId blk_id, // pattern assigned to it and the input block should be valid VTR_ASSERT(molecule.pack_pattern && blk_id); - auto root_ipin = get_compatible_chain_root_pin(molecule.pack_pattern, blk_id); + auto root_ipin = molecule.pack_pattern->chain_root_pins[0][0]; auto model_pin = root_ipin->port->model_port; auto pin_bit = root_ipin->pin_number; From 15b04dd2fea42bff7be47cbdb5578d4f28c14950 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 30 Apr 2025 12:46:42 -0400 Subject: [PATCH 070/176] [vpr][pack] add get_pattern_blocks --- vpr/src/pack/prepack.cpp | 49 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 344d8184a88..4d513f79725 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -117,6 +117,14 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, const AtomNetlist& atom_nlist); +/** + * @brief Get an unordered set of all pb_types in the given pack pattern + * + * @param pack_pattern Pack pattern to get pb_types from + * @return std::unordered_set Set of pb_types in the pack pattern + */ +static std::unordered_set get_pattern_blocks(const t_pack_patterns* pack_pattern); + static void print_chain_starting_points(t_pack_patterns* chain_pattern); /*****************************************/ @@ -1172,6 +1180,47 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, return AtomBlockId::INVALID(); } +static std::unordered_set get_pattern_blocks(const t_pack_patterns* pack_pattern) { + std::unordered_set pattern_blocks; + + auto connections = pack_pattern->root_block->connections; + if (connections == nullptr) { + return pattern_blocks; + } + std::unordered_set visited_from_pins; + std::unordered_set visited_to_pins; + std::queue pack_pattern_blocks; + pack_pattern_blocks.push(connections->from_block); + /** Start from the root block of the pack pattern and add the connected block to the queue */ + while (!pack_pattern_blocks.empty()) { + auto current_pattern_block = pack_pattern_blocks.front(); + pack_pattern_blocks.pop(); + auto current_connenction = current_pattern_block->connections; + /** Iterate through all the connections of the current pattern block to + * add the connected block to the queue + */ + while (current_connenction != nullptr) { + if (visited_from_pins.count(current_connenction->from_pin)) { + if (visited_to_pins.count(current_connenction->to_pin)) { + /* We've already seen this connection */ + current_connenction = current_connenction->next; + continue; + } + } + /** To avoid visiting the same connection twice, since it is both stored in from_pin and to_pin, + * add the from_pin and to_pin to the visited sets + */ + visited_from_pins.insert(current_connenction->from_pin); + visited_to_pins.insert(current_connenction->to_pin); + /** The from_pin block belongs to the pattern block */ + pattern_blocks.insert(current_connenction->from_pin->port->parent_pb_type); + pack_pattern_blocks.push(current_connenction->to_block); + current_connenction = current_connenction->next; + } + } + return pattern_blocks; +} + static void print_pack_molecules(const char* fname, const std::vector& list_of_pack_patterns, const int num_pack_patterns, From b2547956160d987f3df77e71815578d2bdd87410 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 30 Apr 2025 12:54:40 -0400 Subject: [PATCH 071/176] [vpr][pack] add blocks in get_all_connected_primitive_pins if they are a part of the pattern --- vpr/src/pack/prepack.cpp | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 4d513f79725..cce478686d5 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -99,7 +99,9 @@ static void find_all_equivalent_chains(t_pack_patterns* chain_pattern, const t_p static void update_chain_root_pins(t_pack_patterns* chain_pattern, const std::vector& chain_input_pins); -static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector& connected_primitive_pins); +static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, + const std::unordered_set& pattern_blocks, + std::vector& connected_primitive_pins); static void init_molecule_chain_info(const AtomBlockId blk_id, t_pack_molecule& molecule, @@ -1613,9 +1615,10 @@ static void update_chain_root_pins(t_pack_patterns* chain_pattern, const std::vector& chain_input_pins) { std::vector> primitive_input_pins; + std::unordered_set pattern_blocks = get_pattern_blocks(chain_pattern); for (const auto pin_ptr : chain_input_pins) { std::vector connected_primitive_pins; - get_all_connected_primitive_pins(pin_ptr, connected_primitive_pins); + get_all_connected_primitive_pins(pin_ptr, pattern_blocks, connected_primitive_pins); /** * It is required that the chain pins are connected inside a complex @@ -1639,7 +1642,9 @@ static void update_chain_root_pins(t_pack_patterns* chain_pattern, * the Cin pin of all the adder primitives connected to this pin. Which is for typical architectures * will be only one pin connected to the very first adder in the cluster. */ -static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector& connected_primitive_pins) { +static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, + const std::unordered_set& pattern_blocks, + std::vector& connected_primitive_pins) { /* Skip pins for modes that are disabled for packing*/ if ((nullptr != cluster_input_pin->parent_node->pb_type->parent_mode) && (true == cluster_input_pin->parent_node->pb_type->parent_mode->disable_packing)) { @@ -1650,9 +1655,11 @@ static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input const auto& output_edge = cluster_input_pin->output_edges[iedge]; for (int ipin = 0; ipin < output_edge->num_output_pins; ipin++) { if (output_edge->output_pins[ipin]->is_primitive_pin()) { - connected_primitive_pins.push_back(output_edge->output_pins[ipin]); + if (pattern_blocks.find(output_edge->output_pins[ipin]->parent_node->pb_type) != pattern_blocks.end()) { + connected_primitive_pins.push_back(output_edge->output_pins[ipin]); + } } else { - get_all_connected_primitive_pins(output_edge->output_pins[ipin], connected_primitive_pins); + get_all_connected_primitive_pins(output_edge->output_pins[ipin], pattern_blocks, connected_primitive_pins); } } } From 0f9cffb32b15b5a36849878a3099c7c444974794 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 30 Apr 2025 12:56:02 -0400 Subject: [PATCH 072/176] make format --- vpr/src/pack/prepack.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index cce478686d5..044debfaf5d 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -1200,7 +1200,7 @@ static std::unordered_set get_pattern_blocks(const t_pack_patterns* auto current_connenction = current_pattern_block->connections; /** Iterate through all the connections of the current pattern block to * add the connected block to the queue - */ + */ while (current_connenction != nullptr) { if (visited_from_pins.count(current_connenction->from_pin)) { if (visited_to_pins.count(current_connenction->to_pin)) { @@ -1211,7 +1211,7 @@ static std::unordered_set get_pattern_blocks(const t_pack_patterns* } /** To avoid visiting the same connection twice, since it is both stored in from_pin and to_pin, * add the from_pin and to_pin to the visited sets - */ + */ visited_from_pins.insert(current_connenction->from_pin); visited_to_pins.insert(current_connenction->to_pin); /** The from_pin block belongs to the pattern block */ @@ -1642,7 +1642,7 @@ static void update_chain_root_pins(t_pack_patterns* chain_pattern, * the Cin pin of all the adder primitives connected to this pin. Which is for typical architectures * will be only one pin connected to the very first adder in the cluster. */ -static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, +static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, const std::unordered_set& pattern_blocks, std::vector& connected_primitive_pins) { /* Skip pins for modes that are disabled for packing*/ From 73ec320077ab1f5665dd4a698cb08a0ee9657b5b Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 1 May 2025 09:40:09 +0000 Subject: [PATCH 073/176] Bump libs/EXTERNAL/libcatch2 from `76f70b1` to `5abfc0a` Bumps [libs/EXTERNAL/libcatch2](https://github.com/catchorg/Catch2) from `76f70b1` to `5abfc0a`. - [Release notes](https://github.com/catchorg/Catch2/releases) - [Commits](https://github.com/catchorg/Catch2/compare/76f70b1403dbc0781216f49e20e45b71f7eccdd8...5abfc0aa9c1ef4cb40c9f387495134dab02e1af2) --- updated-dependencies: - dependency-name: libs/EXTERNAL/libcatch2 dependency-version: 5abfc0aa9c1ef4cb40c9f387495134dab02e1af2 dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- libs/EXTERNAL/libcatch2 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/EXTERNAL/libcatch2 b/libs/EXTERNAL/libcatch2 index 76f70b1403d..5abfc0aa9c1 160000 --- a/libs/EXTERNAL/libcatch2 +++ b/libs/EXTERNAL/libcatch2 @@ -1 +1 @@ -Subproject commit 76f70b1403dbc0781216f49e20e45b71f7eccdd8 +Subproject commit 5abfc0aa9c1ef4cb40c9f387495134dab02e1af2 From 73746c92047802ce4725d8304e77aecb408b334a Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 1 May 2025 08:50:26 -0400 Subject: [PATCH 074/176] [vpr][pack] add more comments --- vpr/src/pack/prepack.cpp | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 044debfaf5d..243b0b69a67 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -99,6 +99,14 @@ static void find_all_equivalent_chains(t_pack_patterns* chain_pattern, const t_p static void update_chain_root_pins(t_pack_patterns* chain_pattern, const std::vector& chain_input_pins); +/** + * @brief Get all primitive pins connected to the given cluster input pin + * + * @param cluster_input_pin Cluster input pin to get connected primitive pins from + * @param pattern_blocks Set of pb_types in the pack pattern. Pins on the blocks in this set will + * be added to the connected_primitive_pins vector + * @param connected_primitive_pins Vector to store connected primitive pins + */ static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, const std::unordered_set& pattern_blocks, std::vector& connected_primitive_pins); @@ -125,7 +133,7 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, * @param pack_pattern Pack pattern to get pb_types from * @return std::unordered_set Set of pb_types in the pack pattern */ -static std::unordered_set get_pattern_blocks(const t_pack_patterns* pack_pattern); +static std::unordered_set get_pattern_blocks(const t_pack_patterns& pack_pattern); static void print_chain_starting_points(t_pack_patterns* chain_pattern); @@ -1182,10 +1190,10 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, return AtomBlockId::INVALID(); } -static std::unordered_set get_pattern_blocks(const t_pack_patterns* pack_pattern) { +static std::unordered_set get_pattern_blocks(const t_pack_patterns& pack_pattern) { std::unordered_set pattern_blocks; - auto connections = pack_pattern->root_block->connections; + t_pack_pattern_connections* connections = pack_pattern.root_block->connections; if (connections == nullptr) { return pattern_blocks; } @@ -1195,9 +1203,9 @@ static std::unordered_set get_pattern_blocks(const t_pack_patterns* pack_pattern_blocks.push(connections->from_block); /** Start from the root block of the pack pattern and add the connected block to the queue */ while (!pack_pattern_blocks.empty()) { - auto current_pattern_block = pack_pattern_blocks.front(); + t_pack_pattern_block* current_pattern_block = pack_pattern_blocks.front(); pack_pattern_blocks.pop(); - auto current_connenction = current_pattern_block->connections; + t_pack_pattern_connections* current_connenction = current_pattern_block->connections; /** Iterate through all the connections of the current pattern block to * add the connected block to the queue */ @@ -1615,7 +1623,7 @@ static void update_chain_root_pins(t_pack_patterns* chain_pattern, const std::vector& chain_input_pins) { std::vector> primitive_input_pins; - std::unordered_set pattern_blocks = get_pattern_blocks(chain_pattern); + std::unordered_set pattern_blocks = get_pattern_blocks(*chain_pattern); for (const auto pin_ptr : chain_input_pins) { std::vector connected_primitive_pins; get_all_connected_primitive_pins(pin_ptr, pattern_blocks, connected_primitive_pins); @@ -1655,6 +1663,7 @@ static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input const auto& output_edge = cluster_input_pin->output_edges[iedge]; for (int ipin = 0; ipin < output_edge->num_output_pins; ipin++) { if (output_edge->output_pins[ipin]->is_primitive_pin()) { + /** Add the output pin to the vector only if it belongs to a pb_type registered in the pattern_blocks set */ if (pattern_blocks.find(output_edge->output_pins[ipin]->parent_node->pb_type) != pattern_blocks.end()) { connected_primitive_pins.push_back(output_edge->output_pins[ipin]); } From a410349af43a5e2557fad09e8103ea1dfb5d1c64 Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Wed, 30 Apr 2025 11:07:37 -0400 Subject: [PATCH 075/176] Add helper functions to t_pb_type --- libs/libarchfpga/src/physical_types.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index ace0f5be509..ebfcde4b9c9 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1068,6 +1068,14 @@ struct t_pb_type { t_pb_type_power* pb_type_power = nullptr; t_metadata_dict meta; + + inline bool is_root() const { + return parent_mode == nullptr; + } + + inline bool is_primitive() const { + return num_modes == 0; + } }; /** Describes an operational mode of a clustered logic block From 5de62c20da165331d5179c2fb3860de8733bc1a1 Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Wed, 30 Apr 2025 12:32:08 -0400 Subject: [PATCH 076/176] Change t_pb_type users to use helper functions --- libs/libarchfpga/src/arch_util.cpp | 2 +- libs/libarchfpga/src/physical_types.h | 2 +- libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +- .../flat_placement_mass_calculator.cpp | 2 +- vpr/src/base/netlist_walker.cpp | 2 +- vpr/src/base/read_netlist.cpp | 2 +- vpr/src/draw/intra_logic_block.cpp | 33 ++++++++----------- vpr/src/pack/cluster_legalizer.cpp | 19 +++++------ vpr/src/pack/cluster_util.cpp | 4 +-- vpr/src/pack/lb_type_rr_graph.cpp | 2 +- vpr/src/pack/output_clustering.cpp | 20 +++++------ vpr/src/pack/pb_type_graph.cpp | 4 +-- vpr/src/pack/pb_type_graph_annotations.cpp | 2 +- vpr/src/pack/prepack.cpp | 2 +- vpr/src/power/power_sizing.cpp | 2 +- vpr/src/util/vpr_utils.cpp | 6 ++-- vpr/test/test_vpr.cpp | 2 +- 17 files changed, 51 insertions(+), 57 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index c6c8d65fff3..b09bddb0382 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -1077,7 +1077,7 @@ bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::string& bl if (pb_type->blif_model != nullptr) { //Leaf pb_type - VTR_ASSERT(pb_type->num_modes == 0); + VTR_ASSERT(pb_type->is_primitive()); if (blif_model_name == pb_type->blif_model || ".subckt " + blif_model_name == pb_type->blif_model) { return true; diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index ebfcde4b9c9..f730aa48f74 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1361,7 +1361,7 @@ class t_pb_graph_node { t_interconnect_pins** interconnect_pins; /* [0..num_modes-1][0..num_interconnect_in_mode] */ // Returns true if this pb_graph_node represents a primitive type (primitives have 0 modes) - bool is_primitive() const { return this->pb_type->num_modes == 0; } + bool is_primitive() const { return this->pb_type->is_primitive(); } // Returns true if this pb_graph_node represents a root graph node (ex. clb) bool is_root() const { return this->parent_pb_graph_node == nullptr; } diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 9d54b9e2a41..3661516a530 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -1415,7 +1415,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, pb_type->pb_type_power->leakage_default_mode = 0; int mode_idx = 0; - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* The pb_type operates in an implied one mode */ pb_type->num_modes = 1; pb_type->modes = new t_mode[pb_type->num_modes]; diff --git a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp index d9978cdad82..3581c4ce868 100644 --- a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp +++ b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp @@ -68,7 +68,7 @@ static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type) { // capacities as if the pb could choose either one. PrimitiveVector capacity; // If this is a leaf / primitive, create the base PrimitiveVector capacity. - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { LogicalModelId model_id = pb_type->model_id; VTR_ASSERT(model_id.is_valid()); capacity.add_val_to_dim(get_model_mass(model_id), (size_t)model_id); diff --git a/vpr/src/base/netlist_walker.cpp b/vpr/src/base/netlist_walker.cpp index 3411210f3cb..4539ed078af 100644 --- a/vpr/src/base/netlist_walker.cpp +++ b/vpr/src/base/netlist_walker.cpp @@ -42,7 +42,7 @@ void NetlistWalker::walk_blocks(const t_pb_routes& top_pb_route, const t_pb* pb) //Recurse const t_pb_type* pb_type = pb->pb_graph_node->pb_type; - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { const t_mode* mode = &pb_type->modes[pb->mode]; for (int i = 0; i < mode->num_pb_type_children; i++) { for (int j = 0; j < mode->pb_type_children[i].num_pb; j++) { diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index b498b8671b2..eb2638ee4c0 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -463,7 +463,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p VTR_ASSERT(clb_nlist->block_ports(index).size() == (unsigned)pb_type->num_ports); } - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* A primitive type */ AtomBlockId blk_id = atom_ctx.netlist().find_block(pb->name); if (!blk_id) { diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index e253bcdafea..48993eaf8a7 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -202,8 +202,8 @@ static int draw_internal_find_max_lvl(const t_pb_type& pb_type) { t_mode mode; int max_levels = 0; - /* If no modes, we have reached the end of pb_graph */ - if (pb_type.num_modes == 0) + /* If pb_type is a primitive, we have reached the end of pb_graph */ + if (pb_type.is_primitive()) return (pb_type.depth); for (i = 0; i < pb_type.num_modes; ++i) { @@ -221,30 +221,25 @@ static int draw_internal_find_max_lvl(const t_pb_type& pb_type) { * calls helper function to compute bounding box values. */ static void draw_internal_load_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, float parent_width, float parent_height) { - int i, j, k; - t_pb_type* pb_type; - int num_modes, num_children, num_pb; - t_mode mode; float blk_width = 0.; float blk_height = 0.; - /* Get information about the pb_type */ - pb_type = pb_graph_node->pb_type; - num_modes = pb_type->num_modes; - - /* If no modes, we have reached the end of pb_graph */ - if (num_modes == 0) + t_pb_type* pb_type = pb_graph_node->pb_type; + int num_modes = pb_type->num_modes; + /* If pb_type is primitive, we have reached the end of pb_graph */ + if (pb_type->is_primitive()) { return; + } - for (i = 0; i < num_modes; ++i) { - mode = pb_type->modes[i]; - num_children = mode.num_pb_type_children; + for (int i = 0; i < num_modes; ++i) { + t_mode mode = pb_type->modes[i]; + int num_children = mode.num_pb_type_children; - for (j = 0; j < num_children; ++j) { + for (int j = 0; j < num_children; ++j) { /* Find the number of instances for each child pb_type. */ - num_pb = mode.pb_type_children[j].num_pb; + int num_pb = mode.pb_type_children[j].num_pb; - for (k = 0; k < num_pb; ++k) { + for (int k = 0; k < num_pb; ++k) { /* Compute bound box for block. Don't call if pb_type is root-level pb. */ draw_internal_calc_coords(type_descrip_index, &pb_graph_node->child_pb_graph_nodes[i][j][k], @@ -721,7 +716,7 @@ t_pb* highlight_sub_block_helper(const ClusterBlockId clb_index, t_pb* pb, const // and if pb is dud if (pb_type->depth + 1 > max_depth || pb->child_pbs == nullptr - || pb_type->num_modes == 0) { + || pb_type->is_primitive()) { return nullptr; } diff --git a/vpr/src/pack/cluster_legalizer.cpp b/vpr/src/pack/cluster_legalizer.cpp index 0c0040ac3e7..cffeebddd3e 100644 --- a/vpr/src/pack/cluster_legalizer.cpp +++ b/vpr/src/pack/cluster_legalizer.cpp @@ -65,7 +65,7 @@ static void check_cluster_atom_blocks(t_pb* pb, std::unordered_set& const AtomContext& atom_ctx = g_vpr_ctx.atom(); const t_pb_type* pb_type = pb->pb_graph_node->pb_type; - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* primitive */ AtomBlockId blk_id = atom_pb_lookup.pb_atom(pb); if (blk_id) { @@ -396,7 +396,7 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ static bool primitive_feasible(const AtomBlockId blk_id, t_pb* cur_pb, const AtomPBBimap& atom_to_pb) { const t_pb_type* cur_pb_type = cur_pb->pb_graph_node->pb_type; - VTR_ASSERT(cur_pb_type->num_modes == 0); /* primitive */ + VTR_ASSERT(cur_pb_type->is_primitive()); /* primitive */ AtomBlockId cur_pb_blk_id = atom_to_pb.pb_atom(cur_pb); if (cur_pb_blk_id && cur_pb_blk_id != blk_id) { @@ -511,9 +511,7 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, return e_block_pack_status::BLK_FAILED_FEASIBLE; } - bool is_primitive = (pb_type->num_modes == 0); - - if (is_primitive) { + if (pb_type->is_primitive()) { VTR_ASSERT(!atom_to_pb.pb_atom(pb) && atom_to_pb.atom_pb(blk_id) == nullptr && atom_cluster[blk_id] == LegalizationClusterId::INVALID()); @@ -576,7 +574,7 @@ static void reset_lookahead_pins_used(t_pb* cur_pb) { return; /* No pins used, no need to continue */ } - if (pb_type->num_modes > 0 && cur_pb->name != nullptr) { + if (!pb_type->is_primitive() && cur_pb->name != nullptr) { for (int i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { cur_pb->pb_stats->lookahead_input_pins_used[i].clear(); } @@ -821,7 +819,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, const AtomPBBimap& atom_to_pb) { // run recursively till a leaf (primitive) pb block is reached const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type; - if (pb_type->num_modes > 0 && cur_pb->name != nullptr) { + if (!pb_type->is_primitive() && cur_pb->name != nullptr) { if (cur_pb->child_pbs != nullptr) { for (int i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; i++) { if (cur_pb->child_pbs[i] != nullptr) { @@ -835,6 +833,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, // find if this child (primitive) pb block has an atom mapped to it, // if yes compute and mark lookahead pins used for that pb block AtomBlockId blk_id = atom_to_pb.pb_atom(cur_pb); + // TODO: Primitive pb_types should have non-null blif_model. Shoud this be an assertion? if (pb_type->blif_model != nullptr && blk_id) { compute_and_mark_lookahead_pins_used(blk_id, atom_cluster, atom_to_pb); } @@ -848,7 +847,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, static bool check_lookahead_pins_used(t_pb* cur_pb, t_ext_pin_util max_external_pin_util) { const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type; - if (pb_type->num_modes > 0 && cur_pb->name) { + if (!pb_type->is_primitive() && cur_pb->name) { for (int i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { size_t class_size = cur_pb->pb_graph_node->input_pin_class_size[i]; @@ -1015,7 +1014,7 @@ static void revert_place_atom_block(const AtomBlockId blk_id, static void commit_lookahead_pins_used(t_pb* cur_pb) { const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type; - if (pb_type->num_modes > 0 && cur_pb->name) { + if (!pb_type->is_primitive() && cur_pb->name) { for (int i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { VTR_ASSERT(cur_pb->pb_stats->lookahead_input_pins_used[i].size() <= (unsigned int)cur_pb->pb_graph_node->input_pin_class_size[i]); for (size_t j = 0; j < cur_pb->pb_stats->lookahead_input_pins_used[i].size(); j++) { @@ -1076,7 +1075,7 @@ static bool cleanup_pb(t_pb* pb) { t_pb_type* pb_type = pb_child->pb_graph_node->pb_type; /* Primitive, check occupancy */ - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { if (pb_child->name != nullptr) { can_free = false; } diff --git a/vpr/src/pack/cluster_util.cpp b/vpr/src/pack/cluster_util.cpp index fcb4f88f926..e3361971b3d 100644 --- a/vpr/src/pack/cluster_util.cpp +++ b/vpr/src/pack/cluster_util.cpp @@ -215,7 +215,7 @@ size_t update_pb_type_count(const t_pb* pb, std::map& pb_type_c pb_type_count[pb_type]++; - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { for (int i = 0; i < mode->num_pb_type_children; i++) { for (int j = 0; j < mode->pb_type_children[i].num_pb; j++) { if (pb->child_pbs[i] && pb->child_pbs[i][j].name) { @@ -365,7 +365,7 @@ bool pb_used_for_blif_model(const t_pb* pb, const std::string& blif_model_name) } } - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { for (int i = 0; i < mode->num_pb_type_children; i++) { for (int j = 0; j < mode->pb_type_children[i].num_pb; j++) { if (pb->child_pbs[i] && pb->child_pbs[i][j].name) { diff --git a/vpr/src/pack/lb_type_rr_graph.cpp b/vpr/src/pack/lb_type_rr_graph.cpp index 12082386275..99a859c3aba 100644 --- a/vpr/src/pack/lb_type_rr_graph.cpp +++ b/vpr/src/pack/lb_type_rr_graph.cpp @@ -296,7 +296,7 @@ static void alloc_and_load_lb_type_rr_graph_for_pb_graph_node(const t_pb_graph_n parent_node = pb_graph_node->parent_pb_graph_node; int num_modes; - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* This pb_graph_node is a terminating leaf node (primitive) */ /* alloc and load input pins that connect to sinks */ diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp index 60a371aee46..28582294ce4 100644 --- a/vpr/src/pack/output_clustering.cpp +++ b/vpr/src/pack/output_clustering.cpp @@ -229,7 +229,7 @@ static std::string clustering_xml_interconnect_text(t_logical_block_type_ptr typ if (prev_node == OPEN) { /* No previous driver implies that this is either a top-level input pin or a primitive output pin */ const t_pb_graph_pin* cur_pin = pb_graph_pin_lookup_from_index_by_type.pb_gpin(type->index, inode); - VTR_ASSERT(cur_pin->parent_node->pb_type->parent_mode == nullptr || (cur_pin->is_primitive_pin() && cur_pin->port->type == OUT_PORT)); + VTR_ASSERT(cur_pin->parent_node->pb_type->is_root() || (cur_pin->is_primitive_pin() && cur_pin->port->type == OUT_PORT)); return clustering_xml_net_text(pb_route[inode].atom_net_id); } else { const t_pb_graph_pin* cur_pin = pb_graph_pin_lookup_from_index_by_type.pb_gpin(type->index, inode); @@ -291,7 +291,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo for (j = 0; j < pb_type->ports[i].num_pins; j++) { const t_pb_graph_pin* pin = &pb_graph_node->output_pins[port_index][j]; node_index = pin->pin_count_in_cluster; - if (pb_type->num_modes > 0 && pb_route.count(node_index) && pb_route[node_index].atom_net_id) { + if (!pb_type->is_primitive() && pb_route.count(node_index) && pb_route[node_index].atom_net_id) { prev_node = pb_route[node_index].driver_pb_pin_id; const t_pb_graph_pin* prev_pin = pb_graph_pin_lookup_from_index_by_type.pb_gpin(type->index, prev_node); const t_pb_graph_edge* edge = get_edge_between_pins(prev_pin, pin); @@ -330,7 +330,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo for (j = 0; j < pb_type->ports[i].num_pins; j++) { node_index = pb_graph_node->input_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == nullptr) { + if (pb_type->is_root()) { pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id)); } else { pins.push_back(clustering_xml_interconnect_text(type, pb_graph_pin_lookup_from_index_by_type, node_index, pb_route)); @@ -371,7 +371,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo std::vector pins; for (j = 0; j < pb_type->ports[i].num_pins; j++) { node_index = pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == nullptr) { + if (pb_type->is_root()) { pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id)); } else { pins.push_back(clustering_xml_interconnect_text(type, pb_graph_pin_lookup_from_index_by_type, node_index, pb_route)); @@ -382,7 +382,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo } } - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { for (i = 0; i < mode->num_pb_type_children; i++) { child_pb_type = &mode->pb_type_children[i]; for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { @@ -426,7 +426,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty block_node.append_attribute("name") = pb->name; block_node.append_attribute("instance") = vtr::string_fmt("%s[%d]", pb_type->name, pb_index).c_str(); - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { block_node.append_attribute("mode") = mode->name; } else { const auto& atom_ctx = g_vpr_ctx.atom(); @@ -460,7 +460,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty for (j = 0; j < pb_type->ports[i].num_pins; j++) { node_index = pb->pb_graph_node->input_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == nullptr) { + if (pb_type->is_root()) { if (pb_route.count(node_index)) { pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id)); } else { @@ -475,7 +475,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty //The cluster router may have rotated equivalent pins (e.g. LUT inputs), //record the resulting rotation here so it can be unambigously mapped //back to the atom netlist - if (pb_type->ports[i].equivalent != PortEquivalence::NONE && pb_type->parent_mode != nullptr && pb_type->num_modes == 0) { + if (pb_type->ports[i].equivalent != PortEquivalence::NONE && pb_type->parent_mode != nullptr && pb_type->is_primitive()) { //This is a primitive with equivalent inputs auto& atom_ctx = g_vpr_ctx.atom(); @@ -560,7 +560,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty std::vector pins; for (j = 0; j < pb_type->ports[i].num_pins; j++) { node_index = pb->pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == nullptr) { + if (pb_type->is_root()) { if (pb_route.count(node_index)) { pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id)); } else { @@ -575,7 +575,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty } } - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { for (i = 0; i < mode->num_pb_type_children; i++) { for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { /* If child pb is not used but routing is used, I must print things differently */ diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 266f3d38f79..6bd874f6e2b 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -281,7 +281,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node, pb_graph_node->pin_num_range.low = pin_count_in_cluster; for (i = 0; i < pb_type->num_ports; i++) { if (pb_type->ports[i].model_port) { - VTR_ASSERT(pb_type->num_modes == 0); + VTR_ASSERT(pb_type->is_primitive()); } else { VTR_ASSERT(pb_type->num_modes != 0 || pb_type->ports[i].is_clock); } @@ -1645,7 +1645,7 @@ static void echo_pb_rec(const t_pb_graph_node* pb_graph_node, const int level, F } fprintf(fp, "\n"); - if (pb_graph_node->pb_type->num_modes > 0) { + if (!pb_graph_node->pb_type->is_primitive()) { print_tabs(fp, level); fprintf(fp, "Children:\n"); } diff --git a/vpr/src/pack/pb_type_graph_annotations.cpp b/vpr/src/pack/pb_type_graph_annotations.cpp index 63a60188f20..a01fec982b5 100644 --- a/vpr/src/pack/pb_type_graph_annotations.cpp +++ b/vpr/src/pack/pb_type_graph_annotations.cpp @@ -47,7 +47,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { pb_type = pb_graph_node->pb_type; /* Load primitive critical path delays */ - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { annotations = pb_type->annotations; for (i = 0; i < pb_type->num_annotations; i++) { if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) { diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 344d8184a88..4f14aa94839 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -726,7 +726,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans // check if this input pin of the expansion edge has no driving pin if (expansion_edge->input_pins[i]->num_input_edges == 0) { // check if this input pin of the expansion edge belongs to a root block (i.e doesn't have a parent block) - if (expansion_edge->input_pins[i]->parent_node->pb_type->parent_mode == nullptr) { + if (expansion_edge->input_pins[i]->parent_node->pb_type->is_root()) { // This pack pattern extends to CLB (root pb block) input pin, // thus it extends across multiple logic blocks, treat as a chain packing_pattern.is_chain = true; diff --git a/vpr/src/power/power_sizing.cpp b/vpr/src/power/power_sizing.cpp index 9f35996eb2b..31738a8eb6e 100644 --- a/vpr/src/power/power_sizing.cpp +++ b/vpr/src/power/power_sizing.cpp @@ -312,7 +312,7 @@ static double power_count_transistors_pb_node(t_pb_graph_node* pb_node) { t_pb_type* pb_type = pb_node->pb_type; /* Check if this is a leaf node, or whether it has children */ - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* Leaf node */ tc_interc_max = 0; tc_children_max = power_count_transistors_primitive(pb_type); diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index c31c7ab08be..34c2156b98f 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -708,7 +708,7 @@ static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::reg if (pb_type->blif_model != nullptr) { //Leaf pb_type - VTR_ASSERT(pb_type->num_modes == 0); + VTR_ASSERT(pb_type->is_primitive()); if (std::regex_match(pb_type->blif_model, blif_model_regex)) { return true; } else { @@ -769,7 +769,7 @@ int get_max_nets_in_pb_type(const t_pb_type* pb_type) { } } } - if (pb_type->parent_mode == nullptr) { + if (pb_type->is_root()) { max_nets += pb_type->num_input_pins + pb_type->num_output_pins + pb_type->num_clock_pins; } @@ -1169,7 +1169,7 @@ static void load_pin_id_to_pb_mapping_rec(t_pb* cur_pb, t_pb** pin_id_to_pb_mapp } } - if (pb_type->num_modes == 0 || cur_pb->child_pbs == nullptr) { + if (pb_type->is_primitive() || cur_pb->child_pbs == nullptr) { return; } diff --git a/vpr/test/test_vpr.cpp b/vpr/test/test_vpr.cpp index 99651bfe5cd..2a4f7a7fc4a 100644 --- a/vpr/test/test_vpr.cpp +++ b/vpr/test/test_vpr.cpp @@ -71,7 +71,7 @@ TEST_CASE("read_arch_metadata", "[vpr]") { REQUIRE(pb_type_value != nullptr); CHECK_THAT(pb_type_value->as_string().get(&arch.strings), Equals("pb_type = io")); - REQUIRE(type.pb_type->num_modes > 0); + REQUIRE(!type.pb_type->is_primitive()); REQUIRE(type.pb_type->modes != nullptr); for (int imode = 0; imode < type.pb_type->num_modes; ++imode) { From fbe6a4043fb0a149146deefa1b564a0a22c21cdd Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Thu, 1 May 2025 16:34:18 -0400 Subject: [PATCH 077/176] Add documentation for t_pb_type::is_root and is_primitive --- libs/libarchfpga/src/physical_types.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index f730aa48f74..2c01a46650f 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1069,10 +1069,21 @@ struct t_pb_type { t_metadata_dict meta; + /** + * @brief Check if t_pb_type is the root of the pb graph. Root pb_types correspond to a single top level block type and map to a particular type + * of location in the FPGA device grid (e.g. Logic, DSP, RAM etc.) + * + * @return if t_pb_type is root ot not + */ inline bool is_root() const { return parent_mode == nullptr; } + /** + * @brief Check if t_pb_type is a primitive block or equivalently a leaf of the pb graph. + * + * @return if t_pb_type is primitive/leaf ot not + */ inline bool is_primitive() const { return num_modes == 0; } From c4ad99eb4fbde068a55b4cfa6406f01093afcacc Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Thu, 1 May 2025 16:34:55 -0400 Subject: [PATCH 078/176] Fix formatting in libarchfpga/physical_types.h --- libs/libarchfpga/src/physical_types.h | 72 +++++++++++++-------------- vpr/src/pack/cluster_legalizer.cpp | 1 - 2 files changed, 36 insertions(+), 37 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 2c01a46650f..c2459721d93 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1586,7 +1586,7 @@ enum e_directionality { }; /* X_AXIS: Data that describes an x-directed wire segment (CHANX) * - * Y_AXIS: Data that describes an y-directed wire segment (CHANY) * + * Y_AXIS: Data that describes an y-directed wire segment (CHANY) * * BOTH_AXIS: Data that can be applied to both x-directed and y-directed wire segment */ enum e_parallel_axis { X_AXIS, @@ -1643,65 +1643,65 @@ enum e_Fc_type { */ struct t_segment_inf { /** - * @brief The name of the segment type + * @brief The name of the segment type */ std::string name; /** - * @brief ratio of tracks which are of this segment type. + * @brief ratio of tracks which are of this segment type. */ int frequency; /** - * @brief Length (in clbs) of the segment. + * @brief Length (in clbs) of the segment. */ int length; /** - * @brief Index of the switch type that connects other wires to this segment. - * Note that this index is in relation to the switches from the architecture file, - * not the expanded list of switches that is built at the end of build_rr_graph. + * @brief Index of the switch type that connects other wires to this segment. + * Note that this index is in relation to the switches from the architecture file, + * not the expanded list of switches that is built at the end of build_rr_graph. */ short arch_wire_switch; /** - * @brief Index of the switch type that connects output pins to this segment. - * Note that this index is in relation to the switches from the architecture file, - * not the expanded list of switches that is built at the end of build_rr_graph. + * @brief Index of the switch type that connects output pins to this segment. + * Note that this index is in relation to the switches from the architecture file, + * not the expanded list of switches that is built at the end of build_rr_graph. */ short arch_opin_switch; /** - * @brief Same as arch_wire_switch but used only for decremental tracks if it is - * specified in the architecture file. If -1, this value was not set in the - * architecture file and arch_wire_switch should be used for "DEC_DIR" wire segments. + * @brief Same as arch_wire_switch but used only for decremental tracks if it is + * specified in the architecture file. If -1, this value was not set in the + * architecture file and arch_wire_switch should be used for "DEC_DIR" wire segments. */ short arch_wire_switch_dec = -1; /** - * @brief Same as arch_opin_switch but used only for decremental tracks if - * it is specified in the architecture file. If -1, this value was not set in - * the architecture file and arch_opin_switch should be used for "DEC_DIR" wire segments. + * @brief Same as arch_opin_switch but used only for decremental tracks if + * it is specified in the architecture file. If -1, this value was not set in + * the architecture file and arch_opin_switch should be used for "DEC_DIR" wire segments. */ short arch_opin_switch_dec = -1; /** - * @brief Index of the switch type that connects output pins (OPINs) to this - * segment from another die (layer). Note that this index is in relation to - * the switches from the architecture file, not the expanded list of switches - * that is built at the end of build_rr_graph. + * @brief Index of the switch type that connects output pins (OPINs) to this + * segment from another die (layer). Note that this index is in relation to + * the switches from the architecture file, not the expanded list of switches + * that is built at the end of build_rr_graph. */ short arch_inter_die_switch = -1; /** - * @brief The fraction of logic blocks along its length to which this segment can connect. - * (i.e. internal population). + * @brief The fraction of logic blocks along its length to which this segment can connect. + * (i.e. internal population). */ float frac_cb; /** - * @brief The fraction of the length + 1 switch blocks along the segment to which the segment can connect. - * Segments that aren't long lines must connect to at least two switch boxes. + * @brief The fraction of the length + 1 switch blocks along the segment to which the segment can connect. + * Segments that aren't long lines must connect to at least two switch boxes. */ float frac_sb; @@ -1718,27 +1718,27 @@ struct t_segment_inf { enum e_directionality directionality; /** - * @brief Defines what axis the segment is parallel to. See e_parallel_axis - * comments for more details on the values. + * @brief Defines what axis the segment is parallel to. See e_parallel_axis + * comments for more details on the values. */ enum e_parallel_axis parallel_axis; /** - * @brief A vector of booleans indicating whether the segment can connect to a logic block. + * @brief A vector of booleans indicating whether the segment can connect to a logic block. */ std::vector cb; /** - * @brief A vector of booleans indicating whether the segment can connect to a switch block. + * @brief A vector of booleans indicating whether the segment can connect to a switch block. */ std::vector sb; /** * @brief The index of the segment as stored in the appropriate Segs list. - * Upon loading the architecture, we use this field to keep track of the - * segment's index in the unified segment_inf vector. This is useful when - * building the rr_graph for different Y & X channels in terms of track - * distribution and segment type. + * Upon loading the architecture, we use this field to keep track of the + * segment's index in the unified segment_inf vector. This is useful when + * building the rr_graph for different Y & X channels in terms of track + * distribution and segment type. */ int seg_index; @@ -1747,7 +1747,7 @@ struct t_segment_inf { * Possible values are: * - GENERAL: The segment is part of the general routing resources. * - GCLK: The segment is part of the global routing network. - * For backward compatibility, this attribute is optional. If not specified, + * For backward compatibility, this attribute is optional. If not specified, * the resource type for the segment is considered to be GENERAL. */ enum SegResType res_type = SegResType::GENERAL; @@ -1797,12 +1797,12 @@ constexpr std::array SWITCH_T /* Constant/Reserved names for switches in architecture XML * Delayless switch: - * The zero-delay switch created by VPR internally + * The zero-delay switch created by VPR internally * This is a special switch just to ease CAD algorithms * It is mainly used in - * - the edges between SOURCE and SINK nodes in routing resource graphs + * - the edges between SOURCE and SINK nodes in routing resource graphs * - the edges in CLB-to-CLB connections (defined by in arch XML) - * + * */ constexpr const char* VPR_DELAYLESS_SWITCH_NAME = "__vpr_delayless_switch__"; diff --git a/vpr/src/pack/cluster_legalizer.cpp b/vpr/src/pack/cluster_legalizer.cpp index cffeebddd3e..7256a2c84f7 100644 --- a/vpr/src/pack/cluster_legalizer.cpp +++ b/vpr/src/pack/cluster_legalizer.cpp @@ -833,7 +833,6 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, // find if this child (primitive) pb block has an atom mapped to it, // if yes compute and mark lookahead pins used for that pb block AtomBlockId blk_id = atom_to_pb.pb_atom(cur_pb); - // TODO: Primitive pb_types should have non-null blif_model. Shoud this be an assertion? if (pb_type->blif_model != nullptr && blk_id) { compute_and_mark_lookahead_pins_used(blk_id, atom_cluster, atom_to_pb); } From 4275b6ad1a735f285d5a315e80bb73104c26b298 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 1 May 2025 16:18:06 -0700 Subject: [PATCH 079/176] [vpr][pack] change count method to find --- vpr/src/pack/prepack.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 243b0b69a67..20d783b45e6 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -1210,8 +1210,8 @@ static std::unordered_set get_pattern_blocks(const t_pack_patterns& * add the connected block to the queue */ while (current_connenction != nullptr) { - if (visited_from_pins.count(current_connenction->from_pin)) { - if (visited_to_pins.count(current_connenction->to_pin)) { + if (visited_from_pins.find(current_connenction->from_pin) != visited_from_pins.end()) { + if (visited_to_pins.find(current_connenction->to_pin) != visited_to_pins.end()) { /* We've already seen this connection */ current_connenction = current_connenction->next; continue; From 77998cc19c69e8cd0443f894f4460034aaf96a37 Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Thu, 1 May 2025 22:26:12 -0400 Subject: [PATCH 080/176] [Router] Updated the Regression Tests and Corresponding Golden Results Changed `multi_queue_num_threads` and `multi_queue_num_queues` settings in the CI strong regression tests to avoid QoR failure in the CI runs. The coverage of the regression tests for parallel connection router after this change is still fair. --- .../koios_test/config/config.txt | 4 ++-- .../koios_test/config/golden_results.txt | 10 ++++---- .../strong_flat_router/config/config.txt | 4 ++-- .../config/golden_results.txt | 10 ++++---- .../strong_multiclock/config/config.txt | 4 ++-- .../config/golden_results.txt | 4 ++-- .../strong_timing/config/config.txt | 4 ++-- .../strong_timing/config/golden_results.txt | 10 ++++---- .../config/config.txt | 8 +++---- .../config/golden_results.txt | 24 +++++++++---------- 10 files changed, 41 insertions(+), 41 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt index 3c7faa4d0f2..b7420ccf41d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt @@ -39,5 +39,5 @@ script_params_common=-track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt index db8e790d221..13c7fadca33 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 3.48 vpr 75.41 MiB -1 -1 0.19 18324 1 0.06 -1 -1 31768 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77216 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.21 0.000959753 0.000891145 0.0766671 0.0712909 -1 -1 -1 -1 82 3601 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.37 0.355125 0.327648 33448 250998 -1 3687 9 800 863 234820 89374 4.57723 4.57723 -726.049 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.06 0.21 -1 -1 0.04 0.0293975 0.0278224 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 3.89 vpr 75.53 MiB -1 -1 0.23 18320 1 0.05 -1 -1 31776 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77340 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.7 MiB 0.11 3253 1906 39109 13750 20961 4398 75.5 MiB 0.17 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.24 0.00102819 0.000958054 0.0952184 0.0886972 -1 -1 -1 -1 82 3585 15 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.58 0.448941 0.416021 33448 250998 -1 3715 9 792 819 214644 81314 4.57723 4.57723 -685.291 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.07 0.23 -1 -1 0.04 0.0342816 0.0320854 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.44 vpr 76.07 MiB -1 -1 0.24 17952 1 0.05 -1 -1 31776 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77900 130 40 596 562 1 356 185 14 14 196 dsp_top auto 37.0 MiB 0.10 3253 1906 39109 13750 20961 4398 76.1 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000977261 0.000906881 0.0777213 0.0722525 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.15 0.365923 0.337593 33448 250998 -1 3424 10 688 706 802567 802567 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.21 0.21 -1 -1 0.04 0.0310482 0.0293918 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.66 vpr 76.11 MiB -1 -1 0.19 18336 1 0.05 -1 -1 31752 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77936 130 40 596 562 1 356 185 14 14 196 dsp_top auto 37.0 MiB 0.10 3253 1906 39109 13750 20961 4398 76.1 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.21 0.000953879 0.00088635 0.076401 0.0709941 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.35 0.375353 0.346219 33448 250998 -1 3424 10 688 706 784337 784337 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.28 0.21 -1 -1 0.04 0.0314543 0.0297544 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.47 vpr 76.11 MiB -1 -1 0.19 18336 1 0.05 -1 -1 31764 -1 -1 12 130 0 -1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77936 130 40 596 562 1 356 185 14 14 196 dsp_top auto 37.0 MiB 0.10 3253 1906 39109 13750 20961 4398 76.1 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000953407 0.000885151 0.0766354 0.0712962 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.12 0.360483 0.332708 33448 250998 -1 3424 10 688 706 797445 321701 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.32 0.21 -1 -1 0.04 0.0323769 0.0306371 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 3.53 vpr 75.00 MiB -1 -1 0.20 17948 1 0.05 -1 -1 31776 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 76796 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.0 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000972896 0.000903976 0.0756961 0.0702652 -1 -1 -1 -1 82 3601 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.39 0.353988 0.326407 33448 250998 -1 3687 9 800 863 234820 89374 4.57723 4.57723 -726.049 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.06 0.21 -1 -1 0.04 0.029531 0.027938 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 3.67 vpr 75.36 MiB -1 -1 0.19 17948 1 0.05 -1 -1 31772 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77172 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.1 MiB 0.10 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.27 0.00093525 0.000867226 0.074379 0.0690457 -1 -1 -1 -1 82 3585 15 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.46 0.361492 0.333317 33448 250998 -1 3715 9 792 819 214644 81314 4.57723 4.57723 -685.291 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.06 0.21 -1 -1 0.04 0.0295768 0.0280427 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.39 vpr 74.76 MiB -1 -1 0.19 17960 1 0.05 -1 -1 32068 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 76556 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.1 MiB 0.10 3253 1906 39109 13750 20961 4398 74.8 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000971322 0.000902249 0.0754843 0.0701709 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.12 0.359108 0.331481 33448 250998 -1 3424 10 688 706 802479 802479 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.21 0.21 -1 -1 0.04 0.0308245 0.0291405 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 5.39 vpr 75.00 MiB -1 -1 0.20 17960 1 0.05 -1 -1 32092 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 76796 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.12 3253 1906 39109 13750 20961 4398 75.0 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000968255 0.000899263 0.0760549 0.070686 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.88 0.358969 0.330993 33448 250998 -1 3424 10 688 706 796806 796806 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.43 0.21 -1 -1 0.04 0.0319008 0.0301886 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.39 vpr 74.01 MiB -1 -1 0.19 17564 1 0.05 -1 -1 31772 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 75788 130 40 596 562 1 356 185 14 14 196 dsp_top auto 34.9 MiB 0.11 3253 1906 39109 13750 20961 4398 74.0 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.24 0.00096838 0.000899881 0.0767282 0.0713559 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.13 0.361612 0.33375 33448 250998 -1 3424 10 688 706 789226 323167 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.18 0.21 -1 -1 0.04 0.0309043 0.029241 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt index a9d53562104..19447432645 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt @@ -28,5 +28,5 @@ script_params_common=-track_memory_usage --route_chan_width 100 --max_router_ite script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index 385635c2f12..0be72798bb2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 6.40 vpr 78.31 MiB -1 -1 1.74 32308 16 0.37 -1 -1 34716 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80192 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.9 MiB 1.66 9794 6883 28689 8164 16986 3539 78.3 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00181398 0.00159035 0.162885 0.143678 -1 -1 -1 -1 -1 10585 12 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.06 0.211804 0.186281 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 6.68 vpr 78.27 MiB -1 -1 1.75 32308 16 0.38 -1 -1 34724 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80152 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.2 MiB 1.66 9794 6883 28689 8164 16986 3539 78.3 MiB 0.40 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.0025167 0.00230357 0.197326 0.174372 -1 -1 -1 -1 -1 10620 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.20 0.253737 0.222606 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 10.02 vpr 78.31 MiB -1 -1 1.72 32320 16 0.38 -1 -1 34724 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80188 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.9 MiB 1.64 9794 6883 28689 8164 16986 3539 78.3 MiB 0.34 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00179584 0.0015676 0.161529 0.142039 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 4.69 0.209219 0.183788 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 10.89 vpr 78.57 MiB -1 -1 1.76 31720 16 0.37 -1 -1 34324 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80456 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.3 MiB 1.71 9794 6883 28689 8164 16986 3539 78.6 MiB 0.36 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00187306 0.00163416 0.165658 0.145989 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 5.43 0.216342 0.190382 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 9.29 vpr 78.70 MiB -1 -1 1.96 32320 16 0.40 -1 -1 34556 -1 -1 60 45 3 1 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80592 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.5 MiB 1.65 9794 6883 28689 8164 16986 3539 78.7 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00185537 0.00163023 0.165615 0.146041 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 3.65 0.215249 0.189458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 6.51 vpr 78.23 MiB -1 -1 1.74 32316 16 0.38 -1 -1 34724 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80104 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.9 MiB 1.74 9794 6883 28689 8164 16986 3539 78.2 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00180615 0.00158429 0.162884 0.143795 -1 -1 -1 -1 -1 10585 12 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.05 0.208714 0.183536 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 7.03 vpr 77.86 MiB -1 -1 1.73 32316 16 0.37 -1 -1 34728 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79728 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.6 MiB 1.89 9794 6883 28689 8164 16986 3539 77.9 MiB 0.44 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00273275 0.00231808 0.222874 0.195896 -1 -1 -1 -1 -1 10620 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.27 0.289534 0.251628 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 10.17 vpr 78.52 MiB -1 -1 1.76 32332 16 0.37 -1 -1 34728 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80400 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.3 MiB 1.70 9794 6883 28689 8164 16986 3539 78.5 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00182918 0.00160106 0.163945 0.144335 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 4.73 0.214342 0.188032 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 13.04 vpr 78.43 MiB -1 -1 1.72 31948 16 0.38 -1 -1 34428 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80312 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.3 MiB 1.72 9794 6883 28689 8164 16986 3539 78.4 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00182981 0.00160205 0.163671 0.144301 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 7.56 0.218898 0.192942 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 9.13 vpr 78.43 MiB -1 -1 1.78 32312 16 0.37 -1 -1 34724 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80316 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.3 MiB 1.69 9794 6883 28689 8164 16986 3539 78.4 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00182715 0.00160038 0.16255 0.143378 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 3.64 0.211401 0.186214 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt index 3a66d472e2d..1a19286d997 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt @@ -28,5 +28,5 @@ script_params_common=-starting_stage vpr -sdc_file tasks/regression_tests/vtr_re script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index dce7634e482..266c7161ad8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -2,5 +2,5 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd cl k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt index 8e1af6295c1..0494e386027 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt @@ -28,5 +28,5 @@ script_params_common = -track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index e6295ec48fe..6fffcd3b3ab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.84 vpr 66.93 MiB -1 -1 0.27 18116 3 0.11 -1 -1 32740 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68536 99 130 344 474 1 227 298 12 12 144 clb auto 27.2 MiB 0.11 1695 684 72933 23047 34243 15643 66.9 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.00056171 0.000523958 0.0439825 0.040974 -1 -1 -1 -1 38 1437 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.33 0.159159 0.145356 12522 62564 -1 1141 11 437 710 29360 10219 1.94502 1.94502 -130.926 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.018542 0.0172924 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 1.73 vpr 66.80 MiB -1 -1 0.22 18460 3 0.07 -1 -1 33108 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68400 99 130 344 474 1 227 298 12 12 144 clb auto 27.0 MiB 0.11 1695 684 72933 23047 34243 15643 66.8 MiB 0.15 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.000728205 0.000689323 0.0537866 0.0492926 -1 -1 -1 -1 38 1420 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.32 0.142488 0.127075 12522 62564 -1 1150 9 446 701 30426 10498 1.94502 1.94502 -131.108 -1.94502 -0.67939 -0.29768 406292. 2821.48 0.01 0.02 0.04 -1 -1 0.01 0.0139845 0.0127141 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.79 vpr 66.67 MiB -1 -1 0.21 18864 3 0.07 -1 -1 32736 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68272 99 130 344 474 1 227 298 12 12 144 clb auto 26.9 MiB 0.11 1695 684 72933 23047 34243 15643 66.7 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000564139 0.000525059 0.0443486 0.0412882 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.40 0.155724 0.142204 12522 62564 -1 1128 9 408 669 127433 127433 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.04 0.04 -1 -1 0.01 0.0168763 0.0158171 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.93 vpr 66.61 MiB -1 -1 0.22 18860 3 0.07 -1 -1 32736 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68208 99 130 344 474 1 227 298 12 12 144 clb auto 26.9 MiB 0.11 1695 684 72933 23047 34243 15643 66.6 MiB 0.14 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000575717 0.000533107 0.0463823 0.0432761 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.48 0.159837 0.146027 12522 62564 -1 1128 9 408 669 124672 124672 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.07 0.04 -1 -1 0.01 0.0167421 0.0156627 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 2.03 vpr 66.94 MiB -1 -1 0.22 18476 3 0.07 -1 -1 33096 -1 -1 68 99 1 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 68544 99 130 344 474 1 227 298 12 12 144 clb auto 27.6 MiB 0.11 1695 684 72933 23047 34243 15643 66.9 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.11 0.00057061 0.000532262 0.0451549 0.042097 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.58 0.198386 0.181634 12522 62564 -1 1128 9 408 669 125594 43231 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.05 0.04 -1 -1 0.01 0.016725 0.0156512 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.73 vpr 66.23 MiB -1 -1 0.21 18848 3 0.07 -1 -1 33068 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67824 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000568632 0.000529819 0.0441667 0.0411462 -1 -1 -1 -1 38 1437 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.33 0.158129 0.144291 12522 62564 -1 1141 11 437 710 29360 10219 1.94502 1.94502 -130.926 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0184928 0.0172512 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 1.71 vpr 66.23 MiB -1 -1 0.22 18852 3 0.07 -1 -1 32740 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67816 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000612619 0.000577396 0.0464401 0.0430253 -1 -1 -1 -1 38 1420 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.30 0.130527 0.117061 12522 62564 -1 1150 9 446 701 30426 10498 1.94502 1.94502 -131.108 -1.94502 -0.67939 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0159542 0.0144078 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.84 vpr 66.23 MiB -1 -1 0.22 18176 3 0.07 -1 -1 33108 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67820 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000564449 0.000527167 0.0443768 0.0414183 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.38 0.152118 0.139015 12522 62564 -1 1128 9 408 669 127450 127450 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.04 0.04 -1 -1 0.01 0.0159569 0.0149713 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.94 vpr 66.23 MiB -1 -1 0.22 18868 3 0.07 -1 -1 33116 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67824 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000582283 0.000543802 0.0455405 0.0424991 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.47 0.157265 0.143773 12522 62564 -1 1128 9 408 669 125250 125250 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.09 0.04 -1 -1 0.01 0.0167922 0.015747 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.89 vpr 66.23 MiB -1 -1 0.22 18848 3 0.07 -1 -1 33096 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67820 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.14 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000581227 0.000543053 0.0461546 0.0430967 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.44 0.161183 0.147677 12522 62564 -1 1128 9 408 669 126593 45250 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.07 0.04 -1 -1 0.01 0.0170636 0.0159891 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt index 68cc1e4a51d..0b366a2736d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt @@ -32,8 +32,8 @@ script_params_list_add = --timing_update_type incremental --quench_recompute_div script_params_list_add = --timing_update_type incremental --router_algorithm parallel --num_workers 4 # rarely exercised code path script_params_list_add = --timing_update_type full --router_algorithm parallel --num_workers 4 script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 4 --multi_queue_num_queues 16 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt index 8cd97555576..77ef7d0e8b9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt @@ -1,13 +1,13 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.13 vpr 64.25 MiB -1 -1 0.41 23444 5 0.11 -1 -1 32264 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65796 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.02 198 153 432 69 336 27 64.3 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000226854 0.000206508 0.00419594 0.00386458 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.0138664 0.0124915 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.21 vpr 64.64 MiB -1 -1 0.47 23444 5 0.11 -1 -1 32816 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66192 10 2 181 183 1 35 24 6 6 36 clb auto 25.7 MiB 0.02 198 153 432 69 336 27 64.6 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000225754 0.000204889 0.00418926 0.0038596 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.0139128 0.0125426 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.14 vpr 64.00 MiB -1 -1 0.41 23444 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65540 10 2 181 183 1 35 24 6 6 36 clb auto 25.0 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 6.276e-06 2.373e-06 0.00173917 0.00155594 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.00773399 0.0057366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.15 vpr 64.67 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66224 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.02 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000115076 2.5133e-05 0.00166669 0.00142568 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.00749984 0.00567704 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.14 vpr 64.68 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66228 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.03 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 5.327e-06 1.22e-06 0.00176541 0.00146867 -1 -1 -1 -1 -1 142 18 646728 646728 138825. 3856.24 0.01 0.00817779 0.00569878 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 1.15 vpr 64.64 MiB -1 -1 0.42 23460 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66196 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.03 198 153 432 69 336 27 64.6 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000402289 0.000380879 0.00640867 0.00586659 -1 -1 -1 -1 -1 142 18 646728 646728 138825. 3856.24 0.02 0.0190248 0.0169558 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.18 vpr 64.67 MiB -1 -1 0.45 23464 5 0.11 -1 -1 32824 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66220 10 2 181 183 1 35 24 6 6 36 clb auto 25.6 MiB 0.02 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.939e-06 1.304e-06 0.002185 0.00196709 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.00872826 0.00675842 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.19 vpr 64.66 MiB -1 -1 0.42 23460 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66216 10 2 181 183 1 35 24 6 6 36 clb auto 25.6 MiB 0.02 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.081e-06 1.044e-06 0.0015854 0.00142828 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.05 0.00824227 0.00621395 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.15 vpr 64.67 MiB -1 -1 0.41 23464 5 0.11 -1 -1 32816 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66220 10 2 181 183 1 35 24 6 6 36 clb auto 25.3 MiB 0.02 198 153 432 69 336 27 64.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.271e-06 1.168e-06 0.00157844 0.00142246 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.00783423 0.00592468 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.15 vpr 64.64 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32816 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66196 10 2 181 183 1 35 24 6 6 36 clb auto 25.6 MiB 0.02 198 153 432 69 336 27 64.6 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000225699 0.000205384 0.0041722 0.00384118 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.0146306 0.0131119 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_4_--multi_queue_num_queues_16_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.17 vpr 64.15 MiB -1 -1 0.41 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65688 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 64.1 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.00024202 0.000220962 0.00489645 0.0045329 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.06 0.0155069 0.0139264 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.20 vpr 64.65 MiB -1 -1 0.41 23464 5 0.12 -1 -1 32820 -1 -1 12 10 0 0 success cdda01bb5 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-04-25T09:43:13 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 66200 10 2 181 183 1 35 24 6 6 36 clb auto 25.6 MiB 0.02 198 153 432 69 336 27 64.6 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000234309 0.000213247 0.00431784 0.00397848 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.06 0.0150147 0.0134424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.18 vpr 63.79 MiB -1 -1 0.41 23448 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65324 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.04 198 153 432 69 336 27 63.8 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000235029 0.000214051 0.00424678 0.00391288 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.0155905 0.0141088 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.20 vpr 63.94 MiB -1 -1 0.50 23444 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65472 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 63.9 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000230258 0.000209554 0.0042499 0.00390533 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.0141455 0.0127342 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.11 vpr 63.97 MiB -1 -1 0.42 23452 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65504 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.01e-06 1.071e-06 0.00158168 0.00142451 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.00723412 0.00548559 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.13 vpr 63.97 MiB -1 -1 0.41 23448 5 0.11 -1 -1 32628 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65504 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000115071 2.5318e-05 0.00166514 0.00142585 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.00729191 0.00547656 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.11 vpr 63.98 MiB -1 -1 0.42 23452 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65512 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 9.591e-06 1.027e-06 0.00173563 0.0014501 -1 -1 -1 -1 -1 142 18 646728 646728 138825. 3856.24 0.01 0.00799653 0.00565668 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 1.16 vpr 63.95 MiB -1 -1 0.42 23452 5 0.12 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65484 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 63.9 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.00043462 0.000402413 0.00710114 0.00653478 -1 -1 -1 -1 -1 142 18 646728 646728 138825. 3856.24 0.02 0.0217234 0.019335 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.16 vpr 63.97 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65504 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.083e-06 1.137e-06 0.00158114 0.00142356 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.00778711 0.00588202 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.20 vpr 63.88 MiB -1 -1 0.42 23468 5 0.11 -1 -1 32824 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65412 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 63.9 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.78e-06 1.407e-06 0.0017981 0.00159724 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.07 0.00815512 0.00618452 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.18 vpr 63.99 MiB -1 -1 0.42 23468 5 0.11 -1 -1 32824 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65528 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.165e-06 1.08e-06 0.00160201 0.00144669 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.05 0.00798852 0.00607253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.15 vpr 63.94 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65472 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 63.9 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000221105 0.000200581 0.00411028 0.00377693 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.0144868 0.0129751 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.20 vpr 63.53 MiB -1 -1 0.41 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65056 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 63.5 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000225457 0.000205137 0.00415833 0.0038325 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.07 0.0147425 0.0132082 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.17 vpr 63.71 MiB -1 -1 0.42 23452 5 0.11 -1 -1 32816 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65240 10 2 181 183 1 35 24 6 6 36 clb auto 24.3 MiB 0.03 198 153 432 69 336 27 63.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000227544 0.000206409 0.00424772 0.00391181 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.05 0.0147416 0.0132112 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From e275a82d12c333c5306c5584f562fb38ad47fd02 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 2 May 2025 11:33:49 -0400 Subject: [PATCH 081/176] [vpr][CLI] add generate_net_timing_report --- vpr/src/base/read_options.cpp | 5 +++++ vpr/src/base/read_options.h | 1 + 2 files changed, 6 insertions(+) diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 41d1af33800..00d926dd154 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -3010,6 +3010,11 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio analysis_grp.add_argument(args.write_timing_summary, "--write_timing_summary") .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); + + analysis_grp.add_argument(args.generate_net_timing_report, "--generate_net_timing_report") + .help("Generates a net timing report for each net in the design.") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); auto& power_grp = parser.add_argument_group("power analysis options"); diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 13c0d93f3fe..e7c4b3a0dfc 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -267,6 +267,7 @@ struct t_options { argparse::ArgValue post_synth_netlist_unconn_output_handling; argparse::ArgValue post_synth_netlist_module_parameters; argparse::ArgValue write_timing_summary; + argparse::ArgValue generate_net_timing_report; }; argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_options& args); From 97d41b8bf14f6585ebf00100626d60e185c94893 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Fri, 2 May 2025 14:23:52 -0700 Subject: [PATCH 082/176] [vpr][route] remove debugging msg --- vpr/src/route/router_delay_profiling.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index 68fb441a369..509593373ae 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -101,9 +101,6 @@ bool RouterDelayProfiler::calculate_delay(RRNodeId source_node, -1, false, std::unordered_map()); - if (size_t(sink_node) == 778060 && size_t(source_node) == 14) { - router_.set_router_debug(true); - } std::tie(found_path, std::ignore, cheapest) = router_.timing_driven_route_connection_from_route_tree( tree.root(), sink_node, From 333de67ba946a02d2643fd86f3ecb45c4df8c11c Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 2 May 2025 18:27:04 -0400 Subject: [PATCH 083/176] [vpr][analysis] add generate_net_timing_report --- vpr/src/analysis/timing_reports.h | 6 ++++++ vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/read_options.cpp | 2 +- vpr/src/base/vpr_api.cpp | 5 +++++ vpr/src/base/vpr_types.h | 1 + 5 files changed, 14 insertions(+), 1 deletion(-) diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index 72e1013dece..6b094809d65 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -21,4 +21,10 @@ void generate_hold_timing_stats(const std::string& prefix, bool is_flat, const BlkLocRegistry& blk_loc_registry); +void generate_net_timing_report(const std::string& prefix, + const SetupHoldTimingInfo& timing_info, + const AnalysisDelayCalculator& delay_calc, + const t_analysis_opts& analysis_opts, + const BlkLocRegistry& blk_loc_registry); + #endif diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index f911039c184..417b7bbf65b 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -715,6 +715,7 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.timing_update_type = Options.timing_update_type; analysis_opts.write_timing_summary = Options.write_timing_summary; + analysis_opts.generate_net_timing_report = Options.generate_net_timing_report; } static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch) { diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 00d926dd154..6e6578ce388 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -3011,7 +3011,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); - analysis_grp.add_argument(args.generate_net_timing_report, "--generate_net_timing_report") + analysis_grp.add_argument(args.generate_net_timing_report, "--generate_net_timing_report") .help("Generates a net timing report for each net in the design.") .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 2c84a6a7681..fe1d8437c18 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1476,6 +1476,11 @@ void vpr_analysis(const Netlist<>& net_list, merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, Arch.models, vpr_setup.AnalysisOpts); } + if (vpr_setup.AnalysisOpts.generate_net_timing_report) { + generate_net_timing_report(/*prefix=*/"", *timing_info, *analysis_delay_calc, + vpr_setup.AnalysisOpts, blk_loc_registry); + } + //Do power analysis // TODO: Still assumes that cluster net list is used if (vpr_setup.PowerOpts.do_power) { diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 106070c4c97..4330f8c0e68 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1285,6 +1285,7 @@ struct t_analysis_opts { bool timing_report_skew; std::string echo_dot_timing_graph_node; std::string write_timing_summary; + bool generate_net_timing_report; e_timing_update_type timing_update_type; }; From bc515a9f12af79e84e8ed82cd4b5bd0900a5b768 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 5 May 2025 08:59:55 -0400 Subject: [PATCH 084/176] [vpr][pack] apply formatting comments --- vpr/src/pack/prepack.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 243b0b69a67..465704392c3 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -1201,12 +1201,14 @@ static std::unordered_set get_pattern_blocks(const t_pack_patterns& std::unordered_set visited_to_pins; std::queue pack_pattern_blocks; pack_pattern_blocks.push(connections->from_block); + /** Start from the root block of the pack pattern and add the connected block to the queue */ while (!pack_pattern_blocks.empty()) { t_pack_pattern_block* current_pattern_block = pack_pattern_blocks.front(); pack_pattern_blocks.pop(); t_pack_pattern_connections* current_connenction = current_pattern_block->connections; - /** Iterate through all the connections of the current pattern block to + /* + * Iterate through all the connections of the current pattern block to * add the connected block to the queue */ while (current_connenction != nullptr) { @@ -1222,6 +1224,7 @@ static std::unordered_set get_pattern_blocks(const t_pack_patterns& */ visited_from_pins.insert(current_connenction->from_pin); visited_to_pins.insert(current_connenction->to_pin); + /** The from_pin block belongs to the pattern block */ pattern_blocks.insert(current_connenction->from_pin->port->parent_pb_type); pack_pattern_blocks.push(current_connenction->to_block); From 2c8b2c51f780aa6d2dd0a8b440ea9817378650e1 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 5 May 2025 09:59:12 -0400 Subject: [PATCH 085/176] make format --- vpr/src/pack/prepack.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 74d61fccce9..1f9f1a717bc 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -1219,13 +1219,14 @@ static std::unordered_set get_pattern_blocks(const t_pack_patterns& continue; } } - /** To avoid visiting the same connection twice, since it is both stored in from_pin and to_pin, + /* + * To avoid visiting the same connection twice, since it is both stored in from_pin and to_pin, * add the from_pin and to_pin to the visited sets */ visited_from_pins.insert(current_connenction->from_pin); visited_to_pins.insert(current_connenction->to_pin); - - /** The from_pin block belongs to the pattern block */ + + /* The from_pin block belongs to the pattern block */ pattern_blocks.insert(current_connenction->from_pin->port->parent_pb_type); pack_pattern_blocks.push(current_connenction->to_block); current_connenction = current_connenction->next; From 8aebd6a1e7497050abc0848fb22659efe93d12f6 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 5 May 2025 14:08:33 -0400 Subject: [PATCH 086/176] [vpr][analysis] add comments --- vpr/src/analysis/timing_reports.cpp | 58 +++++++++++++++++++++++++++++ vpr/src/analysis/timing_reports.h | 11 ++++-- vpr/src/base/vpr_api.cpp | 3 +- 3 files changed, 67 insertions(+), 5 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 281a40b67a0..fae53e90e23 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -1,3 +1,6 @@ +#include +#include + #include "timing_reports.h" #include "tatum/TimingReporter.hpp" @@ -61,3 +64,58 @@ void generate_hold_timing_stats(const std::string& prefix, timing_reporter.report_unconstrained_hold(prefix + "report_unconstrained_timing.hold.rpt", *timing_info.hold_analyzer()); } + +void generate_net_timing_report(const std::string& prefix, + const SetupHoldTimingInfo& timing_info, + const AnalysisDelayCalculator& delay_calc) { + /* Create a report file for net timing information */ + std::ofstream os(prefix + "report_net_timing.rpt"); + const auto& atom_netlist = g_vpr_ctx.atom().netlist(); + const auto& atom_lookup = g_vpr_ctx.atom().lookup(); + + const auto& timing_ctx = g_vpr_ctx.timing(); + const auto& timing_graph = timing_ctx.graph; + + for (const auto& net : atom_netlist.nets()) { + /* Skip constant nets */ + if (atom_netlist.net_is_constant(net)) { + continue; + } + + const auto& net_name = atom_netlist.net_name(net); + + /* Get source pin and its timing information */ + const auto& source_pin = *atom_netlist.net_pins(net).begin(); + auto source_pin_slack = timing_info.setup_pin_slack(source_pin); + /* Timing graph node id corresponding to the net's source pin */ + auto tg_source_node = atom_lookup.atom_pin_tnode(source_pin); + VTR_ASSERT(tg_source_node.is_valid()); + + const size_t fanout = atom_netlist.net_sinks(net).size(); + os << net_name << " : " << fanout << " : " << atom_netlist.pin_name(source_pin).c_str() << " " << source_pin_slack << " : "; + + /* Iterate over all fanout pins and print their timing information */ + for (size_t net_pin_index = 1; net_pin_index <= fanout; ++net_pin_index) { + const auto& pin = *(atom_netlist.net_pins(net).begin() + net_pin_index); + + /* Get timing graph node id corresponding to the fanout pin */ + const auto& tg_sink_node = atom_lookup.atom_pin_tnode(pin); + VTR_ASSERT(tg_sink_node.is_valid()); + + /* Get timing graph edge id between atom pins */ + const auto& tg_edge_id = timing_graph->find_edge(tg_source_node, tg_sink_node); + VTR_ASSERT(tg_edge_id.is_valid()); + + /* Get timing information for the fanout pin */ + const auto& pin_setup_slack = timing_info.setup_pin_slack(pin); + const auto& pin_delay = delay_calc.max_edge_delay(*timing_graph, tg_edge_id); + + const auto& pin_name = atom_netlist.pin_name(pin); + os << pin_name << " " << std::scientific << pin_setup_slack << " " << pin_delay; + if (net_pin_index < fanout) { + os << " : "; + } + } + os << "," << std::endl; + } +} diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index 6b094809d65..a9735d83911 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -21,10 +21,15 @@ void generate_hold_timing_stats(const std::string& prefix, bool is_flat, const BlkLocRegistry& blk_loc_registry); +/** + * @brief Generates timing information for each net in atom netlist + * + * @param prefix The prefix for the report file to be added to filename: report_net_timing.rpt + * @param timing_info Updated timing information + * @param delay_calc Delay calculator + */ void generate_net_timing_report(const std::string& prefix, const SetupHoldTimingInfo& timing_info, - const AnalysisDelayCalculator& delay_calc, - const t_analysis_opts& analysis_opts, - const BlkLocRegistry& blk_loc_registry); + const AnalysisDelayCalculator& delay_calc); #endif diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index fe1d8437c18..310a3798b11 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1477,8 +1477,7 @@ void vpr_analysis(const Netlist<>& net_list, } if (vpr_setup.AnalysisOpts.generate_net_timing_report) { - generate_net_timing_report(/*prefix=*/"", *timing_info, *analysis_delay_calc, - vpr_setup.AnalysisOpts, blk_loc_registry); + generate_net_timing_report(/*prefix=*/"", *timing_info, *analysis_delay_calc); } //Do power analysis From 010144e9fc9d0e4f57f4453271eedec4d1e77bb2 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 5 May 2025 14:09:09 -0400 Subject: [PATCH 087/176] make format --- vpr/src/analysis/timing_reports.cpp | 2 +- vpr/src/base/read_options.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index fae53e90e23..77e06a560e6 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -90,7 +90,7 @@ void generate_net_timing_report(const std::string& prefix, /* Timing graph node id corresponding to the net's source pin */ auto tg_source_node = atom_lookup.atom_pin_tnode(source_pin); VTR_ASSERT(tg_source_node.is_valid()); - + const size_t fanout = atom_netlist.net_sinks(net).size(); os << net_name << " : " << fanout << " : " << atom_netlist.pin_name(source_pin).c_str() << " " << source_pin_slack << " : "; diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 6e6578ce388..6afb0d3b425 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -3010,7 +3010,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio analysis_grp.add_argument(args.write_timing_summary, "--write_timing_summary") .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); - + analysis_grp.add_argument(args.generate_net_timing_report, "--generate_net_timing_report") .help("Generates a net timing report for each net in the design.") .default_value("off") From b8289db3ed811a9b831dbb036b91929e6b2737fc Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 5 May 2025 14:45:19 -0400 Subject: [PATCH 088/176] [vpr][CLI] remove generate net timing from CLI parameters and generate the report by default --- vpr/src/base/SetupVPR.cpp | 1 - vpr/src/base/read_options.cpp | 5 ----- vpr/src/base/read_options.h | 1 - vpr/src/base/vpr_api.cpp | 5 +---- vpr/src/base/vpr_types.h | 1 - 5 files changed, 1 insertion(+), 12 deletions(-) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 417b7bbf65b..f911039c184 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -715,7 +715,6 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.timing_update_type = Options.timing_update_type; analysis_opts.write_timing_summary = Options.write_timing_summary; - analysis_opts.generate_net_timing_report = Options.generate_net_timing_report; } static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch) { diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 6afb0d3b425..41d1af33800 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -3011,11 +3011,6 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); - analysis_grp.add_argument(args.generate_net_timing_report, "--generate_net_timing_report") - .help("Generates a net timing report for each net in the design.") - .default_value("off") - .show_in(argparse::ShowIn::HELP_ONLY); - auto& power_grp = parser.add_argument_group("power analysis options"); power_grp.add_argument(args.do_power, "--power") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index e7c4b3a0dfc..13c0d93f3fe 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -267,7 +267,6 @@ struct t_options { argparse::ArgValue post_synth_netlist_unconn_output_handling; argparse::ArgValue post_synth_netlist_module_parameters; argparse::ArgValue write_timing_summary; - argparse::ArgValue generate_net_timing_report; }; argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_options& args); diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 310a3798b11..6aa0acffbe2 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1464,6 +1464,7 @@ void vpr_analysis(const Netlist<>& net_list, vpr_setup.AnalysisOpts, vpr_setup.RouterOpts.flat_routing, blk_loc_registry); generate_setup_timing_stats(/*prefix=*/"", *timing_info, *analysis_delay_calc, vpr_setup.AnalysisOpts, vpr_setup.RouterOpts.flat_routing, blk_loc_registry); + generate_net_timing_report(/*prefix=*/"", *timing_info, *analysis_delay_calc); //Write the post-synthesis netlist if (vpr_setup.AnalysisOpts.gen_post_synthesis_netlist) { @@ -1476,10 +1477,6 @@ void vpr_analysis(const Netlist<>& net_list, merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, Arch.models, vpr_setup.AnalysisOpts); } - if (vpr_setup.AnalysisOpts.generate_net_timing_report) { - generate_net_timing_report(/*prefix=*/"", *timing_info, *analysis_delay_calc); - } - //Do power analysis // TODO: Still assumes that cluster net list is used if (vpr_setup.PowerOpts.do_power) { diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 4330f8c0e68..106070c4c97 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1285,7 +1285,6 @@ struct t_analysis_opts { bool timing_report_skew; std::string echo_dot_timing_graph_node; std::string write_timing_summary; - bool generate_net_timing_report; e_timing_update_type timing_update_type; }; From 8fdbe938b16e6f4a43a7fa8c2b484e31a52a45bb Mon Sep 17 00:00:00 2001 From: James Yen <90464912+yenjames@users.noreply.github.com> Date: Mon, 5 May 2025 17:46:48 -0700 Subject: [PATCH 089/176] Unused Packer Options Cleanup (#2976) * Standardized and renamed packer alpha and beta variable. They are now referred to as timing_gain_weight and connection_gain_weight, used as a weight parameter during timing and connection driven clustering respectively. Removed global_clocks, use_attraction_groups, pack_num_moves, pack_move_type from packer. --- doc/src/vpr/command_line_usage.rst | 4 +- vpr/src/base/SetupVPR.cpp | 10 +--- vpr/src/base/ShowSetup.cpp | 5 +- vpr/src/base/read_options.cpp | 22 +------ vpr/src/base/read_options.h | 7 +-- vpr/src/base/vpr_api.cpp | 3 +- vpr/src/base/vpr_types.h | 69 +++++++++++++++++++--- vpr/src/pack/cluster_util.cpp | 1 - vpr/src/pack/greedy_candidate_selector.cpp | 16 ++--- vpr/src/pack/output_clustering.cpp | 20 +++---- vpr/src/pack/output_clustering.h | 4 +- 11 files changed, 88 insertions(+), 73 deletions(-) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 77eb679ca6f..7a87605e6d2 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -569,7 +569,7 @@ For people not working on CAD, you can probably leave all the options to their d **Default**: ``auto`` -.. option:: --alpha_clustering +.. option:: --timing_gain_weight A parameter that weights the optimization of timing vs area. @@ -577,7 +577,7 @@ For people not working on CAD, you can probably leave all the options to their d **Default**: ``0.75`` -.. option:: --beta_clustering +.. option:: --connection_gain_weight A tradeoff parameter that controls the optimization of smaller net absorption vs. the optimization of signal sharing. diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index f911039c184..b40dd89f18d 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -570,15 +570,12 @@ void SetupPackerOpts(const t_options& Options, PackerOpts->doPacking = STAGE_DO; } - //TODO: document? - PackerOpts->global_clocks = true; /* DEFAULT */ - PackerOpts->allow_unrelated_clustering = Options.allow_unrelated_clustering; PackerOpts->connection_driven = Options.connection_driven_clustering; PackerOpts->timing_driven = Options.timing_driven_clustering; PackerOpts->cluster_seed_type = Options.cluster_seed_type; - PackerOpts->alpha = Options.alpha_clustering; - PackerOpts->beta = Options.beta_clustering; + PackerOpts->timing_gain_weight = Options.timing_gain_weight; + PackerOpts->connection_gain_weight = Options.connection_gain_weight; PackerOpts->pack_verbosity = Options.pack_verbosity; PackerOpts->enable_pin_feasibility_filter = Options.enable_clustering_pin_feasibility_filter; PackerOpts->balance_block_type_utilization = Options.balance_block_type_utilization; @@ -588,13 +585,10 @@ void SetupPackerOpts(const t_options& Options, PackerOpts->high_fanout_threshold = Options.pack_high_fanout_threshold; PackerOpts->transitive_fanout_threshold = Options.pack_transitive_fanout_threshold; PackerOpts->feasible_block_array_size = Options.pack_feasible_block_array_size; - PackerOpts->use_attraction_groups = Options.use_attraction_groups; PackerOpts->device_layout = Options.device_layout; PackerOpts->timing_update_type = Options.timing_update_type; - PackerOpts->pack_num_moves = Options.pack_num_moves; - PackerOpts->pack_move_type = Options.pack_move_type; } static void SetupNetlistOpts(const t_options& Options, t_netlist_opts& NetlistOpts) { diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index fba46d4818c..bdabc71e789 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -732,8 +732,8 @@ static void ShowPackerOpts(const t_packer_opts& PackerOpts) { } else { VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown packer allow_unrelated_clustering\n"); } - VTR_LOG("PackerOpts.alpha_clustering: %f\n", PackerOpts.alpha); - VTR_LOG("PackerOpts.beta_clustering: %f\n", PackerOpts.beta); + VTR_LOG("PackerOpts.timing_gain_weight: %f\n", PackerOpts.timing_gain_weight); + VTR_LOG("PackerOpts.connection_gain_weight: %f\n", PackerOpts.connection_gain_weight); VTR_LOG("PackerOpts.cluster_seed_type: "); switch (PackerOpts.cluster_seed_type) { case e_cluster_seed::TIMING: @@ -758,7 +758,6 @@ static void ShowPackerOpts(const t_packer_opts& PackerOpts) { VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown packer cluster_seed_type\n"); } VTR_LOG("PackerOpts.connection_driven: %s", (PackerOpts.connection_driven ? "true\n" : "false\n")); - VTR_LOG("PackerOpts.global_clocks: %s", (PackerOpts.global_clocks ? "true\n" : "false\n")); VTR_LOG("PackerOpts.timing_driven: %s", (PackerOpts.timing_driven ? "true\n" : "false\n")); VTR_LOG("PackerOpts.target_external_pin_util: %s", vtr::join(PackerOpts.target_external_pin_util, " ").c_str()); VTR_LOG("\n"); diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 41d1af33800..6c741c12f6e 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1972,14 +1972,14 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("auto") .show_in(argparse::ShowIn::HELP_ONLY); - pack_grp.add_argument(args.alpha_clustering, "--alpha_clustering") + pack_grp.add_argument(args.timing_gain_weight, "--timing_gain_weight") .help( "Parameter that weights the optimization of timing vs area. 0.0 focuses solely on" " area, 1.0 solely on timing.") .default_value("0.75") .show_in(argparse::ShowIn::HELP_ONLY); - pack_grp.add_argument(args.beta_clustering, "--beta_clustering") + pack_grp.add_argument(args.connection_gain_weight, "--connection_gain_weight") .help( "Parameter that weights the absorption of small nets vs signal sharing." " 0.0 focuses solely on sharing, 1.0 solely on small net absoprtion." @@ -2101,24 +2101,6 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("2") .show_in(argparse::ShowIn::HELP_ONLY); - pack_grp.add_argument(args.use_attraction_groups, "--use_attraction_groups") - .help("Whether attraction groups are used to make it easier to pack primitives in the same floorplan region together.") - .default_value("on") - .show_in(argparse::ShowIn::HELP_ONLY); - - pack_grp.add_argument(args.pack_num_moves, "--pack_num_moves") - .help( - "The number of moves that can be tried in packing stage") - .default_value("100000") - .show_in(argparse::ShowIn::HELP_ONLY); - - pack_grp.add_argument(args.pack_move_type, "--pack_move_type") - .help( - "The move type used in packing." - "The available values are: randomSwap, semiDirectedSwap, semiDirectedSameTypeSwap") - .default_value("semiDirectedSwap") - .show_in(argparse::ShowIn::HELP_ONLY); - auto& place_grp = parser.add_argument_group("placement options"); place_grp.add_argument(args.Seed, "--seed") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 13c0d93f3fe..fc5e4889ad3 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -108,8 +108,8 @@ struct t_options { /* Clustering options */ argparse::ArgValue connection_driven_clustering; argparse::ArgValue allow_unrelated_clustering; - argparse::ArgValue alpha_clustering; - argparse::ArgValue beta_clustering; + argparse::ArgValue timing_gain_weight; + argparse::ArgValue connection_gain_weight; argparse::ArgValue timing_driven_clustering; argparse::ArgValue cluster_seed_type; argparse::ArgValue enable_clustering_pin_feasibility_filter; @@ -120,9 +120,6 @@ struct t_options { argparse::ArgValue pack_feasible_block_array_size; argparse::ArgValue> pack_high_fanout_threshold; argparse::ArgValue pack_verbosity; - argparse::ArgValue use_attraction_groups; - argparse::ArgValue pack_num_moves; - argparse::ArgValue pack_move_type; /* Placement options */ argparse::ArgValue Seed; argparse::ArgValue ShowPlaceTiming; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 2c84a6a7681..0d83e5fc17d 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1400,8 +1400,7 @@ bool vpr_analysis_flow(const Netlist<>& net_list, } std::string post_routing_packing_output_file_name = vpr_setup.PackerOpts.output_file + ".post_routing"; - write_packing_results_to_xml(vpr_setup.PackerOpts.global_clocks, - Arch.architecture_id, + write_packing_results_to_xml(Arch.architecture_id, post_routing_packing_output_file_name.c_str()); } else { VTR_LOG_WARN("Synchronization between packing and routing results is not applied due to illegal circuit implementation\n"); diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 106070c4c97..07257e398ba 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -705,17 +705,75 @@ enum e_stage_action { /** * @brief Options for packing * - * TODO: document each packing parameter + * @param circuit_file_name + * Path to technology mapped user circuit in BLIF format. + * @param output_file + * Path to packed user circuit in net format. + * @param timing_driven + * Whether or not to do timing driven clustering. (Default: on) + * @param timing_gain_weight + * Controls the optimization of timing vs area in timing driven + * clustering. + * A value of 0 focuses only on area; 1 focuses only on timing. + * (Default: 0.75) + * @param connection_gain_weight + * Controls the optimization of smaller net absorption vs. signal + * sharing in connection driven clustering. + * A value of 0 focuses solely on signal sharing; a value of 1 + * focuses solely on absorbing smaller nets into a cluster. + * (Default: 0.9) + * @param cluster_seed_type + * Selection algorithm for selecting next seed. (Default: blend2 if + * timing_driven is on; max_inputs otherwise) + * @param target_device_utilization + * Sets the target device utilization. (Default: 1.0) + * @param allow_unrelated_clustering + * Allows primitives which have no attraction to the given cluster + * to be packed into it. (Default: auto) + * @param connection_driven + * Controls whether or not packing prioritizes the absorption of nets + * with fewer connections into a complex logic block over nets with + * more connections. (Default: on) + * @param pack_verbosity + * Controls how verbose clustering's output is. (Default: 2) + * @param enable_pin_feasibility_filter + * Counts the number of available pins in groups/classes of mutually + * connected pins within a cluster, then filters out candidate + * primitives/atoms/molecules for which the cluster has insufficient + * pins to route (without performing a full routing). (Default: on) + * @param balance_block_type_utilization + * If enabled, when a primitive can potentially be mapped to multiple + * block types the packer will pick the block type which (currently) + * has the lowest utilization. (Default: auto) + * @param target_external_pin_util + * Sets the external pin utilization target. (Default: auto) + * @param prioritize_transitive_connectivity + * Whether transitive connectivity is prioritized over high-fanout + * connectivity. (Default: on) + * @param feasible_block_array_size + * Max size of the priority queue for candidates that pass the early + * filter legality test, but not the more detailed routing test. + * (Default: 30) + * @param doPacking + * Run packing stage. + * @param device_layout + * Controls which device layout/floorplan is used from the + * architecture file. (Default: smallest device which satisfies the + * circuit's resource requirements) + * @param timing_update_type + * Controls how timing analysis updates are performed. (Default: auto) + * @param load_flat_placement + * Whether to reconstruct a packing solution from a flat placement + * file. (Default: off; on if is on) */ struct t_packer_opts { std::string circuit_file_name; std::string sdc_file_name; std::string output_file; - bool global_clocks; bool timing_driven; enum e_cluster_seed cluster_seed_type; - float alpha; - float beta; + float timing_gain_weight; + float connection_gain_weight; float target_device_utilization; e_unrelated_clustering allow_unrelated_clustering; bool connection_driven; @@ -730,9 +788,6 @@ struct t_packer_opts { e_stage_action doPacking; std::string device_layout; e_timing_update_type timing_update_type; - bool use_attraction_groups; - int pack_num_moves; - std::string pack_move_type; bool load_flat_placement = false; }; diff --git a/vpr/src/pack/cluster_util.cpp b/vpr/src/pack/cluster_util.cpp index e3361971b3d..1ed359ca0c1 100644 --- a/vpr/src/pack/cluster_util.cpp +++ b/vpr/src/pack/cluster_util.cpp @@ -77,7 +77,6 @@ void check_and_output_clustering(ClusterLegalizer& cluster_legalizer, } output_clustering(&cluster_legalizer, - packer_opts.global_clocks, is_clock, arch->architecture_id, packer_opts.output_file.c_str(), diff --git a/vpr/src/pack/greedy_candidate_selector.cpp b/vpr/src/pack/greedy_candidate_selector.cpp index 10255890d67..199894b8d23 100644 --- a/vpr/src/pack/greedy_candidate_selector.cpp +++ b/vpr/src/pack/greedy_candidate_selector.cpp @@ -299,7 +299,7 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( AtomNetId net_id = atom_netlist_.pin_net(pin_id); e_gain_update gain_flag = e_gain_update::NO_GAIN; - if (!is_clock_.count(net_id) || !packer_opts_.global_clocks) + if (!is_clock_.count(net_id)) gain_flag = e_gain_update::GAIN; mark_and_update_partial_gain(cluster_gain_stats, @@ -327,13 +327,9 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( for (AtomPinId pin_id : atom_netlist_.block_clock_pins(blk_id)) { AtomNetId net_id = atom_netlist_.pin_net(pin_id); - e_gain_update gain_flag = e_gain_update::GAIN; - if (packer_opts_.global_clocks) - gain_flag = e_gain_update::NO_GAIN; - mark_and_update_partial_gain(cluster_gain_stats, net_id, - gain_flag, + e_gain_update::NO_GAIN, blk_id, cluster_legalizer, high_fanout_net_threshold, @@ -623,9 +619,9 @@ void GreedyCandidateSelector::update_total_gain(ClusterGainStats& cluster_gain_s VTR_ASSERT(num_used_pins > 0); if (packer_opts_.connection_driven) { /*try to absorb as many connections as possible*/ - cluster_gain_stats.gain[blk_id] = ((1 - packer_opts_.beta) + cluster_gain_stats.gain[blk_id] = ((1 - packer_opts_.connection_gain_weight) * (float)cluster_gain_stats.sharing_gain[blk_id] - + packer_opts_.beta * (float)cluster_gain_stats.connection_gain[blk_id]) + + packer_opts_.connection_gain_weight * (float)cluster_gain_stats.connection_gain[blk_id]) / (num_used_pins); } else { cluster_gain_stats.gain[blk_id] = ((float)cluster_gain_stats.sharing_gain[blk_id]) @@ -634,9 +630,9 @@ void GreedyCandidateSelector::update_total_gain(ClusterGainStats& cluster_gain_s /* Add in timing driven cost into cost function */ if (packer_opts_.timing_driven) { - cluster_gain_stats.gain[blk_id] = packer_opts_.alpha + cluster_gain_stats.gain[blk_id] = packer_opts_.timing_gain_weight * cluster_gain_stats.timing_gain[blk_id] - + (1.0 - packer_opts_.alpha) * (float)cluster_gain_stats.gain[blk_id]; + + (1.0 - packer_opts_.timing_gain_weight) * (float)cluster_gain_stats.gain[blk_id]; } } } diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp index 28582294ce4..9cdc27ac399 100644 --- a/vpr/src/pack/output_clustering.cpp +++ b/vpr/src/pack/output_clustering.cpp @@ -640,7 +640,7 @@ static void clustering_xml_blocks_from_netlist(pugi::xml_node& block_node, /* This routine dumps out the output netlist in a format suitable for * * input to vpr. This routine also dumps out the internal structure of * * the cluster, in essentially a graph based format. */ -void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_clocks, const std::unordered_set& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering, bool from_legalizer) { +void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, const std::unordered_set& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering, bool from_legalizer) { const DeviceContext& device_ctx = g_vpr_ctx.device(); const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); @@ -689,17 +689,15 @@ void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_cloc block_node.append_child("inputs").text().set(vtr::join(inputs.begin(), inputs.end(), " ").c_str()); block_node.append_child("outputs").text().set(vtr::join(outputs.begin(), outputs.end(), " ").c_str()); - if (global_clocks) { - std::vector clocks; - for (auto net_id : atom_nlist.nets()) { - if (is_clock.count(net_id)) { - clocks.push_back(atom_nlist.net_name(net_id)); - } + std::vector clocks; + for (auto net_id : atom_nlist.nets()) { + if (is_clock.count(net_id)) { + clocks.push_back(atom_nlist.net_name(net_id)); } - - block_node.append_child("clocks").text().set(vtr::join(clocks.begin(), clocks.end(), " ").c_str()); } + block_node.append_child("clocks").text().set(vtr::join(clocks.begin(), clocks.end(), " ").c_str()); + if (skip_clustering == false) { if (from_legalizer) { VTR_ASSERT(cluster_legalizer_ptr != nullptr); @@ -724,15 +722,13 @@ void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_cloc * As such, this function is expected to be a standard API * which can be called anytime and anywhere after packing is finished. ********************************************************************/ -void write_packing_results_to_xml(const bool& global_clocks, - const std::string& architecture_id, +void write_packing_results_to_xml(const std::string& architecture_id, const char* out_fname) { std::unordered_set is_clock = alloc_and_load_is_clock(); // Since the cluster legalizer is not being used to output the clustering // (from_legalizer is false), passing in nullptr. output_clustering(nullptr, - global_clocks, is_clock, architecture_id, out_fname, diff --git a/vpr/src/pack/output_clustering.h b/vpr/src/pack/output_clustering.h index 92d734248d1..c7537ee8c39 100644 --- a/vpr/src/pack/output_clustering.h +++ b/vpr/src/pack/output_clustering.h @@ -17,15 +17,13 @@ class ClusterLegalizer; /// clustered netlist. If from_legalizer is false, the clustered netlist currently /// in the global scope will be used. void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, - bool global_clocks, const std::unordered_set& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering, bool from_legalizer); -void write_packing_results_to_xml(const bool& global_clocks, - const std::string& architecture_id, +void write_packing_results_to_xml(const std::string& architecture_id, const char* out_fname); #endif From 4079c04dc5cd542ea3306b0577ea9940a51394e1 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Sat, 3 May 2025 21:27:23 -0400 Subject: [PATCH 090/176] [APPack] Updated Max Candidate Distance Interface The max candidate distance is used by APPack to decide which molecules to ignore when packing, based on their distance from the cluster being formed. Cleaned up the interface of this by pre-computing the max candidate distance of all logical blocks ahead of time and reading from these pre-computed values during packing. Added a command-line option to allow the user to override some or all of these max distance thresholds. By default, VPR will select values based on the type of logical block and the primitives it contains. Fixed issue with APPack creating too many IO blocks for some circuits due to the max candidate distance thresholds for IO blocks being too low. More tuning should be done on these values once the mass legalizer has been cleaned up a bit more. --- doc/src/vpr/command_line_usage.rst | 43 ++++ vpr/src/analytical_place/full_legalizer.cpp | 1 + vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/read_options.cpp | 25 ++ vpr/src/base/read_options.h | 1 + vpr/src/base/vpr_api.cpp | 2 +- vpr/src/base/vpr_types.h | 5 + vpr/src/pack/appack_context.h | 63 ++--- vpr/src/pack/appack_max_dist_th_manager.cpp | 271 ++++++++++++++++++++ vpr/src/pack/appack_max_dist_th_manager.h | 118 +++++++++ vpr/src/pack/greedy_candidate_selector.cpp | 6 +- vpr/src/pack/pack.cpp | 6 +- vpr/src/pack/pack.h | 2 + 13 files changed, 496 insertions(+), 48 deletions(-) create mode 100644 vpr/src/pack/appack_max_dist_th_manager.cpp create mode 100644 vpr/src/pack/appack_max_dist_th_manager.h diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 7a87605e6d2..d064b586231 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1270,6 +1270,49 @@ Analytical Placement is generally split into three stages: **Default:** ``0.5`` +.. option:: --appack_max_dist_th { auto | :, } + + Sets the maximum candidate distance thresholds for the logical block types + used by APPack. APPack uses the primitive-level placement produced by the + global placer to cluster primitives together. APPack uses the thresholds + here to ignore primitives which are too far away from the cluster being formed. + + When this option is set to "auto", VPR will select good values for these + thresholds based on the primitives contained within each logical block type. + + Using this option, the user can set the maximum candidate distance threshold + of logical block types to something else. The strings passed in by the user + should be of the form ``:,`` where the regex string is + used to match the name of the logical block type to set, the first float + is a scaling term, and the second float is an offset. The threshold will + be set to max(scale * (W + H), offset), where W and H are the width and height + of the device. This allows the user to specify a threshold based on the + size of the device, while also preventing the number from going below "offset". + When multiple strings are provided, the thresholds are set from left to right, + and any logical block types which have been unset will be set to their "auto" + values. + + For example: + + .. code-block:: none + + --appack_max_dist_th .*:0.1,0 "clb|memory:0,5" + + Would set all logical block types to be 0.1 * (W + H), except for the clb and + memory block, which will be set to a fixed value of 5. + + Another example: + + .. code-block:: none + + --appack_max_dist_th "clb|LAB:0.2,5" + + This will set all of the logical block types to their "auto" thresholds, except + for logical blocks with the name clb/LAB which will be set to 0.2 * (W + H) or + 5 (whichever is larger). + + **Default:** ``auto`` + .. option:: --ap_verbosity Controls the verbosity of the AP flow output. diff --git a/vpr/src/analytical_place/full_legalizer.cpp b/vpr/src/analytical_place/full_legalizer.cpp index 7b7cc9cfb39..369ef53510c 100644 --- a/vpr/src/analytical_place/full_legalizer.cpp +++ b/vpr/src/analytical_place/full_legalizer.cpp @@ -520,6 +520,7 @@ void APPack::legalize(const PartialPlacement& p_placement) { // Run the Packer stage with the flat placement as a hint. try_pack(vpr_setup_.PackerOpts, vpr_setup_.AnalysisOpts, + vpr_setup_.APOpts, arch_, vpr_setup_.PackerRRGraph, prepacker_, diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index b40dd89f18d..807650cd7ec 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -550,6 +550,7 @@ void SetupAPOpts(const t_options& options, apOpts.full_legalizer_type = options.ap_full_legalizer.value(); apOpts.detailed_placer_type = options.ap_detailed_placer.value(); apOpts.ap_timing_tradeoff = options.ap_timing_tradeoff.value(); + apOpts.appack_max_dist_th = options.appack_max_dist_th.value(); apOpts.log_verbosity = options.ap_verbosity.value(); } diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 6c741c12f6e..f94a04b7225 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1945,6 +1945,31 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("0.5") .show_in(argparse::ShowIn::HELP_ONLY); + ap_grp.add_argument(args.appack_max_dist_th, "--appack_max_dist_th") + .help( + "Sets the maximum candidate distance thresholds for the logical block types" + "used by APPack. APPack uses the primitive-level placement produced by the" + "global placer to cluster primitives together. APPack uses the thresholds" + "here to ignore primitives which are too far away from the cluster being formed." + "\n" + "When this option is set to auto, VPR will select good values for these" + "thresholds based on the primitives contained within each logical block type." + "\n" + "Using this option, the user can set the maximum candidate distance threshold" + "of logical block types to something else. The strings passed in by the user" + "should be of the form :, where the regex string is" + "used to match the name of the logical block type to set, the first float" + "is a scaling term, and the second float is an offset. The threshold will" + "be set to max(scale * (W + H), offset), where W and H are the width and height" + "of the device. This allows the user to specify a threshold based on the" + "size of the device, while also preventing the number from going below offset" + "When multiple strings are provided, the thresholds are set from left to right," + "and any logical block types which have been unset will be set to their auto" + "values.") + .nargs('+') + .default_value({"auto"}) + .show_in(argparse::ShowIn::HELP_ONLY); + ap_grp.add_argument(args.ap_verbosity, "--ap_verbosity") .help( "Controls how verbose the AP flow's log messages will be. Higher " diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index fc5e4889ad3..3697667015e 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -102,6 +102,7 @@ struct t_options { argparse::ArgValue ap_partial_legalizer; argparse::ArgValue ap_full_legalizer; argparse::ArgValue ap_detailed_placer; + argparse::ArgValue> appack_max_dist_th; argparse::ArgValue ap_verbosity; argparse::ArgValue ap_timing_tradeoff; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 0d83e5fc17d..97f8f164635 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -658,7 +658,7 @@ bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch) { vpr_setup.PackerOpts.device_layout, vpr_setup.AnalysisOpts); - return try_pack(vpr_setup.PackerOpts, vpr_setup.AnalysisOpts, + return try_pack(vpr_setup.PackerOpts, vpr_setup.AnalysisOpts, vpr_setup.APOpts, arch, vpr_setup.PackerRRGraph, prepacker, diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 07257e398ba..94a97bc9e61 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1113,6 +1113,9 @@ struct t_placer_opts { * @param ap_timing_tradeoff * A trade-off parameter used to decide how focused the AP flow * should be on optimizing timing over wirelength. + * @param appack_max_dist_th + * Array of string passed by the user to configure the max candidate + * distance thresholds. * @param log_verbosity * The verbosity level of log messages in the AP flow, with higher * values leading to more verbose messages. @@ -1130,6 +1133,8 @@ struct t_ap_opts { float ap_timing_tradeoff; + std::vector appack_max_dist_th; + int log_verbosity; }; diff --git a/vpr/src/pack/appack_context.h b/vpr/src/pack/appack_context.h index 0461f26b320..4235fb1fd95 100644 --- a/vpr/src/pack/appack_context.h +++ b/vpr/src/pack/appack_context.h @@ -8,12 +8,12 @@ #pragma once -#include -#include +#include "appack_max_dist_th_manager.h" #include "device_grid.h" #include "flat_placement_types.h" #include "physical_types.h" #include "vpr_context.h" +#include "vpr_types.h" #include "vpr_utils.h" /** @@ -25,29 +25,10 @@ */ struct t_appack_options { // Constructor for the appack options. - t_appack_options(const FlatPlacementInfo& flat_placement_info, - const DeviceGrid& device_grid) { + t_appack_options(const FlatPlacementInfo& flat_placement_info) { // If the flat placement info is valid, we want to use APPack. // TODO: Should probably check that all the information is valid here. use_appack = flat_placement_info.valid; - - // Set the max candidate distance as being some fraction of the longest - // distance on the device (from the bottom corner to the top corner). - // We also use an offset for the minimum this distance can be to prevent - // small devices from finding candidates. - float max_candidate_distance_scale = 0.1f; - float max_candidate_distance_offset = 15.0f; - // Longest L1 distance on the device. - float longest_distance = device_grid.width() + device_grid.height(); - max_candidate_distance = std::max(max_candidate_distance_scale * longest_distance, - max_candidate_distance_offset); - - // Infer the logical block type in the architecture. This will be used - // for the max candidate distance optimization to use a more aggressive - // distance. - t_logical_block_type_ptr logic_block_type = infer_logic_block_type(device_grid); - if (logic_block_type != nullptr) - logic_block_type_index = logic_block_type->index; } // Whether to use APPack or not. @@ -88,22 +69,6 @@ struct t_appack_options { // Squared scaling factor for the quadratic decay term. static constexpr float quad_fac_sqr = (1.0f - attenuation_th) / (dist_th * dist_th); - // =========== Candidate selection distance ============================ // - // When selecting candidates, what distance from the cluster will we - // consider? Any candidate beyond this distance will not be proposed. - // This is set in the constructor. - // TODO: It may be a good idea to have max different distances for different - // types of molecules / clusters. For example, CLBs vs DSPs - float max_candidate_distance = std::numeric_limits::max(); - - // A scaling applied to the max candidate distance of all clusters that are - // not logic blocks. - static constexpr float max_candidate_distance_non_lb_scale = 3.5f; - - // TODO: This should be an option similar to the target pin utilization - // so we can specify the max distance per block type! - int logic_block_type_index = -1; - // =========== Unrelated clustering ==================================== // // After searching for candidates by connectivity and timing, the user may // turn on unrelated clustering, which will allow molecules which are @@ -144,9 +109,21 @@ struct APPackContext : public Context { /** * @brief Constructor for the APPack context. */ - APPackContext(const FlatPlacementInfo& fplace_info, const DeviceGrid& device_grid) - : appack_options(fplace_info, device_grid) - , flat_placement_info(fplace_info) {} + APPackContext(const FlatPlacementInfo& fplace_info, + const t_ap_opts& ap_opts, + const std::vector logical_block_types, + const DeviceGrid& device_grid) + : appack_options(fplace_info) + , flat_placement_info(fplace_info) { + + // If the flat placement info has been provided, calculate max distance + // thresholds for all logical block types. + if (fplace_info.valid) { + max_distance_threshold_manager.init(ap_opts.appack_max_dist_th, + logical_block_types, + device_grid); + } + } /** * @brief Options used to configure APPack. @@ -157,4 +134,8 @@ struct APPackContext : public Context { * @brief The flat placement information passed into APPack. */ const FlatPlacementInfo& flat_placement_info; + + // When selecting candidates, what distance from the cluster will we + // consider? Any candidate beyond this distance will not be proposed. + APPackMaxDistThManager max_distance_threshold_manager; }; diff --git a/vpr/src/pack/appack_max_dist_th_manager.cpp b/vpr/src/pack/appack_max_dist_th_manager.cpp new file mode 100644 index 00000000000..9f9a39815a7 --- /dev/null +++ b/vpr/src/pack/appack_max_dist_th_manager.cpp @@ -0,0 +1,271 @@ +/** + * @file + * @author Alex Singer + * @date May 2025 + * @breif Definition of the max distance threshold manager class. + */ + +#include "appack_max_dist_th_manager.h" +#include +#include +#include +#include +#include "device_grid.h" +#include "physical_types.h" +#include "physical_types_util.h" +#include "vpr_error.h" +#include "vpr_utils.h" +#include "vtr_assert.h" +#include "vtr_log.h" + +/** + * @brief Helper method to convert a string into a float with error checking. + */ +static float str_to_float_or_error(const std::string& str); + +/** + * @brief Helper method to parse one term of the user-provided max distance + * threshold string. + * + * This method decomposes the user string of the form ":," + * into its three components. + */ +static std::tuple parse_max_dist_th(const std::string& max_dist_th); + +/** + * @brief Recursive helper method to deduce if the given pb_type is or contains + * pb_types which are of the memory class. + * + * TODO: This should be a graph traversal instead of a recursive function. + */ +static bool has_memory_pbs(const t_pb_type* pb_type); + +void APPackMaxDistThManager::init(const std::vector& max_dist_ths, + const std::vector& logical_block_types, + const DeviceGrid& device_grid) { + // Automatically set the max distance thresholds. + auto_set_max_distance_thresholds(logical_block_types, device_grid); + + // If the max distance threshold strings have been set (they are not set to + // auto), set the max distance thresholds based on the user-provided strings. + VTR_ASSERT(!max_dist_ths.empty()); + if (max_dist_ths.size() != 1 || max_dist_ths[0] != "auto") { + set_max_distance_thresholds_from_strings(max_dist_ths, logical_block_types, device_grid); + } + + // Set the initilized flag to true. + is_initialized_ = true; + + // Log the max distance thresholds for each logical block type. This is + // similar to how the input and output pin utilizations are printed. + VTR_LOG("APPack is using max distance thresholds: "); + for (const t_logical_block_type& lb_ty : logical_block_types) { + if (lb_ty.is_empty()) + continue; + VTR_LOG("%s:%g ", + lb_ty.name.c_str(), + get_max_dist_threshold(lb_ty)); + } + VTR_LOG("\n"); +} + +void APPackMaxDistThManager::auto_set_max_distance_thresholds(const std::vector& logical_block_types, + const DeviceGrid& device_grid) { + // Compute the max device distance based on the width and height of the + // device. This is the L1 (manhattan) distance. + float max_device_distance = device_grid.width() + device_grid.height(); + + // Compute the max distance thresholds of the different logical block types. + float default_max_distance_th = std::max(default_max_dist_th_scale_ * max_device_distance, + default_max_dist_th_offset_); + float logic_block_max_distance_th = std::max(logic_block_max_dist_th_scale_ * max_device_distance, + logic_block_max_dist_th_offset_); + float memory_max_distance_th = std::max(memory_max_dist_th_scale_ * max_device_distance, + memory_max_dist_th_offset_); + float io_block_max_distance_th = std::max(io_max_dist_th_scale_ * max_device_distance, + io_max_dist_th_offset_); + + // Set all logical block types to have the default max distance threshold. + logical_block_dist_thresholds_.resize(logical_block_types.size(), default_max_distance_th); + + // Find which (if any) of the logical block types most looks like a CLB block. + t_logical_block_type_ptr logic_block_type = infer_logic_block_type(device_grid); + + // Go through each of the logical block types. + for (const t_logical_block_type& lb_ty : logical_block_types) { + // Skip the empty logical block type. This should not have any blocks. + if (lb_ty.is_empty()) + continue; + + // Find which type(s) this logical block type looks like. + bool has_memory = has_memory_pbs(lb_ty.pb_type); + bool is_logic_block_type = (lb_ty.index == logic_block_type->index); + bool is_io_block = is_io_type(pick_physical_type(&lb_ty)); + + // Update the max distance threshold based on the type. If the logical + // block type looks like many block types at the same time (for example + // a CLB which has memory slices within it), then take the average + // of the max distance thresholds of those types. + float max_distance_th_sum = 0.0f; + unsigned block_category_count = 0; + if (is_logic_block_type) { + max_distance_th_sum += logic_block_max_distance_th; + block_category_count++; + } + if (has_memory) { + max_distance_th_sum += memory_max_distance_th; + block_category_count++; + } + if (is_io_block) { + max_distance_th_sum += io_block_max_distance_th; + block_category_count++; + } + if (block_category_count > 0) { + logical_block_dist_thresholds_[lb_ty.index] = max_distance_th_sum / static_cast(block_category_count); + } + } +} + +static bool has_memory_pbs(const t_pb_type* pb_type) { + if (pb_type == nullptr) + return false; + + // Check if this pb_type is a memory class. If so return true. This acts as + // a base case for the recursion. + if (pb_type->class_type == e_pb_type_class::MEMORY_CLASS) + return true; + + // Go through all modes of this pb_type and check if any of those modes' + // children have memory pb_types, if so return true. + for (int mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) { + const t_mode& mode = pb_type->modes[mode_idx]; + for (int child_idx = 0; child_idx < mode.num_pb_type_children; child_idx++) { + if (has_memory_pbs(&mode.pb_type_children[child_idx])) + return true; + } + } + + // If this pb_type is not a memory and its modes do not have memory pbs in + // them, then this pb_type is not a memory. + return false; +} + +void APPackMaxDistThManager::set_max_distance_thresholds_from_strings( + const std::vector& max_dist_ths, + const std::vector& logical_block_types, + const DeviceGrid& device_grid) { + + // Go through each of the user-provided strings. + for (const std::string& max_dist_th : max_dist_ths) { + // If any of them are the word "auto", this was a user error and should + // be flagged. + // TODO: Maybe move this and other semantic checks up to the checker of + // VPR's command line. + if (max_dist_th == "auto") { + VPR_FATAL_ERROR(VPR_ERROR_PACK, + "APPack: Cannot provide both auto and other max distance threshold strings"); + } + + // Parse the string for the regex, scale, and offset. + std::string logical_block_regex_str; + float logical_block_max_dist_th_scale; + float logical_block_max_dist_th_offset; + std::tie(logical_block_regex_str, + logical_block_max_dist_th_scale, + logical_block_max_dist_th_offset) = parse_max_dist_th(max_dist_th); + + // Setup the regex for the logical blocks the user wants to set the + // thresholds for. + std::regex logical_block_regex(logical_block_regex_str); + + // Compute the max distance threshold the user selected. + float max_device_distance = device_grid.width() + device_grid.height(); + float logical_block_max_dist_th = std::max(max_device_distance * logical_block_max_dist_th_scale, + logical_block_max_dist_th_offset); + + // Search through all logical blocks and set the thresholds of any matches + // to the threshold the user selected. + bool found_match = false; + for (const t_logical_block_type& lb_ty : logical_block_types) { + bool is_match = std::regex_match(lb_ty.name, logical_block_regex); + if (!is_match) + continue; + + logical_block_dist_thresholds_[lb_ty.index] = logical_block_max_dist_th; + found_match = true; + } + // If no match is found, send a warning to the user. + if (!found_match) { + VTR_LOG_WARN("Unable to find logical block type for max distance threshold regex string: %s\n", + logical_block_regex_str.c_str()); + } + } +} + +static std::tuple parse_max_dist_th(const std::string& max_dist_th) { + // Verify the format of the string. It must have one and only one colon. + unsigned colon_count = 0; + for (char c : max_dist_th) { + if (c == ':') + colon_count++; + } + if (colon_count != 1) { + VTR_LOG_ERROR("Invalid max distance threshold string: %s\n", + max_dist_th.c_str()); + VPR_FATAL_ERROR(VPR_ERROR_PACK, + "Error when parsing APPack max distance threshold string"); + } + + // Split the string along the colon. + auto del_pos = max_dist_th.find(':'); + std::string logical_block_regex_str = max_dist_th.substr(0, del_pos); + std::string lb_max_dist_th_str = max_dist_th.substr(del_pos + 1, std::string::npos); + + // Split along the comma for the scale/offset. + // Verify that the comma only appears once in the scale/offset string. + unsigned comma_count = 0; + for (char c : lb_max_dist_th_str) { + if (c == ',') + comma_count++; + } + if (comma_count != 1) { + VTR_LOG_ERROR("Invalid max distance threshold string: %s\n", + max_dist_th.c_str()); + VPR_FATAL_ERROR(VPR_ERROR_PACK, + "Error when parsing APPack max distance threshold string"); + } + + // Split the string along the comma. + auto comma_pos = lb_max_dist_th_str.find(','); + std::string lb_max_dist_th_scale_str = lb_max_dist_th_str.substr(0, comma_pos); + std::string lb_max_dist_th_offset_str = lb_max_dist_th_str.substr(comma_pos + 1, std::string::npos); + + // Convert the scale and offset into floats (error checking to be safe). + float lb_max_dist_th_scale = str_to_float_or_error(lb_max_dist_th_scale_str); + float lb_max_dist_th_offset = str_to_float_or_error(lb_max_dist_th_offset_str); + + // Return the results as a tuple. + return std::make_tuple(logical_block_regex_str, lb_max_dist_th_scale, lb_max_dist_th_offset); +} + +static float str_to_float_or_error(const std::string& str) { + float val = -1; + try { + val = std::stof(str); + } catch (const std::invalid_argument& e) { + VTR_LOG_ERROR("Error while parsing max distance threshold value: %s\n" + "Failed with invalid argument: %s\n", + str.c_str(), + e.what()); + } catch (const std::out_of_range& e) { + VTR_LOG_ERROR("Error while parsing max distance threshold value: %s\n" + "Failed with out of range: %s\n", + str.c_str(), + e.what()); + } + if (val < 0.0f) { + VPR_FATAL_ERROR(VPR_ERROR_PACK, + "Error when parsing APPack max distance threshold string"); + } + return val; +} diff --git a/vpr/src/pack/appack_max_dist_th_manager.h b/vpr/src/pack/appack_max_dist_th_manager.h new file mode 100644 index 00000000000..558b224c56b --- /dev/null +++ b/vpr/src/pack/appack_max_dist_th_manager.h @@ -0,0 +1,118 @@ +/** + * @file + * @author Alex Singer + * @date May 2025 + * @brief Declaration of a class that manages the max candidate distance + * thresholding optimization used within APPack. + */ + +#pragma once + +#include +#include +#include "physical_types.h" +#include "vtr_assert.h" + +// Forward declarations. +class DeviceGrid; + +/** + * @brief Manager class which manages parsing and getting the max candidate + * distance thresholds for each of the logical block types in the + * architecture. + * + * The initializer of this class will set the max candidate distance thresholds + * based on the arguments passed by the user. + * + * Within the packer, the get_max_dist_threshold method can be used to get the + * max distance threshold for a given logical block type. + */ +class APPackMaxDistThManager { + // To compute the max distance threshold, we use two numbers to compute it: + // - Scale: This is what fraction of the device the distance should be. + // i.e. the max distance threshold will be scale * (W + H) since + // W+H is the farthes L1 distance possible on the device. + // - Offset: This is the minimum threshold it can have. This prevents small + // devices with small scales having thresholds that are too small. + // The following scales and offsets are set for interesting logical blocks + // when the "auto" selection mode is used. The following numbers were + // empirically found to work well. + + // This is the default scale and offset. Logical blocks that we do not + // recognize as being of the special categories will have this threshold. + static constexpr float default_max_dist_th_scale_ = 0.35f; + static constexpr float default_max_dist_th_offset_ = 15.0f; + + // Logic blocks (such as CLBs and LABs) tend to have more resources on the + // device, thus they have tighter thresholds. This was found to work well. + static constexpr float logic_block_max_dist_th_scale_ = 0.1f; + static constexpr float logic_block_max_dist_th_offset_ = 15.0f; + + // Memory blocks (i.e. blocks that contain pb_types of the memory class) + // seem to have very touchy packing; thus these do not have the max + // threshold to prevent them from creating too many clusters. + static constexpr float memory_max_dist_th_scale_ = 1.0f; + static constexpr float memory_max_dist_th_offset_ = 0.0f; + + // IO blocks tend to have very sparse resources and setting the offset too + // low can create too many blocks. Set this to a higher value. + static constexpr float io_max_dist_th_scale_ = 0.5f; + static constexpr float io_max_dist_th_offset_ = 15.0f; + + public: + APPackMaxDistThManager() = default; + + /** + * @brief Initializer for the manager class. The thresholds for each logical + * block type is selected here. + * + * @param should_initialize + * Whether to compute the thresholds for each logical block or not. This + * is to allow the class to be passed around without AP being enabled. + * @param max_dist_ths + * An array of strings representing the user-defined max distance + * thresholds. This is passed from the command line. + * @param logical_block_types + * An array of all logical block types in the architecture. + * @param device_grid + */ + void init(const std::vector& max_dist_ths, + const std::vector& logical_block_types, + const DeviceGrid& device_grid); + + /** + * @brief Get the max distance threshold of the given lobical block type. + */ + inline float get_max_dist_threshold(const t_logical_block_type& logical_block_ty) const { + VTR_ASSERT_SAFE_MSG(is_initialized_, + "APPackMaxDistThManager has not been initialized, cannot call this method"); + VTR_ASSERT_SAFE_MSG((size_t)logical_block_ty.index < logical_block_dist_thresholds_.size(), + "Logical block type does not have a max distance threshold"); + + return logical_block_dist_thresholds_[logical_block_ty.index]; + } + + private: + /** + * @brief Helper method that initializes the thresholds of all logical + * block types to reasonable numbers based on the characteristics + * of the logical block type. + */ + void auto_set_max_distance_thresholds(const std::vector& logical_block_types, + const DeviceGrid& device_grid); + + /** + * @brief Helper method that sets the thresholds based on the user-provided + * strings. + */ + void set_max_distance_thresholds_from_strings(const std::vector& max_dist_ths, + const std::vector& logical_block_types, + const DeviceGrid& device_grid); + + /// @brief A flag which shows if the thesholds have been computed or not. + bool is_initialized_ = false; + + /// @brief The max distance thresholds of all logical blocks in the architecture. + /// This is initialized in the constructor and accessed during packing. + std::vector logical_block_dist_thresholds_; +}; diff --git a/vpr/src/pack/greedy_candidate_selector.cpp b/vpr/src/pack/greedy_candidate_selector.cpp index 199894b8d23..d4579a45554 100644 --- a/vpr/src/pack/greedy_candidate_selector.cpp +++ b/vpr/src/pack/greedy_candidate_selector.cpp @@ -960,11 +960,7 @@ static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, // distance. Was found to create too many RAM blocks. if (!cluster_gain_stats.is_memory) { // Get the max dist for this block type. - float max_dist = appack_ctx.appack_options.max_candidate_distance; - // If this cluster is anything but a logic block type, then scale - // up the max distance. - if (cluster_type->index != appack_ctx.appack_options.logic_block_type_index) - max_dist *= appack_ctx.appack_options.max_candidate_distance_non_lb_scale; + float max_dist = appack_ctx.max_distance_threshold_manager.get_max_dist_threshold(*cluster_type); // If the distance from the cluster to the candidate is too large, // do not add this molecule to the list of candidates. diff --git a/vpr/src/pack/pack.cpp b/vpr/src/pack/pack.cpp index 85a21c229e6..57ee96a1a7f 100644 --- a/vpr/src/pack/pack.cpp +++ b/vpr/src/pack/pack.cpp @@ -29,6 +29,7 @@ static bool try_size_device_grid(const t_arch& arch, bool try_pack(const t_packer_opts& packer_opts, const t_analysis_opts& analysis_opts, + const t_ap_opts& ap_opts, const t_arch& arch, std::vector* lb_type_rr_graphs, const Prepacker& prepacker, @@ -126,7 +127,10 @@ bool try_pack(const t_packer_opts& packer_opts, VTR_LOG("Packing with high fanout thresholds: %s\n", high_fanout_thresholds.to_string().c_str()); // Construct the APPack Context. - APPackContext appack_ctx(flat_placement_info, device_ctx.grid); + APPackContext appack_ctx(flat_placement_info, + ap_opts, + device_ctx.logical_block_types, + device_ctx.grid); // Initialize the greedy clusterer. GreedyClusterer clusterer(packer_opts, diff --git a/vpr/src/pack/pack.h b/vpr/src/pack/pack.h index 64189ea4ee9..f484146ac66 100644 --- a/vpr/src/pack/pack.h +++ b/vpr/src/pack/pack.h @@ -9,6 +9,7 @@ class FlatPlacementInfo; class PreClusterTimingManager; class Prepacker; struct t_analysis_opts; +struct t_ap_opts; struct t_arch; struct t_lb_type_rr_node; struct t_packer_opts; @@ -37,6 +38,7 @@ struct t_packer_opts; */ bool try_pack(const t_packer_opts& packer_opts, const t_analysis_opts& analysis_opts, + const t_ap_opts& ap_opts, const t_arch& arch, std::vector* lb_type_rr_graphs, const Prepacker& prepacker, From f32bd59346f94736344379f951057670b4a4e9f7 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 6 May 2025 09:14:46 -0400 Subject: [PATCH 091/176] [vtr][parse] fix pattern for init place wl --- vtr_flow/parse/parse_config/common/vpr.place.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/parse/parse_config/common/vpr.place.txt b/vtr_flow/parse/parse_config/common/vpr.place.txt index 865a7d2159a..a061a3f2869 100644 --- a/vtr_flow/parse/parse_config/common/vpr.place.txt +++ b/vtr_flow/parse/parse_config/common/vpr.place.txt @@ -1,5 +1,5 @@ #VPR Place Metrics -initial_placed_wirelength_est;vpr.out;Initial placement BB estimate of wirelength:\s*(\d+) +initial_placed_wirelength_est;vpr.out;Initial placement BB estimate of wirelength:\s*(.*) placed_wirelength_est;vpr.out;BB estimate of min-dist \(placement\) wire length: (\d+) #VPR Number of heap operations From 25bcd43586065528c7192f55a1381f5a9b7c0bb5 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 6 May 2025 11:43:38 -0400 Subject: [PATCH 092/176] [vpr][analysis] add header for net timing report --- vpr/src/analysis/timing_reports.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 77e06a560e6..29cfe2603a7 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -1,3 +1,5 @@ +#include "timing_reports.h" + #include #include @@ -5,6 +7,7 @@ #include "tatum/TimingReporter.hpp" +#include "vtr_version.h" #include "vpr_types.h" #include "globals.h" @@ -76,6 +79,15 @@ void generate_net_timing_report(const std::string& prefix, const auto& timing_ctx = g_vpr_ctx.timing(); const auto& timing_graph = timing_ctx.graph; + os << "# This file is generated by VTR" << std::endl; + os << "# Version: " << vtr::VERSION << std::endl; + os << "# Revision: " << vtr::VCS_REVISION << std::endl; + os << "# For each net, the timing information is reported in the following format:" << std::endl; + os << "# netname : Fanout : source_instance : " + << " : " + << " : ..." + << std::endl; + for (const auto& net : atom_netlist.nets()) { /* Skip constant nets */ if (atom_netlist.net_is_constant(net)) { From e7df9ea59e1cd43740d47df1fbe226a0d28f256c Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 6 May 2025 11:50:13 -0400 Subject: [PATCH 093/176] [vpr][analysis] add timing format to comments --- vpr/src/analysis/timing_reports.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index a9735d83911..e127335849b 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -22,7 +22,11 @@ void generate_hold_timing_stats(const std::string& prefix, const BlkLocRegistry& blk_loc_registry); /** - * @brief Generates timing information for each net in atom netlist + * @brief Generates timing information for each net in atom netlist. For each net, the timing information + * is reported in the following format: + * netname : Fanout : source_instance : + * : + * : ... * * @param prefix The prefix for the report file to be added to filename: report_net_timing.rpt * @param timing_info Updated timing information From 1d50ca126cb9f367f210266503461f7b89ea500a Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 6 May 2025 12:31:27 -0400 Subject: [PATCH 094/176] formatting fix --- vpr/src/analysis/timing_reports.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 29cfe2603a7..1467b9e28a4 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -87,6 +87,8 @@ void generate_net_timing_report(const std::string& prefix, << " : " << " : ..." << std::endl; + + os << std::endl; for (const auto& net : atom_netlist.nets()) { /* Skip constant nets */ From 310ecac66cb6a723324f0bf13c44a6505d271908 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 6 May 2025 12:32:04 -0400 Subject: [PATCH 095/176] Revert "[vpr][CLI] remove generate net timing from CLI parameters and generate the report by default" This reverts commit b8289db3ed811a9b831dbb036b91929e6b2737fc. --- vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/read_options.cpp | 5 +++++ vpr/src/base/read_options.h | 1 + vpr/src/base/vpr_api.cpp | 5 ++++- vpr/src/base/vpr_types.h | 1 + 5 files changed, 12 insertions(+), 1 deletion(-) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index f911039c184..417b7bbf65b 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -715,6 +715,7 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.timing_update_type = Options.timing_update_type; analysis_opts.write_timing_summary = Options.write_timing_summary; + analysis_opts.generate_net_timing_report = Options.generate_net_timing_report; } static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch) { diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 41d1af33800..6afb0d3b425 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -3011,6 +3011,11 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.generate_net_timing_report, "--generate_net_timing_report") + .help("Generates a net timing report for each net in the design.") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + auto& power_grp = parser.add_argument_group("power analysis options"); power_grp.add_argument(args.do_power, "--power") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 13c0d93f3fe..e7c4b3a0dfc 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -267,6 +267,7 @@ struct t_options { argparse::ArgValue post_synth_netlist_unconn_output_handling; argparse::ArgValue post_synth_netlist_module_parameters; argparse::ArgValue write_timing_summary; + argparse::ArgValue generate_net_timing_report; }; argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_options& args); diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 6aa0acffbe2..310a3798b11 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1464,7 +1464,6 @@ void vpr_analysis(const Netlist<>& net_list, vpr_setup.AnalysisOpts, vpr_setup.RouterOpts.flat_routing, blk_loc_registry); generate_setup_timing_stats(/*prefix=*/"", *timing_info, *analysis_delay_calc, vpr_setup.AnalysisOpts, vpr_setup.RouterOpts.flat_routing, blk_loc_registry); - generate_net_timing_report(/*prefix=*/"", *timing_info, *analysis_delay_calc); //Write the post-synthesis netlist if (vpr_setup.AnalysisOpts.gen_post_synthesis_netlist) { @@ -1477,6 +1476,10 @@ void vpr_analysis(const Netlist<>& net_list, merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, Arch.models, vpr_setup.AnalysisOpts); } + if (vpr_setup.AnalysisOpts.generate_net_timing_report) { + generate_net_timing_report(/*prefix=*/"", *timing_info, *analysis_delay_calc); + } + //Do power analysis // TODO: Still assumes that cluster net list is used if (vpr_setup.PowerOpts.do_power) { diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 106070c4c97..4330f8c0e68 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1285,6 +1285,7 @@ struct t_analysis_opts { bool timing_report_skew; std::string echo_dot_timing_graph_node; std::string write_timing_summary; + bool generate_net_timing_report; e_timing_update_type timing_update_type; }; From 2265ce89087cfe05bc4332f865b58ab025b6483c Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 6 May 2025 12:54:48 -0400 Subject: [PATCH 096/176] make format --- vpr/src/analysis/timing_reports.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 1467b9e28a4..0062aff5d81 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -83,11 +83,11 @@ void generate_net_timing_report(const std::string& prefix, os << "# Version: " << vtr::VERSION << std::endl; os << "# Revision: " << vtr::VCS_REVISION << std::endl; os << "# For each net, the timing information is reported in the following format:" << std::endl; - os << "# netname : Fanout : source_instance : " + os << "# netname : Fanout : source_instance : " << " : " - << " : ..." + << " : ..." << std::endl; - + os << std::endl; for (const auto& net : atom_netlist.nets()) { From 0b1a5777e1dad8a208369f469b83cc07af58fca7 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Wed, 30 Apr 2025 17:32:35 -0400 Subject: [PATCH 097/176] [STA] Generating SDC Commands Post-Implementation Added an option to have VPR generate an SDC file containing the timing commands required for an external timing analysis of the post- implementation netlist to match VPR's timing analysis. --- doc/src/vpr/command_line_usage.rst | 10 ++ vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/ShowSetup.cpp | 2 + vpr/src/base/netlist_writer.cpp | 160 ++++++++++++++++++++++++++++- vpr/src/base/netlist_writer.h | 20 +++- vpr/src/base/read_options.cpp | 10 ++ vpr/src/base/read_options.h | 1 + vpr/src/base/vpr_api.cpp | 2 +- vpr/src/base/vpr_types.h | 1 + 9 files changed, 203 insertions(+), 4 deletions(-) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 5a38fdc26bc..61dd775abb9 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1830,6 +1830,16 @@ Analysis Options **Default:** ``off`` +.. option:: --gen_post_implementation_sdc { on | off } + + Generates an SDC file including a list of constraints that would + replicate the timing constraints that the timing analysis within + VPR followed during the flow. This can be helpful for flows that + use external timing analysis tools that have additional capabilities + or more detailed delay models than what VPR uses. + + **Default:** ``off`` + .. option:: --post_synth_netlist_unconn_inputs { unconnected | nets | gnd | vcc } Controls how unconnected input cell ports are handled in the post-synthesis netlist diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 07a826598b4..dc692cdcd11 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -704,6 +704,7 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.gen_post_synthesis_netlist = Options.Generate_Post_Synthesis_Netlist; analysis_opts.gen_post_implementation_merged_netlist = Options.Generate_Post_Implementation_Merged_Netlist; + analysis_opts.gen_post_implementation_sdc = Options.generate_post_implementation_sdc.value(); analysis_opts.timing_report_npaths = Options.timing_report_npaths; analysis_opts.timing_report_detail = Options.timing_report_detail; diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index f35c3f93085..fa81fa9f1ac 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -677,6 +677,8 @@ static void ShowNetlistOpts(const t_netlist_opts& NetlistOpts) { static void ShowAnalysisOpts(const t_analysis_opts& AnalysisOpts) { VTR_LOG("AnalysisOpts.gen_post_synthesis_netlist: %s\n", (AnalysisOpts.gen_post_synthesis_netlist) ? "true" : "false"); + VTR_LOG("AnalysisOpts.gen_post_implementation_merged_netlist: %s\n", AnalysisOpts.gen_post_implementation_merged_netlist ? "true" : "false"); + VTR_LOG("AnalysisOpts.gen_post_implementation_sdc: %s\n", AnalysisOpts.gen_post_implementation_sdc ? "true" : "false"); VTR_LOG("AnalysisOpts.timing_report_npaths: %d\n", AnalysisOpts.timing_report_npaths); VTR_LOG("AnalysisOpts.timing_report_skew: %s\n", AnalysisOpts.timing_report_skew ? "true" : "false"); VTR_LOG("AnalysisOpts.echo_dot_timing_graph_node: %s\n", AnalysisOpts.echo_dot_timing_graph_node.c_str()); diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp index f12bfdedf3a..8a02b9a7be1 100644 --- a/vpr/src/base/netlist_writer.cpp +++ b/vpr/src/base/netlist_writer.cpp @@ -72,6 +72,7 @@ #include #include "atom_netlist.h" #include "atom_netlist_utils.h" +#include "clock_modeling.h" #include "globals.h" #include "logic_vec.h" #include "netlist_walker.h" @@ -2644,6 +2645,147 @@ std::string join_identifier(std::string lhs, std::string rhs) { return lhs + '_' + rhs; } +/** + * @brief Add the original SDC constraints that VPR used during its flow to the + * given SDC file. + * + * @param sdc_os + * Output stream for the target SDC file. The original SDC file passed into + * VPR will be appended to this file. + * @param timing_info + * Information on the timing within VPR. This is used to get the file path + * to the original SDC file. + */ +void add_original_sdc_to_post_implemented_sdc_file(std::ofstream& sdc_os, + const t_timing_inf& timing_info) { + // Open the original SDC file provided to VPR. + std::ifstream original_sdc_file; + original_sdc_file.open(timing_info.SDCFile); + if (!original_sdc_file.is_open()) { + // TODO: VPR automatically creates SDC constraints by default if no SDC + // file is provided. These can be replicated here if needed. + VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER, + "No SDC files provided to VPR; currently cannot generate " + "post-implementation SDC file without it"); + } + + // Write a header to declare where these commands came from. + sdc_os << "\n"; + sdc_os << "#******************************************************************************#\n"; + sdc_os << "# The following SDC commands were provided to VPR from the given SDC file:\n"; + sdc_os << "# \t" << timing_info.SDCFile << "\n"; + sdc_os << "#******************************************************************************#\n"; + + // Append the original SDC file to the post-implementation SDC file. + sdc_os << original_sdc_file.rdbuf(); +} + +/** + * @brief Add propagated clock commands to the given SDC file based on the set + * clock modeling. + * + * This is necessary since VPR decides if clocks are routed or not, which has + * affects on how timing analysis is performed on the clocks. + * + * @param sdc_os + * The file stream to add the propagated clock commands to. + * @param clock_modeling + * The type of clock modeling used by VPR during the CAD flow. + */ +void add_propagated_clocks_to_sdc_file(std::ofstream& sdc_os, + e_clock_modeling clock_modeling) { + + // Ideal and routed clocks are handled by the code below. Other clock models + // like dedicated routing are not supported yet. + // TODO: Supporting dedicated routing should be simple; however it should + // be investigated. Tried quickly but found that the delays produced + // were off by 0.003 ns. Need to investigate why. + if (clock_modeling != e_clock_modeling::ROUTED_CLOCK && clock_modeling != e_clock_modeling::IDEAL_CLOCK) { + VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER, + "Only ideal and routed clock modeling are currentlt " + "supported for post-implementation SDC file generation"); + } + + // The timing constraints contain information on all the clocks in the circuit + // (provided by the user-provided SDC file). + const auto timing_constraints = g_vpr_ctx.timing().constraints; + + // Collect the non-virtual clocks. Virtual clocks are not routed and + // do not get propageted. + std::vector non_virtual_clocks; + for (tatum::DomainId clock_domain_id : timing_constraints->clock_domains()) { + if (!timing_constraints->is_virtual_clock(clock_domain_id)) { + non_virtual_clocks.push_back(clock_domain_id); + } + } + + // If there are no non-virtual clocks, no extra commands needed. Virtual + // clocks are ideal. + if (non_virtual_clocks.empty()) { + return; + } + + // Append a header to explain why these commands are added. + sdc_os << "\n"; + sdc_os << "#******************************************************************************#\n"; + sdc_os << "# The following are clock domains in VPR which have delays on their edges.\n"; + sdc_os << "#\n"; + sdc_os << "# Any non-virtual clock has its delay determined and written out as part of a"; + sdc_os << "# propagated clock command. If VPR was instructed not to route the clock, this"; + sdc_os << "# delay will be an underestimate.\n"; + sdc_os << "#\n"; + sdc_os << "# Note: Virtual clocks do not get routed and are treated as ideal.\n"; + sdc_os << "#******************************************************************************#\n"; + + // Add the SDC commands to set the non-virtual clocks as propagated (non-ideal); + // Note: It was decided that "ideal" (dont route) clock modeling in VPR should still + // set the clocks as propagated to allow for the input pad delays of + // clocks to be included. The SDF delay annotations on clock signals + // should make this safe to do. + for (tatum::DomainId clock_domain_id : non_virtual_clocks) { + sdc_os << "set_propagated_clock "; + sdc_os << timing_constraints->clock_domain_name(clock_domain_id); + sdc_os << "\n"; + } +} + +/** + * @brief Generates a post-implementation SDC file with the given file name + * based on the timing info and clock modeling set for VPR. + * + * @param sdc_filename + * The file name of the SDC file to generate. + * @param timing_info + * Information on the timing used in the VPR flow. + * @param clock_modeling + * The type of clock modeling used by VPR during its flow. + */ +void generate_post_implementation_sdc(const std::string& sdc_filename, + const t_timing_inf& timing_info, + e_clock_modeling clock_modeling) { + if (!timing_info.timing_analysis_enabled) { + VTR_LOG_WARN("Timing analysis is disabled. Post-implementation SDC file " + "will not be generated.\n"); + return; + } + + // Begin writing the post-implementation SDC file. + std::ofstream sdc_os(sdc_filename); + + // Print a header declaring that this file is auto-generated and what version + // of VTR produced it. + sdc_os << "#******************************************************************************#\n"; + sdc_os << "# SDC automatically generated by VPR from a post-place-and-route implementation.\n"; + sdc_os << "#\tVersion: " << vtr::VERSION << "\n"; + sdc_os << "#******************************************************************************#\n"; + + // Add the original SDC that VPR used during its flow. + add_original_sdc_to_post_implemented_sdc_file(sdc_os, timing_info); + + // Add propagated clocks to SDC file if needed. + add_propagated_clocks_to_sdc_file(sdc_os, clock_modeling); +} + } // namespace // @@ -2651,7 +2793,12 @@ std::string join_identifier(std::string lhs, std::string rhs) { // ///@brief Main routine for this file. See netlist_writer.h for details. -void netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, t_analysis_opts opts) { +void netlist_writer(const std::string basename, + std::shared_ptr delay_calc, + const LogicalModels& models, + const t_timing_inf& timing_info, + e_clock_modeling clock_modeling, + t_analysis_opts opts) { std::string verilog_filename = basename + "_post_synthesis.v"; std::string blif_filename = basename + "_post_synthesis.blif"; std::string sdf_filename = basename + "_post_synthesis.sdf"; @@ -2659,7 +2806,6 @@ void netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, t_analysis_opts opts); +void netlist_writer(const std::string basename, + std::shared_ptr delay_calc, + const LogicalModels& models, + const t_timing_inf& timing_info, + e_clock_modeling clock_modeling, + t_analysis_opts opts); /** * @brief Writes out the post implementation netlist in Verilog format. diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 82de8cc0efa..d4b70892580 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -3012,6 +3012,16 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.generate_post_implementation_sdc, "--gen_post_implementation_sdc") + .help( + "Generates an SDC file including a list of constraints that would " + "replicate the timing constraints that the timing analysis within " + "VPR followed during the flow. This can be helpful for flows that " + "use external timing analysis tools that have additional capabilities " + "or more detailed delay models than what VPR uses") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.timing_report_npaths, "--timing_report_npaths") .help("Controls how many timing paths are reported.") .default_value("100") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 9056cdbf9fc..61051940b3a 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -263,6 +263,7 @@ struct t_options { argparse::ArgValue full_stats; argparse::ArgValue Generate_Post_Synthesis_Netlist; argparse::ArgValue Generate_Post_Implementation_Merged_Netlist; + argparse::ArgValue generate_post_implementation_sdc; argparse::ArgValue timing_report_npaths; argparse::ArgValue timing_report_detail; argparse::ArgValue timing_report_skew; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 97f8f164635..560b3e2d527 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1467,7 +1467,7 @@ void vpr_analysis(const Netlist<>& net_list, //Write the post-synthesis netlist if (vpr_setup.AnalysisOpts.gen_post_synthesis_netlist) { netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, - Arch.models, vpr_setup.AnalysisOpts); + Arch.models, vpr_setup.Timing, vpr_setup.clock_modeling, vpr_setup.AnalysisOpts); } //Write the post-implementation merged netlist diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index d19496411f5..8fc929ed06a 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1342,6 +1342,7 @@ struct t_analysis_opts { bool gen_post_synthesis_netlist; bool gen_post_implementation_merged_netlist; + bool gen_post_implementation_sdc; e_post_synth_netlist_unconn_handling post_synth_netlist_unconn_input_handling; e_post_synth_netlist_unconn_handling post_synth_netlist_unconn_output_handling; bool post_synth_netlist_module_parameters; From f07f639e5974fb45c56075a6661768f3f9621db7 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Thu, 1 May 2025 15:25:16 -0400 Subject: [PATCH 098/176] [STA] Added Tutorial for Post-Implementation Timing Analysis Created a tutorial demonstrating how OpenSTA can be used after VPR to perform static timing analysis. --- doc/src/tutorials/index.rst | 1 + doc/src/tutorials/timing_analysis/index.rst | 170 ++++++++ .../timing_analysis_design_cycle.png | Bin 0 -> 212906 bytes vtr_flow/primitives.lib | 370 ++++++++++++++++++ 4 files changed, 541 insertions(+) create mode 100644 doc/src/tutorials/timing_analysis/index.rst create mode 100644 doc/src/tutorials/timing_analysis/timing_analysis_design_cycle.png create mode 100644 vtr_flow/primitives.lib diff --git a/doc/src/tutorials/index.rst b/doc/src/tutorials/index.rst index 1c25145ef32..b9c661fb374 100644 --- a/doc/src/tutorials/index.rst +++ b/doc/src/tutorials/index.rst @@ -10,3 +10,4 @@ Tutorials arch/index titan_benchmarks/index timing_simulation/index + timing_analysis/index diff --git a/doc/src/tutorials/timing_analysis/index.rst b/doc/src/tutorials/timing_analysis/index.rst new file mode 100644 index 00000000000..6f93faa4c0e --- /dev/null +++ b/doc/src/tutorials/timing_analysis/index.rst @@ -0,0 +1,170 @@ +.. _timing_analysis_tutorial: + +Post-Implementation Timing Analysis +----------------------------------- + +This tutorial describes how to perform static timing analysis (STA) on a circuit which has +been implemented by :ref:`VPR` using OpenSTA, an external timing analysis tool. + +External timing analysis can be useful since VPR's timing analyzer (Tatum) does +not support all timing constraints and does not provide a TCL interface to allow +you to directly interrogate the timing graph. VPR also has limited support for +timing exceptions such as multi-cycles and false paths, which tools like OpenSTA +have better support for. + +Some external tools can also ingest more complex timing models (e.g. four +transition rr, rf, fr, ff delays vs. VTR's modeling of all transitions having +the same min,max range). + +.. _fig_timing_analysis_design_cycle: + +.. figure:: timing_analysis_design_cycle.png + + Post-implementation timing analysis design cycle. + +A user design cycle which would use post-implementation timing analysis could perform the following: + 1. Run VPR with the timing commands it can support (simplified constraints). + 2. Perform timing analysis on the resulting netlist using OpenSTA with + more complex timing commands. + 3. The user can then modify the design to meet the complex timing constraints based on the timing report produced by OpenSTA. + 4. The design can then be fed back into VPR and the process can repeat until all constraints are met. + +Generating the Post-Implementation Netlist for STA +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +For this tutorial, we will be using the ``clma`` :ref:`benchmark ` +targetting the ``k6_frac_N10_frac_chain_mem32K_40nm.xml`` architecture. + +We will first create a working directory to hold all the timing analysis files: + +.. code-block:: console + + $ mkdir timing_analysis_tut + $ cd timing_analysis_tut + +Next we will copy over the benchmark and FPGA architecture into the working +directory for convenience: + +.. code-block:: console + + $ cp $VTR_ROOT/vtr_flow/benchmarks/blif/clma.blif . + $ cp $VTR_ROOT/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml . + +.. note:: Replace :term:`$VTR_ROOT` with the root directory of the VTR source tree + +To perform timing analysis externally to VTR, we need to provide an SDC file +which will contain the timing constraints on the clocks and I/Os in the circuit. +For this tutorial, we will use the following ``clma.sdc`` file: + +.. code-block:: tcl + :linenos: + :caption: SDC file ``clma.sdc`` used for timing analysis. + + # Set pclk to be a clock with a 16ns period. + create_clock -period 16 pclk + + # Set the input delays of all input ports in the clma design to be 0 relative to pclk. + set_input_delay -clock pclk -max 0 [get_ports {pi*}] + + # Set the output delays of all output ports in the clma design to be 0 relative to pclk. + set_output_delay -clock pclk -max 0 [get_ports {p__*}] + +Next, we can generate the post-implementation netlist and other necessary files +for timing analysis using VPR. + +.. code-block:: console + + $ vpr \ + $ k6_frac_N10_frac_chain_mem32K_40nm.xml \ + $ clma.blif \ + $ --route_chan_width 100 \ + $ --sdc_file clma.sdc \ + $ --gen_post_synthesis_netlist on \ + $ --gen_post_implementation_sdc on \ + $ --post_synth_netlist_unconn_inputs gnd \ + $ --post_synth_netlist_module_parameters off + +In this command, we provide the architecture, circuit, the channel width, and +the SDC file. The other four commands are what generate the necessary netlist +files for timing analysis: + * ``--gen_post_synthesis_netlist on``: This will generate the post-implementation netlist as a Verilog file. + * ``--gen_post_implementation_sdc on``: This will have VPR generate a new SDC file which contains extra timing information (e.g. clock delays) based on how VPR implemented the design. + * ``--post_synth_netlist_unconn_inputs gnd``: For timing analysis with OpenSTA, we should be explicit about how we handle unconnected signal ports. Here we just ground them for simplicity. + * ``--post_synth_netlist_module_parameters off``: OpenSTA does not allow parameters to be used in the netlist. This command tells VPR to generate a netlist without using parameters. + +Once VPR has completed, we should see the generated Verilog netlist, SDF file, and SDC file: + +.. code-block:: console + + $ ls *.v *.sdf *.sdc + top_post_synthesis.sdc top_post_synthesis.sdf top_post_synthesis.v + + +Performing Timing Analysis using OpenSTA +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To perform static timing analysis for this tutorial, we will be using OpenSTA (https://github.com/parallaxsw/OpenSTA ). +Other STA tools can be used, however they may use slightly different commands. + +First, install OpenSTA onto your system. Building from source is a good option, +which can be done using the following instructions: +https://github.com/parallaxsw/OpenSTA?tab=readme-ov-file#build-from-source + +After OpenSTA is installed, we can perfrom static timing analysis on the post-implementation +netlist generated by VPR. + +It is easiest to write a ``sdf_delays.tcl`` file to setup and configure the timing analysis: + +.. code-block:: tcl + :linenos: + :caption: OpenSTA TCL file ``sdf_delays.tcl``. Note that :term:`$VTR_ROOT` should be replaced with the relevant path. + + # Read a skeleton of a liberty file which contains just enough information to + # allow OpenSTA to perform timing analysis on the post-synthesized netlist using + # an SDF file. This contains descriptions of the timing arcs of the primitives + # in the circuit. + read_liberty $VTR_ROOT/vtr_flow/primitives.lib + + # Read the post-implementation netlist generated by VPR. + read_verilog top_post_synthesis.v + + # Link the top-level design. + link_design top + + # Read the post-synthesis SDF file. + read_sdf top_post_synthesis.sdf + + # Read the SDC commands generated by VPR. + read_sdc top_post_synthesis.sdc + + # Report the setup and hold timing checks using OpenSTA and write them to files. + report_checks -group_path_count 100 -digits 3 -path_delay max > open_sta_report_timing.setup.rpt + report_checks -group_path_count 100 -digits 3 -path_delay min > open_sta_report_timing.hold.rpt + + # Report the minimum period of the clocks and their fmax. + report_clock_min_period + + # Exit OpenSTA's TCL terminal. + # This can be removed if you want terminal access to write TCL commands after + # executing the prior commands. + exit + +Now that we have a ``.tcl`` file, we can launch OpenSTA from the terminal and run it: + +.. code-block:: console + + $ sta sdf_delays.tcl + +Running this command will open a TCL terminal which will execute all of the commands +in ``sdf_delays.tcl``. The TCL file above will write setup and hold timing reports (similar to +the reports written by VPR), report the minimum period of all clocks, and then exit the OpenSTA TCL terminal. + +You can compare the timing reports generated by OpenSTA (``open_sta_report_timing.{setup/hold}.rpt``) +to the timing reports generated by VPR (``report_timing.{setup/hold}.rpt``). +You can also compare the minimum period reported by OpenSTA with the final +period reported by VTR at the bottom of ``vpr_stdout.log``. + +The TCL file above is just an example of what OpenSTA can do. For full documentation +of the different commands available in OpenSTA, see: +https://github.com/parallaxsw/OpenSTA/blob/master/doc/OpenSTA.pdf + diff --git a/doc/src/tutorials/timing_analysis/timing_analysis_design_cycle.png b/doc/src/tutorials/timing_analysis/timing_analysis_design_cycle.png new file mode 100644 index 0000000000000000000000000000000000000000..98b5e76629728be01fcdc028ab0a93e86d5e8353 GIT binary patch literal 212906 zcmeFZWn7f|_C8D~4I(lsDX6r7N=cW9ATc1Iv?3`f%^)CcgCa<$q?FXqC>BZ%DGegs z(*3O4t?qq1=XXB;_s@BuTiwGw-&k?2YhCNUhgMUhB%>$8!^5Lgx_Dj_503~1ziyBa z!N2U0774(A@SQXj*O$pwgpIgIWd;f8YP{ zo9{k?z2jO#bh7{VNARTy0?53dog?}`AA-N{A=)?izdT{zZBlCPb(60w|JO3$(JZiv z|FTegV^~FX(QD@!^^Y|t*sn}?@sF9e3jc}X9NA?u zLIrNx1>g~ou(0?ppsz2DH72rz-tuK~>%)0(FMceT7PjmALVB26JL}n^=PlVkpP;OI z2c6W8iCsMoEA=?cqE+Wa{Ot8?h{X4c`uW#n&tDREp15{7U5(ebv+ew!KU}~AUvFrf z`xyCpYCveOPdu^pEwSzGX^0ZIVdsQXIMO|VODXj7%nd<40$=g#HyI6bYHnJWwbpa+ zP!@MMqBqlFCNDLxcKtK2J~BH+cT{=0c`oA=>!aP58bx~V;1k}@`BX&whe`Uz0>1tB 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only defines the primitives that VPR defines as "library models". + * This includes LUTs (.names) and Flip-Flops (.latch). For user models (the + * models defined in the "models" section of the architecture description file), + * one should create another liberty file. + */ + +library (VTRPrimitives) { + + /* General Attributes */ + delay_model : table_lookup; + + /* Units Attributes */ + time_unit : "1ns"; + + /* Threshold Definitions */ + /* These are the default values according to the Liberty User Manual */ + slew_lower_threshold_pct_fall : 20.00 ; + slew_lower_threshold_pct_rise : 20.00 ; + slew_upper_threshold_pct_fall : 80.00 ; + slew_upper_threshold_pct_rise : 80.00 ; + input_threshold_pct_fall : 50.00 ; + input_threshold_pct_rise : 50.00 ; + output_threshold_pct_fall : 50.00 ; + output_threshold_pct_rise : 50.00 ; + + /* Bus types used for the LUT cells to allow their inputs to be arrays.*/ + type (BUS4) { + base_type: array; + data_type: bit; + bit_width: 4; + bit_from: 3; + bit_to: 0; + } + type (BUS5) { + base_type: array; + data_type: bit; + bit_width: 5; + bit_from: 4; + bit_to: 0; + } + type (BUS6) { + base_type: array; + data_type: bit; + bit_width: 6; + bit_from: 5; + bit_to: 0; + } + type (BUS16) { + base_type: array; + data_type: bit; + bit_width: 16; + bit_from: 15; + bit_to: 0; + } + type (BUS32) { + base_type: array; + data_type: bit; + bit_width: 32; + bit_from: 31; + bit_to: 0; + } + type (BUS64) { + base_type: array; + data_type: bit; + bit_width: 64; + bit_from: 63; + bit_to: 0; + } + + /** + * @brief FPGA interconnect module. This cell acts as a wire in the post- + * implementation netlist to add delays on connections between + * primitives (due to routing delays). + * + * INPUTS: + * datain + * OUPUTS: + * dataout + */ + cell (fpga_interconnect) { + pin (datain) { + direction: input; + } + pin (dataout) { + direction: output; + function: "datain"; + + timing() { + related_pin: "datain"; + timing_sense: positive_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } + + /** + * @brief 4-input LUT module. + * + * INPUTS: + * in: + * The input pins of the LUT, as an array. + * mask: + * The LUT mask that defines the output of the LUT as a function + * of the input. mask[0] is the output if all the inputs are 0, and + * mask[2^k - 1] is the output if all the inputs are 1. + * OUPUTS: + * out + */ + cell (LUT_4) { + bus (mask) { + bus_type: "BUS16"; + direction: input; + } + bus (in) { + bus_type: "BUS4"; + direction: input; + } + pin (out) { + direction: output; + function: "(mask[0] & !in[0] & !in[1] & !in[2] & !in[3]) | (mask[1] & in[0] & !in[1] & !in[2] & !in[3]) | (mask[2] & !in[0] & in[1] & !in[2] & !in[3]) | (mask[3] & in[0] & in[1] & !in[2] & !in[3]) | (mask[4] & !in[0] & !in[1] & in[2] & !in[3]) | (mask[5] & in[0] & !in[1] & in[2] & !in[3]) | (mask[6] & !in[0] & in[1] & in[2] & !in[3]) | (mask[7] & in[0] & in[1] & in[2] & !in[3]) | (mask[8] & !in[0] & !in[1] & !in[2] & in[3]) | (mask[9] & in[0] & !in[1] & !in[2] & in[3]) | (mask[10] & !in[0] & in[1] & !in[2] & in[3]) | (mask[11] & in[0] & in[1] & !in[2] & in[3]) | (mask[12] & !in[0] & !in[1] & in[2] & in[3]) | (mask[13] & in[0] & !in[1] & in[2] & in[3]) | (mask[14] & !in[0] & in[1] & in[2] & in[3]) | (mask[15] & in[0] & in[1] & in[2] & in[3])"; + + timing() { + related_pin: "in"; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } + + /** + * @brief 5-input LUT module. + * + * INPUTS: + * in: + * The input pins of the LUT, as an array. + * mask: + * The LUT mask that defines the output of the LUT as a function + * of the input. mask[0] is the output if all the inputs are 0, and + * mask[2^k - 1] is the output if all the inputs are 1. + * OUPUTS: + * out + */ + cell (LUT_5) { + bus (mask) { + bus_type: "BUS32"; + direction: input; + } + bus (in) { + bus_type: "BUS5"; + direction: input; + } + pin (out) { + direction: output; + function: "(mask[0] & !in[0] & !in[1] & !in[2] & !in[3] & !in[4]) | (mask[1] & in[0] & !in[1] & !in[2] & !in[3] & !in[4]) | (mask[2] & !in[0] & in[1] & !in[2] & !in[3] & !in[4]) | (mask[3] & in[0] & in[1] & !in[2] & !in[3] & !in[4]) | (mask[4] & !in[0] & !in[1] & in[2] & !in[3] & !in[4]) | (mask[5] & in[0] & !in[1] & in[2] & !in[3] & !in[4]) | (mask[6] & !in[0] & in[1] & in[2] & !in[3] & !in[4]) | (mask[7] & in[0] & in[1] & in[2] & !in[3] & !in[4]) | (mask[8] & !in[0] & !in[1] & !in[2] & in[3] & !in[4]) | (mask[9] & in[0] & !in[1] & !in[2] & in[3] & !in[4]) | (mask[10] & !in[0] & in[1] & !in[2] & in[3] & !in[4]) | (mask[11] & in[0] & in[1] & !in[2] & in[3] & !in[4]) | (mask[12] & !in[0] & !in[1] & in[2] & in[3] & !in[4]) | (mask[13] & in[0] & !in[1] & in[2] & in[3] & !in[4]) | (mask[14] & !in[0] & in[1] & in[2] & in[3] & !in[4]) | (mask[15] & in[0] & in[1] & in[2] & in[3] & !in[4]) | (mask[16] & !in[0] & !in[1] & !in[2] & !in[3] & in[4]) | (mask[17] & in[0] & !in[1] & !in[2] & !in[3] & in[4]) | (mask[18] & !in[0] & in[1] & !in[2] & !in[3] & in[4]) | (mask[19] & in[0] & in[1] & !in[2] & !in[3] & in[4]) | (mask[20] & !in[0] & !in[1] & in[2] & !in[3] & in[4]) | (mask[21] & in[0] & !in[1] & in[2] & !in[3] & in[4]) | (mask[22] & !in[0] & in[1] & in[2] & !in[3] & in[4]) | (mask[23] & in[0] & in[1] & in[2] & !in[3] & in[4]) | (mask[24] & !in[0] & !in[1] & !in[2] & in[3] & in[4]) | (mask[25] & in[0] & !in[1] & !in[2] & in[3] & in[4]) | (mask[26] & !in[0] & in[1] & !in[2] & in[3] & in[4]) | (mask[27] & in[0] & in[1] & !in[2] & in[3] & in[4]) | (mask[28] & !in[0] & !in[1] & in[2] & in[3] & in[4]) | (mask[29] & in[0] & !in[1] & in[2] & in[3] & in[4]) | (mask[30] & !in[0] & in[1] & in[2] & in[3] & in[4]) | (mask[31] & in[0] & in[1] & in[2] & in[3] & in[4])"; + + timing() { + related_pin: "in"; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } + + /** + * @brief 6-input LUT module. + * + * INPUTS: + * in: + * The input pins of the LUT, as an array. + * mask: + * The LUT mask that defines the output of the LUT as a function + * of the input. mask[0] is the output if all the inputs are 0, and + * mask[2^k - 1] is the output if all the inputs are 1. + * OUPUTS: + * out + */ + cell (LUT_6) { + bus (mask) { + bus_type: "BUS64"; + direction: input; + } + bus (in) { + bus_type: "BUS6"; + direction: input; + } + pin (out) { + direction: output; + function: "(mask[0] & !in[0] & !in[1] & !in[2] & !in[3] & !in[4] & !in[5]) | (mask[1] & in[0] & !in[1] & !in[2] & !in[3] & !in[4] & !in[5]) | (mask[2] & !in[0] & in[1] & !in[2] & !in[3] & !in[4] & !in[5]) | (mask[3] & in[0] & in[1] & !in[2] & !in[3] & !in[4] & !in[5]) | (mask[4] & !in[0] & !in[1] & in[2] & !in[3] & !in[4] & !in[5]) | (mask[5] & in[0] & !in[1] & in[2] & !in[3] & !in[4] & !in[5]) | (mask[6] & !in[0] & in[1] & in[2] & !in[3] & !in[4] & !in[5]) | (mask[7] & in[0] & in[1] & in[2] & !in[3] & !in[4] & !in[5]) | (mask[8] & !in[0] & !in[1] & !in[2] & in[3] & !in[4] & !in[5]) | (mask[9] & in[0] & !in[1] & !in[2] & in[3] & !in[4] & !in[5]) | (mask[10] & !in[0] & in[1] & !in[2] & in[3] & !in[4] & !in[5]) | (mask[11] & in[0] & in[1] & !in[2] & in[3] & !in[4] & !in[5]) | (mask[12] & !in[0] & !in[1] & in[2] & in[3] & !in[4] & !in[5]) | (mask[13] & in[0] & !in[1] & in[2] & in[3] & !in[4] & !in[5]) | (mask[14] & !in[0] & in[1] & in[2] & in[3] & !in[4] & !in[5]) | (mask[15] & in[0] & in[1] & in[2] & in[3] & !in[4] & !in[5]) | (mask[16] & !in[0] & !in[1] & !in[2] & !in[3] & in[4] & !in[5]) | (mask[17] & in[0] & !in[1] & !in[2] & !in[3] & in[4] & !in[5]) | (mask[18] & !in[0] & in[1] & !in[2] & !in[3] & in[4] & !in[5]) | (mask[19] & in[0] & in[1] & !in[2] & !in[3] & in[4] & !in[5]) | (mask[20] & !in[0] & !in[1] & in[2] & !in[3] & in[4] & !in[5]) | (mask[21] & in[0] & !in[1] & in[2] & !in[3] & in[4] & !in[5]) | (mask[22] & !in[0] & in[1] & in[2] & !in[3] & in[4] & !in[5]) | (mask[23] & in[0] & in[1] & in[2] & !in[3] & in[4] & !in[5]) | (mask[24] & !in[0] & !in[1] & !in[2] & in[3] & in[4] & !in[5]) | (mask[25] & in[0] & !in[1] & !in[2] & in[3] & in[4] & !in[5]) | (mask[26] & !in[0] & in[1] & !in[2] & in[3] & in[4] & !in[5]) | (mask[27] & in[0] & in[1] & !in[2] & in[3] & in[4] & !in[5]) | (mask[28] & !in[0] & !in[1] & in[2] & in[3] & in[4] & !in[5]) | (mask[29] & in[0] & !in[1] & in[2] & in[3] & in[4] & !in[5]) | (mask[30] & !in[0] & in[1] & in[2] & in[3] & in[4] & !in[5]) | (mask[31] & in[0] & in[1] & in[2] & in[3] & in[4] & !in[5]) | (mask[32] & !in[0] & !in[1] & !in[2] & !in[3] & !in[4] & in[5]) | (mask[33] & in[0] & !in[1] & !in[2] & !in[3] & !in[4] & in[5]) | (mask[34] & !in[0] & in[1] & !in[2] & !in[3] & !in[4] & in[5]) | (mask[35] & in[0] & in[1] & !in[2] & !in[3] & !in[4] & in[5]) | (mask[36] & !in[0] & !in[1] & in[2] & !in[3] & !in[4] & in[5]) | (mask[37] & in[0] & !in[1] & in[2] & !in[3] & !in[4] & in[5]) | (mask[38] & !in[0] & in[1] & in[2] & !in[3] & !in[4] & in[5]) | (mask[39] & in[0] & in[1] & in[2] & !in[3] & !in[4] & in[5]) | (mask[40] & !in[0] & !in[1] & !in[2] & in[3] & !in[4] & in[5]) | (mask[41] & in[0] & !in[1] & !in[2] & in[3] & !in[4] & in[5]) | (mask[42] & !in[0] & in[1] & !in[2] & in[3] & !in[4] & in[5]) | (mask[43] & in[0] & in[1] & !in[2] & in[3] & !in[4] & in[5]) | (mask[44] & !in[0] & !in[1] & in[2] & in[3] & !in[4] & in[5]) | (mask[45] & in[0] & !in[1] & in[2] & in[3] & !in[4] & in[5]) | (mask[46] & !in[0] & in[1] & in[2] & in[3] & !in[4] & in[5]) | (mask[47] & in[0] & in[1] & in[2] & in[3] & !in[4] & in[5]) | (mask[48] & !in[0] & !in[1] & !in[2] & !in[3] & in[4] & in[5]) | (mask[49] & in[0] & !in[1] & !in[2] & !in[3] & in[4] & in[5]) | (mask[50] & !in[0] & in[1] & !in[2] & !in[3] & in[4] & in[5]) | (mask[51] & in[0] & in[1] & !in[2] & !in[3] & in[4] & in[5]) | (mask[52] & !in[0] & !in[1] & in[2] & !in[3] & in[4] & in[5]) | (mask[53] & in[0] & !in[1] & in[2] & !in[3] & in[4] & in[5]) | (mask[54] & !in[0] & in[1] & in[2] & !in[3] & in[4] & in[5]) | (mask[55] & in[0] & in[1] & in[2] & !in[3] & in[4] & in[5]) | (mask[56] & !in[0] & !in[1] & !in[2] & in[3] & in[4] & in[5]) | (mask[57] & in[0] & !in[1] & !in[2] & in[3] & in[4] & in[5]) | (mask[58] & !in[0] & in[1] & !in[2] & in[3] & in[4] & in[5]) | (mask[59] & in[0] & in[1] & !in[2] & in[3] & in[4] & in[5]) | (mask[60] & !in[0] & !in[1] & in[2] & in[3] & in[4] & in[5]) | (mask[61] & in[0] & !in[1] & in[2] & in[3] & in[4] & in[5]) | (mask[62] & !in[0] & in[1] & in[2] & in[3] & in[4] & in[5]) | (mask[63] & in[0] & in[1] & in[2] & in[3] & in[4] & in[5])"; + + timing() { + related_pin: "in"; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } + + /** + * @brief D-Flip-Flop module. + * + * INPUTS: + * D: + * The input of the DFF, which will get latched on the rising clock + * edge. + * clock: + * The clock signal for the DFF. + * OUPUTS: + * Q: + * The current value stored in the latch. + * QN: + * The inverse of the current value stored in the latch. + */ + cell (DFF) { + ff (IQ, IQN) { + next_state: "D"; + clocked_on: "clock"; + } + + pin (D) { + direction: input; + + timing() { + related_pin: "clock"; + timing_type: hold_rising; + + fall_constraint(scalar) { + values("0.0"); + } + rise_constraint(scalar) { + values("0.0"); + } + } + + timing() { + related_pin: "clock"; + timing_type: setup_rising; + + fall_constraint(scalar) { + values("0.0"); + } + rise_constraint(scalar) { + values("0.0"); + } + } + } + + pin (clock) { + direction: input; + clock: true; + + timing() { + related_pin: "clock"; + timing_type: min_pulse_width; + + fall_constraint(scalar) { + values("0.0"); + } + rise_constraint(scalar) { + values("0.0"); + } + } + } + + pin (Q) { + direction: output; + function: "IQ"; + + timing() { + related_pin: "clock"; + timing_type: rising_edge; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + + pin (QN) { + direction: output; + function: "IQN"; + + timing() { + related_pin: "clock"; + timing_type: rising_edge; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } +} From 4c484fad8698b29a4449b34872aeb31ae9eb120d Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Fri, 9 May 2025 09:23:28 -0400 Subject: [PATCH 099/176] Add artifact upload to nightly test workflow --- .github/workflows/nightly_test_manual.yml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/.github/workflows/nightly_test_manual.yml b/.github/workflows/nightly_test_manual.yml index f98f412eb8c..5bf32327050 100644 --- a/.github/workflows/nightly_test_manual.yml +++ b/.github/workflows/nightly_test_manual.yml @@ -104,3 +104,12 @@ jobs: run: | source .venv/bin/activate ./run_reg_test.py -j12 vtr_reg_nightly_test7 + + - name: Upload regression results + if: success() || failure() + uses: actions/upload-artifact@v4 + with: + name: nightly_test_results + path: | + vtr_flow/**/*.log + vtr_flow/**/parse_results*.txt From e46d300d382140b420c0413b84a429102c532919 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sat, 10 May 2025 19:55:16 -0400 Subject: [PATCH 100/176] t_det_routing_arch* --> const t_det_routing_arch& --- vpr/src/analytical_place/detailed_placer.cpp | 2 +- vpr/src/base/SetupVPR.cpp | 70 ++++++++++--------- vpr/src/base/SetupVPR.h | 2 +- vpr/src/base/place_and_route.cpp | 16 ++--- vpr/src/base/place_and_route.h | 2 +- vpr/src/base/vpr_api.cpp | 23 +++--- vpr/src/base/vpr_api.h | 4 +- .../PlacementDelayModelCreator.cpp | 4 +- .../delay_model/PlacementDelayModelCreator.h | 2 +- vpr/src/place/place.cpp | 2 +- vpr/src/place/place.h | 2 +- vpr/src/power/power.cpp | 27 ++++--- vpr/src/power/power.h | 10 ++- vpr/src/power/power_callibrate.h | 4 +- vpr/src/route/route.cpp | 10 +-- vpr/src/route/route.h | 2 +- vpr/src/route/route_utils.cpp | 6 +- vpr/src/route/route_utils.h | 2 +- vpr/src/route/router_delay_profiling.cpp | 4 +- vpr/src/route/router_delay_profiling.h | 2 +- vpr/src/route/rr_graph.cpp | 54 +++++++------- vpr/src/route/rr_graph.h | 2 +- 22 files changed, 124 insertions(+), 128 deletions(-) diff --git a/vpr/src/analytical_place/detailed_placer.cpp b/vpr/src/analytical_place/detailed_placer.cpp index 75001fe4c42..9b84e1cf6f9 100644 --- a/vpr/src/analytical_place/detailed_placer.cpp +++ b/vpr/src/analytical_place/detailed_placer.cpp @@ -65,7 +65,7 @@ AnnealerDetailedPlacer::AnnealerDetailedPlacer(const BlkLocRegistry& curr_cluste place_delay_model = PlacementDelayModelCreator::create_delay_model(vpr_setup.PlacerOpts, vpr_setup.RouterOpts, (const Netlist<>&)clustered_netlist, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, arch.Chans, arch.directs, diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index dc692cdcd11..25556636617 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -38,10 +38,12 @@ static void SetupNocOpts(const t_options& Options, t_noc_opts* NocOpts); static void SetupServerOpts(const t_options& Options, t_server_opts* ServerOpts); -static void SetupRoutingArch(const t_arch& Arch, t_det_routing_arch* RoutingArch); + +static void SetupRoutingArch(const t_arch& Arch, t_det_routing_arch& RoutingArch); + static void SetupTiming(const t_options& Options, const bool TimingEnabled, t_timing_inf* Timing); static void SetupSwitches(const t_arch& Arch, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, const std::vector& arch_switches); static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysis_opts); static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch); @@ -97,7 +99,7 @@ void SetupVPR(const t_options* options, t_analysis_opts* analysisOpts, t_noc_opts* nocOpts, t_server_opts* serverOpts, - t_det_routing_arch* routingArch, + t_det_routing_arch& routingArch, std::vector** packerRRGraphs, std::vector& segments, t_timing_inf* timing, @@ -231,9 +233,9 @@ void SetupVPR(const t_options* options, SetupTiming(*options, timingenabled, timing); SetupPackerOpts(*options, packerOpts); SetupAPOpts(*options, *apOpts); - routingArch->write_rr_graph_filename = options->write_rr_graph_file; - routingArch->read_rr_graph_filename = options->read_rr_graph_file; - routingArch->read_rr_edge_override_filename = options->read_rr_edge_override_file; + routingArch.write_rr_graph_filename = options->write_rr_graph_file; + routingArch.read_rr_graph_filename = options->read_rr_graph_file; + routingArch.read_rr_edge_override_filename = options->read_rr_edge_override_file; for (auto has_global_routing : arch->layer_global_routing) { device_ctx.inter_cluster_prog_routing_resources.emplace_back(has_global_routing); @@ -355,17 +357,17 @@ static void SetupTiming(const t_options& Options, const bool TimingEnabled, t_ti * from the arch file with the special switches that VPR needs. */ static void SetupSwitches(const t_arch& Arch, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, const std::vector& arch_switches) { auto& device_ctx = g_vpr_ctx.mutable_device(); int switches_to_copy = (int)arch_switches.size(); int num_arch_switches = (int)arch_switches.size(); - find_ipin_cblock_switch_index(Arch, RoutingArch->wire_to_arch_ipin_switch, RoutingArch->wire_to_arch_ipin_switch_between_dice); + find_ipin_cblock_switch_index(Arch, RoutingArch.wire_to_arch_ipin_switch, RoutingArch.wire_to_arch_ipin_switch_between_dice); /* Depends on device_ctx.num_arch_switches */ - RoutingArch->delayless_switch = num_arch_switches++; + RoutingArch.delayless_switch = num_arch_switches++; /* Alloc the list now that we know the final num_arch_switches value */ device_ctx.arch_switch_inf.resize(num_arch_switches); @@ -377,32 +379,32 @@ static void SetupSwitches(const t_arch& Arch, } /* Delayless switch for connecting sinks and sources with their pins. */ - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].set_type(SwitchType::MUX); - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].name = std::string(VPR_DELAYLESS_SWITCH_NAME); - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].R = 0.; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].Cin = 0.; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].Cout = 0.; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, 0.); - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].mux_trans_size = 0.; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].buf_size_type = BufferSize::ABSOLUTE; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].buf_size = 0.; - VTR_ASSERT_MSG(device_ctx.arch_switch_inf[RoutingArch->delayless_switch].buffered(), "Delayless switch expected to be buffered (isolating)"); - VTR_ASSERT_MSG(device_ctx.arch_switch_inf[RoutingArch->delayless_switch].configurable(), "Delayless switch expected to be configurable"); + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].set_type(SwitchType::MUX); + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].name = std::string(VPR_DELAYLESS_SWITCH_NAME); + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].R = 0.; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].Cin = 0.; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].Cout = 0.; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, 0.); + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].mux_trans_size = 0.; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].buf_size_type = BufferSize::ABSOLUTE; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].buf_size = 0.; + VTR_ASSERT_MSG(device_ctx.arch_switch_inf[RoutingArch.delayless_switch].buffered(), "Delayless switch expected to be buffered (isolating)"); + VTR_ASSERT_MSG(device_ctx.arch_switch_inf[RoutingArch.delayless_switch].configurable(), "Delayless switch expected to be configurable"); - device_ctx.all_sw_inf[RoutingArch->delayless_switch] = device_ctx.arch_switch_inf[RoutingArch->delayless_switch]; + device_ctx.all_sw_inf[RoutingArch.delayless_switch] = device_ctx.arch_switch_inf[RoutingArch.delayless_switch]; - RoutingArch->global_route_switch = RoutingArch->delayless_switch; + RoutingArch.global_route_switch = RoutingArch.delayless_switch; - device_ctx.delayless_switch_idx = RoutingArch->delayless_switch; + device_ctx.delayless_switch_idx = RoutingArch.delayless_switch; //Warn about non-zero Cout values for the ipin switch, since these values have no effect. //VPR do not model the R/C's of block internal routing connection. // //Note that we don't warn about the R value as it may be used to size the buffer (if buf_size_type is AUTO) - if (device_ctx.arch_switch_inf[RoutingArch->wire_to_arch_ipin_switch].Cout != 0.) { + if (device_ctx.arch_switch_inf[RoutingArch.wire_to_arch_ipin_switch].Cout != 0.) { VTR_LOG_WARN("Non-zero switch output capacitance (%g) has no effect when switch '%s' is used for connection block inputs\n", - device_ctx.arch_switch_inf[RoutingArch->wire_to_arch_ipin_switch].Cout, Arch.ipin_cblock_switch_name[0].c_str()); + device_ctx.arch_switch_inf[RoutingArch.wire_to_arch_ipin_switch].Cout, Arch.ipin_cblock_switch_name[0].c_str()); } } @@ -412,18 +414,18 @@ static void SetupSwitches(const t_arch& Arch, * Since checks are already done, this just copies values across */ static void SetupRoutingArch(const t_arch& Arch, - t_det_routing_arch* RoutingArch) { - RoutingArch->switch_block_type = Arch.SBType; - RoutingArch->R_minW_nmos = Arch.R_minW_nmos; - RoutingArch->R_minW_pmos = Arch.R_minW_pmos; - RoutingArch->Fs = Arch.Fs; - RoutingArch->directionality = BI_DIRECTIONAL; + t_det_routing_arch& RoutingArch) { + RoutingArch.switch_block_type = Arch.SBType; + RoutingArch.R_minW_nmos = Arch.R_minW_nmos; + RoutingArch.R_minW_pmos = Arch.R_minW_pmos; + RoutingArch.Fs = Arch.Fs; + RoutingArch.directionality = BI_DIRECTIONAL; if (!Arch.Segments.empty()) { - RoutingArch->directionality = Arch.Segments[0].directionality; + RoutingArch.directionality = Arch.Segments[0].directionality; } /* copy over the switch block information */ - RoutingArch->switchblocks = Arch.switchblocks; + RoutingArch.switchblocks = Arch.switchblocks; } static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { diff --git a/vpr/src/base/SetupVPR.h b/vpr/src/base/SetupVPR.h index 9492da360d6..7470a1fd0c8 100644 --- a/vpr/src/base/SetupVPR.h +++ b/vpr/src/base/SetupVPR.h @@ -18,7 +18,7 @@ void SetupVPR(const t_options* Options, t_analysis_opts* AnalysisOpts, t_noc_opts* NocOpts, t_server_opts* ServerOpts, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, std::vector** PackerRRGraphs, std::vector& Segments, t_timing_inf* Timing, diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index e910d02418f..6fd8dc87f27 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -48,7 +48,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, const t_arch* arch, bool verify_binary_search, int min_chan_width_hint, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, NetPinsMatrix& net_delay, const std::shared_ptr& timing_info, @@ -83,13 +83,13 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, graph_type = e_graph_type::GLOBAL; graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } VTR_ASSERT(!net_delay.empty()); - if (det_routing_arch->directionality == BI_DIRECTIONAL) + if (det_routing_arch.directionality == BI_DIRECTIONAL) udsd_multiplier = 1; else udsd_multiplier = 2; @@ -116,14 +116,14 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, } /* Constraints must be checked to not break rr_graph generator */ - if (det_routing_arch->directionality == UNI_DIRECTIONAL) { + if (det_routing_arch.directionality == UNI_DIRECTIONAL) { if (current % 2 != 0) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Tried odd chan width (%d) in uni-directional routing architecture (chan width must be even).\n", current); } } else { - if (det_routing_arch->Fs % 3) { + if (det_routing_arch.Fs % 3) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Fs must be three in bidirectional mode.\n"); } @@ -158,7 +158,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, } } - if ((current * 3) < det_routing_arch->Fs) { + if ((current * 3) < det_routing_arch.Fs) { VTR_LOG("Width factor is now below specified Fs. Stop search.\n"); final = high; break; @@ -350,7 +350,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, prev2_success = prev_success; prev_success = success; current--; - if (det_routing_arch->directionality == UNI_DIRECTIONAL) { + if (det_routing_arch.directionality == UNI_DIRECTIONAL) { current--; /* width must be even */ } } diff --git a/vpr/src/base/place_and_route.h b/vpr/src/base/place_and_route.h index e595a2cdedb..da27077cfac 100644 --- a/vpr/src/base/place_and_route.h +++ b/vpr/src/base/place_and_route.h @@ -29,7 +29,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, const t_arch* arch, bool verify_binary_search, int min_chan_width_hint, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, NetPinsMatrix& net_delay, const std::shared_ptr& timing_info, diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 560b3e2d527..b841c23bd36 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -293,7 +293,7 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a &vpr_setup->AnalysisOpts, &vpr_setup->NocOpts, &vpr_setup->ServerOpts, - &vpr_setup->RoutingArch, + vpr_setup->RoutingArch, &vpr_setup->PackerRRGraph, vpr_setup->Segments, &vpr_setup->Timing, @@ -830,7 +830,7 @@ void vpr_place(const Netlist<>& net_list, vpr_setup.AnalysisOpts, vpr_setup.NocOpts, arch.Chans, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, arch.directs, g_vpr_ctx.atom().flat_placement_info(), @@ -848,7 +848,7 @@ void vpr_place(const Netlist<>& net_list, } void vpr_load_placement(t_vpr_setup& vpr_setup, - const std::vector directs) { + const std::vector& directs) { vtr::ScopedStartFinishTimer timer("Load Placement"); const auto& device_ctx = g_vpr_ctx.device(); @@ -1044,7 +1044,7 @@ RouteStatus vpr_route_fixed_W(const Netlist<>& net_list, fixed_channel_width, vpr_setup.RouterOpts, vpr_setup.AnalysisOpts, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, net_delay, timing_info, @@ -1081,7 +1081,7 @@ RouteStatus vpr_route_min_W(const Netlist<>& net_list, &arch, router_opts.verify_binary_search, router_opts.min_channel_width_hint, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, net_delay, timing_info, @@ -1121,7 +1121,7 @@ RouteStatus vpr_load_routing(t_vpr_setup& vpr_setup, void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_width_fac, bool is_flat) { auto& device_ctx = g_vpr_ctx.mutable_device(); - auto det_routing_arch = &vpr_setup.RoutingArch; + t_det_routing_arch& det_routing_arch = vpr_setup.RoutingArch; auto& router_opts = vpr_setup.RouterOpts; e_graph_type graph_type; @@ -1130,8 +1130,8 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi graph_type = e_graph_type::GLOBAL; graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } t_chan_width chan_width = init_chan(chan_width_fac, arch.Chans, graph_directionality); @@ -1293,7 +1293,7 @@ void vpr_setup_vpr(t_options* Options, t_analysis_opts* AnalysisOpts, t_noc_opts* NocOpts, t_server_opts* ServerOpts, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, std::vector** PackerRRGraph, std::vector& Segments, t_timing_inf* Timing, @@ -1518,7 +1518,7 @@ void vpr_power_estimation(const t_vpr_setup& vpr_setup, /* Initialize the power module */ bool power_error = power_init(vpr_setup.FileNameOpts.PowerFile.c_str(), - vpr_setup.FileNameOpts.CmosTechFile.c_str(), &Arch, &vpr_setup.RoutingArch); + vpr_setup.FileNameOpts.CmosTechFile.c_str(), &Arch, vpr_setup.RoutingArch); if (power_error) { VTR_LOG_ERROR("Power initialization failed.\n"); } @@ -1529,8 +1529,7 @@ void vpr_power_estimation(const t_vpr_setup& vpr_setup, VTR_LOG("Running power estimation\n"); /* Run power estimation */ - e_power_ret_code power_ret_code = power_total(&power_runtime_s, vpr_setup, - &Arch, &vpr_setup.RoutingArch); + e_power_ret_code power_ret_code = power_total(&power_runtime_s, vpr_setup, &Arch, vpr_setup.RoutingArch); /* Check for errors/warnings */ if (power_ret_code == POWER_RET_CODE_ERRORS) { diff --git a/vpr/src/base/vpr_api.h b/vpr/src/base/vpr_api.h index 28324e60da1..54d4f8bf5c6 100644 --- a/vpr/src/base/vpr_api.h +++ b/vpr/src/base/vpr_api.h @@ -82,7 +82,7 @@ void vpr_place(const Netlist<>& net_list, ///@brief Loads a previous placement void vpr_load_placement(t_vpr_setup& vpr_setup, - const std::vector directs); + const std::vector& directs); /* Routing */ @@ -186,7 +186,7 @@ void vpr_setup_vpr(t_options* Options, t_analysis_opts* AnalysisOpts, t_noc_opts* NocOpts, t_server_opts* ServerOpts, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, std::vector** PackerRRGraph, std::vector& Segments, t_timing_inf* Timing, diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp index e58cb4b9539..8cdffa1029e 100644 --- a/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp @@ -27,7 +27,7 @@ std::unique_ptr PlacementDelayModelCreator::create_delay_model(const t_placer_opts& placer_opts, const t_router_opts& router_opts, const Netlist<>& net_list, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, const std::vector& directs, @@ -38,7 +38,7 @@ PlacementDelayModelCreator::create_delay_model(const t_placer_opts& placer_opts, alloc_routing_structs(chan_width, router_opts, det_routing_arch, segment_inf, directs, is_flat); - const RouterLookahead* router_lookahead = get_cached_router_lookahead(*det_routing_arch, + const RouterLookahead* router_lookahead = get_cached_router_lookahead(det_routing_arch, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.h b/vpr/src/place/delay_model/PlacementDelayModelCreator.h index c92b67d4854..855281d77f2 100644 --- a/vpr/src/place/delay_model/PlacementDelayModelCreator.h +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.h @@ -22,7 +22,7 @@ class PlacementDelayModelCreator { static std::unique_ptr create_delay_model(const t_placer_opts& placer_opts, const t_router_opts& router_opts, const Netlist<>& net_list, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, const std::vector& directs, diff --git a/vpr/src/place/place.cpp b/vpr/src/place/place.cpp index 646e2a6deed..b681ddc0a36 100644 --- a/vpr/src/place/place.cpp +++ b/vpr/src/place/place.cpp @@ -34,7 +34,7 @@ void try_place(const Netlist<>& net_list, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, t_chan_width_dist chan_width_dist, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, const FlatPlacementInfo& flat_placement_info, diff --git a/vpr/src/place/place.h b/vpr/src/place/place.h index c7c3d9f8758..29e202a4e0b 100644 --- a/vpr/src/place/place.h +++ b/vpr/src/place/place.h @@ -11,7 +11,7 @@ void try_place(const Netlist<>& net_list, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, t_chan_width_dist chan_width_dist, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, const FlatPlacementInfo& flat_placement_info, diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index 888507ae804..1b88e2e8317 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -7,7 +7,7 @@ * or email: * vtr.power.estimation@gmail.com * - * If you are using power estimation for your researach please cite: + * If you are using power estimation for your research please cite: * * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation * for Diverse FPGA Architectures. In International Conference on @@ -65,7 +65,7 @@ static t_rr_node_power* rr_node_power; /************************* Function Declarations ********************/ /* Routing */ static void power_usage_routing(t_power_usage* power_usage, - const t_det_routing_arch* routing_arch, + const t_det_routing_arch& routing_arch, bool is_flat); /* Tiles */ @@ -111,7 +111,7 @@ void power_init_pb_pins_rec(t_pb_graph_node* pb_node); void power_uninit_pb_pins_rec(t_pb_graph_node* pb_node); void power_pb_pins_init(); void power_pb_pins_uninit(); -void power_routing_init(const t_det_routing_arch* routing_arch); +void power_routing_init(const t_det_routing_arch& routing_arch); /************************* FUNCTION DEFINITIONS *********************/ /** @@ -783,7 +783,7 @@ static void dealloc_mux_graph_rec(t_mux_node* node) { * Calculates the power of the entire routing fabric (not local routing */ static void power_usage_routing(t_power_usage* power_usage, - const t_det_routing_arch* routing_arch, + const t_det_routing_arch& routing_arch, bool is_flat) { auto& power_ctx = g_vpr_ctx.power(); auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -988,9 +988,9 @@ static void power_usage_routing(t_power_usage* power_usage, connectionbox_fanout = 0; switchbox_fanout = 0; for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) { - if (rr_graph.edge_switch(rr_id, iedge) == routing_arch->wire_to_rr_ipin_switch) { + if (rr_graph.edge_switch(rr_id, iedge) == routing_arch.wire_to_rr_ipin_switch) { connectionbox_fanout++; - } else if (rr_graph.edge_switch(rr_id, iedge) == routing_arch->delayless_switch) { + } else if (rr_graph.edge_switch(rr_id, iedge) == routing_arch.delayless_switch) { /* Do nothing */ } else { switchbox_fanout++; @@ -1180,7 +1180,7 @@ void power_pb_pins_uninit() { } } -void power_routing_init(const t_det_routing_arch* routing_arch) { +void power_routing_init(const t_det_routing_arch& routing_arch) { t_edge_size max_fanin; t_edge_size max_IPIN_fanin; t_edge_size max_seg_to_IPIN_fanout; @@ -1234,9 +1234,9 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { case e_rr_type::CHANX: case e_rr_type::CHANY: for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_node_idx); iedge++) { - if (rr_graph.edge_switch(rr_node_idx, iedge) == routing_arch->wire_to_rr_ipin_switch) { + if (rr_graph.edge_switch(rr_node_idx, iedge) == routing_arch.wire_to_rr_ipin_switch) { fanout_to_IPIN++; - } else if (rr_graph.edge_switch(rr_node_idx, iedge) != routing_arch->delayless_switch) { + } else if (rr_graph.edge_switch(rr_node_idx, iedge) != routing_arch.delayless_switch) { fanout_to_seg++; } } @@ -1304,7 +1304,7 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { bool power_init(const char* power_out_filepath, const char* cmos_tech_behavior_filepath, const t_arch* arch, - const t_det_routing_arch* routing_arch) { + const t_det_routing_arch& routing_arch) { auto& power_ctx = g_vpr_ctx.mutable_power(); bool error = false; @@ -1386,8 +1386,7 @@ bool power_uninit() { delete[] rr_node_power; /* Free mux architectures */ - for (std::map::iterator it = power_ctx.commonly_used->mux_info.begin(); - it != power_ctx.commonly_used->mux_info.end(); it++) { + for (auto it = power_ctx.commonly_used->mux_info.begin(); it != power_ctx.commonly_used->mux_info.end(); it++) { t_power_mux_info* mux_info = it->second; for (mux_size = 1; mux_size <= mux_info->mux_arch_max_size; mux_size++) { dealloc_mux_graph(mux_info->mux_arch[mux_size].mux_graph_head); @@ -1710,7 +1709,7 @@ static void power_print_summary(FILE* fp, const t_vpr_setup& vpr_setup) { * and prints it to the output file * - run_time_s: (Return value) The total runtime in seconds (us accuracy) */ -e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, const t_arch* arch, const t_det_routing_arch* routing_arch) { +e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, const t_arch* arch, const t_det_routing_arch& routing_arch) { t_power_usage total_power; t_power_usage sub_power_usage; clock_t t_start; @@ -1722,7 +1721,7 @@ e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, co power_zero_usage(&total_power); - if (routing_arch->directionality == BI_DIRECTIONAL) { + if (routing_arch.directionality == BI_DIRECTIONAL) { power_log_msg(POWER_LOG_ERROR, "Cannot calculate routing power for bi-directional architectures"); return POWER_RET_CODE_ERRORS; diff --git a/vpr/src/power/power.h b/vpr/src/power/power.h index 42191fafe2d..192245de3b4 100644 --- a/vpr/src/power/power.h +++ b/vpr/src/power/power.h @@ -1,3 +1,5 @@ +#pragma once + /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -19,9 +21,6 @@ * This is the top-level file for power estimation in VTR */ -#ifndef __POWER_H__ -#define __POWER_H__ - /************************* INCLUDES *********************************/ #include @@ -308,11 +307,10 @@ struct t_mux_node { bool power_init(const char* power_out_filepath, const char* cmos_tech_behavior_filepath, const t_arch* arch, - const t_det_routing_arch* routing_arch); + const t_det_routing_arch& routing_arch); bool power_uninit(); /* Top-Level Function */ -e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, const t_arch* arch, const t_det_routing_arch* routing_arch); +e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, const t_arch* arch, const t_det_routing_arch& routing_arch); -#endif /* __POWER_H__ */ diff --git a/vpr/src/power/power_callibrate.h b/vpr/src/power/power_callibrate.h index eb387b4e3d9..48852da4ea9 100644 --- a/vpr/src/power/power_callibrate.h +++ b/vpr/src/power/power_callibrate.h @@ -19,8 +19,7 @@ * againt SPICE. */ -#ifndef __POWER_MISC_H__ -#define __POWER_MISC_H__ +#pragma once /************************* INCLUDES *********************************/ #include "power.h" @@ -49,4 +48,3 @@ float power_usage_mux_for_callibration(int num_inputs, float transistor_size); float power_usage_lut_for_callibration(int num_inputs, float transistor_size); float power_usage_ff_for_callibration(int num_inputs, float transistor_size); void power_print_callibration(); -#endif diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index cad0cf1b7aa..ca1589fdeaa 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -16,7 +16,7 @@ bool route(const Netlist<>& net_list, int width_fac, const t_router_opts& router_opts, const t_analysis_opts& analysis_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, NetPinsMatrix& net_delay, std::shared_ptr timing_info, @@ -40,8 +40,8 @@ bool route(const Netlist<>& net_list, graph_type = e_graph_type::GLOBAL; graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } /* Set the channel widths */ @@ -119,7 +119,7 @@ bool route(const Netlist<>& net_list, route_budgets budgeting_inf(net_list, is_flat); // This needs to be called before filling intra-cluster lookahead maps to ensure that the intra-cluster lookahead maps are initialized. - const RouterLookahead* router_lookahead = get_cached_router_lookahead(*det_routing_arch, + const RouterLookahead* router_lookahead = get_cached_router_lookahead(det_routing_arch, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, @@ -139,7 +139,7 @@ bool route(const Netlist<>& net_list, mut_router_lookahead->compute_intra_tile(); } route_ctx.cached_router_lookahead_.set(cache_key, std::move(mut_router_lookahead)); - router_lookahead = get_cached_router_lookahead(*det_routing_arch, + router_lookahead = get_cached_router_lookahead(det_routing_arch, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, diff --git a/vpr/src/route/route.h b/vpr/src/route/route.h index 082a417008e..5d519228d0d 100644 --- a/vpr/src/route/route.h +++ b/vpr/src/route/route.h @@ -21,7 +21,7 @@ bool route(const Netlist<>& net_list, int width_fac, const t_router_opts& router_opts, const t_analysis_opts& analysis_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, NetPinsMatrix& net_delay, std::shared_ptr timing_info, diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index 687ca44d063..c5f498a9500 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -466,7 +466,7 @@ vtr::vector>> set_net /** Wrapper for create_rr_graph() with extra checks */ void try_graph(int width_fac, const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, const std::vector& directs, @@ -479,8 +479,8 @@ void try_graph(int width_fac, graph_type = e_graph_type::GLOBAL; graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } /* Set the channel widths */ diff --git a/vpr/src/route/route_utils.h b/vpr/src/route/route_utils.h index 19f14e7cdb2..5cac4fbb045 100644 --- a/vpr/src/route/route_utils.h +++ b/vpr/src/route/route_utils.h @@ -143,7 +143,7 @@ vtr::vector>> set_net /** Wrapper for create_rr_graph() with extra checks */ void try_graph(int width_fac, const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, const std::vector& directs, diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index d87fd754df1..28c553c5d8f 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -245,7 +245,7 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src void alloc_routing_structs(const t_chan_width& chan_width, const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, bool is_flat) { @@ -257,7 +257,7 @@ void alloc_routing_structs(const t_chan_width& chan_width, if (router_opts.route_type == GLOBAL) { graph_type = e_graph_type::GLOBAL; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } create_rr_graph(graph_type, diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h index f137e143df9..082349a9a07 100644 --- a/vpr/src/route/router_delay_profiling.h +++ b/vpr/src/route/router_delay_profiling.h @@ -54,7 +54,7 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src void alloc_routing_structs(const t_chan_width& chan_width, const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, bool is_flat); diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index a6219c5b896..718a21ca9fb 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -737,7 +737,7 @@ static void build_intra_cluster_rr_graph(e_graph_type graph_type, * @param det_routing_arch Contain the information from architecture file * @param load_rr_graph Indicate whether the RR graph is loaded from a file */ -static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, +static int get_delayless_switch_id(const t_det_routing_arch& det_routing_arch, bool load_rr_graph); /******************* Subroutine definitions *******************************/ @@ -746,7 +746,7 @@ void create_rr_graph(e_graph_type graph_type, const std::vector& block_types, const DeviceGrid& grid, const t_chan_width& nodes_per_chan, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, const std::vector& segment_inf, const t_router_opts& router_opts, const std::vector& directs, @@ -756,7 +756,7 @@ void create_rr_graph(e_graph_type graph_type, auto& mutable_device_ctx = g_vpr_ctx.mutable_device(); bool echo_enabled = getEchoEnabled() && isEchoFileEnabled(E_ECHO_RR_GRAPH_INDEXED_DATA); const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); - bool load_rr_graph = !det_routing_arch->read_rr_graph_filename.empty(); + bool load_rr_graph = !det_routing_arch.read_rr_graph_filename.empty(); if (channel_widths_unchanged(device_ctx.chan_width, nodes_per_chan) && !device_ctx.rr_graph.empty()) { //No change in channel width, so skip re-building RR graph @@ -768,7 +768,7 @@ void create_rr_graph(e_graph_type graph_type, } } else { if (load_rr_graph) { - if (device_ctx.loaded_rr_graph_filename != det_routing_arch->read_rr_graph_filename) { + if (device_ctx.loaded_rr_graph_filename != det_routing_arch.read_rr_graph_filename) { free_rr_graph(); load_rr_file(&mutable_device_ctx.rr_graph_builder, @@ -783,9 +783,9 @@ void create_rr_graph(e_graph_type graph_type, device_ctx.arch, &mutable_device_ctx.chan_width, router_opts.base_cost_type, - &det_routing_arch->wire_to_rr_ipin_switch, - &det_routing_arch->wire_to_arch_ipin_switch_between_dice, - det_routing_arch->read_rr_graph_filename.c_str(), + &det_routing_arch.wire_to_rr_ipin_switch, + &det_routing_arch.wire_to_arch_ipin_switch_between_dice, + det_routing_arch.read_rr_graph_filename.c_str(), &mutable_device_ctx.loaded_rr_graph_filename, router_opts.read_rr_edge_metadata, router_opts.do_check_rr_graph, @@ -804,36 +804,36 @@ void create_rr_graph(e_graph_type graph_type, block_types, grid, nodes_per_chan, - det_routing_arch->switch_block_type, - det_routing_arch->Fs, - det_routing_arch->switchblocks, + det_routing_arch.switch_block_type, + det_routing_arch.Fs, + det_routing_arch.switchblocks, segment_inf, - det_routing_arch->global_route_switch, - det_routing_arch->wire_to_arch_ipin_switch, - det_routing_arch->wire_to_arch_ipin_switch_between_dice, + det_routing_arch.global_route_switch, + det_routing_arch.wire_to_arch_ipin_switch, + det_routing_arch.wire_to_arch_ipin_switch_between_dice, router_opts.custom_3d_sb_fanin_fanout, - det_routing_arch->delayless_switch, - det_routing_arch->R_minW_nmos, - det_routing_arch->R_minW_pmos, + det_routing_arch.delayless_switch, + det_routing_arch.R_minW_nmos, + det_routing_arch.R_minW_pmos, router_opts.base_cost_type, router_opts.clock_modeling, directs, - &det_routing_arch->wire_to_rr_ipin_switch, + &det_routing_arch.wire_to_rr_ipin_switch, is_flat, Warnings, router_opts.route_verbosity); } // Check if there is an edge override file to read and that it is not already loaded. - if (!det_routing_arch->read_rr_edge_override_filename.empty() - && det_routing_arch->read_rr_edge_override_filename != device_ctx.loaded_rr_edge_override_filename) { + if (!det_routing_arch.read_rr_edge_override_filename.empty() + && det_routing_arch.read_rr_edge_override_filename != device_ctx.loaded_rr_edge_override_filename) { - load_rr_edge_delay_overrides(det_routing_arch->read_rr_edge_override_filename, + load_rr_edge_delay_overrides(det_routing_arch.read_rr_edge_override_filename, mutable_device_ctx.rr_graph_builder, device_ctx.rr_graph); // Remember the loaded filename to avoid reloading it before the RR graph is cleared. - mutable_device_ctx.loaded_rr_edge_override_filename = det_routing_arch->read_rr_edge_override_filename; + mutable_device_ctx.loaded_rr_edge_override_filename = det_routing_arch.read_rr_edge_override_filename; } } @@ -845,8 +845,8 @@ void create_rr_graph(e_graph_type graph_type, block_types, device_ctx.rr_graph, delayless_switch, - det_routing_arch->R_minW_nmos, - det_routing_arch->R_minW_pmos, + det_routing_arch.R_minW_nmos, + det_routing_arch.R_minW_pmos, mutable_device_ctx.rr_graph_builder, is_flat, load_rr_graph); @@ -876,7 +876,7 @@ void create_rr_graph(e_graph_type graph_type, // When this function is called in any stage other than routing, the is_flat flag passed to this function is false, regardless of the flag passed // through command line. So, the graph corresponding to global resources will be created and written down to file if needed. During routing, if flat-routing // is enabled, intra-cluster resources will be added to the graph, but this new bigger graph will not be written down. - if (!det_routing_arch->write_rr_graph_filename.empty() && !is_flat) { + if (!det_routing_arch.write_rr_graph_filename.empty() && !is_flat) { write_rr_graph(&mutable_device_ctx.rr_graph_builder, &mutable_device_ctx.rr_graph, device_ctx.physical_tile_types, @@ -886,7 +886,7 @@ void create_rr_graph(e_graph_type graph_type, device_ctx.arch_switch_inf, device_ctx.arch, &mutable_device_ctx.chan_width, - det_routing_arch->write_rr_graph_filename.c_str(), + det_routing_arch.write_rr_graph_filename.c_str(), echo_enabled, echo_file_name, is_flat); @@ -1600,7 +1600,7 @@ static void build_intra_cluster_rr_graph(e_graph_type graph_type, is_flat); } -static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, +static int get_delayless_switch_id(const t_det_routing_arch& det_routing_arch, bool load_rr_graph) { const auto& device_ctx = g_vpr_ctx.device(); int delayless_switch = OPEN; @@ -1614,7 +1614,7 @@ static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, } } } else { - delayless_switch = static_cast(det_routing_arch->delayless_switch); + delayless_switch = static_cast(det_routing_arch.delayless_switch); } return delayless_switch; diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index 283da1a296c..f0ea08e4302 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -24,7 +24,7 @@ void create_rr_graph(e_graph_type graph_type, const std::vector& block_types, const DeviceGrid& grid, const t_chan_width& nodes_per_chan, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, const std::vector& segment_inf, const t_router_opts& router_opts, const std::vector& directs, From 6d2dc5301e6b69624f0ab51a1b2919d5e699b585 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sat, 10 May 2025 19:55:39 -0400 Subject: [PATCH 101/176] t_chan_width_dist ---> const t_chan_width_dist& --- vpr/src/place/delay_model/PlacementDelayModelCreator.cpp | 2 +- vpr/src/place/delay_model/PlacementDelayModelCreator.h | 2 +- vpr/src/place/place.cpp | 2 +- vpr/src/place/place.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp index 8cdffa1029e..1ec59f4ed10 100644 --- a/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp @@ -29,7 +29,7 @@ PlacementDelayModelCreator::create_delay_model(const t_placer_opts& placer_opts, const Netlist<>& net_list, t_det_routing_arch& det_routing_arch, std::vector& segment_inf, - t_chan_width_dist chan_width_dist, + const t_chan_width_dist& chan_width_dist, const std::vector& directs, bool is_flat) { vtr::ScopedStartFinishTimer timer("Computing placement delta delay look-up"); diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.h b/vpr/src/place/delay_model/PlacementDelayModelCreator.h index 855281d77f2..c003d85e034 100644 --- a/vpr/src/place/delay_model/PlacementDelayModelCreator.h +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.h @@ -24,7 +24,7 @@ class PlacementDelayModelCreator { const Netlist<>& net_list, t_det_routing_arch& det_routing_arch, std::vector& segment_inf, - t_chan_width_dist chan_width_dist, + const t_chan_width_dist& chan_width_dist, const std::vector& directs, bool is_flat); }; diff --git a/vpr/src/place/place.cpp b/vpr/src/place/place.cpp index b681ddc0a36..39d6cd24f82 100644 --- a/vpr/src/place/place.cpp +++ b/vpr/src/place/place.cpp @@ -33,7 +33,7 @@ void try_place(const Netlist<>& net_list, const t_router_opts& router_opts, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, - t_chan_width_dist chan_width_dist, + const t_chan_width_dist& chan_width_dist, t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, diff --git a/vpr/src/place/place.h b/vpr/src/place/place.h index 29e202a4e0b..235dbc0042c 100644 --- a/vpr/src/place/place.h +++ b/vpr/src/place/place.h @@ -10,7 +10,7 @@ void try_place(const Netlist<>& net_list, const t_router_opts& router_opts, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, - t_chan_width_dist chan_width_dist, + const t_chan_width_dist& chan_width_dist, t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, From 56be3371552859fcc3d028c1e7023bb773816cfb Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sat, 10 May 2025 19:57:51 -0400 Subject: [PATCH 102/176] make format --- vpr/src/power/power.h | 1 - 1 file changed, 1 deletion(-) diff --git a/vpr/src/power/power.h b/vpr/src/power/power.h index 192245de3b4..36630921b03 100644 --- a/vpr/src/power/power.h +++ b/vpr/src/power/power.h @@ -313,4 +313,3 @@ bool power_uninit(); /* Top-Level Function */ e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, const t_arch* arch, const t_det_routing_arch& routing_arch); - From 3484443d41c8fc63575070aa19a2f0858ca43d54 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Sun, 11 May 2025 20:42:37 -0400 Subject: [PATCH 103/176] fix compilation error in route_diag by passing det_routing_arch argument by reference instead of pointer --- utils/route_diag/src/main.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index 7160794cc7d..e9a8ccd3a87 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -292,7 +292,7 @@ int main(int argc, const char **argv) { alloc_routing_structs(chan_width, vpr_setup.RouterOpts, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, Arch.directs, is_flat); From 909e3f22551e38f52f4c0fca29dc263c58f785d0 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 06:02:05 -0400 Subject: [PATCH 104/176] [task] add generate_net_timing_report to timing report strong test --- .../strong_timing_report_detail/config/config.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt index 79ab5b22460..2ea1502528b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt @@ -24,7 +24,7 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common = -starting_stage vpr +script_params_common = -starting_stage vpr --generate_net_timing_report on script_params_list_add=--timing_report_detail netlist script_params_list_add=--timing_report_detail aggregated script_params_list_add=--timing_report_detail detailed From 616cc8d7ad35b2fcf3f67ca600c430f74eb149c0 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 06:12:52 -0400 Subject: [PATCH 105/176] [doc] add doc for generating _net_timing_report command line option --- doc/src/vpr/command_line_usage.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 61dd775abb9..cc6ef935b0f 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1517,6 +1517,19 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout * `swns` - setup Worst Negative Slack (sWNS) [ns] * `stns` - Setup Total Negative Slack (sTNS) [ns] + +.. option:: --generate_net_timing_report {on | off} + + Generates a net timing report for each net in the design. For each net, the timing information written in the following format: + + .. code-block:: none + + netname : Fanout : bounding_box_xmin,bounding_box_ymin,bounding_box_xmax,bounding_box_ymax : source_instance : + : + : ... + + **Default:** ``off`` + .. option:: --route_verbosity Controls the verbosity of routing output. From ebcf74bf921707b638f10d0bb3beae87fa692fb5 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 06:14:38 -0400 Subject: [PATCH 106/176] [vpr][timing] update generate_net_timing_report comment --- vpr/src/analysis/timing_reports.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index e127335849b..e5ed5f307db 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -24,7 +24,8 @@ void generate_hold_timing_stats(const std::string& prefix, /** * @brief Generates timing information for each net in atom netlist. For each net, the timing information * is reported in the following format: - * netname : Fanout : source_instance : + * netname : Fanout : bounding_box_xmin,bounding_box_ymin,bounding_box_xmax,bounding_box_ymax: + * source_instance : * : * : ... * From dcbe1b350c7441dbd879d7a4f4d5d80c7fecef3d Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 09:07:26 -0400 Subject: [PATCH 107/176] [vpr][timing] add get_net_bounding_box --- vpr/src/analysis/timing_reports.cpp | 112 +++++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 0062aff5d81..1b8baaf375e 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -4,6 +4,7 @@ #include #include "timing_reports.h" +#include "rr_graph.h" #include "tatum/TimingReporter.hpp" @@ -16,6 +17,113 @@ #include "VprTimingGraphResolver.h" +/** + * @brief Get the bounding box of a net. + * If the net is completely absorbed into a cluster block, return the bounding box of the cluster block. + * Otherwise, return the bounding box of the net's route tree. + * If a net is not routed, bounding box is returned with default values (OPEN). + * + * @param atom_net_id The id of the atom net to get the bounding box of. + */ +static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { + const auto& route_trees = g_vpr_ctx.routing().route_trees; + const auto& rr_graph = g_vpr_ctx.device().rr_graph; + const bool flat_router = g_vpr_ctx.routing().is_flat; + + // Lambda to get the bounding box of a route tree + auto route_tree_bb = [](const RRGraphView& rr_graph, const RouteTree& route_tree) { + t_bb bb; + + // Set the initial bounding box to the root node's location + RRNodeId route_tree_root = route_tree.root().inode; + bb.xmin = rr_graph.node_xlow(route_tree_root); + bb.xmax = rr_graph.node_xhigh(route_tree_root); + bb.ymin = rr_graph.node_ylow(route_tree_root); + bb.ymax = rr_graph.node_yhigh(route_tree_root); + bb.layer_min = rr_graph.node_layer(route_tree_root); + bb.layer_max = rr_graph.node_layer(route_tree_root); + + // Iterate over all nodes in the route tree and update the bounding box + for (auto& rt_node : route_tree.all_nodes()) { + RRNodeId inode = rt_node.inode; + if (rr_graph.node_xlow(inode) < bb.xmin) + bb.xmin = rr_graph.node_xlow(inode); + if (rr_graph.node_xhigh(inode) > bb.xmax) + bb.xmax = rr_graph.node_xhigh(inode); + if (rr_graph.node_ylow(inode) < bb.ymin) + bb.ymin = rr_graph.node_ylow(inode); + if (rr_graph.node_layer(inode) > bb.layer_min) + bb.layer_min = rr_graph.node_layer(inode); + if (rr_graph.node_layer(inode) > bb.layer_max) + bb.layer_max = rr_graph.node_layer(inode); + } + return bb; + }; + + if (flat_router) { + // If flat router is used, route tree data structure can be used + // directly to get the bounding box of the net + const auto& route_tree = route_trees[atom_net_id]; + if (!route_tree) + return t_bb(); + return route_tree_bb(rr_graph, *route_tree); + } else { + // If two-stage router is used, we need to first get the cluster net id + // corresponding to the atom net and then get the bounding box of the net + // from the route tree. If the net is completely absorbed into a cluster block, + const auto& atom_lookup = g_vpr_ctx.atom().lookup(); + const auto& cluster_net_id = atom_lookup.clb_nets(atom_net_id); + std::vector bbs; + t_bb max_bb; + // There maybe multiple cluster nets corresponding to a single atom net. + // We iterate over all cluster nets and the final bounding box is the union + // of all cluster net bounding boxes + if (cluster_net_id != vtr::nullopt) { + for (const auto& clb_net_id : *cluster_net_id) { + const auto& route_tree = route_trees[clb_net_id]; + if (!route_tree) + continue; + bbs.push_back(route_tree_bb(rr_graph, *route_tree)); + } + // Assign the first cluster net's bounding box to the final bounding box + // and then iteratively update it with the union of bounding boxes of + // all cluster nets + max_bb = bbs[0]; + for (size_t i = 1; i < bbs.size(); ++i) { + max_bb.xmin = std::min(bbs[i].xmin, max_bb.xmin); + max_bb.xmax = std::max(bbs[i].xmax, max_bb.xmax); + max_bb.ymin = std::min(bbs[i].ymin, max_bb.ymin); + max_bb.ymax = std::max(bbs[i].ymax, max_bb.ymax); + max_bb.layer_min = std::min(bbs[i].layer_min, max_bb.layer_min); + max_bb.layer_max = std::max(bbs[i].layer_max, max_bb.layer_max); + } + } else { + // If there is no cluster net corresponding to the atom net, + // it means the net is completely absorbed into a cluster block. + // In that case, we set the bounding box the cluster block's bounding box + const auto& atom_ctx = g_vpr_ctx.atom(); + const auto& atom_nlist = atom_ctx.netlist(); + AtomPinId source_pin = atom_nlist.net_driver(atom_net_id); + + AtomBlockId atom_block = atom_nlist.pin_block(source_pin); + VTR_ASSERT(atom_block != AtomBlockId::INVALID()); + ClusterBlockId cluster_block = atom_lookup.atom_clb(atom_block); + VTR_ASSERT(cluster_block != ClusterBlockId::INVALID()); + + const t_pl_loc& cluster_block_loc = g_vpr_ctx.placement().block_locs()[cluster_block].loc; + const auto& grid = g_vpr_ctx.device().grid; + vtr::Rect tile_bb = grid.get_tile_bb({cluster_block_loc.x, cluster_block_loc.y, cluster_block_loc.layer}); + const int block_layer = cluster_block_loc.layer; + return t_bb(tile_bb.xmin(), + tile_bb.xmax(), + tile_bb.ymin(), + tile_bb.ymax(), + block_layer, + block_layer); + } + } +} + void generate_setup_timing_stats(const std::string& prefix, const SetupTimingInfo& timing_info, const AnalysisDelayCalculator& delay_calc, @@ -106,7 +214,9 @@ void generate_net_timing_report(const std::string& prefix, VTR_ASSERT(tg_source_node.is_valid()); const size_t fanout = atom_netlist.net_sinks(net).size(); - os << net_name << " : " << fanout << " : " << atom_netlist.pin_name(source_pin).c_str() << " " << source_pin_slack << " : "; + os << net_name << " : " + << fanout << " : " + << atom_netlist.pin_name(source_pin).c_str() << " " << source_pin_slack << " : "; /* Iterate over all fanout pins and print their timing information */ for (size_t net_pin_index = 1; net_pin_index <= fanout; ++net_pin_index) { From 548d53abc7280d2a12327d367d41fce0754e42b5 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 09:12:14 -0400 Subject: [PATCH 108/176] [vpr][timing] add net bounding box to the report --- vpr/src/analysis/timing_reports.cpp | 6 +++++- vpr/src/analysis/timing_reports.h | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 1b8baaf375e..110e63f9cd1 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -191,7 +191,9 @@ void generate_net_timing_report(const std::string& prefix, os << "# Version: " << vtr::VERSION << std::endl; os << "# Revision: " << vtr::VCS_REVISION << std::endl; os << "# For each net, the timing information is reported in the following format:" << std::endl; - os << "# netname : Fanout : source_instance : " + os << "# netname : Fanout : " + << "bounding_box_xmin,bounding_box_ymin,bounding_box_xmax,bounding_box_ymax : " + << "source_instance : " << " : " << " : ..." << std::endl; @@ -214,8 +216,10 @@ void generate_net_timing_report(const std::string& prefix, VTR_ASSERT(tg_source_node.is_valid()); const size_t fanout = atom_netlist.net_sinks(net).size(); + const auto& net_bb = get_net_bounding_box(net); os << net_name << " : " << fanout << " : " + << net_bb.xmin << "," << net_bb.ymin << "," << net_bb.xmax << "," << net_bb.ymax << " : " << atom_netlist.pin_name(source_pin).c_str() << " " << source_pin_slack << " : "; /* Iterate over all fanout pins and print their timing information */ diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index e5ed5f307db..44efb563439 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -24,7 +24,7 @@ void generate_hold_timing_stats(const std::string& prefix, /** * @brief Generates timing information for each net in atom netlist. For each net, the timing information * is reported in the following format: - * netname : Fanout : bounding_box_xmin,bounding_box_ymin,bounding_box_xmax,bounding_box_ymax: + * netname : Fanout : bounding_box_xmin,bounding_box_ymin,bounding_box_xmax,bounding_box_ymax : * source_instance : * : * : ... From c4b781ee3eb735a3c9e6290ffaadd40fdcfdb86d Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 11:40:18 -0400 Subject: [PATCH 109/176] [test] add test for net timing report --- .../strong_timing_report_detail/config/config.txt | 3 +++ .../config/golden_results.txt | 11 +++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt index 2ea1502528b..ae8e519b4a4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt @@ -28,3 +28,6 @@ script_params_common = -starting_stage vpr --generate_net_timing_report on script_params_list_add=--timing_report_detail netlist script_params_list_add=--timing_report_detail aggregated script_params_list_add=--timing_report_detail detailed +script_params_list_add=--timing_report_detail netlist --flat_routing on +script_params_list_add=--timing_report_detail aggregated --flat_routing on +script_params_list_add=--timing_report_detail detailed --flat_routing on diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index a5bee947840..f82233e2459 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.50 vpr 67.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68660 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.6443e-05 3.2529e-05 0.000274786 0.000214986 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00211509 0.0019009 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0017763 0.00169895 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.49 vpr 67.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8016e-05 3.4218e-05 0.000283686 0.000224427 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0022472 0.00206472 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00179634 0.00171755 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.51 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68932 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 6.2523e-05 4.6425e-05 0.000366128 0.000294026 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00236124 0.00216436 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00189537 0.00181322 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.37 vpr 65.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66624 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 24 21 30 9 19 2 65.1 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.4867e-05 1.6785e-05 0.000178305 0.000138626 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0013303 0.00121195 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0010544 0.00100577 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.38 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66628 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 24 21 30 9 19 2 65.1 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5617e-05 1.7506e-05 0.000177134 0.000138581 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0012973 0.00118019 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00105506 0.00100757 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.41 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66628 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.00 24 21 30 9 19 2 65.1 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5232e-05 1.7334e-05 0.000170999 0.000134182 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00125289 0.00113927 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00129683 0.00123 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist_--flat_routing_on 0.81 vpr 70.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72112 5 3 11 14 2 9 10 4 4 16 clb auto 30.9 MiB 0.01 24 21 30 9 19 2 70.4 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.5406e-05 1.7598e-05 0.000175321 0.000137685 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.25 0.00131841 0.00118136 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.12 0.00 0.00 0.11 0.00 0.00103786 0.000967845 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated_--flat_routing_on 0.81 vpr 70.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72492 5 3 11 14 2 9 10 4 4 16 clb auto 30.9 MiB 0.01 24 21 30 9 19 2 70.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5095e-05 1.6967e-05 0.000167727 0.000130306 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.26 0.00127606 0.0011399 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.12 0.00 0.00 0.12 0.00 0.00102446 0.000963839 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed_--flat_routing_on 0.85 vpr 70.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72112 5 3 11 14 2 9 10 4 4 16 clb auto 30.9 MiB 0.01 24 21 30 9 19 2 70.4 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5982e-05 1.7909e-05 0.000172322 0.000134495 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.26 0.00129831 0.00116036 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.13 0.00 0.00 0.12 0.00 0.00101752 0.000959208 From 755800528fc346f3f6db8554d9a3ab8d1a670192 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 11:41:31 -0400 Subject: [PATCH 110/176] [doc] update doc with new format to net timing report --- doc/src/vpr/command_line_usage.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index cc6ef935b0f..608d0bbf1d5 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1524,7 +1524,9 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout .. code-block:: none - netname : Fanout : bounding_box_xmin,bounding_box_ymin,bounding_box_xmax,bounding_box_ymax : source_instance : + netname : Fanout : + (bounding_box_xmin,bounding_box_ymin,bounding_box_layer_min),(bounding_box_xmax,bounding_box_ymax,bounding_box_layer_max) : + source_instance : : : ... From b2e1530053f81db92067d1b0801af34d6cbedb92 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 11:43:23 -0400 Subject: [PATCH 111/176] [vpr][analysis] fix net timing report bugs + including layer min/max of bb --- vpr/src/analysis/timing_reports.cpp | 19 ++++++++++++++----- vpr/src/analysis/timing_reports.h | 3 ++- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 110e63f9cd1..fec1d9bdef2 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -28,7 +28,6 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { const auto& route_trees = g_vpr_ctx.routing().route_trees; const auto& rr_graph = g_vpr_ctx.device().rr_graph; - const bool flat_router = g_vpr_ctx.routing().is_flat; // Lambda to get the bounding box of a route tree auto route_tree_bb = [](const RRGraphView& rr_graph, const RouteTree& route_tree) { @@ -46,13 +45,18 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { // Iterate over all nodes in the route tree and update the bounding box for (auto& rt_node : route_tree.all_nodes()) { RRNodeId inode = rt_node.inode; + if (rr_graph.node_xlow(inode) < bb.xmin) bb.xmin = rr_graph.node_xlow(inode); if (rr_graph.node_xhigh(inode) > bb.xmax) bb.xmax = rr_graph.node_xhigh(inode); + if (rr_graph.node_ylow(inode) < bb.ymin) bb.ymin = rr_graph.node_ylow(inode); - if (rr_graph.node_layer(inode) > bb.layer_min) + if (rr_graph.node_yhigh(inode) > bb.ymax) + bb.ymax = rr_graph.node_yhigh(inode); + + if (rr_graph.node_layer(inode) < bb.layer_min) bb.layer_min = rr_graph.node_layer(inode); if (rr_graph.node_layer(inode) > bb.layer_max) bb.layer_max = rr_graph.node_layer(inode); @@ -60,7 +64,7 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { return bb; }; - if (flat_router) { + if (g_vpr_ctx.routing().is_flat) { // If flat router is used, route tree data structure can be used // directly to get the bounding box of the net const auto& route_tree = route_trees[atom_net_id]; @@ -85,6 +89,9 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { continue; bbs.push_back(route_tree_bb(rr_graph, *route_tree)); } + if (bbs.empty()) { + return t_bb(); + } // Assign the first cluster net's bounding box to the final bounding box // and then iteratively update it with the union of bounding boxes of // all cluster nets @@ -97,6 +104,7 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { max_bb.layer_min = std::min(bbs[i].layer_min, max_bb.layer_min); max_bb.layer_max = std::max(bbs[i].layer_max, max_bb.layer_max); } + return max_bb; } else { // If there is no cluster net corresponding to the atom net, // it means the net is completely absorbed into a cluster block. @@ -192,7 +200,7 @@ void generate_net_timing_report(const std::string& prefix, os << "# Revision: " << vtr::VCS_REVISION << std::endl; os << "# For each net, the timing information is reported in the following format:" << std::endl; os << "# netname : Fanout : " - << "bounding_box_xmin,bounding_box_ymin,bounding_box_xmax,bounding_box_ymax : " + << "(bounding_box_xmin,bounding_box_ymin,bounding_box_layermin),(bounding_box_xmax,bounding_box_ymax,bounding_box_layermax) : " << "source_instance : " << " : " << " : ..." @@ -219,7 +227,8 @@ void generate_net_timing_report(const std::string& prefix, const auto& net_bb = get_net_bounding_box(net); os << net_name << " : " << fanout << " : " - << net_bb.xmin << "," << net_bb.ymin << "," << net_bb.xmax << "," << net_bb.ymax << " : " + << "(" << net_bb.xmin << "," << net_bb.ymin << "," << net_bb.layer_min << "),(" + << net_bb.xmax << "," << net_bb.ymax << "," << net_bb.layer_max << ") : " << atom_netlist.pin_name(source_pin).c_str() << " " << source_pin_slack << " : "; /* Iterate over all fanout pins and print their timing information */ diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index 44efb563439..0aec721d76a 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -24,7 +24,8 @@ void generate_hold_timing_stats(const std::string& prefix, /** * @brief Generates timing information for each net in atom netlist. For each net, the timing information * is reported in the following format: - * netname : Fanout : bounding_box_xmin,bounding_box_ymin,bounding_box_xmax,bounding_box_ymax : + * netname : Fanout : + * (bounding_box_xmin,bounding_box_ymin,bounding_box_layermin),(bounding_box_xmax,bounding_box_ymax,bounding_box_layermax) : * source_instance : * : * : ... From b625d58bdd03e9541f93942504369da2a3b1e9b0 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 11:44:20 -0400 Subject: [PATCH 112/176] make format --- vpr/src/analysis/timing_reports.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index fec1d9bdef2..bbd4a056082 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -72,8 +72,8 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { return t_bb(); return route_tree_bb(rr_graph, *route_tree); } else { - // If two-stage router is used, we need to first get the cluster net id - // corresponding to the atom net and then get the bounding box of the net + // If two-stage router is used, we need to first get the cluster net id + // corresponding to the atom net and then get the bounding box of the net // from the route tree. If the net is completely absorbed into a cluster block, const auto& atom_lookup = g_vpr_ctx.atom().lookup(); const auto& cluster_net_id = atom_lookup.clb_nets(atom_net_id); @@ -225,8 +225,8 @@ void generate_net_timing_report(const std::string& prefix, const size_t fanout = atom_netlist.net_sinks(net).size(); const auto& net_bb = get_net_bounding_box(net); - os << net_name << " : " - << fanout << " : " + os << net_name << " : " + << fanout << " : " << "(" << net_bb.xmin << "," << net_bb.ymin << "," << net_bb.layer_min << "),(" << net_bb.xmax << "," << net_bb.ymax << "," << net_bb.layer_max << ") : " << atom_netlist.pin_name(source_pin).c_str() << " " << source_pin_slack << " : "; From 40522e535f99fe43cb9c3ee1ffd2026b08a69bae Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 12 May 2025 12:24:19 -0400 Subject: [PATCH 113/176] [vpr][analysis] capture vars by reference in lambda --- vpr/src/analysis/timing_reports.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index bbd4a056082..36cb99c0207 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -30,7 +30,7 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { const auto& rr_graph = g_vpr_ctx.device().rr_graph; // Lambda to get the bounding box of a route tree - auto route_tree_bb = [](const RRGraphView& rr_graph, const RouteTree& route_tree) { + auto route_tree_bb = [&](const RouteTree& route_tree) { t_bb bb; // Set the initial bounding box to the root node's location @@ -70,7 +70,7 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { const auto& route_tree = route_trees[atom_net_id]; if (!route_tree) return t_bb(); - return route_tree_bb(rr_graph, *route_tree); + return route_tree_bb(*route_tree); } else { // If two-stage router is used, we need to first get the cluster net id // corresponding to the atom net and then get the bounding box of the net @@ -87,7 +87,7 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { const auto& route_tree = route_trees[clb_net_id]; if (!route_tree) continue; - bbs.push_back(route_tree_bb(rr_graph, *route_tree)); + bbs.push_back(route_tree_bb(*route_tree)); } if (bbs.empty()) { return t_bb(); From 16140e6d1730c9d48d0a38e4a8f68d63a7274616 Mon Sep 17 00:00:00 2001 From: Rongbo Zhang Date: Mon, 10 Feb 2025 20:08:13 -0500 Subject: [PATCH 114/176] [packer] Changing the vector of candidate molecules into LazyPopUniquePriorityQueue. The class LazyPopUniquePriorityQueue is a priority queue that allows for lazy deletion of elements. It is implemented using a vector and 2 sets, one set keeps track of the elements in the queue, and the other set keeps track of the elements that are pending deletion. The queue is sorted by the sort-value(SV) of the elements, and the elements are stored in a vector. The set is used to keep track of the elements that are pending deletion, so that they can be removed from the queue when they are popped. The class definiation can be found in vpr/src/util/lazy_pop_unique_priority_queue.h Currently, the class supports the following functions: LazyPopUniquePriorityQueue::push(): Pushes a key-sort-value (K-SV) pair into the priority queue and adds the key to the tracking set. LazyPopUniquePriorityQueue::pop(): Returns the K-SV pair with the highest SV whose key is not pending deletion. LazyPopUniquePriorityQueue::remove(): Removes an element from the priority queue immediately. LazyPopUniquePriorityQueue::remove_at_pop_time(): Removes an element from the priority queue when it is popped. LazyPopUniquePriorityQueue::empty(): Returns whether the queue is empty. LazyPopUniquePriorityQueue::clear(): Clears the priority queue vector and the tracking sets. LazyPopUniquePriorityQueue::size(): Returns the number of elements in the queue. LazyPopUniquePriorityQueue::contains(): Returns true if the key is in the queue, false otherwise. --- vpr/src/pack/greedy_candidate_selector.cpp | 131 ++++------- vpr/src/pack/greedy_candidate_selector.h | 35 ++- vpr/src/util/lazy_pop_unique_priority_queue.h | 216 ++++++++++++++++++ 3 files changed, 285 insertions(+), 97 deletions(-) create mode 100644 vpr/src/util/lazy_pop_unique_priority_queue.h diff --git a/vpr/src/pack/greedy_candidate_selector.cpp b/vpr/src/pack/greedy_candidate_selector.cpp index d4579a45554..0ae3972140b 100644 --- a/vpr/src/pack/greedy_candidate_selector.cpp +++ b/vpr/src/pack/greedy_candidate_selector.cpp @@ -64,7 +64,6 @@ static void add_molecule_to_pb_stats_candidates( PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, t_logical_block_type_ptr cluster_type, - int max_queue_size, AttractionInfo& attraction_groups, const Prepacker& prepacker, const AtomNetlist& atom_netlist, @@ -219,13 +218,11 @@ ClusterGainStats GreedyCandidateSelector::create_cluster_gain_stats( // Initialize the cluster gain stats. ClusterGainStats cluster_gain_stats; cluster_gain_stats.seed_molecule_id = cluster_seed_mol_id; - cluster_gain_stats.num_feasible_blocks = NOT_VALID; cluster_gain_stats.has_done_connectivity_and_timing = false; - // TODO: The reason this is being resized and not reserved is due to legacy - // code which should be updated. - cluster_gain_stats.feasible_blocks.resize(packer_opts_.feasible_block_array_size); - for (int i = 0; i < packer_opts_.feasible_block_array_size; i++) - cluster_gain_stats.feasible_blocks[i] = PackMoleculeId::INVALID(); + cluster_gain_stats.initial_search_for_feasible_blocks = true; + cluster_gain_stats.num_candidates_proposed = 0; + cluster_gain_stats.candidates_propose_limit = packer_opts_.feasible_block_array_size; + cluster_gain_stats.feasible_blocks.clear(); cluster_gain_stats.tie_break_high_fanout_net = AtomNetId::INVALID(); cluster_gain_stats.explore_transitive_fanout = true; @@ -288,8 +285,10 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( AttractGroupId atom_grp_id = attraction_groups.get_atom_attraction_group(blk_id); /* reset list of feasible blocks */ - cluster_gain_stats.num_feasible_blocks = NOT_VALID; cluster_gain_stats.has_done_connectivity_and_timing = false; + cluster_gain_stats.initial_search_for_feasible_blocks = true; + cluster_gain_stats.num_candidates_proposed = 0; + cluster_gain_stats.feasible_blocks.clear(); /* TODO: Allow clusters to have more than one attraction group. */ if (atom_grp_id.is_valid()) cluster_gain_stats.attraction_grp_id = atom_grp_id; @@ -680,8 +679,8 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( */ // 1. Find unpacked molecules based on criticality and strong connectedness (connected by low fanout nets) with current cluster - if (cluster_gain_stats.num_feasible_blocks == NOT_VALID) { - cluster_gain_stats.num_feasible_blocks = 0; + if (cluster_gain_stats.initial_search_for_feasible_blocks) { + cluster_gain_stats.initial_search_for_feasible_blocks = false; add_cluster_molecule_candidates_by_connectivity_and_timing(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -691,7 +690,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( if (packer_opts_.prioritize_transitive_connectivity) { // 2. Find unpacked molecules based on transitive connections (eg. 2 hops away) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -699,7 +698,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } // 3. Find unpacked molecules based on weak connectedness (connected by high fanout nets) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -707,7 +706,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } } else { //Reverse order // 3. Find unpacked molecules based on weak connectedness (connected by high fanout nets) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -715,7 +714,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } // 2. Find unpacked molecules based on transitive connections (eg. 2 hops away) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -724,7 +723,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } // 4. Find unpacked molecules based on attraction group of the current cluster (if the cluster has an attraction group) - if (cluster_gain_stats.num_feasible_blocks == 0) { + if (cluster_gain_stats.feasible_blocks.empty()) { add_cluster_molecule_candidates_by_attraction_group(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -732,15 +731,25 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } /* Grab highest gain molecule */ - // If this was a vector, this would just be a pop_back. PackMoleculeId best_molecule = PackMoleculeId::INVALID(); - if (cluster_gain_stats.num_feasible_blocks > 0) { - cluster_gain_stats.num_feasible_blocks--; - int index = cluster_gain_stats.num_feasible_blocks; - best_molecule = cluster_gain_stats.feasible_blocks[index]; + // If there are feasible blocks being proposed and the number of suggestions did not reach the limit. + // Get the block with highest gain from the top of the priority queue. + if (!cluster_gain_stats.feasible_blocks.empty() && !cluster_gain_stats.current_stage_candidates_proposed_limit_reached()) { + best_molecule = cluster_gain_stats.feasible_blocks.pop().first; + VTR_ASSERT(best_molecule != PackMoleculeId::INVALID()); + cluster_gain_stats.num_candidates_proposed++; VTR_ASSERT(!cluster_legalizer.is_mol_clustered(best_molecule)); } + // If we have no feasible blocks, or we have reached the limit of number of pops, + // then we need to clear the feasible blocks list and reset the number of pops. + // This ensures that we can continue searching for feasible blocks for the remaining + // steps (2.transitive, 3.high fanout, 4.attraction group). + if (cluster_gain_stats.feasible_blocks.empty() || cluster_gain_stats.current_stage_candidates_proposed_limit_reached()) { + cluster_gain_stats.feasible_blocks.clear(); + cluster_gain_stats.num_candidates_proposed = 0; + } + // If we are allowing unrelated clustering and no molecule has been found, // get unrelated candidate for cluster. if (allow_unrelated_clustering_ && best_molecule == PackMoleculeId::INVALID()) { @@ -774,7 +783,9 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_connectivity_an LegalizationClusterId legalization_cluster_id, const ClusterLegalizer& cluster_legalizer, AttractionInfo& attraction_groups) { - cluster_gain_stats.explore_transitive_fanout = true; /* If no legal molecules found, enable exploration of molecules two hops away */ + + cluster_gain_stats.explore_transitive_fanout = true; /* If no legal molecules found, enable exploration of molecules two hops away */ + cluster_gain_stats.candidates_propose_limit = packer_opts_.feasible_block_array_size; // set the limit of candidates to propose for (AtomBlockId blk_id : cluster_gain_stats.marked_blocks) { // Get the molecule that contains this block. @@ -785,7 +796,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_connectivity_an add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - packer_opts_.feasible_block_array_size, attraction_groups, prepacker_, atom_netlist_, @@ -801,6 +811,7 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_transitive_conn AttractionInfo& attraction_groups) { //TODO: For now, only done by fan-out; should also consider fan-in cluster_gain_stats.explore_transitive_fanout = false; + cluster_gain_stats.candidates_propose_limit = std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_TRANSITIVE_EXPLORE); // set the limit of candidates to propose /* First time finding transitive fanout candidates therefore alloc and load them */ load_transitive_fanout_candidates(cluster_gain_stats, @@ -814,8 +825,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_transitive_conn add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - std::min(packer_opts_.feasible_block_array_size, - AAPACK_MAX_TRANSITIVE_EXPLORE), attraction_groups, prepacker_, atom_netlist_, @@ -834,6 +843,7 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn * related blocks */ AtomNetId net_id = cluster_gain_stats.tie_break_high_fanout_net; + cluster_gain_stats.candidates_propose_limit = std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_TRANSITIVE_EXPLORE); // set the limit of candidates to propose int count = 0; for (AtomPinId pin_id : atom_netlist_.net_pins(net_id)) { @@ -848,8 +858,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - std::min(packer_opts_.feasible_block_array_size, - AAPACK_MAX_HIGH_FANOUT_EXPLORE), attraction_groups, prepacker_, atom_netlist_, @@ -877,6 +885,7 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou * group molecules for candidate molecules. */ AttractGroupId grp_id = cluster_gain_stats.attraction_grp_id; + cluster_gain_stats.candidates_propose_limit = packer_opts_.feasible_block_array_size; // set the limit of candidates to propose if (grp_id == AttractGroupId::INVALID()) { return; } @@ -909,7 +918,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - packer_opts_.feasible_block_array_size, attraction_groups, prepacker_, atom_netlist_, @@ -931,7 +939,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - packer_opts_.feasible_block_array_size, attraction_groups, prepacker_, atom_netlist_, @@ -946,7 +953,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, t_logical_block_type_ptr cluster_type, - int max_queue_size, AttractionInfo& attraction_groups, const Prepacker& prepacker, const AtomNetlist& atom_netlist, @@ -996,45 +1002,18 @@ static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, } } - for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { - return; // already in queue, do nothing - } + // if already in queue, do nothing + if (cluster_gain_stats.feasible_blocks.contains(molecule_id)) { + return; } - if (cluster_gain_stats.num_feasible_blocks >= max_queue_size - 1) { - /* maximum size for array, remove smallest gain element and sort */ - if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(cluster_gain_stats.feasible_blocks[0], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { - /* single loop insertion sort */ - int j; - for (j = 0; j < cluster_gain_stats.num_feasible_blocks - 1; j++) { - if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) <= get_molecule_gain(cluster_gain_stats.feasible_blocks[j + 1], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { - cluster_gain_stats.feasible_blocks[j] = molecule_id; - break; - } else { - cluster_gain_stats.feasible_blocks[j] = cluster_gain_stats.feasible_blocks[j + 1]; - } - } - if (j == cluster_gain_stats.num_feasible_blocks - 1) { - cluster_gain_stats.feasible_blocks[j] = molecule_id; - } - } - } else { - /* Expand array and single loop insertion sort */ - int j; - for (j = cluster_gain_stats.num_feasible_blocks - 1; j >= 0; j--) { - if (get_molecule_gain(cluster_gain_stats.feasible_blocks[j], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { - cluster_gain_stats.feasible_blocks[j + 1] = cluster_gain_stats.feasible_blocks[j]; - } else { - cluster_gain_stats.feasible_blocks[j + 1] = molecule_id; - break; - } - } - if (j < 0) { - cluster_gain_stats.feasible_blocks[0] = molecule_id; - } - cluster_gain_stats.num_feasible_blocks++; + for (std::pair& feasible_block : cluster_gain_stats.feasible_blocks.heap) { + VTR_ASSERT_DEBUG(get_molecule_gain(feasible_block.first, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) == feasible_block.second); } + + // Insert the molecule into the queue sorted by gain, and maintain the heap property + float molecule_gain = get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx); + cluster_gain_stats.feasible_blocks.push(molecule_id, molecule_gain); } /* @@ -1045,27 +1024,7 @@ static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, */ static void remove_molecule_from_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats) { - int molecule_index; - bool found_molecule = false; - - //find the molecule index - for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { - found_molecule = true; - molecule_index = i; - } - } - - //if it is not in the array, return - if (found_molecule == false) { - return; - } - - //Otherwise, shift the molecules while removing the specified molecule - for (int j = molecule_index; j < cluster_gain_stats.num_feasible_blocks - 1; j++) { - cluster_gain_stats.feasible_blocks[j] = cluster_gain_stats.feasible_blocks[j + 1]; - } - cluster_gain_stats.num_feasible_blocks--; + cluster_gain_stats.feasible_blocks.remove_at_pop_time(molecule_id); } /* diff --git a/vpr/src/pack/greedy_candidate_selector.h b/vpr/src/pack/greedy_candidate_selector.h index a7af8d448b7..b39ad469b45 100644 --- a/vpr/src/pack/greedy_candidate_selector.h +++ b/vpr/src/pack/greedy_candidate_selector.h @@ -23,6 +23,7 @@ #include "vtr_vector.h" #include "vtr_random.h" #include "vtr_vector_map.h" +#include "lazy_pop_unique_priority_queue.h" // Forward declarations class AtomNetlist; @@ -97,13 +98,6 @@ struct ClusterGainStats { /// with the cluster. AttractGroupId attraction_grp_id; - /// @brief Array of feasible blocks to select from [0..max_array_size-1] - /// - /// Sorted in ascending gain order so that the last cluster_ctx.blocks is - /// the most desirable (this makes it easy to pop blocks off the list. - std::vector feasible_blocks; - int num_feasible_blocks; - /// @brief The flat placement location of this cluster. /// /// This is some function of the positions of the molecules which have been @@ -126,6 +120,25 @@ struct ClusterGainStats { /// set when the stats are created based on the primitive pb type /// of the seed. bool is_memory = false; + + /// @brief List of feasible block and its gain pairs. + /// The list is maintained in heap structure with the highest gain block + /// at the front. + LazyPopUniquePriorityQueue feasible_blocks; + + /// @brief Indicator for the initial search for feasible blocks. + bool initial_search_for_feasible_blocks; + + /// @brief Limit for the number of candiate proposed at each stage. + unsigned candidates_propose_limit; + + /// @brief Counter for the number of candiate proposed at each stage. + unsigned num_candidates_proposed; + + /// @brief Check if the current stage candidates proposed limit is reached. + bool current_stage_candidates_proposed_limit_reached() { + return num_candidates_proposed >= candidates_propose_limit; + } }; /** @@ -444,7 +457,7 @@ class GreedyCandidateSelector { // Cluster Candidate Selection // ===================================================================== // - /* + /** * @brief Add molecules with strong connectedness to the current cluster to * the list of feasible blocks. */ @@ -471,7 +484,7 @@ class GreedyCandidateSelector { LegalizationClusterId legalization_cluster_id, const ClusterLegalizer& cluster_legalizer); - /* + /** * @brief Add molecules based on transitive connections (eg. 2 hops away) * with current cluster. */ @@ -481,7 +494,7 @@ class GreedyCandidateSelector { const ClusterLegalizer& cluster_legalizer, AttractionInfo& attraction_groups); - /* + /** * @brief Add molecules based on weak connectedness (connected by high * fanout nets) with current cluster. */ @@ -491,7 +504,7 @@ class GreedyCandidateSelector { const ClusterLegalizer& cluster_legalizer, AttractionInfo& attraction_groups); - /* + /** * @brief If the current cluster being packed has an attraction group * associated with it (i.e. there are atoms in it that belong to an * attraction group), this routine adds molecules from the associated diff --git a/vpr/src/util/lazy_pop_unique_priority_queue.h b/vpr/src/util/lazy_pop_unique_priority_queue.h new file mode 100644 index 00000000000..d375daf19cd --- /dev/null +++ b/vpr/src/util/lazy_pop_unique_priority_queue.h @@ -0,0 +1,216 @@ +/** + * @file + * @author Rongbo Zhang + * @date 2025-04-23 + * @brief This file contains the definition of the LazyPopUniquePriorityQueue class. + * + * The class LazyPopUniquePriorityQueue is a priority queue that allows for lazy deletion of elements. + * The elements are pair of key and sort-value. The key is a unique value to identify the item, and the sort-value is used to sort the item. + * It is implemented using a vector and 2 sets, one set keeps track of the elements in the queue, and the other set keeps track of the elements that are pending deletion, + * so that they can be removed from the queue when they are popped. + * + * Currently, the class supports the following functions: + * LazyPopUniquePriorityQueue::push(): Pushes a key-sort-value (K-SV) pair into the priority queue and adds the key to the tracking set. + * LazyPopUniquePriorityQueue::pop(): Returns the K-SV pair with the highest SV whose key is not pending deletion. + * LazyPopUniquePriorityQueue::remove(): Removes an element from the priority queue immediately. + * LazyPopUniquePriorityQueue::remove_at_pop_time(): Removes an element from the priority queue when it is popped. + * LazyPopUniquePriorityQueue::empty(): Returns whether the queue is empty. + * LazyPopUniquePriorityQueue::clear(): Clears the priority queue vector and the tracking sets. + * LazyPopUniquePriorityQueue::size(): Returns the number of elements in the queue. + * LazyPopUniquePriorityQueue::contains(): Returns true if the key is in the queue, false otherwise. + */ + +#pragma once + +#include +#include +#include + +/** + * @brief Lazy Pop Unique Priority Queue + * + * This is a priority queue that is used to sort items which are identified by the key + * and sorted by the sort value. + * + * It uses a vector to store the key and sort value pair. + * It uses a set to store the keys that are in the vector for uniqueness checking + * and a set to store the delete pending keys which will be removed at pop time. + */ + +template +class LazyPopUniquePriorityQueue { + public: + /** @brief The custom comparsion struct for sorting the items in the priority queue. + * A less than comparison will put the item with the highest sort value to the front of the queue. + * A greater than comparison will put the item with the lowest sort value to the front of the queue. + */ + struct LazyPopUniquePriorityQueueCompare { + bool operator()(const std::pair& a, + const std::pair& b) const { + return a.second < b.second; + } + }; + + /// @brief The vector maintained as heap to store the key and sort value pair. + std::vector> heap; + + /// @brief The set to store the keys that are in the queue. This is used to ensure uniqueness + std::unordered_set content_set; + + /// @brief The set to store the delete pending item from the queue refered by the key. + std::unordered_set delete_pending_set; + + /** + * @brief Push the key and the sort value as a pair into the priority queue. + * + * @param key + * The unique key for the item that will be pushed onto the queue. + * @param value + * The sort value used for sorting the item. + */ + void push(T_key key, T_sort value) { + // Insert the key and sort value pair into the queue if it is not already present + if (content_set.find(key) != content_set.end()) { + // If the key is already in the queue, do nothing + return; + } + // Insert the key and sort value pair into the heap and track the key + // The new item is added to the end of the vector and then the push_heap function is call + // to push the item to the correct position in the heap structure. + heap.emplace_back(key, value); + std::push_heap(heap.begin(), heap.end(), LazyPopUniquePriorityQueueCompare()); + content_set.insert(key); + } + + /** + * @brief Pop the top item from the priority queue. + * + * @return The key and sort value pair. + */ + std::pair pop() { + std::pair top_pair; + while (heap.size() > 0) { + top_pair = heap.front(); + // Remove the key from the heap and the tracking set. + // The pop_heap function will move the top item in the heap structure to the end of the vector container. + // Then the pop_back function will remove the last item. + std::pop_heap(heap.begin(), heap.end(), LazyPopUniquePriorityQueueCompare()); + heap.pop_back(); + content_set.erase(top_pair.first); + + // Checking if the key with the highest sort value is in the delete pending set. + // If it is, ignore the current top item and remove the key from the delete pending set. Then get the next top item. + // Otherwise, the top item found, break the loop. + if (delete_pending_set.find(top_pair.first) != delete_pending_set.end()) { + delete_pending_set.erase(top_pair.first); + top_pair = std::pair(); + } else { + break; + } + } + + // If there is zero non-pending-delete item, clear the queue. + if (empty()) { + clear(); + } + + return top_pair; + } + + /** + * @brief Remove the item with matching key value from the priority queue + * This will immediately remove the item and re-heapify the queue. + * + * This function is expensive, as it requires a full re-heapify of the queue. + * The time complexity is O(n log n) for the re-heapify, where n is the size of the queue. + * It is recommended to use remove_at_pop_time() instead. + * @param key + * The key of the item to be delected from the queue. + */ + void remove(T_key key) { + // If the key is in the priority queue, remove it from the heap and reheapify. + // Otherwise, do nothing. + if (content_set.find(key) != content_set.end()) { + content_set.erase(key); + delete_pending_set.erase(key); + for (int i = 0; i < heap.size(); i++) { + if (heap[i].first == key) { + heap.erase(heap.begin() + i); + break; + } + } + + // If this delete caused the queue to have zero non-pending-delete item, clear the queue. + if (empty()) { + clear(); + // Otherwise re-heapify the queue + } else { + std::make_heap(heap.begin(), heap.end(), LazyPopUniquePriorityQueueCompare()); + } + } + } + + /** + * @brief Remove the item with matching key value from the priority queue at pop time. + * Add the key to the delete pending set for tracking, + * and it will be deleted when it is popped. + * + * This function will not immediately delete the key from the + * priority queue. It will be deleted when it is popped. Thus do not + * expect a size reduction in the priority queue immediately. + * @param key + * The key of the item to be delected from the queue at pop time. + */ + void remove_at_pop_time(T_key key) { + // If the key is in the list, start tracking it in the delete pending list. + // Otherwise, do nothing. + if (content_set.find(key) != content_set.end()) { + delete_pending_set.insert(key); + + // If this marks the last non-pending-delete item as to-be-deleted, clear the queue + if (empty()) { + clear(); + } + } + } + + /** + * @brief Check if the priority queue is empty, i.e. there is zero non-pending-delete item. + * + * @return True if the priority queue is empty, false otherwise. + */ + bool empty() { + return size() == 0; + } + + /** + * @brief Clears the priority queue and the tracking sets. + * + * @return None + */ + void clear() { + heap.clear(); + content_set.clear(); + delete_pending_set.clear(); + } + + /** + * @brief Get the number of non-pending-delete items in the priority queue. + * + * @return The number of non-pending-delete items in the priority queue. + */ + size_t size() { + return heap.size() - delete_pending_set.size(); + } + + /** + * @brief Check if the item referred to the key is in the priority queue. + * + * @param key + * The key of the item. + * @return True if the key is in the priority queue, false otherwise. + */ + bool contains(T_key key) { + return content_set.find(key) != content_set.end(); + } +}; From 88ce1a5563dc2abdaad73d70f85289128f0046ef Mon Sep 17 00:00:00 2001 From: Rongbo Zhang Date: Thu, 1 May 2025 22:07:16 -0400 Subject: [PATCH 115/176] [packer] recollected golden results for regression basic, basic_odin, strong, strong_odin --- .../basic_no_timing/config/golden_results.txt | 10 +- .../basic_timing/config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../basic_no_timing/config/golden_results.txt | 10 +- .../basic_timing/config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../basic_ap/config/golden_results.txt | 10 +- .../koios_test/config/golden_results.txt | 10 +- .../config/golden_results.txt | 4 +- .../strong_3d/3d_cb/config/golden_results.txt | 2 +- .../strong_3d/3d_sb/config/golden_results.txt | 2 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../strong_ap/mcnc/config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../no_fixed_blocks/config/golden_results.txt | 12 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../vtr_chain/config/golden_results.txt | 10 +- .../strong_bidir/config/golden_results.txt | 10 +- .../strong_binary/config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../strong_depop/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_fc_abs/config/golden_results.txt | 4 +- .../apex2_block_locations.place | 352 +++++++++--------- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../read_write/config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +-- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_mcnc/config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_noc/config/golden_results.txt | 4 +- .../strong_pack/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../strong_place/config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +-- .../strong_power/config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_sdc/config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 28 +- .../config/golden_results.txt | 4 +- .../strong_timing/config/golden_results.txt | 10 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 24 +- .../strong_titan/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../koios_test/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../strong_bidir/config/golden_results.txt | 10 +- .../strong_binary/config/golden_results.txt | 6 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../strong_depop/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_fc_abs/config/golden_results.txt | 4 +- .../apex2_block_locations.place | 352 +++++++++--------- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +-- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_mcnc/config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_pack/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../strong_place/config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +-- .../strong_power/config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_sdc/config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 28 +- .../config/golden_results.txt | 4 +- .../strong_timing/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../strong_titan/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- 198 files changed, 1102 insertions(+), 1090 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt index a19aa57c938..2af379bd870 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.71 vpr 62.29 MiB -1 -1 0.45 18372 3 0.09 -1 -1 33140 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63780 99 130 353 483 1 222 301 13 13 169 clb auto 22.7 MiB 0.06 730 30541 5185 13290 12066 62.3 MiB 0.05 0.00 28 1583 11 3.33e+06 2.25e+06 384474. 2275.00 0.18 - k4_N10_memSize16384_memData64.xml diffeq1.v common 3.90 vpr 66.30 MiB -1 -1 0.72 23492 23 0.30 -1 -1 34028 -1 -1 77 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67888 162 96 1200 1141 1 675 340 13 13 169 clb auto 25.9 MiB 0.18 5120 92848 24971 61178 6699 66.3 MiB 0.19 0.00 52 9637 13 3.33e+06 2.76e+06 671819. 3975.26 1.14 - k4_N10_memSize16384_memData64.xml single_wire.v common 2.10 vpr 59.81 MiB -1 -1 0.16 16372 1 0.17 -1 -1 29680 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61244 1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 2 3 0 3 0 59.8 MiB 0.01 0.00 2 1 1 30000 0 1489.46 165.495 0.01 - k4_N10_memSize16384_memData64.xml single_ff.v common 2.13 vpr 59.62 MiB -1 -1 0.15 16244 1 0.17 -1 -1 29552 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61048 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 6 9 6 0 3 59.6 MiB 0.01 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.20 vpr 63.47 MiB -1 -1 0.21 18728 3 0.06 -1 -1 32696 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64996 99 130 353 483 1 220 302 13 13 169 clb auto 23.7 MiB 0.03 1748 641 31674 5814 13912 11948 63.5 MiB 0.03 0.00 36 1209 9 3.33e+06 2.28e+06 481319. 2848.04 0.18 +k4_N10_memSize16384_memData64.xml diffeq1.v common 2.73 vpr 66.43 MiB -1 -1 0.30 23332 23 0.24 -1 -1 33444 -1 -1 78 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68020 162 96 1200 1141 1 690 341 14 14 196 clb auto 26.8 MiB 0.11 8696 5304 81261 22686 53433 5142 66.4 MiB 0.09 0.00 46 10726 18 4.32e+06 2.79e+06 735717. 3753.66 1.03 +k4_N10_memSize16384_memData64.xml single_wire.v common 0.51 vpr 61.51 MiB -1 -1 0.06 17188 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62988 1 1 1 2 0 1 2 3 3 9 -1 auto 22.9 MiB 0.00 2 2 3 0 3 0 61.5 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 +k4_N10_memSize16384_memData64.xml single_ff.v common 0.51 vpr 61.52 MiB -1 -1 0.06 17188 1 0.02 -1 -1 29584 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63000 2 1 3 4 1 3 4 3 3 9 -1 auto 22.9 MiB 0.00 6 6 9 6 0 3 61.5 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt index 751bc75b90b..ca1a4d01acd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.47 vpr 63.16 MiB -1 -1 0.44 18236 3 0.17 -1 -1 33188 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 99 130 344 474 1 225 301 13 13 169 clb auto 23.3 MiB 0.09 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128139 0.00121469 0.100824 0.095478 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254103 0.235005 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0312641 0.0288189 - k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.44 vpr 63.16 MiB -1 -1 0.50 18152 3 0.14 -1 -1 33088 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 99 130 344 474 1 225 301 13 13 169 clb auto 23.2 MiB 0.11 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128481 0.00121739 0.100806 0.0954483 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254201 0.235091 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0311227 0.0286984 - k6_N10_mem32K_40nm.xml diffeq1.v common 9.49 vpr 67.11 MiB -1 -1 0.77 23280 15 0.36 -1 -1 34140 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68724 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.7 MiB 0.29 5596 100404 30167 62963 7274 67.1 MiB 0.72 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332766 0.00312916 0.315543 0.296132 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.42 1.40293 1.28823 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165646 0.152968 - k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 9.36 vpr 66.73 MiB -1 -1 0.76 23068 15 0.37 -1 -1 34060 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68332 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.4 MiB 0.27 5596 100404 30167 62963 7274 66.7 MiB 0.73 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332438 0.00312633 0.31865 0.29876 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.32 1.38842 1.27429 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165924 0.153299 - k6_N10_mem32K_40nm.xml single_wire.v common 2.19 vpr 61.04 MiB -1 -1 0.10 16040 1 0.17 -1 -1 29628 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62508 1 1 1 2 0 1 2 3 3 9 -1 auto 22.4 MiB 0.03 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0106e-05 6.693e-06 6.7577e-05 4.7955e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00184576 0.00171316 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00130358 0.00127692 - k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.14 vpr 61.03 MiB -1 -1 0.18 16180 1 0.17 -1 -1 29612 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62496 1 1 1 2 0 1 2 3 3 9 -1 auto 22.5 MiB 0.01 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 3.4991e-05 2.3839e-05 0.000154694 0.000110075 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.01 0.00205152 0.00184775 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106138 0.00103434 - k6_N10_mem32K_40nm.xml single_ff.v common 2.12 vpr 60.94 MiB -1 -1 0.17 16352 1 0.17 -1 -1 29692 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62400 2 1 3 4 1 3 4 3 3 9 -1 auto 22.4 MiB 0.01 6 9 3 5 1 60.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5239e-05 1.148e-05 9.224e-05 7.1486e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00131631 0.00123081 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.0011347 0.00109647 - k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.11 vpr 61.02 MiB -1 -1 0.17 16384 1 0.17 -1 -1 29576 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62488 2 1 3 4 1 3 4 3 3 9 -1 auto 22.5 MiB 0.00 6 9 3 5 1 61.0 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.54e-05 1.1599e-05 9.8314e-05 7.6493e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.001247 0.00116724 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00104656 0.00101086 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.47 vpr 65.36 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32736 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66928 99 130 344 474 1 224 302 13 13 169 clb auto 25.8 MiB 0.04 1746 762 68106 19514 34631 13961 65.4 MiB 0.11 0.00 2.21168 1.87164 -122.901 -1.87164 1.87164 0.11 0.00056191 0.000527319 0.0403153 0.0378126 -1 -1 -1 -1 32 1396 14 6.63067e+06 4.42837e+06 323148. 1912.12 0.20 0.105519 0.0972534 11612 59521 -1 1378 10 517 775 49020 15288 2.04417 2.04417 -145.25 -2.04417 -0.103145 -0.0426347 396943. 2348.77 0.01 0.02 0.03 -1 -1 0.01 0.0158349 0.0147659 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.47 vpr 64.98 MiB -1 -1 0.21 18440 3 0.06 -1 -1 32732 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66544 99 130 344 474 1 224 302 13 13 169 clb auto 25.6 MiB 0.04 1746 762 68106 19514 34631 13961 65.0 MiB 0.11 0.00 2.21168 1.87164 -122.901 -1.87164 1.87164 0.10 0.00055224 0.000517397 0.0404048 0.0379025 -1 -1 -1 -1 32 1396 14 6.63067e+06 4.42837e+06 323148. 1912.12 0.20 0.106014 0.0977643 11612 59521 -1 1378 10 517 775 49020 15288 2.04417 2.04417 -145.25 -2.04417 -0.103145 -0.0426347 396943. 2348.77 0.01 0.02 0.03 -1 -1 0.01 0.0156154 0.0145562 +k6_N10_mem32K_40nm.xml diffeq1.v common 4.54 vpr 68.83 MiB -1 -1 0.31 23428 15 0.28 -1 -1 33448 -1 -1 61 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70480 162 96 1009 950 1 667 324 16 16 256 mult_36 auto 29.1 MiB 0.15 9690 5422 80388 23076 51132 6180 68.8 MiB 0.31 0.01 24.8942 21.9154 -1692.2 -21.9154 21.9154 0.17 0.00158429 0.00147162 0.124815 0.116405 -1 -1 -1 -1 40 11149 48 1.21132e+07 5.26753e+06 612675. 2393.26 2.08 0.543747 0.50239 19892 118481 -1 8842 23 4046 9257 1093658 327616 22.4259 22.4259 -1741.35 -22.4259 0 0 771607. 3014.09 0.02 0.22 0.06 -1 -1 0.02 0.0887775 0.0834355 +k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 4.58 vpr 68.39 MiB -1 -1 0.32 23432 15 0.29 -1 -1 33816 -1 -1 61 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70028 162 96 1009 950 1 667 324 16 16 256 mult_36 auto 29.0 MiB 0.15 9690 5422 80388 23076 51132 6180 68.4 MiB 0.31 0.01 24.8942 21.9154 -1692.2 -21.9154 21.9154 0.17 0.00159526 0.00148652 0.124933 0.11659 -1 -1 -1 -1 40 11149 48 1.21132e+07 5.26753e+06 612675. 2393.26 2.09 0.544451 0.503424 19892 118481 -1 8842 23 4046 9257 1093658 327616 22.4259 22.4259 -1741.35 -22.4259 0 0 771607. 3014.09 0.02 0.22 0.06 -1 -1 0.02 0.0856913 0.0804183 +k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 63.12 MiB -1 -1 0.07 17288 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64636 1 1 1 2 0 1 2 3 3 9 -1 auto 24.5 MiB 0.00 2 2 3 0 3 0 63.1 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 1.4484e-05 8.56e-06 8.9672e-05 6.0789e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000934459 0.000863394 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000878643 0.000849111 +k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.51 vpr 62.75 MiB -1 -1 0.07 17288 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64252 1 1 1 2 0 1 2 3 3 9 -1 auto 24.5 MiB 0.00 2 2 3 0 3 0 62.7 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.879e-06 3.791e-06 5.5775e-05 3.7475e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00087896 0.000824065 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00081755 0.000787937 +k6_N10_mem32K_40nm.xml single_ff.v common 0.51 vpr 62.75 MiB -1 -1 0.06 17284 1 0.02 -1 -1 29580 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64256 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 3 5 1 62.8 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.134e-06 5.954e-06 7.5691e-05 5.6953e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000934593 0.000872745 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000868574 0.000830121 +k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.52 vpr 62.72 MiB -1 -1 0.06 16904 1 0.02 -1 -1 29584 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64224 2 1 3 4 1 3 4 3 3 9 -1 auto 24.1 MiB 0.00 6 6 9 3 5 1 62.7 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 8.915e-06 5.818e-06 7.4453e-05 5.5619e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000952687 0.000889176 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000926898 0.000890064 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt index e5e577a6aa0..614dc34633a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml mkPktMerge.v common 14.27 vpr 75.54 MiB -1 -1 1.67 25360 2 0.13 -1 -1 33796 -1 -1 43 311 15 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77356 311 156 972 1128 1 953 525 28 28 784 memory auto 28.9 MiB 0.44 8505 220693 82593 126911 11189 69.5 MiB 1.24 0.02 3.82651 -4329.36 -3.82651 3.82651 0.84 0.00554225 0.00490893 0.598549 0.528234 -1 -1 -1 -1 40 13414 12 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 6.02 1.94301 1.71815 62360 400487 -1 12485 12 2406 2992 760238 228941 4.26893 4.26893 -4812.21 -4.26893 -13.8425 -0.321515 2.55406e+06 3257.73 0.09 0.29 0.34 -1 -1 0.09 0.16964 0.153486 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml mkPktMerge.v common 6.31 vpr 70.39 MiB -1 -1 0.75 25736 2 0.09 -1 -1 33528 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72080 311 156 972 1128 1 953 525 28 28 784 memory auto 31.2 MiB 0.27 18876 8716 214342 80322 124048 9972 70.4 MiB 0.61 0.01 4.91229 4.39077 -4239.94 -4.39077 4.39077 0.60 0.00262128 0.0023325 0.283495 0.251921 -1 -1 -1 -1 40 13591 16 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 1.96 0.889033 0.801036 62360 400487 -1 12638 13 2518 2949 727753 230227 4.48005 4.48005 -4599.19 -4.48005 -24.1998 -0.322548 2.55406e+06 3257.73 0.08 0.18 0.22 -1 -1 0.08 0.10009 0.0930957 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt index cbe871a6d70..6c901e19f85 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.71 vpr 61.64 MiB -1 -1 0.45 18444 3 0.09 -1 -1 32856 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63120 99 130 353 483 1 222 301 13 13 169 clb auto 21.8 MiB 0.06 723 26509 3069 10019 13421 61.6 MiB 0.04 0.00 28 1598 8 3.33e+06 2.25e+06 384474. 2275.00 0.18 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 1.11 vpr 62.57 MiB -1 -1 0.21 18340 3 0.06 -1 -1 32272 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64072 99 130 353 483 1 221 302 13 13 169 clb auto 22.8 MiB 0.03 1823 708 26614 3324 9855 13435 62.6 MiB 0.02 0.00 28 1654 13 3.33e+06 2.28e+06 384474. 2275.00 0.12 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt index 68c5f54f784..513370f5331 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 3.06 vpr 62.63 MiB 0.05 9228 -1 -1 4 0.26 -1 -1 34628 -1 -1 78 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64132 99 130 378 508 1 260 308 14 14 196 clb auto 23.1 MiB 0.07 836 35634 7872 13338 14424 62.6 MiB 0.06 0.00 30 1863 18 4.32e+06 2.46e+06 504535. 2574.16 1.49 - k4_N10_memSize16384_memData64.xml diffeq1.v common 3.71 vpr 66.76 MiB 0.03 9312 -1 -1 23 0.28 -1 -1 34812 -1 -1 78 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68360 162 96 1214 1147 1 691 341 14 14 196 clb auto 26.3 MiB 0.20 5391 114581 32074 75067 7440 66.8 MiB 0.23 0.00 50 10696 14 4.32e+06 2.79e+06 792225. 4041.96 1.36 - k4_N10_memSize16384_memData64.xml single_wire.v common 0.50 vpr 60.26 MiB 0.03 6196 -1 -1 1 0.02 -1 -1 29884 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61708 1 1 1 2 0 1 2 3 3 9 -1 auto 21.5 MiB 0.00 2 3 0 3 0 60.3 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 - k4_N10_memSize16384_memData64.xml single_ff.v common 0.50 vpr 60.32 MiB 0.01 6248 -1 -1 1 0.02 -1 -1 29888 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61772 2 1 3 4 1 3 4 3 3 9 -1 auto 21.6 MiB 0.00 6 9 6 0 3 60.3 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 3.37 odin 98.62 MiB 2.09 100992 -1 -1 4 0.20 -1 -1 33712 -1 -1 77 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65108 99 130 378 508 1 264 307 13 13 169 clb auto 23.7 MiB 0.03 2217 834 80002 17611 37329 25062 63.6 MiB 0.06 0.00 38 1591 8 3.33e+06 2.43e+06 504671. 2986.22 0.18 +k4_N10_memSize16384_memData64.xml diffeq1.v common 4.23 odin 85.88 MiB 1.73 87936 -1 -1 23 0.22 -1 -1 34272 -1 -1 78 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68008 162 96 1214 1147 1 683 341 14 14 196 clb auto 26.8 MiB 0.11 8470 5094 83641 22304 55208 6129 66.4 MiB 0.09 0.00 46 10813 38 4.32e+06 2.79e+06 735717. 3753.66 1.06 +k4_N10_memSize16384_memData64.xml single_wire.v common 1.66 vpr 61.51 MiB 1.16 61056 -1 -1 1 0.02 -1 -1 29296 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62984 1 1 1 2 0 1 2 3 3 9 -1 auto 22.9 MiB 0.00 2 2 3 0 3 0 61.5 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 +k4_N10_memSize16384_memData64.xml single_ff.v common 1.59 vpr 61.52 MiB 1.09 61440 -1 -1 1 0.02 -1 -1 29964 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62996 2 1 3 4 1 3 4 3 3 9 -1 auto 22.9 MiB 0.00 6 6 9 6 0 3 61.5 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt index ef84b66a484..ea885b126e3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.50 vpr 64.15 MiB 0.07 9400 -1 -1 3 0.27 -1 -1 34560 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65688 99 130 363 493 1 255 305 13 13 169 clb auto 24.4 MiB 0.09 908 74177 24418 37403 12356 64.1 MiB 0.26 0.00 2.24932 -227.778 -2.24932 2.24932 0.32 0.00128796 0.00121332 0.096703 0.0915143 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.05 0.536952 0.490784 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.11 0.11 0.05 -1 -1 0.11 0.067572 0.0617159 - k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 4.47 vpr 64.18 MiB 0.07 9504 -1 -1 3 0.27 -1 -1 34508 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65716 99 130 363 493 1 255 305 13 13 169 clb auto 24.4 MiB 0.09 908 74177 24418 37403 12356 64.2 MiB 0.25 0.00 2.24932 -227.778 -2.24932 2.24932 0.33 0.00129519 0.00122409 0.0975081 0.0921414 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.05 0.537515 0.491308 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.10 0.10 0.06 -1 -1 0.10 0.0672906 0.0614343 - k6_N10_mem32K_40nm.xml diffeq1.v common 7.21 vpr 67.98 MiB 0.05 9412 -1 -1 15 0.36 -1 -1 34576 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69616 162 96 999 932 1 661 323 16 16 256 mult_36 auto 27.8 MiB 0.27 5495 75599 21207 48608 5784 68.0 MiB 0.58 0.01 21.6615 -1879.46 -21.6615 21.6615 0.51 0.00360796 0.00340202 0.25554 0.240594 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 3.00 1.1065 1.02126 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.21 0.36 0.12 -1 -1 0.21 0.171024 0.158501 - k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 7.19 vpr 68.00 MiB 0.05 9256 -1 -1 15 0.38 -1 -1 34544 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69628 162 96 999 932 1 661 323 16 16 256 mult_36 auto 27.8 MiB 0.27 5495 75599 21207 48608 5784 68.0 MiB 0.58 0.01 21.6615 -1879.46 -21.6615 21.6615 0.51 0.00357179 0.00336822 0.255146 0.240275 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 3.02 1.11639 1.03133 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.21 0.36 0.12 -1 -1 0.21 0.171551 0.159214 - k6_N10_mem32K_40nm.xml single_wire.v common 0.52 vpr 61.57 MiB 0.02 6336 -1 -1 1 0.02 -1 -1 29916 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63052 1 1 1 2 0 1 2 3 3 9 -1 auto 23.1 MiB 0.00 2 3 0 3 0 61.6 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0413e-05 6.444e-06 6.9938e-05 4.9915e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00113499 0.00107062 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00114956 0.00110637 - k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.50 vpr 61.70 MiB 0.01 6288 -1 -1 1 0.02 -1 -1 29852 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63176 1 1 1 2 0 1 2 3 3 9 -1 auto 23.1 MiB 0.00 2 3 0 3 0 61.7 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0828e-05 6.306e-06 8.6241e-05 6.4409e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00147956 0.00135131 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00110491 0.00107479 - k6_N10_mem32K_40nm.xml single_ff.v common 0.51 vpr 61.60 MiB 0.01 6340 -1 -1 1 0.02 -1 -1 29792 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63080 2 1 3 4 1 3 4 3 3 9 -1 auto 23.2 MiB 0.00 6 9 5 1 3 61.6 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5674e-05 1.1879e-05 0.000102525 7.8057e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0012801 0.00119733 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109578 0.00105577 - k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.52 vpr 61.85 MiB 0.01 6336 -1 -1 1 0.02 -1 -1 29872 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63336 2 1 3 4 1 3 4 3 3 9 -1 auto 23.4 MiB 0.00 6 9 5 1 3 61.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5402e-05 1.1583e-05 0.00010302 8.1368e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00128286 0.00120047 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.0011085 0.00106995 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.09 odin 100.12 MiB 2.45 102528 -1 -1 3 0.20 -1 -1 33716 -1 -1 75 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67068 99 130 363 493 1 253 305 13 13 169 clb auto 26.0 MiB 0.04 2273 844 74177 21541 39695 12941 65.5 MiB 0.18 0.00 2.6333 2.22949 -229.909 -2.22949 2.22949 0.11 0.00102109 0.000975646 0.0645574 0.0608928 -1 -1 -1 -1 32 1393 19 6.63067e+06 4.59005e+06 323148. 1912.12 0.23 0.134441 0.124635 11612 59521 -1 1193 22 721 1096 62496 20405 2.52707 2.52707 -230.152 -2.52707 0 0 396943. 2348.77 0.01 0.04 0.03 -1 -1 0.01 0.0262126 0.0241565 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.69 odin 99.75 MiB 2.12 102144 -1 -1 3 0.20 -1 -1 33712 -1 -1 75 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67028 99 130 363 493 1 253 305 13 13 169 clb auto 25.6 MiB 0.04 2273 844 74177 21541 39695 12941 65.5 MiB 0.12 0.00 2.6333 2.22949 -229.909 -2.22949 2.22949 0.10 0.000551623 0.00051622 0.043118 0.0403948 -1 -1 -1 -1 32 1393 19 6.63067e+06 4.59005e+06 323148. 1912.12 0.22 0.113077 0.104115 11612 59521 -1 1193 22 721 1096 62496 20405 2.52707 2.52707 -230.152 -2.52707 0 0 396943. 2348.77 0.01 0.04 0.03 -1 -1 0.01 0.0264785 0.0243931 +k6_N10_mem32K_40nm.xml diffeq1.v common 5.96 odin 87.00 MiB 1.89 89088 -1 -1 15 0.28 -1 -1 34196 -1 -1 62 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71044 162 96 999 932 1 663 325 16 16 256 mult_36 auto 29.4 MiB 0.14 9594 5574 90802 23938 58756 8108 69.4 MiB 0.34 0.01 24.8422 21.1611 -1910.27 -21.1611 21.1611 0.17 0.00167155 0.00156543 0.146309 0.137079 -1 -1 -1 -1 40 11068 31 1.21132e+07 5.32143e+06 612675. 2393.26 1.77 0.555231 0.516342 19892 118481 -1 8993 24 3753 8101 1142271 339586 22.091 22.091 -1952.75 -22.091 0 0 771607. 3014.09 0.02 0.23 0.06 -1 -1 0.02 0.0953915 0.0898028 +k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 6.11 odin 87.00 MiB 2.05 89088 -1 -1 15 0.30 -1 -1 34232 -1 -1 62 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71036 162 96 999 932 1 663 325 16 16 256 mult_36 auto 29.4 MiB 0.14 9594 5574 90802 23938 58756 8108 69.4 MiB 0.35 0.01 24.8422 21.1611 -1910.27 -21.1611 21.1611 0.17 0.00167453 0.00156692 0.147276 0.137984 -1 -1 -1 -1 40 11068 31 1.21132e+07 5.32143e+06 612675. 2393.26 1.73 0.548675 0.510684 19892 118481 -1 8993 24 3753 8101 1142271 339586 22.091 22.091 -1952.75 -22.091 0 0 771607. 3014.09 0.02 0.23 0.06 -1 -1 0.02 0.0940813 0.0885938 +k6_N10_mem32K_40nm.xml single_wire.v common 1.64 vpr 62.75 MiB 1.13 62208 -1 -1 1 0.02 -1 -1 29284 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64252 1 1 1 2 0 1 2 3 3 9 -1 auto 24.5 MiB 0.00 2 2 3 0 3 0 62.7 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.926e-06 3.897e-06 5.931e-05 4.0663e-05 -1 -1 -1 -1 14 13 1 53894 0 3251.56 361.284 0.00 0.000930685 0.000857938 318 537 -1 13 1 1 1 42 40 1.13321 nan -1.13321 -1.13321 0 0 4350.07 483.341 0.00 0.00 0.00 -1 -1 0.00 0.000814883 0.000785455 +k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.64 vpr 63.12 MiB 1.13 62208 -1 -1 1 0.02 -1 -1 29544 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64636 1 1 1 2 0 1 2 3 3 9 -1 auto 24.9 MiB 0.00 2 2 3 0 3 0 63.1 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.671e-06 3.657e-06 5.512e-05 3.7177e-05 -1 -1 -1 -1 14 13 1 53894 0 3251.56 361.284 0.00 0.00087693 0.000816732 318 537 -1 13 1 1 1 42 40 1.13321 nan -1.13321 -1.13321 0 0 4350.07 483.341 0.00 0.00 0.00 -1 -1 0.00 0.000823421 0.000793996 +k6_N10_mem32K_40nm.xml single_ff.v common 1.65 vpr 63.12 MiB 1.14 62592 -1 -1 1 0.02 -1 -1 29584 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64640 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 5 1 3 63.1 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.509e-06 6.128e-06 7.8966e-05 5.8678e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000960819 0.000895847 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000868741 0.000828858 +k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.76 vpr 62.75 MiB 1.24 62208 -1 -1 1 0.02 -1 -1 29596 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64252 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 5 1 3 62.7 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.481e-06 6.058e-06 7.5019e-05 5.5752e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000976511 0.00091156 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000882718 0.000844713 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt index 919720b66b9..0969bfb6332 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml mkPktMerge.v common 18.64 vpr 68.68 MiB 0.15 16588 -1 -1 2 0.14 -1 -1 33680 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70328 311 156 972 1128 1 953 525 28 28 784 memory auto 29.0 MiB 0.43 9306 216459 81370 124762 10327 68.7 MiB 1.23 0.02 3.96757 -4422.94 -3.96757 3.96757 1.99 0.0055271 0.00489462 0.594444 0.523451 -1 -1 -1 -1 36 14708 20 4.25198e+07 1.05374e+07 1.86960e+06 2384.70 9.73 2.38769 2.10211 60012 360096 -1 13625 12 2932 3661 921536 275737 4.35536 4.35536 -4857.74 -4.35536 -16.7192 -0.318417 2.30301e+06 2937.52 0.63 0.34 0.31 -1 -1 0.63 0.170436 0.153664 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml mkPktMerge.v common 10.82 odin 620.14 MiB 5.17 635024 -1 -1 2 0.09 -1 -1 34820 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71248 311 156 972 1128 1 953 525 28 28 784 memory auto 30.5 MiB 0.26 18730 9136 197406 68626 118543 10237 69.6 MiB 0.53 0.01 4.81396 3.68545 -4313.24 -3.68545 3.68545 0.58 0.00250062 0.00220291 0.243094 0.21545 -1 -1 -1 -1 40 14133 17 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 1.98 0.801256 0.718483 62360 400487 -1 13372 13 2874 3403 928204 274043 3.86375 3.86375 -4754.06 -3.86375 -26.664 -0.360359 2.55406e+06 3257.73 0.08 0.19 0.21 -1 -1 0.08 0.0937982 0.0869213 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt index f19725cfd85..68933f7a97c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.61 vpr 62.39 MiB 0.07 9224 -1 -1 4 0.25 -1 -1 34556 -1 -1 78 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63888 99 130 378 508 1 260 308 14 14 196 clb auto 23.3 MiB 0.07 836 35634 7872 13338 14424 62.4 MiB 0.06 0.00 30 1863 18 4.32e+06 2.46e+06 504535. 2574.16 0.99 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 1.46 odin 97.50 MiB 0.17 99840 -1 -1 4 0.19 -1 -1 33712 -1 -1 77 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65056 99 130 378 508 1 264 307 13 13 169 clb auto 23.7 MiB 0.03 2217 834 80002 17611 37329 25062 63.5 MiB 0.07 0.00 38 1591 8 3.33e+06 2.43e+06 504671. 2986.22 0.18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt index f0282e9bf5e..3d0cf31dbb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_k6_frac_N8_22nm.xml single_wire.v common 1.34 vpr 75.71 MiB -1 -1 0.07 20608 1 0.01 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 2 3 0 0 3 75.7 MiB 0.48 0.00 0.2714 0.2714 -0.2714 -0.2714 nan 0.40 1.4684e-05 9.512e-06 8.1482e-05 5.6821e-05 75.7 MiB 0.48 75.7 MiB 0.07 8 16 1 6.79088e+06 0 166176. 575.005 0.15 0.000912133 0.000836449 20206 45088 -1 18 1 1 1 141 56 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.04 -1 -1 0.01 0.000776852 0.0007249 - fixed_k6_frac_N8_22nm.xml single_ff.v common 1.51 vpr 75.95 MiB -1 -1 0.08 20852 1 0.02 -1 -1 33716 -1 -1 1 2 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 22 24 9 1 1 7 76.0 MiB 0.47 0.00 0.930505 0.74674 -1.43836 -0.74674 0.74674 0.39 1.1513e-05 7.851e-06 8.3564e-05 6.0773e-05 76.0 MiB 0.47 76.0 MiB 0.07 20 31 1 6.79088e+06 13472 414966. 1435.87 0.24 0.000928712 0.000851847 22510 95286 -1 32 1 2 2 231 42 0.74674 0.74674 -1.43836 -0.74674 0 0 503264. 1741.40 0.03 0.00 0.08 -1 -1 0.03 0.000833737 0.000775898 - fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 2.74 vpr 76.62 MiB -1 -1 0.26 22392 3 0.07 -1 -1 37308 -1 -1 67 99 1 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78456 99 130 240 229 1 225 297 17 17 289 -1 unnamed_device -1 -1 978 866 19107 2257 1105 15745 76.6 MiB 0.61 0.00 2.26688 1.84068 -122.242 -1.84068 1.84068 0.39 0.000595647 0.000527536 0.0138425 0.0123349 76.6 MiB 0.61 76.6 MiB 0.13 34 1974 43 6.79088e+06 1.45062e+06 618332. 2139.56 0.79 0.175076 0.154945 25102 150614 -1 1739 14 569 895 60631 18120 2.0466 2.0466 -143.082 -2.0466 -0.04337 -0.04337 787024. 2723.27 0.04 0.03 0.13 -1 -1 0.04 0.0355147 0.0319235 - fixed_k6_frac_N8_22nm.xml diffeq1.v common 9.26 vpr 78.62 MiB -1 -1 0.36 26868 15 0.31 -1 -1 37472 -1 -1 47 162 0 5 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 80512 162 96 817 258 1 691 310 17 17 289 -1 unnamed_device -1 -1 7341 6689 25462 269 7038 18155 78.6 MiB 1.27 0.01 22.1608 21.0485 -1573.19 -21.0485 21.0485 0.38 0.00201699 0.00177192 0.0590804 0.052726 78.6 MiB 1.27 78.6 MiB 0.26 54 12827 26 6.79088e+06 2.61318e+06 949917. 3286.91 5.15 0.794403 0.715337 28846 232421 -1 11184 19 3449 7611 967200 252634 20.9913 20.9913 -1571.36 -20.9913 0 0 1.17392e+06 4061.99 0.06 0.26 0.21 -1 -1 0.06 0.158612 0.144189 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_k6_frac_N8_22nm.xml single_wire.v common 1.14 vpr 73.91 MiB -1 -1 0.06 17288 1 0.02 -1 -1 29952 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75684 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 2 3 0 0 3 73.9 MiB 0.33 0.00 0.2714 0.2714 -0.2714 -0.2714 nan 0.24 6.545e-06 3.49e-06 5.3077e-05 3.5069e-05 73.9 MiB 0.33 73.9 MiB 0.09 8 18 1 6.79088e+06 0 166176. 575.005 0.12 0.000968028 0.000900296 20206 45088 -1 18 1 1 1 110 40 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.02 -1 -1 0.01 0.000884953 0.000829916 +fixed_k6_frac_N8_22nm.xml single_ff.v common 1.16 vpr 74.29 MiB -1 -1 0.07 17668 1 0.02 -1 -1 29808 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76068 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 20 20 9 0 3 6 74.3 MiB 0.32 0.00 0.62144 0.62144 -1.18776 -0.62144 0.62144 0.23 9.46e-06 6.107e-06 7.2338e-05 5.3762e-05 74.3 MiB 0.32 74.3 MiB 0.09 20 27 1 6.79088e+06 13472 414966. 1435.87 0.15 0.000991708 0.000923792 22510 95286 -1 27 1 2 2 155 34 0.74674 0.74674 -1.31306 -0.74674 0 0 503264. 1741.40 0.02 0.00 0.05 -1 -1 0.02 0.000927584 0.000870114 +fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 1.96 vpr 74.95 MiB -1 -1 0.21 18824 3 0.06 -1 -1 33092 -1 -1 67 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76744 99 130 240 229 1 221 297 17 17 289 -1 unnamed_device -1 -1 875 831 15147 1842 1372 11933 74.9 MiB 0.45 0.00 1.77902 1.6707 -126.688 -1.6707 1.6707 0.23 0.000544346 0.000510829 0.0106205 0.0100193 74.9 MiB 0.45 74.9 MiB 0.15 32 1830 14 6.79088e+06 1.45062e+06 586450. 2029.24 0.33 0.0772085 0.0707225 24814 144142 -1 1586 13 517 851 46748 14508 2.0466 2.0466 -137.082 -2.0466 -0.16867 -0.16867 744469. 2576.02 0.03 0.03 0.07 -1 -1 0.03 0.0295429 0.0275638 +fixed_k6_frac_N8_22nm.xml diffeq1.v common 5.43 vpr 76.34 MiB -1 -1 0.31 23432 15 0.29 -1 -1 33828 -1 -1 46 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78168 162 96 817 258 1 692 309 17 17 289 -1 unnamed_device -1 -1 7537 6452 26409 275 7390 18744 76.3 MiB 0.94 0.01 22.1138 21.2087 -1557.26 -21.2087 21.2087 0.23 0.00162614 0.00151896 0.0510239 0.0477515 76.3 MiB 0.94 76.3 MiB 0.23 52 12973 34 6.79088e+06 2.59971e+06 926341. 3205.33 2.07 0.452281 0.419264 28558 226646 -1 11227 22 3275 7622 1002575 262444 20.6757 20.6757 -1527 -20.6757 0 0 1.14541e+06 3963.36 0.04 0.21 0.12 -1 -1 0.04 0.135881 0.127356 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt index 13c7fadca33..8d48ba3b7bb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 3.53 vpr 75.00 MiB -1 -1 0.20 17948 1 0.05 -1 -1 31776 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 76796 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.10 3253 1906 39109 13750 20961 4398 75.0 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000972896 0.000903976 0.0756961 0.0702652 -1 -1 -1 -1 82 3601 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.39 0.353988 0.326407 33448 250998 -1 3687 9 800 863 234820 89374 4.57723 4.57723 -726.049 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.06 0.21 -1 -1 0.04 0.029531 0.027938 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 3.67 vpr 75.36 MiB -1 -1 0.19 17948 1 0.05 -1 -1 31772 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 77172 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.1 MiB 0.10 3253 1906 39109 13750 20961 4398 75.4 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.27 0.00093525 0.000867226 0.074379 0.0690457 -1 -1 -1 -1 82 3585 15 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.46 0.361492 0.333317 33448 250998 -1 3715 9 792 819 214644 81314 4.57723 4.57723 -685.291 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.06 0.21 -1 -1 0.04 0.0295768 0.0280427 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.39 vpr 74.76 MiB -1 -1 0.19 17960 1 0.05 -1 -1 32068 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 76556 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.1 MiB 0.10 3253 1906 39109 13750 20961 4398 74.8 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000971322 0.000902249 0.0754843 0.0701709 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.12 0.359108 0.331481 33448 250998 -1 3424 10 688 706 802479 802479 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.21 0.21 -1 -1 0.04 0.0308245 0.0291405 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 5.39 vpr 75.00 MiB -1 -1 0.20 17960 1 0.05 -1 -1 32092 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 76796 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.3 MiB 0.12 3253 1906 39109 13750 20961 4398 75.0 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.22 0.000968255 0.000899263 0.0760549 0.070686 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.88 0.358969 0.330993 33448 250998 -1 3424 10 688 706 796806 796806 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.43 0.21 -1 -1 0.04 0.0319008 0.0301886 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.39 vpr 74.01 MiB -1 -1 0.19 17564 1 0.05 -1 -1 31772 -1 -1 12 130 0 -1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 75788 130 40 596 562 1 356 185 14 14 196 dsp_top auto 34.9 MiB 0.11 3253 1906 39109 13750 20961 4398 74.0 MiB 0.14 0.00 5.12303 5.12303 -649.023 -5.12303 5.12303 0.24 0.00096838 0.000899881 0.0767282 0.0713559 -1 -1 -1 -1 82 3577 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 2.13 0.361612 0.33375 33448 250998 -1 3424 10 688 706 789226 323167 4.57723 4.57723 -678.711 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.18 0.21 -1 -1 0.04 0.0309043 0.029241 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 2.99 vpr 75.31 MiB -1 -1 0.19 18544 1 0.04 -1 -1 31664 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77116 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.2 MiB 0.09 3373 1886 37005 12673 19524 4808 75.3 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.18 0.000888478 0.000830569 0.0676133 0.0633469 -1 -1 -1 -1 80 3637 13 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.12 0.273919 0.254588 33264 246902 -1 3285 7 680 743 143030 53497 4.57723 4.57723 -709.755 -4.57723 0 0 1.50824e+06 7695.10 0.03 0.04 0.16 -1 -1 0.03 0.0237623 0.0226895 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 3.06 vpr 75.10 MiB -1 -1 0.18 18308 1 0.05 -1 -1 31656 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76900 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.0 MiB 0.09 3373 1886 37005 12673 19524 4808 75.1 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.18 0.000947284 0.000887707 0.0714409 0.0669686 -1 -1 -1 -1 80 3614 31 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.17 0.308838 0.28719 33264 246902 -1 3269 7 690 753 144671 54345 4.57723 4.57723 -668.704 -4.57723 0 0 1.50824e+06 7695.10 0.03 0.04 0.16 -1 -1 0.03 0.0243899 0.0232635 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 3.85 vpr 75.10 MiB -1 -1 0.18 18304 1 0.05 -1 -1 31656 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76900 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.0 MiB 0.09 3373 1886 37005 12673 19524 4808 75.1 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.19 0.000947139 0.000884506 0.0718506 0.0673524 -1 -1 -1 -1 80 3571 8 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.78 0.275537 0.25602 33264 246902 -1 3282 7 664 709 751766 751766 4.57723 4.57723 -648.751 -4.57723 0 0 1.50824e+06 7695.10 0.04 0.18 0.18 -1 -1 0.04 0.0251499 0.0240091 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.13 vpr 75.70 MiB -1 -1 0.19 18304 1 0.05 -1 -1 31624 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77512 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.6 MiB 0.09 3373 1886 37005 12673 19524 4808 75.7 MiB 0.13 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.19 0.000936676 0.000876234 0.072396 0.0678269 -1 -1 -1 -1 80 3571 8 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 2.01 0.278036 0.258406 33264 246902 -1 3282 7 664 709 746031 746031 4.57723 4.57723 -648.751 -4.57723 0 0 1.50824e+06 7695.10 0.04 0.23 0.17 -1 -1 0.04 0.0252544 0.0240964 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 3.72 vpr 75.19 MiB -1 -1 0.19 18304 1 0.05 -1 -1 31656 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76992 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.1 MiB 0.09 3373 1886 37005 12673 19524 4808 75.2 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.18 0.000925013 0.000865263 0.0715735 0.0670973 -1 -1 -1 -1 80 3571 8 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.68 0.27697 0.257059 33264 246902 -1 3282 7 664 709 739993 283414 4.57723 4.57723 -648.751 -4.57723 0 0 1.50824e+06 7695.10 0.04 0.17 0.17 -1 -1 0.04 0.0248422 0.0236933 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt index 4e167973fd7..65bf790b0e7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.61 vpr 79.62 MiB -1 -1 0.81 23308 1 0.11 -1 -1 37544 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81536 130 40 1147 997 1 585 196 14 14 196 dsp_top auto 40.6 MiB 0.64 2711 47992 15247 26403 6342 79.6 MiB 0.47 0.01 6.04823 -699.558 -6.04823 6.04823 0.48 0.00203985 0.00179993 0.208906 0.186707 -1 -1 -1 -1 108 5255 25 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 4.22 0.825967 0.736098 36552 325092 -1 4721 19 2233 2309 243533 83581 7.64092 7.64092 -760.756 -7.64092 0 0 1.93951e+06 9895.46 0.09 0.19 0.61 -1 -1 0.09 0.108869 0.100506 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 4.52 vpr 78.22 MiB -1 -1 0.40 19840 1 0.06 -1 -1 33392 -1 -1 23 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 80096 130 40 1147 997 1 592 196 14 14 196 dsp_top auto 39.1 MiB 0.28 5185 2742 51406 16747 29054 5605 78.2 MiB 0.20 0.00 7.18035 6.03913 -683.447 -6.03913 6.03913 0.19 0.00100505 0.000908109 0.0981168 0.0895226 -1 -1 -1 -1 118 5148 28 4.93594e+06 1.40315e+06 1.66654e+06 8502.75 1.79 0.409007 0.367667 37820 362924 -1 5094 24 2395 2501 322053 103825 7.0462 7.0462 -729.408 -7.0462 0 0 2.11586e+06 10795.2 0.05 0.11 0.27 -1 -1 0.05 0.0618139 0.0571071 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt index b1825addf7b..4a4c7e8c58a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 48.72 vpr 1.18 GiB 42 758 0 0 0 0 success v8.0.0-12506-gd5dc5f7b8 release IPO VTR_ASSERT_LEVEL=2 GNU 11.5.0 on Linux-5.4.0-171-generic x86_64 2025-04-26T07:14:03 qlsof01.quicklogic.com /home/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 1240720 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1075.1 MiB 12.14 186170 63157 219808 34278 166444 19086 1191.3 MiB 7.46 0.11 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.02 0.0246574 0.0210761 1.78411 1.4367 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 7.54 -1 -1 1191.3 MiB 4.03 3.22991 2.72734 1191.3 MiB -1 1.82 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 34.99 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1239896 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1077.1 MiB 7.54 181772 63669 220151 34297 170189 15665 1190.3 MiB 5.82 0.09 5.43671 4.9834 -5379.72 -3.9834 2.7577 0.01 0.0231458 0.0183209 1.51922 1.22818 74208 5.86903 18737 1.48189 26177 36020 11211877 1692426 0 0 2.60031e+07 21349.0 16 354380 4692432 -1 5.06256 2.57234 -4972.33 -4.06256 0 0 4.48 -1 -1 1190.3 MiB 3.13 2.65902 2.23319 1190.3 MiB -1 1.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt index 2ba28851792..192e82a31ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 73.49 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12506-gd5dc5f7b8 release IPO VTR_ASSERT_LEVEL=2 GNU 11.5.0 on Linux-5.4.0-171-generic x86_64 2025-04-26T07:14:03 qlsof01.quicklogic.com /home/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 1423216 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1074.8 MiB 12.24 180137 58272 230944 40790 173771 16383 1389.9 MiB 7.97 0.12 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.02551 0.0218529 1.92289 1.55523 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 9.53 -1 -1 1389.9 MiB 9.59 3.30445 2.79009 1389.9 MiB -1 17.61 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 51.26 vpr 1.36 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1422252 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1077.2 MiB 7.54 177076 58479 231119 40825 176329 13965 1388.9 MiB 5.94 0.09 5.0611 5.01815 -4172.98 -4.01815 2.37031 0.04 0.0219122 0.0175206 1.56983 1.27458 100824 7.97406 32812 2.59506 28894 40551 43377071 9674443 0 0 2.54084e+07 20860.8 17 2001132 6214436 -1 5.14007 2.63151 -5380.59 -4.14007 0 0 6.15 -1 -1 1388.9 MiB 6.89 2.74676 2.32243 1388.9 MiB -1 11.16 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt index abc45194ec7..72305f830f8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 2.31 vpr 72.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74048 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.2 MiB 1.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00628067 0.00572957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.95 vpr 72.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73772 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.4 MiB 1.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00606424 0.00546366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.00 vpr 70.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 130 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72224 130 150 1169 1319 1 885 365 12 12 144 clb auto 30.3 MiB 0.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00300143 0.00278911 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.03 vpr 69.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 130 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71656 130 150 1216 1366 1 925 374 12 12 144 clb auto 30.2 MiB 0.61 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00277001 0.00256442 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index 94e710b87f5..c2cab91c857 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.05 vpr 66.01 MiB -1 -1 0.86 26896 5 0.23 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67592 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.0 MiB 0.02 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000412775 0.000360271 0.0136111 0.012803 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.04 -1 -1 66.0 MiB 0.03 0.0339384 0.0288063 66.0 MiB -1 0.00 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.21 vpr 69.14 MiB -1 -1 0.76 26288 4 0.18 -1 -1 36060 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70796 11 2 303 283 2 78 28 7 7 49 clb auto 29.6 MiB 0.27 285 784 175 539 70 69.1 MiB 0.05 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000707376 0.000615193 0.0194274 0.0173585 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 69.1 MiB 0.03 0.0450009 0.0414951 69.1 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.09 vpr 64.65 MiB -1 -1 0.42 23048 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 10 2 181 183 1 36 24 6 6 36 clb auto 25.3 MiB 0.02 196 160 398 88 284 26 64.7 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000227686 0.000206782 0.00385417 0.00356609 -1 -1 -1 -1 136 4.12121 61 1.84848 149 320 10235 1961 646728 646728 138825. 3856.24 17 3164 19284 -1 2.10277 2.10277 -91.6521 -2.10277 0 0 0.01 -1 -1 64.7 MiB 0.01 0.0141506 0.0127546 64.7 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.27 vpr 67.25 MiB -1 -1 0.42 22932 4 0.10 -1 -1 33012 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68868 11 2 303 283 2 85 28 7 7 49 clb auto 27.9 MiB 0.11 462 289 1204 263 848 93 67.3 MiB 0.02 0.00 2.20327 2.04719 -154.888 -2.04719 1.90466 0.00 0.00038481 0.000343694 0.0145236 0.0131117 -1 -1 -1 -1 314 3.97468 124 1.56962 130 211 4049 1168 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.02047 1.86775 -152.224 -2.02047 0 0 0.02 -1 -1 67.3 MiB 0.01 0.028669 0.0263845 67.3 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt index 7f41d46c079..249ce143daf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.75 vpr 67.64 MiB -1 -1 0.42 22416 3 0.08 -1 -1 36896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69264 99 130 344 474 1 227 298 12 12 144 clb auto 28.8 MiB 0.22 846 1293 248 869 176 67.6 MiB 0.10 0.00 1.87518 -117.076 -1.87518 1.87518 0.33 0.000961535 0.000869555 0.00580355 0.00550747 -1 -1 -1 -1 38 1541 12 5.66058e+06 4.21279e+06 319130. 2216.18 1.43 0.231487 0.210357 12522 62564 -1 1321 9 430 670 30619 10041 1.9175 1.9175 -131.199 -1.9175 -0.126268 -0.104429 406292. 2821.48 0.02 0.04 0.09 -1 -1 0.02 0.0283489 0.0264305 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.60 vpr 66.94 MiB -1 -1 0.22 18440 3 0.06 -1 -1 33128 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68544 99 130 344 474 1 228 298 12 12 144 clb auto 27.5 MiB 0.10 863 800 1293 264 867 162 66.9 MiB 0.04 0.00 1.86362 1.90582 -117.68 -1.90582 1.90582 0.09 0.000566314 0.000530143 0.0035014 0.00338303 -1 -1 -1 -1 40 1473 16 5.66058e+06 4.21279e+06 333335. 2314.82 0.32 0.11664 0.106115 12666 64609 -1 1318 11 405 616 29250 9869 1.99389 1.99389 -129.176 -1.99389 -0.260939 -0.108257 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0187502 0.0175858 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt index f90dc9de594..52938d917ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.63 vpr 75.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77436 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.56 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00332256 0.00272635 0.0920151 0.0793873 75.6 MiB 3.56 75.6 MiB 2.42 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.47 0.288973 0.25613 75.6 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.81 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78036 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.93 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00365979 0.00331889 0.047619 0.043593 76.2 MiB 0.93 76.2 MiB 0.59 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.37 -1 -1 76.2 MiB 0.25 0.188446 0.174077 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 11.93 vpr 105.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108360 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 9.23 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.00660438 0.00519941 0.309592 0.257376 105.8 MiB 9.23 105.8 MiB 4.50 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.18 -1 -1 105.8 MiB 0.93 0.709043 0.615207 105.8 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.73 vpr 76.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78628 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.59 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.09 0.0040653 0.00347069 0.103188 0.0899686 76.8 MiB 3.59 76.8 MiB 2.31 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.37 -1 -1 76.8 MiB 0.47 0.321818 0.287107 76.8 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.98 vpr 73.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75472 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.7 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00129454 0.00112381 0.0398145 0.0363439 73.7 MiB 1.50 73.7 MiB 1.00 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.7 MiB 0.20 0.127617 0.117429 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 74.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76044 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.3 MiB 0.45 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00188121 0.00176936 0.0256359 0.0244673 74.3 MiB 0.45 74.3 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 74.3 MiB 0.13 0.105433 0.100554 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 7.07 vpr 103.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106172 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.7 MiB 5.65 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00399056 0.00320166 0.20162 0.170474 103.7 MiB 5.65 103.7 MiB 3.13 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.7 MiB 0.62 0.486586 0.43074 103.7 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.94 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76684 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 74.9 MiB 1.47 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00146693 0.00126108 0.0415462 0.0377108 74.9 MiB 1.47 74.9 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 74.9 MiB 0.19 0.135186 0.124628 74.9 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt index 91c3630a8a8..76465232886 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.88 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.73 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00371221 0.00305644 0.097355 0.0840965 75.4 MiB 3.73 75.4 MiB 2.65 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.4 MiB 0.50 0.299102 0.265267 75.4 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.04 vpr 75.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.0 MiB 1.04 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00356373 0.00322411 0.0543939 0.0472155 76.0 MiB 1.04 76.0 MiB 0.69 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.39 -1 -1 76.0 MiB 0.32 0.22263 0.205375 76.0 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 14.50 vpr 105.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108280 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 11.89 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.0066784 0.00535245 0.30231 0.252682 105.7 MiB 11.89 105.7 MiB 7.07 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.11 -1 -1 105.7 MiB 0.94 0.707357 0.615217 105.7 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.83 vpr 76.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78264 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.4 MiB 3.68 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00384755 0.00327555 0.103123 0.0900634 76.4 MiB 3.68 76.4 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.4 MiB 0.48 0.323332 0.288275 76.4 MiB -1 0.11 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.97 vpr 73.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75120 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.4 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00131792 0.00114251 0.0400779 0.0365448 73.4 MiB 1.50 73.4 MiB 0.99 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.4 MiB 0.20 0.127955 0.117552 73.4 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 73.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75720 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 73.9 MiB 0.45 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00182847 0.00171986 0.0251787 0.0240126 73.9 MiB 0.45 73.9 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 73.9 MiB 0.13 0.107099 0.101914 73.9 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.93 vpr 103.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106292 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.8 MiB 5.52 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00402634 0.00322812 0.200547 0.169453 103.8 MiB 5.52 103.8 MiB 3.00 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.8 MiB 0.62 0.485669 0.429563 103.8 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.99 vpr 75.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77004 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 75.2 MiB 1.48 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00153795 0.00132852 0.0472318 0.0431113 75.2 MiB 1.48 75.2 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 75.2 MiB 0.20 0.147085 0.135687 75.2 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt index e03594be3ed..3917cf290cc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.66 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.54 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00377685 0.0031064 0.0971738 0.0840095 75.4 MiB 3.54 75.4 MiB 2.44 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.35 -1 -1 75.4 MiB 0.49 0.299893 0.266532 75.4 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.87 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.95 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.12 0.00361228 0.00324116 0.0472811 0.0432415 76.2 MiB 0.95 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.40 -1 -1 76.2 MiB 0.27 0.192439 0.178374 76.2 MiB -1 0.12 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.92 vpr 105.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108344 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 13.27 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.27 0.0064285 0.00513075 0.474187 0.399734 105.8 MiB 13.27 105.8 MiB 7.54 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.15 -1 -1 105.8 MiB 0.91 0.870133 0.753188 105.8 MiB -1 0.27 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.70 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.7 MiB 3.57 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00387961 0.00328771 0.108944 0.0952913 76.7 MiB 3.57 76.7 MiB 2.29 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.32 -1 -1 76.7 MiB 0.51 0.337895 0.301103 76.7 MiB -1 0.10 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.96 vpr 73.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75492 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.7 MiB 1.48 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00133012 0.00115567 0.0399995 0.0365239 73.7 MiB 1.48 73.7 MiB 0.98 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.7 MiB 0.20 0.127012 0.116845 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 74.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76048 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.3 MiB 0.45 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00182176 0.00171274 0.0250514 0.0238946 74.3 MiB 0.45 74.3 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 74.3 MiB 0.13 0.104201 0.0993829 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.92 vpr 103.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106000 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.5 MiB 5.51 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00398133 0.00318465 0.201687 0.170276 103.5 MiB 5.51 103.5 MiB 2.97 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.5 MiB 0.63 0.489118 0.432801 103.5 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.93 vpr 75.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76824 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 75.0 MiB 1.46 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00146279 0.00126181 0.0412226 0.0375036 75.0 MiB 1.46 75.0 MiB 0.92 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 75.0 MiB 0.18 0.130876 0.120888 75.0 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt index 260e0e2c056..3759478d8c9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 11.76 vpr 75.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77216 9 19 897 28 0 575 109 16 16 256 -1 mcnc_medium -1 -1 7102 6246 3749 356 2360 1033 75.4 MiB 10.60 0.01 5.59875 5.15754 -83.6777 -5.15754 nan 0.09 0.00367809 0.00303729 0.0800582 0.0701494 75.4 MiB 10.60 75.4 MiB 2.58 9765 17.0122 2613 4.55226 4147 20677 658214 114215 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.35541 nan -88.358 -5.35541 0 0 0.32 -1 -1 75.4 MiB 0.48 0.288075 0.253539 75.4 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.95 vpr 76.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 57 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77892 256 245 954 501 0 585 558 22 22 484 -1 mcnc_large -1 -1 7568 7468 23518 202 3225 20091 76.1 MiB 1.06 0.02 4.58215 4.06321 -789.076 -4.06321 nan 0.17 0.00395794 0.00352194 0.0546633 0.0494666 76.1 MiB 1.06 76.1 MiB 0.64 10448 17.8598 2871 4.90769 2610 5820 337031 73978 2.15576e+07 3.07196e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.29926 nan -860.162 -4.29926 0 0 0.37 -1 -1 76.1 MiB 0.29 0.21912 0.199431 76.1 MiB -1 0.17 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 34.79 vpr 105.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 284 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108284 10 10 2659 20 0 1371 304 22 22 484 -1 mcnc_large -1 -1 32736 26176 50333 12484 33100 4749 105.7 MiB 32.12 0.02 8.62387 6.83404 -65.9282 -6.83404 nan 0.15 0.0053571 0.00415525 0.333874 0.272699 105.7 MiB 32.12 105.7 MiB 4.39 39078 28.5033 10004 7.29686 9032 54400 2294214 310826 2.15576e+07 1.53059e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.03175 nan -67.1956 -7.03175 0 0 1.19 -1 -1 105.7 MiB 0.86 0.709263 0.607527 105.7 MiB -1 0.15 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 12.51 vpr 76.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78100 41 35 1006 76 0 566 161 16 16 256 -1 mcnc_medium -1 -1 7257 6649 5842 273 2922 2647 76.3 MiB 11.37 0.02 5.58018 4.9431 -137.944 -4.9431 nan 0.09 0.00696141 0.00638215 0.115593 0.094552 76.3 MiB 11.37 76.3 MiB 2.39 10043 17.7438 2739 4.83922 3885 20440 636556 113525 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.06598 nan -144.027 -5.06598 0 0 0.35 -1 -1 76.3 MiB 0.47 0.340764 0.297617 76.3 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.47 vpr 72.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74648 9 19 897 28 0 573 109 16 16 256 -1 mcnc_medium -1 -1 6908 6255 4529 398 2936 1195 72.9 MiB 3.99 0.00 5.79498 4.95412 -82.8956 -4.95412 nan 0.04 0.00131961 0.00114781 0.0384284 0.0351556 72.9 MiB 3.99 72.9 MiB 0.98 9742 17.0315 2618 4.57692 4440 22553 733607 128435 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.29908 nan -85.521 -5.29908 0 0 0.11 -1 -1 72.9 MiB 0.20 0.12869 0.118081 72.9 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.82 vpr 74.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75844 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7554 7460 5137 56 892 4189 74.1 MiB 0.43 0.01 5.01539 4.43785 -787.81 -4.43785 nan 0.05 0.00191044 0.00178051 0.0139785 0.0135099 74.1 MiB 0.43 74.1 MiB 0.31 10209 17.4812 2812 4.81507 2325 5207 293343 64225 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 16 47664 245996 -1 4.5769 nan -866.798 -4.5769 0 0 0.13 -1 -1 74.1 MiB 0.13 0.0965434 0.0922593 74.1 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 17.00 vpr 103.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 281 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106276 10 10 2659 20 0 1385 301 22 22 484 -1 mcnc_large -1 -1 32437 26329 47677 11320 31685 4672 103.8 MiB 15.55 0.01 7.86298 6.97012 -66.6328 -6.97012 nan 0.11 0.00394585 0.0031393 0.234275 0.197015 103.8 MiB 15.55 103.8 MiB 3.13 39327 28.3949 10114 7.30253 9446 56175 2430685 325649 2.15576e+07 1.51442e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.25735 nan -68.7995 -7.25735 0 0 0.36 -1 -1 103.8 MiB 0.66 0.518833 0.45621 103.8 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.58 vpr 74.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76560 41 35 1006 76 0 564 161 16 16 256 -1 mcnc_medium -1 -1 7552 6671 7590 431 3792 3367 74.8 MiB 4.11 0.00 5.51469 5.01871 -140.744 -5.01871 nan 0.04 0.00145908 0.00126433 0.0433791 0.0394286 74.8 MiB 4.11 74.8 MiB 0.92 10043 17.8067 2733 4.84574 3791 19758 636928 113707 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.42495 nan -150.307 -5.42495 0 0 0.11 -1 -1 74.8 MiB 0.18 0.135187 0.124838 74.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt index e9dd4dbf472..595d1c891b5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.77 vpr 75.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77552 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.7 MiB 3.65 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00374471 0.00311178 0.0942637 0.0815881 75.7 MiB 3.65 75.7 MiB 2.54 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.7 MiB 0.49 0.296978 0.264335 75.7 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.14 0.0035648 0.00318679 0.0499558 0.0460383 76.2 MiB 0.98 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.2 MiB 0.27 0.197871 0.183716 76.2 MiB -1 0.14 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.47 vpr 105.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108040 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.5 MiB 12.86 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.29 0.0116739 0.00965721 0.534688 0.455619 105.5 MiB 12.86 105.5 MiB 7.17 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.12 -1 -1 105.5 MiB 1.62 1.25142 1.10117 105.5 MiB -1 0.28 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.88 vpr 76.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78644 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.64 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00418085 0.00352692 0.113479 0.0974767 76.8 MiB 3.64 76.8 MiB 2.34 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.8 MiB 0.56 0.365085 0.323172 76.8 MiB -1 0.10 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.97 vpr 74.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75872 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 74.1 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00130604 0.00113413 0.0402888 0.0368028 74.1 MiB 1.50 74.1 MiB 1.00 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 74.1 MiB 0.20 0.127636 0.117479 74.1 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 74.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76432 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.6 MiB 0.45 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00183319 0.00172495 0.025168 0.0240182 74.6 MiB 0.45 74.6 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 74.6 MiB 0.13 0.104876 0.100044 74.6 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.98 vpr 103.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106232 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.7 MiB 5.57 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00463595 0.00382536 0.20651 0.174564 103.7 MiB 5.57 103.7 MiB 3.01 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.7 MiB 0.62 0.493598 0.436694 103.7 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.96 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76684 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 74.9 MiB 1.49 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00152566 0.00131828 0.0432798 0.0392071 74.9 MiB 1.49 74.9 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 74.9 MiB 0.18 0.133178 0.122788 74.9 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt index c179a99eb71..71bbbe6525b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.02 vpr 75.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77392 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.80 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.10 0.00366255 0.00300248 0.0988722 0.0856346 75.6 MiB 3.80 75.6 MiB 2.67 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.58 0.329873 0.296269 75.6 MiB -1 0.10 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77908 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.1 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00361625 0.00323438 0.0481778 0.0440548 76.1 MiB 0.98 76.1 MiB 0.62 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.1 MiB 0.27 0.193703 0.179342 76.1 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.93 vpr 105.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108228 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 13.43 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.25 0.0114469 0.00942196 0.523317 0.437298 105.7 MiB 13.43 105.7 MiB 7.67 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.08 -1 -1 105.7 MiB 1.54 1.21056 1.05802 105.7 MiB -1 0.25 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.95 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.9 MiB 3.70 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00501429 0.0044287 0.113755 0.0975648 76.9 MiB 3.70 76.9 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.9 MiB 0.54 0.357802 0.31714 76.9 MiB -1 0.11 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.98 vpr 73.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75432 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.7 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00133748 0.00116259 0.0408496 0.0373615 73.7 MiB 1.50 73.7 MiB 1.00 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.7 MiB 0.20 0.128419 0.118238 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.91 vpr 74.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76048 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.3 MiB 0.47 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00308404 0.00296931 0.0300262 0.0287318 74.3 MiB 0.47 74.3 MiB 0.32 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.15 -1 -1 74.3 MiB 0.14 0.119217 0.113274 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.93 vpr 103.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106308 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.8 MiB 5.52 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00404456 0.00321972 0.199444 0.168625 103.8 MiB 5.52 103.8 MiB 3.00 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.8 MiB 0.62 0.481167 0.426392 103.8 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.94 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77068 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 75.3 MiB 1.47 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00148096 0.00128726 0.0413364 0.0376351 75.3 MiB 1.47 75.3 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 75.3 MiB 0.18 0.131688 0.121582 75.3 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt index 5bcf12189e9..f73f554221f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.03 vpr 75.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 114 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77596 9 19 897 28 0 606 142 16 16 256 -1 mcnc_medium -1 -1 6550 6536 3472 155 2648 669 75.8 MiB 3.88 0.01 5.7154 5.4597 -89.3112 -5.4597 nan 0.10 0.00370216 0.00307222 0.0661479 0.0591146 75.8 MiB 3.88 75.8 MiB 2.88 10481 17.3240 2782 4.59835 4539 23483 740476 125213 1.05632e+07 6.14392e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72947 nan -94.1462 -5.72947 0 0 0.32 -1 -1 75.8 MiB 0.50 0.310788 0.282654 75.8 MiB -1 0.10 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.32 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 179 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78468 256 245 954 501 0 742 680 22 22 484 -1 mcnc_large -1 -1 9274 7572 60460 2284 20333 37843 76.6 MiB 2.36 0.02 5.23911 4.2903 -840.323 -4.2903 nan 0.13 0.00384619 0.00344153 0.09353 0.0842417 76.6 MiB 2.36 76.6 MiB 1.70 11049 14.8908 3078 4.14825 2733 6987 297544 68761 2.15576e+07 9.64703e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.65189 nan -884.263 -4.65189 0 0 0.41 -1 -1 76.6 MiB 0.28 0.244915 0.224675 76.6 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.12 vpr 106.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108712 10 10 2659 20 0 1430 382 22 22 484 -1 mcnc_large -1 -1 30097 26681 50242 8485 37651 4106 106.2 MiB 14.49 0.06 9.5895 7.11784 -67.5602 -7.11784 nan 0.29 0.0120588 0.0101618 0.577448 0.487406 106.2 MiB 14.49 106.2 MiB 8.21 40770 28.5105 10462 7.31608 8938 61030 2640427 332495 2.15576e+07 1.95096e+07 3.51389e+06 7260.09 17 64568 594370 -1 7.68543 nan -70.9452 -7.68543 0 0 1.09 -1 -1 106.2 MiB 1.70 1.23429 1.08029 106.2 MiB -1 0.29 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.65 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 124 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 665 200 16 16 256 -1 mcnc_medium -1 -1 8699 7144 11296 577 6471 4248 76.9 MiB 4.33 0.02 6.42009 5.14527 -151.192 -5.14527 nan 0.09 0.0040038 0.00343256 0.111382 0.0964207 76.9 MiB 4.33 76.9 MiB 3.06 11808 17.7564 3134 4.71278 5035 27959 918932 152826 1.05632e+07 6.68286e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.4847 nan -160.203 -5.4847 0 0 0.34 -1 -1 76.9 MiB 0.64 0.362116 0.322037 76.9 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.31 vpr 73.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 119 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75768 9 19 897 28 0 656 147 16 16 256 -1 mcnc_medium -1 -1 9465 7387 7500 653 5233 1614 74.0 MiB 1.83 0.00 6.84375 5.63197 -90.064 -5.63197 nan 0.04 0.00131708 0.00113824 0.0411484 0.0370479 74.0 MiB 1.83 74.0 MiB 1.31 11218 17.1267 2998 4.57710 4710 22969 767847 128278 1.05632e+07 6.41339e+06 1.26944e+06 4958.75 18 28900 206586 -1 6.05963 nan -96.1476 -6.05963 0 0 0.11 -1 -1 74.0 MiB 0.20 0.126178 0.115644 74.0 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.42 vpr 74.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 179 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76388 256 245 954 501 0 743 680 22 22 484 -1 mcnc_large -1 -1 9276 7596 60460 2199 20502 37759 74.6 MiB 1.03 0.01 5.23911 4.36438 -841.143 -4.36438 nan 0.05 0.00189527 0.00178544 0.0499427 0.0473007 74.6 MiB 1.03 74.6 MiB 0.79 10985 14.7847 3053 4.10902 2501 6468 260198 59947 2.15576e+07 9.64703e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.95172 nan -902.835 -4.95172 0 0 0.13 -1 -1 74.6 MiB 0.12 0.126567 0.120415 74.6 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 7.71 vpr 103.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106412 10 10 2659 20 0 1387 386 22 22 484 -1 mcnc_large -1 -1 28407 25969 52334 9214 38970 4150 103.9 MiB 6.23 0.01 8.84225 6.87893 -67.3793 -6.87893 nan 0.11 0.00413268 0.00332707 0.201364 0.170726 103.9 MiB 6.23 103.9 MiB 3.63 40223 29.0000 10345 7.45854 8587 59599 2538983 323136 2.15576e+07 1.97252e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.19431 nan -69.2992 -7.19431 0 0 0.36 -1 -1 103.9 MiB 0.68 0.492176 0.435586 103.9 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 2.43 vpr 75.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 125 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76868 41 35 1006 76 0 665 201 16 16 256 -1 mcnc_medium -1 -1 9806 7711 9021 479 5180 3362 75.1 MiB 1.93 0.00 7.51244 5.32876 -152.164 -5.32876 nan 0.04 0.00142804 0.00124551 0.0391378 0.0356815 75.1 MiB 1.93 75.1 MiB 1.39 12022 18.0782 3251 4.88872 4219 22486 741180 125076 1.05632e+07 6.73675e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.72072 nan -160.849 -5.72072 0 0 0.11 -1 -1 75.1 MiB 0.19 0.127975 0.117992 75.1 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt index e8dd91ee6ae..52747da9fdc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt @@ -1,6 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 25.85 vpr 83.03 MiB -1 -1 18.57 47636 3 1.01 -1 -1 38980 -1 -1 48 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85020 196 193 800 0 1 594 438 20 20 400 -1 vtr_extra_small -1 -1 4169 3142 106806 24519 69152 13135 83.0 MiB 3.45 0.01 2.78642 2.3599 -1119.38 -2.3599 2.3599 0.11 0.00336886 0.00290601 0.267623 0.235425 83.0 MiB 3.45 83.0 MiB 1.54 5164 8.82735 1542 2.63590 1808 2713 166829 48700 2.07112e+07 3.13491e+06 1.26946e+06 3173.65 11 38988 203232 -1 2.79177 2.79177 -1205.37 -2.79177 0 0 0.33 -1 -1 83.0 MiB 0.20 0.427611 0.384897 83.0 MiB -1 0.11 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.71 vpr 77.02 MiB -1 -1 0.44 22136 3 0.13 -1 -1 37044 -1 -1 68 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78864 99 130 264 0 1 227 298 20 20 400 -1 vtr_extra_small -1 -1 1534 732 61988 20558 27121 14309 77.0 MiB 1.17 0.01 1.84094 1.63182 -117.029 -1.63182 1.63182 0.10 0.00116098 0.00102609 0.0719437 0.0636329 77.0 MiB 1.17 77.0 MiB 0.48 1289 7.67262 408 2.42857 432 671 35594 10787 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 12 39388 210115 -1 2.0326 2.0326 -137.711 -2.0326 0 0 0.32 -1 -1 77.0 MiB 0.12 0.146262 0.115522 77.0 MiB -1 0.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 45.09 vpr 132.19 MiB -1 -1 6.50 65292 8 5.27 -1 -1 44656 -1 -1 246 385 2 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 135364 385 362 3324 0 1 2378 996 30 30 900 -1 vtr_small -1 -1 45961 31243 503168 167206 308523 27439 132.2 MiB 27.49 0.08 11.3485 9.24445 -10104.3 -9.24445 9.24445 0.52 0.0110533 0.00983869 1.90464 1.67809 132.2 MiB 27.49 132.2 MiB 14.11 42437 17.9590 11048 4.67541 10359 33405 1843617 333376 4.8774e+07 1.47499e+07 6.56785e+06 7297.61 17 120772 1084977 -1 9.50495 9.50495 -10508.2 -9.50495 0 0 2.27 -1 -1 132.2 MiB 0.99 2.49904 2.2274 132.2 MiB -1 0.52 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.73 vpr 86.61 MiB -1 -1 3.85 35472 16 0.66 -1 -1 39332 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88684 45 32 936 0 1 764 142 20 20 400 -1 vtr_extra_small -1 -1 7941 6580 16792 4505 10418 1869 86.6 MiB 7.12 0.02 11.8934 10.8778 -6730.96 -10.8778 10.8778 0.15 0.00604523 0.0052746 0.299411 0.249607 86.6 MiB 7.12 86.6 MiB 4.84 11265 14.8029 2859 3.75690 3304 9224 705116 168424 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 16 44576 305072 -1 11.1238 11.1238 -7296.13 -11.1238 0 0 0.55 -1 -1 86.6 MiB 0.49 0.557197 0.483674 86.6 MiB -1 0.15 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.92 vpr 76.71 MiB -1 -1 0.85 26400 4 0.19 -1 -1 36732 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78556 11 2 140 0 2 80 28 20 20 400 -1 vtr_extra_small -1 -1 371 277 994 274 621 99 76.7 MiB 0.79 0.00 2.14417 2.10685 -170.205 -2.10685 1.95087 0.09 0.000829747 0.000696435 0.0253099 0.0218497 76.7 MiB 0.79 76.7 MiB 0.47 484 6.54054 125 1.68919 154 271 5642 1534 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.24362 1.99822 -177.023 -2.24362 0 0 0.28 -1 -1 76.7 MiB 0.04 0.058266 0.0520206 76.7 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 10.90 vpr 81.36 MiB -1 -1 8.14 44968 3 0.57 -1 -1 35340 -1 -1 49 196 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 83308 196 193 800 0 1 601 439 20 20 400 -1 vtr_extra_small -1 -1 4328 3107 92124 17877 63452 10795 81.4 MiB 1.38 0.00 2.56454 2.37946 -1137.82 -2.37946 2.37946 0.04 0.00170951 0.00159049 0.108014 0.100137 81.4 MiB 1.38 81.4 MiB 0.66 5067 8.55912 1503 2.53885 1660 2444 142383 40675 2.07112e+07 3.18881e+06 1.26946e+06 3173.65 10 38988 203232 -1 2.76727 2.76727 -1220.28 -2.76727 0 0 0.11 -1 -1 81.4 MiB 0.08 0.17114 0.160292 81.4 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.23 vpr 75.47 MiB -1 -1 0.22 18468 3 0.06 -1 -1 33128 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77280 99 130 264 0 1 226 298 20 20 400 -1 vtr_extra_small -1 -1 998 719 42088 12988 22077 7023 75.5 MiB 0.51 0.00 2.00298 1.89487 -117.095 -1.89487 1.89487 0.04 0.000568785 0.000532954 0.0270668 0.0254536 75.5 MiB 0.51 75.5 MiB 0.25 1273 7.62275 391 2.34132 403 645 32624 10084 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 11 39388 210115 -1 2.02782 2.02782 -132.929 -2.02782 0 0 0.12 -1 -1 75.5 MiB 0.03 0.0466214 0.0438046 75.5 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 18.99 vpr 130.75 MiB -1 -1 2.93 61476 8 2.72 -1 -1 42296 -1 -1 244 385 2 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 133892 385 362 3324 0 1 2373 994 30 30 900 -1 vtr_small -1 -1 44934 30685 486878 158175 303508 25195 130.8 MiB 10.73 0.04 10.9569 9.14069 -10026.4 -9.14069 9.14069 0.19 0.0075565 0.00697625 0.821563 0.749283 130.8 MiB 10.73 130.8 MiB 5.59 41636 17.6573 10780 4.57167 10078 33334 1771649 321112 4.8774e+07 1.46421e+07 6.56785e+06 7297.61 16 120772 1084977 -1 9.28426 9.28426 -10368.8 -9.28426 0 0 0.73 -1 -1 130.8 MiB 0.67 1.2751 1.17633 130.8 MiB -1 0.19 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.78 vpr 84.59 MiB -1 -1 1.71 32292 16 0.37 -1 -1 34988 -1 -1 59 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86620 45 32 936 0 1 764 140 20 20 400 -1 vtr_extra_small -1 -1 7967 6824 18290 3791 13097 1402 84.6 MiB 2.77 0.00 11.7422 10.6015 -6978.52 -10.6015 10.6015 0.06 0.00172166 0.00152276 0.108719 0.0971486 84.6 MiB 2.77 84.6 MiB 1.78 11182 14.6938 2948 3.87385 3523 9991 831731 205110 2.07112e+07 5.21975e+06 1.91495e+06 4787.38 14 44576 305072 -1 11.0577 11.0577 -7502.5 -11.0577 0 0 0.18 -1 -1 84.6 MiB 0.20 0.207414 0.189307 84.6 MiB -1 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.46 vpr 74.58 MiB -1 -1 0.41 22932 4 0.10 -1 -1 32968 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76368 11 2 140 0 2 81 28 20 20 400 -1 vtr_extra_small -1 -1 344 282 1246 289 767 190 74.6 MiB 0.35 0.00 2.1429 2.10685 -161.57 -2.10685 1.95087 0.04 0.000382895 0.000341958 0.0148948 0.0134952 74.6 MiB 0.35 74.6 MiB 0.22 481 6.41333 125 1.66667 162 273 5235 1511 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.13367 2.00787 -169.877 -2.13367 0 0 0.10 -1 -1 74.6 MiB 0.02 0.031341 0.0286656 74.6 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt index 9155e1a0c29..9dcd6930755 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.37 vpr 75.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 75.7 MiB 2.52 10470 18.5638 2823 5.00532 4441 21451 721238 120368 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.44204 nan -88.1999 -5.44204 0 0 0.32 -1 -1 75.7 MiB 0.45 0.190621 0.172257 75.7 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.70 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78028 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 76.2 MiB 0.61 10067 17.2380 2785 4.76884 2224 4785 262051 58317 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 14 47664 245996 -1 5.09713 nan -915.356 -5.09713 0 0 0.38 -1 -1 76.2 MiB 0.25 0.146815 0.136123 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.28 vpr 76.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78496 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 76.7 MiB 2.27 10759 18.7766 2936 5.12391 3972 20025 643838 113062 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.52727 nan -151.75 -5.52727 0 0 0.34 -1 -1 76.7 MiB 0.46 0.206081 0.184898 76.7 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.88 vpr 73.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75488 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 73.7 MiB 1.38 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.7 MiB 1.38 73.7 MiB 0.99 10384 18.5098 2834 5.05169 4200 20769 686232 118555 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.71537 nan -90.8975 -5.71537 0 0 0.11 -1 -1 73.7 MiB 0.18 0.0873879 0.0807521 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.80 vpr 74.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76432 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 74.6 MiB 0.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.6 MiB 0.35 74.6 MiB 0.31 10173 17.4195 2800 4.79452 2175 4597 261480 57693 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 19 47664 245996 -1 5.19666 nan -941.622 -5.19666 0 0 0.13 -1 -1 74.6 MiB 0.14 0.093956 0.0894993 74.6 MiB -1 0.05 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.86 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77068 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.3 MiB 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.3 MiB 1.34 75.3 MiB 0.93 11092 18.8639 3046 5.18027 4224 20724 680603 119637 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.63987 nan -156.834 -5.63987 0 0 0.11 -1 -1 75.3 MiB 0.19 0.0927209 0.0860572 75.3 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt index bd1a356f7b3..d9de69d6485 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.48 vpr 75.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77452 9 19 897 28 0 613 107 16 16 256 -1 mcnc_medium -1 -1 7227 6446 4661 444 2922 1295 75.6 MiB 3.30 0.01 5.83587 5.20235 -84.7514 -5.20235 nan 0.09 0.00365365 0.00308713 0.0953072 0.0828485 75.6 MiB 3.30 75.6 MiB 2.61 9964 16.2810 2709 4.42647 4690 20859 701687 124089 1.05632e+07 4.25763e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.47836 nan -87.8661 -5.47836 0 0 0.35 -1 -1 75.6 MiB 0.51 0.314162 0.28034 75.6 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.82 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78032 256 245 954 501 0 598 557 22 22 484 -1 mcnc_large -1 -1 8430 8247 28037 277 4264 23496 76.2 MiB 0.95 0.02 5.00844 4.05195 -786.983 -4.05195 nan 0.13 0.00372964 0.0033122 0.0643989 0.0586623 76.2 MiB 0.95 76.2 MiB 0.58 10883 18.1990 2937 4.91137 2442 5565 332488 69751 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.40791 nan -837.951 -4.40791 0 0 0.37 -1 -1 76.2 MiB 0.26 0.206289 0.19121 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.95 vpr 105.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108108 10 10 2659 20 0 1500 308 22 22 484 -1 mcnc_large -1 -1 33647 26777 51219 12453 33951 4815 105.6 MiB 12.21 0.05 7.95426 6.65363 -64.7441 -6.65363 nan 0.32 0.01158 0.00952696 0.683148 0.577318 105.6 MiB 12.21 105.6 MiB 8.23 39550 26.3667 10138 6.75867 10136 56388 2554636 337283 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.10986 nan -67.2122 -7.10986 0 0 1.12 -1 -1 105.6 MiB 1.79 1.41673 1.23449 105.6 MiB -1 0.32 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 3.96 vpr 76.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78624 41 35 1006 76 0 665 161 16 16 256 -1 mcnc_medium -1 -1 7612 6958 7590 343 3947 3300 76.8 MiB 2.84 0.02 6.23108 5.15201 -145.389 -5.15201 nan 0.09 0.00454121 0.00387629 0.099122 0.086103 76.8 MiB 2.84 76.8 MiB 2.13 10685 16.0677 2885 4.33835 4384 18462 592965 106217 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.45169 nan -154.246 -5.45169 0 0 0.32 -1 -1 76.8 MiB 0.51 0.354223 0.314944 76.8 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.79 vpr 74.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75868 9 19 897 28 0 628 108 16 16 256 -1 mcnc_medium -1 -1 7133 6654 3706 357 2411 938 74.1 MiB 1.24 0.00 5.58018 4.92812 -82.703 -4.92812 nan 0.04 0.00130258 0.00113599 0.0349201 0.0320233 74.1 MiB 1.24 74.1 MiB 0.99 10212 16.2871 2746 4.37959 5878 26871 986532 171228 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 26 28900 206586 -1 5.21469 nan -86.576 -5.21469 0 0 0.11 -1 -1 74.1 MiB 0.27 0.144906 0.13215 74.1 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.82 vpr 74.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 57 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76400 256 245 954 501 0 596 558 22 22 484 -1 mcnc_large -1 -1 8442 8222 21222 240 2369 18613 74.6 MiB 0.43 0.01 4.85109 4.26724 -789.819 -4.26724 nan 0.05 0.00183483 0.0017214 0.0271893 0.0259535 74.6 MiB 0.43 74.6 MiB 0.31 10906 18.2987 2932 4.91946 2356 5389 309032 65263 2.15576e+07 3.07196e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.73179 nan -857.452 -4.73179 0 0 0.13 -1 -1 74.6 MiB 0.12 0.0974406 0.0930916 74.6 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.00 vpr 103.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105732 10 10 2659 20 0 1510 309 22 22 484 -1 mcnc_large -1 -1 31802 27364 49377 11982 32709 4686 103.3 MiB 4.45 0.01 8.38409 6.51429 -63.2845 -6.51429 nan 0.11 0.00401015 0.00322611 0.239471 0.201148 103.3 MiB 4.45 103.3 MiB 3.22 40850 27.0530 10492 6.94834 11089 63641 3035099 392249 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 19 64568 594370 -1 6.78146 nan -65.8802 -6.78146 0 0 0.37 -1 -1 103.3 MiB 0.76 0.540944 0.474742 103.3 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.73 vpr 75.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77056 41 35 1006 76 0 678 159 16 16 256 -1 mcnc_medium -1 -1 7799 7097 7039 323 3443 3273 75.2 MiB 1.24 0.00 5.82238 4.98732 -145.614 -4.98732 nan 0.04 0.001505 0.00130537 0.0413734 0.0374728 75.2 MiB 1.24 75.2 MiB 0.95 10391 15.3260 2846 4.19764 4879 22033 706386 126210 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.2747 nan -150.182 -5.2747 0 0 0.12 -1 -1 75.2 MiB 0.20 0.139029 0.127655 75.2 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt index 353d272ff5e..e985dbf5f92 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.96 vpr 75.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77136 9 19 897 28 0 571 109 16 16 256 -1 mcnc_medium -1 -1 6849 6197 3749 306 2447 996 75.3 MiB 3.80 0.01 5.6777 5.15854 -84.4388 -5.15854 nan 0.12 0.00372518 0.00308527 0.0851251 0.0744623 75.3 MiB 3.80 75.3 MiB 2.72 9547 16.7491 2591 4.54561 4007 19117 612422 105847 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.57046 nan -89.3939 -5.57046 0 0 0.36 -1 -1 75.3 MiB 0.45 0.290389 0.260271 75.3 MiB -1 0.12 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.92 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78044 256 245 954 501 0 584 556 22 22 484 -1 mcnc_large -1 -1 7414 7336 16551 117 1750 14684 76.2 MiB 0.96 0.02 4.79868 3.95956 -780.296 -3.95956 nan 0.14 0.0037776 0.00334019 0.0431145 0.0394451 76.2 MiB 0.96 76.2 MiB 0.63 10156 17.3904 2785 4.76884 2499 5829 309976 67350 2.15576e+07 2.96417e+06 1.49107e+06 3080.73 17 47664 245996 -1 4.43922 nan -858.538 -4.43922 0 0 0.40 -1 -1 76.2 MiB 0.31 0.225991 0.20914 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.50 vpr 105.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 263 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108088 10 10 2659 20 0 1335 283 22 22 484 -1 mcnc_large -1 -1 29142 24368 34619 6112 24966 3541 105.6 MiB 14.79 0.04 8.99039 6.64595 -64.2305 -6.64595 nan 0.30 0.011351 0.00921126 0.534655 0.453947 105.6 MiB 14.79 105.6 MiB 8.92 36909 27.6472 9531 7.13933 8973 57196 2436221 318880 2.15576e+07 1.41741e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.07899 nan -66.0192 -7.07899 0 0 1.11 -1 -1 105.6 MiB 1.75 1.29851 1.13315 105.6 MiB -1 0.30 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.12 vpr 76.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78196 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7414 6419 7538 405 3643 3490 76.4 MiB 3.99 0.01 5.66659 5.10396 -142.048 -5.10396 nan 0.09 0.00395858 0.00331812 0.0974473 0.0845959 76.4 MiB 3.99 76.4 MiB 2.72 9920 17.3124 2710 4.72949 3957 20035 633461 111527 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.31293 nan -148.764 -5.31293 0 0 0.36 -1 -1 76.4 MiB 0.47 0.311907 0.278187 76.4 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.02 vpr 73.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75536 9 19 897 28 0 563 111 16 16 256 -1 mcnc_medium -1 -1 7098 5977 5165 481 3314 1370 73.8 MiB 1.56 0.00 5.87393 5.10533 -84.2691 -5.10533 nan 0.04 0.00129553 0.00112415 0.0425662 0.0388316 73.8 MiB 1.56 73.8 MiB 1.05 9429 16.7776 2543 4.52491 4233 21427 685976 119142 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.42217 nan -87.2542 -5.42217 0 0 0.11 -1 -1 73.8 MiB 0.18 0.129552 0.119237 73.8 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.82 vpr 73.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 54 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75236 256 245 954 501 0 584 555 22 22 484 -1 mcnc_large -1 -1 7542 7463 5115 58 915 4142 73.5 MiB 0.43 0.01 5.52179 4.5111 -812.738 -4.5111 nan 0.05 0.00187057 0.00175451 0.014083 0.0136228 73.5 MiB 0.43 73.5 MiB 0.31 10180 17.4315 2798 4.79110 2290 5418 289765 61404 2.15576e+07 2.91028e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.73551 nan -877.111 -4.73551 0 0 0.13 -1 -1 73.5 MiB 0.11 0.0874376 0.08384 73.5 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 7.39 vpr 103.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 269 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105864 10 10 2659 20 0 1330 289 22 22 484 -1 mcnc_large -1 -1 29067 24555 40399 8417 28233 3749 103.4 MiB 5.92 0.01 8.57662 6.48829 -62.7527 -6.48829 nan 0.11 0.00410389 0.00328836 0.220573 0.18529 103.4 MiB 5.92 103.4 MiB 3.36 37342 28.0767 9643 7.25038 9194 59469 2527516 336331 2.15576e+07 1.44975e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.74005 nan -65.3498 -6.74005 0 0 0.36 -1 -1 103.4 MiB 0.67 0.506692 0.445776 103.4 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 2.01 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76688 41 35 1006 76 0 592 159 16 16 256 -1 mcnc_medium -1 -1 7434 6630 6609 294 3295 3020 74.9 MiB 1.52 0.00 5.72346 5.17082 -143.976 -5.17082 nan 0.04 0.00140043 0.0012182 0.0394494 0.0360877 74.9 MiB 1.52 74.9 MiB 0.98 9848 16.6351 2709 4.57601 4387 22649 730292 125901 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.09467 nan -146.142 -5.09467 0 0 0.11 -1 -1 74.9 MiB 0.20 0.135638 0.125011 74.9 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt index d7bb035e33d..493089933c3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 24.78 vpr 83.23 MiB -1 -1 18.50 47880 3 1.03 -1 -1 38848 -1 -1 50 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85228 196 193 800 389 1 591 440 20 20 400 -1 vtr_extra_small -1 -1 3715 3554 3784 38 823 2923 83.2 MiB 2.24 0.02 2.85588 2.57265 -1175.96 -2.57265 2.57265 0.10 0.00362627 0.00313967 0.0281499 0.026191 83.2 MiB 2.24 83.2 MiB 1.59 5468 9.39519 1600 2.74914 1643 2642 175568 48502 2.07112e+07 3.2427e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.92546 2.92546 -1279.3 -2.92546 0 0 0.33 -1 -1 83.2 MiB 0.23 0.194282 0.17603 83.2 MiB -1 0.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.30 vpr 77.05 MiB -1 -1 0.46 21648 3 0.11 -1 -1 36796 -1 -1 69 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78904 99 130 240 229 1 219 299 20 20 400 -1 vtr_extra_small -1 -1 897 855 16283 1900 1766 12617 77.1 MiB 0.85 0.01 1.95754 1.93615 -150.064 -1.93615 1.93615 0.10 0.00114824 0.00101953 0.0225391 0.0202679 77.1 MiB 0.85 77.1 MiB 0.55 1415 8.84375 420 2.62500 390 656 29567 8292 2.07112e+07 4.26669e+06 1.31074e+06 3276.84 10 39388 210115 -1 1.99132 1.99132 -170.793 -1.99132 0 0 0.34 -1 -1 77.1 MiB 0.05 0.0576019 0.0526431 77.1 MiB -1 0.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.74 vpr 86.56 MiB -1 -1 3.84 35864 16 0.69 -1 -1 39076 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88636 45 32 936 77 1 765 142 20 20 400 -1 vtr_extra_small -1 -1 7990 6993 2362 101 1016 1245 86.6 MiB 6.20 0.02 12.1921 10.5297 -7133.55 -10.5297 10.5297 0.16 0.00556384 0.00434574 0.083545 0.0720334 86.6 MiB 6.20 86.6 MiB 4.77 11420 14.9869 2979 3.90945 3498 9480 737557 180691 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 14 44576 305072 -1 10.8282 10.8282 -7490.44 -10.8282 0 0 0.55 -1 -1 86.6 MiB 0.48 0.322984 0.290732 86.6 MiB -1 0.16 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.69 vpr 76.73 MiB -1 -1 0.87 26256 4 0.17 -1 -1 36604 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 11 2 140 13 2 79 28 20 20 400 -1 vtr_extra_small -1 -1 425 276 658 98 289 271 76.7 MiB 0.68 0.00 2.38519 2.10685 -169.375 -2.10685 1.95087 0.09 0.000833002 0.000701647 0.018572 0.0162134 76.7 MiB 0.68 76.7 MiB 0.44 404 5.53425 120 1.64384 174 291 5454 1630 2.07112e+07 808410 1.12964e+06 2824.09 11 37792 180905 -1 2.17742 1.95241 -171.997 -2.17742 0 0 0.30 -1 -1 76.7 MiB 0.04 0.0564754 0.0510591 76.7 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 10.47 vpr 81.20 MiB -1 -1 8.11 45204 3 0.57 -1 -1 35608 -1 -1 50 196 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 83148 196 193 800 389 1 589 440 20 20 400 -1 vtr_extra_small -1 -1 3998 3782 18832 248 3091 15493 81.2 MiB 0.98 0.00 2.85588 2.47185 -1156.3 -2.47185 2.47185 0.04 0.00172364 0.00159607 0.0308341 0.0290834 81.2 MiB 0.98 81.2 MiB 0.63 5632 9.71035 1634 2.81724 1596 2379 162444 45554 2.07112e+07 3.2427e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.84177 2.84177 -1268.87 -2.84177 0 0 0.12 -1 -1 81.2 MiB 0.09 0.105167 0.0996991 81.2 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.08 vpr 75.51 MiB -1 -1 0.22 18464 3 0.06 -1 -1 33404 -1 -1 69 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77320 99 130 240 229 1 222 299 20 20 400 -1 vtr_extra_small -1 -1 1001 943 16283 1928 655 13700 75.5 MiB 0.37 0.00 1.95754 1.93615 -151.243 -1.93615 1.93615 0.04 0.000568044 0.000533906 0.0123779 0.0117131 75.5 MiB 0.37 75.5 MiB 0.24 1463 8.97546 433 2.65644 390 644 29549 8534 2.07112e+07 4.26669e+06 1.31074e+06 3276.84 9 39388 210115 -1 1.99132 1.99132 -165.748 -1.99132 0 0 0.12 -1 -1 75.5 MiB 0.02 0.0304031 0.0286853 75.5 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.50 vpr 84.02 MiB -1 -1 1.72 32292 16 0.36 -1 -1 35064 -1 -1 59 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86032 45 32 936 77 1 764 140 20 20 400 -1 vtr_extra_small -1 -1 8308 6790 6311 196 3112 3003 84.0 MiB 2.52 0.00 11.697 10.6608 -7088.74 -10.6608 10.6608 0.06 0.00172403 0.00151742 0.0484196 0.0441323 84.0 MiB 2.52 84.0 MiB 1.83 11366 14.9356 2988 3.92641 3444 9377 809880 202958 2.07112e+07 5.21975e+06 1.91495e+06 4787.38 14 44576 305072 -1 10.968 10.968 -7522.1 -10.968 0 0 0.18 -1 -1 84.0 MiB 0.19 0.146169 0.135428 84.0 MiB -1 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.39 vpr 74.81 MiB -1 -1 0.41 22692 4 0.10 -1 -1 32956 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76604 11 2 140 13 2 79 28 20 20 400 -1 vtr_extra_small -1 -1 441 361 112 19 45 48 74.8 MiB 0.32 0.00 2.32519 2.16196 -166.836 -2.16196 1.97742 0.04 0.000403733 0.000348452 0.00435748 0.00414137 74.8 MiB 0.32 74.8 MiB 0.21 486 6.65753 142 1.94521 190 278 5599 1612 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.17143 1.9491 -169.271 -2.17143 0 0 0.10 -1 -1 74.8 MiB 0.02 0.0211176 0.0196106 74.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 37ed89929f5..2c66d16fd32 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 1.86 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.08 0.000682102 0.000589331 0.0191204 0.0168271 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.92 0.219017 0.188624 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.09 0.03 -1 -1 0.01 0.0322472 0.0293972 - k4_n4_v7_longline_bidir.xml styr.blif common 1.71 vpr 60.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61932 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.08 1219 4247 600 3483 164 60.5 MiB 0.06 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000822212 0.000745517 0.0200899 0.0175819 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.71 0.217702 0.191181 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.11 0.03 -1 -1 0.02 0.0360271 0.0325274 - k4_n4_v7_l1_bidir.xml styr.blif common 2.28 vpr 61.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62500 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1285 7613 1616 5547 450 61.0 MiB 0.11 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.00083663 0.000735935 0.0404209 0.0365528 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.11 0.183783 0.164876 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0404434 0.0363816 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61916 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.09 1234 4643 666 3821 156 60.5 MiB 0.06 0.00 3.51175 -43.7413 -3.51175 3.51175 0.10 0.000796689 0.00069941 0.0254117 0.0229956 -1 -1 -1 -1 16 1911 27 2.43e+06 2.07e+06 -1 -1 2.14 0.308921 0.270668 3522 30407 -1 1965 30 1263 4698 759011 126866 28.7744 28.7744 -241.883 -28.7744 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0527885 0.0460513 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml styr.blif common 0.99 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1341 4439 719 3525 195 59.0 MiB 0.03 0.00 8.75156 5.95188 -76.2362 -5.95188 5.95188 0.03 0.000369091 0.000332668 0.0100569 0.0091901 -1 -1 -1 -1 14 2179 38 2.43e+06 2.16e+06 -1 -1 0.45 0.0941641 0.0811795 3402 27531 -1 1923 17 1033 3494 176707 22465 7.58177 7.58177 -95.383 -7.58177 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0164104 0.0147275 +k4_n4_v7_longline_bidir.xml styr.blif common 0.93 vpr 58.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60084 10 10 253 263 1 171 92 11 11 121 clb auto 19.5 MiB 0.03 1829 1318 3611 426 3020 165 58.7 MiB 0.02 0.00 5.19817 4.47516 -54.2373 -4.47516 4.47516 0.04 0.000369472 0.000337461 0.00887057 0.00812854 -1 -1 -1 -1 17 2528 41 2.43e+06 2.16e+06 -1 -1 0.36 0.0873451 0.075572 3202 31699 -1 2252 25 1472 4968 313575 40767 9.40236 9.40236 -107.704 -9.40236 0 0 -1 -1 0.01 0.06 0.01 -1 -1 0.01 0.0212313 0.0188588 +k4_n4_v7_l1_bidir.xml styr.blif common 1.05 vpr 58.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59704 10 10 253 263 1 171 92 11 11 121 clb auto 19.1 MiB 0.03 1829 1340 8579 1857 6361 361 58.3 MiB 0.04 0.00 11.3865 6.30908 -81.1511 -6.30908 6.30908 0.04 0.000366977 0.000330995 0.0174482 0.0159247 -1 -1 -1 -1 11 1565 28 2.43e+06 2.16e+06 -1 -1 0.45 0.0856261 0.0746974 4842 26035 -1 1365 23 1309 5061 314893 55846 8.55913 8.55913 -101.511 -8.55913 0 0 -1 -1 0.00 0.06 0.01 -1 -1 0.00 0.0198322 0.0175973 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.29 vpr 59.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60520 10 10 253 263 1 171 92 11 11 121 clb auto 19.6 MiB 0.03 1829 1326 4025 528 3322 175 59.1 MiB 0.02 0.00 4.50889 3.47884 -44.786 -3.47884 3.47884 0.03 0.000378131 0.000339956 0.00936549 0.00859198 -1 -1 -1 -1 16 2193 28 2.43e+06 2.16e+06 -1 -1 0.67 0.09289 0.0804764 3522 30407 -1 2061 19 1236 4213 766518 139225 14.4125 14.4125 -146.898 -14.4125 0 0 -1 -1 0.00 0.12 0.01 -1 -1 0.00 0.017958 0.0160944 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 99bb28a8269..1eefaffbf17 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 2.33 vpr 66.02 MiB -1 -1 0.85 26768 5 0.17 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000423798 0.000369821 0.00844968 0.00761151 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.19 0.07328 0.0645326 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.03 0.01 -1 -1 0.00 0.0168546 0.0152174 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.62 vpr 65.81 MiB -1 -1 0.84 26884 5 0.22 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67392 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.05 152 432 67 335 30 65.8 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.05 0.000430785 0.000371967 0.00760808 0.00673261 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.40 0.162173 0.135998 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.05 0.01 -1 -1 0.00 0.0294148 0.0268014 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.34 vpr 64.70 MiB -1 -1 0.42 23428 5 0.11 -1 -1 33000 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 151 500 122 353 25 64.7 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000227544 0.000206917 0.00459824 0.0042382 -1 -1 -1 -1 12 169 17 646728 646728 19965.4 554.594 0.05 0.0320813 0.0276697 1696 3924 -1 165 16 218 500 9678 3037 2.12594 2.12594 -92.801 -2.12594 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.010025 0.0089725 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.40 vpr 64.32 MiB -1 -1 0.42 23432 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 151 500 122 353 25 64.3 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000220507 0.000200662 0.0045838 0.00422736 -1 -1 -1 -1 12 169 17 646728 646728 19965.4 554.594 0.12 0.0664389 0.0562702 1696 3924 -1 165 16 218 500 9678 3037 2.12594 2.12594 -92.801 -2.12594 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.00984711 0.00881128 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt index 5d7f440c1da..9b9daa1ca9d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 2.91 vpr 67.98 MiB -1 -1 0.40 22276 3 0.11 -1 -1 36796 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69616 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.20 0.00 1.86472 -118.834 -1.86472 1.86472 0.22 0.000979117 0.000879056 0.0638803 0.0581045 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.56 0.199818 0.181639 12522 62564 -1 1120 9 399 643 21323 6785 1.90702 1.90702 -133.259 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.0304906 0.0285332 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 1.68 vpr 66.70 MiB -1 -1 0.22 18444 3 0.06 -1 -1 33084 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68304 99 130 344 474 1 228 298 12 12 144 clb auto 26.7 MiB 0.11 1675 704 66963 20370 32791 13802 66.7 MiB 0.12 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000559141 0.000523608 0.0432041 0.0404375 -1 -1 -1 -1 40 1452 18 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.16437 0.150951 12666 64609 -1 1219 12 447 673 30224 10238 2.02932 2.02932 -138.474 -2.02932 -0.424985 -0.298787 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0190203 0.0177879 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt index c1c20666920..62bfe78ec62 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.54 vpr 67.39 MiB -1 -1 0.42 22156 3 0.16 -1 -1 36544 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69008 99 130 344 474 1 225 301 13 13 169 clb auto 27.8 MiB 0.09 709 69853 20089 36202 13562 67.4 MiB 0.23 0.00 2.16096 -124.938 -2.16096 2.16096 0.29 0.000913323 0.000821579 0.0687918 0.0619499 -1 -1 -1 -1 30 1301 10 6.63067e+06 4.37447e+06 308771. 1827.05 1.05 0.343222 0.313014 11444 57198 -1 1153 11 545 813 32907 9964 1.99803 1.99803 -136.313 -1.99803 -0.30784 -0.0857401 382024. 2260.50 0.04 0.06 0.10 -1 -1 0.04 0.0301423 0.0279655 - k6_N10_mem32K_40nm.xml diffeq1.v common 13.02 vpr 70.71 MiB -1 -1 0.61 26808 15 0.59 -1 -1 38128 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72412 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 31.1 MiB 0.36 5686 93732 25708 60129 7895 70.7 MiB 0.92 0.01 21.5854 -1586.88 -21.5854 21.5854 0.47 0.00359311 0.00328994 0.373845 0.344857 -1 -1 -1 -1 42 11019 36 1.21132e+07 5.26753e+06 637230. 2489.18 7.15 1.94736 1.79599 20148 122574 -1 9118 25 3874 8580 1140724 318272 22.5245 22.5245 -1660.58 -22.5245 0 0 799729. 3123.94 0.07 0.71 0.15 -1 -1 0.07 0.298338 0.280888 - k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB -1 -1 0.11 20620 1 0.02 -1 -1 33040 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0264e-05 6.201e-06 6.8769e-05 4.6066e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00116982 0.00111262 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106891 0.001042 - k6_N10_mem32K_40nm.xml single_ff.v common 0.54 vpr 65.06 MiB -1 -1 0.09 21000 1 0.02 -1 -1 33296 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66620 2 1 3 4 1 3 4 3 3 9 -1 auto 26.6 MiB 0.00 6 9 3 5 1 65.1 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.01 2.0617e-05 1.4741e-05 0.000141684 0.000107774 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00168512 0.00158841 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00172391 0.0016612 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.58 vpr 67.37 MiB -1 -1 0.39 22284 3 0.08 -1 -1 36712 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68984 99 130 344 474 1 225 301 19 19 361 o auto 27.9 MiB 0.07 850 78925 21699 38013 19213 67.4 MiB 0.30 0.00 2.16428 -129.737 -2.16428 2.16428 1.74 0.000907451 0.000818758 0.097179 0.0888059 -1 -1 -1 -1 36 1162 10 1.79173e+07 4.37447e+06 833707. 2309.44 1.42 0.329975 0.298327 24998 161561 -1 1074 10 581 868 36231 9318 1.99581 1.99581 -134.677 -1.99581 -0.182839 -0.0660558 1.02328e+06 2834.56 0.12 0.05 0.23 -1 -1 0.12 0.0286893 0.0266338 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 20.39 vpr 77.82 MiB -1 -1 0.54 26812 15 0.47 -1 -1 38260 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79688 162 96 1009 950 1 665 324 24 24 576 i auto 30.8 MiB 0.33 7393 99292 28927 58867 11498 77.8 MiB 1.03 0.02 21.7254 -1657.33 -21.7254 21.7254 3.05 0.00462453 0.00428627 0.416981 0.375188 -1 -1 -1 -1 38 12380 31 3.08128e+07 5.26753e+06 1.42563e+06 2475.05 11.34 2.12533 1.94729 42274 284153 -1 10868 19 3672 8078 1198132 301968 22.4983 22.4983 -1725.65 -22.4983 0 0 1.79535e+06 3116.93 0.13 0.60 0.50 -1 -1 0.13 0.215504 0.199648 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.51 vpr 65.29 MiB -1 -1 0.10 20720 1 0.02 -1 -1 33044 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1044e-05 6.598e-06 7.3231e-05 5.0487e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00113801 0.00107607 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.00158495 0.00154688 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.64 vpr 65.29 MiB -1 -1 0.10 20876 1 0.03 -1 -1 33324 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 2 1 3 4 1 3 4 4 4 16 i auto 27.0 MiB 0.00 7 9 0 1 8 65.3 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.4352e-05 9.526e-06 0.000103801 7.6571e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00161569 0.00152133 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00155787 0.00150496 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.49 vpr 66.48 MiB -1 -1 0.22 18824 3 0.06 -1 -1 33092 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68076 99 130 344 474 1 224 302 13 13 169 clb auto 26.8 MiB 0.04 1746 762 68106 19514 34631 13961 66.5 MiB 0.11 0.00 2.21168 1.87164 -122.901 -1.87164 1.87164 0.11 0.000545151 0.000510762 0.0399859 0.0374705 -1 -1 -1 -1 32 1396 14 6.63067e+06 4.42837e+06 323148. 1912.12 0.21 0.10715 0.0986602 11612 59521 -1 1378 10 517 775 49020 15288 2.04417 2.04417 -145.25 -2.04417 -0.103145 -0.0426347 396943. 2348.77 0.01 0.03 0.03 -1 -1 0.01 0.0162028 0.0151156 +k6_N10_mem32K_40nm.xml diffeq1.v common 4.73 vpr 69.38 MiB -1 -1 0.32 23428 15 0.29 -1 -1 34064 -1 -1 61 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71040 162 96 1009 950 1 667 324 16 16 256 mult_36 auto 29.7 MiB 0.16 9690 5422 80388 23076 51132 6180 69.4 MiB 0.32 0.01 24.8942 21.9154 -1692.2 -21.9154 21.9154 0.18 0.0016374 0.00152032 0.126843 0.118121 -1 -1 -1 -1 40 11149 48 1.21132e+07 5.26753e+06 612675. 2393.26 2.18 0.566686 0.523646 19892 118481 -1 8842 23 4046 9257 1093658 327616 22.4259 22.4259 -1741.35 -22.4259 0 0 771607. 3014.09 0.02 0.23 0.07 -1 -1 0.02 0.0905548 0.0850156 +k6_N10_mem32K_40nm.xml single_wire.v common 0.53 vpr 63.50 MiB -1 -1 0.07 17288 1 0.02 -1 -1 29952 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 1 1 1 2 0 1 2 3 3 9 -1 auto 25.2 MiB 0.00 2 2 3 0 3 0 63.5 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.533e-06 3.577e-06 5.4316e-05 3.6591e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000899985 0.000839888 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000879513 0.000848701 +k6_N10_mem32K_40nm.xml single_ff.v common 0.53 vpr 63.50 MiB -1 -1 0.07 17292 1 0.02 -1 -1 29972 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65020 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 6 6 9 3 5 1 63.5 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 1.9086e-05 1.5272e-05 8.8302e-05 6.8383e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000997361 0.00092975 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000928588 0.000891047 +k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 2.68 vpr 66.09 MiB -1 -1 0.23 18680 3 0.06 -1 -1 33044 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67676 99 130 344 474 1 224 302 19 19 361 o auto 26.0 MiB 0.04 2630 951 69118 18569 36933 13616 66.1 MiB 0.12 0.00 2.44032 1.89487 -136.14 -1.89487 1.89487 0.68 0.000571066 0.000535628 0.0419031 0.0391258 -1 -1 -1 -1 36 1362 12 1.79173e+07 4.42837e+06 833707. 2309.44 0.54 0.158153 0.144928 24998 161561 -1 1242 10 542 821 37855 9195 1.91637 1.91637 -141.984 -1.91637 -0.260117 -0.143334 1.02328e+06 2834.56 0.03 0.03 0.09 -1 -1 0.03 0.0197224 0.0183669 +k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 5.48 vpr 76.38 MiB -1 -1 0.31 23816 15 0.29 -1 -1 34012 -1 -1 61 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78212 162 96 1009 950 1 667 324 24 24 576 i auto 30.0 MiB 0.16 14162 6905 91508 24620 57078 9810 76.4 MiB 0.36 0.01 26.8808 21.7286 -1710.39 -21.7286 21.7286 1.13 0.00162259 0.00150985 0.144903 0.134733 -1 -1 -1 -1 32 12694 37 3.08128e+07 5.26753e+06 1.24505e+06 2161.54 1.45 0.414682 0.384459 39974 242477 -1 10860 26 4768 10723 1400040 362149 22.9048 22.9048 -1885.36 -22.9048 0 0 1.54255e+06 2678.04 0.05 0.27 0.13 -1 -1 0.05 0.0982135 0.0920022 +k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.54 vpr 63.39 MiB -1 -1 0.07 17288 1 0.02 -1 -1 29952 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64908 1 1 1 2 0 1 2 4 4 16 i auto 25.1 MiB 0.00 3 3 3 0 0 3 63.4 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 7.064e-06 3.953e-06 5.5843e-05 3.7452e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.000937595 0.000878513 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.000868787 0.000834386 +k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.53 vpr 63.02 MiB -1 -1 0.07 17672 1 0.02 -1 -1 29920 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64528 2 1 3 4 1 3 4 4 4 16 i auto 24.8 MiB 0.00 7 7 9 0 1 8 63.0 MiB 0.00 0.00 0.55247 0.55247 -0.955943 -0.55247 0.55247 0.00 9.672e-06 6.229e-06 7.3202e-05 5.3956e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.00 0.000992269 0.000917558 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00094227 0.000904416 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 278399cb6d8..c7a42e2d8a5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.77 vpr 65.95 MiB -1 -1 0.64 26892 5 0.17 -1 -1 36964 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67536 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 568 210 329 29 66.0 MiB 0.00 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 12 168 36 646728 646728 19965.4 554.594 0.12 0.0658358 0.0559906 1696 3924 -1 165 24 236 544 12437 3707 2.26842 2.26842 -94.6601 -2.26842 0 0 25971.8 721.439 0.00 0.03 0.00 -1 -1 0.00 0.0200385 0.0180231 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.30 vpr 64.27 MiB -1 -1 0.42 23048 5 0.11 -1 -1 32508 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65812 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 165 874 360 491 23 64.3 MiB 0.00 0.00 -1 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 12 194 14 646728 646728 19965.4 554.594 0.05 0.0268855 0.0229859 1696 3924 -1 170 14 189 408 8500 2615 2.16176 2.16176 -92.1884 -2.16176 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.00914723 0.00823102 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt index b44eab4cd1c..457ca6aae28 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 14.98 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.82 4.4449e-05 3.636e-05 0.000492339 0.000302558 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.14 0.00246861 0.00204917 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00171876 0.00162871 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 17.28 vpr 59.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60472 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.88 4.5558e-05 3.7864e-05 0.000392587 0.000316954 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00226581 0.00204304 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00121674 0.00115171 - sub_tiles.xml sub_tiles.blif common_--check_route_off 16.44 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.05 6.9962e-05 5.8494e-05 0.000570046 0.000472887 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.09 0.00239105 0.00217713 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00134624 0.00127449 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common_--check_route_full 4.62 vpr 57.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58524 6 7 19 26 0 19 26 3 3 9 -1 auto 18.7 MiB 0.00 51 51 216 43 63 110 57.2 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.90 2.1456e-05 1.7214e-05 0.000207128 0.000166346 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00133396 0.00120338 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.0010614 0.00100173 +sub_tiles.xml sub_tiles.blif common_--check_route_quick 4.53 vpr 57.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58908 6 7 19 26 0 19 26 3 3 9 -1 auto 19.1 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.82 2.2115e-05 1.7856e-05 0.000217527 0.000170315 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00124615 0.00111395 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00107232 0.00101111 +sub_tiles.xml sub_tiles.blif common_--check_route_off 4.56 vpr 57.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58520 6 7 19 26 0 19 26 3 3 9 -1 auto 18.7 MiB 0.00 51 51 216 43 63 110 57.1 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.84 2.2198e-05 1.7921e-05 0.000224128 0.000167458 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.0014896 0.00134369 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00102348 0.00096044 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index 124aaee2a04..5f3bbb09c0f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.66 vpr 66.09 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33388 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67676 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.65 100 74 24 47 3 66.1 MiB 0.00 0.00 2.48207 -28.4593 -2.48207 2.48207 0.02 0.000164662 0.000145718 0.00164144 0.00155216 -1 -1 -1 -1 38 129 6 151211 75605.7 48493.3 1939.73 0.18 0.0548944 0.0466047 2100 8065 -1 122 13 105 125 3874 2046 2.74837 2.74837 -33.9524 -2.74837 0 0 61632.8 2465.31 0.00 0.01 0.01 -1 -1 0.00 0.00954243 0.00888996 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.19 MiB -1 -1 0.14 21572 1 0.04 -1 -1 34020 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68800 19 18 308 249 1 134 43 5 5 25 clb auto 27.7 MiB 5.80 445 2068 454 1604 10 67.2 MiB 0.04 0.00 4.5386 -91.3528 -4.5386 4.5386 0.02 0.000449316 0.000397091 0.0186893 0.0169167 -1 -1 -1 -1 50 721 33 151211 151211 61632.8 2465.31 0.30 0.144091 0.126311 2268 9834 -1 620 20 733 1185 38218 18241 5.03997 5.03997 -109.631 -5.03997 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0288144 0.0262691 53 83 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.12 vpr 64.71 MiB -1 -1 0.07 17596 1 0.02 -1 -1 30072 -1 -1 3 9 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 9 8 75 70 1 34 20 5 5 25 clb auto 25.5 MiB 0.37 114 98 74 21 50 3 64.7 MiB 0.00 0.00 2.48207 2.48207 -27.0891 -2.48207 2.48207 0.01 0.000107575 9.8776e-05 0.00110372 0.00106107 -1 -1 -1 -1 38 138 12 151211 75605.7 48493.3 1939.73 0.06 0.0197476 0.0166644 2100 8065 -1 119 12 82 91 2625 1383 2.45975 2.45975 -29.6014 -2.45975 0 0 61632.8 2465.31 0.00 0.01 0.00 -1 -1 0.00 0.00468675 0.00431297 13 18 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.60 vpr 65.51 MiB -1 -1 0.09 18364 1 0.03 -1 -1 30608 -1 -1 9 19 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67084 19 18 308 249 1 135 46 6 6 36 clb auto 26.2 MiB 3.56 587 468 1358 299 1048 11 65.5 MiB 0.02 0.00 4.87574 4.8546 -99.0856 -4.8546 4.8546 0.02 0.000300463 0.000275416 0.00787823 0.00739934 -1 -1 -1 -1 40 1040 31 403230 226817 88484.8 2457.91 0.20 0.07778 0.0678958 3734 16003 -1 750 18 631 1001 35065 15346 5.69994 5.69994 -115.447 -5.69994 0 0 110337. 3064.92 0.00 0.02 0.01 -1 -1 0.00 0.0168321 0.0154848 54 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index e2bde77991f..316cb57d442 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.40 vpr 59.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61208 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9684e-05 6.8866e-05 0.000576703 0.000522527 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00940561 0.00796331 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00917782 0.00398665 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.34 vpr 59.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61228 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4384e-05 5.704e-05 0.000402489 0.000366894 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0100179 0.00835542 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00286153 0.00265955 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 59.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61188 1 4 28 32 2 10 9 4 4 16 clb auto 21.1 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4879e-05 5.7282e-05 0.000404422 0.000368079 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00971796 0.00808787 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00303232 0.00280678 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.31 vpr 58.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59868 1 4 28 32 2 10 9 4 4 16 clb auto 19.8 MiB 0.01 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 6.53e-05 5.4819e-05 0.000394918 0.000361284 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0059078 0.00495365 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0017688 0.00164015 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.31 vpr 57.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59208 1 4 28 32 2 10 9 4 4 16 clb auto 19.2 MiB 0.00 22 21 27 10 10 7 57.8 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.7045e-05 4.1525e-05 0.000356415 0.000327846 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00503283 0.0042397 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00176555 0.00162958 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 57.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59112 1 4 28 32 2 10 9 4 4 16 clb auto 19.1 MiB 0.00 22 21 27 10 10 7 57.7 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.1269e-05 3.581e-05 0.000380089 0.000351263 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00490459 0.00412987 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00176255 0.0016337 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt index 9d76eedbd00..b227476183e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.31 vpr 59.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61216 2 2 22 24 2 4 6 4 4 16 clb auto 21.3 MiB 0.00 8 15 5 7 3 59.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 5.264e-05 4.5649e-05 0.000308634 0.000273818 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.002301 0.00212354 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00265986 0.00219441 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.29 vpr 58.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59572 2 2 22 24 2 4 6 4 4 16 clb auto 19.5 MiB 0.00 8 8 15 5 7 3 58.2 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.01 3.3312e-05 2.8021e-05 0.000249857 0.000222009 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.00 0.00183223 0.00169467 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00137997 0.0012867 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt index 55f3e1dd3ba..b7e6584d848 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index 948d09b747d..e1f6058b268 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.66 MiB -1 -1 0.07 21096 1 0.02 -1 -1 33168 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 6 3 0 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.5934e-05 1.0639e-05 9.4808e-05 6.8481e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00119359 0.00110751 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.27 vpr 59.66 MiB -1 -1 0.08 20840 1 0.02 -1 -1 33340 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 9 9 5 2 2 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.6744e-05 1.0373e-05 9.4261e-05 6.634e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00132946 0.0012632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 31.57 parmys 210.75 MiB -1 -1 25.18 215804 2 1.59 -1 -1 60048 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63168 5 156 191 347 1 163 316 15 15 225 clb auto 22.1 MiB 0.04 31 86316 62145 3320 20851 61.7 MiB 0.22 0.02 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000537912 0.000491594 0.0397632 0.036381 -1 -1 -1 -1 -1 50 5 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0494991 0.045404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 25.71 parmys 210.82 MiB -1 -1 22.20 215880 2 0.99 -1 -1 60300 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62916 5 156 191 347 1 163 316 15 15 225 clb auto 21.9 MiB 0.02 33 86316 61936 3548 20832 61.4 MiB 0.10 0.00 1.51877 -14.6769 -1.51877 1.51877 0.00 0.000236107 0.000213852 0.0263786 0.0239723 -1 -1 -1 -1 -1 59 7 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0328145 0.0299576 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 20748 1 0.02 -1 -1 33304 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 6 2 1 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.6453e-05 1.1342e-05 0.000108728 7.9328e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.0015946 0.00150943 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 21132 1 0.02 -1 -1 33192 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 9 9 5 2 2 65.2 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.8934e-05 1.2137e-05 0.000113982 8.1444e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.00161693 0.00153615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 5.07 vpr 72.77 MiB -1 -1 1.12 29456 2 0.10 -1 -1 37868 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74516 311 156 972 1128 1 953 525 28 28 784 memory auto 32.5 MiB 0.54 8655 197406 67882 119014 10510 72.8 MiB 1.23 0.02 3.83315 -4315.62 -3.83315 3.83315 0.00 0.0052551 0.00459042 0.542684 0.463052 -1 -1 -1 -1 -1 12421 13 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.41 0.761716 0.663478 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 5.34 vpr 72.84 MiB -1 -1 1.44 29580 2 0.14 -1 -1 38000 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74592 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.55 8675 193172 64013 116396 12763 72.8 MiB 0.82 0.01 3.94715 -3504.6 -3.94715 3.94715 0.00 0.00308193 0.00262987 0.364549 0.310746 -1 -1 -1 -1 -1 12709 18 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.33 0.5457 0.474589 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.33 vpr 58.26 MiB -1 -1 0.06 17124 1 0.02 -1 -1 29960 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59656 2 1 3 4 1 3 4 3 3 9 -1 auto 19.5 MiB 0.00 6 6 9 6 3 0 58.3 MiB 0.00 0.00 0.631526 0.55447 -0.91031 -0.55447 0.55447 0.00 9.096e-06 5.714e-06 7.2854e-05 5.3361e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00119026 0.00111378 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.35 vpr 57.88 MiB -1 -1 0.06 17120 1 0.02 -1 -1 29900 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59272 2 1 3 4 1 3 4 3 3 9 -1 auto 19.5 MiB 0.00 9 9 9 5 2 2 57.9 MiB 0.00 0.00 0.50194 0.48631 -0.91031 -0.48631 0.48631 0.00 1.0552e-05 6.177e-06 7.7442e-05 5.6208e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00124162 0.00117322 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 18.39 parmys 207.19 MiB -1 -1 15.30 212160 2 0.89 -1 -1 56412 -1 -1 155 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61752 5 156 191 347 1 163 316 15 15 225 clb auto 20.3 MiB 0.02 93 31 86316 62044 3278 20994 60.3 MiB 0.08 0.00 1.75726 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000224295 0.000210617 0.0190742 0.0179017 -1 -1 -1 -1 -1 46 7 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0245095 0.0229368 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 18.49 parmys 207.43 MiB -1 -1 15.24 212412 2 0.90 -1 -1 56416 -1 -1 155 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61372 5 156 191 347 1 163 316 15 15 225 clb auto 20.6 MiB 0.02 102 33 86316 61971 3553 20792 59.9 MiB 0.07 0.00 1.51873 1.47673 -14.6018 -1.47673 1.47673 0.00 0.000227964 0.000214063 0.0189836 0.0177643 -1 -1 -1 -1 -1 49 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0236295 0.02208 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.38 vpr 63.18 MiB -1 -1 0.06 17272 1 0.02 -1 -1 29964 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64696 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 6 2 1 63.2 MiB 0.00 0.00 0.629525 0.55247 -0.90831 -0.55247 0.55247 0.00 9.944e-06 6.35e-06 7.7389e-05 5.7155e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.00103762 0.000966446 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.36 vpr 63.41 MiB -1 -1 0.06 17128 1 0.02 -1 -1 29980 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64932 2 1 3 4 1 3 4 3 3 9 -1 auto 24.8 MiB 0.00 9 9 9 5 2 2 63.4 MiB 0.00 0.00 0.49994 0.48631 -0.90831 -0.48631 0.48631 0.00 1.0823e-05 6.339e-06 7.8471e-05 5.6828e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.000951333 0.000890977 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 2.92 vpr 70.77 MiB -1 -1 0.75 26116 2 0.09 -1 -1 33620 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72472 311 156 972 1128 1 953 525 28 28 784 memory auto 31.7 MiB 0.27 18876 8963 212225 78866 122905 10454 70.8 MiB 0.61 0.01 4.92557 4.25856 -4308.38 -4.25856 4.25856 0.00 0.00268505 0.00240057 0.286887 0.256005 -1 -1 -1 -1 -1 12922 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.19 0.383503 0.345483 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 2.96 vpr 71.48 MiB -1 -1 0.73 26120 2 0.09 -1 -1 33580 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73192 311 156 972 1128 1 953 525 28 28 784 memory auto 32.0 MiB 0.27 19048 9147 216459 76243 126716 13500 71.5 MiB 0.65 0.01 5.19493 4.54954 -3411.74 -4.54954 4.54954 0.00 0.00270574 0.0024254 0.30082 0.26586 -1 -1 -1 -1 -1 13132 15 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.22 0.424559 0.380762 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt index 9cebacaf785..5bc7bdd18eb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.85 vpr 66.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 8 4 25 28 5 19 19 6 6 36 clb auto 27.5 MiB 0.60 51 194 39 119 36 66.0 MiB 0.01 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 8.3509e-05 6.4713e-05 0.00086545 0.000699438 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.0 MiB 0.00 0.00307466 0.00275514 66.0 MiB -1 0.00 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21296 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.34 vpr 63.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65512 8 4 25 28 5 19 19 6 6 36 clb auto 25.3 MiB 0.17 73 51 194 39 119 36 64.0 MiB 0.00 0.00 1.51369 1.41795 -5.85435 -1.41795 0.545 0.00 3.4898e-05 2.684e-05 0.000448159 0.000363972 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 673 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.00 -1 -1 64.0 MiB 0.00 0.00175021 0.00156962 64.0 MiB -1 0.00 +k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.04 vpr 18.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 18952 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index c751724ac21..feaca68d693 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.30 vpr 65.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66556 -1 2 2 4 0 2 4 4 4 16 clb auto 26.8 MiB 0.00 0 9 0 2 7 65.0 MiB 0.00 0.00 nan 0 0 nan 0.01 9.099e-06 4.802e-06 6.6245e-05 4.4664e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00112148 0.00105568 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00152182 0.00148612 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.32 vpr 63.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65152 -1 2 2 4 0 2 4 4 4 16 clb auto 25.0 MiB 0.00 0 0 9 0 2 7 63.6 MiB 0.00 0.00 nan nan 0 0 nan 0.00 8.028e-06 4.217e-06 6.2739e-05 4.2279e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.000902134 0.000846924 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.000893006 0.000861174 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index 19c7fb784a9..4228b940981 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 36.32 vpr 86.72 MiB -1 -1 4.05 45484 3 0.90 -1 -1 40972 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88800 236 305 3199 3011 1 1520 677 25 25 625 -1 25x25 45.9 MiB 3.77 14108 309661 104995 184095 20571 86.7 MiB 2.82 0.04 4.79923 -2884.9 -4.79923 4.79923 1.31 0.00890658 0.00798503 1.05545 0.927146 -1 -1 -1 -1 58 25094 44 3.19446e+07 9.87633e+06 2.35761e+06 3772.18 18.23 4.76599 4.25993 69363 480205 -1 22477 18 6375 16887 1571491 383129 5.01505 5.01505 -3124.26 -5.01505 0 0 3.00727e+06 4811.63 0.12 0.58 0.43 -1 -1 0.12 0.287158 0.267873 - column_io.xml raygentop.v common 21.72 vpr 86.87 MiB -1 -1 3.94 45412 3 0.59 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88956 236 305 3199 3011 1 1520 677 25 25 625 io auto 46.1 MiB 2.22 12585 268067 93998 147700 26369 86.9 MiB 1.58 0.02 4.73901 -2866.75 -4.73901 4.73901 0.71 0.00580557 0.00496502 0.564483 0.497852 -1 -1 -1 -1 54 26673 50 2.82259e+07 9.87633e+06 2.01770e+06 3228.33 9.11 2.60416 2.32669 60384 399159 -1 22031 17 6221 15823 1566992 390050 4.92063 4.92063 -3214.76 -4.92063 0 0 2.61977e+06 4191.64 0.11 0.57 0.36 -1 -1 0.11 0.283045 0.264698 - multiwidth_blocks.xml raygentop.v common 24.35 vpr 86.45 MiB -1 -1 4.29 45400 3 0.88 -1 -1 40680 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88524 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.5 MiB 3.44 13659 253212 84696 147080 21436 86.4 MiB 2.39 0.03 4.97053 -2888.67 -4.97053 4.97053 0.57 0.0095941 0.00864195 0.904905 0.798443 -1 -1 -1 -1 70 23087 25 1.65001e+07 9.87633e+06 1.31889e+06 3653.42 9.29 3.5266 3.16984 37321 246261 -1 21189 14 5796 14717 1380152 383870 5.13329 5.13329 -3164.24 -5.13329 0 0 1.66774e+06 4619.77 0.06 0.50 0.26 -1 -1 0.06 0.248992 0.232939 - non_column.xml raygentop.v common 55.37 vpr 101.45 MiB -1 -1 4.51 45384 3 0.78 -1 -1 40740 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103880 236 305 3188 3000 1 1523 673 33 33 1089 io auto 46.9 MiB 3.81 15255 254201 81770 140693 31738 97.7 MiB 2.36 0.03 4.86131 -2900.08 -4.86131 4.86131 2.27 0.00977579 0.00884174 0.917497 0.805822 -1 -1 -1 -1 48 30162 49 5.44432e+07 9.66075e+06 2.98548e+06 2741.49 34.00 4.50443 4.0188 95950 575791 -1 25045 20 6804 18118 1664218 433730 5.45028 5.45028 -3158.16 -5.45028 0 0 3.81303e+06 3501.40 0.21 0.95 0.95 -1 -1 0.21 0.482241 0.44347 - non_column_tall_aspect_ratio.xml raygentop.v common 44.05 vpr 108.02 MiB -1 -1 4.73 45644 3 0.86 -1 -1 40856 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110616 236 305 3188 3000 1 1523 673 23 46 1058 io auto 47.3 MiB 3.74 14790 242409 83942 122709 35758 98.8 MiB 2.21 0.03 4.6713 -2947.44 -4.6713 4.6713 2.10 0.00881355 0.00803567 0.866396 0.762137 -1 -1 -1 -1 54 27998 49 5.05849e+07 9.66075e+06 3.28516e+06 3105.07 22.44 5.06657 4.53255 98319 656086 -1 23970 19 6505 16966 1638977 432992 5.05886 5.05886 -3281.32 -5.05886 0 0 4.26512e+06 4031.31 0.30 0.98 1.19 -1 -1 0.30 0.480325 0.442198 - non_column_wide_aspect_ratio.xml raygentop.v common 55.14 vpr 115.98 MiB -1 -1 4.85 45536 3 0.89 -1 -1 40604 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 118764 236 305 3188 3000 1 1523 673 53 27 1431 io auto 47.2 MiB 4.13 15438 292525 96949 170972 24604 116.0 MiB 2.79 0.04 4.87363 -3002.95 -4.87363 4.87363 2.83 0.00999099 0.00902684 1.12807 0.98489 -1 -1 -1 -1 46 32183 50 7.18852e+07 9.66075e+06 3.81039e+06 2662.74 30.50 4.16688 3.69158 125381 744275 -1 26057 24 7716 19635 2034521 534369 5.1816 5.1816 -3336.75 -5.1816 0 0 4.88937e+06 3416.75 0.38 1.34 1.15 -1 -1 0.38 0.614347 0.564321 - custom_sbloc.xml raygentop.v common 26.06 vpr 86.32 MiB -1 -1 4.50 45448 3 1.04 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88392 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 4.20 13741 271038 86813 158916 25309 86.3 MiB 2.67 0.04 4.66207 -2945.67 -4.66207 4.66207 0.62 0.0101306 0.00867476 0.964821 0.865378 -1 -1 -1 -1 68 24218 46 1.65001e+07 9.87633e+06 1.26689e+06 3509.39 7.14 3.30943 2.96886 36601 241349 -1 21082 17 5846 15055 1419293 377571 4.86127 4.86127 -3204.17 -4.86127 0 0 1.57833e+06 4372.12 0.09 0.93 0.49 -1 -1 0.09 0.46499 0.431595 - multiple_io_types.xml raygentop.v common 162.68 vpr 512.77 MiB -1 -1 4.59 44868 3 0.91 -1 -1 40632 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 525072 236 305 3199 3011 1 1520 677 70 70 4900 io_left auto 46.0 MiB 4.88 29540 98720 5114 25125 68481 512.8 MiB 0.75 0.03 4.77694 -3775.91 -4.77694 4.77694 29.11 0.00955143 0.00822118 0.265489 0.23233 -1 -1 -1 -1 46 47171 45 2.76175e+08 9.87633e+06 1.25363e+07 2558.43 103.39 4.74809 4.24216 425698 2387761 -1 40627 18 8645 22202 3622069 899914 5.14884 5.14884 -4109.51 -5.14884 0 0 1.61910e+07 3304.29 1.21 1.53 3.08 -1 -1 1.21 0.445697 0.411568 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_grid.xml raygentop.v common 17.52 vpr 84.87 MiB -1 -1 2.11 42840 3 0.53 -1 -1 37004 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86904 236 305 3199 3011 1 1523 675 25 25 625 -1 25x25 45.9 MiB 1.88 30826 14481 296575 101967 175892 18716 84.9 MiB 1.19 0.02 7.09553 4.79307 -2895.89 -4.79307 4.79307 0.49 0.00404936 0.00373604 0.453796 0.412288 -1 -1 -1 -1 56 27441 32 3.19446e+07 9.76854e+06 2.27235e+06 3635.76 8.42 1.54762 1.41602 68115 457904 -1 23429 18 6422 16721 1633043 414220 4.92066 4.92066 -3228.39 -4.92066 0 0 2.89946e+06 4639.14 0.09 0.43 0.26 -1 -1 0.09 0.228671 0.215662 +column_io.xml raygentop.v common 13.20 vpr 84.73 MiB -1 -1 2.11 42840 3 0.53 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86760 236 305 3199 3011 1 1523 675 25 25 625 io auto 45.5 MiB 1.86 28947 12805 264026 93507 163068 7451 84.7 MiB 1.07 0.02 6.19083 4.92182 -2798.47 -4.92182 4.92182 0.45 0.00386921 0.003551 0.384409 0.349362 -1 -1 -1 -1 54 25735 23 2.82259e+07 9.76854e+06 2.01770e+06 3228.33 4.39 1.3452 1.22801 60384 399159 -1 22144 15 5803 15289 1517391 375232 5.17726 5.17726 -3105.16 -5.17726 0 0 2.61977e+06 4191.64 0.08 0.39 0.23 -1 -1 0.08 0.208718 0.197683 +multiwidth_blocks.xml raygentop.v common 11.01 vpr 85.16 MiB -1 -1 2.10 42644 3 0.51 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87204 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.9 MiB 1.83 27296 13664 243313 79797 144041 19475 85.2 MiB 0.96 0.01 7.04872 4.69621 -2916.6 -4.69621 4.69621 0.21 0.00375866 0.00345546 0.355094 0.322715 -1 -1 -1 -1 70 24143 30 1.65001e+07 9.76854e+06 1.31889e+06 3653.42 3.07 1.33175 1.21367 37321 246261 -1 21464 15 6203 15799 1529026 424169 4.71101 4.71101 -3112.78 -4.71101 0 0 1.66774e+06 4619.77 0.04 0.35 0.16 -1 -1 0.04 0.187972 0.177589 +non_column.xml raygentop.v common 14.99 vpr 98.91 MiB -1 -1 2.24 41936 3 0.48 -1 -1 38412 -1 -1 126 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 101288 236 305 3188 3000 1 1520 674 33 33 1089 io auto 46.7 MiB 1.99 36533 15061 269488 91860 157197 20431 97.4 MiB 1.00 0.01 7.4161 4.90918 -2943.89 -4.90918 4.90918 0.82 0.00384724 0.00350765 0.37964 0.345058 -1 -1 -1 -1 54 27586 33 5.44432e+07 9.71464e+06 3.30487e+06 3034.77 4.75 1.37884 1.25939 100302 649205 -1 23881 20 6491 17318 1529311 414224 6.12281 6.12281 -3223.84 -6.12281 0 0 4.28921e+06 3938.67 0.13 0.43 0.50 -1 -1 0.13 0.232808 0.218578 +non_column_tall_aspect_ratio.xml raygentop.v common 16.02 vpr 97.64 MiB -1 -1 2.30 42268 3 0.49 -1 -1 38420 -1 -1 126 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 99984 236 305 3188 3000 1 1520 674 23 46 1058 io auto 48.2 MiB 1.93 38199 14733 245856 82760 136190 26906 95.4 MiB 0.94 0.01 8.90911 4.95032 -2931.23 -4.95032 4.95032 0.79 0.003732 0.00342402 0.351006 0.319132 -1 -1 -1 -1 52 28730 41 5.05849e+07 9.71464e+06 3.17293e+06 2998.99 5.91 1.39167 1.27101 97261 632982 -1 24184 19 6976 18077 1589447 411584 5.61027 5.61027 -3209.89 -5.61027 0 0 4.15960e+06 3931.57 0.13 0.42 0.46 -1 -1 0.13 0.222476 0.208816 +non_column_wide_aspect_ratio.xml raygentop.v common 16.23 vpr 114.89 MiB -1 -1 2.23 42456 3 0.51 -1 -1 38084 -1 -1 126 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 117652 236 305 3188 3000 1 1520 674 53 27 1431 io auto 47.4 MiB 2.01 41800 15715 293120 96558 176401 20161 114.9 MiB 1.13 0.02 8.75852 4.83208 -2966.14 -4.83208 4.83208 1.11 0.00394946 0.00359569 0.43193 0.391243 -1 -1 -1 -1 50 29305 30 7.18852e+07 9.71464e+06 4.09444e+06 2861.24 5.10 1.45359 1.3252 128243 787897 -1 25411 18 6656 17052 1503266 383226 5.17928 5.17928 -3293.35 -5.17928 0 0 5.23266e+06 3656.65 0.17 0.41 0.52 -1 -1 0.17 0.218658 0.206004 +custom_sbloc.xml raygentop.v common 11.14 vpr 85.09 MiB -1 -1 2.11 42068 3 0.51 -1 -1 36976 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87128 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.9 MiB 1.88 27296 13137 255149 87552 148387 19210 85.1 MiB 1.03 0.02 7.00084 4.99197 -2892.82 -4.99197 4.99197 0.22 0.00391014 0.00357245 0.373695 0.338718 -1 -1 -1 -1 68 22261 27 1.65001e+07 9.76854e+06 1.26689e+06 3509.39 3.06 1.3486 1.22808 36601 241349 -1 20367 15 5668 14466 1281380 334598 4.957 4.957 -3115.31 -4.957 0 0 1.57833e+06 4372.12 0.04 0.34 0.15 -1 -1 0.04 0.197825 0.186835 +multiple_io_types.xml raygentop.v common 38.75 vpr 510.90 MiB -1 -1 2.11 42452 3 0.54 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 523164 236 305 3199 3011 1 1523 675 70 70 4900 io_left auto 45.9 MiB 2.29 68337 27793 95363 4323 24983 66057 510.9 MiB 0.44 0.01 10.4866 5.00659 -3523.06 -5.00659 5.00659 12.29 0.00405701 0.00372146 0.166522 0.152725 -1 -1 -1 -1 52 42943 37 2.76175e+08 9.76854e+06 1.39708e+07 2851.19 12.38 1.27647 1.16971 445294 2682153 -1 37901 18 8291 21706 3271061 840277 5.11058 5.11058 -3856.44 -5.11058 0 0 1.83718e+07 3749.35 0.63 0.68 1.74 -1 -1 0.63 0.221189 0.207674 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index 9ad80c43a91..a52c4e985c2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.93 MiB -1 -1 0.36 22040 3 0.12 -1 -1 36928 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69560 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.23 673 63978 19550 30341 14087 67.9 MiB 0.25 0.01 1.86472 -118.834 -1.86472 1.86472 0.23 0.00124652 0.00114654 0.0791433 0.0725521 -1 -1 -1 -1 38 1384 9 5.66058e+06 4.21279e+06 328943. 2284.32 0.66 0.24355 0.222932 12522 66188 -1 1114 9 395 636 21516 6871 1.90702 1.90702 -133.439 -1.90702 -1.20917 -0.320482 418267. 2904.63 0.04 0.05 0.10 -1 -1 0.04 0.0351893 0.0324309 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 1.65 vpr 66.48 MiB -1 -1 0.22 18444 3 0.06 -1 -1 33100 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68076 99 130 344 474 1 228 298 12 12 144 clb auto 27.1 MiB 0.10 1675 704 66963 20370 32791 13802 66.5 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.10 0.000547023 0.000511318 0.0407422 0.0381484 -1 -1 -1 -1 40 1447 14 5.66058e+06 4.21279e+06 343462. 2385.15 0.33 0.154346 0.141557 12666 68385 -1 1229 9 430 657 29320 9898 2.03042 2.03042 -138.775 -2.03042 -0.436676 -0.298787 431791. 2998.55 0.01 0.02 0.04 -1 -1 0.01 0.0159269 0.0149459 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt index 88d0cc36263..7a201af14f7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 65.74 vpr 1.17 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1222776 13 29 26295 20086 1 12439 800 40 32 1280 -1 EP4SGX110 1063.6 MiB 14.29 72376 238368 44187 187356 6825 1172.1 MiB 12.27 0.21 5.14869 -5574.19 -4.14869 2.7734 0.01 0.0513395 0.0444487 3.37672 2.67885 83490 6.71303 20017 1.60947 25863 35776 9229792 1644713 0 0 2.34683e+07 18334.6 15 375646 4004209 -1 5.37962 2.85331 -5732.11 -4.37962 0 0 7.55 -1 -1 1172.1 MiB 6.09 5.72718 4.67253 1172.1 MiB -1 3.79 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 35.31 vpr 1.17 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1222524 13 29 26295 20086 1 12646 791 40 32 1280 -1 EP4SGX110 1077.3 MiB 7.77 239076 73734 242087 47102 187997 6988 1170.3 MiB 6.30 0.09 5.63444 5.39011 -5538.73 -4.39011 2.81304 0.01 0.0220364 0.0193919 1.79552 1.47773 84889 6.71378 20487 1.62029 25867 34992 8975854 1601365 0 0 2.34683e+07 18334.6 16 375646 4004209 -1 5.63353 2.99154 -5719.81 -4.63353 0 0 3.73 -1 -1 1170.3 MiB 2.72 2.96387 2.51924 1170.3 MiB -1 1.28 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index f8dbe6d76d8..9399e0cc166 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.26 vpr 64.63 MiB -1 -1 0.36 22472 3 0.08 -1 -1 36672 -1 -1 72 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66184 99 130 353 483 1 273 302 15 15 225 memory auto 25.1 MiB 0.03 836 70130 21082 33527 15521 64.6 MiB 0.28 0.00 1.52582 -78.5706 -1.52582 1.52582 0.00 0.00103975 0.000940046 0.0805857 0.0730912 -1 -1 -1 -1 1163 5.43458 640 2.99065 663 1535 177334 49638 1.16234e+06 363548 2.18283e+06 9701.45 10 48952 428016 -1 1.65868 1.65868 -90.7494 -1.65868 -2.16982 -0.309514 0.64 -1 -1 64.6 MiB 0.08 0.105372 0.095866 64.6 MiB -1 0.38 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 1.29 vpr 62.83 MiB -1 -1 0.27 18364 3 0.06 -1 -1 33116 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64340 99 130 353 483 1 273 302 15 15 225 memory auto 23.4 MiB 0.02 2130 858 65070 19636 30261 15173 62.8 MiB 0.12 0.00 1.71828 1.52582 -77.3355 -1.52582 1.52582 0.00 0.00058607 0.000549367 0.0386887 0.0361876 -1 -1 -1 -1 1238 5.78505 678 3.16822 700 1565 188506 51086 1.16234e+06 363548 2.18283e+06 9701.45 11 48952 428016 -1 1.60126 1.60126 -87.5381 -1.60126 -2.22487 -0.375057 0.27 -1 -1 62.8 MiB 0.04 0.0551511 0.0514246 62.8 MiB -1 0.14 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index 01809a06f11..9b0f40005b1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 22.14 vpr 81.82 MiB -1 -1 1.50 29500 2 0.12 -1 -1 37736 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83780 311 156 1015 1158 1 965 514 28 28 784 memory auto 35.0 MiB 0.98 9365 202198 74776 117229 10193 76.8 MiB 1.40 0.02 4.8046 -3913.87 -4.8046 4.8046 1.69 0.00610306 0.00535177 0.650008 0.562031 -1 -1 -1 -1 46 14326 15 4.25198e+07 9.94461e+06 2.42825e+06 3097.26 10.53 2.95135 2.62498 81963 495902 -1 13813 11 2359 2703 832718 314081 4.94363 4.94363 -4384.42 -4.94363 -367.864 -1.26276 3.12000e+06 3979.60 0.25 1.49 0.70 -1 -1 0.25 0.183604 0.168791 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 21.14 vpr 85.34 MiB -1 -1 1.46 29488 2 0.17 -1 -1 37984 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 87384 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.6 MiB 1.02 9365 202198 74776 117229 10193 77.2 MiB 1.49 0.03 4.8046 -3913.87 -4.8046 4.8046 1.72 0.00745529 0.00636204 0.709181 0.610899 -1 -1 -1 -1 46 14531 14 4.25198e+07 9.94461e+06 2.47848e+06 3161.33 10.27 3.22179 2.86209 81963 509322 -1 13895 10 2295 2641 564364 164225 5.2138 5.2138 -4583.26 -5.2138 -149.396 -1.20609 3.17357e+06 4047.92 0.16 0.89 0.46 -1 -1 0.16 0.127663 0.117099 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 25.61 vpr 78.92 MiB -1 -1 1.51 29244 2 0.15 -1 -1 37516 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80812 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.8 MiB 0.83 9442 200140 70475 118412 11253 78.1 MiB 1.44 0.02 4.10149 -3784.12 -4.10149 4.10149 1.51 0.00620655 0.00547017 0.672177 0.575194 -1 -1 -1 -1 40 16586 15 4.25198e+07 9.94461e+06 2.15085e+06 2743.43 14.64 1.95101 1.72006 78831 435812 -1 15579 11 2621 3012 1218850 719774 5.45816 5.45816 -4586.28 -5.45816 -1608.52 -3.17721 2.68809e+06 3428.68 0.23 1.76 0.54 -1 -1 0.23 0.216383 0.199419 15 950 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 7.83 vpr 76.29 MiB -1 -1 0.77 25744 2 0.08 -1 -1 34464 -1 -1 32 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78124 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.3 MiB 0.45 19865 9549 204256 72417 120221 11618 75.2 MiB 0.58 0.01 5.60967 3.86883 -3854.15 -3.86883 3.86883 0.62 0.00251817 0.00223801 0.26652 0.235626 -1 -1 -1 -1 38 15620 13 4.25198e+07 9.94461e+06 2.06185e+06 2629.91 2.65 0.824788 0.739806 78047 421269 -1 14413 13 2666 3203 1457933 704363 4.53757 4.53757 -4350.73 -4.53757 -517.68 -1.45296 2.60823e+06 3326.82 0.08 0.69 0.22 -1 -1 0.08 0.100156 0.0932531 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 7.65 vpr 76.19 MiB -1 -1 0.74 25740 2 0.09 -1 -1 34340 -1 -1 32 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78020 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.3 MiB 0.49 19865 9549 204256 72417 120221 11618 75.1 MiB 0.60 0.01 5.60967 3.86883 -3854.15 -3.86883 3.86883 0.65 0.00269112 0.00240935 0.28253 0.250663 -1 -1 -1 -1 36 16026 28 4.25198e+07 9.94461e+06 2.00618e+06 2558.90 2.54 0.974248 0.877683 76483 403003 -1 14763 13 2964 3560 850058 256440 4.32275 4.32275 -4167.47 -4.32275 -202.025 -1.15486 2.47848e+06 3161.33 0.09 0.52 0.21 -1 -1 0.09 0.103198 0.09627 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 9.40 vpr 77.06 MiB -1 -1 0.72 25744 2 0.08 -1 -1 34472 -1 -1 32 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78912 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.3 MiB 0.45 19865 9322 210430 75479 122755 12196 77.1 MiB 0.61 0.01 5.60967 3.96043 -3633.05 -3.96043 3.96043 0.61 0.00270142 0.00233618 0.287893 0.256515 -1 -1 -1 -1 36 16853 27 4.25198e+07 9.94461e+06 1.96702e+06 2508.96 4.16 0.934384 0.84348 76483 392433 -1 15496 13 2658 3060 1573658 1035121 5.75178 5.75178 -4622.22 -5.75178 -1616.18 -3.24966 2.42368e+06 3091.42 0.11 0.81 0.20 -1 -1 0.11 0.100558 0.0936526 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index 6c7432d3e12..0dbc3e0ca1d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.52 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.33 10472 141533 36950 100839 3744 71.5 MiB 1.36 0.02 7.46482 -1369.01 -7.46482 7.46482 0.53 0.00499636 0.00433729 0.369387 0.30729 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 10.94 2.01193 1.71604 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.85 0.23 -1 -1 0.04 0.262211 0.23364 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 5.00 vpr 70.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71820 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.0 MiB 0.17 24088 10407 135291 36283 95683 3325 70.1 MiB 0.56 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.21 0.00207977 0.00177833 0.142029 0.122896 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.49 0.448442 0.390716 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.31 0.08 -1 -1 0.02 0.092161 0.0837678 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index 15d40a35dda..9ddaee22f6b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 34.16 vpr 84.50 MiB -1 -1 7.12 54432 5 2.11 -1 -1 42788 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86528 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 1.85 10543 233626 82676 126206 24744 84.5 MiB 2.72 0.04 4.85425 -2733.64 -4.85425 4.85425 0.66 0.00818288 0.00722228 1.06716 0.90034 -1 -1 -1 -1 76 20844 33 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 15.57 4.03457 3.54046 52074 423490 -1 18742 16 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.47 0.38 -1 -1 0.11 0.260053 0.24125 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 14.31 vpr 83.68 MiB -1 -1 3.39 52068 5 1.36 -1 -1 39324 -1 -1 152 193 5 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85688 193 205 2718 2652 1 1315 555 20 20 400 memory auto 44.0 MiB 0.95 22187 10660 223995 81694 118286 24015 83.7 MiB 1.00 0.01 7.82756 5.10197 -2914.56 -5.10197 5.10197 0.30 0.00338005 0.00303666 0.361314 0.32297 -1 -1 -1 -1 76 21455 22 2.07112e+07 1.09319e+07 2.02110e+06 5052.76 4.74 1.15276 1.03306 52074 423490 -1 19292 16 5251 14325 1187541 264668 5.21056 5.21056 -3121.27 -5.21056 -9.98113 -0.359474 2.51807e+06 6295.18 0.07 0.30 0.24 -1 -1 0.07 0.177801 0.166764 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index d0e64cbc176..eafba3af010 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.94 vpr 67.99 MiB -1 -1 0.39 22036 3 0.12 -1 -1 36636 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69620 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.21 0.00 1.86472 -118.834 -1.86472 1.86472 0.24 0.000996678 0.000900839 0.0648293 0.0586504 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.58 0.202532 0.183764 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.06 0.09 -1 -1 0.02 0.0346978 0.0324594 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.66 vpr 66.19 MiB -1 -1 0.21 18444 3 0.06 -1 -1 33260 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67776 99 130 344 474 1 228 298 12 12 144 clb auto 26.7 MiB 0.10 1675 704 66963 20370 32791 13802 66.2 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000579768 0.000542374 0.0417708 0.0391511 -1 -1 -1 -1 40 1453 15 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.160171 0.147086 12666 64609 -1 1222 11 442 668 30453 10334 2.02932 2.02932 -138.236 -2.02932 -0.424985 -0.298787 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0178875 0.0167542 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index 2abafbec4a3..eb67e75c426 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 151.16 vpr 252.22 MiB -1 -1 13.65 124444 5 69.06 -1 -1 68628 -1 -1 1352 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 258272 169 197 21117 21314 1 6442 1718 39 39 1521 clb auto 120.8 MiB 5.85 49865 999363 355164 624898 19301 252.2 MiB 12.58 0.10 3.94387 -15329.6 -3.94387 3.94387 5.65 0.0282487 0.0224608 3.71486 2.98245 -1 -1 -1 -1 38 62474 28 2.4642e+07 2.4336e+07 4.29790e+06 2825.71 27.54 18.235 14.9379 119030 883757 -1 58887 28 30785 67364 2647531 463217 3.72242 3.72242 -16216.3 -3.72242 0 0 5.41627e+06 3561.00 0.27 2.70 0.65 -1 -1 0.27 1.99577 1.72788 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 145.25 vpr 237.36 MiB -1 -1 13.92 124256 5 67.78 -1 -1 68500 -1 -1 1342 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 243060 169 197 21117 21314 1 6530 1708 39 39 1521 clb auto 120.5 MiB 3.79 49914 971183 338147 610049 22987 237.4 MiB 14.52 0.10 3.63479 -14732.8 -3.63479 3.63479 5.35 0.02794 0.0220913 4.48744 3.66675 -1 -1 -1 -1 40 62766 41 7.37824e+07 7.23272e+07 4.31957e+06 2839.95 22.87 16.3688 13.4703 120550 875283 -1 59263 24 31348 67380 2546099 475966 3.57863 3.57863 -15572.9 -3.57863 0 0 5.40678e+06 3554.75 0.57 4.00 1.03 -1 -1 0.57 2.85785 2.46864 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml stereovision0.v common 72.53 vpr 246.70 MiB -1 -1 8.23 120932 5 28.98 -1 -1 65024 -1 -1 1352 169 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 252616 169 197 21117 21314 1 6509 1718 39 39 1521 clb auto 132.6 MiB 3.02 188600 47945 958223 329930 610922 17371 246.7 MiB 6.36 0.07 7.48908 3.85395 -15165.3 -3.85395 3.85395 3.42 0.0181451 0.0155648 1.86364 1.5515 -1 -1 -1 -1 36 61910 50 2.4642e+07 2.4336e+07 4.11737e+06 2707.01 12.81 6.8221 5.66675 115990 821377 -1 57410 21 30914 66833 2643745 477357 3.6821 3.6821 -15912.4 -3.6821 0 0 5.03985e+06 3313.51 0.18 1.66 0.40 -1 -1 0.18 1.17936 1.0401 +k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 70.91 vpr 248.29 MiB -1 -1 7.52 121112 5 28.19 -1 -1 65024 -1 -1 1363 169 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 254252 169 197 21117 21314 1 6565 1729 39 39 1521 clb auto 131.8 MiB 2.87 190099 51107 987164 353007 612737 21420 248.3 MiB 6.23 0.06 9.87654 3.59906 -14959.3 -3.59906 3.59906 3.27 0.0160602 0.0137781 1.82077 1.51774 -1 -1 -1 -1 38 67057 39 7.37824e+07 7.3459e+07 4.16760e+06 2740.04 13.11 6.23411 5.17893 119030 845795 -1 61286 30 33152 70295 2804113 519856 3.34587 3.34587 -15492.9 -3.34587 0 0 5.22668e+06 3436.35 0.18 1.99 0.42 -1 -1 0.18 1.42002 1.25013 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 3a5d60de356..473197a68cf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.5 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.3168e-05 1.5881e-05 0.000156154 0.000121512 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00179937 0.00168173 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00151021 0.00147037 - k6_frac_N10_40nm.xml conn_order.eblif common 0.33 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 2 1 4 5 1 3 4 3 3 9 -1 auto 22.1 MiB 0.00 6 9 4 1 4 60.5 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.6567e-05 1.1555e-05 0.000123665 9.5691e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00181279 0.00171778 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154282 0.00150229 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.28 vpr 58.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59984 3 1 5 6 1 4 5 3 3 9 -1 auto 19.8 MiB 0.00 9 9 12 4 4 4 58.6 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 1.1225e-05 7.794e-06 8.6604e-05 6.6961e-05 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.00 0.00101901 0.000945649 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00092696 0.000891961 +k6_frac_N10_40nm.xml conn_order.eblif common 0.27 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 2 1 4 5 1 3 4 3 3 9 -1 auto 20.2 MiB 0.00 6 6 9 4 1 4 59.0 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0452e-05 7.093e-06 8.2382e-05 6.3346e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.000974719 0.000907358 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00090434 0.000865615 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt index 6afcd280a0b..6639b016754 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.28 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.2578e-05 1.4571e-05 0.000133192 9.8031e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00167256 0.00156119 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00133191 0.00129055 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml eblif_write.eblif common 0.26 vpr 57.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58440 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.7 MiB 0.00 16 14 18 7 10 1 57.1 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3418e-05 8.319e-06 9.1048e-05 6.8306e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.0012188 0.00113608 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000858214 0.00082141 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index 826beb46c2f..8c6f8958beb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.94 vpr 66.02 MiB -1 -1 0.82 27148 5 0.18 -1 -1 36836 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.09 152 432 67 335 30 66.0 MiB 0.04 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000434946 0.000380309 0.00759691 0.00679441 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.0281069 0.0251327 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.16 vpr 64.28 MiB -1 -1 0.41 23672 5 0.11 -1 -1 32960 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 10 2 181 183 1 36 24 6 6 36 clb auto 25.3 MiB 0.04 196 151 534 120 387 27 64.3 MiB 0.04 0.00 2.24505 2.14835 -91.7778 -2.14835 2.14835 0.00 0.000220534 0.00020053 0.00485037 0.00446277 -1 -1 -1 -1 -1 141 16 646728 646728 60312.4 1675.34 0.01 0.0147489 0.0132903 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt index 106e5784d60..765891605f6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.33 vpr 58.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60324 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.4 MiB 0.00 9 9 3 6 0 58.9 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 1.5162e-05 1.0275e-05 0.00029282 0.000262472 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00144752 0.00135246 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00148764 0.00144592 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.27 vpr 57.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58436 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 18.3 MiB 0.00 11 9 9 3 6 0 57.1 MiB 0.00 0.00 3.98683 3.8649 -3.8649 -3.8649 nan 0.00 9.355e-06 5.92e-06 6.6641e-05 4.6524e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00114442 0.00107229 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000890675 0.00085789 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index f0909e951de..d07d79cabc3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.12 vpr 65.83 MiB -1 -1 0.80 26828 5 0.17 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67408 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.03 152 432 67 335 30 65.8 MiB 0.01 0.00 2.15218 -93.3318 -2.15218 2.15218 0.04 0.000541794 0.000472344 0.00646942 0.00583397 -1 -1 -1 -1 8 206 22 646728 646728 33486.6 930.184 0.18 0.0650705 0.0566044 1588 8314 -1 169 20 235 523 16218 5641 2.44258 2.44258 -104.337 -2.44258 0 0 42482.2 1180.06 0.00 0.03 0.01 -1 -1 0.00 0.0191215 0.0169186 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.33 vpr 64.04 MiB -1 -1 0.42 23364 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65580 10 2 181 183 1 36 24 6 6 36 clb auto 24.7 MiB 0.02 196 164 398 79 297 22 64.0 MiB 0.01 0.00 2.2508 2.15218 -91.8425 -2.15218 2.15218 0.01 0.000224237 0.000202847 0.00388388 0.0035963 -1 -1 -1 -1 14 175 18 646728 646728 52871.9 1468.66 0.06 0.031454 0.0271745 1728 14180 -1 158 12 158 364 11157 4123 2.26022 2.26022 -100.753 -2.26022 0 0 63794.4 1772.07 0.00 0.01 0.01 -1 -1 0.00 0.00852136 0.00764565 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place index 70ff5b0f62d..84ede063b47 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place @@ -1,175 +1,181 @@ #block name x y subblk layer block number #---------- -- -- ------ ----- ------------ -o_1_ 4 3 0 0 #0 -o_2_ 1 2 1 0 #1 -o_0_ 3 3 4 0 #2 -n_n1827 3 1 5 0 #3 -n_n1829 3 1 0 0 #4 -n_n1812 1 1 3 0 #5 -n_n1866 3 1 3 0 #6 -n_n1865 4 1 5 0 #7 -[493] 5 4 4 0 #8 -n_n544 4 4 3 0 #9 -n_n416 2 2 2 0 #10 -n_n394 2 1 3 0 #11 -n_n391 2 1 0 0 #12 -n_n300 2 1 1 0 #13 -[260] 3 5 3 0 #14 -n_n437 5 1 3 0 #15 -[223] 3 4 2 0 #16 -[79] 3 5 0 0 #17 -[410] 3 5 4 0 #18 -[516] 4 5 4 0 #19 -[245] 5 5 3 0 #20 -[340] 3 3 5 0 #21 -[432] 3 5 1 0 #22 -[80] 4 4 4 0 #23 -[541] 5 4 2 0 #24 -n_n309 2 1 5 0 #25 -[8] 4 5 1 0 #26 -[546] 4 5 3 0 #27 -n_n706 3 1 2 0 #28 -[261] 3 1 4 0 #29 -[463] 5 2 3 0 #30 -n_n1575 4 5 0 0 #31 -n_n1571 3 4 1 0 #32 -[132] 2 5 4 0 #33 -[355] 3 4 0 0 #34 -[214] 5 3 4 0 #35 -[267] 5 4 0 0 #36 -n_n329 5 1 4 0 #37 -[420] 5 3 1 0 #38 -n_n849 3 1 1 0 #39 -[478] 5 5 0 0 #40 -[578] 1 2 5 0 #41 -[253] 2 3 0 0 #42 -[4] 4 2 0 0 #43 -[56] 1 1 2 0 #44 -[226] 2 2 4 0 #45 -[282] 3 3 2 0 #46 -[377] 1 1 0 0 #47 -[71] 1 1 1 0 #48 -[319] 5 2 0 0 #49 -[233] 2 4 3 0 #50 -[246] 2 4 0 0 #51 -[301] 3 5 5 0 #52 -[441] 2 5 1 0 #53 -[608] 5 4 5 0 #54 -[21] 2 1 2 0 #55 -[311] 4 1 4 0 #56 -[344] 3 2 1 0 #57 -[310] 4 1 3 0 #58 -[315] 4 1 1 0 #59 -[29] 3 2 4 0 #60 -[273] 3 4 5 0 #61 -n_n1690 2 4 4 0 #62 -[383] 4 4 1 0 #63 -[390] 3 2 3 0 #64 -[705] 5 4 3 0 #65 -[41] 5 3 2 0 #66 -[351] 5 2 4 0 #67 -[484] 5 2 5 0 #68 -[437] 5 5 1 0 #69 -[349] 2 3 4 0 #70 -[65] 5 5 4 0 #71 -[221] 4 5 5 0 #72 -[402] 2 4 2 0 #73 -[521] 1 2 0 0 #74 -[767] 4 2 3 0 #75 -[133] 2 5 2 0 #76 -[234] 4 3 4 0 #77 -[868] 3 3 3 0 #78 -[904] 4 3 1 0 #79 -[906] 5 3 3 0 #80 -[919] 4 2 1 0 #81 -[1253] 4 1 0 0 #82 -[1283] 1 2 4 0 #83 -[1340] 3 2 0 0 #84 -[1382] 2 2 5 0 #85 -[1404] 3 2 2 0 #86 -[1417] 1 2 3 0 #87 -[1534] 4 4 2 0 #88 -[1615] 2 5 5 0 #89 -[6947] 3 4 4 0 #90 -[7082] 4 4 0 0 #91 -[7159] 5 2 1 0 #92 -[7165] 5 4 1 0 #93 -[7191] 4 3 2 0 #94 -[7319] 1 3 1 0 #95 -[7321] 3 3 0 0 #96 -[7351] 2 3 5 0 #97 -[7388] 2 2 3 0 #98 -[7423] 2 1 4 0 #99 -[7466] 3 2 5 0 #100 -[7782] 4 3 3 0 #101 -[7822] 3 4 3 0 #102 -[7885] 3 5 2 0 #103 -[7888] 4 2 4 0 #104 -[7997] 5 5 2 0 #105 -[8027] 5 3 0 0 #106 -[50] 2 3 3 0 #107 -[288] 2 3 1 0 #108 -[539] 5 3 5 0 #109 -[372] 4 3 5 0 #110 -n_n1584 2 4 5 0 #111 -[196] 2 3 2 0 #112 -[585] 1 3 2 0 #113 -[365] 4 4 5 0 #114 -[492] 4 2 2 0 #115 -[616] 3 3 1 0 #116 -[430] 2 2 1 0 #117 -[663] 2 2 0 0 #118 -[700] 4 2 5 0 #119 -[322] 1 3 5 0 #120 -[739] 1 3 4 0 #121 -[745] 4 1 2 0 #122 -[771] 2 4 1 0 #123 -[95] 4 5 2 0 #124 -[345] 1 2 2 0 #125 -[759] 1 3 0 0 #126 -[1066] 1 4 3 0 #127 -[7199] 5 2 2 0 #128 -[7969] 2 5 3 0 #129 -[7328] 1 3 3 0 #130 -[7559] 1 4 4 0 #131 -out:o_1_ 6 3 3 0 #132 -out:o_2_ 0 2 3 0 #133 -out:o_0_ 3 6 5 0 #134 -i_30_ 3 6 3 0 #135 -i_20_ 6 5 2 0 #136 -i_9_ 2 0 5 0 #137 -i_10_ 4 0 1 0 #138 -i_7_ 3 6 1 0 #139 -i_8_ 2 0 7 0 #140 -i_5_ 2 0 1 0 #141 -i_6_ 3 0 7 0 #142 -i_27_ 4 6 6 0 #143 -i_14_ 4 6 3 0 #144 -i_3_ 4 6 5 0 #145 -i_28_ 3 0 6 0 #146 -i_13_ 4 6 0 0 #147 -i_4_ 6 1 6 0 #148 -i_25_ 2 6 1 0 #149 -i_12_ 2 0 4 0 #150 -i_1_ 6 1 5 0 #151 -i_26_ 4 0 4 0 #152 -i_11_ 2 0 3 0 #153 -i_2_ 6 1 7 0 #154 -i_23_ 3 6 4 0 #155 -i_18_ 2 0 2 0 #156 -i_24_ 3 0 5 0 #157 -i_17_ 3 6 2 0 #158 -i_0_ 4 0 0 0 #159 -i_21_ 4 6 4 0 #160 -i_16_ 3 6 6 0 #161 -i_22_ 2 0 0 0 #162 -i_32_ 3 0 0 0 #163 -i_31_ 3 6 7 0 #164 -i_34_ 3 6 0 0 #165 -i_33_ 3 0 3 0 #166 -i_19_ 2 0 6 0 #167 -i_36_ 5 6 7 0 #168 -i_35_ 3 0 4 0 #169 -i_38_ 3 0 2 0 #170 -i_29_ 4 6 1 0 #171 -i_37_ 4 0 5 0 #172 +o_1_ 4 1 4 0 #0 +o_2_ 4 3 4 0 #1 +o_0_ 2 2 0 0 #2 +n_n1829 3 5 4 0 #3 +n_n1812 5 3 5 0 #4 +n_n1866 4 5 1 0 #5 +n_n1865 4 5 3 0 #6 +[493] 2 1 2 0 #7 +n_n544 3 1 0 0 #8 +n_n416 4 4 0 0 #9 +n_n394 5 4 5 0 #10 +n_n391 5 3 4 0 #11 +n_n300 4 5 5 0 #12 +[260] 3 2 4 0 #13 +[223] 3 1 4 0 #14 +[79] 2 2 4 0 #15 +[410] 1 3 1 0 #16 +[516] 1 3 2 0 #17 +[530] 1 1 1 0 #18 +[245] 1 2 0 0 #19 +[340] 1 4 4 0 #20 +[432] 3 1 2 0 #21 +[533] 2 3 3 0 #22 +[80] 2 2 5 0 #23 +[535] 1 2 1 0 #24 +n_n316 4 2 4 0 #25 +[541] 1 2 5 0 #26 +n_n1563 2 2 1 0 #27 +n_n1585 2 3 4 0 #28 +[38] 2 3 2 0 #29 +n_n706 4 2 3 0 #30 +n_n608 2 1 1 0 #31 +[261] 4 1 0 0 #32 +[463] 5 1 3 0 #33 +n_n1578 1 2 3 0 #34 +[124] 2 3 1 0 #35 +[132] 3 3 2 0 #36 +[227] 1 1 3 0 #37 +[267] 2 2 2 0 #38 +n_n329 2 2 3 0 #39 +n_n849 4 5 0 0 #40 +[478] 2 3 0 0 #41 +[578] 5 5 0 0 #42 +[253] 5 3 2 0 #43 +[4] 5 4 3 0 #44 +[56] 4 4 3 0 #45 +[226] 4 2 5 0 #46 +[282] 5 4 2 0 #47 +[377] 5 5 4 0 #48 +[71] 5 3 3 0 #49 +[246] 3 2 1 0 #50 +[301] 3 1 1 0 #51 +[311] 4 4 4 0 #52 +[344] 4 4 1 0 #53 +[310] 4 2 2 0 #54 +[315] 4 3 0 0 #55 +[78] 3 5 5 0 #56 +[656] 5 3 0 0 #57 +[29] 2 4 1 0 #58 +[273] 3 1 3 0 #59 +[668] 1 2 4 0 #60 +[674] 5 3 1 0 #61 +[74] 1 2 2 0 #62 +n_n1704 4 1 3 0 #63 +[327] 4 5 2 0 #64 +[305] 1 4 3 0 #65 +n_n1702 4 1 5 0 #66 +[351] 5 2 3 0 #67 +[437] 3 3 3 0 #68 +[349] 5 1 5 0 #69 +[65] 1 1 0 0 #70 +[221] 2 1 5 0 #71 +[343] 3 4 5 0 #72 +[406] 5 2 5 0 #73 +[521] 5 4 0 0 #74 +[161] 3 1 5 0 #75 +[189] 2 4 2 0 #76 +[906] 2 4 3 0 #77 +[977] 4 3 5 0 #78 +[1340] 4 4 5 0 #79 +[1426] 5 2 1 0 #80 +[1435] 5 4 1 0 #81 +[1542] 4 3 3 0 #82 +[1615] 3 4 3 0 #83 +[1619] 4 1 2 0 #84 +[6958] 1 4 2 0 #85 +[7025] 5 2 4 0 #86 +[7082] 1 1 5 0 #87 +[7160] 3 2 2 0 #88 +[7319] 3 4 0 0 #89 +[7321] 4 5 4 0 #90 +[7388] 3 3 0 0 #91 +[7390] 3 5 2 0 #92 +[7787] 1 3 3 0 #93 +[7791] 2 3 5 0 #94 +[7811] 2 1 3 0 #95 +[7822] 4 2 0 0 #96 +[7829] 2 1 4 0 #97 +[7885] 3 4 4 0 #98 +[7899] 1 3 5 0 #99 +[7901] 1 1 4 0 #100 +[7997] 1 3 4 0 #101 +[8027] 2 1 0 0 #102 +[8042] 1 4 1 0 #103 +[50] 3 5 3 0 #104 +[307] 3 2 5 0 #105 +[275] 3 2 3 0 #106 +[372] 3 4 1 0 #107 +[503] 3 5 0 0 #108 +[585] 2 4 4 0 #109 +[63] 2 5 3 0 #110 +[431] 5 2 2 0 #111 +[447] 3 3 1 0 #112 +[615] 2 4 5 0 #113 +n_n1716 1 3 0 0 #114 +[254] 4 3 2 0 #115 +[381] 5 4 4 0 #116 +[430] 4 3 1 0 #117 +[276] 4 4 2 0 #118 +[760] 3 4 2 0 #119 +[768] 4 1 1 0 #120 +[792] 2 5 2 0 #121 +[721] 5 2 0 0 #122 +[877] 3 2 0 0 #123 +[884] 4 2 1 0 #124 +[1021] 3 3 5 0 #125 +[1077] 3 3 4 0 #126 +[1700] 1 4 0 0 #127 +[7108] 2 4 0 0 #128 +[7211] 5 1 1 0 #129 +[7516] 2 5 0 0 #130 +[7531] 2 5 4 0 #131 +[7820] 1 4 5 0 #132 +[7917] 2 5 5 0 #133 +[7028] 2 5 1 0 #134 +[7774] 1 5 5 0 #135 +[7778] 1 5 2 0 #136 +[177] 1 1 2 0 #137 +out:o_1_ 4 0 0 0 #138 +out:o_2_ 4 6 1 0 #139 +out:o_0_ 2 0 4 0 #140 +i_30_ 2 6 7 0 #141 +i_20_ 2 0 3 0 #142 +i_9_ 5 6 5 0 #143 +i_10_ 3 6 6 0 #144 +i_7_ 2 0 5 0 #145 +i_8_ 4 6 4 0 #146 +i_5_ 5 6 6 0 #147 +i_6_ 3 0 3 0 #148 +i_27_ 3 0 1 0 #149 +i_14_ 2 0 1 0 #150 +i_3_ 6 4 5 0 #151 +i_28_ 3 0 7 0 #152 +i_13_ 2 0 2 0 #153 +i_4_ 6 2 7 0 #154 +i_25_ 4 6 0 0 #155 +i_12_ 1 0 4 0 #156 +i_1_ 6 2 2 0 #157 +i_26_ 3 6 2 0 #158 +i_11_ 4 0 1 0 #159 +i_2_ 4 6 7 0 #160 +i_23_ 2 0 7 0 #161 +i_18_ 5 6 4 0 #162 +i_24_ 2 0 6 0 #163 +i_17_ 3 0 0 0 #164 +i_0_ 4 0 5 0 #165 +i_21_ 2 6 1 0 #166 +i_16_ 0 3 0 0 #167 +i_22_ 3 6 0 0 #168 +i_32_ 3 6 7 0 #169 +i_31_ 2 6 5 0 #170 +i_34_ 1 0 6 0 #171 +i_33_ 4 0 7 0 #172 +i_19_ 6 4 6 0 #173 +i_36_ 1 0 1 0 #174 +i_35_ 1 0 7 0 #175 +i_38_ 4 6 3 0 #176 +i_29_ 3 6 1 0 #177 +i_37_ 3 0 6 0 #178 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt index e41ab909d3a..98cc3d128ec 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 14.77 vpr 75.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76916 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.4 MiB 4.62 5572 1135 0 0 1135 75.1 MiB 0.08 0.01 5.10521 -15.0504 -5.10521 nan 0.19 0.00530639 0.00465724 0.0561264 0.0529208 -1 -1 -1 -1 164 7542 34 1.34735e+06 7.11401e+06 957298. 19536.7 7.09 2.13567 1.82713 18546 296938 -1 6979 21 5560 22630 961929 323712 5.65021 nan -16.5347 -5.65021 0 0 1.19720e+06 24432.6 0.05 0.66 0.37 -1 -1 0.05 0.343651 0.311264 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fix_clusters_test_arch.xml apex2.blif common 6.23 vpr 73.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 138 38 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75236 38 3 1916 1919 0 1057 179 7 7 49 clb auto 34.1 MiB 2.35 5571 5572 1187 0 0 1187 73.5 MiB 0.04 0.00 4.76188 4.76188 -14.2451 -4.76188 nan 0.08 0.00208545 0.00186173 0.0310117 0.0298705 -1 -1 -1 -1 158 7466 37 1.34735e+06 7.43737e+06 924312. 18863.5 2.34 0.677508 0.587661 18354 286522 -1 7089 17 5844 24589 1071101 337183 5.3663 nan -15.678 -5.3663 0 0 1.15416e+06 23554.3 0.02 0.27 0.14 -1 -1 0.02 0.139789 0.12986 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index c4013f9bc8c..9b948711612 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.09 vpr 66.02 MiB -1 -1 0.81 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67608 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.06 152 364 33 322 9 66.0 MiB 0.01 0.00 2.14643 -90.9948 -2.14643 2.14643 0.04 0.000424487 0.000372936 0.00685813 0.00616631 -1 -1 -1 -1 12 186 21 646728 646728 19965.4 554.594 0.11 0.0652242 0.0564867 1696 3924 -1 174 15 217 480 10553 3153 2.17275 2.17275 -93.6282 -2.17275 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0180304 0.016231 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 64.27 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32964 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 296 27 253 16 64.3 MiB 0.01 0.00 2.24217 2.14643 -91.5793 -2.14643 2.14643 0.01 0.000335492 0.000314689 0.00350594 0.00327742 -1 -1 -1 -1 14 192 17 646728 646728 22986.6 638.518 0.06 0.0356328 0.0309596 1728 4488 -1 182 16 236 481 10669 3290 2.16575 2.16575 -94.0923 -2.16575 0 0 30529.5 848.041 0.00 0.01 0.00 -1 -1 0.00 0.0100937 0.00903234 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt index ce66e9945a6..23f9598f828 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 1.95 vpr 67.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 14 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 14 8 926 934 0 494 101 11 11 121 -1 mcnc_small 28.1 MiB 0.87 4705 3156 292 2673 191 67.8 MiB 0.15 0.01 4.69669 -33.5098 -4.69669 nan 0.00 0.00334751 0.00291356 0.0814872 0.072816 -1 -1 -1 -1 -1 6609 17 4.36541e+06 4.25763e+06 511363. 4226.14 0.32 0.279395 0.254136 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 1.11 vpr 65.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67296 14 8 926 934 0 487 100 11 11 121 -1 mcnc_small 26.7 MiB 0.56 4953 4661 2884 275 2439 170 65.7 MiB 0.06 0.00 4.90946 4.65107 -32.6907 -4.65107 nan 0.00 0.00127156 0.0011063 0.0300633 0.0277592 -1 -1 -1 -1 -1 6424 17 4.36541e+06 4.20373e+06 511363. 4226.14 0.13 0.110566 0.102078 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index 0be72798bb2..7eb8d053014 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 6.51 vpr 78.23 MiB -1 -1 1.74 32316 16 0.38 -1 -1 34724 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80104 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.9 MiB 1.74 9794 6883 28689 8164 16986 3539 78.2 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00180615 0.00158429 0.162884 0.143795 -1 -1 -1 -1 -1 10585 12 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.05 0.208714 0.183536 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 7.03 vpr 77.86 MiB -1 -1 1.73 32316 16 0.37 -1 -1 34728 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 79728 45 32 1192 1151 1 782 141 14 14 196 memory auto 39.6 MiB 1.89 9794 6883 28689 8164 16986 3539 77.9 MiB 0.44 0.01 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00273275 0.00231808 0.222874 0.195896 -1 -1 -1 -1 -1 10620 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.27 0.289534 0.251628 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 10.17 vpr 78.52 MiB -1 -1 1.76 32332 16 0.37 -1 -1 34728 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80400 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.3 MiB 1.70 9794 6883 28689 8164 16986 3539 78.5 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00182918 0.00160106 0.163945 0.144335 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 4.73 0.214342 0.188032 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 13.04 vpr 78.43 MiB -1 -1 1.72 31948 16 0.38 -1 -1 34428 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80312 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.3 MiB 1.72 9794 6883 28689 8164 16986 3539 78.4 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00182981 0.00160205 0.163671 0.144301 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 7.56 0.218898 0.192942 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 9.13 vpr 78.43 MiB -1 -1 1.78 32312 16 0.37 -1 -1 34724 -1 -1 60 45 3 1 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 80316 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.3 MiB 1.69 9794 6883 28689 8164 16986 3539 78.4 MiB 0.35 0.00 11.8719 10.9558 -7219.74 -10.9558 10.9558 0.00 0.00182715 0.00160038 0.16255 0.143378 -1 -1 -1 -1 -1 10536 11 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 3.64 0.211401 0.186214 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 6.01 vpr 77.68 MiB -1 -1 1.68 32288 16 0.36 -1 -1 34604 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79540 45 32 1192 1151 1 792 142 14 14 196 memory auto 40.6 MiB 1.58 10043 6801 30482 8149 18842 3491 77.7 MiB 0.34 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00171355 0.00152094 0.162718 0.14447 -1 -1 -1 -1 -1 10299 11 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 0.88 0.202524 0.179111 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 6.27 vpr 77.15 MiB -1 -1 1.71 32288 16 0.37 -1 -1 34608 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79000 45 32 1192 1151 1 792 142 14 14 196 memory auto 39.9 MiB 1.64 10043 6801 30482 8149 18842 3491 77.1 MiB 0.39 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00214484 0.00195565 0.196008 0.174756 -1 -1 -1 -1 -1 10115 13 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 0.95 0.248675 0.219198 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 9.25 vpr 77.65 MiB -1 -1 1.66 31904 16 0.35 -1 -1 34608 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79516 45 32 1192 1151 1 792 142 14 14 196 memory auto 40.6 MiB 1.57 10043 6801 30482 8149 18842 3491 77.7 MiB 0.34 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00177126 0.00157234 0.163228 0.145232 -1 -1 -1 -1 -1 10238 12 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 4.18 0.209091 0.185247 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 9.88 vpr 77.00 MiB -1 -1 1.78 31520 16 0.37 -1 -1 34608 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78844 45 32 1192 1151 1 792 142 14 14 196 memory auto 40.0 MiB 1.62 10043 6801 30482 8149 18842 3491 77.0 MiB 0.35 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00173508 0.00153623 0.165626 0.146946 -1 -1 -1 -1 -1 10238 12 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 4.50 0.217008 0.191955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 8.49 vpr 77.91 MiB -1 -1 1.72 31908 16 0.37 -1 -1 34604 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79784 45 32 1192 1151 1 792 142 14 14 196 memory auto 40.6 MiB 1.62 10043 6801 30482 8149 18842 3491 77.9 MiB 0.35 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00171847 0.00152015 0.16361 0.145098 -1 -1 -1 -1 -1 10238 12 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 3.23 0.210793 0.186366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 120190057e8..4e9493beb61 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 28.09 vpr 86.75 MiB -1 -1 4.22 45380 3 0.89 -1 -1 40652 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88832 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.9 MiB 3.72 13488 259154 85177 151229 22748 86.8 MiB 1.98 0.02 4.96832 -2863.05 -4.96832 4.96832 0.58 0.00616009 0.0056108 0.73686 0.651724 -1 -1 -1 -1 70 25183 26 1.65001e+07 9.87633e+06 1.20853e+06 3347.73 11.82 3.63311 3.252 37321 249029 -1 22818 16 6009 15172 1561129 440571 5.14889 5.14889 -3166.68 -5.14889 0 0 1.52253e+06 4217.55 0.11 0.96 0.44 -1 -1 0.11 0.466679 0.43649 - buffered_flyover_wires.xml raygentop.v common 23.51 vpr 86.14 MiB -1 -1 4.32 45316 3 0.90 -1 -1 40936 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88212 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 3.23 13888 238357 80681 139370 18306 86.1 MiB 2.42 0.04 5.12299 -3013.43 -5.12299 5.12299 0.55 0.0104225 0.00890059 0.853806 0.753587 -1 -1 -1 -1 68 27200 39 1.65001e+07 9.87633e+06 1.22105e+06 3382.40 7.94 3.27933 2.93318 36601 236909 -1 22538 20 6241 16122 1654804 449740 5.13382 5.13382 -3162.81 -5.13382 0 0 1.52022e+06 4211.15 0.06 0.81 0.27 -1 -1 0.06 0.458331 0.421893 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +shorted_flyover_wires.xml raygentop.v common 11.46 vpr 85.09 MiB -1 -1 2.03 42452 3 0.51 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87132 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.9 MiB 1.81 27296 13779 258108 83434 152259 22415 85.1 MiB 0.97 0.01 7.04327 4.6633 -2876.07 -4.6633 4.6633 0.21 0.00369266 0.0033896 0.35934 0.327445 -1 -1 -1 -1 66 28610 42 1.65001e+07 9.76854e+06 1.15238e+06 3192.19 3.53 1.25456 1.14436 36241 234685 -1 23562 17 7064 18761 2090675 558075 5.13544 5.13544 -3151.56 -5.13544 0 0 1.43513e+06 3975.42 0.04 0.44 0.14 -1 -1 0.04 0.201995 0.190283 +buffered_flyover_wires.xml raygentop.v common 11.12 vpr 85.59 MiB -1 -1 2.02 42076 3 0.51 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87648 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 46.3 MiB 1.81 27785 13427 264026 91487 153189 19350 85.6 MiB 1.03 0.01 6.32496 5.30188 -3110.04 -5.30188 5.30188 0.22 0.00395257 0.00354299 0.383991 0.348239 -1 -1 -1 -1 68 25731 48 1.65001e+07 9.76854e+06 1.22105e+06 3382.40 3.17 1.46185 1.33293 36601 236909 -1 21906 18 6197 16350 1514118 406281 5.17215 5.17215 -3213.24 -5.17215 0 0 1.52022e+06 4211.15 0.04 0.38 0.15 -1 -1 0.04 0.206095 0.194201 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index dabc7597d44..ae490f43ed2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 6.82 vpr 64.38 MiB -1 -1 0.19 22024 1 0.04 -1 -1 33832 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65924 193 32 545 422 1 386 228 22 22 484 block_FPU auto 25.0 MiB 5.38 4984 53124 22938 29850 336 64.4 MiB 0.31 0.00 2.985 -851.626 -2.985 2.985 0.00 0.00244064 0.00235262 0.159831 0.149979 -1 -1 -1 -1 6456 16.7688 1716 4.45714 553 553 191807 53335 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -877.692 -2.985 -13.5705 -0.0851 0.36 -1 -1 64.4 MiB 0.06 0.186546 0.175569 64.4 MiB -1 0.10 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +hard_fpu_arch_timing.xml mm3.v common 1.28 vpr 62.66 MiB -1 -1 0.11 18300 1 0.03 -1 -1 30628 -1 -1 0 193 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64160 193 32 545 422 1 385 229 30 30 900 block_FPU auto 23.1 MiB 0.16 8272 4968 58329 25699 32293 337 62.7 MiB 0.17 0.00 2.985 2.985 -855.954 -2.985 2.985 0.00 0.00102583 0.000966153 0.089769 0.084748 -1 -1 -1 -1 6670 17.3698 1756 4.57292 533 533 185005 50756 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -882.014 -2.985 -13.6953 -0.0851 0.28 -1 -1 62.7 MiB 0.04 0.107853 0.101999 62.7 MiB -1 0.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index e0477400548..f345fde64cd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.15 vpr 68.14 MiB -1 -1 0.41 22436 3 0.11 -1 -1 37108 -1 -1 67 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69772 99 130 344 474 1 216 297 13 13 169 clb auto 28.7 MiB 1.30 640 27027 4243 10587 12197 68.1 MiB 0.05 0.00 34 1346 6 0 0 460544. 2725.11 1.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 2.01 vpr 66.15 MiB -1 -1 0.22 18728 3 0.06 -1 -1 33276 -1 -1 67 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67736 99 130 344 474 1 217 297 13 13 169 clb auto 26.3 MiB 0.76 1670 634 27027 2767 7163 17097 66.1 MiB 0.02 0.00 34 1203 16 0 0 460544. 2725.11 0.23 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index cf73f2ff4e0..247acfa46dc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.78 vpr 66.14 MiB -1 -1 0.81 27148 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67724 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000401166 0.00034964 0.00709766 0.00632609 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.027091 0.0241271 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.06 vpr 63.98 MiB -1 -1 0.41 23428 5 0.10 -1 -1 32964 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65516 10 2 181 183 1 36 24 6 6 36 clb auto 24.6 MiB 0.02 196 151 534 120 387 27 64.0 MiB 0.01 0.00 2.24505 2.14835 -91.7778 -2.14835 2.14835 0.00 0.000222636 0.000202558 0.0047703 0.00439302 -1 -1 -1 -1 -1 141 16 646728 646728 60312.4 1675.34 0.01 0.01476 0.0132928 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index f56e6001d52..79a3b00fa18 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.43 vpr 60.44 MiB -1 -1 -1 -1 0 0.02 -1 -1 33044 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61892 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.1 MiB 0.00 0 3 0 0 3 60.4 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4987e-05 8.361e-06 8.9733e-05 6.0433e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00144709 0.00137547 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.48 vpr 60.32 MiB -1 -1 -1 -1 0 0.02 -1 -1 33032 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61768 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.0 MiB 0.00 0 3 0 0 3 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3826e-05 7.652e-06 8.7137e-05 5.7527e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00164227 0.00157106 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.51 vpr 60.30 MiB -1 -1 -1 -1 0 0.02 -1 -1 33252 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61752 6 1 1 8 0 1 8 3 3 9 -1 auto 22.1 MiB 0.00 0 21 0 10 11 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2976e-05 6.744e-06 7.713e-05 4.9652e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00173371 0.00166423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.39 vpr 60.55 MiB -1 -1 -1 -1 0 0.02 -1 -1 33080 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62004 6 1 1 8 0 1 8 3 3 9 -1 auto 22.1 MiB 0.00 0 21 0 10 11 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2909e-05 6.758e-06 8.8443e-05 5.844e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00166613 0.00149072 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.39 vpr 60.46 MiB -1 -1 -1 -1 1 0.02 -1 -1 33424 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 2 1 3 4 0 3 4 3 3 9 -1 auto 22.1 MiB 0.00 9 9 3 3 3 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.603e-05 1.0932e-05 0.000113667 8.4174e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00156248 0.00148561 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.53 vpr 60.38 MiB -1 -1 -1 -1 1 0.06 -1 -1 35020 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61832 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.4 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.1156e-05 1.5721e-05 0.000164706 0.000132685 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.0021653 0.00196366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.54 vpr 60.58 MiB -1 -1 -1 -1 1 0.06 -1 -1 35532 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 5 1 6 7 0 6 7 3 3 9 -1 auto 22.3 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.769e-05 2.1131e-05 0.000172602 0.000136847 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00216675 0.00196156 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.35 vpr 60.45 MiB -1 -1 -1 -1 1 0.02 -1 -1 33200 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61900 3 1 5 6 1 4 5 3 3 9 -1 auto 22.1 MiB 0.00 9 12 7 1 4 60.4 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.0212e-05 1.4682e-05 0.000132923 0.000102253 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00163341 0.00154977 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml false_path_mux.blif common 0.52 vpr 60.54 MiB -1 -1 -1 -1 1 0.06 -1 -1 35376 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61992 4 1 4 6 0 4 6 3 3 9 -1 auto 22.1 MiB 0.00 12 15 9 3 3 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.9387e-05 1.4052e-05 0.000137513 0.000106148 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00195643 0.00179437 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_2x2.blif common 0.50 vpr 60.48 MiB -1 -1 -1 -1 1 0.05 -1 -1 35232 -1 -1 1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61928 4 4 8 12 0 8 9 3 3 9 -1 auto 22.1 MiB 0.00 24 27 18 6 3 60.5 MiB 0.00 0.00 0.67231 -2.68924 -0.67231 nan 0.00 5.0286e-05 3.8471e-05 0.00028724 0.000243111 -1 -1 -1 -1 -1 10 10 53894 53894 38783.3 4309.26 0.00 0.00268807 0.00242566 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x3.blif common 0.52 vpr 60.40 MiB -1 -1 -1 -1 1 0.07 -1 -1 36088 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61848 6 6 12 18 0 12 13 3 3 9 -1 auto 22.1 MiB 0.01 36 43 32 7 4 60.4 MiB 0.00 0.00 0.69831 -4.13786 -0.69831 nan 0.00 5.0007e-05 4.1034e-05 0.000382344 0.000335402 -1 -1 -1 -1 -1 17 12 53894 53894 38783.3 4309.26 0.00 0.00342842 0.00312147 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x4.blif common 0.46 vpr 60.50 MiB -1 -1 -1 -1 2 0.06 -1 -1 35480 -1 -1 3 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61952 7 8 22 30 0 15 18 4 4 16 clb auto 22.0 MiB 0.01 51 64 26 37 1 60.5 MiB 0.00 0.00 1.24888 -7.62396 -1.24888 nan 0.00 9.577e-05 8.3665e-05 0.00076909 0.000710256 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00462233 0.00417537 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_4x4.blif common 0.59 vpr 60.60 MiB -1 -1 -1 -1 4 0.09 -1 -1 35628 -1 -1 2 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62056 8 8 29 37 0 21 18 4 4 16 clb auto 22.1 MiB 0.02 74 64 20 44 0 60.6 MiB 0.00 0.00 2.04839 -11.7951 -2.04839 nan 0.00 0.000130354 0.000112521 0.00109012 0.00100934 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.01 0.00751475 0.0068714 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x5.blif common 0.62 vpr 61.08 MiB -1 -1 -1 -1 4 0.10 -1 -1 36048 -1 -1 4 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62548 10 10 47 57 0 39 24 4 4 16 clb auto 22.1 MiB 0.02 149 92 35 57 0 61.1 MiB 0.00 0.00 2.73035 -18.1288 -2.73035 nan 0.00 0.000192825 0.000170363 0.0016493 0.0015433 -1 -1 -1 -1 -1 123 10 215576 215576 99039.1 6189.95 0.01 0.00945092 0.00871858 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x6.blif common 0.78 vpr 61.08 MiB -1 -1 -1 -1 5 0.12 -1 -1 36408 -1 -1 5 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62544 11 11 61 72 0 51 27 5 5 25 clb auto 22.1 MiB 0.04 192 547 116 431 0 61.1 MiB 0.01 0.00 3.17925 -21.2667 -3.17925 nan 0.00 0.000440575 0.000406236 0.00673609 0.00616031 -1 -1 -1 -1 -1 163 16 485046 269470 186194. 7447.77 0.02 0.0214973 0.0195896 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_1bit.blif common 0.44 vpr 60.18 MiB -1 -1 -1 -1 1 0.05 -1 -1 34452 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61628 3 2 5 7 0 5 6 3 3 9 -1 auto 22.0 MiB 0.00 15 15 9 5 1 60.2 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 1.5359e-05 1.1242e-05 0.000119111 9.5167e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00191506 0.00178438 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_2bit.blif common 0.51 vpr 60.47 MiB -1 -1 -1 -1 1 0.06 -1 -1 35224 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61920 5 3 8 11 0 8 9 3 3 9 -1 auto 22.0 MiB 0.00 24 27 21 6 0 60.5 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 5.5301e-05 4.4627e-05 0.000313259 0.000267198 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00296269 0.00261801 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_3bit.blif common 0.50 vpr 60.56 MiB -1 -1 -1 -1 2 0.05 -1 -1 35444 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62016 7 4 12 16 0 11 12 3 3 9 -1 auto 22.1 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 2.6083e-05 2.0859e-05 0.000215587 0.000188913 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00234895 0.0022029 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_4bit.blif common 0.54 vpr 60.64 MiB -1 -1 -1 -1 2 0.06 -1 -1 35364 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62096 9 5 15 20 0 14 15 3 3 9 -1 auto 22.1 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 0.000111332 9.9634e-05 0.000559539 0.000502391 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.00351338 0.00318651 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_5bit.blif common 0.52 vpr 60.46 MiB -1 -1 -1 -1 3 0.07 -1 -1 35520 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 11 6 19 25 0 17 18 3 3 9 -1 auto 22.0 MiB 0.01 51 64 33 24 7 60.5 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 0.000697205 8.3358e-05 0.00115444 0.000499005 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00500091 0.00398839 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.35 vpr 58.06 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59452 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.6 MiB 0.00 0 0 3 0 0 3 58.1 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.359e-06 3.476e-06 5.5645e-05 3.585e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000873938 0.000817223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.31 vpr 58.67 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.3e-06 3.512e-06 5.499e-05 3.6206e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000892963 0.000836486 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.35 vpr 58.60 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60008 6 1 1 8 0 1 8 3 3 9 -1 auto 20.2 MiB 0.00 0 0 21 0 10 11 58.6 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.343e-06 3.449e-06 5.5257e-05 3.6332e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00089067 0.000837628 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.34 vpr 58.66 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 6 1 1 8 0 1 8 3 3 9 -1 auto 19.9 MiB 0.00 0 0 21 0 10 11 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.587e-06 3.716e-06 5.4406e-05 3.4996e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000917158 0.000862935 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and.blif common 0.36 vpr 59.04 MiB -1 -1 -1 -1 1 0.02 -1 -1 29952 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 2 1 3 4 0 3 4 3 3 9 -1 auto 20.2 MiB 0.00 9 9 9 3 3 3 59.0 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 8.998e-06 5.729e-06 7.4084e-05 5.5177e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000991073 0.000933863 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.38 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31488 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 5 1 6 7 0 6 7 3 3 9 -1 auto 20.2 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 3.9064e-05 8.628e-06 0.000128172 7.9888e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00115707 0.0010134 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.38 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31844 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 5 1 6 7 0 6 7 3 3 9 -1 auto 20.2 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.2372e-05 8.797e-06 0.000102625 8.1155e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00116441 0.00104858 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and_latch.blif common 0.29 vpr 58.64 MiB -1 -1 -1 -1 1 0.02 -1 -1 30396 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60048 3 1 5 6 1 4 5 3 3 9 -1 auto 19.8 MiB 0.00 9 9 12 7 1 4 58.6 MiB 0.00 0.00 0.603526 0.52647 -0.88231 -0.52647 0.52647 0.00 1.0705e-05 7.341e-06 8.8486e-05 6.7399e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000959409 0.00089725 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml false_path_mux.blif common 0.39 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31812 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 4 1 4 6 0 4 6 3 3 9 -1 auto 20.5 MiB 0.00 12 12 15 9 3 3 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 9.788e-06 6.583e-06 8.1737e-05 6.1503e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.0010608 0.000952163 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_2x2.blif common 0.39 vpr 58.68 MiB -1 -1 -1 -1 1 0.03 -1 -1 31488 -1 -1 1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60092 4 4 8 12 0 8 9 3 3 9 -1 auto 19.9 MiB 0.00 24 24 27 18 6 3 58.7 MiB 0.00 0.00 0.749366 0.67231 -2.68924 -0.67231 nan 0.00 1.8939e-05 1.3649e-05 0.000162092 0.000138463 -1 -1 -1 -1 -1 12 10 53894 53894 38783.3 4309.26 0.00 0.00140862 0.00128245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x3.blif common 0.37 vpr 58.71 MiB -1 -1 -1 -1 1 0.04 -1 -1 31968 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60120 6 6 12 18 0 12 13 3 3 9 -1 auto 19.9 MiB 0.00 36 36 43 32 7 4 58.7 MiB 0.00 0.00 0.775365 0.69831 -4.13786 -0.69831 nan 0.00 2.7335e-05 2.2775e-05 0.000258357 0.000231618 -1 -1 -1 -1 -1 15 12 53894 53894 38783.3 4309.26 0.00 0.00192479 0.00174204 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x4.blif common 0.42 vpr 58.85 MiB -1 -1 -1 -1 2 0.04 -1 -1 32096 -1 -1 3 7 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60264 7 8 22 30 0 15 18 4 4 16 clb auto 20.2 MiB 0.01 62 51 64 26 37 1 58.9 MiB 0.00 0.00 1.24888 1.24888 -7.62396 -1.24888 nan 0.00 4.707e-05 4.1118e-05 0.000466731 0.00043626 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00249603 0.0023213 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 0.42 vpr 58.89 MiB -1 -1 -1 -1 4 0.05 -1 -1 32476 -1 -1 2 8 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60300 8 8 29 37 0 21 18 4 4 16 clb auto 19.9 MiB 0.01 82 74 64 20 44 0 58.9 MiB 0.00 0.00 2.04839 2.04839 -11.7951 -2.04839 nan 0.00 6.5626e-05 5.6815e-05 0.000641099 0.000602927 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.00 0.00383531 0.00351223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 0.48 vpr 59.06 MiB -1 -1 -1 -1 4 0.05 -1 -1 32832 -1 -1 4 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60480 10 10 47 57 0 39 24 4 4 16 clb auto 19.9 MiB 0.01 161 149 92 35 57 0 59.1 MiB 0.00 0.00 2.80144 2.73035 -18.1288 -2.73035 nan 0.00 9.8348e-05 8.8676e-05 0.000979759 0.000931858 -1 -1 -1 -1 -1 120 10 215576 215576 99039.1 6189.95 0.01 0.00519014 0.00479486 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 0.53 vpr 59.55 MiB -1 -1 -1 -1 5 0.08 -1 -1 32920 -1 -1 5 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60984 11 11 61 72 0 49 27 5 5 25 clb auto 20.2 MiB 0.02 227 192 427 90 337 0 59.6 MiB 0.00 0.00 3.28962 3.19291 -21.0185 -3.19291 nan 0.00 0.000128815 0.000117588 0.00236378 0.00220408 -1 -1 -1 -1 -1 193 14 485046 269470 186194. 7447.77 0.01 0.00880785 0.00804809 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.40 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31076 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 3 2 5 7 0 5 6 3 3 9 -1 auto 19.9 MiB 0.00 15 15 15 9 5 1 58.7 MiB 0.00 0.00 0.749366 0.67231 -1.34462 -0.67231 nan 0.00 1.2467e-05 8.835e-06 0.000106543 8.3665e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00119604 0.00107178 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.37 vpr 58.68 MiB -1 -1 -1 -1 1 0.03 -1 -1 32244 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60092 5 3 8 11 0 8 9 3 3 9 -1 auto 20.2 MiB 0.00 24 24 27 21 6 0 58.7 MiB 0.00 0.00 0.749366 0.67231 -2.01693 -0.67231 nan 0.00 1.8254e-05 1.2993e-05 0.000148648 0.000125027 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.0014931 0.0013283 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.38 vpr 58.69 MiB -1 -1 -1 -1 2 0.03 -1 -1 32240 -1 -1 1 7 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60100 7 4 12 16 0 11 12 3 3 9 -1 auto 20.2 MiB 0.00 33 33 38 24 11 3 58.7 MiB 0.00 0.00 1.08437 1.08437 -4.00246 -1.08437 nan 0.00 2.2984e-05 1.8516e-05 0.000207845 0.000175806 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00145538 0.00134835 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.41 vpr 58.46 MiB -1 -1 -1 -1 2 0.04 -1 -1 32252 -1 -1 1 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59868 9 5 15 20 0 14 15 3 3 9 -1 auto 20.1 MiB 0.00 42 42 51 29 17 5 58.5 MiB 0.00 0.00 1.08437 1.00731 -4.36655 -1.00731 nan 0.00 2.742e-05 2.2732e-05 0.000248101 0.000222336 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.0019693 0.00177377 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.38 vpr 58.76 MiB -1 -1 -1 -1 3 0.04 -1 -1 32252 -1 -1 1 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60168 11 6 19 25 0 17 18 3 3 9 -1 auto 19.9 MiB 0.00 51 51 64 36 21 7 58.8 MiB 0.00 0.00 1.41937 1.34231 -6.71386 -1.34231 nan 0.00 3.3633e-05 2.7198e-05 0.000306471 0.000277811 -1 -1 -1 -1 -1 21 11 53894 53894 38783.3 4309.26 0.00 0.00206016 0.00187465 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt index b020b50a0e5..1ecd9f11e08 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.27 vpr 60.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61896 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.1 MiB 0.00 0 3 0 0 3 60.4 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1967e-05 6.442e-06 7.5021e-05 4.7762e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.0014839 0.00141592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2368e-05 6.553e-06 8.0604e-05 5.2726e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00150763 0.00143643 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.26 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4901e-05 1.736e-05 0.000158286 0.000127589 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00189837 0.00180984 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4603e-05 1.7125e-05 0.000156465 0.000123185 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00157342 0.00148859 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.34 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 5 1 6 7 0 6 7 3 3 9 -1 auto 22.3 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.3071e-05 1.7468e-05 0.00015565 0.000122418 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00131998 0.0012364 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4504e-05 1.843e-05 0.0003637 0.000327179 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00295184 0.00278863 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.23 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.342e-06 3.456e-06 5.6768e-05 3.7362e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000896307 0.000835936 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.23 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.9 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.496e-06 3.551e-06 5.473e-05 3.5509e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000856124 0.000804075 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.22 vpr 58.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59692 6 1 7 8 0 7 8 3 3 9 -1 auto 19.9 MiB 0.00 21 21 21 14 7 0 58.3 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.3219e-05 8.724e-06 9.8134e-05 7.7659e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.000949863 0.000887812 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.22 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 6 1 7 8 0 7 8 3 3 9 -1 auto 20.2 MiB 0.00 21 21 21 14 7 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.3984e-05 9.157e-06 9.9693e-05 7.937e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00102012 0.000957668 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.25 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 5 1 6 7 0 6 7 3 3 9 -1 auto 19.9 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.2769e-05 9.287e-06 9.9591e-05 7.789e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.000993215 0.000930904 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.26 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 5 1 6 7 0 6 7 3 3 9 -1 auto 19.8 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.2704e-05 9.014e-06 9.8711e-05 7.7635e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00102457 0.00096424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index 0122eef07c9..61460af32b8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 2.14 vpr 66.94 MiB -1 -1 0.82 26648 5 0.18 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.08 154 69 23 41 5 66.9 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000368162 0.000336195 0.00306832 0.0028942 -1 -1 -1 -1 8 112 5 646728 377258 -1 -1 0.14 0.0630721 0.0541641 1804 2280 -1 112 3 60 81 2140 1007 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0123441 0.0115171 - x_uniform_y_gaussian.xml stereovision3.v common 2.28 vpr 66.56 MiB -1 -1 0.87 27028 5 0.18 -1 -1 36836 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68156 10 2 181 183 1 37 19 6 6 36 clb auto 27.6 MiB 0.06 139 119 44 63 12 66.6 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000434392 0.000379213 0.00478977 0.00443186 -1 -1 -1 -1 8 108 4 646728 377258 -1 -1 0.14 0.0614636 0.053576 1804 2280 -1 92 5 93 129 3144 1427 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0131686 0.0124064 - x_gaussian_y_gaussian.xml stereovision3.v common 1.95 vpr 66.73 MiB -1 -1 0.78 27032 5 0.16 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 141 69 21 42 6 66.7 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000231421 0.000200473 0.00279286 0.00262007 -1 -1 -1 -1 6 107 4 646728 377258 -1 -1 0.13 0.0525266 0.046082 1804 2280 -1 105 4 77 102 2777 1152 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.0109087 0.0101911 - x_delta_y_uniform.xml stereovision3.v common 2.13 vpr 66.94 MiB -1 -1 0.67 26768 5 0.15 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.07 154 369 96 253 20 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000435432 0.00038302 0.00911423 0.00823072 -1 -1 -1 -1 24 117 4 646728 377258 -1 -1 0.31 0.174316 0.150618 1804 2280 -1 116 2 59 79 2150 954 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153537 0.0147732 - x_delta_y_delta.xml stereovision3.v common 2.28 vpr 66.92 MiB -1 -1 0.81 26892 5 0.18 -1 -1 36968 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68524 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.10 140 544 127 376 41 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000465798 0.000412818 0.0124105 0.0110487 -1 -1 -1 -1 48 106 2 646728 377258 -1 -1 0.23 0.117282 0.102085 1804 2280 -1 106 2 57 77 1975 772 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00952273 0.00912406 - x_uniform_y_delta.xml stereovision3.v common 2.20 vpr 66.74 MiB -1 -1 0.80 27028 5 0.22 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68344 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 127 494 89 373 32 66.7 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000426768 0.000373257 0.0117897 0.0105633 -1 -1 -1 -1 14 88 2 646728 377258 -1 -1 0.16 0.10372 0.0914305 1804 2280 -1 88 2 57 77 1819 773 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00845179 0.00814396 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +x_gaussian_y_uniform.xml stereovision3.v common 1.36 vpr 64.43 MiB -1 -1 0.49 23052 5 0.11 -1 -1 32972 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 10 2 181 183 1 38 19 6 6 36 clb auto 25.4 MiB 0.03 174 128 319 80 215 24 64.4 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000210252 0.000191555 0.00433045 0.0040507 -1 -1 -1 -1 8 83 5 646728 377258 -1 -1 0.05 0.0286843 0.0251732 1804 2280 -1 86 4 94 125 2948 1117 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00698257 0.00662571 +x_uniform_y_gaussian.xml stereovision3.v common 1.34 vpr 65.04 MiB -1 -1 0.41 23292 5 0.10 -1 -1 33008 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66604 10 2 181 183 1 38 19 6 6 36 clb auto 26.0 MiB 0.03 174 125 394 105 261 28 65.0 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000217937 0.000198402 0.00515017 0.00479852 -1 -1 -1 -1 6 93 11 646728 377258 -1 -1 0.07 0.0334088 0.0293253 1804 2280 -1 82 3 62 84 2005 787 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00687978 0.00657072 +x_gaussian_y_gaussian.xml stereovision3.v common 1.31 vpr 65.10 MiB -1 -1 0.41 23440 5 0.11 -1 -1 32940 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 10 2 181 183 1 38 19 6 6 36 clb auto 25.7 MiB 0.03 174 133 319 65 242 12 65.1 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000225609 0.000205573 0.004477 0.00418391 -1 -1 -1 -1 6 107 5 646728 377258 -1 -1 0.06 0.0291106 0.0255214 1804 2280 -1 95 6 98 132 3372 1383 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00753689 0.00707645 +x_delta_y_uniform.xml stereovision3.v common 1.31 vpr 64.97 MiB -1 -1 0.42 23052 5 0.11 -1 -1 32980 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66528 10 2 181 183 1 38 19 6 6 36 clb auto 25.9 MiB 0.03 174 147 69 22 43 4 65.0 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000228718 0.00020709 0.00234451 0.00224898 -1 -1 -1 -1 14 107 3 646728 377258 -1 -1 0.04 0.0265392 0.0232934 1804 2280 -1 107 3 66 90 2381 972 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00673078 0.00642275 +x_delta_y_delta.xml stereovision3.v common 1.32 vpr 65.40 MiB -1 -1 0.41 23432 5 0.11 -1 -1 33148 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66972 10 2 181 183 1 38 19 6 6 36 clb auto 26.1 MiB 0.03 174 131 269 71 179 19 65.4 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000219412 0.000199508 0.00413631 0.00388102 -1 -1 -1 -1 24 87 3 646728 377258 -1 -1 0.04 0.0278594 0.0245156 1804 2280 -1 86 2 58 78 1869 774 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.0064994 0.00624883 +x_uniform_y_delta.xml stereovision3.v common 1.32 vpr 64.94 MiB -1 -1 0.42 23052 5 0.10 -1 -1 32976 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66500 10 2 181 183 1 38 19 6 6 36 clb auto 25.9 MiB 0.03 174 128 369 99 241 29 64.9 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000220849 0.000200914 0.00495943 0.00462535 -1 -1 -1 -1 24 82 2 646728 377258 -1 -1 0.04 0.0283483 0.0249661 1804 2280 -1 82 2 59 79 1850 830 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00721289 0.00692991 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 93fc1046440..83ca6e84d6c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.95 vpr 65.89 MiB -1 -1 0.73 26760 5 0.17 -1 -1 36900 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67476 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.04 153 500 90 382 28 65.9 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000660248 0.000574242 0.010203 0.00905969 -1 -1 -1 -1 6 103 13 646728 646728 -1 -1 0.12 0.059948 0.0525698 1456 2040 -1 101 16 136 266 9131 3659 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0191372 0.0164753 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.99 vpr 66.10 MiB -1 -1 0.79 27276 5 0.17 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67688 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 148 466 75 365 26 66.1 MiB 0.01 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000394392 0.000346251 0.00742774 0.00666175 -1 -1 -1 -1 8 100 16 646728 646728 -1 -1 0.14 0.0718777 0.0632492 1456 2040 -1 101 19 134 278 9113 3613 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0163481 0.014725 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 2.10 vpr 66.14 MiB -1 -1 0.85 26896 5 0.16 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67728 10 2 181 183 1 35 24 6 6 36 clb auto 27.1 MiB 0.05 142 500 108 364 28 66.1 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000538248 0.000486042 0.00902515 0.00805903 -1 -1 -1 -1 4 86 10 646728 646728 -1 -1 0.05 0.0281105 0.0249862 1456 2040 -1 87 9 108 188 5936 2196 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153203 0.0141626 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 64.18 MiB -1 -1 0.40 23288 5 0.11 -1 -1 32972 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 169 92 28 59 5 64.2 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000222832 0.000202358 0.00189553 0.00180424 -1 -1 -1 -1 6 131 18 646728 646728 -1 -1 0.07 0.0299729 0.0258466 1456 2040 -1 122 14 118 244 8464 3501 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00939131 0.00846423 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.30 vpr 64.65 MiB -1 -1 0.40 23432 5 0.10 -1 -1 33060 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 10 2 181 183 1 36 24 6 6 36 clb auto 25.4 MiB 0.02 196 163 296 52 224 20 64.7 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000228208 0.000207579 0.00320945 0.00299815 -1 -1 -1 -1 8 116 21 646728 646728 -1 -1 0.07 0.0318341 0.0274652 1456 2040 -1 116 18 143 312 10670 4334 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0103289 0.00920865 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.40 vpr 64.28 MiB -1 -1 0.48 23288 5 0.11 -1 -1 32952 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 150 398 89 285 24 64.3 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000226121 0.000205896 0.00396848 0.00369334 -1 -1 -1 -1 6 101 8 646728 646728 -1 -1 0.05 0.0290504 0.0252608 1456 2040 -1 102 10 126 245 7156 2526 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00790433 0.00720692 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt index afb5b419a6b..f07c0f7fced 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 5.23 vpr 66.07 MiB -1 -1 0.81 27256 5 0.19 -1 -1 36672 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67656 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 1.88 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000389361 0.000337837 0.00712682 0.00635643 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.83 0.023313 0.0208517 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.46 vpr 64.65 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32960 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66200 10 2 181 183 1 36 24 6 6 36 clb auto 25.3 MiB 0.02 196 160 398 88 284 26 64.6 MiB 1.20 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.00022322 0.000202277 0.00402302 0.00372354 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.60 0.0145321 0.0130932 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index 0cf367e9bdb..6488588daa2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 61.52 MiB -1 -1 0.73 27008 5 0.16 -1 -1 36840 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63000 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.06 123 1025 767 190 68 61.5 MiB 0.03 0.00 2.0306 -84.8829 -2.0306 2.0306 0.02 0.000393487 0.000346106 0.0203419 0.0179997 -1 -1 -1 -1 24 106 9 485046 377258 28445.8 1137.83 0.08 0.0705347 0.0617863 1707 5297 -1 110 10 80 114 1470 618 1.99984 1.99984 -90.3874 -1.99984 0 0 37126.9 1485.07 0.00 0.02 0.01 -1 -1 0.00 0.0158626 0.0146013 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml stereovision3.v common 1.30 vpr 59.75 MiB -1 -1 0.41 23292 5 0.11 -1 -1 32980 -1 -1 7 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61184 10 2 181 183 1 38 19 5 5 25 clb auto 20.2 MiB 0.03 159 125 1025 754 215 56 59.8 MiB 0.02 0.00 2.0306 2.0306 -85.6043 -2.0306 2.0306 0.01 0.00022991 0.000209474 0.0111608 0.0101844 -1 -1 -1 -1 22 124 12 485046 377258 26278.6 1051.14 0.05 0.0381372 0.0332965 1659 4669 -1 117 9 73 106 1326 594 1.98035 1.98035 -88.0122 -1.98035 0 0 33449.3 1337.97 0.00 0.01 0.00 -1 -1 0.00 0.00879543 0.00815896 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 891302c2b5a..b41137fb06f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 17.21 vpr 71.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72880 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.3 MiB 0.39 10472 141533 36950 100839 3744 71.2 MiB 1.37 0.02 7.46482 -1369.01 -7.46482 7.46482 0.56 0.00521343 0.00460525 0.3928 0.329697 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.35 2.1497 1.85535 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.84 0.19 -1 -1 0.04 0.261179 0.233132 - k4_N4_90nm.xml ex5p.blif common 19.31 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68632 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.35 12004 99857 28319 69545 1993 67.0 MiB 0.94 0.02 6.86459 -313.968 -6.86459 nan 0.53 0.00337095 0.00291084 0.218826 0.187023 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 13.54 0.813128 0.698644 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.07 1.22 0.29 -1 -1 0.07 0.185657 0.165735 - k4_N4_90nm.xml s298.blif common 16.74 vpr 73.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 75068 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.1 MiB 0.44 13813 156389 45768 109723 898 73.3 MiB 1.71 0.02 12.2682 -96.384 -12.2682 12.2682 0.97 0.00611806 0.00498358 0.468986 0.387941 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 9.00 1.38473 1.15574 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.09 1.18 0.31 -1 -1 0.09 0.19019 0.169418 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml diffeq.blif common 4.77 vpr 71.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72796 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.6 MiB 0.17 24088 10407 135291 36283 95683 3325 71.1 MiB 0.54 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.20 0.00204037 0.00175241 0.138253 0.119973 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.35 0.423016 0.368466 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.30 0.08 -1 -1 0.02 0.0915204 0.0830254 +k4_N4_90nm.xml ex5p.blif common 6.43 vpr 66.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67608 8 63 1072 1135 0 892 433 22 22 484 clb auto 26.5 MiB 0.13 20089 11891 97016 28068 66779 2169 66.0 MiB 0.40 0.01 11.9965 7.14697 -323.69 -7.14697 nan 0.18 0.00132575 0.00117704 0.0896217 0.0802147 -1 -1 -1 -1 32 16897 50 891726 807012 949946. 1962.70 4.19 0.332063 0.290275 43920 162796 -1 13798 21 8357 30046 2938323 715872 6.93884 nan -322.607 -6.93884 0 0 1.22393e+06 2528.78 0.04 0.44 0.09 -1 -1 0.04 0.0723896 0.0654424 +k4_N4_90nm.xml s298.blif common 8.59 vpr 72.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 579 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73820 4 6 1942 1948 1 1135 589 27 27 729 clb auto 32.0 MiB 0.19 26761 13173 158541 45950 111660 931 72.1 MiB 0.65 0.01 27.8284 12.5893 -95.8017 -12.5893 12.5893 0.28 0.00228242 0.00194389 0.165963 0.143503 -1 -1 -1 -1 24 18368 39 1.39333e+06 1.29078e+06 1.12265e+06 1539.99 5.38 0.550834 0.474162 54650 192211 -1 15957 20 8308 43971 3554658 708435 12.1943 12.1943 -92.9601 -12.1943 0 0 1.47093e+06 2017.74 0.02 0.58 0.11 -1 -1 0.02 0.116729 0.105328 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index 639ae9a9ce5..0e878ef14f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.46 vpr 69.17 MiB -1 -1 0.83 26540 4 0.20 -1 -1 36184 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.25 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.00065953 0.000573934 0.00619824 0.00583905 -1 -1 -1 -1 399 5.32000 131 1.74667 151 217 4511 1215 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.12 0.1152 0.11141 69.2 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.32 vpr 67.17 MiB -1 -1 0.41 23076 4 0.10 -1 -1 32984 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68784 11 2 303 283 2 82 28 7 7 49 clb auto 27.4 MiB 0.11 424 278 994 204 585 205 67.2 MiB 0.02 0.00 4.1851 4.05951 0 0 3.91314 0.00 0.000345438 0.000313951 0.0112699 0.0104324 -1 -1 -1 -1 318 4.18421 118 1.55263 161 242 4599 1282 1.07788e+06 808410 219490. 4479.39 5 5100 32136 -1 4.18749 3.93845 0 0 -197.86 -1.707 0.02 -1 -1 67.2 MiB 0.07 0.0774666 0.0747377 67.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index 4db4b05c471..a7808c8d24d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.05 vpr 68.36 MiB -1 -1 0.39 22432 3 0.12 -1 -1 36928 -1 -1 65 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70000 99 130 344 474 1 215 295 12 12 144 clb auto 29.2 MiB 0.19 685 24820 3391 8404 13025 68.4 MiB 0.05 0.00 32 1772 8 5.66058e+06 4.05111e+06 305575. 2122.05 1.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.32 vpr 66.69 MiB -1 -1 0.22 18840 3 0.06 -1 -1 33104 -1 -1 65 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68288 99 130 344 474 1 215 295 12 12 144 clb auto 27.3 MiB 0.07 1546 614 23839 3086 6279 14474 66.7 MiB 0.02 0.00 38 1473 8 5.66058e+06 4.05111e+06 345440. 2398.89 0.20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt index 59b02c3fd0e..3a223b5cf9f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links - stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 104.06 vpr 1.07 GiB -1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1126272 2 32 2204 1661 1 1102 107 36 20 720 -1 EP4SGX110 955.6 MiB 4.04 6649 10733 2374 7396 963 1099.9 MiB 0.85 0.01 7.22684 -4978.81 -7.22684 7.22684 14.03 0.00387297 0.00336653 0.329346 0.282395 154 8599 14 0 0 6.94291e+06 9642.93 42.85 2.6403 2.32523 176404 1494154 -1 8630 10 2443 4554 1083511 308854 7.50808 7.50808 -5329.84 -7.50808 0 0 8.91809e+06 12386.2 1.07 0.65 2.72 -1 -1 1.07 0.27806 0.251316 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 +arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links +stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 40.63 vpr 1.07 GiB -1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1124608 2 32 2204 1661 1 1104 108 36 20 720 -1 EP4SGX110 954.6 MiB 2.03 15097 6710 12958 2982 8805 1171 1098.2 MiB 0.42 0.01 8.01944 7.31997 -4968.85 -7.31997 7.31997 5.35 0.00271249 0.00239307 0.162656 0.143711 154 8889 12 0 0 6.94291e+06 9642.93 8.24 0.999967 0.885649 176404 1494154 -1 8829 14 2492 4758 998347 275320 7.64666 7.64666 -5202.88 -7.64666 0 0 8.91809e+06 12386.2 0.44 0.31 1.33 -1 -1 0.44 0.140458 0.130997 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index b67a185d189..08e549a0cfe 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.76 vpr 66.03 MiB -1 -1 0.86 26892 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00186164 0.0017947 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.10 vpr 64.27 MiB -1 -1 0.42 23432 5 0.11 -1 -1 33216 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00102325 0.000991048 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 153be88f8d6..ced45279053 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.90 vpr 66.02 MiB -1 -1 0.83 26896 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000402396 0.000353615 0.00726063 0.00647248 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00909673 0.00824277 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.08 vpr 64.28 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32960 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 151 500 122 353 25 64.3 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000220907 0.000200935 0.00457561 0.00422076 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00559149 0.00520404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt index 6e6ab2e273c..0495632427e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 0.60 vpr 60.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62244 11 11 59 70 0 48 26 4 4 16 clb auto 22.1 MiB 0.03 179 862 260 602 0 60.8 MiB 0.02 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000312912 0.000279273 0.00803541 0.00727675 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.11 0.0569851 0.0502764 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.01 0.00 -1 -1 0.00 0.0102047 0.00933765 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.06 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23944 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.3 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml mult_5x6.blif common 0.38 vpr 59.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60668 11 11 59 70 0 48 26 4 4 16 clb auto 20.2 MiB 0.02 205 178 672 211 461 0 59.2 MiB 0.01 0.00 2.48509 2.46139 -19.889 -2.46139 nan 0.01 0.000116739 0.000106346 0.00301039 0.00279891 -1 -1 -1 -1 30 215 23 215576 215576 18771.3 1173.21 0.04 0.0201992 0.0174425 1016 3020 -1 186 15 222 505 8959 4790 2.75695 nan -23.0631 -2.75695 0 0 22855.5 1428.47 0.00 0.01 0.00 -1 -1 0.00 0.00609754 0.00553999 +k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.05 vpr 20.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 21248 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt index 12efb65ec8c..a5132decd03 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 2.54 vpr 77.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78852 33 32 161 193 1 65 97 34 34 1156 -1 32x32 21.4 MiB 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00178122 0.0017245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 1.00 vpr 74.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76400 33 32 161 193 1 65 97 34 34 1156 -1 32x32 18.9 MiB 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000953076 0.000926056 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt index 87ace76c192..675c9ec8c27 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.20 vpr 64.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66472 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.9 MiB 0.00 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 4.3045e-05 2.9263e-05 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common 0.16 vpr 62.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64408 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 24 21 30 9 19 2 62.9 MiB 0.00 0.00 0.739166 0.646042 -3.51892 -0.646042 0.571 0.00 2.3236e-05 1.6158e-05 0.000950924 0.000910209 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000950924 0.000910209 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt index 8361bf1bfe6..63ec0c82585 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.75 vpr 978.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001760 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.46 364 858 131 680 47 978.3 MiB 0.06 0.00 6.37129 -69.6808 -6.37129 6.37129 1.81 0.000551403 0.000481676 0.0153225 0.013705 -1 -1 -1 -1 22 874 22 0 0 110609. 1256.92 1.54 0.247666 0.215864 11258 24748 -1 728 16 428 1746 95453 49745 6.73416 6.73416 -75.7525 -6.73416 0 0 134428. 1527.59 0.01 0.08 0.07 -1 -1 0.01 0.0332471 0.0304495 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 37.57 vpr 978.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001868 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.66 371 950 121 778 51 978.4 MiB 0.07 0.00 6.34606 -69.4373 -6.34606 6.34606 2.32 0.000744808 0.000651566 0.0166971 0.0148799 -1 -1 -1 -1 32 654 12 0 0 153433. 1743.56 0.90 0.149648 0.129506 11830 34246 -1 601 15 249 896 54680 24076 6.61838 6.61838 -74.0379 -6.61838 0 0 205860. 2339.32 0.01 0.07 0.09 -1 -1 0.01 0.0346715 0.0320467 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 34.09 vpr 978.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001652 10 10 168 178 1 68 30 11 8 88 io auto 955.4 MiB 0.44 376 582 74 468 40 978.2 MiB 0.07 0.00 6.26487 -68.7007 -6.26487 6.26487 2.74 0.000593656 0.000520243 0.0126605 0.0115382 -1 -1 -1 -1 28 858 45 0 0 134428. 1527.59 1.21 0.206409 0.180557 11590 29630 -1 614 14 305 1283 69506 33247 6.72367 6.72367 -73.5822 -6.72367 0 0 173354. 1969.93 0.01 0.08 0.06 -1 -1 0.01 0.0327372 0.0302784 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 41.01 vpr 978.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002252 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.60 352 582 88 454 40 978.8 MiB 0.05 0.00 6.37106 -69.2764 -6.37106 6.37106 3.17 0.000446168 0.000388088 0.0115458 0.0104844 -1 -1 -1 -1 22 778 22 0 0 110609. 1256.92 1.84 0.253098 0.220545 11258 24748 -1 690 15 386 1546 88347 46120 6.75259 6.75259 -75.6874 -6.75259 0 0 134428. 1527.59 0.01 0.08 0.06 -1 -1 0.01 0.0310233 0.0286671 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 22.92 vpr 980.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003552 10 10 168 178 1 65 30 11 8 88 io auto 953.5 MiB 0.34 461 363 812 65 683 64 980.0 MiB 0.06 0.00 6.74915 6.53925 -69.3815 -6.53925 6.53925 1.02 0.000306729 0.00027993 0.00872325 0.00811554 -1 -1 -1 -1 18 1016 35 0 0 88979.3 1011.13 0.42 0.0610226 0.0537175 11100 22242 -1 903 21 541 2228 132955 67625 6.88394 6.88394 -78.1788 -6.88394 0 0 114778. 1304.29 0.00 0.06 0.03 -1 -1 0.00 0.0200797 0.0183694 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 22.00 vpr 979.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002788 10 10 168 178 1 65 30 11 8 88 io auto 952.8 MiB 0.32 461 360 766 54 639 73 979.3 MiB 0.06 0.00 6.74915 6.50519 -69.5865 -6.50519 6.50519 0.99 0.000304647 0.000272539 0.00848216 0.00790543 -1 -1 -1 -1 22 737 19 0 0 110609. 1256.92 0.26 0.0516738 0.0459714 11258 24748 -1 741 17 354 1302 73546 39254 6.97435 6.97435 -75.9089 -6.97435 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.017292 0.0159531 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 22.43 vpr 979.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002984 10 10 168 178 1 65 30 11 8 88 io auto 953.0 MiB 0.32 461 374 858 76 722 60 979.5 MiB 0.05 0.00 6.74915 6.37842 -69.0199 -6.37842 6.37842 1.38 0.000304178 0.000276269 0.00897291 0.0083292 -1 -1 -1 -1 18 1028 44 0 0 88979.3 1011.13 0.39 0.0630047 0.0554817 11100 22242 -1 860 17 503 1822 111191 56265 7.04132 7.04132 -78.8721 -7.04132 0 0 114778. 1304.29 0.00 0.06 0.03 -1 -1 0.00 0.0175163 0.0161202 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 22.53 vpr 979.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002948 10 10 168 178 1 65 30 11 8 88 io auto 953.6 MiB 0.32 461 351 812 66 693 53 979.4 MiB 0.06 0.00 6.74915 6.37842 -69.076 -6.37842 6.37842 1.41 0.0006279 0.000600407 0.0105144 0.00982327 -1 -1 -1 -1 18 886 33 0 0 88979.3 1011.13 0.35 0.0596658 0.0528181 11100 22242 -1 779 16 420 1590 93739 47077 6.94344 6.94344 -77.4262 -6.94344 0 0 114778. 1304.29 0.00 0.05 0.03 -1 -1 0.00 0.0171118 0.0158021 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index 10a6cf257aa..3ed02e126a6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 36.65 vpr 978.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002024 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.33 0.000579422 0.00050489 0.0121495 0.01103 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.00 0.197686 0.174013 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.07 0.08 -1 -1 0.01 0.0316604 0.0292377 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 28.63 vpr 978.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001964 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.43 356 628 86 501 41 978.5 MiB 0.06 0.00 6.32784 -69.1369 -6.32784 6.32784 1.45 0.000300815 0.000260189 0.00775385 0.00704586 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 0.78 0.12183 0.106239 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.07 0.04 -1 -1 0.01 0.0278034 0.0259211 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 22.41 vpr 980.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003552 10 10 168 178 1 65 30 11 8 88 io auto 953.5 MiB 0.32 530 354 766 109 603 54 980.0 MiB 0.05 0.00 6.8164 6.25965 -69.3407 -6.25965 6.25965 0.97 0.000305911 0.00027714 0.00819653 0.00761311 -1 -1 -1 -1 20 842 24 0 0 100248. 1139.18 0.28 0.0523692 0.0463301 11180 23751 -1 740 16 428 1793 101987 51614 6.72979 6.72979 -75.9114 -6.72979 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0176516 0.0163051 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 22.21 vpr 980.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003548 10 10 168 178 1 65 30 11 8 88 io auto 953.5 MiB 0.33 530 359 766 97 619 50 980.0 MiB 0.05 0.00 6.8164 6.26487 -69.3105 -6.26487 6.26487 0.99 0.000310412 0.000282703 0.00828685 0.00771023 -1 -1 -1 -1 22 829 20 0 0 110609. 1256.92 0.27 0.0520543 0.046207 11258 24748 -1 771 17 378 1439 87505 45574 6.83905 6.83905 -76.8941 -6.83905 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.0186146 0.0171176 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt index bee9bf5e15f..6f6380c9b82 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 3.66 vpr 76.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78656 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.7 MiB 2.32 6246 12245 2336 8854 1055 76.8 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.22 0.00367856 0.00299064 0.169598 0.144286 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.174334 0.148491 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.50 vpr 76.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78400 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.21 6248 12409 2316 9051 1042 76.6 MiB 0.36 0.01 5.00015 -217.921 -5.00015 nan 0.26 0.00350625 0.00296092 0.150187 0.130251 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.154752 0.13448 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 4.86 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78576 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.5 MiB 1.80 6557 16051 3559 11939 553 76.7 MiB 0.46 0.01 5.39652 -231.823 -5.39652 nan 1.19 0.00333577 0.00278218 0.186781 0.161087 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.19137 0.165152 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.27 vpr 76.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78592 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.48 6642 53385 10847 39555 2983 76.8 MiB 0.94 0.01 5.30857 -236.309 -5.30857 nan 1.66 0.00199214 0.00171649 0.207463 0.177518 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.212761 0.182102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml ex5p.blif common_--place_effort_scaling_circuit 1.72 vpr 75.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77356 8 63 1072 1135 0 611 133 11 11 121 clb auto 35.8 MiB 1.13 7518 6082 8947 1533 6815 599 75.5 MiB 0.13 0.00 5.94011 5.07653 -213.869 -5.07653 nan 0.08 0.00137467 0.00121391 0.0556444 0.0510707 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0578783 0.0530616 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 1.74 vpr 75.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76912 8 63 1072 1135 0 611 133 11 11 121 clb auto 35.4 MiB 1.14 7518 6142 9355 1631 7067 657 75.1 MiB 0.14 0.00 5.94011 4.97625 -208.188 -4.97625 nan 0.08 0.00136238 0.00119962 0.0598913 0.054887 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0620728 0.0568398 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 3.05 vpr 74.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76600 8 63 1072 1135 0 611 133 27 27 729 -1 auto 34.7 MiB 1.17 17047 6704 22507 6724 13850 1933 74.8 MiB 0.27 0.00 9.03576 5.62812 -248.555 -5.62812 nan 0.62 0.0013434 0.00117795 0.109585 0.098544 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.11189 0.100604 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 3.16 vpr 75.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77312 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.8 MiB 1.12 17047 6681 64488 18508 41026 4954 75.5 MiB 0.50 0.01 9.03576 5.51074 -242.103 -5.51074 nan 0.60 0.00133767 0.00117811 0.100107 0.0904562 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.102225 0.0923579 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt index 344063856f9..395177b0d33 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.31 vpr 66.14 MiB -1 -1 0.81 26892 5 0.20 -1 -1 36924 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.1 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000410176 0.000357432 0.00947888 0.00721552 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.10 0.0626682 0.052856 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0168161 0.0151469 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.34 vpr 63.99 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65528 10 2 181 183 1 36 24 6 6 36 clb auto 24.5 MiB 0.02 196 151 500 122 353 25 64.0 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000235085 0.000214701 0.00476972 0.00440908 -1 -1 -1 -1 12 169 17 646728 646728 19965.4 554.594 0.06 0.03334 0.0288534 1696 3924 -1 165 16 218 500 9678 3037 2.12594 2.12594 -92.801 -2.12594 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.0100241 0.00897853 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt index a4fadd34b2c..5843e7559a3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.35 vpr 62.50 MiB -1 -1 -1 -1 0 0.02 -1 -1 33168 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64000 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2148e-05 6.319e-06 7.9011e-05 5.1305e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00149016 0.00141935 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.45 vpr 62.59 MiB -1 -1 -1 -1 0 0.03 -1 -1 33140 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 0 3 0 0 3 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2883e-05 7.145e-06 8.5494e-05 5.1608e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00156787 0.00149125 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.37 vpr 62.62 MiB -1 -1 -1 -1 0 0.02 -1 -1 33248 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64128 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4288e-05 8.001e-06 8.7045e-05 5.7557e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.0015153 0.00144219 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.39 vpr 62.59 MiB -1 -1 -1 -1 0 0.02 -1 -1 33208 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64096 6 1 1 8 0 1 8 3 3 9 -1 auto 24.2 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2682e-05 6.827e-06 7.4747e-05 4.546e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00148015 0.0014067 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.37 vpr 62.59 MiB -1 -1 -1 -1 1 0.02 -1 -1 32904 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 2 1 3 4 0 3 4 3 3 9 -1 auto 24.2 MiB 0.00 9 9 5 0 4 62.6 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.5556e-05 1.071e-05 9.7598e-05 7.1292e-05 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.00 0.00159844 0.00147185 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.47 vpr 62.71 MiB -1 -1 -1 -1 2 0.05 -1 -1 34804 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 5 1 7 8 0 7 7 3 3 9 -1 auto 24.3 MiB 0.00 20 18 12 0 6 62.7 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4161e-05 1.7898e-05 0.000147057 0.000117193 -1 -1 -1 -1 -1 8 6 3900 3900 7855.82 872.868 0.00 0.00183362 0.0017084 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.53 vpr 62.71 MiB -1 -1 -1 -1 2 0.06 -1 -1 35320 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 5 1 7 8 0 7 7 3 3 9 -1 auto 24.3 MiB 0.00 20 18 13 0 5 62.7 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4929e-05 1.9146e-05 0.000149053 0.000119002 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.00207292 0.001883 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.42 vpr 62.59 MiB -1 -1 -1 -1 1 0.03 -1 -1 33204 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 3 1 5 6 1 4 5 3 3 9 -1 auto 24.2 MiB 0.00 9 12 9 0 3 62.6 MiB 0.00 0.00 0.274843 -0.536407 -0.274843 0.274843 0.00 2.0225e-05 1.4435e-05 0.000138329 0.000106209 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.00194055 0.00179435 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.55 vpr 62.71 MiB -1 -1 -1 -1 1 0.05 -1 -1 35156 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64220 4 1 4 6 0 4 6 3 3 9 -1 auto 24.2 MiB 0.00 12 15 11 0 4 62.7 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.8428e-05 1.2806e-05 0.000110516 8.1976e-05 -1 -1 -1 -1 -1 7 16 3900 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0.00 0.70303 0.70303 -0.70303 -0.70303 nan 0.00 1.3014e-05 9.636e-06 9.8067e-05 7.8745e-05 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.00117211 0.00105469 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.32 vpr 60.80 MiB -1 -1 -1 -1 1 0.02 -1 -1 29988 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62260 3 1 5 6 1 4 5 3 3 9 -1 auto 22.5 MiB 0.00 9 9 12 9 0 3 60.8 MiB 0.00 0.00 0.274843 0.274843 -0.536407 -0.274843 0.274843 0.00 1.0936e-05 7.525e-06 8.3706e-05 6.3702e-05 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.0011052 0.00100775 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.41 vpr 60.80 MiB -1 -1 -1 -1 1 0.03 -1 -1 31816 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62264 4 1 4 6 0 4 6 3 3 9 -1 auto 22.2 MiB 0.00 12 12 15 11 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -0.443777 -0.443777 nan 0.00 1.0318e-05 6.84e-06 7.4714e-05 5.4959e-05 -1 -1 -1 -1 -1 7 16 3900 3900 7855.82 872.868 0.00 0.00114292 0.00101594 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.40 vpr 60.80 MiB -1 -1 -1 -1 1 0.03 -1 -1 31872 -1 -1 1 4 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62264 4 4 8 12 0 8 9 3 3 9 -1 auto 22.5 MiB 0.00 25 25 27 23 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -1.77511 -0.443777 nan 0.00 1.7936e-05 1.41e-05 0.000134733 0.000114066 -1 -1 -1 -1 -1 30 13 3900 3900 7855.82 872.868 0.00 0.00140331 0.00125307 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.42 vpr 60.60 MiB -1 -1 -1 -1 3 0.04 -1 -1 32344 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62056 6 6 28 34 0 28 15 5 5 25 clb auto 21.8 MiB 0.00 113 107 51 16 35 0 60.6 MiB 0.00 0.00 1.19848 1.19848 -5.43061 -1.19848 nan 0.00 4.9605e-05 4.359e-05 0.000391617 0.00036093 -1 -1 -1 -1 -1 190 16 23400 11700 33739.5 1349.58 0.01 0.00302204 0.00268104 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.43 vpr 60.45 MiB -1 -1 -1 -1 4 0.04 -1 -1 32088 -1 -1 5 7 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61904 7 8 39 47 0 39 20 5 5 25 clb auto 22.1 MiB 0.01 182 166 236 59 163 14 60.5 MiB 0.00 0.00 1.48602 1.46514 -7.47508 -1.46514 nan 0.00 6.7634e-05 5.9467e-05 0.000923947 0.000839342 -1 -1 -1 -1 -1 326 19 23400 19500 33739.5 1349.58 0.02 0.0046745 0.00410086 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.47 vpr 60.96 MiB -1 -1 -1 -1 8 0.05 -1 -1 32092 -1 -1 6 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62428 8 8 51 59 0 51 22 5 5 25 clb auto 22.5 MiB 0.01 241 211 352 90 254 8 61.0 MiB 0.00 0.00 2.56944 2.55689 -12.2592 -2.55689 nan 0.00 8.5471e-05 7.753e-05 0.00148029 0.00135617 -1 -1 -1 -1 -1 432 21 23400 23400 33739.5 1349.58 0.02 0.00641372 0.00564603 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.54 vpr 61.32 MiB -1 -1 -1 -1 7 0.06 -1 -1 32828 -1 -1 11 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62792 10 10 95 105 0 95 31 6 6 36 clb auto 22.2 MiB 0.01 521 440 511 77 404 30 61.3 MiB 0.01 0.00 2.69967 2.57044 -18.1695 -2.57044 nan 0.00 0.000150117 0.00013686 0.0022957 0.00211495 -1 -1 -1 -1 -1 938 24 165600 42900 61410.5 1705.85 0.05 0.010575 0.00932341 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 0.56 vpr 61.28 MiB -1 -1 -1 -1 8 0.07 -1 -1 32924 -1 -1 11 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62752 11 11 94 105 0 94 33 6 6 36 clb auto 22.2 MiB 0.01 523 447 709 77 581 51 61.3 MiB 0.01 0.00 2.83651 2.78731 -20.9698 -2.78731 nan 0.00 0.000145948 0.000133465 0.00280111 0.00257676 -1 -1 -1 -1 -1 978 22 165600 42900 61410.5 1705.85 0.05 0.0108181 0.0095662 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.40 vpr 60.80 MiB -1 -1 -1 -1 1 0.03 -1 -1 31076 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62264 3 2 5 7 0 5 6 3 3 9 -1 auto 22.5 MiB 0.00 15 15 15 11 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -0.887553 -0.443777 nan 0.00 1.2426e-05 8.986e-06 0.000101661 8.0396e-05 -1 -1 -1 -1 -1 12 16 3900 3900 7855.82 872.868 0.00 0.00124405 0.00110619 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.40 vpr 60.58 MiB -1 -1 -1 -1 2 0.03 -1 -1 31864 -1 -1 1 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62036 5 3 9 12 0 9 9 3 3 9 -1 auto 22.1 MiB 0.00 26 26 27 24 0 3 60.6 MiB 0.00 0.00 0.70303 0.70303 -1.84984 -0.70303 nan 0.00 1.6846e-05 1.3184e-05 0.000128485 0.000107138 -1 -1 -1 -1 -1 19 17 3900 3900 7855.82 872.868 0.00 0.00145588 0.00128914 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.38 vpr 61.18 MiB -1 -1 -1 -1 3 0.03 -1 -1 31860 -1 -1 1 7 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62644 7 4 13 17 0 13 12 3 3 9 -1 auto 22.6 MiB 0.00 37 37 38 34 0 4 61.2 MiB 0.00 0.00 0.962283 0.962283 -3.07137 -0.962283 nan 0.00 2.2173e-05 1.8007e-05 0.000170305 0.000147797 -1 -1 -1 -1 -1 39 18 3900 3900 7855.82 872.868 0.00 0.00176748 0.00156548 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.41 vpr 60.81 MiB -1 -1 -1 -1 4 0.04 -1 -1 31864 -1 -1 1 9 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62268 9 5 17 22 0 17 15 3 3 9 -1 auto 22.2 MiB 0.00 48 48 51 43 0 8 60.8 MiB 0.00 0.00 1.22154 1.22154 -4.55216 -1.22154 nan 0.00 2.7739e-05 2.3216e-05 0.000212345 0.000188425 -1 -1 -1 -1 -1 65 18 3900 3900 7855.82 872.868 0.00 0.0020451 0.00180274 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.40 vpr 60.60 MiB -1 -1 -1 -1 4 0.04 -1 -1 31480 -1 -1 2 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62052 11 6 24 30 0 24 19 4 4 16 clb auto 21.9 MiB 0.00 96 81 219 61 139 19 60.6 MiB 0.00 0.00 1.37337 1.3375 -6.59285 -1.3375 nan 0.00 3.6283e-05 3.0702e-05 0.000516197 0.000448261 -1 -1 -1 -1 -1 131 14 7800 7800 17482.0 1092.63 0.01 0.00253984 0.00224901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index def1a137d22..5a0e83cd6e5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.05 vpr 68.39 MiB -1 -1 0.40 21908 3 0.11 -1 -1 37048 -1 54888 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70028 99 130 344 474 1 227 298 12 12 144 clb auto 29.0 MiB 0.23 673 63978 19550 30341 14087 68.4 MiB 0.26 0.00 1.86472 -118.834 -1.86472 1.86472 0.28 0.000886976 0.000801272 0.0813306 0.0745016 -1 -1 -1 -1 38 1393 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.68 0.238994 0.21577 12522 62564 -1 1106 10 397 647 21454 6807 1.90702 1.90702 -131.595 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.03 0.05 0.11 -1 -1 0.03 0.0347348 0.0326652 0.01152 0.2117 0.0667 0.7216 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.51 vpr 71.63 MiB -1 -1 0.57 27156 15 0.44 -1 -1 38000 -1 56764 39 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73348 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 32.3 MiB 0.47 5553 86322 27524 51152 7646 71.6 MiB 0.85 0.01 20.9417 -1607.93 -20.9417 20.9417 0.48 0.003704 0.00340296 0.38455 0.354826 -1 -1 -1 -1 50 10993 26 1.21132e+07 4.08187e+06 780512. 3048.87 3.85 1.2672 1.17071 25484 153448 -1 9617 17 3054 6060 825747 253645 22.1678 22.1678 -1734.75 -22.1678 0 0 1.00276e+06 3917.05 0.06 0.43 0.25 -1 -1 0.06 0.181388 0.170418 0.007894 0.3513 0.0164 0.6323 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.12 vpr 66.85 MiB -1 -1 0.23 18444 3 0.06 -1 -1 32728 -1 52608 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68452 99 130 344 474 1 228 298 12 12 144 clb auto 27.4 MiB 0.10 1675 704 66963 20370 32791 13802 66.8 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000588264 0.00055103 0.0412906 0.0386681 -1 -1 -1 -1 40 1447 16 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.15889 0.145741 12666 64609 -1 1220 8 417 630 29292 10027 2.02932 2.02932 -139.109 -2.02932 -0.436676 -0.298787 419432. 2912.72 0.01 0.02 0.04 -1 -1 0.01 0.0158392 0.0149265 0.01097 0.2173 0.06774 0.7149 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 6.02 vpr 70.39 MiB -1 -1 0.31 23676 15 0.29 -1 -1 33804 -1 54344 39 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72084 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 30.5 MiB 0.18 9745 5422 92394 29404 54877 8113 70.4 MiB 0.35 0.00 23.0626 21.1445 -1627.16 -21.1445 21.1445 0.18 0.00152927 0.00141434 0.152545 0.142035 -1 -1 -1 -1 52 12275 40 1.21132e+07 4.08187e+06 805949. 3148.24 2.13 0.550493 0.509323 25992 162577 -1 9489 19 3386 7023 823162 268347 21.9567 21.9567 -1721.84 -21.9567 0 0 1.06067e+06 4143.25 0.03 0.18 0.10 -1 -1 0.03 0.0804895 0.0759977 0.008009 0.3554 0.01727 0.6273 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index 82620e51799..9639f26e4f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.71 vpr 65.87 MiB -1 -1 0.78 26896 5 0.18 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67448 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00039706 0.000346093 0.00713489 0.00637234 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.03 -1 -1 65.9 MiB 0.02 0.0245431 0.0219785 65.9 MiB -1 0.00 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.90 vpr 68.91 MiB -1 -1 0.73 26796 4 0.18 -1 -1 36100 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70560 11 2 303 283 2 78 28 7 7 49 clb auto 29.2 MiB 0.18 285 784 175 539 70 68.9 MiB 0.03 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000657098 0.000563918 0.0210266 0.0187872 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 68.9 MiB 0.03 0.0456598 0.0418503 68.9 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.15 vpr 64.27 MiB -1 -1 0.46 23432 5 0.10 -1 -1 32588 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 25.1 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000230059 0.000208481 0.00401393 0.00371679 -1 -1 -1 -1 136 4.12121 61 1.84848 149 320 10235 1961 646728 646728 138825. 3856.24 17 3164 19284 -1 2.10277 2.10277 -91.6521 -2.10277 0 0 0.01 -1 -1 64.3 MiB 0.01 0.0145441 0.0130986 64.3 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.26 vpr 67.26 MiB -1 -1 0.40 23072 4 0.10 -1 -1 32604 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68872 11 2 303 283 2 85 28 7 7 49 clb auto 27.9 MiB 0.11 462 289 1204 263 848 93 67.3 MiB 0.02 0.00 2.20327 2.04719 -154.888 -2.04719 1.90466 0.00 0.000392594 0.000350448 0.0146209 0.0131383 -1 -1 -1 -1 314 3.97468 124 1.56962 130 211 4049 1168 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.02047 1.86775 -152.224 -2.02047 0 0 0.02 -1 -1 67.3 MiB 0.01 0.0286825 0.0263238 67.3 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index b3939ae8bad..5f4f5529d11 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 40.08 vpr 84.36 MiB -1 -1 7.36 54308 5 2.17 -1 -1 42700 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86380 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 2.10 10543 233626 82676 126206 24744 84.4 MiB 2.58 0.04 4.85425 -2733.64 -4.85425 4.85425 0.83 0.0094896 0.008538 0.955143 0.814553 -1 -1 -1 -1 76 20844 34 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 19.63 4.86995 4.26704 52074 423490 -1 18742 17 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.70 0.57 -1 -1 0.11 0.429237 0.387696 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 14.68 vpr 84.02 MiB -1 -1 3.34 52052 5 1.33 -1 -1 38940 -1 -1 152 193 5 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86040 193 205 2718 2652 1 1315 555 20 20 400 memory auto 43.9 MiB 0.95 22187 10660 223995 81694 118286 24015 84.0 MiB 1.00 0.01 7.82756 5.10197 -2914.56 -5.10197 5.10197 0.30 0.00326192 0.00293721 0.360015 0.322066 -1 -1 -1 -1 76 20582 44 2.07112e+07 1.09319e+07 2.02110e+06 5052.76 5.14 1.27624 1.14447 52074 423490 -1 19292 17 5251 14325 1187541 264668 5.21056 5.21056 -3121.27 -5.21056 -9.98113 -0.359474 2.51807e+06 6295.18 0.07 0.32 0.24 -1 -1 0.07 0.190256 0.17845 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt index b2a77a6f0e1..ecbe1740334 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.71 vpr 71.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73312 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.45 4992 14048 2664 10357 1027 71.6 MiB 0.29 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00333844 0.00278407 0.128199 0.109732 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.21 -1 -1 71.6 MiB 0.30 0.276888 0.244984 71.6 MiB -1 0.05 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 1.81 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.47 4992 14048 2664 10357 1027 71.5 MiB 0.31 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00291779 0.00252096 0.133598 0.1169 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.20 -1 -1 71.5 MiB 0.31 0.289515 0.258703 71.5 MiB -1 0.06 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 0.93 vpr 69.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71608 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7035 5048 13708 2494 10216 998 69.9 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.0012128 0.0010607 0.0506511 0.0454061 -1 -1 -1 -1 6826 15.1353 1836 4.07095 3768 15421 585680 92261 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17836 nan -185.935 -4.17836 0 0 0.08 -1 -1 69.9 MiB 0.17 0.129356 0.117175 69.9 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 0.89 vpr 69.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70996 8 63 748 811 0 451 161 14 14 196 clb auto 30.3 MiB 0.22 7035 5048 13708 2494 10216 998 69.3 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.00121456 0.00105201 0.0492265 0.0440361 -1 -1 -1 -1 6906 15.3126 1853 4.10865 3897 16323 609528 97595 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17947 nan -185.454 -4.17947 0 0 0.08 -1 -1 69.3 MiB 0.16 0.125412 0.113776 69.3 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index f0bed076f05..4f76e3d108b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.89 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73344 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.50 4993 17086 3593 12286 1207 71.6 MiB 0.32 0.01 3.65588 -160.421 -3.65588 nan 0.04 0.00302942 0.00252731 0.141328 0.121812 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.15 -1 -1 71.6 MiB 0.43 0.306494 0.271472 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.75 vpr 71.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73176 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.38 4933 15350 2970 11325 1055 71.5 MiB 0.31 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00317678 0.00277359 0.137596 0.118868 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.5 MiB 0.37 0.319312 0.282053 71.5 MiB -1 0.04 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.41 vpr 71.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73128 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.28 0.01 3.77945 -168.167 -3.77945 nan 0.06 0.00517556 0.0043803 0.123856 0.107999 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.14 -1 -1 71.4 MiB 0.56 0.3503 0.312891 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.58 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.7 MiB 0.45 5048 17520 3917 12196 1407 71.5 MiB 0.35 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00283082 0.00243406 0.152931 0.13159 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.10 -1 -1 71.5 MiB 0.60 0.372321 0.328664 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 0.98 vpr 69.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71212 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.23 7019 5149 19389 4557 13188 1644 69.5 MiB 0.16 0.00 5.27085 3.74489 -168.03 -3.74489 nan 0.02 0.00125283 0.0010941 0.0674999 0.0604792 -1 -1 -1 -1 7151 15.8559 1918 4.25277 4270 17535 1282134 224677 9.20055e+06 4.85046e+06 701736. 3580.29 23 16332 105598 -1 4.37015 nan -196.64 -4.37015 0 0 0.06 -1 -1 69.5 MiB 0.22 0.147101 0.13314 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 0.92 vpr 69.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71024 8 63 748 811 0 451 161 14 14 196 clb auto 29.9 MiB 0.24 7019 5029 15019 2779 11014 1226 69.4 MiB 0.13 0.00 5.64572 4.2713 -188.25 -4.2713 nan 0.00 0.00120263 0.00103977 0.0546017 0.0489804 -1 -1 -1 -1 7035 15.5987 1894 4.19956 3783 16134 598321 102284 9.20055e+06 4.85046e+06 701736. 3580.29 20 16332 105598 -1 4.48059 nan -193.333 -4.48059 0 0 0.06 -1 -1 69.4 MiB 0.16 0.131335 0.119172 69.4 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 1.67 vpr 69.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70840 8 63 748 811 0 451 161 14 14 196 clb auto 30.1 MiB 0.23 7019 5066 19826 4740 13454 1632 69.2 MiB 0.16 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00120109 0.00105045 0.0672362 0.0599274 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 69.2 MiB 0.22 0.144275 0.130119 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.74 vpr 69.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71212 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.24 7019 5066 19826 4740 13454 1632 69.5 MiB 0.17 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00118757 0.00104417 0.0682317 0.0610542 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 69.5 MiB 0.22 0.149143 0.134994 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt index 2e384423539..96895dbdd9f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.81 vpr 71.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72996 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.46 5066 14916 2828 10927 1161 71.3 MiB 0.27 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00329282 0.00274638 0.115858 0.0987687 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.40 0.297064 0.262289 71.3 MiB -1 0.03 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 1.90 vpr 71.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72932 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.47 5066 14916 2828 10927 1161 71.2 MiB 0.34 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00295504 0.00249967 0.137157 0.115922 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.16 -1 -1 71.2 MiB 0.41 0.334676 0.294068 71.2 MiB -1 0.04 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 0.93 vpr 69.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71216 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.23 7035 5098 13271 2309 10001 961 69.5 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00119761 0.00104527 0.0488071 0.0438389 -1 -1 -1 -1 7155 15.8647 1916 4.24834 4312 18456 674497 110334 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.5 MiB 0.17 0.127664 0.116164 69.5 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 0.92 vpr 69.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71600 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.23 7035 5098 13271 2309 10001 961 69.9 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00119935 0.00104077 0.0477462 0.0428434 -1 -1 -1 -1 7141 15.8337 1913 4.24168 4366 18775 685171 111801 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.9 MiB 0.18 0.127342 0.115562 69.9 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt index dda3cef9fb9..30111b74667 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.94 vpr 67.28 MiB -1 -1 0.14 21160 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68892 6 1 16 17 2 10 9 17 17 289 -1 auto 28.8 MiB 0.03 30 162 45 109 8 67.3 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.60 4.7388e-05 3.614e-05 0.00109694 0.000865862 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.37 0.00363015 0.00323679 24098 82050 -1 103 2 14 14 8045 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.04 0.16 0.10 -1 -1 0.04 0.00205247 0.00194107 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.71 vpr 67.09 MiB -1 -1 0.11 20776 1 0.02 -1 -1 33508 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.29 2.6273e-05 2.0281e-05 0.000147698 0.000116195 -1 -1 -1 -1 20 62 1 6.63067e+06 53894 227243. 1344.63 0.21 0.00195838 0.00183532 13251 44387 -1 55 1 4 4 2060 1116 1.77078 1.77078 -1.77078 -1.77078 -0.365681 -0.365681 294987. 1745.49 0.02 0.09 0.06 -1 -1 0.02 0.00158307 0.00153637 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.80 vpr 67.12 MiB -1 -1 0.13 21160 1 0.05 -1 -1 35572 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68728 6 1 16 17 2 10 9 17 17 289 -1 auto 28.7 MiB 0.01 30 162 45 109 8 67.1 MiB 0.00 0.00 1.43377 -4.13192 -1.43377 0.805 0.60 4.8373e-05 3.7154e-05 0.00108209 0.000859607 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.36 0.00311589 0.00272737 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.04 0.17 0.12 -1 -1 0.04 0.00220953 0.00209751 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.66 vpr 67.09 MiB -1 -1 0.12 20904 1 0.02 -1 -1 33532 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.23 2.2312e-05 1.624e-05 0.000140559 0.000108632 -1 -1 -1 -1 20 58 1 6.63067e+06 53894 235789. 1395.20 0.22 0.00172037 0.00159801 13251 46155 -1 59 1 4 4 2248 1144 1.92085 1.92085 -1.92085 -1.92085 -0.365681 -0.365681 303533. 1796.05 0.02 0.10 0.07 -1 -1 0.02 0.00161749 0.00156481 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.79 vpr 67.18 MiB -1 -1 0.14 20780 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68788 6 1 16 17 2 10 9 17 17 289 -1 auto 28.9 MiB 0.02 30 162 45 109 8 67.2 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.52 4.3023e-05 3.3348e-05 0.0010817 0.000870707 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.27 0.00353152 0.00316566 24098 82150 -1 581 2 13 13 6290 3262 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.04 0.17 0.11 -1 -1 0.04 0.00234323 0.00223031 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.63 vpr 67.17 MiB -1 -1 0.08 21164 1 0.02 -1 -1 33664 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68780 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.2 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.27 1.6733e-05 1.1353e-05 0.00024751 0.000102039 -1 -1 -1 -1 20 193 1 6.63067e+06 53894 225153. 1332.26 0.23 0.00204227 0.00181801 13251 44463 -1 186 1 4 4 914 327 2.39001 2.39001 -2.39001 -2.39001 -0.984912 -0.984912 292904. 1733.16 0.02 0.07 0.05 -1 -1 0.02 0.00162703 0.00157897 0 4 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.46 vpr 65.00 MiB -1 -1 0.08 17308 1 0.04 -1 -1 31584 -1 -1 2 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66564 6 1 16 17 2 10 9 17 17 289 -1 auto 26.4 MiB 0.01 128 30 162 45 109 8 65.0 MiB 0.00 0.00 2.32203 1.4327 -4.13089 -1.4327 0.805 0.21 2.6931e-05 1.6557e-05 0.000584509 0.000451852 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.15 0.00187029 0.00164769 24098 82050 -1 103 2 14 14 8045 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.02 0.07 0.04 -1 -1 0.02 0.00128046 0.00121058 1 9 +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 0.95 vpr 64.76 MiB -1 -1 0.07 17312 1 0.02 -1 -1 29984 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 3 1 5 6 1 4 5 13 13 169 -1 auto 26.5 MiB 0.00 38 25 12 5 6 1 64.8 MiB 0.00 0.00 1.12186 0.96686 -1.43992 -0.96686 0.96686 0.11 1.176e-05 7.373e-06 9.5504e-05 7.1942e-05 -1 -1 -1 -1 20 46 1 6.63067e+06 53894 227243. 1344.63 0.08 0.00102566 0.000948714 13251 44387 -1 49 1 4 4 2037 1117 1.60624 1.60624 -1.60624 -1.60624 -0.386566 -0.386566 294987. 1745.49 0.01 0.04 0.02 -1 -1 0.01 0.000916629 0.000875809 0 4 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.43 vpr 65.00 MiB -1 -1 0.08 17312 1 0.03 -1 -1 31592 -1 -1 2 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 6 1 16 17 2 10 9 17 17 289 -1 auto 26.4 MiB 0.01 128 30 162 45 109 8 65.0 MiB 0.00 0.00 2.32504 1.43377 -4.13192 -1.43377 0.805 0.21 2.2762e-05 1.6724e-05 0.000573962 0.000444673 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.15 0.00187733 0.00165636 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.02 0.07 0.04 -1 -1 0.02 0.0012306 0.00116318 1 9 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 0.98 vpr 64.72 MiB -1 -1 0.06 17312 1 0.02 -1 -1 29240 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66272 3 1 5 6 1 4 5 13 13 169 -1 auto 25.9 MiB 0.00 38 25 12 5 6 1 64.7 MiB 0.00 0.00 1.12186 0.96686 -1.43992 -0.96686 0.96686 0.11 2.7322e-05 6.969e-06 0.000108399 6.8796e-05 -1 -1 -1 -1 20 50 1 6.63067e+06 53894 235789. 1395.20 0.08 0.00104947 0.000960311 13251 46155 -1 48 1 4 4 2008 1087 1.59583 1.59583 -1.59583 -1.59583 -0.386566 -0.386566 303533. 1796.05 0.01 0.04 0.02 -1 -1 0.01 0.000933815 0.000894029 0 4 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.43 vpr 65.00 MiB -1 -1 0.08 17308 1 0.03 -1 -1 31608 -1 -1 2 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 6 1 16 17 2 10 9 17 17 289 -1 auto 26.8 MiB 0.01 128 30 162 45 109 8 65.0 MiB 0.00 0.00 2.32203 1.4327 -4.13089 -1.4327 0.805 0.21 2.2521e-05 1.65e-05 0.000581369 0.000454157 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.14 0.00184821 0.00163011 24098 82150 -1 581 2 13 13 6290 3262 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.02 0.07 0.04 -1 -1 0.02 0.00119849 0.00113118 1 9 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.00 vpr 65.00 MiB -1 -1 0.07 17308 1 0.02 -1 -1 29972 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 3 1 5 6 1 4 5 13 13 169 -1 auto 26.8 MiB 0.00 38 25 12 5 6 1 65.0 MiB 0.00 0.00 1.12186 0.96686 -1.43992 -0.96686 0.96686 0.12 1.2422e-05 7.808e-06 9.6046e-05 7.2011e-05 -1 -1 -1 -1 20 177 1 6.63067e+06 53894 225153. 1332.26 0.08 0.00102812 0.000944896 13251 44463 -1 180 1 4 4 885 322 2.22548 2.22548 -2.22548 -2.22548 -1.0058 -1.0058 292904. 1733.16 0.01 0.04 0.02 -1 -1 0.01 0.000967633 0.00090832 0 4 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index 5c6245f2fa3..3a7061254a7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 0.74 vpr 59.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61260 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 21.1 MiB 0.24 70 15 4 10 1 59.8 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000194851 0.000170942 0.00110293 0.00100939 -1 -1 -1 -1 27 263 12 133321 74067 -1 -1 0.15 0.0230545 0.019405 1284 5874 -1 260 8 79 79 17257 10064 1.64234 1.64234 -16.7917 -1.64234 0 0 -1 -1 0.00 0.01 0.01 -1 -1 0.00 0.0047943 0.00439499 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +slicem.xml carry_chain.blif common 0.56 vpr 58.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59816 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 19.2 MiB 0.14 70 70 15 4 10 1 58.4 MiB 0.00 0.00 0.552322 0.523836 -5.19346 -0.523836 0.523836 0.00 6.9663e-05 6.2493e-05 0.000564407 0.000524739 -1 -1 -1 -1 27 337 26 133321 74067 -1 -1 0.09 0.0140806 0.0116706 1284 5874 -1 249 10 84 84 16544 9291 1.47622 1.47622 -16.7882 -1.47622 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0056494 0.00499524 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index bcdd78ccdb6..05b6fd95464 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.33 vpr 58.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60252 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.2 MiB 0.00 31 59 13 43 3 58.8 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.7056e-05 2.9732e-05 0.000307367 0.000251846 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00402393 0.00331535 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00212051 0.00200433 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml ndff.blif common 0.27 vpr 57.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58548 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 36 31 59 13 43 3 57.2 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8658e-05 1.4445e-05 0.000175579 0.000141999 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00231473 0.00196653 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00104772 0.000979247 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index 07d413f9696..95dfec9c5ad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.89 vpr 69.17 MiB -1 -1 0.74 26544 4 0.19 -1 -1 36136 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.19 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.000817884 0.000697618 0.00655739 0.00606976 -1 -1 -1 -1 398 5.30667 131 1.74667 104 164 3400 907 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.01 0.0209255 0.0197757 69.2 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.24 vpr 66.91 MiB -1 -1 0.41 23076 4 0.10 -1 -1 32604 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68520 11 2 303 283 2 82 28 7 7 49 clb auto 27.1 MiB 0.11 424 278 994 204 585 205 66.9 MiB 0.02 0.00 4.1851 4.05951 0 0 3.91314 0.00 0.000352617 0.000321562 0.011537 0.010684 -1 -1 -1 -1 320 4.21053 119 1.56579 117 192 3627 1005 1.07788e+06 808410 219490. 4479.39 5 5100 32136 -1 4.18749 3.93845 0 0 -197.86 -1.707 0.02 -1 -1 66.9 MiB 0.01 0.0238196 0.022287 66.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index 4625b2401ff..3d8cc9cc7a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.45 vpr 65.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 21 4 65.2 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.03 3.7635e-05 2.9892e-05 0.000225074 0.00018278 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.02 0.00833787 0.0081741 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00218203 0.00181006 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.44 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66812 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.2 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1854e-05 2.4534e-05 0.000226572 0.000187065 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.03 0.00709054 0.0068829 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00198245 0.00170015 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.39 vpr 65.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66832 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 22 3 65.3 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.5201e-05 2.6601e-05 0.00022707 0.000179701 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00304545 0.00286146 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00175316 0.00162725 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.41 vpr 65.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.4 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.0901e-05 3.1228e-05 0.000248936 0.000196898 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00216389 0.0019624 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00684314 0.00669963 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.43 vpr 65.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66876 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.3 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 3.9504e-05 2.6238e-05 0.000255838 0.000203867 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00256208 0.00226692 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00410374 0.00385942 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.30 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66632 5 3 11 14 2 9 10 4 4 16 clb auto 26.7 MiB 0.00 21 30 5 23 2 65.1 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 2.4424e-05 1.8925e-05 0.00016567 0.000135551 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.00149783 0.00138533 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00190216 0.00178073 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.32 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65020 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 5 21 4 63.5 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 1.912e-05 1.4716e-05 0.000138868 0.000113336 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.00122882 0.00112591 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00108963 0.00101167 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.32 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65020 5 3 11 14 2 9 10 4 4 16 clb auto 25.2 MiB 0.00 22 22 30 6 14 10 63.5 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.00 1.8239e-05 1.4253e-05 0.000129443 0.000106202 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00121369 0.001109 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00103908 0.000972534 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.33 vpr 63.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64980 5 3 11 14 2 9 10 4 4 16 clb auto 24.8 MiB 0.00 22 21 30 5 22 3 63.5 MiB 0.00 0.00 0.646297 0.646297 -2.19033 -0.646297 0.571 0.00 2.1582e-05 1.6466e-05 0.00015818 0.000130127 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.00 0.00130867 0.00118702 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00114602 0.00105988 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.32 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 7 16 7 63.5 MiB 0.00 0.00 1.64604 1.6463 -5.31965 -1.6463 0.571 0.00 4.4605e-05 3.8769e-05 0.000176185 0.000144336 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.0012431 0.00112184 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00115182 0.00106621 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.33 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 5 3 11 14 2 9 10 4 4 16 clb auto 25.4 MiB 0.00 22 22 30 8 15 7 63.5 MiB 0.00 0.00 1.44967 1.44967 -2.9103 -1.44967 0.571 0.00 2.6664e-05 1.7569e-05 0.00016333 0.000129614 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00152422 0.00133207 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00118439 0.00108721 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.32 vpr 63.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65128 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 5 23 2 63.6 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.00 2.1111e-05 1.6553e-05 0.000146148 0.000120267 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.0012502 0.00114398 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00116517 0.00107026 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index 3373ba9d87f..6e62fc65a75 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.57 vpr 66.20 MiB -1 -1 0.12 21572 1 0.03 -1 -1 33720 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.67 85 398 116 276 6 66.2 MiB 0.01 0.00 2.48207 -27.4234 -2.48207 2.48207 0.03 0.000168115 0.000148552 0.00382732 0.00348451 -1 -1 -1 -1 26 186 18 151211 75605.7 37105.9 1484.24 0.07 0.0274796 0.0239744 1908 5841 -1 144 14 104 128 3783 2136 2.42625 2.42625 -32.7566 -2.42625 0 0 45067.1 1802.68 0.00 0.01 0.01 -1 -1 0.00 0.00858616 0.00782966 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.85 vpr 66.12 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33420 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67704 11 10 108 97 1 49 23 4 4 16 clb auto 26.9 MiB 2.02 135 87 35 39 13 66.1 MiB 0.00 0.00 3.45122 -42.4992 -3.45122 3.45122 0.01 0.000185565 0.000169189 0.00161119 0.00153779 -1 -1 -1 -1 34 225 26 50403.8 50403.8 21558.4 1347.40 0.10 0.0502132 0.0405962 1020 3049 -1 158 14 151 165 4063 2532 3.88646 3.88646 -47.5118 -3.88646 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00719488 0.00664889 15 27 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 6.48 vpr 66.58 MiB -1 -1 0.14 21316 1 0.03 -1 -1 33560 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68180 13 12 149 129 1 68 32 6 6 36 clb auto 27.2 MiB 5.18 196 882 281 588 13 66.6 MiB 0.01 0.00 3.49758 -52.6333 -3.49758 3.49758 0.04 0.000188427 0.000167514 0.00680212 0.00627325 -1 -1 -1 -1 40 395 29 403230 176413 88484.8 2457.91 0.24 0.0901214 0.0785509 3734 16003 -1 328 14 283 356 13658 6213 3.44595 3.44595 -58.2463 -3.44595 0 0 110337. 3064.92 0.00 0.04 0.03 -1 -1 0.00 0.0323499 0.0245182 25 38 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 4.00 vpr 66.86 MiB -1 -1 0.14 21572 1 0.03 -1 -1 33512 -1 -1 7 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 15 14 196 165 1 92 36 6 6 36 clb auto 27.2 MiB 2.65 304 744 159 567 18 66.9 MiB 0.02 0.00 3.62628 -64.4645 -3.62628 3.62628 0.05 0.000406252 0.000363743 0.00800716 0.00737412 -1 -1 -1 -1 52 651 42 403230 176413 110337. 3064.92 0.29 0.109536 0.0955888 4014 20275 -1 496 16 373 551 19804 8423 3.5903 3.5903 -70.6456 -3.5903 0 0 143382. 3982.83 0.00 0.03 0.03 -1 -1 0.00 0.0200523 0.0184119 37 51 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.34 vpr 67.21 MiB -1 -1 0.16 21320 1 0.03 -1 -1 33716 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68824 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 6.96 396 2495 611 1868 16 67.2 MiB 0.04 0.00 3.8369 -73.5721 -3.8369 3.8369 0.03 0.000487285 0.000432143 0.0227482 0.0204679 -1 -1 -1 -1 46 672 23 151211 126010 57775.2 2311.01 0.27 0.134818 0.118379 2220 9391 -1 565 21 712 1067 32893 15487 5.93712 5.93712 -106.904 -5.93712 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0286301 0.0260985 44 66 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.49 vpr 67.34 MiB -1 -1 0.15 21572 1 0.03 -1 -1 33768 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68960 19 18 308 249 1 133 43 5 5 25 clb auto 27.8 MiB 6.09 448 2143 525 1607 11 67.3 MiB 0.04 0.00 4.70186 -94.0493 -4.70186 4.70186 0.03 0.000586405 0.000522924 0.0211391 0.0191781 -1 -1 -1 -1 46 706 50 151211 151211 57775.2 2311.01 0.36 0.18155 0.16007 2220 9391 -1 599 18 697 1112 32896 15750 4.84188 4.84188 -104.71 -4.84188 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0301574 0.0276463 53 83 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.10 vpr 64.34 MiB -1 -1 0.07 17596 1 0.02 -1 -1 30128 -1 -1 3 9 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 9 8 75 70 1 34 20 5 5 25 clb auto 25.2 MiB 0.37 116 87 425 142 281 2 64.3 MiB 0.01 0.00 2.64007 2.48207 -26.067 -2.48207 2.48207 0.01 9.3228e-05 8.39e-05 0.0022793 0.00210862 -1 -1 -1 -1 26 268 23 151211 75605.7 37105.9 1484.24 0.04 0.015438 0.0132379 1908 5841 -1 135 7 69 74 2147 1228 2.87707 2.87707 -32.0609 -2.87707 0 0 45067.1 1802.68 0.00 0.01 0.00 -1 -1 0.00 0.00462719 0.00432137 13 18 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.34 vpr 64.48 MiB -1 -1 0.08 17592 1 0.02 -1 -1 30088 -1 -1 2 11 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 11 10 108 97 1 48 23 4 4 16 clb auto 25.6 MiB 1.57 142 127 279 85 156 38 64.5 MiB 0.00 0.00 3.45122 3.45122 -42.3331 -3.45122 3.45122 0.01 0.000120597 0.000109581 0.00222065 0.00210236 -1 -1 -1 -1 34 218 18 50403.8 50403.8 21558.4 1347.40 0.07 0.0281563 0.0239356 1020 3049 -1 142 9 139 176 4698 2930 3.29429 3.29429 -44.332 -3.29429 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00541739 0.00503817 14 27 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.61 vpr 64.09 MiB -1 -1 0.08 17596 1 0.02 -1 -1 30140 -1 -1 7 13 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 13 12 149 129 1 68 32 6 6 36 clb auto 24.5 MiB 2.75 257 197 732 245 474 13 64.1 MiB 0.01 0.00 3.49758 3.49758 -52.6672 -3.49758 3.49758 0.02 0.000156374 0.000142533 0.00392726 0.00368989 -1 -1 -1 -1 48 388 31 403230 176413 104013. 2889.24 0.11 0.0414693 0.0356383 3910 18599 -1 284 17 330 478 14391 6422 3.69853 3.69853 -57.0037 -3.69853 0 0 131137. 3642.71 0.00 0.01 0.01 -1 -1 0.00 0.00915593 0.00833327 25 38 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.32 vpr 65.20 MiB -1 -1 0.08 17980 1 0.02 -1 -1 30160 -1 -1 6 15 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66768 15 14 196 165 1 93 35 5 5 25 clb auto 25.2 MiB 1.42 387 299 1118 289 798 31 65.2 MiB 0.01 0.00 3.70693 3.64998 -62.024 -3.64998 3.64998 0.01 0.000202129 0.0001848 0.00594995 0.00555165 -1 -1 -1 -1 38 642 42 151211 151211 48493.3 1939.73 0.14 0.0566763 0.0489294 2100 8065 -1 443 21 562 836 28073 13943 4.5307 4.5307 -77.3289 -4.5307 0 0 61632.8 2465.31 0.00 0.02 0.00 -1 -1 0.00 0.0127536 0.0115505 36 51 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 4.33 vpr 65.36 MiB -1 -1 0.09 17596 1 0.03 -1 -1 30128 -1 -1 5 17 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66932 17 16 251 206 1 120 38 5 5 25 clb auto 25.7 MiB 3.40 485 430 227 58 164 5 65.4 MiB 0.01 0.00 3.91442 3.88071 -76.4934 -3.88071 3.88071 0.01 0.000245396 0.000224553 0.00332248 0.00320063 -1 -1 -1 -1 46 639 28 151211 126010 57775.2 2311.01 0.15 0.061068 0.0527302 2220 9391 -1 566 15 540 892 27101 12502 4.50773 4.50773 -92.5696 -4.50773 0 0 73020.3 2920.81 0.00 0.02 0.01 -1 -1 0.00 0.0138066 0.0127692 45 66 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.46 vpr 65.57 MiB -1 -1 0.09 18360 1 0.03 -1 -1 30076 -1 -1 9 19 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67144 19 18 308 249 1 134 46 6 6 36 clb auto 25.9 MiB 3.44 628 450 3408 877 2509 22 65.6 MiB 0.03 0.00 5.19392 4.85986 -99.9643 -4.85986 4.85986 0.02 0.000293829 0.000269579 0.0149755 0.0138941 -1 -1 -1 -1 56 839 22 403230 226817 117789. 3271.93 0.17 0.0794032 0.0696928 4086 21443 -1 597 17 428 696 24582 10181 4.89622 4.89622 -97.5059 -4.89622 0 0 149557. 4154.36 0.00 0.02 0.01 -1 -1 0.00 0.0165564 0.0152987 54 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt index 900ba99d8f4..9e56ce66f42 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 17.03 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.49 3.9173e-05 3.1698e-05 0.000338068 0.000271828 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00193749 0.00171766 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00201882 0.00189534 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common 4.41 vpr 57.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58528 6 7 19 26 0 19 26 3 3 9 -1 auto 18.3 MiB 0.00 51 51 216 43 63 110 57.2 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.70 2.1988e-05 1.7826e-05 0.000208624 0.000166423 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00147039 0.00133536 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.00101656 0.000954631 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt index 160cbfe1388..c6ae836957f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.33 vpr 59.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60416 2 2 4 5 0 4 5 3 3 9 -1 auto 20.7 MiB 0.00 8 12 0 0 12 59.0 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7245e-05 1.217e-05 9.686e-05 7.1239e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.0017081 0.00158045 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00139703 0.00135574 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +heterogeneous_tile.xml sub_tile_directs.blif common 0.27 vpr 56.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58056 2 2 4 5 0 4 5 3 3 9 -1 auto 18.3 MiB 0.00 8 8 12 0 0 12 56.7 MiB 0.00 0.00 1.899 1.899 -3.798 -1.899 nan 0.01 9.727e-06 6.488e-06 6.998e-05 5.1168e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.00 0.00122818 0.00113256 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000846926 0.000812399 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index 6303f27bd50..da0293d8273 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.72 vpr 66.86 MiB -1 -1 0.36 22284 3 0.10 -1 -1 36712 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 99 73 292 365 1 173 192 8 8 64 io memory auto 27.1 MiB 0.06 704 10699 1176 8237 1286 66.9 MiB 0.06 0.00 2.09255 -114.438 -2.09255 2.09255 0.09 0.000494971 0.000445037 0.0176268 0.0158319 -1 -1 -1 -1 32 1440 34 2.23746e+06 1.57199e+06 106908. 1670.44 0.32 0.14258 0.127902 4378 18911 -1 1142 12 555 876 46439 15775 1.9226 1.9226 -129.963 -1.9226 -0.449924 -0.248875 130676. 2041.82 0.01 0.04 0.02 -1 -1 0.01 0.0280032 0.0259551 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.13 vpr 65.30 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32716 -1 -1 20 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66864 99 73 292 365 1 172 193 8 8 64 io memory auto 25.6 MiB 0.04 1172 675 12447 1623 9101 1723 65.3 MiB 0.03 0.00 1.95866 1.82604 -115.206 -1.82604 1.82604 0.04 0.000448857 0.000413203 0.0118962 0.0110762 -1 -1 -1 -1 32 1268 15 2.23746e+06 1.62588e+06 106908. 1670.44 0.13 0.0638055 0.0575788 4378 18911 -1 1059 9 499 808 37153 12810 1.99391 1.99391 -128.303 -1.99391 -0.246226 -0.119866 130676. 2041.82 0.00 0.02 0.01 -1 -1 0.00 0.0126544 0.0117786 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index 9a4d84cf163..4c74c74dc2a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 1.36 vpr 68.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70192 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.18 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000585274 0.000508741 0.0133922 0.0121686 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183472 0.161021 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0299915 0.0274705 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.08 vpr 68.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70320 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.7 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000329127 0.000280288 0.00811479 0.00735661 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.35 0.13039 0.113608 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0216396 0.0198831 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 3.83 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70724 10 10 168 178 1 162 111 14 14 196 clb auto 29.5 MiB 0.87 1467 5165 686 4267 212 69.1 MiB 0.06 0.00 2.95542 -36.8348 -2.95542 2.95542 0.33 0.000607935 0.000523594 0.0180811 0.0161249 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.224715 0.196946 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.10 -1 -1 0.03 0.0292402 0.0269351 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.85 vpr 68.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69972 10 10 168 178 1 75 33 7 7 49 clb auto 28.8 MiB 0.15 414 605 98 486 21 68.3 MiB 0.01 0.00 2.40687 -27.3475 -2.40687 2.40687 0.04 0.000340986 0.000290037 0.00724905 0.00664099 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.16 0.0618811 0.0547109 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.03 0.01 -1 -1 0.00 0.0207833 0.0191052 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.40 vpr 69.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70700 10 10 168 178 1 163 124 14 14 196 clb auto 29.4 MiB 0.95 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.22 0.000345985 0.000292911 0.012717 0.0113191 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.21 0.0326189 0.0295477 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.08 -1 -1 0.03 0.0265139 0.024324 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.40 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70232 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.6 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000587109 0.000509454 0.0135198 0.0122638 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183086 0.160678 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0347629 0.0319856 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.32 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70240 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.16 399 703 140 536 27 68.6 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.03 0.000756907 0.000658585 0.016978 0.0153763 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.44 0.169468 0.148387 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.03477 0.0320116 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 3.38 vpr 68.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70504 10 10 168 178 1 162 111 14 14 196 clb auto 29.2 MiB 0.88 1467 5165 686 4267 212 68.9 MiB 0.04 0.00 2.95542 -36.8348 -2.95542 2.95542 0.28 0.000322881 0.000275771 0.0115436 0.0102519 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.09 0.158857 0.137775 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.02 0.05 0.05 -1 -1 0.02 0.0172724 0.0158752 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.48 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70176 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000502609 0.00043998 0.0125423 0.0114378 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.54 0.190745 0.166737 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.07 0.02 -1 -1 0.00 0.0474457 0.0433946 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 30.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30760 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30632 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.09 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 30.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31272 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml styr.blif common_--target_ext_pin_util_1 0.71 vpr 66.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67956 10 10 168 178 1 75 32 6 6 36 clb auto 26.7 MiB 0.11 467 424 582 89 470 23 66.4 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000313613 0.000281494 0.00679637 0.00633558 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0534045 0.0470259 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0179228 0.0165339 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.72 vpr 66.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68432 10 10 168 178 1 75 32 6 6 36 clb auto 27.1 MiB 0.11 467 424 582 89 470 23 66.8 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000305552 0.000274195 0.00713015 0.0066753 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.054037 0.0476882 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0176859 0.0162969 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 1.56 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68816 10 10 168 178 1 162 110 14 14 196 clb auto 27.5 MiB 0.42 2218 1472 5633 779 4632 222 67.2 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.15 0.00031345 0.000281685 0.00904718 0.00829193 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.27 0.0481118 0.0422936 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.01 0.03 0.04 -1 -1 0.01 0.0135904 0.0125798 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.78 vpr 66.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68504 10 10 168 178 1 73 34 7 7 49 clb auto 27.1 MiB 0.13 556 403 749 133 594 22 66.9 MiB 0.01 0.00 2.47538 2.3678 -27.2356 -2.3678 2.3678 0.02 0.000298629 0.000272401 0.00710384 0.00662899 -1 -1 -1 -1 28 1121 29 1.07788e+06 754516 79600.7 1624.51 0.14 0.0554737 0.0489437 3864 14328 -1 1032 22 640 2278 94416 33063 2.98849 2.98849 -34.8096 -2.98849 0 0 95067.4 1940.15 0.00 0.04 0.01 -1 -1 0.00 0.0199587 0.0182086 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 1.42 vpr 66.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68488 10 10 168 178 1 163 124 14 14 196 clb auto 27.5 MiB 0.44 2325 1534 6922 992 5667 263 66.9 MiB 0.03 0.00 4.16044 3.06133 -37.5377 -3.06133 3.06133 0.14 0.000311352 0.000274658 0.00930477 0.00849636 -1 -1 -1 -1 20 3156 16 9.20055e+06 5.60498e+06 295730. 1508.82 0.15 0.02425 0.0219885 18004 60473 -1 3023 14 646 2892 171027 37325 3.649 3.649 -45.9039 -3.649 0 0 387483. 1976.95 0.01 0.04 0.03 -1 -1 0.01 0.0134846 0.0122796 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 0.69 vpr 66.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68048 10 10 168 178 1 75 32 6 6 36 clb auto 27.1 MiB 0.11 467 424 582 89 470 23 66.5 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000306309 0.000275002 0.00676603 0.00631847 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0532485 0.0469451 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0175558 0.0161696 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 0.73 vpr 66.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68428 10 10 168 178 1 75 32 6 6 36 clb auto 27.1 MiB 0.11 467 424 582 89 470 23 66.8 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000307986 0.000276629 0.0070174 0.00655743 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0545965 0.0481718 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0179832 0.0165712 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 1.50 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68808 10 10 168 178 1 162 110 14 14 196 clb auto 27.5 MiB 0.41 2218 1472 5633 779 4632 222 67.2 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.14 0.000314699 0.000283874 0.00894991 0.00821764 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.26 0.0462803 0.0408134 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.02 0.03 0.04 -1 -1 0.02 0.0139896 0.0128573 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 0.71 vpr 66.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67820 10 10 168 178 1 75 32 6 6 36 clb auto 26.9 MiB 0.11 467 424 582 89 470 23 66.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.01 0.00030683 0.000275575 0.00684586 0.00639772 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0539268 0.047514 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.017759 0.0163694 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.09 vpr 27.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28308 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.5 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.09 vpr 28.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28940 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.8 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.08 vpr 27.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28552 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.4 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 28.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28768 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt index b99a452bc00..d76b9e88079 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 8.05 vpr 75.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76868 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.4 MiB 3.87 8858 177806 51921 111135 14750 75.1 MiB 1.04 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00614227 0.00545306 0.382618 0.335662 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.30 0.645332 0.579161 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 3.97 vpr 74.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 118 229 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76288 229 197 2152 2349 1 1012 544 16 16 256 io auto 34.5 MiB 1.98 13816 8635 175845 51740 110676 13429 74.5 MiB 0.61 0.01 3.6187 2.93018 -676.548 -2.93018 2.93018 0.00 0.00279674 0.00248348 0.242611 0.219358 -1 -1 -1 -1 -1 11066 15 1.05632e+07 6.35949e+06 4.24953e+06 16599.7 0.17 0.383649 0.351659 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index 6fffcd3b3ab..996a275157f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.73 vpr 66.23 MiB -1 -1 0.21 18848 3 0.07 -1 -1 33068 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67824 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000568632 0.000529819 0.0441667 0.0411462 -1 -1 -1 -1 38 1437 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.33 0.158129 0.144291 12522 62564 -1 1141 11 437 710 29360 10219 1.94502 1.94502 -130.926 -1.94502 -0.717819 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0184928 0.0172512 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 1.71 vpr 66.23 MiB -1 -1 0.22 18852 3 0.07 -1 -1 32740 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67816 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000612619 0.000577396 0.0464401 0.0430253 -1 -1 -1 -1 38 1420 13 5.66058e+06 4.21279e+06 319130. 2216.18 0.30 0.130527 0.117061 12522 62564 -1 1150 9 446 701 30426 10498 1.94502 1.94502 -131.108 -1.94502 -0.67939 -0.29768 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0159542 0.0144078 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.84 vpr 66.23 MiB -1 -1 0.22 18176 3 0.07 -1 -1 33108 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67820 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000564449 0.000527167 0.0443768 0.0414183 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.38 0.152118 0.139015 12522 62564 -1 1128 9 408 669 127450 127450 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.04 0.04 -1 -1 0.01 0.0159569 0.0149713 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.94 vpr 66.23 MiB -1 -1 0.22 18868 3 0.07 -1 -1 33116 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67824 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.13 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000582283 0.000543802 0.0455405 0.0424991 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.47 0.157265 0.143773 12522 62564 -1 1128 9 408 669 125250 125250 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.09 0.04 -1 -1 0.01 0.0167922 0.015747 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.89 vpr 66.23 MiB -1 -1 0.22 18848 3 0.07 -1 -1 33096 -1 -1 68 99 1 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 67820 99 130 344 474 1 227 298 12 12 144 clb auto 26.8 MiB 0.11 1695 684 72933 23047 34243 15643 66.2 MiB 0.14 0.00 1.98228 1.86362 -118.513 -1.86362 1.86362 0.10 0.000581227 0.000543053 0.0461546 0.0430967 -1 -1 -1 -1 38 1391 8 5.66058e+06 4.21279e+06 319130. 2216.18 0.44 0.161183 0.147677 12522 62564 -1 1128 9 408 669 126593 45250 1.94524 1.94524 -129.851 -1.94524 -1.0383 -0.320482 406292. 2821.48 0.01 0.07 0.04 -1 -1 0.01 0.0170636 0.0159891 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.94 vpr 66.48 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32732 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68076 99 130 344 474 1 228 298 12 12 144 clb auto 26.8 MiB 0.10 1675 704 66963 20370 32791 13802 66.5 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000562371 0.000525588 0.0406586 0.038039 -1 -1 -1 -1 40 1453 15 5.66058e+06 4.21279e+06 333335. 2314.82 0.58 0.162361 0.14854 12666 64609 -1 1222 11 442 668 30453 10334 2.02932 2.02932 -138.236 -2.02932 -0.424985 -0.298787 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0185134 0.0173313 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 1.87 vpr 66.56 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32732 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68156 99 130 344 474 1 228 298 12 12 144 clb auto 26.7 MiB 0.10 1675 704 66963 20370 32791 13802 66.6 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000558315 0.00052341 0.0411328 0.0379157 -1 -1 -1 -1 40 1452 13 5.66058e+06 4.21279e+06 333335. 2314.82 0.54 0.134079 0.119822 12666 64609 -1 1250 11 460 694 31414 10385 2.02932 2.02932 -140.547 -2.02932 -0.436676 -0.298787 419432. 2912.72 0.01 0.02 0.04 -1 -1 0.01 0.0157064 0.0140295 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 2.16 vpr 66.34 MiB -1 -1 0.21 18828 3 0.06 -1 -1 32772 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67932 99 130 344 474 1 228 298 12 12 144 clb auto 26.5 MiB 0.10 1675 704 66963 20370 32791 13802 66.3 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.10 0.000551715 0.000515 0.0404626 0.0378544 -1 -1 -1 -1 40 1412 11 5.66058e+06 4.21279e+06 333335. 2314.82 0.78 0.166185 0.152303 12666 64609 -1 1211 10 419 673 142013 142013 1.98169 1.98169 -135.576 -1.98169 -0.436676 -0.298787 419432. 2912.72 0.01 0.05 0.04 -1 -1 0.01 0.0176156 0.0165382 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 2.23 vpr 66.57 MiB -1 -1 0.22 18444 3 0.06 -1 -1 32724 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68168 99 130 344 474 1 228 298 12 12 144 clb auto 26.8 MiB 0.10 1675 704 66963 20370 32791 13802 66.6 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000570894 0.000535109 0.0411409 0.0385856 -1 -1 -1 -1 40 1412 11 5.66058e+06 4.21279e+06 333335. 2314.82 0.84 0.161192 0.147867 12666 64609 -1 1211 10 419 673 140888 140888 1.98169 1.98169 -135.576 -1.98169 -0.436676 -0.298787 419432. 2912.72 0.01 0.10 0.04 -1 -1 0.01 0.0169308 0.0158811 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 2.12 vpr 66.28 MiB -1 -1 0.21 18444 3 0.06 -1 -1 32736 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67868 99 130 344 474 1 228 298 12 12 144 clb auto 26.5 MiB 0.10 1675 704 66963 20370 32791 13802 66.3 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000568987 0.000532832 0.0407334 0.0381626 -1 -1 -1 -1 40 1412 11 5.66058e+06 4.21279e+06 333335. 2314.82 0.77 0.160479 0.147022 12666 64609 -1 1211 10 419 673 141703 53908 1.98169 1.98169 -135.576 -1.98169 -0.436676 -0.298787 419432. 2912.72 0.01 0.05 0.04 -1 -1 0.01 0.0175063 0.0163964 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt index 7b4fc76c6e6..d74871bcfe5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.55 vpr 67.97 MiB -1 -1 0.42 22420 3 0.14 -1 -1 36800 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69600 99 130 344 474 1 225 298 12 12 144 clb auto 28.5 MiB 0.19 695 57013 16754 28454 11805 68.0 MiB 0.25 0.00 1.84453 -73.0907 -1.84453 1.84453 0.29 0.000572985 0.000494317 0.0593261 0.049655 -1 -1 -1 -1 32 1551 10 5.66058e+06 4.21279e+06 281316. 1953.58 1.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 1.25 vpr 66.54 MiB -1 -1 0.21 18440 3 0.06 -1 -1 32720 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68140 99 130 344 474 1 224 298 12 12 144 clb auto 27.1 MiB 0.09 1590 710 59003 16103 31150 11750 66.5 MiB 0.09 0.00 2.39882 1.86362 -71.5534 -1.86362 1.86362 0.09 0.000538644 0.000497828 0.023206 0.0214651 -1 -1 -1 -1 30 1493 8 5.66058e+06 4.21279e+06 267238. 1855.82 0.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt index 50b6703de2b..f151570289b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.13 vpr 67.88 MiB -1 -1 0.41 22284 3 0.13 -1 -1 36924 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69508 99 130 344 474 1 218 298 12 12 144 clb auto 28.4 MiB 0.23 632 70943 19608 36161 15174 67.9 MiB 0.23 0.00 2.24009 0 0 2.24009 0.25 0.000717536 0.00062496 0.0508972 0.0435443 -1 -1 -1 -1 32 1480 8 5.66058e+06 4.21279e+06 281316. 1953.58 0.55 0.227253 0.196073 11950 52952 -1 1327 7 304 419 24960 8371 2.42926 2.42926 0 0 0 0 345702. 2400.71 0.03 0.05 0.08 -1 -1 0.03 0.020098 0.0186968 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 1.54 vpr 66.54 MiB -1 -1 0.22 18440 3 0.07 -1 -1 32712 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68132 99 130 344 474 1 220 298 12 12 144 clb auto 26.8 MiB 0.08 1597 670 73928 20988 37298 15642 66.5 MiB 0.10 0.00 2.12094 1.86992 0 0 1.86992 0.09 0.00032505 0.000297593 0.0266159 0.0244779 -1 -1 -1 -1 32 1510 10 5.66058e+06 4.21279e+06 281316. 1953.58 0.24 0.114031 0.0985162 11950 52952 -1 1387 6 289 390 22972 7530 2.02363 2.02363 0 0 0 0 345702. 2400.71 0.01 0.01 0.03 -1 -1 0.01 0.00829442 0.00764588 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index a5bee947840..ece07b7e104 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.50 vpr 67.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68660 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.6443e-05 3.2529e-05 0.000274786 0.000214986 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00211509 0.0019009 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0017763 0.00169895 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.49 vpr 67.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8016e-05 3.4218e-05 0.000283686 0.000224427 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0022472 0.00206472 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00179634 0.00171755 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.51 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68932 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 6.2523e-05 4.6425e-05 0.000366128 0.000294026 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00236124 0.00216436 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00189537 0.00181322 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.37 vpr 65.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66972 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.00 24 21 30 9 19 2 65.4 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.365e-05 1.6268e-05 0.00017217 0.000137772 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00127205 0.00116262 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00100347 0.000952445 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.38 vpr 64.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 24 21 30 9 19 2 64.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3226e-05 1.5977e-05 0.000162476 0.000128834 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0012484 0.00113683 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00104939 0.000997318 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.38 vpr 65.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66972 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.00 24 21 30 9 19 2 65.4 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3551e-05 1.6219e-05 0.000166445 0.000130951 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00125751 0.00114805 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00103369 0.000982231 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt index db634e1dc04..f5a70e45013 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.81 vpr 69.01 MiB -1 -1 0.66 26668 4 0.21 -1 -1 35972 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70664 11 2 303 283 2 78 28 7 7 49 clb auto 29.4 MiB 0.25 285 784 175 539 70 69.0 MiB 0.04 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000759025 0.000652417 0.0254764 0.023241 -1 -1 -1 -1 -1 313 6 1.07788e+06 808410 219490. 4479.39 0.03 0.050656 0.046841 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.77 vpr 66.82 MiB -1 -1 0.40 23072 4 0.10 -1 -1 32592 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68428 11 2 303 283 2 85 28 7 7 49 clb auto 27.2 MiB 0.11 462 289 1204 263 848 93 66.8 MiB 0.02 0.00 2.20327 2.04719 -154.888 -2.04719 1.90466 0.00 0.000386086 0.000344716 0.0143127 0.012902 -1 -1 -1 -1 -1 314 6 1.07788e+06 808410 219490. 4479.39 0.01 0.0280135 0.0257414 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt index 77ef7d0e8b9..0e6c2e24870 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt @@ -1,13 +1,13 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.18 vpr 63.79 MiB -1 -1 0.41 23448 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65324 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.04 198 153 432 69 336 27 63.8 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000235029 0.000214051 0.00424678 0.00391288 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.0155905 0.0141088 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.20 vpr 63.94 MiB -1 -1 0.50 23444 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65472 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 63.9 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000230258 0.000209554 0.0042499 0.00390533 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.0141455 0.0127342 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.11 vpr 63.97 MiB -1 -1 0.42 23452 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65504 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.01e-06 1.071e-06 0.00158168 0.00142451 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.00723412 0.00548559 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.13 vpr 63.97 MiB -1 -1 0.41 23448 5 0.11 -1 -1 32628 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65504 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000115071 2.5318e-05 0.00166514 0.00142585 -1 -1 -1 -1 -1 141 15 646728 646728 138825. 3856.24 0.01 0.00729191 0.00547656 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.11 vpr 63.98 MiB -1 -1 0.42 23452 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65512 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 9.591e-06 1.027e-06 0.00173563 0.0014501 -1 -1 -1 -1 -1 142 18 646728 646728 138825. 3856.24 0.01 0.00799653 0.00565668 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 1.16 vpr 63.95 MiB -1 -1 0.42 23452 5 0.12 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65484 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 63.9 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.00043462 0.000402413 0.00710114 0.00653478 -1 -1 -1 -1 -1 142 18 646728 646728 138825. 3856.24 0.02 0.0217234 0.019335 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.16 vpr 63.97 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65504 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.083e-06 1.137e-06 0.00158114 0.00142356 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.00778711 0.00588202 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.20 vpr 63.88 MiB -1 -1 0.42 23468 5 0.11 -1 -1 32824 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65412 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 63.9 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.78e-06 1.407e-06 0.0017981 0.00159724 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.07 0.00815512 0.00618452 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.18 vpr 63.99 MiB -1 -1 0.42 23468 5 0.11 -1 -1 32824 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65528 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 64.0 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 4.165e-06 1.08e-06 0.00160201 0.00144669 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.05 0.00798852 0.00607253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.15 vpr 63.94 MiB -1 -1 0.42 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65472 10 2 181 183 1 35 24 6 6 36 clb auto 24.9 MiB 0.03 198 153 432 69 336 27 63.9 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000221105 0.000200581 0.00411028 0.00377693 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.03 0.0144868 0.0129751 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.20 vpr 63.53 MiB -1 -1 0.41 23464 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65056 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.03 198 153 432 69 336 27 63.5 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000225457 0.000205137 0.00415833 0.0038325 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.07 0.0147425 0.0132082 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.17 vpr 63.71 MiB -1 -1 0.42 23452 5 0.11 -1 -1 32816 -1 -1 12 10 0 0 success c8266d389-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-01T21:51:43 betzgrp-wintermute /home/yanhang1/parallel-router/vtr-verilog-to-routing/vtr_flow/tasks 65240 10 2 181 183 1 35 24 6 6 36 clb auto 24.3 MiB 0.03 198 153 432 69 336 27 63.7 MiB 0.01 0.00 2.2957 2.14835 -93.1844 -2.14835 2.14835 0.00 0.000227544 0.000206409 0.00424772 0.00391181 -1 -1 -1 -1 -1 145 17 646728 646728 138825. 3856.24 0.05 0.0147416 0.0132112 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.09 vpr 64.27 MiB -1 -1 0.42 23428 5 0.11 -1 -1 32572 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000222766 0.000201734 0.00389424 0.00360389 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.0142381 0.0128197 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.09 vpr 63.95 MiB -1 -1 0.41 23428 5 0.10 -1 -1 32576 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65484 10 2 181 183 1 36 24 6 6 36 clb auto 24.6 MiB 0.02 196 160 398 88 284 26 63.9 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000222779 0.000201937 0.00391759 0.00362401 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.0142174 0.0127941 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.11 vpr 64.30 MiB -1 -1 0.44 23428 5 0.10 -1 -1 32584 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 10 2 181 183 1 36 24 6 6 36 clb auto 24.8 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.0708e-05 1.5231e-05 0.0014017 0.00127195 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.00714763 0.00535987 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.08 vpr 63.74 MiB -1 -1 0.41 23416 5 0.10 -1 -1 32592 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65272 10 2 181 183 1 36 24 6 6 36 clb auto 24.7 MiB 0.02 196 160 398 88 284 26 63.7 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000128757 3.5271e-05 0.00160333 0.00138472 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.00746153 0.00560158 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.13 vpr 63.79 MiB -1 -1 0.41 23800 5 0.10 -1 -1 32580 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65316 10 2 181 183 1 36 24 6 6 36 clb auto 24.8 MiB 0.03 196 160 398 88 284 26 63.8 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 4.2273e-05 3.0292e-05 0.00168368 0.0014329 -1 -1 -1 -1 -1 146 18 646728 646728 138825. 3856.24 0.01 0.00798524 0.00566268 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 1.10 vpr 64.06 MiB -1 -1 0.41 23416 5 0.10 -1 -1 32584 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65596 10 2 181 183 1 36 24 6 6 36 clb auto 24.6 MiB 0.02 196 160 398 88 284 26 64.1 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000395659 0.000368361 0.00601719 0.00558884 -1 -1 -1 -1 -1 146 18 646728 646728 138825. 3856.24 0.02 0.0192173 0.0172102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.08 vpr 64.30 MiB -1 -1 0.40 23048 5 0.10 -1 -1 32596 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.0413e-05 1.4906e-05 0.00139428 0.00126275 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.03 0.00728859 0.00538349 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.15 vpr 64.30 MiB -1 -1 0.41 23428 5 0.10 -1 -1 32624 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.0732e-05 1.524e-05 0.00145249 0.00132501 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.08 0.00760196 0.00568525 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.10 vpr 64.30 MiB -1 -1 0.42 23044 5 0.11 -1 -1 32596 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.1096e-05 1.5558e-05 0.00147388 0.00133793 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.05 0.0075207 0.00563955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.14 vpr 64.30 MiB -1 -1 0.42 23044 5 0.11 -1 -1 32588 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000221012 0.00020011 0.00389967 0.00361209 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.03 0.0153274 0.0137388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.14 vpr 64.28 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32588 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000225132 0.000204043 0.00417724 0.00383718 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.05 0.0187942 0.0167045 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.13 vpr 64.27 MiB -1 -1 0.42 23428 5 0.11 -1 -1 32588 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000223349 0.000202453 0.00387379 0.0035863 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.04 0.0153058 0.0136886 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index e84a1129700..e88e2fe2f90 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.79 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215864 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.3 MiB 15.63 75097 245792 47628 188491 9673 1158.7 MiB 16.87 0.21 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0552629 0.0482483 4.22516 3.43532 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 5.27 -1 -1 1158.7 MiB 5.35 6.14131 5.12726 1158.7 MiB -1 3.33 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 33.99 vpr 1.16 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1214544 13 29 26295 20086 1 12646 791 39 29 1131 LAB auto 1076.9 MiB 7.80 231619 75107 234775 43541 180854 10380 1154.4 MiB 6.01 0.08 5.55061 5.16398 -5504.03 -4.16398 2.86102 0.00 0.0216745 0.0190067 1.74141 1.438 87307 6.90501 21230 1.67906 25811 34329 9106433 1637889 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.36451 2.98815 -5707.14 -4.36451 0 0 3.24 -1 -1 1154.4 MiB 2.59 2.80019 2.37571 1154.4 MiB -1 1.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt index 7d3888ea0e0..b5222df5ce6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 19.43 vpr 384.88 MiB 35 93 0 0 8 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 394112 18 17 2338 2195 1 2035 136 17 13 221 io_cell auto 342.6 MiB 9.23 11597 14096 2127 10583 1386 384.9 MiB 0.99 0.03 3.78594 -3334.96 -2.78594 3.78594 0.00 0.0127693 0.0106573 0.428449 0.35312 12754 6.27657 3971 1.95423 6857 16497 4298918 925978 0 0 3.37726e+06 15281.7 12 52540 541133 -1 3.215 3.215 -2910.24 -2.215 0 0 1.33 -1 -1 384.9 MiB 1.91 0.811838 0.706005 384.9 MiB -1 0.27 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 9.50 vpr 385.09 MiB 35 86 0 0 8 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 394328 18 17 2338 2195 1 2026 129 17 13 221 io_cell auto 344.2 MiB 4.44 19688 12064 13129 2012 9707 1410 385.1 MiB 0.43 0.01 4.85192 3.71062 -3391.61 -2.71062 3.71062 0.00 0.00349484 0.00291013 0.180937 0.154879 13833 6.83786 4143 2.04795 6992 16873 4273349 902603 0 0 3.37726e+06 15281.7 13 52540 541133 -1 3.321 3.321 -2993.48 -2.321 0 0 0.55 -1 -1 385.1 MiB 0.88 0.370237 0.329843 385.1 MiB -1 0.14 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 6ff0e8d886f..2870c0dcfa7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 22.01 vpr 69.98 MiB -1 -1 0.42 25672 5 0.18 -1 -1 37676 -1 -1 17 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 71656 66 96 983 697 1 557 191 16 16 256 mult_27 auto 30.8 MiB 2.52 4520 41915 13784 24449 3682 70.0 MiB 0.47 0.01 16.7771 -983.813 -16.7771 16.7771 0.51 0.00380097 0.00356084 0.223806 0.20783 -1 -1 -1 -1 82 9891 30 4.83877e+06 1.03328e+06 1.63760e+06 6396.87 14.79 1.72784 1.60303 43164 348864 -1 8812 16 2703 5592 1100371 345017 16.7238 16.7238 -1023.47 -16.7238 0 0 2.03272e+06 7940.32 0.12 0.37 0.48 -1 -1 0.12 0.123499 0.117943 138 202 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 5.80 vpr 68.89 MiB -1 -1 0.20 22204 5 0.10 -1 -1 33784 -1 -1 17 66 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70540 66 96 983 697 1 561 191 16 16 256 mult_27 auto 29.3 MiB 0.61 8149 4596 38072 11997 23544 2531 68.9 MiB 0.22 0.00 19.4757 17.0827 -970.661 -17.0827 17.0827 0.21 0.00129546 0.00120683 0.0982081 0.091818 -1 -1 -1 -1 62 12202 30 4.83877e+06 1.03328e+06 1.31386e+06 5132.27 2.93 0.40155 0.371234 39852 267778 -1 9854 19 3552 7322 1583377 471194 17.0705 17.0705 -1067.68 -17.0705 0 0 1.60318e+06 6262.42 0.04 0.25 0.14 -1 -1 0.04 0.0690741 0.0653357 140 202 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index 8a9769fe6bb..5887a04a315 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.48 vpr 65.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66896 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000116029 0.000100823 0.0010942 0.00101432 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.3 MiB 0.01 0.00766251 0.00688033 65.3 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.51 vpr 65.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66796 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000165834 0.000146968 0.00119076 0.00110326 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.00909464 0.00816836 65.2 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.24 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000113726 9.7512e-05 0.00114825 0.00106423 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.3 MiB 0.03 -1 -1 65.3 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.24 vpr 65.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66624 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.1 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.00013832 0.000115541 0.000955845 0.00087775 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.1 MiB 0.03 -1 -1 65.1 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.17 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64492 6 8 39 47 1 20 17 5 5 25 clb auto 24.3 MiB 0.01 107 88 59 31 28 0 63.0 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 7.9358e-05 7.06e-05 0.000702625 0.000659908 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.0 MiB 0.01 0.00494254 0.00441175 63.0 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.17 vpr 62.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64364 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.01 107 88 59 31 28 0 62.9 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 7.9701e-05 7.0904e-05 0.000704152 0.00066155 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 62.9 MiB 0.01 0.00497552 0.00444693 62.9 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.18 vpr 63.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64692 6 8 39 47 1 20 17 5 5 25 clb auto 24.9 MiB 0.01 107 88 59 31 28 0 63.2 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 8.0556e-05 7.1754e-05 0.000710303 0.000667295 -1 -1 -1 -1 -1 -1 -1 -1 656 1029 31338 15241 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.2 MiB 0.02 -1 -1 63.2 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.19 vpr 63.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64668 6 8 39 47 1 20 17 5 5 25 clb auto 24.3 MiB 0.01 107 88 59 31 28 0 63.2 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 7.9004e-05 7.0259e-05 0.000720378 0.000678096 -1 -1 -1 -1 141 7.42105 65 3.42105 656 1029 31338 15241 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9119 -1.84852 0 0 0.00 -1 -1 63.2 MiB 0.02 -1 -1 63.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index cb597e00427..54d5147cb89 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.77 vpr 60.00 MiB -1 -1 0.91 26856 6 0.21 -1 -1 36836 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61436 10 2 186 188 1 48 40 8 8 64 clb auto 20.5 MiB 0.04 230 992 145 785 62 60.0 MiB 0.03 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000447321 0.000382714 0.00843147 0.00745792 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.09 -1 -1 60.0 MiB 0.03 0.0220189 0.0194464 60.0 MiB -1 0.01 - k6_frac_N10_40nm.xml stereovision3.v common 2.04 vpr 61.65 MiB -1 -1 0.81 26884 5 0.16 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.07 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000403252 0.000354056 0.00494195 0.00440924 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.03 -1 -1 61.7 MiB 0.01 0.0168116 0.0156639 61.7 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 1.32 vpr 58.29 MiB -1 -1 0.39 23264 6 0.10 -1 -1 32592 -1 -1 28 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59688 10 2 186 188 1 46 40 8 8 64 clb auto 18.3 MiB 0.01 370 219 1196 185 951 60 58.3 MiB 0.01 0.00 3.46426 2.64808 -111.051 -2.64808 2.64808 0.00 0.000230277 0.000209848 0.00499518 0.00455702 -1 -1 -1 -1 190 4.41860 190 4.41860 181 461 16985 3541 80255.5 62421 276194. 4315.53 13 9480 40228 -1 2.65254 2.65254 -110.961 -2.65254 -0.0734 -0.0734 0.03 -1 -1 58.3 MiB 0.01 0.013254 0.0119008 58.3 MiB -1 0.00 +k6_frac_N10_40nm.xml stereovision3.v common 1.27 vpr 59.75 MiB -1 -1 0.39 23288 5 0.10 -1 -1 32580 -1 -1 7 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61184 10 2 181 183 1 38 19 5 5 25 clb auto 20.0 MiB 0.03 159 121 469 107 323 39 59.8 MiB 0.01 0.00 2.03188 2.03188 -84.6958 -2.03188 2.03188 0.00 0.000218134 0.000198163 0.00575791 0.00533131 -1 -1 -1 -1 105 3.00000 54 1.54286 61 90 1611 507 485046 377258 99699.4 3987.98 6 2523 14238 -1 2.07226 2.07226 -86.1872 -2.07226 0 0 0.01 -1 -1 59.8 MiB 0.01 0.0133683 0.0124329 59.8 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt index 0fde75bd1ed..f0211e745a4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.09 vpr 60.07 MiB -1 -1 0.81 26980 6 0.15 -1 -1 36756 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61512 10 2 186 188 1 48 40 8 8 64 clb auto 20.6 MiB 0.03 230 992 145 785 62 60.1 MiB 0.02 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000430706 0.00037483 0.00785446 0.00688801 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.08 -1 -1 60.1 MiB 0.02 0.0211284 0.0188358 60.1 MiB -1 0.01 - k6_frac_N10_40nm.xml stereovision3.v common 1.94 vpr 61.65 MiB -1 -1 0.77 26880 5 0.18 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.1 MiB 0.06 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000420371 0.000366917 0.00494209 0.00453968 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.02 -1 -1 61.7 MiB 0.01 0.0164382 0.0153894 61.7 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 1.31 vpr 57.90 MiB -1 -1 0.44 23268 6 0.10 -1 -1 32592 -1 -1 28 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59288 10 2 186 188 1 46 40 8 8 64 clb auto 17.9 MiB 0.01 370 219 1196 185 951 60 57.9 MiB 0.01 0.00 3.46426 2.64808 -111.051 -2.64808 2.64808 0.00 0.000227528 0.000206718 0.00514212 0.00468684 -1 -1 -1 -1 190 4.41860 190 4.41860 181 461 16985 3541 80255.5 62421 276194. 4315.53 13 9480 40228 -1 2.65254 2.65254 -110.961 -2.65254 -0.0734 -0.0734 0.03 -1 -1 57.9 MiB 0.01 0.0133773 0.0120246 57.9 MiB -1 0.00 +k6_frac_N10_40nm.xml stereovision3.v common 1.31 vpr 59.16 MiB -1 -1 0.41 23148 5 0.11 -1 -1 32568 -1 -1 7 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60580 10 2 181 183 1 38 19 5 5 25 clb auto 19.7 MiB 0.03 159 121 469 107 323 39 59.2 MiB 0.01 0.00 2.03188 2.03188 -84.6958 -2.03188 2.03188 0.00 0.000227941 0.000207215 0.00601851 0.00558608 -1 -1 -1 -1 105 3.00000 54 1.54286 61 90 1611 507 485046 377258 99699.4 3987.98 6 2523 14238 -1 2.07226 2.07226 -86.1872 -2.07226 0 0 0.01 -1 -1 59.2 MiB 0.01 0.0138386 0.0128888 59.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt index 9a8744d436c..2f0425ccd8e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 32.55 vpr 978.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001924 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.50 371 490 69 397 24 978.4 MiB 0.08 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000745164 0.00064564 0.0121362 0.0109717 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.4 MiB 0.14 0.0524157 0.0489871 978.4 MiB -1 0.02 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml styr.blif common 22.04 vpr 979.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002912 10 10 168 178 1 65 30 11 8 88 io auto 953.3 MiB 0.33 530 402 720 97 571 52 979.4 MiB 0.06 0.00 6.8225 6.61671 -72.4654 -6.61671 6.61671 0.00 0.000312489 0.00027995 0.00825822 0.00768717 -1 -1 -1 -1 669 10.4531 198 3.09375 255 965 67200 31259 0 0 194014. 2204.70 14 11730 32605 -1 6.73871 6.73871 -74.3689 -6.73871 0 0 0.04 -1 -1 979.4 MiB 0.05 0.0249525 0.0231555 979.4 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt index 7b5437463d7..25a87198d21 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 5.51 vpr 77.59 MiB 0.04 8576 -1 -1 1 0.07 -1 -1 35240 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79456 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.13 1890 35427 11493 18934 5000 77.6 MiB 0.27 0.00 5.12303 -647.058 -5.12303 5.12303 0.48 0.00206617 0.00189672 0.14394 0.133207 -1 -1 -1 -1 64 3873 16 4.93594e+06 1.0962e+06 976140. 4980.31 2.20 0.636996 0.595296 31408 195022 -1 3500 9 851 887 209984 82943 4.57723 4.57723 -694.457 -4.57723 0 0 1.23909e+06 6321.90 0.09 0.15 0.39 -1 -1 0.09 0.0903946 0.0866517 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 8.46 odin 122.62 MiB 5.36 125568 -1 -1 1 0.05 -1 -1 32100 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77964 130 40 596 562 1 355 185 14 14 196 dsp_top auto 37.0 MiB 0.09 3418 1865 39635 13944 21044 4647 76.1 MiB 0.13 0.00 5.12303 5.12303 -651.76 -5.12303 5.12303 0.19 0.000866185 0.000806089 0.069875 0.0652099 -1 -1 -1 -1 82 3469 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.21 0.315755 0.291609 33448 250998 -1 3353 9 741 768 180939 69062 4.57723 4.57723 -669.54 -4.57723 0 0 1.53308e+06 7821.82 0.03 0.05 0.18 -1 -1 0.03 0.0246455 0.0233771 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt index 23cf7b0b85f..b6ed7b07205 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 14.85 vpr 81.40 MiB 0.10 11392 -1 -1 1 0.12 -1 -1 37676 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83352 130 40 1203 1030 1 586 196 14 14 196 dsp_top auto 41.3 MiB 0.63 2691 46285 14724 25599 5962 81.4 MiB 0.45 0.01 6.58999 -703.566 -6.58999 6.58999 0.48 0.00220042 0.00200207 0.214554 0.193316 -1 -1 -1 -1 108 5210 35 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 10.07 1.93637 1.74105 36552 325092 -1 4641 23 2669 2746 326887 113256 6.77766 6.77766 -770.287 -6.77766 0 0 1.93951e+06 9895.46 0.12 0.27 0.65 -1 -1 0.12 0.138318 0.125698 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 11.04 odin 218.25 MiB 6.64 223488 -1 -1 1 0.07 -1 -1 33976 -1 -1 23 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 81316 130 40 1203 1030 1 587 196 14 14 196 dsp_top auto 39.6 MiB 0.32 5039 2615 41733 12907 23223 5603 79.4 MiB 0.17 0.00 7.16349 6.55057 -693.511 -6.55057 6.55057 0.19 0.00100498 0.000913787 0.0833981 0.0763062 -1 -1 -1 -1 120 4838 28 4.93594e+06 1.40315e+06 1.69991e+06 8673.00 1.88 0.40623 0.365025 38028 369366 -1 4452 23 2538 2614 296097 92461 6.77726 6.77726 -734.869 -6.77726 0 0 2.14988e+06 10968.8 0.05 0.10 0.27 -1 -1 0.05 0.0620611 0.0571425 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt index 235e1da0107..1881b26da15 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.88 vpr 72.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74068 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.4 MiB 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00708147 0.00640458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 2.22 vpr 72.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73804 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.3 MiB 1.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00920908 0.00830291 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 0.97 vpr 70.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 130 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72308 130 150 1169 1319 1 885 365 12 12 144 clb auto 30.7 MiB 0.62 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00294981 0.00272321 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 0.95 vpr 70.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 130 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72368 130 150 1216 1366 1 925 374 12 12 144 clb auto 30.9 MiB 0.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00295932 0.00273669 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt index d3c7d61af84..b884d061731 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.36 vpr 66.46 MiB 0.08 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68060 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 425 2283 406 1804 73 66.5 MiB 0.05 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000768694 0.000638603 0.0252644 0.022728 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.5 MiB 0.08 0.0775573 0.0705898 66.5 MiB -1 0.01 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.76 vpr 69.14 MiB 0.09 10368 -1 -1 5 0.19 -1 -1 36576 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70804 11 30 313 321 2 115 55 7 7 49 clb auto 29.7 MiB 0.40 448 1927 352 1502 73 69.1 MiB 0.07 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000863635 0.000740182 0.0221309 0.0195205 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.05 -1 -1 69.1 MiB 0.06 0.0568064 0.051944 69.1 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.40 odin 166.88 MiB 2.47 170880 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67040 11 30 262 292 2 99 61 7 7 49 clb auto 25.4 MiB 0.04 688 437 2341 384 1888 69 65.5 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000377471 0.000327024 0.0100275 0.00887733 -1 -1 -1 -1 434 4.56842 177 1.86316 730 1655 64750 15779 1.07788e+06 1.07788e+06 207176. 4228.08 23 4440 29880 -1 2.44651 2.32748 -175.142 -2.44651 0 0 0.02 -1 -1 65.5 MiB 0.03 0.0315352 0.027637 65.5 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.59 odin 157.12 MiB 2.50 160896 -1 -1 5 0.11 -1 -1 33308 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69568 11 30 313 321 2 114 55 7 7 49 clb auto 28.7 MiB 0.18 671 455 1719 301 1356 62 67.9 MiB 0.02 0.00 2.73611 2.6413 -165.526 -2.6413 2.31106 0.00 0.000410886 0.000359843 0.0107195 0.00966653 -1 -1 -1 -1 571 5.28704 218 2.01852 192 380 9910 2908 1.07788e+06 754516 219490. 4479.39 12 5100 32136 -1 2.66069 2.29553 -166.559 -2.66069 0 0 0.02 -1 -1 67.9 MiB 0.02 0.0302329 0.0275299 67.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt index df63a32e433..300983f84f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.27 vpr 67.81 MiB 0.06 9984 -1 -1 3 0.40 -1 -1 39908 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.8 MiB 0.14 1080 1293 313 846 134 67.8 MiB 0.06 0.00 2.45187 -223.196 -2.45187 2.45187 0.31 0.000607122 0.000549979 0.00491114 0.00472929 -1 -1 -1 -1 34 2076 26 5.66058e+06 4.21279e+06 293002. 2034.74 1.92 0.386002 0.351306 12094 55633 -1 1662 10 540 720 43948 13958 2.71514 2.71514 -233.572 -2.71514 0 0 360780. 2505.42 0.02 0.06 0.08 -1 -1 0.02 0.0335019 0.0302667 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.81 odin 100.50 MiB 2.18 102912 -1 -1 3 0.19 -1 -1 34104 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67628 99 130 363 493 1 252 298 12 12 144 clb auto 26.8 MiB 0.07 1168 1026 1293 339 819 135 66.0 MiB 0.05 0.00 2.24785 2.1902 -216.85 -2.1902 2.1902 0.09 0.000548458 0.000511942 0.00340329 0.00328177 -1 -1 -1 -1 38 1909 17 5.66058e+06 4.21279e+06 319130. 2216.18 0.37 0.116514 0.106136 12522 62564 -1 1585 12 545 712 54323 17831 2.61371 2.61371 -231.046 -2.61371 0 0 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0185263 0.0173288 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt index c57ad9bdb40..1d55e8e0081 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 1.89 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.09 0.000707997 0.000614185 0.0204147 0.0180597 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.97 0.236366 0.209157 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.10 0.02 -1 -1 0.01 0.0335803 0.0304927 - k4_n4_v7_longline_bidir.xml styr.blif common 1.77 vpr 60.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61816 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.05 1219 4247 600 3483 164 60.4 MiB 0.05 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000681666 0.000592315 0.0189188 0.016758 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.80 0.256847 0.227018 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.10 0.03 -1 -1 0.02 0.0370258 0.033411 - k4_n4_v7_l1_bidir.xml styr.blif common 2.35 vpr 61.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62632 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1285 7613 1616 5547 450 61.2 MiB 0.12 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.000675324 0.000585254 0.0347554 0.0308708 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.17 0.183607 0.16336 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.13 0.02 -1 -1 0.01 0.0396264 0.0357171 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.49 vpr 60.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61772 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.05 1234 4643 666 3821 156 60.3 MiB 0.09 0.01 3.51175 -43.7413 -3.51175 3.51175 0.09 0.000766831 0.000671887 0.0247522 0.0222268 -1 -1 -1 -1 14 2053 42 2.43e+06 2.07e+06 -1 -1 2.23 0.282741 0.249953 3402 27531 -1 1991 28 1438 5059 778762 132220 26.9853 26.9853 -248.248 -26.9853 0 0 -1 -1 0.01 0.37 0.03 -1 -1 0.01 0.0480187 0.0429407 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml styr.blif common 0.97 vpr 58.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60368 10 10 253 263 1 171 92 11 11 121 clb auto 19.7 MiB 0.03 1829 1341 4439 719 3525 195 59.0 MiB 0.03 0.00 8.75156 5.95188 -76.2362 -5.95188 5.95188 0.03 0.000362225 0.000326331 0.00992626 0.00907431 -1 -1 -1 -1 14 2179 38 2.43e+06 2.16e+06 -1 -1 0.45 0.0943506 0.081458 3402 27531 -1 1923 17 1033 3494 176707 22465 7.58177 7.58177 -95.383 -7.58177 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0158882 0.0142757 +k4_n4_v7_longline_bidir.xml styr.blif common 0.91 vpr 59.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60464 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1318 3611 426 3020 165 59.0 MiB 0.02 0.00 5.19817 4.47516 -54.2373 -4.47516 4.47516 0.04 0.000357538 0.00032632 0.00871064 0.00799197 -1 -1 -1 -1 17 2528 41 2.43e+06 2.16e+06 -1 -1 0.35 0.0835775 0.0724263 3202 31699 -1 2252 25 1472 4968 313575 40767 9.40236 9.40236 -107.704 -9.40236 0 0 -1 -1 0.01 0.06 0.01 -1 -1 0.01 0.0211626 0.0187929 +k4_n4_v7_l1_bidir.xml styr.blif common 1.04 vpr 59.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60436 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1340 8579 1857 6361 361 59.0 MiB 0.04 0.00 11.3865 6.30908 -81.1511 -6.30908 6.30908 0.04 0.000371081 0.000335053 0.0176792 0.0161598 -1 -1 -1 -1 11 1565 28 2.43e+06 2.16e+06 -1 -1 0.44 0.0827522 0.0722935 4842 26035 -1 1365 23 1309 5061 314893 55846 8.55913 8.55913 -101.511 -8.55913 0 0 -1 -1 0.00 0.06 0.01 -1 -1 0.00 0.0191151 0.0170035 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.24 vpr 59.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61052 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1326 4025 528 3322 175 59.6 MiB 0.02 0.00 4.50889 3.47884 -44.786 -3.47884 3.47884 0.03 0.000371134 0.000327233 0.00920502 0.00841011 -1 -1 -1 -1 16 2193 28 2.43e+06 2.16e+06 -1 -1 0.64 0.0871949 0.0752766 3522 30407 -1 2061 19 1236 4213 766518 139225 14.4125 14.4125 -146.898 -14.4125 0 0 -1 -1 0.00 0.11 0.01 -1 -1 0.00 0.0176916 0.0159417 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt index 0bd2ba5a636..5397c667c6c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.92 vpr 66.34 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36540 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000749649 0.00064239 0.0161237 0.0140852 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.28 0.147245 0.127953 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.08 0.01 -1 -1 0.00 0.047308 0.0404063 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.40 vpr 66.13 MiB 0.07 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67716 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.08 427 1815 293 1474 48 66.1 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000744837 0.000636456 0.0185703 0.0149662 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.64 0.298818 0.25277 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.10 0.01 -1 -1 0.00 0.0500747 0.044978 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 3.86 odin 167.25 MiB 2.53 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67272 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 430 2821 451 2299 71 65.7 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000428515 0.000373651 0.0118289 0.0104043 -1 -1 -1 -1 18 673 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.18 0.0738407 0.0618149 2616 8308 -1 591 24 845 2121 68310 27246 2.65985 2.3922 -190.754 -2.65985 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0224978 0.0195692 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 4.06 odin 166.88 MiB 2.52 170880 -1 -1 4 0.12 -1 -1 33096 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 430 2821 451 2299 71 65.7 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.00040163 0.000347773 0.0117465 0.0103215 -1 -1 -1 -1 18 673 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.40 0.133348 0.110447 2616 8308 -1 591 24 845 2121 68310 27246 2.65985 2.3922 -190.754 -2.65985 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0230397 0.0200505 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt index 7d75ebf7e22..a646b3f38b3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.32 vpr 67.44 MiB 0.07 9856 -1 -1 3 0.36 -1 -1 39552 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69060 99 130 363 493 1 255 305 13 13 169 clb auto 27.9 MiB 0.11 817 73151 23083 37131 12937 67.4 MiB 0.30 0.01 2.36834 -235.63 -2.36834 2.36834 0.29 0.00233393 0.00223993 0.0738859 0.066584 -1 -1 -1 -1 32 1352 17 6.63067e+06 4.59005e+06 323148. 1912.12 0.52 0.196726 0.178694 11612 59521 -1 1138 16 719 1086 65347 22389 2.48507 2.48507 -238.178 -2.48507 0 0 396943. 2348.77 0.02 0.13 0.12 -1 -1 0.02 0.0517727 0.0472555 - k6_N10_mem32K_40nm.xml diffeq1.v common 10.12 vpr 70.60 MiB 0.03 9856 -1 -1 15 0.44 -1 -1 38380 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72292 162 96 999 932 1 661 323 16 16 256 mult_36 auto 31.3 MiB 0.38 5531 95525 26953 60139 8433 70.6 MiB 0.91 0.01 21.9361 -1891.35 -21.9361 21.9361 0.47 0.00396915 0.00366377 0.403824 0.374905 -1 -1 -1 -1 44 11294 43 1.21132e+07 5.21364e+06 665287. 2598.78 5.71 1.78116 1.66467 20656 131250 -1 8771 24 4066 8799 1047369 299882 22.5944 22.5944 -1935.68 -22.5944 0 0 864808. 3378.16 0.04 0.50 0.16 -1 -1 0.04 0.234899 0.221057 - k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB 0.01 6912 -1 -1 1 0.02 -1 -1 32916 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0231e-05 6.013e-06 7.2755e-05 4.8573e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00153872 0.00147005 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109157 0.00106485 - k6_N10_mem32K_40nm.xml single_ff.v common 0.49 vpr 65.16 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33280 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 5 1 3 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5008e-05 1.0331e-05 0.000105161 7.8059e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0016194 0.0015365 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00112886 0.00109032 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.85 vpr 67.48 MiB 0.06 9856 -1 -1 3 0.36 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69100 99 130 363 493 1 255 305 19 19 361 o auto 27.9 MiB 0.10 1043 75203 18688 40447 16068 67.5 MiB 0.27 0.00 2.5827 -243.865 -2.5827 2.5827 1.92 0.000939884 0.00084584 0.0725048 0.0652395 -1 -1 -1 -1 36 1432 20 1.79173e+07 4.59005e+06 833707. 2309.44 1.36 0.302543 0.27272 24998 161561 -1 1342 23 802 1298 88966 26229 2.93129 2.93129 -249.701 -2.93129 0 0 1.02328e+06 2834.56 0.07 0.10 0.15 -1 -1 0.07 0.0554021 0.0511266 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 12.40 vpr 79.29 MiB 0.04 9856 -1 -1 15 0.45 -1 -1 38032 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81188 162 96 999 932 1 661 323 24 24 576 i auto 31.0 MiB 0.28 7114 95525 25526 57948 12051 79.3 MiB 0.94 0.01 21.4854 -1914.4 -21.4854 21.4854 3.35 0.00392701 0.00363416 0.415599 0.386608 -1 -1 -1 -1 32 12804 30 3.08128e+07 5.21364e+06 1.24505e+06 2161.54 3.94 1.18592 1.11276 39974 242477 -1 10817 26 4455 9936 1378660 349639 22.5193 22.5193 -2054.22 -22.5193 0 0 1.54255e+06 2678.04 0.12 0.65 0.37 -1 -1 0.12 0.246186 0.231211 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.47 vpr 65.28 MiB 0.02 6784 -1 -1 1 0.02 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66848 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1306e-05 5.604e-06 7.2139e-05 4.6493e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00155951 0.00148904 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.0014785 0.00144447 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.49 vpr 65.16 MiB 0.02 7040 -1 -1 1 0.02 -1 -1 33288 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 4 4 16 i auto 26.9 MiB 0.00 7 9 0 2 7 65.2 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.6222e-05 1.0832e-05 0.00010458 7.8535e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00166008 0.00157112 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00159511 0.00154443 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.73 odin 99.75 MiB 2.11 102144 -1 -1 3 0.19 -1 -1 34096 -1 -1 75 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67636 99 130 363 493 1 253 305 13 13 169 clb auto 26.3 MiB 0.04 2273 844 74177 21541 39695 12941 66.1 MiB 0.12 0.00 2.6333 2.22949 -229.909 -2.22949 2.22949 0.10 0.000545037 0.000509709 0.0421815 0.0394416 -1 -1 -1 -1 32 1393 19 6.63067e+06 4.59005e+06 323148. 1912.12 0.22 0.112186 0.103342 11612 59521 -1 1193 22 721 1096 62496 20405 2.52707 2.52707 -230.152 -2.52707 0 0 396943. 2348.77 0.01 0.04 0.03 -1 -1 0.01 0.0263727 0.0242585 +k6_N10_mem32K_40nm.xml diffeq1.v common 5.78 odin 87.00 MiB 1.78 89088 -1 -1 15 0.28 -1 -1 34656 -1 -1 62 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71816 162 96 999 932 1 663 325 16 16 256 mult_36 auto 30.1 MiB 0.14 9594 5574 90802 23938 58756 8108 70.1 MiB 0.35 0.01 24.8422 21.1611 -1910.27 -21.1611 21.1611 0.17 0.0016689 0.00156792 0.146815 0.137632 -1 -1 -1 -1 40 11068 31 1.21132e+07 5.32143e+06 612675. 2393.26 1.71 0.542302 0.504589 19892 118481 -1 8993 24 3753 8101 1142271 339586 22.091 22.091 -1952.75 -22.091 0 0 771607. 3014.09 0.02 0.24 0.06 -1 -1 0.02 0.0989663 0.0931558 +k6_N10_mem32K_40nm.xml single_wire.v common 1.85 vpr 63.42 MiB 1.35 62208 -1 -1 1 0.02 -1 -1 29676 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64940 1 1 1 2 0 1 2 3 3 9 -1 auto 25.2 MiB 0.00 2 2 3 0 3 0 63.4 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.563e-06 3.5e-06 5.6873e-05 3.8119e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000892945 0.000838657 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000818035 0.000790317 +k6_N10_mem32K_40nm.xml single_ff.v common 1.65 vpr 63.43 MiB 1.13 62208 -1 -1 1 0.02 -1 -1 29980 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64952 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 6 6 9 5 1 3 63.4 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.457e-06 6.162e-06 7.5674e-05 5.5802e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000948394 0.000881804 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000868136 0.00083058 +k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 4.88 odin 100.12 MiB 2.18 102528 -1 -1 3 0.21 -1 -1 34188 -1 -1 75 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67452 99 130 363 493 1 253 305 19 19 361 o auto 26.1 MiB 0.04 3198 975 75203 18286 41793 15124 65.9 MiB 0.12 0.00 3.0814 2.23502 -240.202 -2.23502 2.23502 0.64 0.00056767 0.000530953 0.0438763 0.0412509 -1 -1 -1 -1 36 1305 22 1.79173e+07 4.59005e+06 833707. 2309.44 0.55 0.162802 0.14941 24998 161561 -1 1270 26 731 1078 66382 19258 2.55328 2.55328 -255.132 -2.55328 0 0 1.02328e+06 2834.56 0.03 0.05 0.08 -1 -1 0.03 0.0294887 0.0270957 +k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 7.03 odin 86.62 MiB 1.78 88704 -1 -1 15 0.28 -1 -1 34628 -1 -1 62 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78268 162 96 999 932 1 663 325 24 24 576 i auto 29.9 MiB 0.14 13908 6960 97504 27766 60997 8741 76.4 MiB 0.37 0.01 27.051 21.3253 -1909.99 -21.3253 21.3253 1.08 0.00180313 0.00169217 0.157695 0.147632 -1 -1 -1 -1 44 10768 25 3.08128e+07 5.32143e+06 1.60659e+06 2789.21 1.63 0.547726 0.510008 44574 325925 -1 10016 19 3329 7120 1011052 264242 21.9724 21.9724 -1931.12 -21.9724 0 0 2.07854e+06 3608.58 0.06 0.19 0.17 -1 -1 0.06 0.0798925 0.0754695 +k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 1.63 vpr 63.87 MiB 1.12 62208 -1 -1 1 0.02 -1 -1 29672 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65400 1 1 1 2 0 1 2 4 4 16 i auto 25.6 MiB 0.00 3 3 3 0 0 3 63.9 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.534e-06 3.573e-06 5.5302e-05 3.705e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.000882082 0.000817487 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.000822123 0.000791877 +k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 1.69 vpr 63.77 MiB 1.15 62208 -1 -1 1 0.02 -1 -1 29988 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65296 2 1 3 4 1 3 4 4 4 16 i auto 24.9 MiB 0.00 7 7 9 0 2 7 63.8 MiB 0.00 0.00 0.55247 0.55247 -0.955943 -0.55247 0.55247 0.00 9.557e-06 6.18e-06 8.3767e-05 6.4375e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.00 0.00096046 0.000887599 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.000877327 0.000830252 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt index a4f4578b4e4..c0c4d5fb80e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.22 vpr 66.21 MiB 0.06 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67796 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 485 3687 781 2795 111 66.2 MiB 0.01 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 734 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.65 0.239065 0.204044 2616 8308 -1 583 23 761 1801 50764 16568 2.52485 2.36559 -186.102 -2.52485 0 0 59124.6 1206.62 0.00 0.07 0.01 -1 -1 0.00 0.0486043 0.0430292 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 4.05 odin 167.25 MiB 2.81 171264 -1 -1 4 0.12 -1 -1 33076 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 466 3421 681 2621 119 65.7 MiB 0.00 0.00 -1 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 697 29 1.07788e+06 1.07788e+06 45686.6 932.380 0.15 0.0585359 0.0490389 2616 8308 -1 557 36 1075 2921 72281 22541 2.63547 2.45943 -188.872 -2.63547 0 0 59124.6 1206.62 0.00 0.05 0.00 -1 -1 0.00 0.028993 0.0249322 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt index d3b62c629ad..7b3feedaa81 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 14.36 vpr 58.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60212 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.8 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.10 4.6187e-05 3.8396e-05 0.000395937 0.000323618 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00202221 0.00179313 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00173217 0.0016394 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 16.94 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.28 4.6086e-05 3.7994e-05 0.000373556 0.000302701 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00235088 0.00212378 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00221042 0.00197359 - sub_tiles.xml sub_tiles.blif common_--check_route_off 16.20 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60476 6 7 19 26 0 19 26 3 3 9 -1 auto 20.7 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 14.72 4.2295e-05 3.5105e-05 0.000363474 0.000296118 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00229484 0.00207762 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00174454 0.00165562 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common_--check_route_full 4.36 vpr 57.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58904 6 7 19 26 0 19 26 3 3 9 -1 auto 18.7 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.68 2.1665e-05 1.7518e-05 0.000208626 0.000167637 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00147674 0.00134179 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.00098867 0.000928688 +sub_tiles.xml sub_tiles.blif common_--check_route_quick 4.36 vpr 57.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59084 6 7 19 26 0 19 26 3 3 9 -1 auto 18.9 MiB 0.00 51 51 216 43 63 110 57.7 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.66 2.2092e-05 1.7777e-05 0.00021225 0.000170395 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00147126 0.00133195 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00102901 0.000969282 +sub_tiles.xml sub_tiles.blif common_--check_route_off 4.38 vpr 57.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58908 6 7 19 26 0 19 26 3 3 9 -1 auto 18.9 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.68 2.1964e-05 1.7853e-05 0.000215424 0.000174304 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00138082 0.00125409 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.00102124 0.000958615 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt index 7b6b29fbf31..a0b1d2547f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.50 vpr 66.18 MiB 0.01 6912 -1 -1 1 0.03 -1 -1 33524 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67768 9 8 71 66 1 35 20 5 5 25 clb auto 27.2 MiB 0.61 102 641 211 420 10 66.2 MiB 0.01 0.00 2.52843 -27.3721 -2.52843 2.52843 0.02 0.000162932 0.000142933 0.00487777 0.00439017 -1 -1 -1 -1 32 152 12 151211 75605.7 43252.0 1730.08 0.15 0.05219 0.0443549 2004 6761 -1 170 13 131 173 5906 3259 2.68643 2.68643 -34.5837 -2.68643 0 0 52324.5 2092.98 0.00 0.01 0.01 -1 -1 0.00 0.00766663 0.00704697 14 17 16 6 0 0 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.42 vpr 67.07 MiB 0.01 6912 -1 -1 1 0.04 -1 -1 33628 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 19 18 299 240 1 146 45 6 6 36 clb auto 27.6 MiB 4.94 477 2365 468 1860 37 67.1 MiB 0.04 0.00 4.92757 -99.6523 -4.92757 4.92757 0.05 0.000316619 0.0002807 0.0196432 0.0179661 -1 -1 -1 -1 54 1052 25 403230 201615 113905. 3164.04 0.53 0.17427 0.152991 4050 20995 -1 792 24 850 1349 48852 19559 4.89358 4.89358 -108.576 -4.89358 0 0 146644. 4073.44 0.00 0.05 0.03 -1 -1 0.00 0.0285954 0.0259387 62 82 85 13 0 0 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 2.21 vpr 64.45 MiB 1.16 63360 -1 -1 1 0.02 -1 -1 30140 -1 -1 3 9 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 9 8 71 66 1 36 20 5 5 25 clb auto 25.1 MiB 0.31 137 104 641 234 396 11 64.4 MiB 0.01 0.00 2.52843 2.52843 -27.3563 -2.52843 2.52843 0.01 8.3886e-05 7.5678e-05 0.00287988 0.00265606 -1 -1 -1 -1 36 198 14 151211 75605.7 46719.2 1868.77 0.06 0.0208895 0.0176785 2052 7582 -1 134 10 105 135 3075 1640 2.65565 2.65565 -30.2407 -2.65565 0 0 57775.2 2311.01 0.00 0.01 0.00 -1 -1 0.00 0.00421623 0.00386847 14 17 16 6 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.88 vpr 65.83 MiB 1.29 66048 -1 -1 1 0.03 -1 -1 30508 -1 -1 8 19 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67412 19 18 299 240 1 146 45 6 6 36 clb auto 26.5 MiB 2.57 653 478 2685 571 2068 46 65.8 MiB 0.02 0.00 4.89372 4.92757 -99.729 -4.92757 4.92757 0.02 0.000299081 0.00027449 0.0126207 0.0117249 -1 -1 -1 -1 54 1009 23 403230 201615 113905. 3164.04 0.18 0.0769279 0.0673934 4050 20995 -1 757 20 679 1069 35690 14737 4.92407 4.92407 -104.302 -4.92407 0 0 146644. 4073.44 0.00 0.03 0.01 -1 -1 0.00 0.0173043 0.0158511 62 82 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt index 82e16e68c58..545c792005d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.35 vpr 59.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61244 1 4 28 32 2 10 9 4 4 16 clb auto 21.2 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9876e-05 6.8917e-05 0.000564474 0.000511898 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00933145 0.00790294 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0020437 0.00190467 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.33 vpr 60.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61444 1 4 28 32 2 10 9 4 4 16 clb auto 21.5 MiB 0.01 21 27 10 10 7 60.0 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 9.3379e-05 8.2596e-05 0.000566541 0.000512464 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00867291 0.00731794 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00253268 0.00233063 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.35 vpr 59.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61264 1 4 28 32 2 10 9 4 4 16 clb auto 21.4 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.8562e-05 6.7163e-05 0.000561289 0.000507136 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00963983 0.0081025 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00296634 0.00273132 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.30 vpr 58.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59868 1 4 28 32 2 10 9 4 4 16 clb auto 20.0 MiB 0.01 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.1534e-05 3.5999e-05 0.000369868 0.000335443 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00499499 0.00420054 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0016791 0.00155334 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.31 vpr 58.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59872 1 4 28 32 2 10 9 4 4 16 clb auto 19.8 MiB 0.00 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.9315e-05 4.3528e-05 0.00035389 0.000323547 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0051196 0.00430647 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00175992 0.00162646 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.30 vpr 58.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59868 1 4 28 32 2 10 9 4 4 16 clb auto 20.0 MiB 0.00 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.6269e-05 3.5157e-05 0.000348083 0.000313527 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00483693 0.00405856 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0016602 0.0015331 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt index 17671e26cfa..6445c2b0e4d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.35 vpr 59.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61088 2 2 22 24 2 4 6 4 4 16 clb auto 21.2 MiB 0.01 8 15 5 7 3 59.7 MiB 0.00 0.00 1.297 0 0 1.297 0.01 6.7393e-05 5.6956e-05 0.000402551 0.000351966 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00291274 0.00268287 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00264613 0.00228889 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.29 vpr 58.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59568 2 2 22 24 2 4 6 4 4 16 clb auto 19.8 MiB 0.00 8 8 15 5 7 3 58.2 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.00 3.2501e-05 2.7243e-05 0.000238975 0.000209911 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.00 0.00178494 0.00164738 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00133399 0.0012414 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt index 55f3e1dd3ba..b7e6584d848 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt index c54c9279c53..cf139e11ffa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33484 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 3 5 1 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.4271e-05 9.019e-06 0.000105429 7.7044e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00167801 0.00157995 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33216 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 9 9 3 3 3 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.5585e-05 1.0104e-05 0.000105029 7.6023e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.00153942 0.00144868 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.33 abc 63.01 MiB 0.24 59520 -1 -1 2 1.56 -1 -1 64520 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63024 5 156 191 347 1 163 316 15 15 225 clb auto 22.0 MiB 0.04 29 82016 58904 3157 19955 61.5 MiB 0.15 0.00 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000408132 0.000370067 0.0341355 0.031078 -1 -1 -1 -1 -1 32 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0428942 0.0391583 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.51 abc 63.14 MiB 0.34 59776 -1 -1 2 1.51 -1 -1 64652 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63260 5 156 191 347 1 163 316 15 15 225 clb auto 22.2 MiB 0.02 41 76641 54775 3226 18640 61.8 MiB 0.14 0.00 1.49775 -14.6172 -1.49775 1.49775 0.00 0.000395712 0.000358237 0.0299271 0.0269791 -1 -1 -1 -1 -1 63 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0377601 0.0341837 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.33 vpr 65.29 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33412 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 2 1 3 4 1 3 4 3 3 9 -1 auto 26.8 MiB 0.00 6 9 3 5 1 65.3 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5615e-05 1.0606e-05 0.000109326 8.0241e-05 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.00165784 0.00156601 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.25 vpr 65.38 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33208 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 2 1 3 4 1 3 4 3 3 9 -1 auto 27.1 MiB 0.00 9 9 3 3 3 65.4 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.6671e-05 1.1297e-05 0.000111494 8.1284e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00178932 0.0017001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.46 vpr 71.98 MiB 0.15 16896 -1 -1 2 0.16 -1 -1 37600 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73704 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.58 8394 210108 78030 120895 11183 72.0 MiB 1.33 0.02 3.90475 -4339.03 -3.90475 3.90475 0.00 0.00537924 0.00456001 0.565099 0.476317 -1 -1 -1 -1 -1 12247 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.38 0.731735 0.628685 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.57 vpr 72.21 MiB 0.16 17152 -1 -1 2 0.16 -1 -1 37596 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73948 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.52 9639 203757 70988 121974 10795 72.2 MiB 1.36 0.02 4.05379 -3834.49 -4.05379 4.05379 0.00 0.00624609 0.00547423 0.627089 0.535493 -1 -1 -1 -1 -1 13797 11 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.48 0.824983 0.713955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.40 vpr 58.26 MiB 0.08 45312 -1 -1 1 0.02 -1 -1 29944 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59656 2 1 3 4 1 3 4 3 3 9 -1 auto 19.5 MiB 0.00 6 6 9 3 5 1 58.3 MiB 0.00 0.00 0.55447 0.55447 -0.91031 -0.55447 0.55447 0.00 9.136e-06 5.869e-06 7.1791e-05 5.3179e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00118302 0.00110755 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.41 vpr 58.25 MiB 0.08 45312 -1 -1 1 0.02 -1 -1 29640 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59652 2 1 3 4 1 3 4 3 3 9 -1 auto 20.0 MiB 0.00 9 9 9 3 3 3 58.3 MiB 0.00 0.00 0.56425 0.48631 -0.91031 -0.48631 0.48631 0.00 9.58e-06 5.86e-06 7.4441e-05 5.4651e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.001162 0.00108609 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 10.50 odin 789.80 MiB 7.89 808752 -1 -1 2 0.86 -1 -1 50628 -1 -1 155 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62228 5 156 191 347 1 163 316 15 15 225 clb auto 21.0 MiB 0.02 118 29 82016 59012 3139 19865 60.8 MiB 0.07 0.00 1.99335 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000220093 0.000206488 0.0175726 0.0164762 -1 -1 -1 -1 -1 32 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0225735 0.0211146 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 10.56 odin 789.05 MiB 7.83 807988 -1 -1 2 0.87 -1 -1 50628 -1 -1 155 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62228 5 156 191 347 1 163 316 15 15 225 clb auto 21.0 MiB 0.02 126 33 76641 54911 3193 18537 60.8 MiB 0.06 0.00 1.66097 1.47673 -14.6018 -1.47673 1.47673 0.00 0.000216751 0.000203309 0.016441 0.0153792 -1 -1 -1 -1 -1 47 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0210131 0.0196249 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 1.51 vpr 63.88 MiB 1.14 62208 -1 -1 1 0.02 -1 -1 29976 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 2 1 3 4 1 3 4 3 3 9 -1 auto 25.3 MiB 0.00 6 6 9 3 5 1 63.9 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.181e-06 5.927e-06 7.6264e-05 5.5982e-05 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.00095459 0.000884928 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 1.51 vpr 63.88 MiB 1.14 62208 -1 -1 1 0.02 -1 -1 30008 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 2 1 3 4 1 3 4 3 3 9 -1 auto 25.6 MiB 0.00 9 9 9 3 3 3 63.9 MiB 0.00 0.00 0.56425 0.48631 -0.90831 -0.48631 0.48631 0.00 1.0512e-05 6.419e-06 7.8418e-05 5.706e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.000974856 0.000905471 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 7.23 odin 619.65 MiB 5.01 634520 -1 -1 2 0.08 -1 -1 35196 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73164 311 156 972 1128 1 953 525 28 28 784 memory auto 32.0 MiB 0.26 18730 8256 201640 71067 119264 11309 71.4 MiB 0.55 0.01 4.8206 3.69209 -4283.73 -3.69209 3.69209 0.00 0.00248503 0.00221098 0.252544 0.224143 -1 -1 -1 -1 -1 12173 14 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.19 0.35082 0.314831 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 7.11 odin 620.36 MiB 4.85 635252 -1 -1 2 0.08 -1 -1 35200 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73164 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.26 19537 8661 201640 66024 123894 11722 71.4 MiB 0.54 0.01 4.71974 3.76482 -3710.64 -3.76482 3.76482 0.00 0.00245698 0.00217799 0.245651 0.216211 -1 -1 -1 -1 -1 12504 13 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.20 0.340896 0.304187 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt index 270c7d97d80..a7e3857a45b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.68 vpr 66.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 8 4 25 28 5 19 19 6 6 36 clb auto 27.9 MiB 0.43 51 194 39 119 36 66.2 MiB 0.00 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 6.5511e-05 4.9348e-05 0.000956967 0.000802791 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.2 MiB 0.00 0.00312006 0.00280809 66.2 MiB -1 0.01 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.33 vpr 64.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 8 4 25 28 5 19 19 6 6 36 clb auto 26.0 MiB 0.16 73 51 194 39 119 36 64.7 MiB 0.00 0.00 1.51369 1.41795 -5.85435 -1.41795 0.545 0.00 3.3733e-05 2.5958e-05 0.000434238 0.000352095 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 673 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.00 -1 -1 64.7 MiB 0.00 0.0016542 0.00148021 64.7 MiB -1 0.00 +k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.04 vpr 18.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 18960 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt index a8229d3cc5f..fe67fdd70e7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.39 vpr 65.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 -1 2 2 4 0 2 4 4 4 16 clb auto 27.0 MiB 0.00 0 9 0 2 7 65.3 MiB 0.00 0.00 nan 0 0 nan 0.01 1.324e-05 7.342e-06 8.3458e-05 5.501e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00154065 0.00146112 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00148898 0.00145049 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.31 vpr 63.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64696 -1 2 2 4 0 2 4 4 4 16 clb auto 24.6 MiB 0.00 0 0 9 0 2 7 63.2 MiB 0.00 0.00 nan nan 0 0 nan 0.00 8.207e-06 4.305e-06 6.3919e-05 4.1976e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.000882294 0.00082251 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.000867933 0.000836225 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt index dedf8b436ab..2f44136a1bd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 22.04 vpr 87.12 MiB 0.37 32000 -1 -1 3 1.37 -1 -1 43832 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89216 214 305 2963 2869 1 1444 650 25 25 625 -1 25x25 45.9 MiB 3.49 12196 290492 92452 176193 21847 87.1 MiB 1.73 0.04 4.70145 -2687.49 -4.70145 4.70145 0.77 0.009062 0.00821446 0.664489 0.598586 -1 -1 -1 -1 50 24072 42 3.19446e+07 9.79696e+06 2.03477e+06 3255.63 9.38 3.04543 2.74886 65619 409230 -1 20090 15 5518 12429 1427524 369655 4.84691 4.84691 -2936.69 -4.84691 0 0 2.61863e+06 4189.80 0.13 0.72 0.40 -1 -1 0.13 0.405468 0.382168 - column_io.xml raygentop.v common 30.34 vpr 87.28 MiB 0.43 32000 -1 -1 3 1.83 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89376 214 305 2963 2869 1 1444 650 25 25 625 io auto 46.2 MiB 3.96 11325 239840 77339 132443 30058 87.3 MiB 2.09 0.03 4.40936 -2625.55 -4.40936 4.40936 1.20 0.0090281 0.0081843 0.836879 0.749323 -1 -1 -1 -1 48 24462 25 2.82259e+07 9.79696e+06 1.82181e+06 2914.90 14.53 3.9566 3.54503 57888 355703 -1 20518 17 5996 13599 1716937 426068 4.7409 4.7409 -2939.5 -4.7409 0 0 2.33544e+06 3736.71 0.17 0.92 0.52 -1 -1 0.17 0.442866 0.410518 - multiwidth_blocks.xml raygentop.v common 23.34 vpr 87.11 MiB 0.46 32000 -1 -1 3 1.66 -1 -1 43932 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89196 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.70 10825 234212 78128 135288 20796 87.1 MiB 2.20 0.03 4.45499 -2656.92 -4.45499 4.45499 0.58 0.00914429 0.00826611 0.84541 0.761865 -1 -1 -1 -1 60 22314 37 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 8.15 3.5171 3.1499 34801 210837 -1 18718 16 6372 15066 2125910 636768 4.83864 4.83864 -2933.88 -4.83864 0 0 1.43369e+06 3971.44 0.09 1.02 0.34 -1 -1 0.09 0.423489 0.392785 - non_column.xml raygentop.v common 50.57 vpr 101.43 MiB 0.57 32128 -1 -1 3 1.64 -1 -1 43688 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103864 214 305 2963 2869 1 1444 650 33 33 1089 io auto 47.6 MiB 3.38 13852 267980 91761 149229 26990 98.5 MiB 2.25 0.03 4.81737 -2748.68 -4.81737 4.81737 2.25 0.00871345 0.00790536 0.883704 0.789723 -1 -1 -1 -1 46 27889 41 5.44432e+07 9.79696e+06 2.87196e+06 2637.24 31.91 4.82411 4.34906 94862 558952 -1 23226 19 7179 17098 2136481 565014 5.00295 5.00295 -3094.61 -5.00295 0 0 3.68462e+06 3383.49 0.29 1.11 0.95 -1 -1 0.29 0.492691 0.457205 - non_column_tall_aspect_ratio.xml raygentop.v common 41.13 vpr 107.46 MiB 0.65 32128 -1 -1 3 2.07 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110040 214 305 2963 2869 1 1444 650 23 46 1058 io auto 47.5 MiB 4.75 12924 225770 77986 115287 32497 98.0 MiB 1.99 0.02 4.68258 -2746.61 -4.68258 4.68258 2.17 0.00617553 0.00548634 0.751525 0.668955 -1 -1 -1 -1 50 24702 35 5.05849e+07 9.79696e+06 3.07243e+06 2904.00 20.48 4.80846 4.28853 95149 595581 -1 21346 17 5714 12751 1591343 424414 4.99583 4.99583 -3024.29 -4.99583 0 0 3.91054e+06 3696.17 0.39 1.00 1.06 -1 -1 0.39 0.462953 0.424532 - non_column_wide_aspect_ratio.xml raygentop.v common 40.58 vpr 101.39 MiB 0.68 32000 -1 -1 3 1.80 -1 -1 43696 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103820 214 305 2963 2869 1 1444 650 43 22 946 io auto 47.4 MiB 4.77 13982 276422 90498 164087 21837 95.1 MiB 2.48 0.03 4.68152 -2857.71 -4.68152 4.68152 2.06 0.0081203 0.0072676 0.94579 0.847056 -1 -1 -1 -1 50 26296 34 4.55909e+07 9.79696e+06 2.70028e+06 2854.41 19.21 5.11489 4.60481 84704 520009 -1 22872 18 6244 14195 1614167 427447 4.86473 4.86473 -3155.96 -4.86473 0 0 3.44953e+06 3646.44 0.30 1.16 1.00 -1 -1 0.30 0.501153 0.460019 - custom_sbloc.xml raygentop.v common 25.95 vpr 86.98 MiB 0.39 32000 -1 -1 3 1.58 -1 -1 43804 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89072 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.8 MiB 4.86 11696 245468 82823 140883 21762 87.0 MiB 2.50 0.04 4.53013 -2681.39 -4.53013 4.53013 0.61 0.00909806 0.00824441 0.931511 0.836258 -1 -1 -1 -1 62 22622 49 1.65001e+07 9.79696e+06 1.15634e+06 3203.15 10.71 4.10582 3.71488 35161 219597 -1 19429 17 6137 14618 1898349 506769 4.83748 4.83748 -2977.52 -4.83748 0 0 1.43990e+06 3988.64 0.05 0.92 0.41 -1 -1 0.05 0.399467 0.368878 - multiple_io_types.xml raygentop.v common 148.40 vpr 474.05 MiB 0.38 31872 -1 -1 3 1.46 -1 -1 43604 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 485424 214 305 2963 2869 1 1444 650 67 67 4489 io_left auto 46.2 MiB 5.36 26050 90698 4115 22648 63935 474.0 MiB 0.95 0.03 4.73667 -3563.79 -4.73667 4.73667 26.71 0.00792183 0.00702959 0.36772 0.321766 -1 -1 -1 -1 52 41451 45 2.48753e+08 9.79696e+06 1.27607e+07 2842.65 95.91 4.21007 3.80326 406473 2447650 -1 35770 21 7664 17455 3505363 891802 5.27395 5.27395 -3927.86 -5.27395 0 0 1.67786e+07 3737.72 0.99 1.06 2.69 -1 -1 0.99 0.318577 0.29589 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_grid.xml raygentop.v common 21.99 odin 1.52 GiB 10.24 1591816 -1 -1 3 0.83 -1 -1 40304 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88816 214 305 2963 2869 1 1441 650 25 25 625 -1 25x25 46.7 MiB 2.18 25402 12254 282050 88602 172367 21081 86.7 MiB 0.99 0.01 5.35403 4.41932 -2744.04 -4.41932 4.41932 0.47 0.00359037 0.00330877 0.395607 0.36374 -1 -1 -1 -1 48 24508 46 3.19446e+07 9.79696e+06 1.97188e+06 3155.02 3.94 1.43281 1.32186 64995 397836 -1 20934 15 5849 13951 1555077 389423 4.73647 4.73647 -2992.8 -4.73647 0 0 2.52596e+06 4041.53 0.08 0.37 0.21 -1 -1 0.08 0.18958 0.180028 +column_io.xml raygentop.v common 22.07 odin 1.52 GiB 10.19 1592260 -1 -1 3 0.83 -1 -1 39704 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88780 214 305 2963 2869 1 1441 650 25 25 625 io auto 46.3 MiB 2.17 25737 12044 245468 82104 140823 22541 86.7 MiB 0.89 0.01 5.96169 4.61982 -2725.2 -4.61982 4.61982 0.43 0.00356427 0.0032823 0.345995 0.317544 -1 -1 -1 -1 50 25560 24 2.82259e+07 9.79696e+06 1.88190e+06 3011.03 4.29 1.24128 1.1434 58512 365993 -1 21648 16 6081 14502 1687459 402383 4.72983 4.72983 -3044.61 -4.72983 0 0 2.41964e+06 3871.43 0.07 0.37 0.20 -1 -1 0.07 0.190288 0.180368 +multiwidth_blocks.xml raygentop.v common 21.54 odin 1.54 GiB 11.06 1614276 -1 -1 3 0.82 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88684 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.24 24028 11655 245468 82518 140645 22305 86.6 MiB 0.92 0.01 5.44642 4.52802 -2634.46 -4.52802 4.52802 0.21 0.00362024 0.00333019 0.352063 0.323303 -1 -1 -1 -1 60 24300 34 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 3.19 1.15359 1.06265 34801 210837 -1 20057 19 6400 15852 2295662 663397 4.80907 4.80907 -2946.21 -4.80907 0 0 1.43369e+06 3971.44 0.04 0.46 0.12 -1 -1 0.04 0.210626 0.199034 +non_column.xml raygentop.v common 47.75 odin 1.93 GiB 34.32 2023384 -1 -1 3 0.84 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 102400 214 305 2963 2869 1 1441 650 33 33 1089 io auto 47.7 MiB 2.23 35936 13660 262352 89101 152531 20720 98.5 MiB 0.94 0.01 6.8947 4.81737 -2806.8 -4.81737 4.81737 0.81 0.00362339 0.00334265 0.375896 0.345261 -1 -1 -1 -1 44 28243 27 5.44432e+07 9.79696e+06 2.74036e+06 2516.40 4.20 1.29667 1.19485 93774 543488 -1 22727 18 6328 15147 1605451 431979 4.86083 4.86083 -3079.84 -4.86083 0 0 3.56397e+06 3272.70 0.12 0.42 0.35 -1 -1 0.12 0.213772 0.202022 +non_column_tall_aspect_ratio.xml raygentop.v common 51.79 odin 1.93 GiB 39.18 2023256 -1 -1 3 0.83 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 102100 214 305 2963 2869 1 1441 650 23 46 1058 io auto 48.3 MiB 2.18 34433 12310 253910 86017 138818 29075 97.8 MiB 0.90 0.01 6.20818 4.74318 -2736.15 -4.74318 4.74318 0.80 0.0037281 0.0034064 0.359725 0.330304 -1 -1 -1 -1 52 22487 30 5.05849e+07 9.79696e+06 3.17293e+06 2998.99 3.53 1.28793 1.18725 97261 632982 -1 20510 16 5114 12053 1254371 346946 4.98587 4.98587 -2932.2 -4.98587 0 0 4.15960e+06 3931.57 0.12 0.33 0.42 -1 -1 0.12 0.187592 0.178023 +non_column_wide_aspect_ratio.xml raygentop.v common 50.76 odin 1.93 GiB 38.21 2023656 -1 -1 3 0.84 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 98352 214 305 2963 2869 1 1441 650 43 22 946 io auto 48.4 MiB 2.19 32195 14077 256724 83624 150449 22651 94.9 MiB 0.92 0.01 6.20333 4.54267 -2819.04 -4.54267 4.54267 0.70 0.00362855 0.00334198 0.36694 0.336882 -1 -1 -1 -1 42 27740 26 4.55909e+07 9.79696e+06 2.29725e+06 2428.38 3.62 1.2805 1.17964 79978 445530 -1 23661 21 6769 17034 1969793 532017 5.2623 5.2623 -3159.48 -5.2623 0 0 2.89121e+06 3056.25 0.09 0.47 0.28 -1 -1 0.09 0.224224 0.210925 +custom_sbloc.xml raygentop.v common 20.32 odin 1.51 GiB 10.16 1588048 -1 -1 3 0.82 -1 -1 39876 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88684 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.17 24028 12399 225770 74858 132033 18879 86.6 MiB 0.84 0.01 5.49355 4.39465 -2699.44 -4.39465 4.39465 0.21 0.00358021 0.0033004 0.322189 0.295867 -1 -1 -1 -1 60 25212 46 1.65001e+07 9.79696e+06 1.11685e+06 3093.75 3.18 1.03862 0.957059 34801 214773 -1 20923 16 6158 14594 1766703 471535 4.72432 4.72432 -3000.62 -4.72432 0 0 1.41014e+06 3906.19 0.03 0.37 0.13 -1 -1 0.03 0.187347 0.177768 +multiple_io_types.xml raygentop.v common 83.03 odin 1.54 GiB 10.26 1617740 -1 -1 3 0.83 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 484432 214 305 2963 2869 1 1441 650 67 67 4489 io_left auto 47.0 MiB 2.58 60956 25475 99140 5163 24781 69196 473.1 MiB 0.42 0.01 9.23589 4.60777 -3590.83 -4.60777 4.60777 11.18 0.00363304 0.00335274 0.163246 0.151042 -1 -1 -1 -1 38 47769 50 2.48753e+08 9.79696e+06 9.69761e+06 2160.30 49.39 1.31777 1.21279 366081 1845534 -1 38574 21 9565 21545 4981287 1328871 5.11017 5.11017 -4030.7 -5.11017 0 0 1.23326e+07 2747.29 0.44 0.96 1.12 -1 -1 0.44 0.226022 0.212296 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt index 032d95a320e..9ace93e2d4a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.66 MiB 0.06 9856 -1 -1 3 0.38 -1 -1 39496 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69284 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.23 0.00 2.23767 -220.613 -2.23767 2.23767 0.25 0.00122229 0.00116469 0.0742124 0.0677305 -1 -1 -1 -1 38 1639 12 5.66058e+06 4.21279e+06 328943. 2284.32 0.72 0.298961 0.271262 12522 66188 -1 1359 8 559 726 39339 13482 2.60043 2.60043 -237.265 -2.60043 0 0 418267. 2904.63 0.03 0.05 0.11 -1 -1 0.03 0.0322868 0.0303399 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.83 odin 100.50 MiB 2.19 102912 -1 -1 3 0.20 -1 -1 34096 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67960 99 130 363 493 1 252 298 12 12 144 clb auto 27.1 MiB 0.06 2018 885 69948 23010 34855 12083 66.4 MiB 0.11 0.00 2.57832 2.17528 -217.156 -2.17528 2.17528 0.09 0.000518599 0.000485055 0.0395951 0.0370221 -1 -1 -1 -1 40 1651 16 5.66058e+06 4.21279e+06 343462. 2385.15 0.31 0.146639 0.134351 12666 68385 -1 1603 9 533 666 46991 15253 2.5852 2.5852 -243.226 -2.5852 0 0 431791. 2998.55 0.01 0.02 0.04 -1 -1 0.01 0.015929 0.0149791 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt index a65248b7f30..0b0f4fd6adf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.43 vpr 64.82 MiB 0.05 9728 -1 -1 4 0.35 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66380 99 130 378 508 1 307 305 15 15 225 memory auto 25.3 MiB 0.06 1083 69047 24301 32567 12179 64.8 MiB 0.22 0.01 1.63577 -172.755 -1.63577 1.63577 0.00 0.00106212 0.000958102 0.0684136 0.0626923 -1 -1 -1 -1 1479 6.03673 767 3.13061 797 1865 235419 59319 1.16234e+06 375248 2.18283e+06 9701.45 16 48952 428016 -1 1.89463 1.89463 -188.601 -1.89463 -0.194976 -0.108352 0.68 -1 -1 64.8 MiB 0.11 0.107667 0.0986163 64.8 MiB -1 0.37 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 3.02 odin 94.88 MiB 1.73 97152 -1 -1 4 0.19 -1 -1 34104 -1 -1 80 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65108 99 130 378 508 1 307 310 15 15 225 memory auto 24.1 MiB 0.02 2811 1131 73670 26591 35126 11953 63.6 MiB 0.13 0.00 1.90937 1.69007 -171.787 -1.69007 1.69007 0.00 0.000578502 0.000540501 0.0429258 0.0401158 -1 -1 -1 -1 1607 6.55918 824 3.36327 788 1831 251903 61748 1.16234e+06 394748 2.18283e+06 9701.45 13 48952 428016 -1 1.87081 1.87081 -179.525 -1.87081 0 0 0.25 -1 -1 63.6 MiB 0.05 0.0608034 0.0566295 63.6 MiB -1 0.13 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt index c044fb36631..3a232fd7306 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 16.11 vpr 77.95 MiB 0.11 17024 -1 -1 2 0.10 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79820 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.7 MiB 0.63 9390 201609 69489 120331 11789 76.8 MiB 1.40 0.02 4.09817 -3462.19 -4.09817 4.09817 1.75 0.00638402 0.00561878 0.639416 0.550497 -1 -1 -1 -1 36 15662 18 4.25198e+07 9.89071e+06 1.97160e+06 2514.80 6.39 2.29245 2.04057 76483 392267 -1 14444 15 3124 3650 1031496 356426 4.24327 4.24327 -4339.34 -4.24327 -405.202 -1.29702 2.42825e+06 3097.26 0.20 1.56 0.59 -1 -1 0.20 0.278119 0.255639 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 12.94 vpr 83.35 MiB 0.18 17024 -1 -1 2 0.12 -1 -1 37644 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 85352 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.95 9390 201609 69489 120331 11789 83.4 MiB 0.81 0.01 4.09817 -3462.19 -4.09817 4.09817 1.06 0.00320533 0.00273182 0.351431 0.298654 -1 -1 -1 -1 36 15777 15 4.25198e+07 9.89071e+06 2.00618e+06 2558.90 4.74 1.57738 1.39763 76483 403003 -1 14373 10 2886 3379 762706 219312 4.3954 4.3954 -4595.94 -4.3954 -153.524 -1.32288 2.47848e+06 3161.33 0.22 1.20 0.50 -1 -1 0.22 0.199455 0.182428 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 20.64 vpr 78.23 MiB 0.14 17152 -1 -1 2 0.19 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80112 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.82 8956 201609 71778 118284 11547 78.2 MiB 1.41 0.02 3.73942 -3418.22 -3.73942 3.73942 1.71 0.00607733 0.00531502 0.647808 0.554869 -1 -1 -1 -1 36 16279 32 4.25198e+07 9.89071e+06 1.96702e+06 2508.96 9.86 2.33237 2.04039 76483 392433 -1 15198 14 2704 3167 1739681 1219090 5.58949 5.58949 -4496.49 -5.58949 -1697.62 -3.42836 2.42368e+06 3091.42 0.20 2.25 0.55 -1 -1 0.20 0.242641 0.222883 15 950 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 11.69 odin 621.34 MiB 5.06 636252 -1 -1 2 0.09 -1 -1 33636 -1 -1 31 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78136 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.6 MiB 0.45 18226 8928 193401 64117 117643 11641 75.2 MiB 0.54 0.01 4.81013 3.67388 -3454.23 -3.67388 3.67388 0.61 0.00248748 0.00222031 0.252503 0.224419 -1 -1 -1 -1 40 14778 13 4.25198e+07 9.89071e+06 2.15543e+06 2749.27 2.14 0.803025 0.722118 78831 435646 -1 13800 11 2663 3052 814928 278609 4.53842 4.53842 -4454.28 -4.53842 -315.655 -1.23838 2.69266e+06 3434.52 0.09 0.53 0.23 -1 -1 0.09 0.0944896 0.0883248 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 11.70 odin 620.13 MiB 5.29 635016 -1 -1 2 0.09 -1 -1 33880 -1 -1 31 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 84032 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.6 MiB 0.45 18226 8928 193401 64117 117643 11641 82.1 MiB 0.54 0.01 4.81013 3.67388 -3454.23 -3.67388 3.67388 0.63 0.00245028 0.00217565 0.247052 0.218738 -1 -1 -1 -1 40 14952 13 4.25198e+07 9.89071e+06 2.19000e+06 2793.37 1.99 0.790372 0.708952 78831 446382 -1 13786 11 2650 3108 720747 217033 4.26762 4.26762 -4440.59 -4.26762 -135.258 -1.2599 2.74289e+06 3498.59 0.09 0.50 0.23 -1 -1 0.09 0.089366 0.0832744 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 12.45 odin 621.68 MiB 4.90 636596 -1 -1 2 0.09 -1 -1 33592 -1 -1 31 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78660 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.6 MiB 0.45 18226 9203 197505 67339 118442 11724 75.7 MiB 0.57 0.01 4.81013 3.956 -3512.79 -3.956 3.956 0.61 0.00267688 0.0023959 0.268374 0.238465 -1 -1 -1 -1 36 16669 23 4.25198e+07 9.89071e+06 1.96702e+06 2508.96 2.91 0.894838 0.805745 76483 392433 -1 15397 11 2678 3089 1644949 1134599 5.57406 5.57406 -4431.03 -5.57406 -1496.8 -3.14941 2.42368e+06 3091.42 0.08 0.80 0.20 -1 -1 0.08 0.0890233 0.0831689 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt index 3e3e8b64dd5..1c24f6d46d7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.94 vpr 71.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73360 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.5 MiB 0.26 10472 141533 36950 100839 3744 71.6 MiB 1.41 0.02 7.46482 -1369.01 -7.46482 7.46482 0.60 0.00534435 0.00471558 0.398834 0.330633 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.25 2.1497 1.834 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.76 0.21 -1 -1 0.04 0.209487 0.18755 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 4.75 vpr 70.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72680 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.6 MiB 0.17 24088 10407 135291 36283 95683 3325 71.0 MiB 0.54 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.20 0.00206891 0.00176944 0.139634 0.121098 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.35 0.423683 0.369434 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.31 0.07 -1 -1 0.02 0.0912069 0.0826102 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt index 57a8e16dad9..d1aa0e8c66f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 26.42 vpr 86.55 MiB 0.39 29568 -1 -1 4 2.92 -1 -1 43300 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88632 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.3 MiB 1.96 10985 240245 81936 130873 27436 86.6 MiB 2.98 0.04 4.42447 -2617.73 -4.42447 4.42447 0.87 0.010731 0.00973575 1.17585 1.01795 -1 -1 -1 -1 78 21148 32 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 12.21 3.92596 3.45972 52874 439520 -1 19015 16 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.81 0.45 -1 -1 0.19 0.495649 0.459932 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 21.77 odin 1.01 GiB 10.88 1062996 -1 -1 4 1.59 -1 -1 40164 -1 -1 165 193 5 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88044 193 205 2863 2789 1 1378 568 20 20 400 memory auto 45.3 MiB 0.99 22943 10817 247423 86121 133897 27405 86.0 MiB 1.12 0.01 6.47551 5.02579 -2678.97 -5.02579 5.02579 0.30 0.0037987 0.00341071 0.425979 0.382513 -1 -1 -1 -1 76 21112 33 2.07112e+07 1.16325e+07 2.02110e+06 5052.76 3.90 1.38116 1.24918 52074 423490 -1 19105 16 5044 13854 1088699 242536 5.48145 5.48145 -2895.27 -5.48145 -14.3689 -0.360359 2.51807e+06 6295.18 0.07 0.33 0.25 -1 -1 0.07 0.209497 0.196991 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt index 7d3c0c996a1..9c6c4e1f901 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.83 vpr 67.63 MiB 0.09 9984 -1 -1 3 0.34 -1 -1 39772 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69252 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.20 804 66963 21682 33533 11748 67.6 MiB 0.34 0.01 2.23767 -220.613 -2.23767 2.23767 0.27 0.000902266 0.000807045 0.0650955 0.0583605 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 1.19 0.319458 0.291293 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.06 0.09 -1 -1 0.03 0.0273369 0.0256329 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.80 odin 100.12 MiB 2.12 102528 -1 -1 3 0.19 -1 -1 34340 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67576 99 130 363 493 1 252 298 12 12 144 clb auto 27.1 MiB 0.07 2018 885 69948 23010 34855 12083 66.0 MiB 0.12 0.00 2.57832 2.17528 -217.156 -2.17528 2.17528 0.09 0.000549765 0.000514583 0.0413233 0.0386326 -1 -1 -1 -1 40 1646 17 5.66058e+06 4.21279e+06 333335. 2314.82 0.32 0.152035 0.139133 12666 64609 -1 1625 10 525 650 46110 15051 2.57635 2.57635 -244.199 -2.57635 0 0 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0172408 0.0161803 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index ceb027e03e3..56c59c8279b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 198.12 vpr 257.14 MiB 2.00 126464 -1 -1 5 139.65 -1 -1 78708 -1 -1 1337 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 263312 157 197 21024 21221 1 6369 1691 39 39 1521 clb auto 124.7 MiB 6.38 48812 948271 327778 599083 21410 257.1 MiB 9.39 0.13 3.8487 -15314.7 -3.8487 3.8487 8.33 0.0426525 0.0388129 3.00817 2.44576 -1 -1 -1 -1 38 60857 30 2.4642e+07 2.4066e+07 4.29790e+06 2825.71 13.17 9.3436 7.78726 119030 883757 -1 57009 24 29792 62484 2448958 439074 3.78459 3.78459 -15886.2 -3.78459 0 0 5.41627e+06 3561.00 0.27 2.25 0.65 -1 -1 0.27 1.68943 1.4738 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 201.99 vpr 255.40 MiB 2.14 126336 -1 -1 5 142.90 -1 -1 78972 -1 -1 1356 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 261528 157 197 21024 21221 1 6467 1710 39 39 1521 clb auto 124.6 MiB 7.21 49809 962484 334554 607807 20123 255.4 MiB 9.87 0.12 3.26114 -15027.4 -3.26114 3.26114 7.20 0.0351221 0.0281327 3.06287 2.48936 -1 -1 -1 -1 38 63075 34 7.37824e+07 7.30817e+07 4.16760e+06 2740.04 13.41 9.93144 8.27431 119030 845795 -1 59104 24 31762 70331 2621462 488165 3.1068 3.1068 -15929.2 -3.1068 0 0 5.22668e+06 3436.35 0.24 2.20 0.62 -1 -1 0.24 1.62443 1.4202 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml stereovision0.v common 159.89 odin 1.78 GiB 65.32 1868440 -1 -1 5 58.75 -1 -1 75080 -1 -1 1333 157 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 258252 157 197 21024 21221 1 6351 1687 39 39 1521 clb auto 136.7 MiB 2.92 183607 48717 965335 340609 600791 23935 252.2 MiB 6.37 0.06 8.3236 3.67149 -15448.9 -3.67149 3.67149 3.29 0.0168149 0.0146145 1.94454 1.62852 -1 -1 -1 -1 38 62381 33 2.4642e+07 2.3994e+07 4.29790e+06 2825.71 11.96 6.69956 5.60674 119030 883757 -1 57672 22 29914 63381 2482926 444293 3.4728 3.4728 -15928.1 -3.4728 0 0 5.41627e+06 3561.00 0.18 1.64 0.43 -1 -1 0.18 1.19722 1.06601 +k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 158.67 odin 1.79 GiB 64.83 1877584 -1 -1 5 58.24 -1 -1 75848 -1 -1 1329 157 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 259152 157 197 21024 21221 1 6395 1683 39 39 1521 clb auto 137.0 MiB 2.93 182137 48305 952348 332116 600539 19693 253.1 MiB 6.32 0.07 7.71591 3.21097 -14756.9 -3.21097 3.21097 3.24 0.0192976 0.0166812 1.91255 1.59488 -1 -1 -1 -1 38 61719 36 7.37824e+07 7.16265e+07 4.16760e+06 2740.04 11.71 7.21472 6.04706 119030 845795 -1 58052 25 31719 70350 2555452 477654 3.64157 3.64157 -15795.2 -3.64157 0 0 5.22668e+06 3436.35 0.18 1.82 0.42 -1 -1 0.18 1.31991 1.15859 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt index 53aa221bde0..fb1ca9776ae 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.35 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.6 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 6.5921e-05 4.9487e-05 0.000173999 0.000134314 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00172845 0.00161091 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.0015722 0.00153245 - k6_frac_N10_40nm.xml conn_order.eblif common 0.43 vpr 60.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61580 2 1 4 5 1 3 4 3 3 9 -1 auto 21.9 MiB 0.01 6 9 4 1 4 60.1 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.01 1.6713e-05 1.1905e-05 0.000118437 9.2123e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00165899 0.00156225 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00153235 0.00149153 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.27 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 3 1 5 6 1 4 5 3 3 9 -1 auto 20.2 MiB 0.00 9 9 12 4 4 4 59.0 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 1.0813e-05 7.425e-06 8.2569e-05 6.2814e-05 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.00 0.000987116 0.000914894 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000870274 0.000836286 +k6_frac_N10_40nm.xml conn_order.eblif common 0.28 vpr 58.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60368 2 1 4 5 1 3 4 3 3 9 -1 auto 20.4 MiB 0.00 6 6 9 4 1 4 59.0 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0172e-05 6.799e-06 8.1876e-05 6.3112e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00098864 0.000921289 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000863087 0.000831269 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt index c0c64f8d2c1..4ac9645c21c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.32 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.3959e-05 1.5869e-05 0.000131827 9.7152e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00165685 0.00154691 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00177312 0.00171917 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml eblif_write.eblif common 0.26 vpr 56.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58312 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 16 14 18 7 10 1 56.9 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3321e-05 8.124e-06 8.7295e-05 6.3966e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00108886 0.00100644 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000892955 0.000854475 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt index c750dd52020..1850eda3b9d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.53 vpr 66.67 MiB 0.08 10368 -1 -1 4 0.21 -1 -1 36920 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68272 11 30 262 292 2 99 60 7 7 49 clb auto 27.0 MiB 0.11 431 1932 256 1610 66 66.7 MiB 0.10 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000756181 0.000646522 0.0198618 0.0177275 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0693622 0.0613246 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.93 odin 167.25 MiB 2.90 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66524 11 30 262 292 2 99 61 7 7 49 clb auto 24.9 MiB 0.07 688 427 2461 355 2028 78 65.0 MiB 0.07 0.00 2.92195 2.72416 -177.287 -2.72416 2.43773 0.00 0.000398095 0.00034762 0.0110046 0.00970371 -1 -1 -1 -1 -1 457 20 1.07788e+06 1.07788e+06 90369.8 1844.28 0.03 0.0316159 0.0277496 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt index 41d36d5dda6..f229cdbb877 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.40 vpr 58.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60148 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.5 MiB 0.00 9 9 3 6 0 58.7 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 2.1313e-05 1.5936e-05 0.000108787 8.0593e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00168168 0.00158747 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00146867 0.00143048 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.27 vpr 56.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58320 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 18.6 MiB 0.00 11 9 9 3 6 0 57.0 MiB 0.00 0.00 3.98683 3.8649 -3.8649 -3.8649 nan 0.00 8.943e-06 5.558e-06 6.5235e-05 4.5246e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00118852 0.00111324 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000892854 0.000855363 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt index 41bceae31db..5f0f030f6ff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.46 vpr 66.34 MiB 0.09 10240 -1 -1 4 0.25 -1 -1 36836 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67932 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.10 417 1932 303 1579 50 66.3 MiB 0.03 0.00 2.45862 -181.765 -2.45862 2.33618 0.06 0.000452546 0.000389719 0.0170733 0.0149049 -1 -1 -1 -1 14 566 30 1.07788e+06 1.02399e+06 81563.3 1664.56 0.67 0.279658 0.24196 2472 22196 -1 446 21 890 1897 62387 19776 2.78119 2.51931 -191.416 -2.78119 0 0 98201.7 2004.12 0.00 0.07 0.02 -1 -1 0.00 0.0396875 0.0352228 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 3.79 odin 167.25 MiB 2.51 171264 -1 -1 4 0.12 -1 -1 33108 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67024 11 30 262 292 2 99 61 7 7 49 clb auto 25.5 MiB 0.04 688 429 2941 457 2408 76 65.5 MiB 0.02 0.00 2.93468 2.74942 -180.398 -2.74942 2.45106 0.02 0.000395628 0.000342485 0.0122261 0.0107509 -1 -1 -1 -1 16 538 33 1.07788e+06 1.07788e+06 88828.2 1812.82 0.14 0.0725413 0.0612719 2520 24504 -1 531 31 912 2238 78937 24519 2.94529 2.53849 -196.108 -2.94529 0 0 104221. 2126.97 0.00 0.04 0.01 -1 -1 0.00 0.0270076 0.0233037 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place index 9813ce389c5..84ede063b47 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place @@ -1,175 +1,181 @@ #block name x y subblk layer block number #---------- -- -- ------ ----- ------------ -o_1_ 4 3 2 0 #0 -o_2_ 1 1 2 0 #1 -o_0_ 1 4 4 0 #2 -n_n1827 2 2 3 0 #3 -n_n1829 1 2 5 0 #4 -n_n1812 1 1 3 0 #5 -n_n1866 1 3 4 0 #6 -n_n1865 1 2 4 0 #7 -[493] 4 5 2 0 #8 -n_n544 5 4 5 0 #9 -n_n416 4 1 4 0 #10 -n_n394 2 1 2 0 #11 -n_n391 2 1 3 0 #12 -n_n300 3 1 0 0 #13 -[260] 3 5 3 0 #14 -n_n437 3 3 3 0 #15 -[223] 5 4 1 0 #16 -[79] 3 5 0 0 #17 -[410] 2 4 1 0 #18 -[516] 4 5 4 0 #19 -[245] 3 4 2 0 #20 -[340] 2 5 5 0 #21 -[432] 2 4 5 0 #22 -[80] 3 4 1 0 #23 -[541] 5 3 5 0 #24 -n_n309 2 1 5 0 #25 -[8] 4 5 5 0 #26 -[546] 3 4 5 0 #27 -n_n706 1 2 3 0 #28 -[261] 2 2 1 0 #29 -[463] 4 4 3 0 #30 -n_n1575 3 5 4 0 #31 -n_n1571 2 4 3 0 #32 -[132] 1 5 3 0 #33 -[355] 2 4 2 0 #34 -[214] 4 4 5 0 #35 -[267] 5 4 4 0 #36 -n_n329 3 2 0 0 #37 -[420] 5 2 2 0 #38 -n_n849 2 2 5 0 #39 -[478] 5 4 0 0 #40 -[578] 4 1 3 0 #41 -[253] 4 2 0 0 #42 -[4] 4 1 5 0 #43 -[56] 1 1 4 0 #44 -[226] 3 1 2 0 #45 -[282] 1 3 3 0 #46 -[377] 1 2 1 0 #47 -[71] 1 1 1 0 #48 -[319] 5 2 5 0 #49 -[233] 4 3 1 0 #50 -[246] 3 4 4 0 #51 -[301] 3 5 1 0 #52 -[441] 5 5 0 0 #53 -[608] 5 4 3 0 #54 -[21] 2 1 4 0 #55 -[311] 4 4 1 0 #56 -[344] 3 2 2 0 #57 -[310] 2 2 2 0 #58 -[315] 1 3 2 0 #59 -[29] 1 4 0 0 #60 -[273] 2 4 4 0 #61 -n_n1690 3 4 0 0 #62 -[383] 5 3 1 0 #63 -[390] 2 2 4 0 #64 -[705] 4 4 4 0 #65 -[41] 4 3 5 0 #66 -[351] 4 1 1 0 #67 -[484] 4 2 1 0 #68 -[437] 5 3 4 0 #69 -[349] 3 2 4 0 #70 -[65] 3 5 5 0 #71 -[221] 4 5 1 0 #72 -[402] 2 4 0 0 #73 -[521] 4 1 0 0 #74 -[767] 4 1 2 0 #75 -[133] 2 5 0 0 #76 -[234] 4 3 4 0 #77 -[868] 1 4 3 0 #78 -[904] 4 4 2 0 #79 -[906] 4 2 4 0 #80 -[919] 2 3 3 0 #81 -[1253] 1 3 0 0 #82 -[1283] 3 1 3 0 #83 -[1340] 3 2 3 0 #84 -[1382] 1 1 0 0 #85 -[1404] 3 2 1 0 #86 -[1417] 3 1 1 0 #87 -[1534] 4 3 3 0 #88 -[1615] 3 5 2 0 #89 -[6947] 2 3 2 0 #90 -[7082] 4 3 0 0 #91 -[7159] 4 2 5 0 #92 -[7165] 5 3 2 0 #93 -[7191] 5 3 3 0 #94 -[7319] 3 3 0 0 #95 -[7321] 5 2 0 0 #96 -[7351] 2 3 4 0 #97 -[7388] 1 2 0 0 #98 -[7423] 2 1 0 0 #99 -[7466] 3 2 5 0 #100 -[7782] 4 4 0 0 #101 -[7822] 2 5 4 0 #102 -[7885] 2 5 3 0 #103 -[7888] 2 3 1 0 #104 -[7997] 5 5 2 0 #105 -[8027] 5 2 4 0 #106 -[50] 2 3 0 0 #107 -[288] 3 3 2 0 #108 -[539] 5 2 1 0 #109 -[372] 4 2 3 0 #110 -n_n1584 2 5 1 0 #111 -[196] 2 2 0 0 #112 -[585] 3 3 5 0 #113 -[365] 4 5 3 0 #114 -[492] 1 4 5 0 #115 -[616] 3 3 1 0 #116 -[430] 2 1 1 0 #117 -[663] 1 2 2 0 #118 -[700] 4 2 2 0 #119 -[322] 1 3 5 0 #120 -[739] 3 3 4 0 #121 -[745] 5 3 0 0 #122 -[771] 3 4 3 0 #123 -[95] 4 5 0 0 #124 -[345] 3 1 4 0 #125 -[759] 3 1 5 0 #126 -[1066] 1 3 1 0 #127 -[7199] 5 1 5 0 #128 -[7969] 5 5 3 0 #129 -[7328] 1 4 1 0 #130 -[7559] 5 2 3 0 #131 -out:o_1_ 3 6 1 0 #132 -out:o_2_ 1 0 5 0 #133 -out:o_0_ 1 6 2 0 #134 -i_30_ 3 6 3 0 #135 -i_20_ 4 0 6 0 #136 -i_9_ 3 0 5 0 #137 -i_10_ 0 1 4 0 #138 -i_7_ 2 6 7 0 #139 -i_8_ 3 0 7 0 #140 -i_5_ 2 0 1 0 #141 -i_6_ 3 0 0 0 #142 -i_27_ 4 6 4 0 #143 -i_14_ 2 6 5 0 #144 -i_3_ 3 0 2 0 #145 -i_28_ 2 0 3 0 #146 -i_13_ 2 0 2 0 #147 -i_4_ 3 0 6 0 #148 -i_25_ 1 0 0 0 #149 -i_12_ 2 0 0 0 #150 -i_1_ 4 0 3 0 #151 -i_26_ 1 0 7 0 #152 -i_11_ 4 0 5 0 #153 -i_2_ 3 0 3 0 #154 -i_23_ 4 6 7 0 #155 -i_18_ 4 0 1 0 #156 -i_24_ 2 0 7 0 #157 -i_17_ 4 0 2 0 #158 -i_0_ 2 6 3 0 #159 -i_21_ 5 6 5 0 #160 -i_16_ 4 6 2 0 #161 -i_22_ 1 0 4 0 #162 -i_32_ 4 0 4 0 #163 -i_31_ 2 0 5 0 #164 -i_34_ 3 6 5 0 #165 -i_33_ 1 0 3 0 #166 -i_19_ 6 1 1 0 #167 -i_36_ 3 6 7 0 #168 -i_35_ 2 0 6 0 #169 -i_38_ 3 0 4 0 #170 -i_29_ 2 6 4 0 #171 -i_37_ 4 6 1 0 #172 +o_1_ 4 1 4 0 #0 +o_2_ 4 3 4 0 #1 +o_0_ 2 2 0 0 #2 +n_n1829 3 5 4 0 #3 +n_n1812 5 3 5 0 #4 +n_n1866 4 5 1 0 #5 +n_n1865 4 5 3 0 #6 +[493] 2 1 2 0 #7 +n_n544 3 1 0 0 #8 +n_n416 4 4 0 0 #9 +n_n394 5 4 5 0 #10 +n_n391 5 3 4 0 #11 +n_n300 4 5 5 0 #12 +[260] 3 2 4 0 #13 +[223] 3 1 4 0 #14 +[79] 2 2 4 0 #15 +[410] 1 3 1 0 #16 +[516] 1 3 2 0 #17 +[530] 1 1 1 0 #18 +[245] 1 2 0 0 #19 +[340] 1 4 4 0 #20 +[432] 3 1 2 0 #21 +[533] 2 3 3 0 #22 +[80] 2 2 5 0 #23 +[535] 1 2 1 0 #24 +n_n316 4 2 4 0 #25 +[541] 1 2 5 0 #26 +n_n1563 2 2 1 0 #27 +n_n1585 2 3 4 0 #28 +[38] 2 3 2 0 #29 +n_n706 4 2 3 0 #30 +n_n608 2 1 1 0 #31 +[261] 4 1 0 0 #32 +[463] 5 1 3 0 #33 +n_n1578 1 2 3 0 #34 +[124] 2 3 1 0 #35 +[132] 3 3 2 0 #36 +[227] 1 1 3 0 #37 +[267] 2 2 2 0 #38 +n_n329 2 2 3 0 #39 +n_n849 4 5 0 0 #40 +[478] 2 3 0 0 #41 +[578] 5 5 0 0 #42 +[253] 5 3 2 0 #43 +[4] 5 4 3 0 #44 +[56] 4 4 3 0 #45 +[226] 4 2 5 0 #46 +[282] 5 4 2 0 #47 +[377] 5 5 4 0 #48 +[71] 5 3 3 0 #49 +[246] 3 2 1 0 #50 +[301] 3 1 1 0 #51 +[311] 4 4 4 0 #52 +[344] 4 4 1 0 #53 +[310] 4 2 2 0 #54 +[315] 4 3 0 0 #55 +[78] 3 5 5 0 #56 +[656] 5 3 0 0 #57 +[29] 2 4 1 0 #58 +[273] 3 1 3 0 #59 +[668] 1 2 4 0 #60 +[674] 5 3 1 0 #61 +[74] 1 2 2 0 #62 +n_n1704 4 1 3 0 #63 +[327] 4 5 2 0 #64 +[305] 1 4 3 0 #65 +n_n1702 4 1 5 0 #66 +[351] 5 2 3 0 #67 +[437] 3 3 3 0 #68 +[349] 5 1 5 0 #69 +[65] 1 1 0 0 #70 +[221] 2 1 5 0 #71 +[343] 3 4 5 0 #72 +[406] 5 2 5 0 #73 +[521] 5 4 0 0 #74 +[161] 3 1 5 0 #75 +[189] 2 4 2 0 #76 +[906] 2 4 3 0 #77 +[977] 4 3 5 0 #78 +[1340] 4 4 5 0 #79 +[1426] 5 2 1 0 #80 +[1435] 5 4 1 0 #81 +[1542] 4 3 3 0 #82 +[1615] 3 4 3 0 #83 +[1619] 4 1 2 0 #84 +[6958] 1 4 2 0 #85 +[7025] 5 2 4 0 #86 +[7082] 1 1 5 0 #87 +[7160] 3 2 2 0 #88 +[7319] 3 4 0 0 #89 +[7321] 4 5 4 0 #90 +[7388] 3 3 0 0 #91 +[7390] 3 5 2 0 #92 +[7787] 1 3 3 0 #93 +[7791] 2 3 5 0 #94 +[7811] 2 1 3 0 #95 +[7822] 4 2 0 0 #96 +[7829] 2 1 4 0 #97 +[7885] 3 4 4 0 #98 +[7899] 1 3 5 0 #99 +[7901] 1 1 4 0 #100 +[7997] 1 3 4 0 #101 +[8027] 2 1 0 0 #102 +[8042] 1 4 1 0 #103 +[50] 3 5 3 0 #104 +[307] 3 2 5 0 #105 +[275] 3 2 3 0 #106 +[372] 3 4 1 0 #107 +[503] 3 5 0 0 #108 +[585] 2 4 4 0 #109 +[63] 2 5 3 0 #110 +[431] 5 2 2 0 #111 +[447] 3 3 1 0 #112 +[615] 2 4 5 0 #113 +n_n1716 1 3 0 0 #114 +[254] 4 3 2 0 #115 +[381] 5 4 4 0 #116 +[430] 4 3 1 0 #117 +[276] 4 4 2 0 #118 +[760] 3 4 2 0 #119 +[768] 4 1 1 0 #120 +[792] 2 5 2 0 #121 +[721] 5 2 0 0 #122 +[877] 3 2 0 0 #123 +[884] 4 2 1 0 #124 +[1021] 3 3 5 0 #125 +[1077] 3 3 4 0 #126 +[1700] 1 4 0 0 #127 +[7108] 2 4 0 0 #128 +[7211] 5 1 1 0 #129 +[7516] 2 5 0 0 #130 +[7531] 2 5 4 0 #131 +[7820] 1 4 5 0 #132 +[7917] 2 5 5 0 #133 +[7028] 2 5 1 0 #134 +[7774] 1 5 5 0 #135 +[7778] 1 5 2 0 #136 +[177] 1 1 2 0 #137 +out:o_1_ 4 0 0 0 #138 +out:o_2_ 4 6 1 0 #139 +out:o_0_ 2 0 4 0 #140 +i_30_ 2 6 7 0 #141 +i_20_ 2 0 3 0 #142 +i_9_ 5 6 5 0 #143 +i_10_ 3 6 6 0 #144 +i_7_ 2 0 5 0 #145 +i_8_ 4 6 4 0 #146 +i_5_ 5 6 6 0 #147 +i_6_ 3 0 3 0 #148 +i_27_ 3 0 1 0 #149 +i_14_ 2 0 1 0 #150 +i_3_ 6 4 5 0 #151 +i_28_ 3 0 7 0 #152 +i_13_ 2 0 2 0 #153 +i_4_ 6 2 7 0 #154 +i_25_ 4 6 0 0 #155 +i_12_ 1 0 4 0 #156 +i_1_ 6 2 2 0 #157 +i_26_ 3 6 2 0 #158 +i_11_ 4 0 1 0 #159 +i_2_ 4 6 7 0 #160 +i_23_ 2 0 7 0 #161 +i_18_ 5 6 4 0 #162 +i_24_ 2 0 6 0 #163 +i_17_ 3 0 0 0 #164 +i_0_ 4 0 5 0 #165 +i_21_ 2 6 1 0 #166 +i_16_ 0 3 0 0 #167 +i_22_ 3 6 0 0 #168 +i_32_ 3 6 7 0 #169 +i_31_ 2 6 5 0 #170 +i_34_ 1 0 6 0 #171 +i_33_ 4 0 7 0 #172 +i_19_ 6 4 6 0 #173 +i_36_ 1 0 1 0 #174 +i_35_ 1 0 7 0 #175 +i_38_ 4 6 3 0 #176 +i_29_ 3 6 1 0 #177 +i_37_ 3 0 6 0 #178 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt index 76744275cd6..c02d12cd3b3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 15.55 vpr 74.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76704 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.1 MiB 5.08 5783 1135 0 0 1135 74.9 MiB 0.08 0.01 5.08129 -15.1527 -5.08129 nan 0.20 0.00521387 0.00456397 0.054855 0.0516446 -1 -1 -1 -1 164 7880 41 1.34735e+06 7.11401e+06 957298. 19536.7 8.09 2.3336 2.00198 18546 296938 -1 7311 19 6308 26453 1146687 361661 5.58525 nan -16.6102 -5.58525 0 0 1.19720e+06 24432.6 0.03 0.49 0.23 -1 -1 0.03 0.228213 0.208678 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fix_clusters_test_arch.xml apex2.blif common 6.20 vpr 73.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 138 38 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75236 38 3 1916 1919 0 1057 179 7 7 49 clb auto 34.1 MiB 2.36 5571 5572 1187 0 0 1187 73.5 MiB 0.04 0.00 4.76188 4.76188 -14.2451 -4.76188 nan 0.07 0.0020291 0.00182219 0.0299414 0.0288567 -1 -1 -1 -1 158 7466 37 1.34735e+06 7.43737e+06 924312. 18863.5 2.34 0.677286 0.586504 18354 286522 -1 7089 17 5844 24589 1071101 337183 5.3663 nan -15.678 -5.3663 0 0 1.15416e+06 23554.3 0.02 0.27 0.14 -1 -1 0.02 0.13834 0.128348 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt index 2735c09358a..c05a6c5feab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.00 vpr 66.73 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36456 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.07 499 1698 69 1565 64 66.7 MiB 0.04 0.00 2.45489 -182.908 -2.45489 2.31533 0.06 0.000803566 0.000668095 0.0165762 0.0143795 -1 -1 -1 -1 18 719 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.43 0.155736 0.134195 2616 8308 -1 605 32 901 2129 57619 17801 2.65666 2.40393 -192.483 -2.65666 0 0 59124.6 1206.62 0.00 0.09 0.01 -1 -1 0.00 0.062047 0.0552258 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.83 odin 166.50 MiB 2.52 170496 -1 -1 4 0.12 -1 -1 33108 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 25.5 MiB 0.04 688 531 1981 91 1813 77 65.7 MiB 0.02 0.00 2.92675 2.71243 -182.607 -2.71243 2.42504 0.02 0.000399329 0.000342509 0.00938853 0.00827764 -1 -1 -1 -1 18 741 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.17 0.0698213 0.0586341 2616 8308 -1 669 22 765 1836 62890 21794 2.72374 2.48096 -195.552 -2.72374 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0213747 0.0186684 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt index 03193b42990..bb3ec60f9df 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 26.23 vpr 87.18 MiB 0.37 31744 -1 -1 3 1.50 -1 -1 43564 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89276 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 46.2 MiB 4.36 11021 242654 80011 140532 22111 87.2 MiB 2.29 0.03 4.72515 -2651.47 -4.72515 4.72515 0.68 0.00870927 0.00789125 0.867466 0.775905 -1 -1 -1 -1 58 24978 46 1.65001e+07 9.79696e+06 1.00638e+06 2787.76 11.26 3.56546 3.21933 34441 208101 -1 21032 16 5966 14058 1826516 536884 5.22938 5.22938 -3010.82 -5.22938 0 0 1.28387e+06 3556.43 0.10 1.10 0.34 -1 -1 0.10 0.47794 0.447984 - buffered_flyover_wires.xml raygentop.v common 23.64 vpr 87.26 MiB 0.39 31872 -1 -1 3 1.51 -1 -1 43828 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89352 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.72 11369 231398 74152 135293 21953 87.3 MiB 2.16 0.03 4.81413 -2746.12 -4.81413 4.81413 0.60 0.00796315 0.00714187 0.791566 0.711054 -1 -1 -1 -1 64 23029 28 1.65001e+07 9.79696e+06 1.15406e+06 3196.84 8.51 3.3002 2.94744 35881 226057 -1 19740 15 5519 12704 1627954 469106 4.80072 4.80072 -2914.34 -4.80072 0 0 1.44847e+06 4012.38 0.10 0.92 0.36 -1 -1 0.10 0.422967 0.392398 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +shorted_flyover_wires.xml raygentop.v common 21.34 odin 1.51 GiB 10.42 1588180 -1 -1 3 0.82 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88708 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.19 24028 11417 245468 84522 140289 20657 86.6 MiB 0.91 0.01 5.44161 4.44985 -2711.83 -4.44985 4.44985 0.22 0.0036036 0.00332323 0.350101 0.321011 -1 -1 -1 -1 62 24833 45 1.65001e+07 9.79696e+06 1.07728e+06 2984.15 3.72 1.37948 1.27017 35161 217957 -1 21028 18 6730 15878 2433481 654279 5.215 5.215 -3026.13 -5.215 0 0 1.33769e+06 3705.50 0.04 0.49 0.13 -1 -1 0.04 0.202402 0.191487 +buffered_flyover_wires.xml raygentop.v common 21.52 odin 1.54 GiB 10.85 1614668 -1 -1 3 0.83 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88816 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.7 MiB 2.17 24520 12150 245468 84299 140070 21099 86.7 MiB 0.91 0.01 5.76052 4.50441 -2846.22 -4.50441 4.50441 0.22 0.0036495 0.00331524 0.34963 0.320924 -1 -1 -1 -1 64 25856 29 1.65001e+07 9.79696e+06 1.15406e+06 3196.84 3.52 1.26975 1.16892 35881 226057 -1 21156 15 6633 15933 2219536 617587 4.97633 4.97633 -3163.74 -4.97633 0 0 1.44847e+06 4012.38 0.04 0.44 0.14 -1 -1 0.04 0.182386 0.172674 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt index b90ac6049e3..43da8d8e85b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 3.31 vpr 64.39 MiB 0.03 7296 -1 -1 1 0.04 -1 -1 34228 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65940 193 32 545 422 1 289 227 21 21 441 io auto 25.0 MiB 1.91 3735 46591 19762 26388 441 64.4 MiB 0.33 0.00 2.985 -824.634 -2.985 2.985 0.00 0.00288823 0.00269357 0.190083 0.178688 -1 -1 -1 -1 4590 15.9375 1212 4.20833 431 431 162323 43530 809148 68766.3 979092. 2220.16 5 24050 197379 -1 2.985 2.985 -813.802 -2.985 -21.7856 -0.0851 0.43 -1 -1 64.4 MiB 0.09 0.239729 0.22641 64.4 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +hard_fpu_arch_timing.xml mm3.v common 2.92 odin 76.88 MiB 1.75 78720 -1 -1 1 0.03 -1 -1 30624 -1 -1 0 193 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64292 193 32 545 422 1 289 227 21 21 441 io auto 23.2 MiB 0.38 5010 3747 45899 19410 26043 446 62.8 MiB 0.13 0.00 2.985 2.985 -824.872 -2.985 2.985 0.00 0.00102822 0.000970656 0.0710574 0.0670693 -1 -1 -1 -1 4610 16.0069 1211 4.20486 431 431 145305 38673 809148 68766.3 979092. 2220.16 6 24050 197379 -1 2.985 2.985 -813.692 -2.985 -21.8252 -0.0851 0.13 -1 -1 62.8 MiB 0.03 0.0906843 0.085784 62.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt index 356e91ccb39..91c6bc9bce7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 3.01 vpr 67.75 MiB 0.06 9728 -1 -1 3 0.26 -1 -1 39908 -1 -1 69 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69380 99 130 363 493 1 251 299 13 13 169 clb auto 28.2 MiB 0.66 756 79220 19640 31087 28493 67.8 MiB 0.16 0.00 36 1238 7 0 0 481804. 2850.91 0.62 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.04 odin 102.38 MiB 2.28 104832 -1 -1 3 0.20 -1 -1 34096 -1 -1 71 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68324 99 130 363 493 1 251 301 13 13 169 clb auto 26.7 MiB 0.40 2129 766 78925 23058 31147 24720 66.7 MiB 0.06 0.00 34 1460 7 0 0 460544. 2725.11 0.23 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt index a8ea9747374..b2d02f39e8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.21 vpr 66.19 MiB 0.08 10368 -1 -1 4 0.19 -1 -1 36516 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67780 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.09 431 1932 256 1610 66 66.2 MiB 0.04 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000582727 0.000489391 0.0185537 0.0162573 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0660847 0.0581726 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.41 odin 167.25 MiB 2.50 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 427 2461 355 2028 78 65.7 MiB 0.02 0.00 2.92195 2.72416 -177.287 -2.72416 2.43773 0.00 0.000399205 0.000348503 0.0106789 0.00938853 -1 -1 -1 -1 -1 457 20 1.07788e+06 1.07788e+06 90369.8 1844.28 0.03 0.0308402 0.0270103 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt index 265af1c4b6f..a39697152a5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.39 vpr 60.20 MiB -1 -1 -1 -1 0 0.02 -1 -1 33040 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61648 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.2 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1661e-05 6.33e-06 7.7033e-05 5.0742e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00147387 0.00140823 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.38 vpr 60.24 MiB -1 -1 -1 -1 0 0.02 -1 -1 32912 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61684 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.2 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1339e-05 5.859e-06 8.8591e-05 5.8829e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00162493 0.00154875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.37 vpr 60.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 32868 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 6 1 1 8 0 1 8 3 3 9 -1 auto 22.1 MiB 0.00 0 21 0 10 11 60.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3541e-05 7.635e-06 8.6471e-05 5.7499e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00150205 0.00143129 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.38 vpr 60.58 MiB -1 -1 -1 -1 0 0.02 -1 -1 32612 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 6 1 1 8 0 1 8 3 3 9 -1 auto 22.3 MiB 0.00 0 21 0 10 11 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.7003e-05 9.772e-06 9.7802e-05 6.5568e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00166482 0.00158779 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.39 vpr 60.29 MiB -1 -1 -1 -1 1 0.03 -1 -1 33040 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61732 2 1 3 4 0 3 4 3 3 9 -1 auto 21.9 MiB 0.00 9 9 3 3 3 60.3 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.5758e-05 1.1048e-05 0.000114967 8.6726e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00169019 0.00161423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.50 vpr 60.59 MiB -1 -1 -1 -1 1 0.05 -1 -1 34804 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.5271e-05 1.9684e-05 0.000266101 0.000119821 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00203214 0.00174712 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.51 vpr 60.46 MiB -1 -1 -1 -1 1 0.05 -1 -1 35364 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.0382e-05 1.5156e-05 0.000144485 0.00011379 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00203203 0.0018606 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.35 vpr 60.57 MiB -1 -1 -1 -1 1 0.02 -1 -1 33216 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 3 1 5 6 1 4 5 3 3 9 -1 auto 22.1 MiB 0.00 9 12 7 1 4 60.6 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.8755e-05 1.3531e-05 0.00012903 9.8796e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00153901 0.00145183 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml false_path_mux.blif common 0.50 vpr 60.45 MiB -1 -1 -1 -1 1 0.06 -1 -1 35348 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61904 4 1 4 6 0 4 6 3 3 9 -1 auto 22.1 MiB 0.00 12 15 9 3 3 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.3369e-05 1.7039e-05 0.000173745 0.000138562 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00205463 0.00186426 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_2x2.blif common 0.47 vpr 60.48 MiB -1 -1 -1 -1 1 0.06 -1 -1 35020 -1 -1 1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61928 4 4 8 12 0 8 9 3 3 9 -1 auto 22.1 MiB 0.00 24 27 18 6 3 60.5 MiB 0.00 0.00 0.67231 -2.68924 -0.67231 nan 0.00 3.869e-05 2.9429e-05 0.000257326 0.00021682 -1 -1 -1 -1 -1 10 10 53894 53894 38783.3 4309.26 0.00 0.00244349 0.00222744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x3.blif common 0.51 vpr 60.62 MiB -1 -1 -1 -1 1 0.07 -1 -1 36084 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62076 6 6 12 18 0 12 13 3 3 9 -1 auto 22.1 MiB 0.01 36 43 32 7 4 60.6 MiB 0.00 0.00 0.69831 -4.13786 -0.69831 nan 0.00 7.4526e-05 6.3137e-05 0.000498869 0.000443741 -1 -1 -1 -1 -1 17 12 53894 53894 38783.3 4309.26 0.00 0.00383316 0.00343212 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x4.blif common 0.55 vpr 60.62 MiB -1 -1 -1 -1 2 0.07 -1 -1 35568 -1 -1 3 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62076 7 8 22 30 0 15 18 4 4 16 clb auto 22.1 MiB 0.01 51 64 26 37 1 60.6 MiB 0.00 0.00 1.24888 -7.62396 -1.24888 nan 0.00 9.8331e-05 8.571e-05 0.000766204 0.000700688 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00447879 0.00416054 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_4x4.blif common 0.55 vpr 60.55 MiB -1 -1 -1 -1 4 0.08 -1 -1 35668 -1 -1 2 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62004 8 8 29 37 0 21 18 4 4 16 clb auto 22.0 MiB 0.02 74 64 20 44 0 60.6 MiB 0.00 0.00 2.04839 -11.7951 -2.04839 nan 0.00 0.000135237 0.000115292 0.00112979 0.00104286 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.01 0.00691358 0.00626039 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x5.blif common 0.61 vpr 60.96 MiB -1 -1 -1 -1 4 0.10 -1 -1 36048 -1 -1 4 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62424 10 10 47 57 0 39 24 4 4 16 clb auto 22.1 MiB 0.02 149 92 35 57 0 61.0 MiB 0.00 0.00 2.73035 -18.1288 -2.73035 nan 0.00 0.000225575 0.000203726 0.00149243 0.00139063 -1 -1 -1 -1 -1 123 10 215576 215576 99039.1 6189.95 0.01 0.00763482 0.00712644 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x6.blif common 0.83 vpr 60.83 MiB -1 -1 -1 -1 5 0.15 -1 -1 36408 -1 -1 5 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62288 11 11 61 72 0 51 27 5 5 25 clb auto 21.9 MiB 0.03 192 547 116 431 0 60.8 MiB 0.01 0.00 3.17925 -21.2667 -3.17925 nan 0.00 0.000354484 0.000320379 0.00678629 0.00617992 -1 -1 -1 -1 -1 163 16 485046 269470 186194. 7447.77 0.02 0.0240229 0.0219824 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_1bit.blif common 0.49 vpr 60.46 MiB -1 -1 -1 -1 1 0.06 -1 -1 34452 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 3 2 5 7 0 5 6 3 3 9 -1 auto 22.0 MiB 0.00 15 15 9 5 1 60.5 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 3.2064e-05 2.4155e-05 0.000200579 0.000160863 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00242941 0.00220554 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_2bit.blif common 0.46 vpr 60.28 MiB -1 -1 -1 -1 1 0.06 -1 -1 35352 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61728 5 3 8 11 0 8 9 3 3 9 -1 auto 21.9 MiB 0.00 24 27 21 6 0 60.3 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 3.5791e-05 2.5977e-05 0.000240831 0.000201092 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00270512 0.00243979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_3bit.blif common 0.52 vpr 60.61 MiB -1 -1 -1 -1 2 0.06 -1 -1 35400 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62060 7 4 12 16 0 11 12 3 3 9 -1 auto 22.3 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 4.7612e-05 3.9433e-05 0.000326091 0.000287024 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00528941 0.00513278 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_4bit.blif common 0.64 vpr 60.55 MiB -1 -1 -1 -1 2 0.07 -1 -1 35520 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62008 9 5 15 20 0 14 15 3 3 9 -1 auto 22.2 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 8.1588e-05 7.0424e-05 0.000516653 0.000461489 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.01 0.00432254 0.00385687 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_5bit.blif common 0.56 vpr 60.67 MiB -1 -1 -1 -1 3 0.07 -1 -1 35440 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62124 11 6 19 25 0 17 18 3 3 9 -1 auto 22.1 MiB 0.01 51 64 33 24 7 60.7 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 5.6728e-05 4.4391e-05 0.000433977 0.000387108 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00412344 0.0036326 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.34 vpr 58.67 MiB -1 -1 -1 -1 0 0.02 -1 -1 29684 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.089e-06 3.317e-06 5.6683e-05 3.778e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000889494 0.000836499 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.34 vpr 59.04 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 59.0 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.199e-06 3.438e-06 5.6499e-05 3.6758e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00086748 0.000809475 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.35 vpr 58.36 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59760 6 1 1 8 0 1 8 3 3 9 -1 auto 19.5 MiB 0.00 0 0 21 0 10 11 58.4 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.125e-06 3.333e-06 5.6385e-05 3.6627e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000917244 0.000850516 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.34 vpr 58.55 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59956 6 1 1 8 0 1 8 3 3 9 -1 auto 19.7 MiB 0.00 0 0 21 0 10 11 58.6 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.243e-06 3.368e-06 5.7388e-05 3.8084e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000924173 0.000870894 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and.blif common 0.34 vpr 59.04 MiB -1 -1 -1 -1 1 0.02 -1 -1 29952 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 2 1 3 4 0 3 4 3 3 9 -1 auto 20.6 MiB 0.00 9 9 9 3 3 3 59.0 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 8.568e-06 5.408e-06 7.134e-05 5.2207e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000943335 0.000884471 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.40 vpr 58.47 MiB -1 -1 -1 -1 1 0.03 -1 -1 31872 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59876 5 1 6 7 0 6 7 3 3 9 -1 auto 20.0 MiB 0.00 18 18 18 13 5 0 58.5 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.1859e-05 8.393e-06 9.4908e-05 7.4463e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00118215 0.00106723 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.38 vpr 58.44 MiB -1 -1 -1 -1 1 0.03 -1 -1 31456 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59840 5 1 6 7 0 6 7 3 3 9 -1 auto 19.6 MiB 0.00 18 18 18 13 5 0 58.4 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.1739e-05 8.203e-06 0.000106965 8.6112e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.0011722 0.00105647 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and_latch.blif common 0.31 vpr 58.76 MiB -1 -1 -1 -1 1 0.02 -1 -1 29888 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60172 3 1 5 6 1 4 5 3 3 9 -1 auto 20.3 MiB 0.00 9 9 12 7 1 4 58.8 MiB 0.00 0.00 0.603526 0.52647 -0.88231 -0.52647 0.52647 0.00 1.1008e-05 7.698e-06 8.9061e-05 6.8418e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00102668 0.000965951 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml false_path_mux.blif common 0.39 vpr 59.05 MiB -1 -1 -1 -1 1 0.03 -1 -1 31816 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60464 4 1 4 6 0 4 6 3 3 9 -1 auto 20.2 MiB 0.00 12 12 15 9 3 3 59.0 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.0053e-05 6.686e-06 8.6436e-05 6.5007e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00107231 0.000965027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_2x2.blif common 0.40 vpr 59.06 MiB -1 -1 -1 -1 1 0.03 -1 -1 31488 -1 -1 1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60476 4 4 8 12 0 8 9 3 3 9 -1 auto 20.6 MiB 0.00 24 24 27 18 6 3 59.1 MiB 0.00 0.00 0.749366 0.67231 -2.68924 -0.67231 nan 0.00 1.9318e-05 1.3972e-05 0.000158654 0.000133247 -1 -1 -1 -1 -1 12 10 53894 53894 38783.3 4309.26 0.00 0.00140163 0.00127272 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x3.blif common 0.37 vpr 59.46 MiB -1 -1 -1 -1 1 0.04 -1 -1 31964 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60884 6 6 12 18 0 12 13 3 3 9 -1 auto 20.6 MiB 0.00 36 36 43 32 7 4 59.5 MiB 0.00 0.00 0.775365 0.69831 -4.13786 -0.69831 nan 0.00 2.7042e-05 2.2564e-05 0.000247601 0.000221527 -1 -1 -1 -1 -1 15 12 53894 53894 38783.3 4309.26 0.00 0.00183205 0.00165112 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x4.blif common 0.44 vpr 58.50 MiB -1 -1 -1 -1 2 0.04 -1 -1 32092 -1 -1 3 7 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59908 7 8 22 30 0 15 18 4 4 16 clb auto 19.9 MiB 0.01 62 51 64 26 37 1 58.5 MiB 0.00 0.00 1.24888 1.24888 -7.62396 -1.24888 nan 0.00 4.8704e-05 4.2552e-05 0.000465724 0.000435078 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.0025176 0.00234313 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 0.43 vpr 58.89 MiB -1 -1 -1 -1 4 0.04 -1 -1 32472 -1 -1 2 8 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60308 8 8 29 37 0 21 18 4 4 16 clb auto 20.2 MiB 0.01 82 74 64 20 44 0 58.9 MiB 0.00 0.00 2.04839 2.04839 -11.7951 -2.04839 nan 0.00 6.6449e-05 5.7293e-05 0.000651925 0.000612325 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.00 0.00383257 0.00350913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 0.48 vpr 59.43 MiB -1 -1 -1 -1 4 0.06 -1 -1 32828 -1 -1 4 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60860 10 10 47 57 0 39 24 4 4 16 clb auto 20.2 MiB 0.01 161 149 92 35 57 0 59.4 MiB 0.00 0.00 2.80144 2.73035 -18.1288 -2.73035 nan 0.00 9.807e-05 8.8114e-05 0.000986347 0.000939221 -1 -1 -1 -1 -1 120 10 215576 215576 99039.1 6189.95 0.01 0.00527492 0.00488366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 0.55 vpr 59.18 MiB -1 -1 -1 -1 5 0.07 -1 -1 32492 -1 -1 5 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60604 11 11 61 72 0 49 27 5 5 25 clb auto 20.2 MiB 0.02 227 192 427 90 337 0 59.2 MiB 0.00 0.00 3.28962 3.19291 -21.0185 -3.19291 nan 0.00 0.000132308 0.000120709 0.00247373 0.00230808 -1 -1 -1 -1 -1 193 14 485046 269470 186194. 7447.77 0.01 0.00907418 0.0082901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.39 vpr 58.82 MiB -1 -1 -1 -1 1 0.03 -1 -1 31076 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60236 3 2 5 7 0 5 6 3 3 9 -1 auto 20.0 MiB 0.00 15 15 15 9 5 1 58.8 MiB 0.00 0.00 0.749366 0.67231 -1.34462 -0.67231 nan 0.00 1.2937e-05 9.527e-06 0.000111053 8.9028e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00124373 0.00111746 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.37 vpr 59.06 MiB -1 -1 -1 -1 1 0.03 -1 -1 32248 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60476 5 3 8 11 0 8 9 3 3 9 -1 auto 20.6 MiB 0.00 24 24 27 21 6 0 59.1 MiB 0.00 0.00 0.749366 0.67231 -2.01693 -0.67231 nan 0.00 1.8848e-05 1.3648e-05 0.000147542 0.000123211 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00160521 0.0014395 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.40 vpr 59.07 MiB -1 -1 -1 -1 2 0.03 -1 -1 32248 -1 -1 1 7 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60488 7 4 12 16 0 11 12 3 3 9 -1 auto 20.3 MiB 0.00 33 33 38 24 11 3 59.1 MiB 0.00 0.00 1.08437 1.08437 -4.00246 -1.08437 nan 0.00 2.2911e-05 1.8441e-05 0.000197494 0.000174107 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00143759 0.00133696 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.39 vpr 58.84 MiB -1 -1 -1 -1 2 0.04 -1 -1 32248 -1 -1 1 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60252 9 5 15 20 0 14 15 3 3 9 -1 auto 20.0 MiB 0.00 42 42 51 29 17 5 58.8 MiB 0.00 0.00 1.08437 1.00731 -4.36655 -1.00731 nan 0.00 2.7047e-05 2.2343e-05 0.000265248 0.00023853 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.00193659 0.00174421 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.41 vpr 58.64 MiB -1 -1 -1 -1 3 0.03 -1 -1 32248 -1 -1 1 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60048 11 6 19 25 0 17 18 3 3 9 -1 auto 19.8 MiB 0.00 51 51 64 36 21 7 58.6 MiB 0.00 0.00 1.41937 1.34231 -6.71386 -1.34231 nan 0.00 3.3381e-05 2.6743e-05 0.000296707 0.000268415 -1 -1 -1 -1 -1 21 11 53894 53894 38783.3 4309.26 0.00 0.00209724 0.00191061 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt index 33183dc0a9f..9c8f24bb57f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.33 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3821e-05 7.858e-06 8.9635e-05 6.0426e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00127569 0.00120513 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61760 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.0 MiB 0.00 0 3 0 0 3 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2203e-05 6.662e-06 7.9048e-05 5.258e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00167909 0.00160437 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.30 vpr 60.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61712 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.3 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 3.2696e-05 2.3426e-05 0.000197822 0.000159059 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.0018336 0.0017293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 6 1 7 8 0 7 8 3 3 9 -1 auto 22.3 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.7376e-05 1.9376e-05 0.000172772 0.000138442 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00173443 0.0016423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.26 vpr 60.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61804 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.4 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.1966e-05 1.6158e-05 0.000132177 0.000102284 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00191949 0.00184253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.5373e-05 1.8911e-05 0.000175189 0.000138808 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00175813 0.00166803 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.23 vpr 58.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.41e-06 3.582e-06 5.4963e-05 3.5971e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000865124 0.000812185 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.21 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 59.0 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.345e-06 3.614e-06 5.5264e-05 3.6499e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000882878 0.000829048 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.23 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 6 1 7 8 0 7 8 3 3 9 -1 auto 20.2 MiB 0.00 21 21 21 14 7 0 59.0 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.3883e-05 9.097e-06 9.7954e-05 7.7169e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00101724 0.000957538 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.22 vpr 59.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60464 6 1 7 8 0 7 8 3 3 9 -1 auto 20.2 MiB 0.00 21 21 21 14 7 0 59.0 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.4054e-05 9.237e-06 0.000103459 8.117e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00100695 0.000945272 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.24 vpr 58.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59720 5 1 6 7 0 6 7 3 3 9 -1 auto 19.5 MiB 0.00 18 18 18 13 5 0 58.3 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.2891e-05 9.225e-06 0.000102343 8.0654e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00102367 0.000961224 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.25 vpr 59.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60844 5 1 6 7 0 6 7 3 3 9 -1 auto 20.7 MiB 0.00 18 18 18 13 5 0 59.4 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.213e-05 8.696e-06 0.000106784 8.1447e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.000983793 0.000910586 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt index eaf5555874c..049137ed642 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 1.83 vpr 66.90 MiB 0.07 10496 -1 -1 4 0.18 -1 -1 36452 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68504 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.20 415 2196 413 1711 72 66.9 MiB 0.04 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.0007561 0.000646489 0.0218848 0.0192021 -1 -1 -1 -1 12 302 11 1.07788e+06 700622 -1 -1 0.20 0.128028 0.113742 2680 3516 -1 297 3 164 241 11232 5767 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0191965 0.0182163 - x_uniform_y_gaussian.xml stereovision3.v common 1.88 vpr 67.18 MiB 0.07 10624 -1 -1 4 0.21 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 11 30 262 292 2 110 54 7 7 49 clb auto 28.1 MiB 0.13 404 2298 458 1774 66 67.2 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.00 0.000687045 0.000583062 0.0174363 0.0155371 -1 -1 -1 -1 12 308 8 1.07788e+06 700622 -1 -1 0.31 0.110517 0.0976349 2680 3516 -1 297 3 168 247 11340 5786 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0178597 0.0169935 - x_gaussian_y_gaussian.xml stereovision3.v common 1.87 vpr 66.84 MiB 0.06 10496 -1 -1 4 0.16 -1 -1 36536 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68444 11 30 262 292 2 110 54 7 7 49 clb auto 27.9 MiB 0.18 410 2298 443 1773 82 66.8 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000756768 0.000647761 0.0255781 0.0225686 -1 -1 -1 -1 14 303 4 1.07788e+06 700622 -1 -1 0.40 0.162052 0.141633 2680 3516 -1 295 3 165 244 11438 5780 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0211596 0.0200797 - x_delta_y_uniform.xml stereovision3.v common 1.95 vpr 67.15 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36504 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68764 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.14 450 3012 620 2301 91 67.2 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000754694 0.000686961 0.028 0.0247412 -1 -1 -1 -1 48 342 3 1.07788e+06 700622 -1 -1 0.49 0.268135 0.232895 2680 3516 -1 342 3 170 251 11060 5468 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0196307 0.0186303 - x_delta_y_delta.xml stereovision3.v common 2.11 vpr 67.59 MiB 0.07 10496 -1 -1 4 0.22 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69212 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.13 519 3012 615 2292 105 67.6 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000782235 0.000651544 0.0273675 0.0237579 -1 -1 -1 -1 54 442 17 1.07788e+06 700622 -1 -1 0.52 0.268766 0.234157 2680 3516 -1 431 4 215 308 16404 8615 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0214181 0.0202532 - x_uniform_y_delta.xml stereovision3.v common 2.05 vpr 67.14 MiB 0.07 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68756 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.15 435 2502 457 1952 93 67.1 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000965335 0.000843275 0.027473 0.0239971 -1 -1 -1 -1 34 323 16 1.07788e+06 700622 -1 -1 0.51 0.30529 0.26214 2680 3516 -1 317 16 376 682 28098 12512 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.06 0.01 -1 -1 0.00 0.0352499 0.0319547 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +x_gaussian_y_uniform.xml stereovision3.v common 3.79 odin 167.62 MiB 2.53 171648 -1 -1 4 0.12 -1 -1 33076 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67216 11 30 262 292 2 107 54 7 7 49 clb auto 26.7 MiB 0.06 616 394 1788 342 1398 48 65.6 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000394558 0.000343514 0.00983066 0.00882096 -1 -1 -1 -1 10 309 8 1.07788e+06 700622 -1 -1 0.14 0.0540553 0.0467468 2680 3516 -1 281 3 216 332 13740 6540 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0110537 0.0104942 +x_uniform_y_gaussian.xml stereovision3.v common 3.74 odin 167.25 MiB 2.55 171264 -1 -1 4 0.12 -1 -1 33232 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67052 11 30 262 292 2 107 54 7 7 49 clb auto 26.5 MiB 0.06 616 416 1584 291 1249 44 65.5 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000398166 0.000347484 0.00915684 0.00820103 -1 -1 -1 -1 14 315 2 1.07788e+06 700622 -1 -1 0.07 0.0511739 0.044167 2680 3516 -1 312 2 155 239 9997 5015 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.0106007 0.0101553 +x_gaussian_y_gaussian.xml stereovision3.v common 4.09 odin 167.62 MiB 2.87 171648 -1 -1 4 0.12 -1 -1 33092 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66724 11 30 262 292 2 107 54 7 7 49 clb auto 26.2 MiB 0.07 616 414 2094 382 1620 92 65.2 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000407004 0.00035303 0.0114405 0.0101707 -1 -1 -1 -1 14 297 3 1.07788e+06 700622 -1 -1 0.07 0.0544621 0.0470729 2680 3516 -1 298 16 183 323 13761 7064 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0194151 0.0174723 +x_delta_y_uniform.xml stereovision3.v common 3.79 odin 167.62 MiB 2.50 171648 -1 -1 4 0.12 -1 -1 33076 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67272 11 30 262 292 2 107 54 7 7 49 clb auto 26.4 MiB 0.06 616 433 2604 491 2026 87 65.7 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000398035 0.000342425 0.013054 0.0115899 -1 -1 -1 -1 38 323 9 1.07788e+06 700622 -1 -1 0.15 0.0912421 0.0775499 2680 3516 -1 318 3 165 251 11417 5738 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0116648 0.0110807 +x_delta_y_delta.xml stereovision3.v common 3.94 odin 167.62 MiB 2.63 171648 -1 -1 4 0.13 -1 -1 33080 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67316 11 30 262 292 2 107 54 7 7 49 clb auto 26.4 MiB 0.06 616 488 3114 640 2376 98 65.7 MiB 0.03 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000397581 0.000346847 0.0150194 0.0132722 -1 -1 -1 -1 54 378 8 1.07788e+06 700622 -1 -1 0.15 0.0912923 0.077708 2680 3516 -1 377 4 186 272 12468 6162 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0121325 0.0114634 +x_uniform_y_delta.xml stereovision3.v common 3.83 odin 167.62 MiB 2.54 171648 -1 -1 4 0.12 -1 -1 33108 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67272 11 30 262 292 2 107 54 7 7 49 clb auto 26.4 MiB 0.07 616 423 2196 403 1708 85 65.7 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000402032 0.0003504 0.0118642 0.0105316 -1 -1 -1 -1 38 306 15 1.07788e+06 700622 -1 -1 0.15 0.0944893 0.0801165 2680 3516 -1 305 15 191 335 14110 6670 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.018365 0.0165829 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt index a4fce4cf22f..3cbac41fce1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 2.02 vpr 67.00 MiB 0.08 10496 -1 -1 4 0.20 -1 -1 36452 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68608 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.11 419 1815 318 1436 61 67.0 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000706488 0.000606458 0.0228093 0.0209659 -1 -1 -1 -1 8 283 18 1.07788e+06 1.02399e+06 -1 -1 0.38 0.186498 0.171178 2100 3116 -1 280 18 572 1139 59841 29637 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.07 0.00 -1 -1 0.00 0.0346595 0.0310733 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 2.04 vpr 66.32 MiB 0.07 10496 -1 -1 4 0.26 -1 -1 36580 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67916 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 428 1698 248 1401 49 66.3 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000764131 0.000648712 0.0183265 0.0161998 -1 -1 -1 -1 10 297 21 1.07788e+06 1.02399e+06 -1 -1 0.45 0.176554 0.15406 2100 3116 -1 286 18 539 1058 53794 27022 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.08 0.00 -1 -1 0.00 0.0402826 0.0356284 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.99 vpr 66.21 MiB 0.09 10368 -1 -1 4 0.24 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67800 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 447 1815 292 1481 42 66.2 MiB 0.07 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.00090328 0.000782565 0.0181809 0.0161296 -1 -1 -1 -1 16 296 17 1.07788e+06 1.02399e+06 -1 -1 0.25 0.115099 0.100427 2100 3116 -1 300 17 545 1102 57605 27890 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.12 0.01 -1 -1 0.00 0.0397962 0.0356125 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 3.96 odin 167.25 MiB 2.71 171264 -1 -1 4 0.12 -1 -1 33208 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 439 1981 340 1577 64 65.7 MiB 0.02 0.00 2.02388 2.02388 -140.31 -2.02388 1.9292 0.00 0.000388075 0.000339041 0.00890656 0.00797424 -1 -1 -1 -1 8 310 17 1.07788e+06 1.07788e+06 -1 -1 0.15 0.0572597 0.0490883 2100 3116 -1 300 19 436 776 44386 23435 2.02388 1.9292 -140.31 -2.02388 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.018872 0.0167477 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 4.23 odin 167.25 MiB 2.96 171264 -1 -1 4 0.13 -1 -1 33100 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67188 11 30 262 292 2 99 61 7 7 49 clb auto 26.2 MiB 0.05 688 420 1741 256 1424 61 65.6 MiB 0.02 0.00 2.02388 2.02388 -140.31 -2.02388 1.9292 0.00 0.000396128 0.000345351 0.00833909 0.00744772 -1 -1 -1 -1 14 287 20 1.07788e+06 1.07788e+06 -1 -1 0.11 0.0588694 0.0501538 2100 3116 -1 283 20 516 944 48724 24190 2.02388 1.9292 -140.31 -2.02388 0 0 -1 -1 0.00 0.04 0.00 -1 -1 0.00 0.0200585 0.0177613 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 3.74 odin 167.25 MiB 2.53 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67648 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 446 2341 306 1971 64 66.1 MiB 0.02 0.00 2.02388 2.02388 -140.31 -2.02388 1.9292 0.00 0.000390978 0.000340979 0.0100418 0.00894967 -1 -1 -1 -1 16 306 15 1.07788e+06 1.07788e+06 -1 -1 0.10 0.0586835 0.0503287 2100 3116 -1 315 15 490 966 53909 27396 2.02388 1.9292 -140.31 -2.02388 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0167801 0.0150028 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt index e6884fa004e..d1fcdc4c422 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 6.17 vpr 66.89 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36612 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68492 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.11 425 2283 406 1804 73 66.9 MiB 2.36 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.00076202 0.000633481 0.0213386 0.0169977 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 1.35 0.0886305 0.079884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 5.87 odin 167.62 MiB 2.55 171648 -1 -1 4 0.12 -1 -1 33104 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67040 11 30 262 292 2 99 61 7 7 49 clb auto 25.4 MiB 0.04 688 437 2341 384 1888 69 65.5 MiB 1.26 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.00040053 0.000347422 0.0103465 0.00915139 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.64 0.0330431 0.0289561 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt index b4a9052cd04..931ceee65ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 2.01 vpr 61.71 MiB 0.06 10112 -1 -1 4 0.22 -1 -1 36708 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63196 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 442 4182 3410 664 108 61.7 MiB 0.07 0.00 2.55648 -171.707 -2.55648 2.31607 0.04 0.000697499 0.000590032 0.035108 0.0301305 -1 -1 -1 -1 36 688 16 862304 700622 64877.6 1802.15 0.32 0.199199 0.171554 2900 12076 -1 568 12 312 493 15436 6065 2.62572 2.28031 -177.78 -2.62572 0 0 80896.3 2247.12 0.00 0.04 0.02 -1 -1 0.00 0.0300653 0.0274931 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml stereovision3.v common 2.73 odin 151.50 MiB 1.45 155136 -1 -1 4 0.12 -1 -1 33076 -1 -1 13 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61812 11 30 262 292 2 107 54 6 6 36 clb auto 21.0 MiB 0.06 561 417 4182 3406 658 118 60.4 MiB 0.04 0.00 2.44705 2.32039 -170.792 -2.32039 2.20653 0.01 0.000401205 0.0003469 0.019576 0.0171142 -1 -1 -1 -1 36 788 25 862304 700622 64877.6 1802.15 0.19 0.107302 0.0903116 2900 12076 -1 552 14 362 618 15589 5868 2.33898 2.20362 -179.305 -2.33898 0 0 80896.3 2247.12 0.00 0.02 0.01 -1 -1 0.00 0.0188673 0.0170516 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt index 8d2903c2d48..a50dd42d5d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 18.17 vpr 71.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72740 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.53 10472 141533 36950 100839 3744 71.0 MiB 1.46 0.02 7.46482 -1369.01 -7.46482 7.46482 0.64 0.00605549 0.00528423 0.429203 0.364085 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.91 2.29628 1.96589 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.03 0.83 0.15 -1 -1 0.03 0.252853 0.225541 - k4_N4_90nm.xml ex5p.blif common 20.35 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68624 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.32 12004 99857 28319 69545 1993 67.0 MiB 1.07 0.02 6.86459 -313.968 -6.86459 nan 0.52 0.0035933 0.00315668 0.2475 0.211473 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 14.36 0.89434 0.759948 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.08 1.43 0.30 -1 -1 0.08 0.237816 0.212077 - k4_N4_90nm.xml s298.blif common 19.44 vpr 73.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74984 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.0 MiB 0.49 13813 156389 45768 109723 898 73.2 MiB 1.80 0.03 12.2682 -96.384 -12.2682 12.2682 0.93 0.0106993 0.00945176 0.491739 0.389383 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 10.93 1.63745 1.34189 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.10 1.48 0.31 -1 -1 0.10 0.297955 0.263351 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml diffeq.blif common 4.83 vpr 71.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73060 64 39 1935 1974 1 1075 542 23 23 529 clb auto 31.1 MiB 0.17 24088 10407 135291 36283 95683 3325 71.3 MiB 0.54 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.20 0.00206649 0.00175858 0.139723 0.120994 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.40 0.433146 0.377372 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.30 0.07 -1 -1 0.02 0.0892118 0.0808294 +k4_N4_90nm.xml ex5p.blif common 6.43 vpr 66.13 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67716 8 63 1072 1135 0 892 433 22 22 484 clb auto 26.3 MiB 0.13 20089 11891 97016 28068 66779 2169 66.1 MiB 0.40 0.01 11.9965 7.14697 -323.69 -7.14697 nan 0.18 0.00134043 0.00119147 0.0897746 0.080448 -1 -1 -1 -1 32 16897 50 891726 807012 949946. 1962.70 4.19 0.334258 0.292305 43920 162796 -1 13798 21 8357 30046 2938323 715872 6.93884 nan -322.607 -6.93884 0 0 1.22393e+06 2528.78 0.04 0.44 0.09 -1 -1 0.04 0.0716204 0.0648027 +k4_N4_90nm.xml s298.blif common 8.54 vpr 73.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 579 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74816 4 6 1942 1948 1 1135 589 27 27 729 clb auto 33.1 MiB 0.18 26761 13173 158541 45950 111660 931 73.1 MiB 0.66 0.01 27.8284 12.5893 -95.8017 -12.5893 12.5893 0.28 0.00244424 0.00207476 0.168219 0.145073 -1 -1 -1 -1 24 18368 39 1.39333e+06 1.29078e+06 1.12265e+06 1539.99 5.30 0.547643 0.470994 54650 192211 -1 15957 20 8308 43971 3554658 708435 12.1943 12.1943 -92.9601 -12.1943 0 0 1.47093e+06 2017.74 0.02 0.60 0.11 -1 -1 0.02 0.121878 0.109788 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt index 4db936a1dd3..542dfe84888 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.78 vpr 69.28 MiB 0.09 10496 -1 -1 5 0.19 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70944 11 30 313 321 2 114 55 7 7 49 clb auto 29.8 MiB 0.39 459 2031 574 1374 83 69.3 MiB 0.03 0.00 4.6413 0 0 4.31525 0.00 0.000635584 0.000552586 0.0173645 0.0155707 -1 -1 -1 -1 570 5.27778 228 2.11111 239 439 10467 3202 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 69.3 MiB 0.14 0.147679 0.140851 69.3 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 4.04 odin 157.12 MiB 2.89 160896 -1 -1 5 0.11 -1 -1 33304 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69500 11 30 313 321 2 115 55 7 7 49 clb auto 28.6 MiB 0.17 671 430 3071 674 1846 551 67.9 MiB 0.03 0.00 4.73611 4.6413 0 0 4.32062 0.00 0.000385155 0.000350825 0.0148038 0.0136631 -1 -1 -1 -1 568 5.21101 230 2.11009 310 604 14151 4248 1.07788e+06 754516 219490. 4479.39 9 5100 32136 -1 4.69675 4.35776 0 0 -164.736 -1.707 0.02 -1 -1 67.9 MiB 0.08 0.0926108 0.0891897 67.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt index 19fe5d4556f..bcb0b5d161b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt index 8285cf5d7b5..2a360b9ec50 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 2.66 vpr 68.27 MiB 0.06 9984 -1 -1 3 0.36 -1 -1 39780 -1 -1 66 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69908 99 130 363 493 1 250 296 12 12 144 clb auto 29.2 MiB 0.21 805 57484 15208 21002 21274 68.3 MiB 0.11 0.00 40 1774 10 5.66058e+06 4.105e+06 360333. 2502.31 0.52 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 4.11 odin 100.88 MiB 2.60 103296 -1 -1 3 0.20 -1 -1 34072 -1 -1 66 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67788 99 130 363 493 1 256 296 12 12 144 clb auto 26.8 MiB 0.09 2010 809 75232 21521 28755 24956 66.2 MiB 0.06 0.00 48 1681 14 5.66058e+06 4.105e+06 424682. 2949.18 0.24 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt index 735a18dab2b..0b6e20be258 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.45 vpr 66.93 MiB 0.09 10368 -1 -1 4 0.22 -1 -1 36756 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68532 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00571426 0.00556672 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.38 odin 167.25 MiB 2.52 171264 -1 -1 4 0.12 -1 -1 33292 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 11 30 262 292 2 99 61 7 7 49 clb auto 25.3 MiB 0.04 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00122021 0.00115346 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt index 402ade22624..630005b88fb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.29 vpr 66.33 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36632 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67920 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.05 0.000892007 0.00076546 0.0179963 0.0157273 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0202445 0.0178347 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.62 odin 167.25 MiB 2.66 171264 -1 -1 4 0.12 -1 -1 33108 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 430 2821 451 2299 71 65.7 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000405286 0.000352219 0.0118962 0.0104836 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0130883 0.0116044 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt index 8bf865796ba..93796b474f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 0.57 vpr 60.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62456 11 11 59 70 0 48 26 4 4 16 clb auto 22.0 MiB 0.04 179 862 260 602 0 61.0 MiB 0.01 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000234107 0.000208327 0.0069198 0.00625105 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.10 0.0507337 0.0443992 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.02 0.00 -1 -1 0.00 0.0119559 0.010883 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.07 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23940 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml mult_5x6.blif common 0.38 vpr 59.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61048 11 11 59 70 0 48 26 4 4 16 clb auto 20.2 MiB 0.02 205 178 672 211 461 0 59.6 MiB 0.01 0.00 2.48509 2.46139 -19.889 -2.46139 nan 0.00 0.000113648 0.000103358 0.00299057 0.00277639 -1 -1 -1 -1 30 215 23 215576 215576 18771.3 1173.21 0.04 0.0197788 0.0170591 1016 3020 -1 186 15 222 505 8959 4790 2.75695 nan -23.0631 -2.75695 0 0 22855.5 1428.47 0.00 0.01 0.00 -1 -1 0.00 0.00593139 0.0053815 +k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.05 vpr 21.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 21872 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt index af7706738c0..60a3dab3584 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.24 vpr 64.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66340 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.8 MiB 0.01 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 6.4699e-05 4.5848e-05 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common 0.16 vpr 63.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64788 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 24 21 30 9 19 2 63.3 MiB 0.00 0.00 0.739166 0.646042 -3.51892 -0.646042 0.571 0.00 2.3495e-05 1.6333e-05 0.000928287 0.000887308 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000928287 0.000887308 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt index 25609b75a68..b70afe597bd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 40.74 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.79 0.000585035 0.000506509 0.0125856 0.0113967 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.17 0.202681 0.177336 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.09 0.08 -1 -1 0.01 0.0322374 0.0298184 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 42.57 vpr 978.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001668 10 10 168 178 1 68 30 11 8 88 io auto 955.1 MiB 0.58 356 628 86 501 41 978.2 MiB 0.08 0.00 6.32784 -69.1369 -6.32784 6.32784 2.79 0.00106817 0.000941606 0.0173949 0.0157097 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.41 0.24274 0.212439 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.08 0.08 -1 -1 0.01 0.0393492 0.0368597 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 41.18 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.77 378 628 92 504 32 978.5 MiB 0.06 0.00 6.37842 -68.9795 -6.37842 6.37842 3.93 0.000461318 0.000398366 0.0135017 0.0123478 -1 -1 -1 -1 30 740 27 0 0 144567. 1642.81 1.27 0.212409 0.18717 11730 32605 -1 579 10 219 802 50034 22946 6.80801 6.80801 -73.0986 -6.80801 0 0 194014. 2204.70 0.01 0.06 0.10 -1 -1 0.01 0.0272644 0.0255028 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 43.49 vpr 978.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002044 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.67 353 582 71 475 36 978.6 MiB 0.10 0.00 6.2342 -69.2052 -6.2342 6.2342 4.26 0.00126519 0.00120018 0.0174025 0.0162066 -1 -1 -1 -1 22 762 19 0 0 110609. 1256.92 0.57 0.121021 0.108951 11258 24748 -1 710 14 413 1547 91286 47129 6.80216 6.80216 -76.023 -6.80216 0 0 134428. 1527.59 0.01 0.08 0.05 -1 -1 0.01 0.0301878 0.0279201 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 22.09 vpr 980.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003660 10 10 168 178 1 65 30 11 8 88 io auto 953.7 MiB 0.32 530 354 766 109 603 54 980.1 MiB 0.05 0.00 6.8164 6.25965 -69.3407 -6.25965 6.25965 0.98 0.00031125 0.000282067 0.00812631 0.00755584 -1 -1 -1 -1 20 842 24 0 0 100248. 1139.18 0.28 0.0526186 0.0466377 11180 23751 -1 740 16 428 1793 101987 51614 6.72979 6.72979 -75.9114 -6.72979 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0174048 0.0160478 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 22.04 vpr 980.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003680 10 10 168 178 1 65 30 11 8 88 io auto 953.7 MiB 0.32 530 359 766 97 619 50 980.2 MiB 0.05 0.00 6.8164 6.26487 -69.3105 -6.26487 6.26487 0.99 0.000319106 0.000291575 0.0081832 0.0076106 -1 -1 -1 -1 22 829 20 0 0 110609. 1256.92 0.27 0.0523685 0.0465314 11258 24748 -1 771 17 378 1439 87505 45574 6.83905 6.83905 -76.8941 -6.83905 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.0173368 0.0159174 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 22.55 vpr 980.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003972 10 10 168 178 1 65 30 11 8 88 io auto 954.0 MiB 0.32 530 349 674 94 530 50 980.4 MiB 0.05 0.00 6.77016 6.47558 -68.8469 -6.47558 6.47558 1.38 0.000298307 0.000270422 0.00750644 0.00701996 -1 -1 -1 -1 20 861 19 0 0 100248. 1139.18 0.29 0.050198 0.0445509 11180 23751 -1 680 16 330 1259 70362 36922 6.87801 6.87801 -76.1492 -6.87801 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0169506 0.0156205 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 22.55 vpr 979.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003392 10 10 168 178 1 65 30 11 8 88 io auto 953.4 MiB 0.33 530 348 720 100 579 41 979.9 MiB 0.05 0.00 6.77016 6.34606 -69.0457 -6.34606 6.34606 1.41 0.000302169 0.000275003 0.00785604 0.00733066 -1 -1 -1 -1 20 851 21 0 0 100248. 1139.18 0.27 0.0516757 0.0458386 11180 23751 -1 743 16 380 1503 81107 41070 6.53785 6.53785 -75.082 -6.53785 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0170992 0.0157992 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt index de612c1c661..ee5d462d98b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 41.99 vpr 978.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001688 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.85 385 628 76 517 35 978.2 MiB 0.09 0.00 6.37842 -68.9926 -6.37842 6.37842 2.49 0.000740479 0.000647957 0.0145497 0.0133659 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.45 0.22055 0.192568 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.11 0.10 -1 -1 0.01 0.0358167 0.033477 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 41.03 vpr 978.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001836 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.66 356 628 86 501 41 978.4 MiB 0.10 0.00 6.32784 -69.1369 -6.32784 6.32784 2.55 0.000491141 0.000429611 0.0148781 0.0136279 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.47 0.229896 0.203057 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.11 0.09 -1 -1 0.01 0.0316333 0.0293122 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 22.15 vpr 979.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003264 10 10 168 178 1 65 30 11 8 88 io auto 953.3 MiB 0.33 530 354 766 109 603 54 979.8 MiB 0.05 0.00 6.8164 6.25965 -69.3407 -6.25965 6.25965 0.97 0.000321472 0.000271532 0.00806108 0.00747147 -1 -1 -1 -1 20 842 24 0 0 100248. 1139.18 0.28 0.05278 0.0466501 11180 23751 -1 740 16 428 1793 101987 51614 6.72979 6.72979 -75.9114 -6.72979 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0173118 0.0159829 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 22.13 vpr 979.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003148 10 10 168 178 1 65 30 11 8 88 io auto 953.4 MiB 0.32 530 359 766 97 619 50 979.6 MiB 0.06 0.00 6.8164 6.26487 -69.3105 -6.26487 6.26487 0.99 0.000295946 0.000268265 0.00820091 0.00762383 -1 -1 -1 -1 22 829 20 0 0 110609. 1256.92 0.27 0.0515235 0.045775 11258 24748 -1 771 17 378 1439 87505 45574 6.83905 6.83905 -76.8941 -6.83905 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.0174113 0.0159753 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt index be79764ceb1..fa723315ce7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 4.26 vpr 76.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78288 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.83 6246 12245 2336 8854 1055 76.5 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.27 0.00393519 0.00333322 0.167205 0.141172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.170495 0.143929 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.34 vpr 76.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78408 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.32 6248 12409 2316 9051 1042 76.6 MiB 0.27 0.01 5.00015 -217.921 -5.00015 nan 0.18 0.00183948 0.00156955 0.109821 0.0973753 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.11472 0.101715 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 6.81 vpr 76.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78560 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.45 6557 16051 3559 11939 553 76.7 MiB 0.47 0.01 5.39652 -231.823 -5.39652 nan 1.67 0.00368316 0.00300979 0.191413 0.165252 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.196386 0.169658 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.69 vpr 76.65 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78492 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.4 MiB 2.51 6642 53385 10847 39555 2983 76.7 MiB 1.06 0.02 5.30857 -236.309 -5.30857 nan 1.91 0.00201874 0.00161249 0.24975 0.219272 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.258981 0.227848 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml ex5p.blif common_--place_effort_scaling_circuit 1.80 vpr 75.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77676 8 63 1072 1135 0 611 133 11 11 121 clb auto 35.8 MiB 1.19 7518 6082 8947 1533 6815 599 75.9 MiB 0.13 0.00 5.94011 5.07653 -213.869 -5.07653 nan 0.08 0.00138085 0.00120833 0.0557598 0.0510581 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.058042 0.0530968 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 1.84 vpr 75.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77592 8 63 1072 1135 0 611 133 11 11 121 clb auto 36.1 MiB 1.21 7518 6142 9355 1631 7067 657 75.8 MiB 0.15 0.00 5.94011 4.97625 -208.188 -4.97625 nan 0.08 0.00138735 0.00121011 0.0616278 0.0561673 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0639105 0.0582109 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 3.02 vpr 75.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77316 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.8 MiB 1.16 17047 6704 22507 6724 13850 1933 75.5 MiB 0.27 0.00 9.03576 5.62812 -248.555 -5.62812 nan 0.63 0.00138573 0.00121317 0.11031 0.0991692 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.112545 0.10117 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 3.29 vpr 75.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77316 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.8 MiB 1.17 17047 6681 64488 18508 41026 4954 75.5 MiB 0.52 0.01 9.03576 5.51074 -242.103 -5.51074 nan 0.64 0.00137865 0.00122309 0.103759 0.0934135 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.105985 0.0954026 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt index b0056cc1abc..3c0cb5f8c63 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.86 vpr 66.93 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68536 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.9 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.00072366 0.000614909 0.0157761 0.0136171 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.27 0.140412 0.11741 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.06 0.01 -1 -1 0.00 0.0578011 0.0529737 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.92 odin 167.25 MiB 2.63 171264 -1 -1 4 0.12 -1 -1 33088 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67040 11 30 262 292 2 99 61 7 7 49 clb auto 25.8 MiB 0.04 688 430 2821 451 2299 71 65.5 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000396362 0.000343176 0.0120084 0.0105776 -1 -1 -1 -1 18 673 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.18 0.073831 0.0622022 2616 8308 -1 591 24 845 2121 68310 27246 2.65985 2.3922 -190.754 -2.65985 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0227802 0.0197882 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt index c15f8828261..cd20352a239 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.38 vpr 62.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 33172 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63964 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.2 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4078e-05 8.305e-06 7.897e-05 5.195e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00158662 0.00151514 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.40 vpr 62.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 32980 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63964 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.2 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1945e-05 6.486e-06 7.545e-05 4.8841e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00148797 0.00142035 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.44 vpr 62.59 MiB -1 -1 -1 -1 0 0.02 -1 -1 32992 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64096 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 2.0091e-05 1.2082e-05 0.000201085 0.000162772 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00181183 0.00172223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.43 vpr 62.71 MiB -1 -1 -1 -1 0 0.02 -1 -1 33076 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.7 MiB 0.00 0.00 nan 0 0 nan 0.00 1.9557e-05 1.1746e-05 0.00010411 6.6917e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.0019441 0.00185632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.39 vpr 62.59 MiB -1 -1 -1 -1 1 0.02 -1 -1 33300 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 2 1 3 4 0 3 4 3 3 9 -1 auto 24.3 MiB 0.00 9 9 5 0 4 62.6 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.6008e-05 1.0878e-05 0.0001005 7.3545e-05 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.00 0.00172772 0.00159734 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.62 vpr 62.37 MiB -1 -1 -1 -1 2 0.06 -1 -1 35272 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63864 5 1 7 8 0 7 7 3 3 9 -1 auto 24.0 MiB 0.00 20 18 12 0 6 62.4 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4824e-05 1.9123e-05 0.000151781 0.000121494 -1 -1 -1 -1 -1 8 6 3900 3900 7855.82 872.868 0.00 0.00207121 0.00193926 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.55 vpr 62.58 MiB -1 -1 -1 -1 2 0.06 -1 -1 35192 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64080 5 1 7 8 0 7 7 3 3 9 -1 auto 24.2 MiB 0.00 20 18 13 0 5 62.6 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4985e-05 1.9224e-05 0.000155624 0.000125459 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.002084 0.00190667 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.39 vpr 62.40 MiB -1 -1 -1 -1 1 0.02 -1 -1 33452 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower 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25 27 23 0 4 61.2 MiB 0.00 0.00 0.443777 0.443777 -1.77511 -0.443777 nan 0.00 1.7573e-05 1.3738e-05 0.000134702 0.000112478 -1 -1 -1 -1 -1 30 13 3900 3900 7855.82 872.868 0.00 0.00139893 0.00124994 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.41 vpr 61.21 MiB -1 -1 -1 -1 3 0.04 -1 -1 32352 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62680 6 6 28 34 0 28 15 5 5 25 clb auto 22.5 MiB 0.00 113 107 51 16 35 0 61.2 MiB 0.00 0.00 1.19848 1.19848 -5.43061 -1.19848 nan 0.00 4.9548e-05 4.359e-05 0.000386615 0.000355713 -1 -1 -1 -1 -1 190 16 23400 11700 33739.5 1349.58 0.01 0.00300051 0.00265436 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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/home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62808 8 8 51 59 0 51 22 5 5 25 clb auto 22.7 MiB 0.01 241 211 352 90 254 8 61.3 MiB 0.00 0.00 2.56944 2.55689 -12.2592 -2.55689 nan 0.00 8.608e-05 7.7986e-05 0.0014657 0.0013411 -1 -1 -1 -1 -1 432 21 23400 23400 33739.5 1349.58 0.02 0.00627483 0.00552861 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.54 vpr 61.46 MiB -1 -1 -1 -1 7 0.06 -1 -1 32828 -1 -1 11 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62936 10 10 95 105 0 95 31 6 6 36 clb auto 22.3 MiB 0.01 521 440 511 77 404 30 61.5 MiB 0.01 0.00 2.69967 2.57044 -18.1695 -2.57044 nan 0.00 0.000151539 0.000138116 0.00236646 0.00218357 -1 -1 -1 -1 -1 938 24 165600 42900 61410.5 1705.85 0.05 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VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62288 3 2 5 7 0 5 6 3 3 9 -1 auto 22.2 MiB 0.00 15 15 15 11 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -0.887553 -0.443777 nan 0.00 1.209e-05 8.732e-06 9.1869e-05 7.2945e-05 -1 -1 -1 -1 -1 12 16 3900 3900 7855.82 872.868 0.00 0.00124012 0.00110096 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.38 vpr 61.18 MiB -1 -1 -1 -1 2 0.03 -1 -1 31868 -1 -1 1 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62648 5 3 9 12 0 9 9 3 3 9 -1 auto 22.5 MiB 0.00 26 26 27 24 0 3 61.2 MiB 0.00 0.00 0.70303 0.70303 -1.84984 -0.70303 nan 0.00 1.7006e-05 1.3134e-05 0.000130625 0.000109922 -1 -1 -1 -1 -1 19 17 3900 3900 7855.82 872.868 0.00 0.00148586 0.00131377 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.40 vpr 61.18 MiB -1 -1 -1 -1 3 0.03 -1 -1 31864 -1 -1 1 7 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62648 7 4 13 17 0 13 12 3 3 9 -1 auto 22.5 MiB 0.00 37 37 38 34 0 4 61.2 MiB 0.00 0.00 0.962283 0.962283 -3.07137 -0.962283 nan 0.00 2.1905e-05 1.7808e-05 0.000171216 0.000147331 -1 -1 -1 -1 -1 39 18 3900 3900 7855.82 872.868 0.00 0.00170731 0.00150491 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.41 vpr 61.19 MiB -1 -1 -1 -1 4 0.03 -1 -1 31864 -1 -1 1 9 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62656 9 5 17 22 0 17 15 3 3 9 -1 auto 22.9 MiB 0.00 48 48 51 43 0 8 61.2 MiB 0.00 0.00 1.22154 1.22154 -4.55216 -1.22154 nan 0.00 2.6838e-05 2.2089e-05 0.000214843 0.000189834 -1 -1 -1 -1 -1 65 18 3900 3900 7855.82 872.868 0.00 0.00202953 0.00177973 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.41 vpr 61.20 MiB -1 -1 -1 -1 4 0.03 -1 -1 31868 -1 -1 2 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62664 11 6 24 30 0 24 19 4 4 16 clb auto 22.5 MiB 0.00 96 81 219 61 139 19 61.2 MiB 0.00 0.00 1.37337 1.3375 -6.59285 -1.3375 nan 0.00 3.5886e-05 3.0342e-05 0.000510299 0.000442952 -1 -1 -1 -1 -1 131 14 7800 7800 17482.0 1092.63 0.01 0.00251022 0.00221932 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt index 1f6be016ab1..4ad63c55fd1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.79 vpr 67.81 MiB 0.06 9856 -1 -1 3 0.37 -1 -1 39772 -1 54808 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.13 821 70943 24958 34400 11585 67.8 MiB 0.24 0.00 2.51136 -219.195 -2.51136 2.51136 0.28 0.000896235 0.000803075 0.0731146 0.0664864 -1 -1 -1 -1 40 1499 25 5.66058e+06 4.21279e+06 333335. 2314.82 1.63 0.35542 0.319058 12666 64609 -1 1442 10 553 749 42115 14455 2.64494 2.64494 -235.699 -2.64494 0 0 419432. 2912.72 0.02 0.06 0.11 -1 -1 0.02 0.0374155 0.0350957 0.008441 0.2001 0.06777 0.7321 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 16.21 vpr 71.75 MiB 0.06 9856 -1 -1 15 0.50 -1 -1 38288 -1 56228 38 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73476 162 96 999 932 1 689 301 16 16 256 mult_36 auto 32.3 MiB 0.49 5426 96061 33445 54809 7807 71.8 MiB 1.03 0.02 21.3991 -1811.48 -21.3991 21.3991 0.51 0.00504368 0.00468153 0.493175 0.461597 -1 -1 -1 -1 56 11482 33 1.21132e+07 4.02797e+06 870502. 3400.40 8.42 2.47741 2.31569 26504 172068 -1 9223 22 3083 6041 811453 269172 22.8885 22.8885 -1951.66 -22.8885 0 0 1.11200e+06 4343.75 0.07 0.47 0.29 -1 -1 0.07 0.221232 0.208061 0.007874 0.3571 0.01689 0.626 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.21 odin 100.12 MiB 2.22 102528 -1 -1 3 0.20 -1 -1 34100 -1 52224 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68248 99 130 363 493 1 251 298 12 12 144 clb auto 27.9 MiB 0.07 2086 873 75918 23929 39390 12599 66.6 MiB 0.13 0.00 2.81842 2.17528 -220.25 -2.17528 2.17528 0.09 0.00057296 0.000536541 0.045254 0.042348 -1 -1 -1 -1 32 1783 21 5.66058e+06 4.21279e+06 281316. 1953.58 0.21 0.115911 0.106856 11950 52952 -1 1569 8 475 592 37949 12971 2.62567 2.62567 -236.989 -2.62567 0 0 345702. 2400.71 0.01 0.02 0.03 -1 -1 0.01 0.0148651 0.0139996 0.008359 0.1947 0.06177 0.7435 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 7.33 odin 87.38 MiB 2.02 89472 -1 -1 15 0.28 -1 -1 34648 -1 54320 39 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72896 162 96 999 932 1 692 302 16 16 256 mult_36 auto 31.6 MiB 0.22 9298 5609 93406 28941 57235 7230 71.2 MiB 0.37 0.01 25.0935 21.2697 -1792.21 -21.2697 21.2697 0.17 0.00167786 0.00157594 0.166256 0.156124 -1 -1 -1 -1 42 13435 49 1.21132e+07 4.08187e+06 666210. 2602.38 1.63 0.455209 0.425126 24208 131534 -1 10212 18 3382 6827 1034510 307036 22.5724 22.5724 -1934.15 -22.5724 0 0 835850. 3265.04 0.02 0.20 0.07 -1 -1 0.02 0.0801778 0.0759457 0.00765 0.3347 0.01582 0.6495 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt index d6f9144a21f..91c650b7642 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 66.34 MiB 0.08 10496 -1 -1 4 0.22 -1 -1 36740 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.07 425 2283 406 1804 73 66.3 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000792071 0.00065667 0.0233552 0.0207856 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.3 MiB 0.07 0.0694098 0.0624777 66.3 MiB -1 0.01 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.84 vpr 69.28 MiB 0.07 10496 -1 -1 5 0.19 -1 -1 36360 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70940 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.48 448 1927 352 1502 73 69.3 MiB 0.05 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.00080657 0.000690329 0.0283624 0.0258806 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.06 -1 -1 69.3 MiB 0.04 0.0633117 0.0585851 69.3 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.89 odin 167.25 MiB 2.94 171264 -1 -1 4 0.12 -1 -1 33084 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.00039432 0.000341138 0.0102726 0.00907409 -1 -1 -1 -1 434 4.56842 177 1.86316 730 1655 64750 15779 1.07788e+06 1.07788e+06 207176. 4228.08 23 4440 29880 -1 2.44651 2.32748 -175.142 -2.44651 0 0 0.02 -1 -1 65.7 MiB 0.03 0.0322281 0.0281216 65.7 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.73 odin 156.75 MiB 2.62 160512 -1 -1 5 0.11 -1 -1 33288 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69568 11 30 313 321 2 114 55 7 7 49 clb auto 28.6 MiB 0.19 671 455 1719 301 1356 62 67.9 MiB 0.02 0.00 2.73611 2.6413 -165.526 -2.6413 2.31106 0.00 0.000431787 0.000378246 0.0113226 0.0102357 -1 -1 -1 -1 571 5.28704 218 2.01852 192 380 9910 2908 1.07788e+06 754516 219490. 4479.39 12 5100 32136 -1 2.66069 2.29553 -166.559 -2.66069 0 0 0.02 -1 -1 67.9 MiB 0.02 0.031952 0.0291815 67.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt index 9c4fd28b84b..ced6ee7cc83 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 29.83 vpr 86.25 MiB 0.45 29568 -1 -1 4 2.98 -1 -1 43168 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88324 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.0 MiB 2.27 10985 240245 81936 130873 27436 86.3 MiB 2.86 0.03 4.42447 -2617.73 -4.42447 4.42447 0.89 0.00871072 0.007701 1.03653 0.893245 -1 -1 -1 -1 78 21148 33 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 13.92 4.09327 3.61448 52874 439520 -1 19015 17 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.98 0.77 -1 -1 0.19 0.584807 0.525478 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 21.80 odin 1.01 GiB 10.99 1063152 -1 -1 4 1.51 -1 -1 40168 -1 -1 165 193 5 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87924 193 205 2863 2789 1 1378 568 20 20 400 memory auto 45.9 MiB 1.01 22943 10817 247423 86121 133897 27405 85.9 MiB 1.12 0.01 6.47551 5.02579 -2678.97 -5.02579 5.02579 0.32 0.00374808 0.00338021 0.423272 0.380582 -1 -1 -1 -1 76 21112 34 2.07112e+07 1.16325e+07 2.02110e+06 5052.76 3.91 1.38132 1.25049 52074 423490 -1 19105 17 5044 13854 1088699 242536 5.48145 5.48145 -2895.27 -5.48145 -14.3689 -0.360359 2.51807e+06 6295.18 0.07 0.33 0.24 -1 -1 0.07 0.214376 0.201156 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt index 812f4d3bdb5..63f396f9727 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.96 vpr 71.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73224 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.52 4992 14048 2664 10357 1027 71.5 MiB 0.35 0.02 4.19211 -186.67 -4.19211 nan 0.00 0.00713555 0.00269028 0.139755 0.114328 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.22 -1 -1 71.5 MiB 0.32 0.294582 0.254721 71.5 MiB -1 0.05 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 2.24 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73336 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.64 4992 14048 2664 10357 1027 71.6 MiB 0.33 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00345084 0.002875 0.154792 0.13937 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.26 -1 -1 71.6 MiB 0.37 0.334856 0.303047 71.6 MiB -1 0.08 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 0.96 vpr 70.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71996 8 63 748 811 0 451 161 14 14 196 clb auto 31.2 MiB 0.24 7035 5048 13708 2494 10216 998 70.3 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.0012361 0.00107738 0.0505529 0.0454928 -1 -1 -1 -1 6826 15.1353 1836 4.07095 3768 15421 585680 92261 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17836 nan -185.935 -4.17836 0 0 0.08 -1 -1 70.3 MiB 0.19 0.141694 0.128755 70.3 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 0.91 vpr 69.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71608 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7035 5048 13708 2494 10216 998 69.9 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.00117606 0.00102769 0.0494933 0.0444045 -1 -1 -1 -1 6906 15.3126 1853 4.10865 3897 16323 609528 97595 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17947 nan -185.454 -4.17947 0 0 0.08 -1 -1 69.9 MiB 0.16 0.127311 0.115445 69.9 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt index ca94c478175..a43902b89ef 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.33 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.53 4993 17086 3593 12286 1207 71.5 MiB 0.39 0.01 3.65588 -160.421 -3.65588 nan 0.05 0.00324947 0.00265148 0.171741 0.145172 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.19 -1 -1 71.5 MiB 0.65 0.403427 0.354208 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.06 vpr 71.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72900 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.61 4933 15350 2970 11325 1055 71.2 MiB 0.33 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00354772 0.00306723 0.134491 0.114487 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.2 MiB 0.37 0.342443 0.304101 71.2 MiB -1 0.04 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 4.12 vpr 71.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73084 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.46 5048 17520 3917 12196 1407 71.4 MiB 0.41 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.0055915 0.00450451 0.174816 0.150375 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.22 -1 -1 71.4 MiB 0.70 0.438594 0.389856 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.79 vpr 71.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73092 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.34 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00371073 0.00310746 0.151921 0.128885 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.16 -1 -1 71.4 MiB 0.65 0.390878 0.342895 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.01 vpr 70.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72112 8 63 748 811 0 451 161 14 14 196 clb auto 31.2 MiB 0.23 7019 5149 19389 4557 13188 1644 70.4 MiB 0.16 0.00 5.27085 3.74489 -168.03 -3.74489 nan 0.02 0.00126033 0.00109349 0.0665406 0.0595916 -1 -1 -1 -1 7151 15.8559 1918 4.25277 4270 17535 1282134 224677 9.20055e+06 4.85046e+06 701736. 3580.29 23 16332 105598 -1 4.37015 nan -196.64 -4.37015 0 0 0.06 -1 -1 70.4 MiB 0.22 0.146899 0.133127 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 0.92 vpr 69.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71600 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7019 5029 15019 2779 11014 1226 69.9 MiB 0.13 0.00 5.64572 4.2713 -188.25 -4.2713 nan 0.00 0.00124937 0.00108276 0.0545594 0.0488954 -1 -1 -1 -1 7035 15.5987 1894 4.19956 3783 16134 598321 102284 9.20055e+06 4.85046e+06 701736. 3580.29 20 16332 105598 -1 4.48059 nan -193.333 -4.48059 0 0 0.06 -1 -1 69.9 MiB 0.19 0.141965 0.128041 69.9 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 1.71 vpr 70.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71984 8 63 748 811 0 451 161 14 14 196 clb auto 31.2 MiB 0.24 7019 5066 19826 4740 13454 1632 70.3 MiB 0.16 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00121598 0.00106627 0.0675193 0.0602983 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 70.3 MiB 0.22 0.145124 0.131162 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.68 vpr 70.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71980 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7019 5066 19826 4740 13454 1632 70.3 MiB 0.16 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00119569 0.00104348 0.0665483 0.0593856 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 70.3 MiB 0.22 0.143597 0.129548 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt index 73afad51c48..fecff9d091a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 2.09 vpr 71.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73036 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.3 MiB 0.32 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00299665 0.00251735 0.139481 0.119628 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.42 0.337391 0.298836 71.3 MiB -1 0.06 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 2.37 vpr 71.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73112 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.4 MiB 0.36 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00287338 0.00244407 0.145055 0.130505 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.23 -1 -1 71.4 MiB 0.57 0.403361 0.368877 71.4 MiB -1 0.07 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 0.93 vpr 69.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71600 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.24 7035 5098 13271 2309 10001 961 69.9 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00119598 0.00104626 0.0485432 0.0437081 -1 -1 -1 -1 7155 15.8647 1916 4.24834 4312 18456 674497 110334 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.9 MiB 0.18 0.128344 0.116744 69.9 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 0.91 vpr 70.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71984 8 63 748 811 0 451 161 14 14 196 clb auto 31.2 MiB 0.23 7035 5098 13271 2309 10001 961 70.3 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00124712 0.00108956 0.049401 0.0444125 -1 -1 -1 -1 7141 15.8337 1913 4.24168 4366 18775 685171 111801 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 70.3 MiB 0.17 0.12868 0.116884 70.3 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt index d51a6534507..d1a8675565f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 1.14 vpr 59.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61108 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 20.9 MiB 0.25 70 15 4 10 1 59.7 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000126011 0.000111009 0.000872338 0.000798258 -1 -1 -1 -1 25 262 18 133321 74067 -1 -1 0.48 0.0703731 0.0607281 1252 5405 -1 274 13 122 122 23159 13821 1.78919 1.78919 -18.223 -1.78919 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.00593831 0.00529293 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +slicem.xml carry_chain.blif common 0.55 vpr 58.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60200 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 19.9 MiB 0.14 70 70 15 4 10 1 58.8 MiB 0.00 0.00 0.552322 0.523836 -5.19346 -0.523836 0.523836 0.00 6.816e-05 6.1015e-05 0.000550461 0.000511682 -1 -1 -1 -1 27 337 26 133321 74067 -1 -1 0.09 0.0140307 0.0116797 1284 5874 -1 249 10 84 84 16544 9291 1.47622 1.47622 -16.7882 -1.47622 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00286435 0.00259865 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt index 2974b610be2..5dba66ce28c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.30 vpr 59.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60508 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.6 MiB 0.00 31 59 13 43 3 59.1 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.5462e-05 2.8363e-05 0.000299521 0.0002448 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00397217 0.00338578 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00197845 0.00188555 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml ndff.blif common 0.28 vpr 57.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58932 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.8 MiB 0.00 36 31 59 13 43 3 57.6 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8904e-05 1.4655e-05 0.00017596 0.000143236 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00219197 0.00184136 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00106544 0.00100507 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt index 936401071c3..b163155ac32 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.54 vpr 68.95 MiB 0.06 10496 -1 -1 5 0.18 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70604 11 30 313 321 2 114 55 7 7 49 clb auto 29.5 MiB 0.39 459 2031 574 1374 83 68.9 MiB 0.04 0.00 4.6413 0 0 4.31525 0.00 0.000717512 0.000626394 0.019463 0.0174272 -1 -1 -1 -1 569 5.26852 227 2.10185 207 393 9602 2945 1.07788e+06 754516 219490. 4479.39 7 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 68.9 MiB 0.06 0.0634405 0.0562085 68.9 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.58 odin 157.12 MiB 2.51 160896 -1 -1 5 0.11 -1 -1 33284 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69888 11 30 313 321 2 115 55 7 7 49 clb auto 28.4 MiB 0.17 671 430 3071 674 1846 551 68.2 MiB 0.03 0.00 4.73611 4.6413 0 0 4.32062 0.00 0.000379979 0.000346033 0.014831 0.0136619 -1 -1 -1 -1 573 5.25688 232 2.12844 279 564 13433 4035 1.07788e+06 754516 219490. 4479.39 9 5100 32136 -1 4.69675 4.35776 0 0 -164.736 -1.707 0.02 -1 -1 68.2 MiB 0.02 0.0309486 0.0287174 68.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index f1ae2610488..e9412340705 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.44 vpr 65.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66884 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.01 21 30 5 21 4 65.3 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.01 3.9163e-05 3.0734e-05 0.00023521 0.000191167 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00213897 0.00197887 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00188153 0.00176769 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.42 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66820 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.3 MiB 0.00 0.00 0.571 0 0 0.571 0.01 6.1332e-05 3.1443e-05 0.00028123 0.000216755 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00219985 0.00199813 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0028018 0.00269609 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.40 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66764 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 21 30 5 22 3 65.2 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.8778e-05 3.099e-05 0.000214053 0.000176854 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00219902 0.00204346 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00216696 0.00200612 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.40 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.3 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.3301e-05 3.3225e-05 0.000258104 0.000204952 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00214578 0.0019473 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00224405 0.00207678 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.38 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.4 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 5.0024e-05 3.2956e-05 0.000205951 0.000157313 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00254156 0.00219599 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0022282 0.00180897 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.40 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.00 21 30 5 23 2 65.4 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 5.2455e-05 4.3444e-05 0.00030806 0.000256078 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.01 0.00225516 0.00206503 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00187829 0.00175106 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.31 vpr 63.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 21 4 63.9 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 1.9532e-05 1.4985e-05 0.000133208 0.000107724 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.00115214 0.00105112 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00103168 0.000957693 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.33 vpr 63.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 5 3 11 14 2 9 10 4 4 16 clb auto 25.3 MiB 0.00 22 22 30 6 14 10 63.9 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.00 1.7929e-05 1.4042e-05 0.000128716 0.000105881 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00119508 0.00109064 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00110004 0.00102934 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.31 vpr 64.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 22 3 64.2 MiB 0.00 0.00 0.646297 0.646297 -2.19033 -0.646297 0.571 0.00 2.1502e-05 1.6408e-05 0.000150491 0.000121289 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00123245 0.00111483 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00112413 0.00104219 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.33 vpr 63.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65340 5 3 11 14 2 9 10 4 4 16 clb auto 25.2 MiB 0.00 22 21 30 7 16 7 63.8 MiB 0.00 0.00 1.64604 1.6463 -5.31965 -1.6463 0.571 0.00 2.3243e-05 1.7592e-05 0.000161496 0.000129112 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.00125222 0.00112683 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00115066 0.00105296 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.30 vpr 64.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 22 30 8 15 7 64.2 MiB 0.00 0.00 1.44967 1.44967 -2.9103 -1.44967 0.571 0.00 2.7152e-05 1.8078e-05 0.000163344 0.000129482 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.0014976 0.00130776 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00117943 0.00108545 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.33 vpr 63.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 23 2 63.9 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.00 2.1693e-05 1.7097e-05 0.000167017 0.000140121 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.00122871 0.00112733 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00114705 0.00106508 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt index 5a4eb2784da..99931973f06 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.55 vpr 66.09 MiB 0.01 7168 -1 -1 1 0.03 -1 -1 33640 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67672 9 8 75 70 1 36 20 5 5 25 clb auto 27.1 MiB 0.69 94 695 228 460 7 66.1 MiB 0.01 0.00 2.48207 -26.1618 -2.48207 2.48207 0.03 0.000181733 0.000161557 0.00585234 0.0052913 -1 -1 -1 -1 52 134 15 151211 75605.7 63348.9 2533.96 0.11 0.0432562 0.0374575 2316 10503 -1 114 8 106 124 3566 1793 2.40307 2.40307 -27.5996 -2.40307 0 0 82390.3 3295.61 0.00 0.01 0.02 -1 -1 0.00 0.0069119 0.0064541 13 18 19 7 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.05 vpr 66.50 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33588 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68092 11 10 108 97 1 47 23 4 4 16 clb auto 27.2 MiB 3.14 125 439 123 270 46 66.5 MiB 0.01 0.00 3.45122 -41.5692 -3.45122 3.45122 0.01 0.000220655 0.000197533 0.0046684 0.00428671 -1 -1 -1 -1 30 238 26 50403.8 50403.8 19887.8 1242.99 0.18 0.0734016 0.0633094 992 2748 -1 177 19 176 222 5882 3651 3.90204 3.90204 -49.9067 -3.90204 0 0 24232.7 1514.54 0.00 0.02 0.00 -1 -1 0.00 0.013296 0.0120352 15 27 29 8 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 5.44 vpr 66.68 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33700 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68284 13 12 149 129 1 69 32 6 6 36 clb auto 27.4 MiB 4.03 199 682 229 444 9 66.7 MiB 0.02 0.00 3.51316 -53.1567 -3.51316 3.51316 0.06 0.000399911 0.000364812 0.00775114 0.00715794 -1 -1 -1 -1 40 438 24 403230 176413 88484.8 2457.91 0.50 0.147128 0.127344 3734 16003 -1 329 29 379 534 18280 7787 3.72931 3.72931 -57.4119 -3.72931 0 0 110337. 3064.92 0.00 0.02 0.01 -1 -1 0.00 0.0175574 0.0158074 25 38 42 9 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.95 vpr 66.76 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33776 -1 -1 6 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 15 14 196 165 1 93 35 5 5 25 clb auto 27.2 MiB 2.85 306 947 216 708 23 66.8 MiB 0.02 0.00 3.70693 -62.6491 -3.70693 3.70693 0.02 0.000376121 0.000333163 0.00931262 0.00852228 -1 -1 -1 -1 44 480 22 151211 151211 54748.7 2189.95 0.20 0.0954411 0.083284 2196 9177 -1 392 18 349 466 14859 7098 4.20858 4.20858 -72.9456 -4.20858 0 0 71025.7 2841.03 0.00 0.03 0.01 -1 -1 0.00 0.0211201 0.0192846 36 51 57 11 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.23 vpr 67.12 MiB 0.01 7040 -1 -1 1 0.06 -1 -1 33688 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68736 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 7.05 397 2054 481 1553 20 67.1 MiB 0.04 0.00 3.86806 -74.2346 -3.86806 3.86806 0.03 0.00048716 0.000431817 0.0193024 0.0173986 -1 -1 -1 -1 50 602 24 151211 126010 61632.8 2465.31 0.24 0.130358 0.114428 2268 9834 -1 534 19 619 1012 32161 14755 4.95834 4.95834 -93.7979 -4.95834 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0271021 0.0248239 44 66 75 13 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.18 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33916 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 19 18 308 249 1 137 45 6 6 36 clb auto 27.7 MiB 5.92 455 2365 460 1885 20 67.2 MiB 0.03 0.00 4.8546 -99.6039 -4.8546 4.8546 0.03 0.000494067 0.000457319 0.0145592 0.0132203 -1 -1 -1 -1 62 737 27 403230 201615 131137. 3642.71 0.40 0.139917 0.121866 4226 23319 -1 634 19 613 910 31131 12187 5.08188 5.08188 -101.573 -5.08188 0 0 160622. 4461.73 0.00 0.04 0.02 -1 -1 0.00 0.0328006 0.0301511 55 83 93 14 0 0 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 2.20 vpr 64.73 MiB 1.09 63360 -1 -1 1 0.02 -1 -1 30140 -1 -1 3 9 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 9 8 75 70 1 34 20 5 5 25 clb auto 25.9 MiB 0.35 123 90 614 218 387 9 64.7 MiB 0.01 0.00 2.48207 2.48207 -27.847 -2.48207 2.48207 0.01 9.1142e-05 8.2526e-05 0.00284948 0.00263576 -1 -1 -1 -1 44 151 38 151211 75605.7 54748.7 2189.95 0.07 0.0244535 0.0205798 2196 9177 -1 119 9 90 109 2746 1383 2.64007 2.64007 -30.0799 -2.64007 0 0 71025.7 2841.03 0.00 0.01 0.01 -1 -1 0.00 0.00398542 0.00370067 13 18 19 7 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 3.56 vpr 64.87 MiB 1.21 64512 -1 -1 1 0.02 -1 -1 30152 -1 -1 2 11 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66424 11 10 108 97 1 49 23 4 4 16 clb auto 25.6 MiB 1.61 144 130 311 98 183 30 64.9 MiB 0.01 0.00 3.45122 3.45122 -42.5068 -3.45122 3.45122 0.01 0.000122211 0.00011105 0.00236027 0.00222968 -1 -1 -1 -1 38 205 31 50403.8 50403.8 23356.0 1459.75 0.07 0.0310065 0.0263469 1064 3436 -1 155 11 118 137 3972 2416 3.45122 3.45122 -47.4838 -3.45122 0 0 29887.0 1867.94 0.00 0.01 0.00 -1 -1 0.00 0.0060327 0.00557363 15 27 29 8 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 4.85 vpr 65.21 MiB 1.19 64896 -1 -1 1 0.02 -1 -1 29976 -1 -1 7 13 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66780 13 12 149 129 1 68 32 6 6 36 clb auto 25.9 MiB 2.80 259 213 732 224 501 7 65.2 MiB 0.01 0.00 3.50789 3.50789 -53.116 -3.50789 3.50789 0.02 0.000156429 0.000142731 0.00389953 0.0036633 -1 -1 -1 -1 56 371 18 403230 176413 117789. 3271.93 0.11 0.0381154 0.0327749 4086 21443 -1 348 11 215 316 13445 5456 3.49231 3.49231 -56.5872 -3.49231 0 0 149557. 4154.36 0.00 0.01 0.01 -1 -1 0.00 0.00764244 0.0070994 25 38 42 9 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.35 vpr 65.61 MiB 1.06 64896 -1 -1 1 0.02 -1 -1 30188 -1 -1 7 15 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67184 15 14 196 165 1 92 36 6 6 36 clb auto 26.3 MiB 1.37 403 300 744 201 529 14 65.6 MiB 0.01 0.00 3.89713 3.62628 -64.1883 -3.62628 3.62628 0.02 0.000203778 0.000186501 0.00460964 0.00434602 -1 -1 -1 -1 36 756 35 403230 176413 82124.2 2281.23 0.15 0.0535333 0.0461786 3630 14583 -1 550 23 686 1034 36633 15919 4.66971 4.66971 -82.2718 -4.66971 0 0 100559. 2793.30 0.00 0.02 0.01 -1 -1 0.00 0.0134913 0.0122142 37 51 57 11 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 5.28 vpr 65.84 MiB 1.14 65664 -1 -1 1 0.03 -1 -1 30264 -1 -1 5 17 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67420 17 16 251 206 1 120 38 5 5 25 clb auto 25.9 MiB 3.23 489 407 2495 683 1791 21 65.8 MiB 0.02 0.00 3.91442 3.88071 -74.5105 -3.88071 3.88071 0.01 0.000246257 0.000225884 0.0123032 0.011433 -1 -1 -1 -1 50 657 26 151211 126010 61632.8 2465.31 0.13 0.0697365 0.0608136 2268 9834 -1 542 20 727 1123 36489 16871 4.71841 4.71841 -93.0154 -4.71841 0 0 77226.2 3089.05 0.00 0.02 0.01 -1 -1 0.00 0.0149146 0.0135832 45 66 75 13 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 5.52 vpr 65.22 MiB 1.10 66432 -1 -1 1 0.03 -1 -1 30340 -1 -1 7 19 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 19 18 308 249 1 134 44 6 6 36 clb auto 25.6 MiB 3.44 593 481 1815 377 1429 9 65.2 MiB 0.02 0.00 4.92231 4.8546 -99.9033 -4.8546 4.8546 0.02 0.000291676 0.00026758 0.00958251 0.00895714 -1 -1 -1 -1 68 826 27 403230 176413 143382. 3982.83 0.18 0.0751968 0.0658061 4366 25715 -1 720 17 520 914 34542 12871 4.61234 4.61234 -99.3851 -4.61234 0 0 176130. 4892.50 0.00 0.02 0.02 -1 -1 0.00 0.0164293 0.0151379 53 83 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt index 8a6305788b3..3046d61aebd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 17.34 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.93 4.894e-05 4.1022e-05 0.00272802 0.000370563 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00475066 0.00224296 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00235645 0.00226006 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common 4.55 vpr 57.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58916 6 7 19 26 0 19 26 3 3 9 -1 auto 19.4 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.82 2.1746e-05 1.7637e-05 0.000209106 0.000168705 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00145582 0.00132483 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00105587 0.000992599 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt index 518626ca870..792e122ceda 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.35 vpr 58.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60280 2 2 4 5 0 4 5 3 3 9 -1 auto 20.6 MiB 0.00 8 12 0 0 12 58.9 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7797e-05 1.2853e-05 0.000104532 7.7041e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.00210372 0.00170648 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.0014857 0.00144705 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +heterogeneous_tile.xml sub_tile_directs.blif common 0.28 vpr 56.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58116 2 2 4 5 0 4 5 3 3 9 -1 auto 18.4 MiB 0.00 8 8 12 0 0 12 56.8 MiB 0.00 0.00 1.899 1.899 -3.798 -1.899 nan 0.01 9.975e-06 6.727e-06 7.0576e-05 5.1334e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.00 0.00125353 0.00115577 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000874998 0.000839109 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt index 2adfcb2953c..06a46bcee1a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.13 vpr 66.94 MiB 0.07 9984 -1 -1 3 0.37 -1 -1 39768 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68544 99 74 307 381 1 199 193 8 8 64 io memory auto 27.3 MiB 0.07 869 22473 4565 15889 2019 66.9 MiB 0.09 0.00 2.15432 -215.614 -2.15432 2.15432 0.09 0.000919068 0.000833008 0.0321902 0.029066 -1 -1 -1 -1 32 1554 36 2.23746e+06 1.57199e+06 106908. 1670.44 0.41 0.172041 0.155343 4378 18911 -1 1152 12 699 1089 60199 20903 2.21433 2.21433 -220.084 -2.21433 0 0 130676. 2041.82 0.01 0.06 0.03 -1 -1 0.01 0.0316397 0.0293511 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.49 odin 99.75 MiB 2.08 102144 -1 -1 3 0.21 -1 -1 34100 -1 -1 19 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67276 99 74 307 381 1 197 193 8 8 64 io memory auto 25.6 MiB 0.03 1382 812 18574 3262 13483 1829 65.7 MiB 0.04 0.00 2.24422 2.11879 -214.824 -2.11879 2.11879 0.04 0.00043653 0.000403884 0.0169436 0.0157473 -1 -1 -1 -1 34 1407 30 2.23746e+06 1.57199e+06 111309. 1739.21 0.29 0.114174 0.102974 4442 19988 -1 1106 23 739 1099 89273 34816 2.38477 2.38477 -220.891 -2.38477 0 0 136889. 2138.88 0.00 0.04 0.01 -1 -1 0.00 0.0218706 0.0199682 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt index b4f05d4d127..67c1e31e1bc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 1.31 vpr 68.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70324 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.20 399 703 140 536 27 68.7 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000310541 0.000262563 0.00936798 0.00854482 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.46 0.175458 0.152388 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0280432 0.0256776 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.18 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70172 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.5 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000328824 0.000280405 0.00830952 0.00754823 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.31 0.10752 0.0932813 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0371511 0.0342602 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 4.10 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70728 10 10 168 178 1 162 111 14 14 196 clb auto 29.4 MiB 0.90 1467 5165 686 4267 212 69.1 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.39 0.000594399 0.00050939 0.0158932 0.0140866 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.204118 0.178235 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.04 0.10 0.10 -1 -1 0.04 0.0402804 0.0376719 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.27 vpr 68.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70312 10 10 168 178 1 75 33 7 7 49 clb auto 29.2 MiB 0.22 414 605 98 486 21 68.7 MiB 0.02 0.00 2.40687 -27.3475 -2.40687 2.40687 0.06 0.000598343 0.000517434 0.011833 0.0108149 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.28 0.112886 0.100348 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.05 0.02 -1 -1 0.00 0.0342617 0.0315172 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.32 vpr 68.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70636 10 10 168 178 1 163 124 14 14 196 clb auto 29.3 MiB 0.71 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.24 0.000341831 0.000287957 0.0139093 0.0123738 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.36 0.0484505 0.0438885 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.07 -1 -1 0.03 0.0262959 0.0240352 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.51 vpr 68.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70184 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000592996 0.000513744 0.0148871 0.0136124 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.60 0.233947 0.201424 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0337396 0.0309919 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.26 vpr 68.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69936 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.14 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000607215 0.000528624 0.0138198 0.0125584 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.45 0.178959 0.157093 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0299846 0.0274172 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 4.05 vpr 68.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70468 10 10 168 178 1 162 111 14 14 196 clb auto 29.3 MiB 0.89 1467 5165 686 4267 212 68.8 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.31 0.000662054 0.000579378 0.0167691 0.0149922 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.58 0.235946 0.204687 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.12 -1 -1 0.03 0.0296338 0.0273566 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.49 vpr 68.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69976 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.21 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000326035 0.000277526 0.0147842 0.0134826 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.61 0.214908 0.181228 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.02 -1 -1 0.00 0.0279877 0.0256826 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30628 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.7 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.11 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.11 vpr 30.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31020 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.11 vpr 30.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30716 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml styr.blif common_--target_ext_pin_util_1 0.71 vpr 67.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68820 10 10 168 178 1 75 32 6 6 36 clb auto 27.9 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.01 0.000307944 0.000276032 0.00676594 0.00627534 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0533675 0.0468966 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0175152 0.0161192 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.75 vpr 67.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68820 10 10 168 178 1 75 32 6 6 36 clb auto 27.5 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.00031604 0.000283289 0.00712143 0.00664783 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0548186 0.0483415 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.020456 0.018652 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 1.53 vpr 67.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69336 10 10 168 178 1 162 110 14 14 196 clb auto 28.0 MiB 0.43 2218 1472 5633 779 4632 222 67.7 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.15 0.000304349 0.000273692 0.0088502 0.00811274 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.27 0.0479021 0.0422392 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.02 0.03 0.04 -1 -1 0.02 0.013483 0.0124375 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.77 vpr 67.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68892 10 10 168 178 1 73 34 7 7 49 clb auto 27.5 MiB 0.13 556 403 749 133 594 22 67.3 MiB 0.01 0.00 2.47538 2.3678 -27.2356 -2.3678 2.3678 0.02 0.0003094 0.000282354 0.00717457 0.00670075 -1 -1 -1 -1 28 1121 29 1.07788e+06 754516 79600.7 1624.51 0.14 0.0552858 0.0488082 3864 14328 -1 1032 22 640 2278 94416 33063 2.98849 2.98849 -34.8096 -2.98849 0 0 95067.4 1940.15 0.00 0.04 0.01 -1 -1 0.00 0.0204833 0.0186535 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 1.53 vpr 67.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69248 10 10 168 178 1 163 124 14 14 196 clb auto 28.3 MiB 0.47 2325 1534 6922 992 5667 263 67.6 MiB 0.03 0.00 4.16044 3.06133 -37.5377 -3.06133 3.06133 0.16 0.000326442 0.000288594 0.0112173 0.010305 -1 -1 -1 -1 20 3156 16 9.20055e+06 5.60498e+06 295730. 1508.82 0.17 0.0294748 0.0269576 18004 60473 -1 3023 14 646 2892 171027 37325 3.649 3.649 -45.9039 -3.649 0 0 387483. 1976.95 0.01 0.04 0.03 -1 -1 0.01 0.0139433 0.0127176 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 0.71 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68816 10 10 168 178 1 75 32 6 6 36 clb auto 27.9 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000314617 0.000282107 0.00692448 0.00646733 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0534945 0.0471471 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0176284 0.0162169 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 0.69 vpr 66.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68176 10 10 168 178 1 75 32 6 6 36 clb auto 26.9 MiB 0.11 467 424 582 89 470 23 66.6 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.01 0.000305919 0.000274687 0.00679179 0.00634009 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0535061 0.0471986 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0175573 0.0161405 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 1.49 vpr 67.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69192 10 10 168 178 1 162 110 14 14 196 clb auto 28.3 MiB 0.41 2218 1472 5633 779 4632 222 67.6 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.15 0.000318412 0.000287457 0.00903161 0.00829414 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.26 0.0468353 0.0413059 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.01 0.03 0.04 -1 -1 0.01 0.0128862 0.0118738 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 0.71 vpr 67.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68824 10 10 168 178 1 75 32 6 6 36 clb auto 27.9 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.01 0.000318255 0.000286123 0.00690877 0.00645849 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0541523 0.0478013 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0177266 0.0163392 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.09 vpr 28.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28936 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.8 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.09 vpr 29.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 29704 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 27.5 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.09 vpr 28.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28964 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 27.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 28.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 29320 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 27.1 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt index 95f2081009b..97bcad685cb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 9.08 vpr 75.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77084 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.8 MiB 4.29 8858 177806 51921 111135 14750 75.3 MiB 1.45 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00692729 0.00619106 0.572476 0.497763 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.34 0.862195 0.757255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 4.10 vpr 74.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 118 229 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76392 229 197 2152 2349 1 1012 544 16 16 256 io auto 34.6 MiB 2.04 13816 8635 175845 51740 110676 13429 74.6 MiB 0.62 0.01 3.6187 2.93018 -676.548 -2.93018 2.93018 0.00 0.00285906 0.00253098 0.244304 0.219997 -1 -1 -1 -1 -1 11066 15 1.05632e+07 6.35949e+06 4.24953e+06 16599.7 0.18 0.389441 0.356177 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt index a285dc5eca4..86b1be0aab8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.34 vpr 67.74 MiB 0.06 9856 -1 -1 3 0.39 -1 -1 39776 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69364 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.29 0.00 2.23767 -220.613 -2.23767 2.23767 0.27 0.00107588 0.000959454 0.0879605 0.0803385 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 0.81 0.341856 0.310926 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.05 0.14 -1 -1 0.03 0.0261531 0.0245164 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.91 odin 100.12 MiB 2.20 102528 -1 -1 3 0.20 -1 -1 34288 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68344 99 130 363 493 1 252 298 12 12 144 clb auto 27.5 MiB 0.07 2018 885 69948 23010 34855 12083 66.7 MiB 0.12 0.00 2.57832 2.17528 -217.156 -2.17528 2.17528 0.09 0.000560638 0.000524271 0.0428473 0.0401199 -1 -1 -1 -1 40 1646 17 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.159079 0.1459 12666 64609 -1 1625 10 525 650 46110 15051 2.57635 2.57635 -244.199 -2.57635 0 0 419432. 2912.72 0.01 0.02 0.04 -1 -1 0.01 0.0167278 0.0157148 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt index ddf76e6dee9..61db489ac85 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.16 vpr 67.80 MiB 0.06 9984 -1 -1 3 0.37 -1 -1 39748 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.14 877 59998 22493 27317 10188 67.8 MiB 0.17 0.00 2.17528 -133.517 -2.17528 2.17528 0.25 0.000598743 0.00053199 0.0416228 0.0366674 -1 -1 -1 -1 40 1685 15 5.66058e+06 4.21279e+06 333335. 2314.82 1.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.61 odin 100.12 MiB 2.11 102528 -1 -1 3 0.19 -1 -1 34096 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67704 99 130 363 493 1 252 298 12 12 144 clb auto 27.3 MiB 0.06 2007 832 63978 23229 30524 10225 66.1 MiB 0.09 0.00 2.23767 2.17638 -131.403 -2.17638 2.17638 0.09 0.000333564 0.000306163 0.0239387 0.0220541 -1 -1 -1 -1 40 1539 8 5.66058e+06 4.21279e+06 333335. 2314.82 0.44 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt index 4503f0925f9..af9a878e7be 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.64 vpr 67.62 MiB 0.06 9856 -1 -1 3 0.30 -1 -1 39896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69248 99 130 363 493 1 252 298 12 12 144 clb auto 28.5 MiB 0.14 956 73928 27133 34341 12454 67.6 MiB 0.26 0.00 2.30557 0 0 2.30557 0.25 0.000962793 0.000867177 0.0597068 0.0524058 -1 -1 -1 -1 38 1840 8 5.66058e+06 4.21279e+06 319130. 2216.18 1.37 0.282428 0.244945 12522 62564 -1 1734 8 415 510 29213 8865 2.61298 2.61298 0 0 0 0 406292. 2821.48 0.02 0.03 0.09 -1 -1 0.02 0.0187719 0.0170722 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 2.01 odin 99.38 MiB 0.18 101760 -1 -1 3 0.20 -1 -1 33348 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67932 99 130 363 493 1 253 298 12 12 144 clb auto 27.5 MiB 0.07 1922 792 82883 30333 38996 13554 66.3 MiB 0.12 0.00 2.3756 2.31285 0 0 2.31285 0.09 0.000342166 0.000313838 0.0308764 0.0284297 -1 -1 -1 -1 38 1683 10 5.66058e+06 4.21279e+06 319130. 2216.18 0.44 0.205871 0.176164 12522 62564 -1 1509 8 399 488 29742 9782 3.03498 3.03498 0 0 0 0 406292. 2821.48 0.01 0.02 0.04 -1 -1 0.01 0.00956584 0.00877781 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt index 0a5e59f0296..60debff32f8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.62 vpr 67.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68616 5 3 11 14 2 9 10 4 4 16 clb auto 28.6 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8501e-05 3.4711e-05 0.00027851 0.000219913 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00215999 0.00198392 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181366 0.00173531 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.62 vpr 67.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68636 5 3 11 14 2 9 10 4 4 16 clb auto 28.5 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.1152e-05 3.666e-05 0.000287379 0.000227035 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.03 0.0023614 0.00216487 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.0022135 0.00167838 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.55 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68936 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.7208e-05 4.2383e-05 0.000322556 0.000257546 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.02 0.00215648 0.00197387 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181267 0.00173458 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.37 vpr 65.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67352 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.00 24 21 30 9 19 2 65.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3433e-05 1.6316e-05 0.000167701 0.000131993 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00124098 0.00112929 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00103978 0.000979331 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.38 vpr 66.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67744 5 3 11 14 2 9 10 4 4 16 clb auto 27.5 MiB 0.00 24 21 30 9 19 2 66.2 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.4371e-05 1.7073e-05 0.000167678 0.000133091 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00122278 0.00111533 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00104402 0.000992025 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.41 vpr 65.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67356 5 3 11 14 2 9 10 4 4 16 clb auto 27.5 MiB 0.00 24 21 30 9 19 2 65.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3581e-05 1.6396e-05 0.000163408 0.000128983 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00126469 0.0011518 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00112382 0.00106571 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt index 9d457582f18..1814e2bfbd5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.68 vpr 69.25 MiB 0.08 10496 -1 -1 5 0.17 -1 -1 36364 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70908 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.39 448 1927 352 1502 73 69.2 MiB 0.04 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000798161 0.000674358 0.0213182 0.0191108 -1 -1 -1 -1 -1 595 8 1.07788e+06 754516 219490. 4479.39 0.04 0.060298 0.0550487 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 4.79 odin 156.75 MiB 3.12 160512 -1 -1 5 0.11 -1 -1 33284 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69568 11 30 313 321 2 114 55 7 7 49 clb auto 28.3 MiB 0.18 671 455 1719 301 1356 62 67.9 MiB 0.02 0.00 2.73611 2.6413 -165.526 -2.6413 2.31106 0.00 0.000433259 0.000381809 0.011092 0.0100284 -1 -1 -1 -1 -1 571 12 1.07788e+06 754516 219490. 4479.39 0.02 0.0308004 0.0280931 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt index 070113b9371..f78c9ca7563 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.31 vpr 66.76 MiB 0.06 10368 -1 -1 4 0.22 -1 -1 36924 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 425 2283 406 1804 73 66.8 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000550429 0.00044745 0.0205892 0.0175295 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0715823 0.0554655 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.35 vpr 67.11 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36664 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68720 11 30 262 292 2 99 60 7 7 49 clb auto 27.5 MiB 0.09 425 2283 406 1804 73 67.1 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000592669 0.000483133 0.0176652 0.0153201 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.08 0.0695138 0.0618702 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.40 vpr 66.21 MiB 0.07 10368 -1 -1 4 0.18 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67804 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000259913 0.000168736 0.00804711 0.00632437 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.05 0.0326926 0.0257255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.40 vpr 66.24 MiB 0.07 10368 -1 -1 4 0.22 -1 -1 36412 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67828 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000820125 0.000270462 0.0105947 0.00836537 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0358221 0.028376 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 3.52 odin 166.88 MiB 2.58 170880 -1 -1 4 0.12 -1 -1 33100 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000407927 0.000352794 0.0103629 0.00913612 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.03 0.0329737 0.0288413 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 3.51 odin 167.25 MiB 2.59 171264 -1 -1 4 0.12 -1 -1 33100 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000396579 0.000343532 0.0101806 0.00898166 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.03 0.0321781 0.0281256 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 3.92 odin 167.25 MiB 2.91 171264 -1 -1 4 0.12 -1 -1 33076 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67276 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.03 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 7.0829e-05 2.2318e-05 0.00621115 0.00447324 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.03 0.0212245 0.0160265 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 3.38 odin 167.25 MiB 2.47 171264 -1 -1 4 0.12 -1 -1 33108 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.01 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000417801 7.7923e-05 0.00452636 0.00335783 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.02 0.016299 0.0118717 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt index ec4372e5ea5..5ebdbecff03 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 76.86 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215732 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.5 MiB 14.49 75097 245792 47628 188491 9673 1158.4 MiB 19.32 0.31 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0645942 0.0566793 4.57717 3.66743 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 8.99 -1 -1 1158.4 MiB 6.77 7.11559 5.86421 1158.4 MiB -1 3.90 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 32.94 vpr 1.16 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1215300 13 29 26295 20086 1 12646 791 39 29 1131 LAB auto 1077.6 MiB 7.56 231619 75107 234775 43541 180854 10380 1154.8 MiB 5.78 0.08 5.55061 5.16398 -5504.03 -4.16398 2.86102 0.00 0.022899 0.0201602 1.65582 1.36851 87307 6.90501 21230 1.67906 25811 34329 9106433 1637889 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.36451 2.98815 -5707.14 -4.36451 0 0 3.12 -1 -1 1154.8 MiB 2.51 2.68373 2.2771 1154.8 MiB -1 1.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt index 9097fbde85d..ea5a62166c3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 18.00 vpr 70.38 MiB 0.05 10112 -1 -1 6 0.25 -1 -1 38052 -1 -1 15 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72072 66 96 1000 687 1 578 192 18 18 324 mult_27 auto 31.1 MiB 2.15 5241 46091 14804 26339 4948 70.4 MiB 0.71 0.01 16.7702 -967.772 -16.7702 16.7702 0.75 0.00350611 0.00326694 0.374139 0.351063 -1 -1 -1 -1 54 12671 42 6.4517e+06 1.13409e+06 1.49609e+06 4617.55 10.37 1.47511 1.37701 50360 316156 -1 11227 19 3612 7762 1892477 579383 16.9221 16.9221 -1089.8 -16.9221 0 0 1.91711e+06 5917.01 0.13 0.79 0.45 -1 -1 0.13 0.185679 0.177041 133 202 146 33 66 33 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 8.84 odin 81.00 MiB 1.62 82944 -1 -1 6 0.10 -1 -1 34308 -1 -1 16 66 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70700 66 96 1000 687 1 578 193 18 18 324 mult_27 auto 29.7 MiB 0.88 8817 5194 44753 13259 26140 5354 69.0 MiB 0.26 0.00 17.614 16.4128 -968.178 -16.4128 16.4128 0.28 0.00142532 0.00134186 0.124539 0.117372 -1 -1 -1 -1 56 13393 29 6.4517e+06 1.15929e+06 1.55150e+06 4788.57 3.94 0.460824 0.429459 50684 323660 -1 11784 18 3706 7635 1966406 594465 16.8068 16.8068 -1080.85 -16.8068 0 0 1.95585e+06 6036.58 0.05 0.30 0.16 -1 -1 0.05 0.0694977 0.0659629 133 202 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt index 9b26c986ccf..ec7b2e0c03c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.53 vpr 65.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66664 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.03 88 59 31 28 0 65.1 MiB 0.01 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.00022667 0.0001997 0.00145978 0.00134015 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.01 -1 -1 65.1 MiB 0.01 0.0151269 0.0141345 65.1 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.49 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000166651 0.000146123 0.00118945 0.00110009 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.0110046 0.0100571 65.2 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.25 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66768 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000189994 0.000167385 0.00110293 0.00101544 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.2 MiB 0.03 -1 -1 65.2 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.27 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000187343 0.000161123 0.00133988 0.00123837 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.2 MiB 0.04 -1 -1 65.2 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.18 vpr 63.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65184 6 8 39 47 1 20 17 5 5 25 clb auto 25.3 MiB 0.01 107 88 59 31 28 0 63.7 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 7.9799e-05 7.1099e-05 0.000712939 0.000670565 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.7 MiB 0.01 0.00498597 0.004445 63.7 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.18 vpr 63.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65460 6 8 39 47 1 20 17 5 5 25 clb auto 25.2 MiB 0.01 107 88 59 31 28 0 63.9 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 8.1571e-05 7.2642e-05 0.000740217 0.000697213 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.9 MiB 0.01 0.00512095 0.00457576 63.9 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.19 vpr 63.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64752 6 8 39 47 1 20 17 5 5 25 clb auto 24.9 MiB 0.01 107 88 59 31 28 0 63.2 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 8.191e-05 7.295e-05 0.000726941 0.000683562 -1 -1 -1 -1 -1 -1 -1 -1 656 1029 31338 15241 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.2 MiB 0.02 -1 -1 63.2 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.19 vpr 63.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65292 6 8 39 47 1 20 17 5 5 25 clb auto 25.1 MiB 0.01 107 88 59 31 28 0 63.8 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 8.0823e-05 7.2013e-05 0.00072635 0.000683135 -1 -1 -1 -1 141 7.42105 65 3.42105 656 1029 31338 15241 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9119 -1.84852 0 0 0.00 -1 -1 63.8 MiB 0.02 -1 -1 63.8 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt index a8c8aed1d54..f6f2c1145a0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.42 vpr 61.41 MiB 0.07 9984 -1 -1 6 0.21 -1 -1 36540 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62880 11 30 336 366 2 175 110 11 11 121 clb auto 21.7 MiB 0.07 1099 5370 731 4291 348 61.4 MiB 0.07 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.000895008 0.000764708 0.0287001 0.0253164 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.19 -1 -1 61.4 MiB 0.11 0.0797492 0.0714232 61.4 MiB -1 0.02 - k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 62.21 MiB 0.06 9984 -1 -1 4 0.20 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63704 11 30 262 292 2 110 54 6 6 36 clb auto 22.6 MiB 0.15 403 1584 300 1231 53 62.2 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000808513 0.00071129 0.0212101 0.0190689 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.05 -1 -1 62.2 MiB 0.04 0.0510796 0.0464992 62.2 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 2.87 odin 150.38 MiB 1.42 153984 -1 -1 6 0.13 -1 -1 33084 -1 -1 65 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61456 11 30 336 366 2 170 106 11 11 121 clb auto 20.6 MiB 0.03 1794 1031 5856 842 4573 441 60.0 MiB 0.03 0.00 6.01276 3.5056 -244.76 -3.5056 3.41098 0.00 0.000481658 0.0004129 0.0143059 0.0124525 -1 -1 -1 -1 976 5.87952 976 5.87952 913 2746 123850 27697 180575 144906 597941. 4941.66 13 20106 83797 -1 3.39028 3.23041 -241.825 -3.39028 -0.29331 -0.0734 0.06 -1 -1 60.0 MiB 0.04 0.0324494 0.0284835 60.0 MiB -1 0.01 +k6_frac_N10_40nm.xml stereovision3.v common 2.96 odin 151.50 MiB 1.71 155136 -1 -1 4 0.12 -1 -1 33092 -1 -1 13 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61812 11 30 262 292 2 107 54 6 6 36 clb auto 21.0 MiB 0.07 561 400 1890 329 1495 66 60.4 MiB 0.02 0.00 2.44705 2.33435 -170.194 -2.33435 2.21316 0.00 0.000401082 0.000350284 0.0105728 0.00946584 -1 -1 -1 -1 486 4.71845 224 2.17476 223 387 11633 4030 862304 700622 161034. 4473.17 11 3844 24048 -1 2.35133 2.20841 -178.735 -2.35133 0 0 0.01 -1 -1 60.4 MiB 0.02 0.0271978 0.024617 60.4 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt index c745d2940f2..c5a98194fb1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.36 vpr 61.16 MiB 0.06 9984 -1 -1 6 0.24 -1 -1 36564 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62624 11 30 336 366 2 175 110 11 11 121 clb auto 21.6 MiB 0.08 1099 5370 731 4291 348 61.2 MiB 0.08 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.00109238 0.000939106 0.0296397 0.0256861 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.18 -1 -1 61.2 MiB 0.09 0.0740596 0.0653877 61.2 MiB -1 0.03 - k6_frac_N10_40nm.xml stereovision3.v common 1.71 vpr 62.40 MiB 0.03 10112 -1 -1 4 0.22 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63900 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 403 1584 300 1231 53 62.4 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000733682 0.000641677 0.0178767 0.0155436 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.04 -1 -1 62.4 MiB 0.04 0.0527381 0.04796 62.4 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 2.68 odin 150.38 MiB 1.39 153984 -1 -1 6 0.12 -1 -1 33080 -1 -1 65 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61460 11 30 336 366 2 170 106 11 11 121 clb auto 20.2 MiB 0.03 1794 1031 5856 842 4573 441 60.0 MiB 0.03 0.00 6.01276 3.5056 -244.76 -3.5056 3.41098 0.00 0.000486395 0.00042381 0.0138701 0.0120728 -1 -1 -1 -1 976 5.87952 976 5.87952 913 2746 123850 27697 180575 144906 597941. 4941.66 13 20106 83797 -1 3.39028 3.23041 -241.825 -3.39028 -0.29331 -0.0734 0.06 -1 -1 60.0 MiB 0.03 0.0307292 0.0268906 60.0 MiB -1 0.01 +k6_frac_N10_40nm.xml stereovision3.v common 2.71 odin 151.50 MiB 1.49 155136 -1 -1 4 0.12 -1 -1 33104 -1 -1 13 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61808 11 30 262 292 2 107 54 6 6 36 clb auto 21.0 MiB 0.06 561 400 1890 329 1495 66 60.4 MiB 0.02 0.00 2.44705 2.33435 -170.194 -2.33435 2.21316 0.00 0.000398384 0.000344047 0.010359 0.0092135 -1 -1 -1 -1 486 4.71845 224 2.17476 223 387 11633 4030 862304 700622 161034. 4473.17 11 3844 24048 -1 2.35133 2.20841 -178.735 -2.35133 0 0 0.01 -1 -1 60.4 MiB 0.02 0.026643 0.0240418 60.4 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt index 8249d51c4a6..7e66c359122 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 34.23 vpr 978.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001816 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.58 371 490 69 397 24 978.3 MiB 0.06 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000593468 0.00051514 0.0111956 0.0102241 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.3 MiB 0.07 0.0418866 0.0386921 978.3 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml styr.blif common 21.32 vpr 979.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003348 10 10 168 178 1 65 30 11 8 88 io auto 953.3 MiB 0.33 530 402 720 97 571 52 979.8 MiB 0.06 0.00 6.8225 6.61671 -72.4654 -6.61671 6.61671 0.00 0.000286578 0.00025614 0.00775293 0.0072086 -1 -1 -1 -1 669 10.4531 198 3.09375 255 965 67200 31259 0 0 194014. 2204.70 14 11730 32605 -1 6.73871 6.73871 -74.3689 -6.73871 0 0 0.03 -1 -1 979.8 MiB 0.05 0.0239292 0.0222252 979.8 MiB -1 0.01 From e0a1fadbe5d01ec3dd09fde17faebd2fd9912d24 Mon Sep 17 00:00:00 2001 From: Rongbo Zhang Date: Mon, 12 May 2025 14:58:27 -0400 Subject: [PATCH 116/176] [packer] recollected golden results for Nightly --- .../figure_8/config/config.txt | 2 +- .../figure_8/config/golden_results.txt | 422 ++-- .../multless_consts/config/golden_results.txt | 2050 ++++++++--------- .../open_cores/config/golden_results.txt | 14 +- .../open_cores_frac/config/golden_results.txt | 22 +- .../config/golden_results.txt | 62 +- .../config/golden_results.txt | 30 +- .../vpr_reg_mcnc/config/golden_results.txt | 42 +- .../config/golden_results.txt | 40 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 16 +- .../titan_other/config/golden_results.txt | 48 +- .../vtr_bidir/config/golden_results.txt | 82 +- .../config/golden_results.txt | 10 +- .../complex_switch/config/golden_results.txt | 30 +- .../config/golden_results.txt | 44 +- .../config/golden_results.txt | 40 +- .../config/golden_results.txt | 48 +- .../config/golden_results.txt | 48 +- .../config/golden_results.txt | 48 +- .../config/golden_results.txt | 48 +- .../ap_titan/config/golden_results.txt | 44 +- .../config/golden_results.txt | 34 +- 23 files changed, 1621 insertions(+), 1621 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt index 6bdbf89bdbe..2946d486557 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt @@ -128,4 +128,4 @@ qor_parse_file=qor_standard.txt # Pass requirements pass_requirements_file=pass_requirements_chain_small.txt -script_params=-lut_size 6 -routing_failure_predictor off -seed 1 +script_params=-lut_size 6 -routing_failure_predictor off -seed 2 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt index 99080e3a8c6..ef10cbea02c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt @@ -1,211 +1,211 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.81 vpr 61.53 MiB -1 -1 0.14 17176 2 0.05 -1 -1 31920 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63004 9 5 28 33 1 17 16 17 17 289 -1 unnamed_device 22.7 MiB 0.01 102 56 22 34 0 61.5 MiB 0.00 0.00 1.25905 -11.4776 -1.25905 1.25905 0.35 8.882e-05 8.0374e-05 0.000503367 0.000460617 -1 -1 -1 -1 20 177 7 6.55708e+06 24110 394039. 1363.46 0.24 0.00338036 0.00301975 19870 87366 -1 145 5 37 42 2127 683 1.13885 1.13885 -10.6853 -1.13885 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00234608 0.00214041 13 6 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.75 vpr 61.79 MiB -1 -1 0.15 17260 2 0.07 -1 -1 31784 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63268 11 6 34 40 1 20 19 17 17 289 -1 unnamed_device 23.1 MiB 0.01 68 419 92 314 13 61.8 MiB 0.01 0.00 1.13885 -12.6274 -1.13885 1.13885 0.36 0.000104018 9.4606e-05 0.00207701 0.00189506 -1 -1 -1 -1 20 166 5 6.55708e+06 24110 394039. 1363.46 0.25 0.00525114 0.0047588 19870 87366 -1 137 4 34 37 1601 538 1.01865 1.01865 -12.5587 -1.01865 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00240353 0.00219298 16 7 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.70 vpr 61.61 MiB -1 -1 0.12 17184 3 0.05 -1 -1 31860 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63088 13 7 41 48 1 27 23 17 17 289 -1 unnamed_device 22.9 MiB 0.01 135 631 147 469 15 61.6 MiB 0.01 0.00 1.37725 -16.6067 -1.37725 1.37725 0.32 0.000129747 0.00011854 0.00286597 0.002624 -1 -1 -1 -1 20 273 10 6.55708e+06 36165 394039. 1363.46 0.25 0.007305 0.00653074 19870 87366 -1 227 7 76 83 3857 1249 1.25705 1.25705 -17.2319 -1.25705 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0033876 0.00303842 19 9 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.80 vpr 61.52 MiB -1 -1 0.13 17272 3 0.04 -1 -1 31840 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62992 15 8 47 55 1 35 27 17 17 289 -1 unnamed_device 23.1 MiB 0.01 246 1107 227 797 83 61.5 MiB 0.01 0.00 1.23151 -21.1845 -1.23151 1.23151 0.32 0.000140574 0.000128754 0.00439077 0.0040239 -1 -1 -1 -1 22 399 8 6.55708e+06 48220 420624. 1455.45 0.33 0.0233791 0.0196844 20158 92377 -1 374 12 138 186 9733 2657 1.23151 1.23151 -21.7797 -1.23151 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00470751 0.00408781 23 10 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.98 vpr 61.69 MiB -1 -1 0.16 17380 3 0.05 -1 -1 32048 -1 -1 6 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63172 17 9 56 65 1 37 32 17 17 289 -1 unnamed_device 23.3 MiB 0.01 141 1132 207 843 82 61.7 MiB 0.01 0.00 1.73785 -23.0011 -1.73785 1.73785 0.32 0.000177397 0.000163282 0.00448382 0.00413693 -1 -1 -1 -1 26 292 10 6.55708e+06 72330 477104. 1650.88 0.34 0.0230579 0.0195262 21022 109990 -1 253 10 116 150 5905 2088 1.73785 1.73785 -22.979 -1.73785 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00488895 0.00427019 26 14 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.00 vpr 61.60 MiB -1 -1 0.17 17588 4 0.08 -1 -1 31936 -1 -1 6 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63080 19 10 60 70 1 46 35 17 17 289 -1 unnamed_device 23.2 MiB 0.02 206 890 192 689 9 61.6 MiB 0.01 0.00 1.83817 -26.8738 -1.83817 1.83817 0.32 0.00018623 0.000172113 0.00345229 0.00318807 -1 -1 -1 -1 24 503 11 6.55708e+06 72330 448715. 1552.65 0.34 0.023586 0.0197806 20734 103517 -1 456 14 189 265 14696 4171 1.79897 1.79897 -29.1306 -1.79897 0 0 554710. 1919.41 0.02 0.02 0.09 -1 -1 0.02 0.00625358 0.00539304 29 13 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.85 vpr 61.68 MiB -1 -1 0.11 17620 4 0.06 -1 -1 31780 -1 -1 7 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63156 21 11 69 80 1 45 39 17 17 289 -1 unnamed_device 23.2 MiB 0.02 234 1425 276 1119 30 61.7 MiB 0.01 0.00 2.00308 -29.8235 -2.00308 2.00308 0.32 0.00021215 0.000195206 0.00517815 0.0047725 -1 -1 -1 -1 20 484 10 6.55708e+06 84385 394039. 1363.46 0.26 0.011519 0.0102836 19870 87366 -1 431 8 137 199 8705 2803 1.8657 1.8657 -30.3926 -1.8657 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00515178 0.00455678 33 17 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.06 vpr 61.65 MiB -1 -1 0.13 17464 5 0.06 -1 -1 32020 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63128 23 12 76 88 1 52 42 17 17 289 -1 unnamed_device 23.1 MiB 0.02 299 2130 460 1580 90 61.6 MiB 0.02 0.00 2.1851 -34.7155 -2.1851 2.1851 0.31 0.000225836 0.000208793 0.00737873 0.0068159 -1 -1 -1 -1 30 557 11 6.55708e+06 84385 526063. 1820.29 0.39 0.0385933 0.032892 21886 126133 -1 477 9 132 177 10121 2634 2.0649 2.0649 -34.6717 -2.0649 0 0 666494. 2306.21 0.03 0.01 0.10 -1 -1 0.03 0.0056861 0.00499978 36 19 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.97 vpr 61.68 MiB -1 -1 0.15 17448 5 0.06 -1 -1 32056 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63164 25 13 83 96 1 61 46 17 17 289 -1 unnamed_device 23.1 MiB 0.03 382 1604 307 1258 39 61.7 MiB 0.02 0.00 2.1433 -40.194 -2.1433 2.1433 0.32 0.0002374 0.000218617 0.00535399 0.0049428 -1 -1 -1 -1 20 750 24 6.55708e+06 96440 394039. 1363.46 0.28 0.0174527 0.0152737 19870 87366 -1 675 11 204 284 17644 4645 2.0231 2.0231 -41.4897 -2.0231 0 0 477104. 1650.88 0.02 0.02 0.08 -1 -1 0.02 0.00708701 0.00625295 39 21 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.98 vpr 61.82 MiB -1 -1 0.12 17548 5 0.06 -1 -1 31808 -1 -1 10 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 27 14 91 105 1 72 51 17 17 289 -1 unnamed_device 23.2 MiB 0.05 487 1931 345 1368 218 61.8 MiB 0.02 0.00 2.31696 -45.6334 -2.31696 2.31696 0.32 0.000303653 0.000273882 0.00640562 0.00591371 -1 -1 -1 -1 26 873 12 6.55708e+06 120550 477104. 1650.88 0.36 0.0365231 0.0313217 21022 109990 -1 816 8 208 332 18433 4780 1.9839 1.9839 -46.0894 -1.9839 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00631768 0.005585 44 24 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.92 vpr 61.82 MiB -1 -1 0.15 17672 6 0.07 -1 -1 32032 -1 -1 10 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 29 15 95 110 1 74 54 17 17 289 -1 unnamed_device 23.2 MiB 0.03 326 1992 324 1638 30 61.8 MiB 0.02 0.00 2.92362 -47.3926 -2.92362 2.92362 0.32 0.000283404 0.000262906 0.00638465 0.00592117 -1 -1 -1 -1 26 681 9 6.55708e+06 120550 477104. 1650.88 0.29 0.0229025 0.019846 21022 109990 -1 645 14 253 412 18759 5604 2.76422 2.76422 -48.0089 -2.76422 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00906397 0.00783781 46 23 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.02 vpr 61.88 MiB -1 -1 0.17 17476 6 0.07 -1 -1 31980 -1 -1 10 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63364 31 16 104 120 1 74 57 17 17 289 -1 unnamed_device 23.2 MiB 0.03 413 2455 496 1792 167 61.9 MiB 0.02 0.00 2.5437 -52.0473 -2.5437 2.5437 0.32 0.000314967 0.000292737 0.00803663 0.00746438 -1 -1 -1 -1 28 797 9 6.55708e+06 120550 500653. 1732.36 0.37 0.0394837 0.0339214 21310 115450 -1 706 7 169 223 12972 3468 2.5437 2.5437 -53.9588 -2.5437 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.0066224 0.00586415 50 27 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.89 vpr 61.88 MiB -1 -1 0.17 17512 7 0.07 -1 -1 32112 -1 -1 10 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63364 33 17 112 129 1 80 60 17 17 289 -1 unnamed_device 23.1 MiB 0.03 455 2400 450 1872 78 61.9 MiB 0.01 0.00 2.77173 -56.4743 -2.77173 2.77173 0.28 0.000151138 0.000138573 0.00382632 0.0035109 -1 -1 -1 -1 22 966 13 6.55708e+06 120550 420624. 1455.45 0.24 0.0223788 0.0192259 20158 92377 -1 820 14 243 337 17062 5047 2.6619 2.6619 -58.7642 -2.6619 0 0 500653. 1732.36 0.02 0.02 0.08 -1 -1 0.02 0.010673 0.0092982 54 30 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.09 vpr 61.96 MiB -1 -1 0.17 17540 7 0.06 -1 -1 31948 -1 -1 13 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63444 37 19 127 146 1 95 69 17 17 289 -1 unnamed_device 23.1 MiB 0.04 580 5286 1128 3575 583 62.0 MiB 0.04 0.00 2.83296 -65.8925 -2.83296 2.83296 0.32 0.000370259 0.000344095 0.0149742 0.013844 -1 -1 -1 -1 28 987 8 6.55708e+06 156715 500653. 1732.36 0.38 0.0517571 0.0451646 21310 115450 -1 947 6 224 327 15796 4347 2.6201 2.6201 -68.3998 -2.6201 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.00692764 0.00618013 63 35 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.16 vpr 61.99 MiB -1 -1 0.15 17432 8 0.07 -1 -1 31996 -1 -1 14 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63480 41 21 139 160 1 106 76 17 17 289 -1 unnamed_device 22.9 MiB 0.04 588 8396 2008 5342 1046 62.0 MiB 0.05 0.00 3.1799 -77.5868 -3.1799 3.1799 0.34 0.000399995 0.000371199 0.0222085 0.0206233 -1 -1 -1 -1 26 1120 12 6.55708e+06 168770 477104. 1650.88 0.38 0.0643844 0.0565876 21022 109990 -1 1022 10 319 425 23447 6363 3.1799 3.1799 -79.2365 -3.1799 0 0 585099. 2024.56 0.03 0.02 0.12 -1 -1 0.03 0.00931512 0.00841851 67 37 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.19 vpr 62.45 MiB -1 -1 0.13 17484 9 0.07 -1 -1 31884 -1 -1 15 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63948 45 23 153 176 1 107 83 17 17 289 -1 unnamed_device 23.1 MiB 0.05 536 7643 1816 4897 930 62.4 MiB 0.05 0.00 4.01419 -88.5998 -4.01419 4.01419 0.32 0.000435711 0.000404292 0.0198098 0.0183771 -1 -1 -1 -1 26 1149 13 6.55708e+06 180825 477104. 1650.88 0.44 0.0661535 0.0580745 21022 109990 -1 1003 13 321 492 25700 7436 3.87922 3.87922 -89.4779 -3.87922 0 0 585099. 2024.56 0.03 0.03 0.10 -1 -1 0.03 0.0114958 0.0102772 73 41 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.19 vpr 62.10 MiB -1 -1 0.13 17776 10 0.07 -1 -1 32012 -1 -1 15 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63588 49 25 166 191 1 117 89 17 17 289 -1 unnamed_device 22.7 MiB 0.04 524 8207 1797 5151 1259 62.1 MiB 0.05 0.00 4.48062 -100.236 -4.48062 4.48062 0.32 0.000471573 0.000438453 0.0210235 0.0195468 -1 -1 -1 -1 26 1157 12 6.55708e+06 180825 477104. 1650.88 0.44 0.070761 0.0623165 21022 109990 -1 1039 10 321 455 24838 7158 4.40948 4.40948 -103.002 -4.40948 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0115319 0.01024 78 44 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.40 vpr 62.41 MiB -1 -1 0.16 17836 11 0.07 -1 -1 32112 -1 -1 20 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 57 29 198 227 1 147 106 17 17 289 -1 unnamed_device 23.0 MiB 0.05 782 8606 1708 6393 505 62.4 MiB 0.06 0.00 4.94665 -134.466 -4.94665 4.94665 0.33 0.000571874 0.000532504 0.0215301 0.0200481 -1 -1 -1 -1 28 1522 13 6.55708e+06 241100 500653. 1732.36 0.43 0.0827513 0.0729032 21310 115450 -1 1371 8 367 517 27034 7537 4.59642 4.59642 -133.949 -4.59642 0 0 612192. 2118.31 0.03 0.03 0.11 -1 -1 0.03 0.0120118 0.0107143 93 56 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.50 vpr 62.60 MiB -1 -1 0.19 17800 13 0.08 -1 -1 32188 -1 -1 20 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 65 33 224 257 1 164 118 17 17 289 -1 unnamed_device 22.9 MiB 0.06 928 17169 4443 10653 2073 62.6 MiB 0.10 0.00 5.28408 -153.681 -5.28408 5.28408 0.36 0.000649312 0.000604542 0.0408491 0.0380181 -1 -1 -1 -1 30 1659 12 6.55708e+06 241100 526063. 1820.29 0.47 0.109688 0.0977858 21886 126133 -1 1555 13 429 584 31745 8729 5.08288 5.08288 -153.594 -5.08288 0 0 666494. 2306.21 0.04 0.03 0.12 -1 -1 0.04 0.016224 0.0145393 107 62 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.63 vpr 63.23 MiB -1 -1 0.20 18112 19 0.10 -1 -1 32232 -1 -1 34 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 97 49 340 389 1 260 180 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1520 22532 5263 15517 1752 63.2 MiB 0.13 0.00 7.62655 -301.388 -7.62655 7.62655 0.29 0.000991752 0.000926486 0.0481233 0.0448481 -1 -1 -1 -1 30 2687 13 6.55708e+06 409870 526063. 1820.29 0.51 0.154423 0.138579 21886 126133 -1 2432 11 662 955 55712 14661 7.28333 7.28333 -297.521 -7.28333 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0249464 0.0224501 165 98 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.24 vpr 63.93 MiB -1 -1 0.28 18296 26 0.13 -1 -1 32396 -1 -1 41 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65464 129 65 453 518 1 334 235 17 17 289 -1 unnamed_device 24.1 MiB 0.10 1951 55259 16458 32932 5869 63.9 MiB 0.28 0.00 10.6369 -487.594 -10.6369 10.6369 0.34 0.00134162 0.00125451 0.10975 0.102432 -1 -1 -1 -1 30 3742 35 6.55708e+06 494255 526063. 1820.29 0.78 0.289369 0.262587 21886 126133 -1 3039 12 909 1148 67590 18881 10.0187 10.0187 -472.64 -10.0187 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0361792 0.0327806 210 131 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.49 abc 29.28 MiB -1 -1 0.10 17348 1 0.02 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.58 abc 29.28 MiB -1 -1 0.12 17328 1 0.03 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23928 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.66 abc 29.27 MiB -1 -1 0.14 17352 1 0.02 -1 -1 29972 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24144 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.66 abc 29.22 MiB -1 -1 0.14 17312 1 0.02 -1 -1 29924 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24024 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.63 abc 29.30 MiB -1 -1 0.14 17436 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.61 abc 29.30 MiB -1 -1 0.15 17384 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24072 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.58 abc 29.34 MiB -1 -1 0.16 17320 1 0.03 -1 -1 30048 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23932 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.55 abc 29.36 MiB -1 -1 0.14 17188 1 0.02 -1 -1 30068 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24076 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.83 abc 29.29 MiB -1 -1 0.16 17156 1 0.02 -1 -1 29992 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.67 abc 29.23 MiB -1 -1 0.15 17352 1 0.02 -1 -1 29936 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23964 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.64 abc 29.44 MiB -1 -1 0.15 17296 1 0.02 -1 -1 30144 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24080 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.82 abc 29.46 MiB -1 -1 0.16 17372 1 0.02 -1 -1 30164 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24028 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.90 abc 29.28 MiB -1 -1 0.16 17348 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24032 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.13 abc 29.58 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30288 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24004 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.11 abc 29.28 MiB -1 -1 0.15 17584 1 0.03 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24108 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 1.33 abc 29.30 MiB -1 -1 0.15 17496 1 0.04 -1 -1 30004 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24068 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 1.13 abc 29.30 MiB -1 -1 0.16 17684 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24012 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.59 abc 29.43 MiB -1 -1 0.16 17528 1 0.02 -1 -1 30140 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24212 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.61 abc 29.43 MiB -1 -1 0.14 17660 1 0.03 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24056 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.60 abc 29.41 MiB -1 -1 0.12 17788 1 0.03 -1 -1 30116 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24088 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.42 abc 29.55 MiB -1 -1 0.21 18072 1 0.03 -1 -1 30256 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24028 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.58 abc 29.32 MiB -1 -1 0.15 17340 1 0.02 -1 -1 30024 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23756 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.56 abc 29.36 MiB -1 -1 0.14 17204 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23848 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.46 abc 29.20 MiB -1 -1 0.08 17420 1 0.02 -1 -1 29904 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23768 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.55 abc 29.36 MiB -1 -1 0.16 17368 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23832 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.50 abc 29.30 MiB -1 -1 0.11 17336 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23792 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.56 abc 29.30 MiB -1 -1 0.14 17268 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23780 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.64 abc 29.29 MiB -1 -1 0.15 17364 1 0.03 -1 -1 29996 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23676 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.77 abc 29.50 MiB -1 -1 0.15 17480 1 0.02 -1 -1 30208 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23908 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.87 abc 29.35 MiB -1 -1 0.13 17308 1 0.03 -1 -1 30056 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23860 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.78 abc 29.34 MiB -1 -1 0.15 17316 1 0.02 -1 -1 30044 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23840 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.90 abc 29.28 MiB -1 -1 0.13 17320 1 0.03 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23792 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.55 abc 29.28 MiB -1 -1 0.15 17412 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23760 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.57 abc 29.43 MiB -1 -1 0.14 17428 1 0.02 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23804 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.59 abc 29.38 MiB -1 -1 0.15 17580 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23888 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.59 abc 29.28 MiB -1 -1 0.16 17688 1 0.02 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23704 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.54 abc 29.29 MiB -1 -1 0.14 17696 1 0.02 -1 -1 29988 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23960 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.53 abc 29.36 MiB -1 -1 0.09 17412 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.64 abc 29.38 MiB -1 -1 0.15 17288 1 0.03 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23700 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.68 abc 29.30 MiB -1 -1 0.17 17596 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23696 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.67 abc 29.53 MiB -1 -1 0.14 17704 1 0.03 -1 -1 30236 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.81 abc 29.84 MiB -1 -1 0.22 18144 1 0.04 -1 -1 30556 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23768 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.67 vpr 61.95 MiB -1 -1 0.09 17252 1 0.03 -1 -1 30116 -1 -1 3 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63432 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 23.2 MiB 0.01 145 80 29 46 5 61.9 MiB 0.00 0.00 0.83871 -12.0914 -0.83871 0.83871 0.32 8.9493e-05 8.1196e-05 0.000627793 0.000575929 -1 -1 -1 -1 20 218 6 6.64007e+06 37674 394039. 1363.46 0.25 0.00366787 0.00331915 20530 87850 -1 213 8 56 56 3444 969 0.890248 0.890248 -12.2124 -0.890248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0028001 0.00250588 14 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.81 vpr 61.82 MiB -1 -1 0.15 17384 1 0.02 -1 -1 29928 -1 -1 4 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 23.1 MiB 0.01 179 525 133 355 37 61.8 MiB 0.01 0.00 0.803048 -13.1622 -0.803048 0.803048 0.33 0.000104816 9.5546e-05 0.00232117 0.00211796 -1 -1 -1 -1 20 294 8 6.64007e+06 50232 394039. 1363.46 0.25 0.00578063 0.00517738 20530 87850 -1 279 8 74 74 5640 1476 0.923248 0.923248 -15.592 -0.923248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00307315 0.00274174 17 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.86 vpr 61.86 MiB -1 -1 0.14 17352 1 0.02 -1 -1 30052 -1 -1 5 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63344 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 23.5 MiB 0.01 158 889 183 672 34 61.9 MiB 0.01 0.00 0.825048 -14.9551 -0.825048 0.825048 0.32 0.00012299 0.000112599 0.00344711 0.00315992 -1 -1 -1 -1 22 332 15 6.64007e+06 62790 420624. 1455.45 0.31 0.0177773 0.0149893 20818 92861 -1 288 10 103 103 5874 1694 0.934248 0.934248 -16.7505 -0.934248 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.00384738 0.00340089 20 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.89 vpr 61.98 MiB -1 -1 0.15 17472 1 0.02 -1 -1 30136 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63468 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.6 MiB 0.02 130 827 161 522 144 62.0 MiB 0.01 0.00 1.18536 -16.9426 -1.18536 1.18536 0.32 0.000141038 0.000129717 0.00333865 0.00306739 -1 -1 -1 -1 22 336 15 6.64007e+06 50232 420624. 1455.45 0.34 0.0179109 0.0151424 20818 92861 -1 281 7 118 118 7761 2504 1.08545 1.08545 -19.5322 -1.08545 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.0039426 0.00354868 22 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 2.04 vpr 61.95 MiB -1 -1 0.14 17348 1 0.02 -1 -1 30048 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63440 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.5 MiB 0.02 156 1759 570 827 362 62.0 MiB 0.02 0.00 1.19636 -19.8289 -1.19636 1.19636 0.32 0.000158366 0.000145724 0.00632531 0.00582349 -1 -1 -1 -1 32 266 11 6.64007e+06 62790 554710. 1919.41 0.38 0.0232912 0.0199009 22834 132086 -1 249 10 97 97 4881 1477 0.834048 0.834048 -18.8492 -0.834048 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00447744 0.00392841 25 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.90 vpr 61.86 MiB -1 -1 0.14 17316 1 0.03 -1 -1 30144 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63348 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.4 MiB 0.02 160 1574 392 922 260 61.9 MiB 0.02 0.00 1.20736 -22.28 -1.20736 1.20736 0.31 0.000177199 0.000163665 0.00559114 0.00516294 -1 -1 -1 -1 22 389 20 6.64007e+06 62790 420624. 1455.45 0.33 0.0271204 0.0230692 20818 92861 -1 335 13 170 170 11128 3516 1.05245 1.05245 -23.8346 -1.05245 0 0 500653. 1732.36 0.03 0.02 0.09 -1 -1 0.03 0.00547305 0.00480176 28 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.93 vpr 62.00 MiB -1 -1 0.15 17268 1 0.03 -1 -1 30160 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63488 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 326 2054 512 1388 154 62.0 MiB 0.02 0.00 1.21836 -28.0305 -1.21836 1.21836 0.32 0.000193986 0.000179202 0.0069198 0.00639758 -1 -1 -1 -1 26 550 12 6.64007e+06 75348 477104. 1650.88 0.35 0.0275302 0.0234892 21682 110474 -1 504 11 163 163 10372 2794 1.00925 1.00925 -29.7279 -1.00925 0 0 585099. 2024.56 0.03 0.02 0.10 -1 -1 0.03 0.00561273 0.00490548 31 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.92 vpr 62.17 MiB -1 -1 0.10 17364 1 0.03 -1 -1 30004 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63660 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.5 MiB 0.02 202 2274 577 1358 339 62.2 MiB 0.02 0.00 1.22936 -27.3302 -1.22936 1.22936 0.32 0.000217044 0.000200805 0.00744746 0.00689241 -1 -1 -1 -1 26 516 20 6.64007e+06 87906 477104. 1650.88 0.37 0.03361 0.0286167 21682 110474 -1 423 19 254 254 15495 4842 1.14165 1.14165 -28.5397 -1.14165 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00847906 0.00723997 35 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 2.03 vpr 62.03 MiB -1 -1 0.13 17356 1 0.02 -1 -1 30120 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63516 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 23.5 MiB 0.02 225 3162 1067 1505 590 62.0 MiB 0.03 0.00 1.24036 -30.3091 -1.24036 1.24036 0.32 0.000223716 0.000206705 0.00935455 0.00864973 -1 -1 -1 -1 28 585 26 6.64007e+06 100464 500653. 1732.36 0.41 0.0378559 0.0324088 21970 115934 -1 409 25 362 362 24657 7379 1.02145 1.02145 -29.5255 -1.02145 0 0 612192. 2118.31 0.04 0.03 0.10 -1 -1 0.04 0.00908575 0.00781132 38 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.07 vpr 62.03 MiB -1 -1 0.15 17336 1 0.02 -1 -1 30088 -1 -1 9 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63520 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 23.5 MiB 0.02 251 4650 1464 2253 933 62.0 MiB 0.03 0.00 1.25136 -32.7881 -1.25136 1.25136 0.32 0.000239703 0.00022173 0.0129775 0.0119987 -1 -1 -1 -1 32 519 22 6.64007e+06 113022 554710. 1919.41 0.41 0.0419733 0.0362927 22834 132086 -1 437 14 276 276 16327 5300 1.03125 1.03125 -33.0873 -1.03125 0 0 701300. 2426.64 0.03 0.02 0.12 -1 -1 0.03 0.00771732 0.00669493 41 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.96 vpr 62.14 MiB -1 -1 0.15 17348 1 0.02 -1 -1 29924 -1 -1 9 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63628 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 23.5 MiB 0.01 462 4409 1391 2113 905 62.1 MiB 0.03 0.00 1.26236 -39.7652 -1.26236 1.26236 0.32 0.000252152 0.000233455 0.012075 0.0111778 -1 -1 -1 -1 26 812 23 6.64007e+06 113022 477104. 1650.88 0.39 0.0429496 0.0370839 21682 110474 -1 713 17 323 323 26583 6736 1.03125 1.03125 -39.6574 -1.03125 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.00919565 0.00794342 44 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.09 vpr 62.16 MiB -1 -1 0.15 17408 1 0.02 -1 -1 30248 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63656 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.5 MiB 0.03 343 4978 1636 2249 1093 62.2 MiB 0.04 0.00 1.62267 -39.5838 -1.62267 1.62267 0.30 0.000273462 0.000253412 0.0135717 0.0125654 -1 -1 -1 -1 30 686 17 6.64007e+06 113022 526063. 1820.29 0.40 0.0434449 0.0377212 22546 126617 -1 539 11 219 219 10604 3260 0.95891 0.95891 -36.3522 -0.95891 0 0 666494. 2306.21 0.03 0.02 0.10 -1 -1 0.03 0.00745402 0.00655316 46 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.01 vpr 62.13 MiB -1 -1 0.08 17640 1 0.02 -1 -1 30132 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63624 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.4 MiB 0.03 352 6329 2210 2989 1130 62.1 MiB 0.04 0.00 1.63367 -42.2226 -1.63367 1.63367 0.32 0.000292013 0.000271082 0.0171275 0.0158779 -1 -1 -1 -1 28 736 12 6.64007e+06 113022 500653. 1732.36 0.42 0.0478919 0.0418393 21970 115934 -1 618 18 335 335 18999 5605 1.21545 1.21545 -44.5486 -1.21545 0 0 612192. 2118.31 0.03 0.03 0.08 -1 -1 0.03 0.0108162 0.00934396 49 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.08 vpr 62.25 MiB -1 -1 0.14 17540 1 0.02 -1 -1 30084 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.5 MiB 0.03 393 6867 2746 3975 146 62.2 MiB 0.05 0.00 1.65567 -49.3018 -1.65567 1.65567 0.32 0.000329974 0.000306635 0.0176624 0.0164096 -1 -1 -1 -1 30 805 15 6.64007e+06 138138 526063. 1820.29 0.41 0.0534439 0.0465752 22546 126617 -1 630 14 325 325 20407 5991 1.07325 1.07325 -45.7613 -1.07325 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0100761 0.0087606 55 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.04 vpr 62.60 MiB -1 -1 0.13 17640 1 0.03 -1 -1 30388 -1 -1 13 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 23.3 MiB 0.02 587 9239 3659 4903 677 62.6 MiB 0.06 0.00 1.67767 -57.8173 -1.67767 1.67767 0.32 0.000360642 0.000335237 0.0220756 0.0205309 -1 -1 -1 -1 30 1014 13 6.64007e+06 163254 526063. 1820.29 0.42 0.0603789 0.0531045 22546 126617 -1 868 10 304 304 26082 6742 1.02025 1.02025 -52.0508 -1.02025 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.00886711 0.00781227 62 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.27 vpr 62.54 MiB -1 -1 0.16 17708 1 0.02 -1 -1 30284 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64044 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 23.2 MiB 0.03 505 10228 3751 5231 1246 62.5 MiB 0.06 0.00 1.69967 -61.6923 -1.69967 1.69967 0.32 0.000396366 0.000369082 0.0236606 0.0219962 -1 -1 -1 -1 32 1098 29 6.64007e+06 175812 554710. 1919.41 0.53 0.0745634 0.0654141 22834 132086 -1 841 14 524 524 35053 10407 1.18565 1.18565 -55.6154 -1.18565 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0118029 0.0103314 68 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.22 vpr 62.62 MiB -1 -1 0.14 17656 1 0.03 -1 -1 30336 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64128 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.3 MiB 0.04 715 8278 1733 6367 178 62.6 MiB 0.06 0.00 2.07098 -71.4065 -2.07098 2.07098 0.32 0.000425886 0.000396892 0.0193216 0.0179715 -1 -1 -1 -1 30 1249 15 6.64007e+06 175812 526063. 1820.29 0.44 0.0656005 0.0577432 22546 126617 -1 1106 11 343 343 25695 6324 1.09525 1.09525 -65.1787 -1.09525 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0113828 0.0101237 73 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.31 vpr 62.69 MiB -1 -1 0.16 17512 1 0.03 -1 -1 30076 -1 -1 18 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64196 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 23.3 MiB 0.04 774 16452 3708 11655 1089 62.7 MiB 0.10 0.00 2.11498 -86.7435 -2.11498 2.11498 0.32 0.000485084 0.000450927 0.0341069 0.0317077 -1 -1 -1 -1 32 1465 18 6.64007e+06 226044 554710. 1919.41 0.49 0.0895901 0.0796678 22834 132086 -1 1213 17 542 542 36079 10159 1.35645 1.35645 -81.4884 -1.35645 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.016593 0.0145733 86 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.38 vpr 62.91 MiB -1 -1 0.18 17672 1 0.03 -1 -1 30064 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.3 MiB 0.05 1165 18135 6420 10093 1622 62.9 MiB 0.11 0.00 2.50829 -108.778 -2.50829 2.50829 0.32 0.0005667 0.000528433 0.0374509 0.0349335 -1 -1 -1 -1 30 1825 43 6.64007e+06 238602 526063. 1820.29 0.51 0.122573 0.10861 22546 126617 -1 1603 14 500 500 39832 9325 1.21425 1.21425 -91.6209 -1.21425 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.016578 0.0146599 97 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.65 vpr 63.45 MiB -1 -1 0.17 17900 1 0.03 -1 -1 30280 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64976 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.9 MiB 0.07 1660 32449 9442 20195 2812 63.5 MiB 0.20 0.00 3.38291 -180.139 -3.38291 3.38291 0.32 0.000868353 0.000813665 0.0603321 0.056479 -1 -1 -1 -1 30 2741 24 6.64007e+06 364182 526063. 1820.29 0.58 0.167976 0.151769 22546 126617 -1 2404 13 827 827 63818 16162 1.39605 1.39605 -140.523 -1.39605 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0236694 0.0212549 145 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.96 vpr 63.93 MiB -1 -1 0.19 18156 1 0.03 -1 -1 30516 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65460 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.4 MiB 0.11 2246 49637 16069 29592 3976 63.9 MiB 0.33 0.01 4.25753 -269.223 -4.25753 4.25753 0.32 0.00123279 0.00116168 0.0889312 0.0837218 -1 -1 -1 -1 32 3518 14 6.64007e+06 489762 554710. 1919.41 0.66 0.226555 0.20755 22834 132086 -1 3131 12 959 959 74779 19366 1.56805 1.56805 -190.941 -1.56805 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0304292 0.0275916 193 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.70 vpr 61.73 MiB -1 -1 0.12 17344 1 0.03 -1 -1 29928 -1 -1 3 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63216 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 22.9 MiB 0.01 148 80 29 46 5 61.7 MiB 0.00 0.00 0.83871 -11.7447 -0.83871 0.83871 0.32 8.8927e-05 8.028e-05 0.000604437 0.000548194 -1 -1 -1 -1 20 230 8 6.65987e+06 38034 394039. 1363.46 0.25 0.00388017 0.00347642 20530 87850 -1 214 10 61 61 5414 1452 0.83871 0.83871 -11.8866 -0.83871 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0031468 0.00280409 14 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.72 vpr 61.69 MiB -1 -1 0.14 17312 1 0.02 -1 -1 29920 -1 -1 4 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63168 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 23.0 MiB 0.01 189 525 130 355 40 61.7 MiB 0.01 0.00 0.803048 -13.1363 -0.803048 0.803048 0.32 0.000104272 9.5105e-05 0.00233488 0.00212885 -1 -1 -1 -1 20 304 9 6.65987e+06 50712 394039. 1363.46 0.26 0.00586479 0.00523143 20530 87850 -1 282 10 105 105 8718 2335 0.83871 0.83871 -14.5944 -0.83871 0 0 477104. 1650.88 0.03 0.01 0.08 -1 -1 0.03 0.00378422 0.00342251 17 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.86 vpr 61.82 MiB -1 -1 0.13 17280 1 0.02 -1 -1 29868 -1 -1 5 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 23.4 MiB 0.01 147 1105 244 814 47 61.8 MiB 0.01 0.00 0.830189 -14.844 -0.830189 0.830189 0.33 0.00012577 0.000112704 0.00426613 0.00390409 -1 -1 -1 -1 26 305 15 6.65987e+06 63390 477104. 1650.88 0.34 0.0191538 0.0162467 21682 110474 -1 272 12 128 128 8327 2403 0.950389 0.950389 -16.4625 -0.950389 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00423977 0.00371064 20 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.02 vpr 61.80 MiB -1 -1 0.16 17392 1 0.02 -1 -1 30000 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63288 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.4 MiB 0.01 132 947 214 545 188 61.8 MiB 0.01 0.00 1.20253 -16.9819 -1.20253 1.20253 0.34 0.00014165 0.000130082 0.00397733 0.00363354 -1 -1 -1 -1 32 286 17 6.65987e+06 50712 554710. 1919.41 0.38 0.0203804 0.0172185 22834 132086 -1 207 12 103 103 5880 1787 0.856048 0.856048 -16.2356 -0.856048 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00468142 0.00409653 22 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.96 vpr 61.77 MiB -1 -1 0.14 17420 1 0.02 -1 -1 30048 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63256 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.4 MiB 0.02 169 1039 221 683 135 61.8 MiB 0.01 0.00 1.19636 -19.6785 -1.19636 1.19636 0.34 0.000160216 0.000147534 0.00392966 0.00362469 -1 -1 -1 -1 30 342 14 6.65987e+06 63390 526063. 1820.29 0.37 0.0217562 0.0183847 22546 126617 -1 290 13 143 143 7116 2212 0.823048 0.823048 -19.6378 -0.823048 0 0 666494. 2306.21 0.03 0.01 0.10 -1 -1 0.03 0.00533708 0.00464817 25 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.96 vpr 61.78 MiB -1 -1 0.10 17400 1 0.02 -1 -1 30056 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63264 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.3 MiB 0.02 158 1684 407 960 317 61.8 MiB 0.02 0.00 1.20736 -22.0789 -1.20736 1.20736 0.32 0.000176486 0.000162987 0.00597002 0.0055165 -1 -1 -1 -1 30 316 15 6.65987e+06 63390 526063. 1820.29 0.37 0.0258595 0.0220154 22546 126617 -1 281 20 183 183 9032 2990 1.07445 1.07445 -22.6488 -1.07445 0 0 666494. 2306.21 0.05 0.02 0.14 -1 -1 0.05 0.00796327 0.00683749 28 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.96 vpr 61.98 MiB -1 -1 0.14 17436 1 0.02 -1 -1 30148 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63472 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 335 1865 426 1314 125 62.0 MiB 0.02 0.00 1.21836 -28.0156 -1.21836 1.21836 0.32 0.000195988 0.000181389 0.00640653 0.00592412 -1 -1 -1 -1 26 555 11 6.65987e+06 76068 477104. 1650.88 0.35 0.0272629 0.0232932 21682 110474 -1 547 16 214 214 18567 4835 1.08545 1.08545 -31.2059 -1.08545 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00706697 0.00607694 31 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.03 vpr 62.06 MiB -1 -1 0.16 17404 1 0.02 -1 -1 30128 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63552 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.4 MiB 0.02 204 3498 1194 1551 753 62.1 MiB 0.03 0.00 1.22936 -27.6572 -1.22936 1.22936 0.32 0.000212462 0.000196166 0.0109339 0.0101005 -1 -1 -1 -1 30 454 21 6.65987e+06 88746 526063. 1820.29 0.39 0.0363204 0.0312013 22546 126617 -1 361 18 221 221 11264 3655 1.04739 1.04739 -26.9812 -1.04739 0 0 666494. 2306.21 0.03 0.02 0.10 -1 -1 0.03 0.00812448 0.00696129 35 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.99 vpr 61.94 MiB -1 -1 0.15 17252 1 0.02 -1 -1 29996 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63428 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 23.4 MiB 0.02 266 3244 1063 1597 584 61.9 MiB 0.03 0.00 1.24036 -31.1975 -1.24036 1.24036 0.32 0.000180091 0.000164931 0.00943785 0.00872483 -1 -1 -1 -1 28 564 34 6.65987e+06 101424 500653. 1732.36 0.43 0.046281 0.0393218 21970 115934 -1 503 13 227 227 15114 4347 1.14045 1.14045 -33.3649 -1.14045 0 0 612192. 2118.31 0.03 0.02 0.11 -1 -1 0.03 0.00698344 0.00607333 38 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.09 vpr 62.05 MiB -1 -1 0.15 17416 1 0.02 -1 -1 29976 -1 -1 9 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63544 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 23.4 MiB 0.02 267 4650 1648 2149 853 62.1 MiB 0.04 0.00 1.25136 -33.284 -1.25136 1.25136 0.32 0.000283328 0.000262351 0.0142241 0.0131692 -1 -1 -1 -1 32 627 21 6.65987e+06 114102 554710. 1919.41 0.42 0.0429261 0.0372136 22834 132086 -1 519 21 333 333 18881 5985 1.12945 1.12945 -35.2713 -1.12945 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0149715 0.0126565 41 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 2.07 vpr 61.92 MiB -1 -1 0.15 17644 1 0.02 -1 -1 29984 -1 -1 9 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63408 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 23.3 MiB 0.02 324 3518 788 2107 623 61.9 MiB 0.03 0.00 1.26236 -35.6797 -1.26236 1.26236 0.32 0.000253071 0.000234583 0.00979541 0.0090734 -1 -1 -1 -1 30 698 25 6.65987e+06 114102 526063. 1820.29 0.42 0.0425967 0.0366082 22546 126617 -1 520 15 327 327 17260 5451 1.02039 1.02039 -33.4205 -1.02039 0 0 666494. 2306.21 0.03 0.02 0.08 -1 -1 0.03 0.00850795 0.00740024 44 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.14 vpr 61.97 MiB -1 -1 0.16 17636 1 0.02 -1 -1 30264 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63460 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.3 MiB 0.02 363 4978 1495 2401 1082 62.0 MiB 0.04 0.00 1.62267 -39.2597 -1.62267 1.62267 0.32 0.000271456 0.000251613 0.0137065 0.0126797 -1 -1 -1 -1 28 787 18 6.65987e+06 114102 500653. 1732.36 0.43 0.0450106 0.0390537 21970 115934 -1 646 20 384 384 28172 7864 1.10039 1.10039 -40.1031 -1.10039 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0116488 0.010003 46 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.15 vpr 61.95 MiB -1 -1 0.15 17460 1 0.02 -1 -1 30056 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63440 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.3 MiB 0.02 358 6329 2576 3638 115 62.0 MiB 0.05 0.00 1.63367 -43.0819 -1.63367 1.63367 0.32 0.000297215 0.00027577 0.0173583 0.0161231 -1 -1 -1 -1 30 697 17 6.65987e+06 114102 526063. 1820.29 0.41 0.0506732 0.0443138 22546 126617 -1 563 18 309 309 15903 4551 0.975189 0.975189 -38.2274 -0.975189 0 0 666494. 2306.21 0.03 0.03 0.09 -1 -1 0.03 0.0107508 0.00928908 49 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.29 vpr 62.15 MiB -1 -1 0.17 17580 1 0.02 -1 -1 30004 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63640 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.3 MiB 0.03 395 6867 2582 3609 676 62.1 MiB 0.05 0.00 1.65567 -48.7086 -1.65567 1.65567 0.32 0.000325622 0.000302353 0.0174514 0.0161951 -1 -1 -1 -1 28 927 37 6.65987e+06 139458 500653. 1732.36 0.49 0.0658178 0.0568171 21970 115934 -1 701 14 374 374 29107 8630 1.23745 1.23745 -49.5635 -1.23745 0 0 612192. 2118.31 0.02 0.02 0.07 -1 -1 0.02 0.00594303 0.00527331 55 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.41 vpr 62.28 MiB -1 -1 0.12 17468 1 0.02 -1 -1 30460 -1 -1 13 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63772 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 23.0 MiB 0.03 491 9081 3707 5187 187 62.3 MiB 0.06 0.00 1.67767 -56.6155 -1.67767 1.67767 0.32 0.00035997 0.000334363 0.0218976 0.020333 -1 -1 -1 -1 30 1037 25 6.65987e+06 164814 526063. 1820.29 0.49 0.0667016 0.0582429 22546 126617 -1 743 15 369 369 22934 6790 1.02419 1.02419 -50.6361 -1.02419 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0117394 0.0102506 62 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 3.61 vpr 62.31 MiB -1 -1 0.11 17580 1 0.02 -1 -1 30308 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63808 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 23.1 MiB 0.03 499 10228 3488 4555 2185 62.3 MiB 0.06 0.00 1.69967 -61.5408 -1.69967 1.69967 0.32 0.000393075 0.000365679 0.0237597 0.0221074 -1 -1 -1 -1 30 1113 21 6.65987e+06 177492 526063. 1820.29 1.46 0.127983 0.11047 22546 126617 -1 863 16 593 593 46003 13579 1.18459 1.18459 -55.1595 -1.18459 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.0130362 0.0113889 68 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.71 vpr 62.41 MiB -1 -1 0.16 17728 1 0.02 -1 -1 30344 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.1 MiB 0.03 627 5353 1046 4033 274 62.4 MiB 0.04 0.00 2.07098 -70.3136 -2.07098 2.07098 0.32 0.000433307 0.000403645 0.0129451 0.0120394 -1 -1 -1 -1 32 1170 15 6.65987e+06 177492 554710. 1919.41 0.45 0.0588027 0.0514064 22834 132086 -1 1054 17 432 432 30738 8937 1.32345 1.32345 -69.7201 -1.32345 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0145867 0.0127516 73 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.29 vpr 62.52 MiB -1 -1 0.16 17584 1 0.04 -1 -1 30108 -1 -1 18 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64016 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 23.4 MiB 0.04 750 10596 2249 7776 571 62.5 MiB 0.07 0.00 2.11498 -85.1831 -2.11498 2.11498 0.31 0.000494895 0.000460975 0.0226536 0.02111 -1 -1 -1 -1 32 1479 15 6.65987e+06 228204 554710. 1919.41 0.47 0.0757256 0.0669986 22834 132086 -1 1199 18 520 520 35837 10747 1.36745 1.36745 -82.2692 -1.36745 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0174867 0.0153336 86 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.36 vpr 62.79 MiB -1 -1 0.14 17900 1 0.03 -1 -1 29940 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.2 MiB 0.04 1148 18135 6273 10055 1807 62.8 MiB 0.11 0.00 2.50829 -108.743 -2.50829 2.50829 0.31 0.000567141 0.000528695 0.0376235 0.035098 -1 -1 -1 -1 32 1762 17 6.65987e+06 240882 554710. 1919.41 0.48 0.101169 0.0902369 22834 132086 -1 1641 35 572 572 92037 50076 1.42045 1.42045 -99.1377 -1.42045 0 0 701300. 2426.64 0.03 0.09 0.11 -1 -1 0.03 0.034255 0.0298774 97 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.76 vpr 62.72 MiB -1 -1 0.15 17948 1 0.04 -1 -1 30296 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64224 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.6 MiB 0.05 1644 32449 9393 19839 3217 62.7 MiB 0.19 0.00 3.38291 -180.76 -3.38291 3.38291 0.32 0.000880433 0.000823692 0.0609751 0.0571335 -1 -1 -1 -1 32 2858 35 6.65987e+06 367662 554710. 1919.41 0.66 0.183589 0.165605 22834 132086 -1 2422 21 853 853 74293 19928 1.63645 1.63645 -152.543 -1.63645 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0343826 0.0306978 145 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.04 vpr 63.06 MiB -1 -1 0.22 18240 1 0.04 -1 -1 30524 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.1 MiB 0.07 2278 49637 16106 29325 4206 63.1 MiB 0.32 0.01 4.25753 -269.84 -4.25753 4.25753 0.32 0.00119888 0.00112752 0.0868525 0.0816403 -1 -1 -1 -1 32 3524 24 6.65987e+06 494442 554710. 1919.41 0.71 0.239232 0.218193 22834 132086 -1 3207 15 1082 1082 88606 22556 1.61205 1.61205 -194.499 -1.61205 0 0 701300. 2426.64 0.03 0.09 0.13 -1 -1 0.03 0.0362035 0.0327639 193 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 1.77 vpr 62.61 MiB -1 -1 0.15 17432 1 0.02 -1 -1 30000 -1 -1 1 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64112 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 23.9 MiB 0.02 49 141 51 88 2 62.6 MiB 0.00 0.00 0.723895 -9.92304 -0.723895 0.723895 0.26 8.8052e-05 7.9849e-05 0.000999121 0.000908116 -1 -1 -1 -1 20 98 10 6.95648e+06 14475.7 414966. 1435.87 0.30 0.0111389 0.00932378 23170 95770 -1 97 7 39 39 2258 798 0.74674 0.74674 -9.97418 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00275107 0.00248696 7 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 1.90 vpr 62.60 MiB -1 -1 0.14 17416 1 0.02 -1 -1 29904 -1 -1 1 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 24.1 MiB 0.05 62 455 89 352 14 62.6 MiB 0.01 0.00 0.723895 -12.1764 -0.723895 0.723895 0.34 0.000105243 9.602e-05 0.00245462 0.00224036 -1 -1 -1 -1 20 159 11 6.95648e+06 14475.7 414966. 1435.87 0.28 0.006791 0.00608146 23170 95770 -1 135 8 71 71 4591 1516 0.74674 0.74674 -13.0356 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.10 -1 -1 0.02 0.00316305 0.00283131 8 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 1.98 vpr 62.57 MiB -1 -1 0.14 17264 1 0.02 -1 -1 29984 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64076 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 24.1 MiB 0.05 78 532 113 404 15 62.6 MiB 0.01 0.00 0.802432 -14.5369 -0.802432 0.802432 0.35 0.00012283 0.00011251 0.00266091 0.00244373 -1 -1 -1 -1 22 226 14 6.95648e+06 28951.4 443629. 1535.05 0.33 0.0192559 0.0165149 23458 102101 -1 200 12 93 93 4853 1733 1.04203 1.04203 -16.6837 -1.04203 0 0 531479. 1839.03 0.02 0.01 0.10 -1 -1 0.02 0.00425953 0.003729 10 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 1.92 vpr 62.76 MiB -1 -1 0.09 17224 1 0.03 -1 -1 30004 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.3 MiB 0.03 198 745 185 473 87 62.8 MiB 0.01 0.00 0.852632 -19.2076 -0.852632 0.852632 0.34 0.000140716 0.00012916 0.00337215 0.00309938 -1 -1 -1 -1 26 321 13 6.95648e+06 28951.4 503264. 1741.40 0.36 0.0195341 0.0165326 24322 120374 -1 321 11 126 126 8370 2235 1.09223 1.09223 -20.8791 -1.09223 0 0 618332. 2139.56 0.04 0.01 0.12 -1 -1 0.04 0.00464353 0.00415812 11 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 2.08 vpr 62.92 MiB -1 -1 0.15 17404 1 0.02 -1 -1 30132 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 24.4 MiB 0.03 223 1078 298 659 121 62.9 MiB 0.01 0.00 0.852632 -21.5769 -0.852632 0.852632 0.33 0.000157576 0.000145183 0.00461473 0.00425641 -1 -1 -1 -1 30 354 9 6.95648e+06 28951.4 556674. 1926.21 0.39 0.0212789 0.0180897 25186 138497 -1 308 12 127 127 6401 1953 0.959892 0.959892 -22.0373 -0.959892 0 0 706193. 2443.58 0.03 0.01 0.11 -1 -1 0.03 0.00509797 0.00446228 13 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 2.35 vpr 62.62 MiB -1 -1 0.16 17360 1 0.02 -1 -1 30072 -1 -1 4 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 24.1 MiB 0.02 137 2113 694 1199 220 62.6 MiB 0.02 0.00 0.852632 -22.0391 -0.852632 0.852632 0.33 0.000175963 0.000162527 0.0077691 0.00716049 -1 -1 -1 -1 34 351 30 6.95648e+06 57902.7 618332. 2139.56 0.63 0.045466 0.0380876 25762 151098 -1 282 21 287 287 12600 4481 1.08603 1.08603 -23.81 -1.08603 0 0 787024. 2723.27 0.05 0.03 0.14 -1 -1 0.05 0.00901771 0.00775726 15 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 2.12 vpr 62.77 MiB -1 -1 0.16 17304 1 0.03 -1 -1 30060 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 21 11 76 77 1 49 36 17 17 289 -1 unnamed_device 24.3 MiB 0.02 347 1157 244 770 143 62.8 MiB 0.01 0.00 0.896632 -29.3782 -0.896632 0.896632 0.34 0.000195865 0.000181237 0.00446093 0.00413933 -1 -1 -1 -1 32 570 14 6.95648e+06 57902.7 586450. 2029.24 0.45 0.0343905 0.0288988 25474 144626 -1 537 14 225 225 20970 4717 0.993732 0.993732 -31.9978 -0.993732 0 0 744469. 2576.02 0.03 0.02 0.10 -1 -1 0.03 0.00662926 0.0057376 17 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 2.48 vpr 62.92 MiB -1 -1 0.16 17280 1 0.02 -1 -1 30048 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64432 23 12 83 84 1 55 39 17 17 289 -1 unnamed_device 24.3 MiB 0.02 176 2481 826 1259 396 62.9 MiB 0.02 0.00 0.896632 -27.0337 -0.896632 0.896632 0.34 0.000210709 0.000195162 0.00860788 0.00797035 -1 -1 -1 -1 34 483 24 6.95648e+06 57902.7 618332. 2139.56 0.67 0.0520092 0.0437792 25762 151098 -1 363 22 394 394 26948 8701 1.04203 1.04203 -28.5778 -1.04203 0 0 787024. 2723.27 0.04 0.03 0.16 -1 -1 0.04 0.00958538 0.00817473 18 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 2.16 vpr 62.77 MiB -1 -1 0.15 17464 1 0.02 -1 -1 30040 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.1 MiB 0.02 224 1468 277 1132 59 62.8 MiB 0.02 0.00 0.918632 -30.5074 -0.918632 0.918632 0.34 0.000235964 0.000218668 0.00528816 0.00487691 -1 -1 -1 -1 28 585 18 6.95648e+06 72378.4 531479. 1839.03 0.42 0.0314017 0.026693 24610 126494 -1 522 14 291 291 16745 5276 1.13003 1.13003 -35.7088 -1.13003 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00737591 0.00639021 20 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 2.17 vpr 62.77 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30064 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 24.1 MiB 0.03 339 2916 911 1507 498 62.8 MiB 0.02 0.00 0.951632 -33.9905 -0.951632 0.951632 0.33 0.000237851 0.000219672 0.0093005 0.00860411 -1 -1 -1 -1 30 672 15 6.95648e+06 72378.4 556674. 1926.21 0.43 0.0359111 0.0309348 25186 138497 -1 538 13 312 312 21190 5519 1.20223 1.20223 -37.9867 -1.20223 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.0076564 0.00668502 21 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 2.25 vpr 62.77 MiB -1 -1 0.16 17140 1 0.02 -1 -1 29948 -1 -1 5 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 29 15 104 105 1 72 49 17 17 289 -1 unnamed_device 24.1 MiB 0.03 501 2808 751 1668 389 62.8 MiB 0.02 0.00 0.951632 -40.8249 -0.951632 0.951632 0.34 0.000242718 0.000218442 0.00856423 0.00788443 -1 -1 -1 -1 28 933 14 6.95648e+06 72378.4 531479. 1839.03 0.51 0.0366332 0.0315532 24610 126494 -1 839 20 482 482 52768 11792 1.09223 1.09223 -45.6629 -1.09223 0 0 648988. 2245.63 0.03 0.03 0.14 -1 -1 0.03 0.0104657 0.00901245 23 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 2.48 vpr 62.93 MiB -1 -1 0.17 17680 1 0.02 -1 -1 30380 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.2 MiB 0.04 310 4417 1777 2577 63 62.9 MiB 0.03 0.00 1.33396 -40.1371 -1.33396 1.33396 0.33 0.000271468 0.000251395 0.013265 0.0122886 -1 -1 -1 -1 36 703 18 6.95648e+06 72378.4 648988. 2245.63 0.68 0.065333 0.0558986 26050 158493 -1 570 15 424 424 34284 9332 1.09503 1.09503 -39.6024 -1.09503 0 0 828058. 2865.25 0.03 0.03 0.13 -1 -1 0.03 0.00937891 0.00816579 24 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_016bits.v common 2.24 vpr 62.85 MiB -1 -1 0.14 17620 1 0.02 -1 -1 30060 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64360 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 24.2 MiB 0.05 328 4735 1875 2804 56 62.9 MiB 0.04 0.00 1.34496 -43.1769 -1.34496 1.34496 0.33 0.000293442 0.00027197 0.0142331 0.0131982 -1 -1 -1 -1 30 767 17 6.95648e+06 72378.4 556674. 1926.21 0.46 0.0473708 0.0411429 25186 138497 -1 631 20 455 455 37921 9718 1.25333 1.25333 -46.1252 -1.25333 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0119303 0.0103075 25 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_018bits.v common 2.33 vpr 62.87 MiB -1 -1 0.15 17668 1 0.03 -1 -1 30120 -1 -1 5 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64376 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 24.1 MiB 0.07 367 6541 2699 3775 67 62.9 MiB 0.05 0.00 1.36696 -49.1573 -1.36696 1.36696 0.33 0.000329616 0.000306498 0.0189951 0.0176578 -1 -1 -1 -1 32 856 19 6.95648e+06 72378.4 586450. 2029.24 0.49 0.0571506 0.0498642 25474 144626 -1 628 18 477 477 33113 8842 1.22703 1.22703 -50.8059 -1.22703 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0122266 0.0105782 28 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 2.39 vpr 63.03 MiB -1 -1 0.17 17652 1 0.02 -1 -1 30388 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64544 41 21 146 147 1 95 67 17 17 289 -1 unnamed_device 24.0 MiB 0.07 409 6867 2815 3994 58 63.0 MiB 0.05 0.00 1.38896 -56.2399 -1.38896 1.38896 0.33 0.00036088 0.000335508 0.0193484 0.0179993 -1 -1 -1 -1 30 1163 35 6.95648e+06 72378.4 556674. 1926.21 0.60 0.0698336 0.0607412 25186 138497 -1 785 16 563 563 51275 13421 1.44463 1.44463 -60.8139 -1.44463 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0123152 0.0107333 31 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 3.70 vpr 63.18 MiB -1 -1 0.17 17588 1 0.03 -1 -1 30316 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 45 23 160 161 1 108 74 17 17 289 -1 unnamed_device 24.0 MiB 0.08 466 7514 3111 4336 67 63.2 MiB 0.05 0.00 1.41096 -62.5444 -1.41096 1.41096 0.34 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2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64012 13 7 48 49 1 26 22 17 17 289 -1 unnamed_device 24.0 MiB 0.01 88 442 89 343 10 62.5 MiB 0.02 0.00 0.802432 -14.6238 -0.802432 0.802432 0.33 0.000416283 0.000382138 0.00349914 0.00321787 -1 -1 -1 -1 22 196 8 6.99608e+06 29431.4 443629. 1535.05 0.33 0.0164598 0.0139839 23458 102101 -1 190 12 106 106 6171 2132 0.793379 0.793379 -15.9608 -0.793379 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00429213 0.00376112 10 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_007bits.v common 1.96 vpr 62.73 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30052 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.3 MiB 0.01 96 709 205 450 54 62.7 MiB 0.01 0.00 0.859432 -17.7199 -0.859432 0.859432 0.34 0.000140372 0.000128807 0.00323931 0.00297881 -1 -1 -1 -1 26 228 25 6.99608e+06 29431.4 503264. 1741.40 0.37 0.0216731 0.0182166 24322 120374 -1 198 12 131 131 4752 1834 0.927732 0.927732 -17.9149 -0.927732 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00468069 0.0040988 11 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 2.08 vpr 62.63 MiB -1 -1 0.15 17184 1 0.02 -1 -1 30084 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64132 17 9 62 63 1 38 28 17 17 289 -1 unnamed_device 24.1 MiB 0.02 260 952 218 609 125 62.6 MiB 0.01 0.00 0.824432 -22.1673 -0.824432 0.824432 0.34 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/home/elgamma8/research/release/vtr-verilog-to-routing 64072 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 23.9 MiB 0.03 255 1618 324 1252 42 62.6 MiB 0.02 0.00 0.890432 -31.1278 -0.890432 0.890432 0.34 0.000224588 0.000208394 0.00581343 0.00537445 -1 -1 -1 -1 30 526 13 6.99608e+06 73578.4 556674. 1926.21 0.42 0.0313334 0.0268842 25186 138497 -1 496 10 236 236 16715 4353 0.99734 0.99734 -33.2379 -0.99734 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00608414 0.00533822 20 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 2.17 vpr 62.79 MiB -1 -1 0.16 17396 1 0.02 -1 -1 29940 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 24.2 MiB 0.02 266 2916 905 1615 396 62.8 MiB 0.02 0.00 0.912432 -33.5679 -0.912432 0.912432 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 57 29 202 203 1 141 95 17 17 289 -1 unnamed_device 23.7 MiB 0.05 724 11543 4737 6716 90 63.1 MiB 0.07 0.00 1.44876 -82.7694 -1.44876 1.44876 0.34 0.000487581 0.000453293 0.0278211 0.0258836 -1 -1 -1 -1 38 1462 37 6.99608e+06 132441 678818. 2348.85 1.07 0.136751 0.119606 26626 170182 -1 1129 17 624 624 44907 12336 1.24188 1.24188 -80.687 -1.24188 0 0 902133. 3121.57 0.03 0.04 0.14 -1 -1 0.03 0.0169488 0.0148993 44 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 3.01 vpr 63.09 MiB -1 -1 0.10 17544 1 0.03 -1 -1 30048 -1 -1 9 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 23.7 MiB 0.05 873 16299 6945 9215 139 63.1 MiB 0.10 0.00 1.85309 -97.7499 -1.85309 1.85309 0.34 0.000588436 0.000549662 0.0383991 0.0358314 -1 -1 -1 -1 40 1590 25 6.99608e+06 132441 706193. 2443.58 1.10 0.154029 0.135738 26914 176310 -1 1430 16 781 781 64746 16342 1.32403 1.32403 -95.1334 -1.32403 0 0 926341. 3205.33 0.04 0.05 0.14 -1 -1 0.04 0.0186641 0.0164658 50 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_048bits.v common 3.65 vpr 63.71 MiB -1 -1 0.17 17844 1 0.03 -1 -1 30352 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65236 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.0 MiB 0.08 1811 29672 12269 17337 66 63.7 MiB 0.18 0.00 2.38942 -170.114 -2.38942 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63376 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 23.2 MiB 0.01 78 394 86 293 15 61.9 MiB 0.01 0.00 1.02368 -13.4328 -1.02368 1.02368 0.36 0.000106267 9.6689e-05 0.00206803 0.0018958 -1 -1 -1 -1 22 194 10 6.79088e+06 26944 443629. 1535.05 0.32 0.0137002 0.0115006 22798 101617 -1 190 9 83 96 4150 1453 1.02368 1.02368 -14.6764 -1.02368 0 0 531479. 1839.03 0.03 0.01 0.09 -1 -1 0.03 0.00336983 0.00298904 10 7 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_006bits.v common 1.81 vpr 61.99 MiB -1 -1 0.15 17184 3 0.06 -1 -1 31848 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 23.3 MiB 0.01 103 562 132 416 14 62.0 MiB 0.01 0.00 1.14898 -15.8855 -1.14898 1.14898 0.33 5.793e-05 5.1492e-05 0.00140278 0.00125839 -1 -1 -1 -1 22 254 12 6.79088e+06 26944 443629. 1535.05 0.33 0.0182156 0.0151027 22798 101617 -1 234 12 97 105 6113 2065 1.14898 1.14898 -17.5434 -1.14898 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00432033 0.00378435 11 9 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_007bits.v common 2.04 vpr 62.02 MiB -1 -1 0.15 17292 3 0.05 -1 -1 31872 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63512 15 8 47 55 1 35 25 17 17 289 -1 unnamed_device 23.6 MiB 0.04 109 1285 395 736 154 62.0 MiB 0.01 0.00 1.27433 -19.2894 -1.27433 1.27433 0.34 0.000142197 0.0001303 0.00559248 0.00513681 -1 -1 -1 -1 26 347 17 6.79088e+06 26944 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fixed_k6_frac_N8_22nm.xml adder_009bits.v common 2.16 vpr 61.99 MiB -1 -1 0.15 17304 4 0.06 -1 -1 31992 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 19 10 60 70 1 46 32 17 17 289 -1 unnamed_device 23.5 MiB 0.07 157 2582 733 1373 476 62.0 MiB 0.02 0.00 1.65028 -26.9205 -1.65028 1.65028 0.34 0.000185515 0.000170984 0.0102122 0.00942314 -1 -1 -1 -1 28 440 24 6.79088e+06 40416 531479. 1839.03 0.40 0.0336774 0.0287458 23950 126010 -1 341 14 189 208 10515 3869 1.68943 1.68943 -27.6328 -1.68943 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00634766 0.00548015 17 13 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_010bits.v common 2.09 vpr 62.10 MiB -1 -1 0.16 17224 4 0.06 -1 -1 31688 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63592 21 11 69 80 1 54 36 17 17 289 -1 unnamed_device 23.6 MiB 0.06 276 1275 269 996 10 62.1 MiB 0.01 0.00 1.56413 -30.7636 -1.56413 1.56413 0.33 0.000211308 0.000195146 0.00522765 0.00483659 -1 -1 -1 -1 22 697 22 6.79088e+06 53888 443629. 1535.05 0.40 0.0360258 0.0302982 22798 101617 -1 574 14 232 281 20802 5741 1.51379 1.51379 -32.6549 -1.51379 0 0 531479. 1839.03 0.02 0.02 0.09 -1 -1 0.02 0.00716795 0.00620991 21 17 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_011bits.v common 1.98 vpr 62.01 MiB -1 -1 0.17 17236 5 0.06 -1 -1 31940 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63496 23 12 76 88 1 60 39 17 17 289 -1 unnamed_device 23.5 MiB 0.06 263 1359 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17720 6 0.06 -1 -1 32036 -1 -1 5 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63792 29 15 95 110 1 77 49 17 17 289 -1 unnamed_device 23.7 MiB 0.07 324 3342 734 2532 76 62.3 MiB 0.03 0.00 2.42352 -48.7848 -2.42352 2.42352 0.34 0.000283292 0.000262432 0.0115124 0.0106785 -1 -1 -1 -1 26 904 32 6.79088e+06 67360 503264. 1741.40 0.48 0.0553618 0.0473417 23662 119890 -1 757 13 322 384 23522 6789 2.15502 2.15502 -49.648 -2.15502 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00885209 0.00771765 29 23 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_015bits.v common 2.30 vpr 62.27 MiB -1 -1 0.17 17660 6 0.06 -1 -1 32064 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63764 31 16 104 120 1 81 52 17 17 289 -1 unnamed_device 23.5 MiB 0.08 317 3641 1047 1889 705 62.3 MiB 0.03 0.00 2.28032 -49.0709 -2.28032 2.28032 0.33 0.000311764 0.00028965 0.0128153 0.0118974 -1 -1 -1 -1 26 896 44 6.79088e+06 67360 503264. 1741.40 0.47 0.0611187 0.0522955 23662 119890 -1 675 11 298 344 27538 10777 2.15502 2.15502 -50.3725 -2.15502 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00864617 0.00757546 31 27 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_016bits.v common 2.48 vpr 62.32 MiB -1 -1 0.18 17592 7 0.06 -1 -1 32008 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63820 33 17 112 129 1 84 56 17 17 289 -1 unnamed_device 23.6 MiB 0.08 457 2945 706 2143 96 62.3 MiB 0.03 0.00 2.65628 -60.2407 -2.65628 2.65628 0.33 0.000333352 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 45 23 153 176 1 119 77 17 17 289 -1 unnamed_device 23.3 MiB 0.15 477 7086 2063 3975 1048 62.5 MiB 0.05 0.00 3.57268 -91.263 -3.57268 3.57268 0.36 0.000445506 0.0004138 0.0204716 0.0190194 -1 -1 -1 -1 32 1120 12 6.79088e+06 121248 586450. 2029.24 0.47 0.0666694 0.0586499 24814 144142 -1 908 9 364 474 24629 7210 3.27175 3.27175 -87.1614 -3.27175 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0105039 0.00938562 45 41 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_024bits.v common 2.58 vpr 62.59 MiB -1 -1 0.17 17684 10 0.08 -1 -1 31972 -1 -1 10 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64088 49 25 166 191 1 129 84 17 17 289 -1 unnamed_device 23.3 MiB 0.19 888 10149 2418 6579 1152 62.6 MiB 0.06 0.00 3.52584 -103.921 -3.52584 3.52584 0.33 0.000474217 0.000440445 0.028013 0.0260292 -1 -1 -1 -1 26 1697 15 6.79088e+06 134720 503264. 1741.40 0.43 0.0796154 0.0704286 23662 119890 -1 1585 14 501 640 47109 11368 3.40054 3.40054 -105.083 -3.40054 0 0 618332. 2139.56 0.03 0.04 0.10 -1 -1 0.03 0.014678 0.0129495 49 44 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_028bits.v common 2.81 vpr 62.74 MiB -1 -1 0.20 17628 11 0.08 -1 -1 32024 -1 -1 12 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64244 57 29 198 227 1 154 98 17 17 289 -1 unnamed_device 23.3 MiB 0.23 831 11348 3274 6773 1301 62.7 MiB 0.07 0.00 4.16358 -130.313 -4.16358 4.16358 0.33 0.000571622 0.000532297 0.0308967 0.0287436 -1 -1 -1 -1 26 1812 27 6.79088e+06 161664 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fixed_k6_frac_N8_22nm.xml adder_048bits.v common 3.47 vpr 63.47 MiB -1 -1 0.26 18060 19 0.10 -1 -1 32316 -1 -1 20 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64996 97 49 340 389 1 268 166 17 17 289 -1 unnamed_device 23.8 MiB 0.35 1595 32542 9530 19534 3478 63.5 MiB 0.17 0.00 6.87725 -295.573 -6.87725 6.87725 0.33 0.000987348 0.000922056 0.0729955 0.0681292 -1 -1 -1 -1 32 3045 22 6.79088e+06 269440 586450. 2029.24 0.63 0.194659 0.175474 24814 144142 -1 2743 18 968 1302 86378 21246 6.58745 6.58745 -293.066 -6.58745 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0363793 0.0325585 103 98 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_064bits.v common 4.24 vpr 64.23 MiB -1 -1 0.16 18356 26 0.11 -1 -1 32464 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65776 129 65 453 518 1 344 218 17 17 289 -1 unnamed_device 24.5 MiB 0.57 1971 49998 15091 29566 5341 64.2 MiB 0.25 0.00 10.4784 -507.086 -10.4784 10.4784 0.33 0.00132893 0.00124528 0.106245 0.0993901 -1 -1 -1 -1 40 3524 26 6.79088e+06 323328 706193. 2443.58 1.34 0.392274 0.354177 26254 175826 -1 3188 13 1107 1495 97622 26410 9.85193 9.85193 -491.088 -9.85193 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0540559 0.0490496 131 131 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_004bits.v common 1.82 vpr 62.44 MiB -1 -1 0.10 17380 1 0.02 -1 -1 30064 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 23.6 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0.00597313 23170 95770 -1 289 11 141 141 13137 3115 1.05067 1.05067 -17.0701 -1.05067 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00365303 0.00321754 13 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_006bits.v common 2.34 vpr 62.30 MiB -1 -1 0.13 17340 1 0.03 -1 -1 29940 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63796 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 23.8 MiB 0.06 100 806 191 526 89 62.3 MiB 0.01 0.00 0.833073 -15.3512 -0.833073 0.833073 0.34 0.000122088 0.000111989 0.00334155 0.00306422 -1 -1 -1 -1 36 229 22 6.87369e+06 55895.4 648988. 2245.63 0.63 0.0342161 0.0282667 26050 158493 -1 180 17 218 218 8477 3065 0.958373 0.958373 -15.1722 -0.958373 0 0 828058. 2865.25 0.05 0.03 0.11 -1 -1 0.05 0.00917581 0.00770806 15 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_007bits.v common 2.03 vpr 62.57 MiB -1 -1 0.14 17352 1 0.02 -1 -1 29992 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64072 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 24.2 MiB 0.05 134 1128 368 603 157 62.6 MiB 0.01 0.00 1.2044 -18.5156 -1.2044 1.2044 0.35 0.000154596 0.000139466 0.00453151 0.00408993 -1 -1 -1 -1 26 307 17 6.87369e+06 41921.5 503264. 1741.40 0.35 0.021363 0.0179662 24322 120374 -1 267 14 146 146 6496 2236 0.989373 0.989373 -20.3361 -0.989373 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00517942 0.0045165 16 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_008bits.v common 1.99 vpr 62.28 MiB -1 -1 0.08 17312 1 0.02 -1 -1 29984 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63776 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.8 MiB 0.05 146 1877 632 931 314 62.3 MiB 0.02 0.00 1.2154 -21.3035 -1.2154 1.2154 0.34 0.000157735 0.000145122 0.00722208 0.00664584 -1 -1 -1 -1 26 297 13 6.87369e+06 41921.5 503264. 1741.40 0.37 0.0248125 0.0212051 24322 120374 -1 273 13 150 150 7334 2479 1.00037 1.00037 -22.2134 -1.00037 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00528613 0.0045942 19 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_009bits.v common 2.16 vpr 62.50 MiB -1 -1 0.14 17120 1 0.02 -1 -1 30024 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63996 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 24.1 MiB 0.07 160 2332 796 1082 454 62.5 MiB 0.02 0.00 1.2264 -24.1787 -1.2264 1.2264 0.34 0.000175241 0.000161634 0.008706 0.00803815 -1 -1 -1 -1 32 327 12 6.87369e+06 41921.5 586450. 2029.24 0.41 0.0280777 0.0241535 25474 144626 -1 286 11 164 164 7398 2391 1.01137 1.01137 -24.7636 -1.01137 0 0 744469. 2576.02 0.04 0.01 0.12 -1 -1 0.04 0.00504681 0.00448936 20 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_010bits.v common 2.07 vpr 62.51 MiB -1 -1 0.15 17260 1 0.02 -1 -1 30120 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.0 MiB 0.07 175 2101 728 1079 294 62.5 MiB 0.02 0.00 1.2374 -27.2124 -1.2374 1.2374 0.34 0.000193984 0.000179478 0.00761103 0.00704442 -1 -1 -1 -1 30 382 13 6.87369e+06 55895.4 556674. 1926.21 0.41 0.0291491 0.0249416 25186 138497 -1 293 13 196 196 9565 2925 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0.02 -1 -1 30204 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64060 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.0 MiB 0.06 241 3493 1152 1593 748 62.6 MiB 0.03 0.00 1.2594 -33.5756 -1.2594 1.2594 0.34 0.00022384 0.000206819 0.0111138 0.0102745 -1 -1 -1 -1 32 501 21 6.87369e+06 69869.2 586450. 2029.24 0.43 0.0379716 0.0326576 25474 144626 -1 425 8 199 199 11182 3603 0.989373 0.989373 -33.3362 -0.989373 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00518953 0.00458893 26 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_013bits.v common 2.80 vpr 62.49 MiB -1 -1 0.15 17308 1 0.02 -1 -1 30232 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.9 MiB 0.06 240 2998 1051 1663 284 62.5 MiB 0.03 0.00 1.2773 -35.5756 -1.2773 1.2773 0.33 0.000246381 0.00022827 0.00947207 0.00876673 -1 -1 -1 -1 30 618 21 6.87369e+06 69869.2 556674. 1926.21 1.12 0.0733815 0.0616699 25186 138497 -1 480 17 350 350 21752 6218 1.04437 1.04437 -34.6874 -1.04437 0 0 706193. 2443.58 0.03 0.02 0.09 -1 -1 0.03 0.00875841 0.00753696 28 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 2.19 vpr 62.53 MiB -1 -1 0.16 17388 1 0.02 -1 -1 30104 -1 -1 7 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 23.9 MiB 0.07 310 4093 1402 1938 753 62.5 MiB 0.03 0.00 1.2814 -39.7439 -1.2814 1.2814 0.33 0.000252751 0.00023371 0.0117669 0.0108889 -1 -1 -1 -1 28 763 21 6.87369e+06 97816.9 531479. 1839.03 0.43 0.041926 0.0362437 24610 126494 -1 614 12 343 343 23714 6541 1.12567 1.12567 -40.5186 -1.12567 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00730899 0.00637495 31 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 2.29 vpr 62.38 MiB -1 -1 0.15 17576 1 0.02 -1 -1 30264 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63880 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.7 MiB 0.08 337 6389 2578 2834 977 62.4 MiB 0.05 0.00 1.65963 -43.635 -1.65963 1.65963 0.34 0.000271225 0.000250996 0.0184151 0.0170486 -1 -1 -1 -1 32 726 25 6.87369e+06 83843 586450. 2029.24 0.47 0.0547587 0.0475343 25474 144626 -1 583 15 400 400 26645 7674 1.12567 1.12567 -42.064 -1.12567 0 0 744469. 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 23.7 MiB 0.08 390 6188 2490 3601 97 62.5 MiB 0.04 0.00 1.68573 -53.5906 -1.68573 1.68573 0.33 0.000329317 0.000306042 0.0173699 0.0161432 -1 -1 -1 -1 30 851 16 6.87369e+06 97816.9 556674. 1926.21 0.44 0.0537216 0.0467985 25186 138497 -1 693 11 381 381 25789 7299 1.13037 1.13037 -51.5244 -1.13037 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0086009 0.00751161 38 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 2.36 vpr 62.71 MiB -1 -1 0.15 17564 1 0.02 -1 -1 30288 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64220 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.7 MiB 0.08 447 8134 3300 4657 177 62.7 MiB 0.06 0.00 1.70773 -60.3017 -1.70773 1.70773 0.33 0.00036247 0.000336699 0.0215112 0.0200033 -1 -1 -1 -1 32 937 23 6.87369e+06 111791 586450. 2029.24 0.50 0.0651527 0.0569837 25474 144626 -1 774 21 527 527 36101 10508 1.18067 1.18067 -56.9294 -1.18067 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0145839 0.0125579 42 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 2.78 vpr 62.66 MiB -1 -1 0.17 17644 1 0.03 -1 -1 30472 -1 -1 10 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 23.6 MiB 0.11 503 9208 3768 5283 157 62.7 MiB 0.06 0.00 1.72973 -67.8771 -1.72973 1.72973 0.33 0.000386869 0.00035906 0.02257 0.0209781 -1 -1 -1 -1 36 1109 22 6.87369e+06 139738 648988. 2245.63 0.82 0.0992719 0.0860563 26050 158493 -1 898 22 643 643 58388 16256 1.24467 1.24467 -62.8028 -1.24467 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0165817 0.0143669 47 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 2.34 vpr 62.91 MiB -1 -1 0.17 17604 1 0.02 -1 -1 30380 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.7 MiB 0.09 607 6023 1283 4464 276 62.9 MiB 0.05 0.00 2.11206 -76.1943 -2.11206 2.11206 0.33 0.000426528 0.000396958 0.0153869 0.0143251 -1 -1 -1 -1 32 1299 16 6.87369e+06 125765 586450. 2029.24 0.48 0.0620614 0.0543264 25474 144626 -1 1097 14 609 609 45524 12761 1.34167 1.34167 -75.6214 -1.34167 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0127044 0.0111413 51 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 2.41 vpr 62.80 MiB -1 -1 0.17 17660 1 0.03 -1 -1 30076 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.5 MiB 0.09 789 12307 2769 8813 725 62.8 MiB 0.08 0.00 2.15606 -94.5222 -2.15606 2.15606 0.33 0.000492644 0.000458135 0.0286183 0.0266446 -1 -1 -1 -1 32 1559 17 6.87369e+06 153712 586450. 2029.24 0.53 0.0833133 0.0738776 25474 144626 -1 1393 18 688 688 59523 16512 1.49997 1.49997 -95.1329 -1.49997 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0173005 0.0151701 58 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 2.57 vpr 63.14 MiB -1 -1 0.17 17576 1 0.03 -1 -1 30072 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.11 981 17205 4139 12245 821 63.1 MiB 0.11 0.00 2.56039 -112.802 -2.56039 2.56039 0.34 0.0005709 0.000533122 0.0389788 0.0363756 -1 -1 -1 -1 32 1799 22 6.87369e+06 167686 586450. 2029.24 0.56 0.106634 0.0949936 25474 144626 -1 1617 15 720 720 63562 16203 1.47797 1.47797 -105.078 -1.47797 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0173981 0.0153283 67 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 2.89 vpr 63.28 MiB -1 -1 0.15 17828 1 0.03 -1 -1 30264 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 24.0 MiB 0.12 1584 31076 9475 18689 2912 63.3 MiB 0.19 0.00 3.45705 -193.743 -3.45705 3.45705 0.34 0.0008684 0.000814632 0.0625391 0.0585774 -1 -1 -1 -1 32 3068 37 6.87369e+06 251529 586450. 2029.24 0.78 0.189406 0.170897 25474 144626 -1 2611 15 1093 1093 100501 26292 1.79097 1.79097 -171.802 -1.79097 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0264197 0.0236566 99 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 3.73 vpr 64.25 MiB -1 -1 0.22 18156 1 0.04 -1 -1 30548 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65796 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.5 MiB 0.14 1992 52618 19565 29996 3057 64.3 MiB 0.34 0.01 4.35372 -280.144 -4.35372 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503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00293029 0.00260954 10 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 1.92 vpr 62.25 MiB -1 -1 0.16 17372 1 0.02 -1 -1 29916 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63744 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 23.5 MiB 0.03 158 587 141 409 37 62.2 MiB 0.01 0.00 0.834592 -14.4431 -0.834592 0.834592 0.34 0.000109323 9.9479e-05 0.00278401 0.00252793 -1 -1 -1 -1 22 303 8 6.89349e+06 42281.5 443629. 1535.05 0.32 0.0144953 0.0122181 23458 102101 -1 278 9 87 87 6583 1789 0.914373 0.914373 -16.0104 -0.914373 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00331916 0.00294637 13 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 2.05 vpr 62.27 MiB -1 -1 0.15 17272 1 0.02 -1 -1 30048 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63760 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 23.6 MiB 0.05 133 1044 310 591 143 62.3 MiB 0.01 0.00 0.833073 -15.9272 -0.833073 0.833073 0.34 0.000124785 0.000114174 0.00422947 0.00386489 -1 -1 -1 -1 26 290 13 6.89349e+06 56375.4 503264. 1741.40 0.36 0.0182724 0.0154763 24322 120374 -1 221 12 125 125 5631 2000 0.94932 0.94932 -16.2556 -0.94932 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.0041284 0.00360823 15 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 2.07 vpr 62.25 MiB -1 -1 0.09 17396 1 0.03 -1 -1 30132 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 23.8 MiB 0.04 133 1204 333 631 240 62.2 MiB 0.01 0.00 1.2044 -18.4031 -1.2044 1.2044 0.34 0.000139573 0.000128145 0.0049121 0.00451093 -1 -1 -1 -1 32 295 12 6.89349e+06 42281.5 586450. 2029.24 0.41 0.0205912 0.0174698 25474 144626 -1 203 14 129 129 5391 1760 0.853073 0.853073 -17.6358 -0.853073 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00488954 0.00422668 16 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 1.99 vpr 62.19 MiB -1 -1 0.15 17216 1 0.02 -1 -1 29988 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63680 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.7 MiB 0.05 147 1877 621 864 392 62.2 MiB 0.02 0.00 1.2154 -21.3086 -1.2154 1.2154 0.33 0.000157194 0.000144466 0.00719049 0.006617 -1 -1 -1 -1 26 326 10 6.89349e+06 42281.5 503264. 1741.40 0.36 0.0239307 0.0204765 24322 120374 -1 297 13 172 172 9130 2854 1.11467 1.11467 -23.1377 -1.11467 0 0 618332. 2139.56 0.03 0.01 0.08 -1 -1 0.03 0.00521984 0.00452385 19 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 2.15 vpr 62.36 MiB -1 -1 0.15 17412 1 0.02 -1 -1 30144 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63856 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 23.9 MiB 0.04 160 2382 879 1128 375 62.4 MiB 0.02 0.00 1.2264 -24.2382 -1.2264 1.2264 0.35 0.000196203 0.000178208 0.0083255 0.00754874 -1 -1 -1 -1 26 391 28 6.89349e+06 42281.5 503264. 1741.40 0.41 0.0303822 0.0257506 24322 120374 -1 301 12 172 172 9169 2958 0.88802 0.88802 -24.0325 -0.88802 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.0054245 0.00471594 20 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 2.13 vpr 62.29 MiB -1 -1 0.16 17316 1 0.02 -1 -1 30208 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63788 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 23.8 MiB 0.05 178 2101 697 1026 378 62.3 MiB 0.03 0.00 1.2374 -27.3972 -1.2374 1.2374 0.34 0.000272143 0.000242871 0.014502 0.0134048 -1 -1 -1 -1 26 398 15 6.89349e+06 56375.4 503264. 1741.40 0.41 0.0366146 0.031747 24322 120374 -1 357 12 211 211 13104 3962 1.00232 1.00232 -27.9123 -1.00232 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00586481 0.00508309 22 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 2.14 vpr 62.36 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30020 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63856 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 23.9 MiB 0.05 194 2488 804 1234 450 62.4 MiB 0.02 0.00 1.2484 -29.9141 -1.2484 1.2484 0.34 0.000209881 0.00019386 0.00831107 0.00768353 -1 -1 -1 -1 32 419 16 6.89349e+06 70469.2 586450. 2029.24 0.44 0.0369654 0.0314569 25474 144626 -1 365 14 187 187 12612 3522 1.15867 1.15867 -31.3059 -1.15867 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00694411 0.00599348 24 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 2.17 vpr 62.26 MiB -1 -1 0.16 17436 1 0.02 -1 -1 30088 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63756 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 23.7 MiB 0.05 217 3493 1104 1725 664 62.3 MiB 0.05 0.00 1.2594 -32.5677 -1.2594 1.2594 0.34 0.000304479 0.000281407 0.0209988 0.0194009 -1 -1 -1 -1 32 482 20 6.89349e+06 70469.2 586450. 2029.24 0.43 0.0482192 0.0420835 25474 144626 -1 389 12 280 280 15448 4965 1.02237 1.02237 -32.661 -1.02237 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00656711 0.00568522 26 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 2.48 vpr 62.37 MiB -1 -1 0.16 17368 1 0.02 -1 -1 30088 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63868 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.8 MiB 0.05 241 2998 936 1427 635 62.4 MiB 0.03 0.00 1.2704 -35.731 -1.2704 1.2704 0.34 0.000238318 0.000220139 0.00954251 0.00882072 -1 -1 -1 -1 36 554 23 6.89349e+06 70469.2 648988. 2245.63 0.68 0.0569241 0.0482567 26050 158493 -1 470 11 304 304 20930 6434 1.17597 1.17597 -35.5601 -1.17597 0 0 828058. 2865.25 0.03 0.02 0.15 -1 -1 0.03 0.00655121 0.00571957 28 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 2.30 vpr 62.49 MiB -1 -1 0.15 17252 1 0.03 -1 -1 30068 -1 -1 7 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 23.8 MiB 0.06 311 4093 1430 1919 744 62.5 MiB 0.03 0.00 1.2814 -39.6 -1.2814 1.2814 0.34 0.00025249 0.000233658 0.0117448 0.0108621 -1 -1 -1 -1 32 651 22 6.89349e+06 98656.9 586450. 2029.24 0.45 0.0440558 0.0379748 25474 144626 -1 546 15 298 298 20497 5584 0.96032 0.96032 -37.5765 -0.96032 0 0 744469. 2576.02 0.03 0.02 0.13 -1 -1 0.03 0.00837419 0.00725538 31 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 2.23 vpr 62.42 MiB -1 -1 0.16 17588 1 0.02 -1 -1 30232 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63916 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.7 MiB 0.07 342 6191 2383 2979 829 62.4 MiB 0.04 0.00 1.65273 -42.5434 -1.65273 1.65273 0.35 0.000272263 0.000252147 0.0177761 0.0164574 -1 -1 -1 -1 28 782 16 6.89349e+06 84563 531479. 1839.03 0.47 0.050838 0.0446254 24610 126494 -1 632 16 412 412 30562 8836 1.09932 1.09932 -43.4614 -1.09932 0 0 648988. 2245.63 0.03 0.03 0.11 -1 -1 0.03 0.00917276 0.00791503 32 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 2.23 vpr 62.59 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30196 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.9 MiB 0.07 355 5727 2349 2359 1019 62.6 MiB 0.04 0.00 1.66373 -46.554 -1.66373 1.66373 0.34 0.00029317 0.000271463 0.0164277 0.0152439 -1 -1 -1 -1 30 761 18 6.89349e+06 84563 556674. 1926.21 0.43 0.0452337 0.0395422 25186 138497 -1 615 14 322 322 20560 5635 1.13667 1.13667 -43.9673 -1.13667 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00900274 0.00782068 35 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 2.26 vpr 62.61 MiB -1 -1 0.15 17668 1 0.02 -1 -1 30096 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64116 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 24.0 MiB 0.07 391 6563 2630 3842 91 62.6 MiB 0.05 0.00 1.68573 -53.2796 -1.68573 1.68573 0.33 0.000328745 0.0003059 0.0180114 0.01674 -1 -1 -1 -1 30 836 17 6.89349e+06 98656.9 556674. 1926.21 0.44 0.0548421 0.0477938 25186 138497 -1 695 15 451 451 29891 8374 1.03337 1.03337 -49.3183 -1.03337 0 0 706193. 2443.58 0.03 0.03 0.13 -1 -1 0.03 0.0118554 0.0102459 38 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 2.36 vpr 62.61 MiB -1 -1 0.15 17628 1 0.02 -1 -1 30352 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.6 MiB 0.06 444 7702 3109 4434 159 62.6 MiB 0.05 0.00 1.70773 -59.9521 -1.70773 1.70773 0.33 0.000367369 0.000341624 0.0204269 0.0189835 -1 -1 -1 -1 32 990 21 6.89349e+06 112751 586450. 2029.24 0.51 0.0631649 0.0551747 25474 144626 -1 819 18 512 512 38144 10646 1.11467 1.11467 -55.3744 -1.11467 0 0 744469. 2576.02 0.06 0.04 0.12 -1 -1 0.06 0.0153282 0.0133693 42 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 2.91 vpr 62.58 MiB -1 -1 0.17 17744 1 0.02 -1 -1 30460 -1 -1 10 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 23.5 MiB 0.10 525 9208 3753 5295 160 62.6 MiB 0.06 0.00 1.72973 -67.5033 -1.72973 1.72973 0.34 0.000392949 0.000365341 0.0227959 0.0211971 -1 -1 -1 -1 38 1007 50 6.89349e+06 140938 678818. 2348.85 0.90 0.1159 0.10007 26626 170182 -1 870 15 498 498 29786 8882 1.34722 1.34722 -61.6964 -1.34722 0 0 902133. 3121.57 0.04 0.03 0.15 -1 -1 0.04 0.0128133 0.0111561 47 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 2.37 vpr 62.61 MiB -1 -1 0.16 17696 1 0.02 -1 -1 30324 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64116 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.5 MiB 0.08 661 9623 2236 7262 125 62.6 MiB 0.07 0.00 2.11206 -77.8242 -2.11206 2.11206 0.33 0.000423349 0.000394636 0.0238414 0.0221996 -1 -1 -1 -1 32 1386 20 6.89349e+06 126845 586450. 2029.24 0.50 0.0733721 0.0645323 25474 144626 -1 1142 15 563 563 48813 12563 1.46697 1.46697 -78.8793 -1.46697 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0131862 0.0115318 51 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 2.40 vpr 63.05 MiB -1 -1 0.14 17632 1 0.02 -1 -1 30148 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64564 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.6 MiB 0.08 791 11419 2578 8125 716 63.1 MiB 0.07 0.00 2.15606 -94.8463 -2.15606 2.15606 0.33 0.000485905 0.00045224 0.0262913 0.0244792 -1 -1 -1 -1 32 1495 15 6.89349e+06 155032 586450. 2029.24 0.50 0.0789967 0.0700395 25474 144626 -1 1370 17 655 655 52543 14035 1.33262 1.33262 -89.2547 -1.33262 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0163034 0.0142892 58 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 2.53 vpr 63.12 MiB -1 -1 0.17 17808 1 0.03 -1 -1 30108 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.09 986 17205 3974 12341 890 63.1 MiB 0.11 0.00 2.56039 -113.021 -2.56039 2.56039 0.33 0.000575876 0.000537719 0.0387672 0.0362165 -1 -1 -1 -1 30 1859 34 6.89349e+06 169126 556674. 1926.21 0.57 0.116327 0.103243 25186 138497 -1 1589 16 746 746 58837 14814 1.31532 1.31532 -101.149 -1.31532 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0180394 0.0158572 67 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 2.95 vpr 63.42 MiB -1 -1 0.17 17756 1 0.03 -1 -1 30288 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1569 31076 8349 20038 2689 63.4 MiB 0.19 0.00 3.45705 -193.838 -3.45705 3.45705 0.33 0.000873253 0.000818313 0.0625323 0.0585782 -1 -1 -1 -1 32 3055 34 6.89349e+06 253689 586450. 2029.24 0.75 0.184089 0.166063 25474 144626 -1 2514 15 1003 1003 86721 22065 1.69397 1.69397 -165.636 -1.69397 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0259565 0.0232087 99 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 3.51 vpr 63.59 MiB -1 -1 0.17 17944 1 0.03 -1 -1 30596 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.4 MiB 0.15 2051 53273 20114 30300 2859 63.6 MiB 0.35 0.01 4.35372 -281.486 -4.35372 4.35372 0.33 0.00119747 0.00112577 0.101104 0.0950117 -1 -1 -1 -1 34 3564 19 6.89349e+06 338252 618332. 2139.56 1.07 0.340154 0.308577 25762 151098 -1 3156 13 1279 1279 97169 24263 1.63107 1.63107 -202.647 -1.63107 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0325631 0.0294317 131 2 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.21 vpr 63.07 MiB -1 -1 0.08 17216 2 0.04 -1 -1 31888 -1 -1 2 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64584 9 5 28 33 1 17 16 17 17 289 -1 unnamed_device 24.4 MiB 0.00 206 58 316 70 231 15 63.1 MiB 0.00 0.00 1.16527 1.11131 -10.1426 -1.11131 1.11131 0.22 7.9062e-05 7.3069e-05 0.000978869 0.000858061 -1 -1 -1 -1 20 133 6 6.55708e+06 24110 394039. 1363.46 0.14 0.00272539 0.00244507 19870 87366 -1 140 6 54 66 3199 1154 0.991107 0.991107 -10.7779 -0.991107 0 0 477104. 1650.88 0.02 0.00 0.04 -1 -1 0.02 0.00168949 0.00155092 13 6 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.26 vpr 63.08 MiB -1 -1 0.07 17456 2 0.04 -1 -1 31896 -1 -1 2 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64592 11 6 34 40 1 20 19 17 17 289 -1 unnamed_device 24.8 MiB 0.01 235 165 169 43 125 1 63.1 MiB 0.00 0.00 1.15051 1.15051 -14.6176 -1.15051 1.15051 0.23 4.9826e-05 4.3461e-05 0.000576171 0.000516811 -1 -1 -1 -1 20 270 9 6.55708e+06 24110 394039. 1363.46 0.15 0.00298509 0.00268579 19870 87366 -1 254 5 41 49 3983 1060 1.15051 1.15051 -15.5478 -1.15051 0 0 477104. 1650.88 0.02 0.00 0.04 -1 -1 0.02 0.00178452 0.0016474 16 7 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.28 vpr 63.05 MiB -1 -1 0.07 17212 3 0.04 -1 -1 31752 -1 -1 3 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64560 13 7 41 48 1 27 23 17 17 289 -1 unnamed_device 24.4 MiB 0.01 288 154 503 122 377 4 63.0 MiB 0.00 0.00 1.59011 1.34971 -17.0626 -1.34971 1.34971 0.23 5.8081e-05 5.1278e-05 0.001237 0.00110407 -1 -1 -1 -1 20 256 9 6.55708e+06 36165 394039. 1363.46 0.15 0.00391025 0.00350799 19870 87366 -1 243 6 70 92 4668 1412 1.22951 1.22951 -17.2303 -1.22951 0 0 477104. 1650.88 0.02 0.01 0.04 -1 -1 0.02 0.00227019 0.00206149 19 9 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.31 vpr 62.96 MiB -1 -1 0.08 17216 3 0.04 -1 -1 31932 -1 -1 4 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64472 15 8 47 55 1 35 27 17 17 289 -1 unnamed_device 24.8 MiB 0.01 442 155 907 221 612 74 63.0 MiB 0.01 0.00 1.71231 1.23151 -18.0927 -1.23151 1.23151 0.22 6.8894e-05 6.1471e-05 0.0018756 0.00167021 -1 -1 -1 -1 22 378 12 6.55708e+06 48220 420624. 1455.45 0.18 0.010518 0.00892074 20158 92377 -1 337 10 122 167 8236 2616 1.23151 1.23151 -20.8181 -1.23151 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00276206 0.00248152 23 10 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.63 vpr 63.03 MiB -1 -1 0.08 17588 3 0.04 -1 -1 31864 -1 -1 6 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64544 17 9 56 65 1 37 32 17 17 289 -1 unnamed_device 24.3 MiB 0.01 481 161 1132 232 876 24 63.0 MiB 0.01 0.00 1.59011 1.34971 -21.5902 -1.34971 1.34971 0.27 8.0064e-05 7.1661e-05 0.00228018 0.00204205 -1 -1 -1 -1 20 272 12 6.55708e+06 72330 394039. 1363.46 0.40 0.0122381 0.01043 19870 87366 -1 284 12 131 162 7562 2867 1.34971 1.34971 -22.2403 -1.34971 0 0 477104. 1650.88 0.02 0.01 0.04 -1 -1 0.02 0.00331893 0.00293692 26 14 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.75 vpr 63.50 MiB -1 -1 0.08 17588 4 0.04 -1 -1 31948 -1 -1 6 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65028 19 10 60 70 1 46 35 17 17 289 -1 unnamed_device 24.8 MiB 0.01 653 226 1802 440 1080 282 63.5 MiB 0.01 0.00 2.19111 1.83817 -26.7688 -1.83817 1.83817 0.23 8.5661e-05 7.6544e-05 0.00313154 0.00280441 -1 -1 -1 -1 26 408 9 6.55708e+06 72330 477104. 1650.88 0.59 0.0215133 0.0180047 21022 109990 -1 393 12 175 252 11265 3487 1.79897 1.79897 -26.967 -1.79897 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00346704 0.00308223 29 13 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.75 vpr 63.50 MiB -1 -1 0.08 17212 4 0.04 -1 -1 32004 -1 -1 7 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 21 11 69 80 1 45 39 17 17 289 -1 unnamed_device 24.9 MiB 0.01 529 261 897 182 697 18 63.5 MiB 0.01 0.00 2.07857 1.95837 -30.8495 -1.95837 1.95837 0.23 9.6795e-05 8.6472e-05 0.00179586 0.00163169 -1 -1 -1 -1 24 511 10 6.55708e+06 84385 448715. 1552.65 0.60 0.0302311 0.0254077 20734 103517 -1 466 9 123 172 11308 3061 1.83817 1.83817 -31.9733 -1.83817 0 0 554710. 1919.41 0.02 0.01 0.05 -1 -1 0.02 0.00346504 0.0031259 33 17 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.67 vpr 63.26 MiB -1 -1 0.08 17600 5 0.04 -1 -1 32008 -1 -1 7 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64776 23 12 76 88 1 52 42 17 17 289 -1 unnamed_device 25.0 MiB 0.01 771 207 3930 1133 1983 814 63.3 MiB 0.01 0.00 2.7665 2.15756 -32.1287 -2.15756 2.15756 0.22 0.000103351 9.2568e-05 0.00623842 0.00560991 -1 -1 -1 -1 26 473 11 6.55708e+06 84385 477104. 1650.88 0.50 0.0314563 0.0266482 21022 109990 -1 432 10 170 219 11782 3614 1.91716 1.91716 -32.3688 -1.91716 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00374793 0.00337898 36 19 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.79 vpr 63.64 MiB -1 -1 0.08 17216 5 0.04 -1 -1 31832 -1 -1 8 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65172 25 13 83 96 1 61 46 17 17 289 -1 unnamed_device 24.8 MiB 0.01 904 221 1850 356 1231 263 63.6 MiB 0.01 0.00 3.1879 2.1433 -36.3224 -2.1433 2.1433 0.22 0.000113375 0.000102402 0.00306364 0.0027673 -1 -1 -1 -1 30 501 11 6.55708e+06 96440 526063. 1820.29 0.60 0.0373232 0.0313535 21886 126133 -1 359 12 213 299 9554 3461 2.0231 2.0231 -33.1408 -2.0231 0 0 666494. 2306.21 0.02 0.01 0.07 -1 -1 0.02 0.00428155 0.00383391 39 21 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.42 vpr 62.89 MiB -1 -1 0.09 17984 5 0.05 -1 -1 32040 -1 -1 10 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64396 27 14 91 105 1 72 51 17 17 289 -1 unnamed_device 24.4 MiB 0.01 838 348 2213 475 1505 233 62.9 MiB 0.01 0.00 2.93506 2.31696 -40.7652 -2.31696 2.31696 0.22 0.000126183 0.000114202 0.00358244 0.00324098 -1 -1 -1 -1 26 746 16 6.55708e+06 120550 477104. 1650.88 0.21 0.0192314 0.0165318 21022 109990 -1 623 11 208 325 14496 4355 2.1851 2.1851 -42.6532 -2.1851 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00488328 0.00438588 44 24 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.89 vpr 63.12 MiB -1 -1 0.09 17596 6 0.05 -1 -1 31452 -1 -1 10 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64640 29 15 95 110 1 74 54 17 17 289 -1 unnamed_device 24.2 MiB 0.02 840 494 1992 357 1549 86 63.1 MiB 0.01 0.00 3.04382 2.92362 -51.8434 -2.92362 2.92362 0.22 0.00013344 0.000121346 0.0032091 0.0029238 -1 -1 -1 -1 30 838 14 6.55708e+06 120550 526063. 1820.29 0.67 0.0390571 0.0329705 21886 126133 -1 758 10 229 373 18230 5006 2.76422 2.76422 -51.4947 -2.76422 0 0 666494. 2306.21 0.02 0.01 0.07 -1 -1 0.02 0.004325 0.00388466 46 23 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 1.69 vpr 62.89 MiB -1 -1 0.09 17396 6 0.05 -1 -1 32048 -1 -1 10 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64396 31 16 104 120 1 74 57 17 17 289 -1 unnamed_device 24.2 MiB 0.01 941 335 4635 1193 2485 957 62.9 MiB 0.02 0.00 2.87676 2.63636 -51.3629 -2.63636 2.63636 0.23 0.000147029 0.000133637 0.0069038 0.00628263 -1 -1 -1 -1 26 734 12 6.55708e+06 120550 477104. 1650.88 0.48 0.0402772 0.0344133 21022 109990 -1 632 11 267 356 20796 6731 2.63636 2.63636 -51.9456 -2.63636 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00551217 0.00494734 50 27 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.37 vpr 62.72 MiB -1 -1 0.09 17600 7 0.05 -1 -1 31796 -1 -1 10 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64228 33 17 112 129 1 80 60 17 17 289 -1 unnamed_device 24.1 MiB 0.02 916 393 2751 484 2197 70 62.7 MiB 0.01 0.00 3.08137 2.84722 -55.8943 -2.84722 2.84722 0.23 0.000153737 0.000139913 0.00434086 0.00396577 -1 -1 -1 -1 22 827 11 6.55708e+06 120550 420624. 1455.45 0.20 0.0220409 0.0190779 20158 92377 -1 736 10 230 311 16768 5148 2.75456 2.75456 -59.488 -2.75456 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00502704 0.00452521 54 30 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.93 vpr 63.90 MiB -1 -1 0.09 17592 7 0.05 -1 -1 32116 -1 -1 13 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65432 37 19 127 146 1 95 69 17 17 289 -1 unnamed_device 24.8 MiB 0.02 1059 482 6555 1850 3443 1262 63.9 MiB 0.02 0.00 3.04582 2.80542 -63.7105 -2.80542 2.80542 0.22 0.000169604 0.000153899 0.0087697 0.00797272 -1 -1 -1 -1 30 1039 14 6.55708e+06 156715 526063. 1820.29 0.68 0.0419468 0.0361873 21886 126133 -1 800 9 267 408 15759 4770 2.47236 2.47236 -60.7748 -2.47236 0 0 666494. 2306.21 0.02 0.01 0.06 -1 -1 0.02 0.00604123 0.00539192 63 35 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.47 vpr 63.06 MiB -1 -1 0.08 17600 8 0.05 -1 -1 32096 -1 -1 14 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64572 41 21 139 160 1 106 76 17 17 289 -1 unnamed_device 24.1 MiB 0.02 1429 658 5676 1327 3947 402 63.1 MiB 0.02 0.00 3.2211 3.08613 -77.565 -3.08613 3.08613 0.24 0.000189407 0.000172319 0.00739107 0.00673116 -1 -1 -1 -1 26 1251 14 6.55708e+06 168770 477104. 1650.88 0.24 0.0294767 0.0257743 21022 109990 -1 1145 12 324 447 27951 7208 3.03216 3.03216 -79.6098 -3.03216 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00654646 0.00591075 67 37 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.17 vpr 63.80 MiB -1 -1 0.08 17588 9 0.05 -1 -1 31900 -1 -1 15 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65328 45 23 153 176 1 107 83 17 17 289 -1 unnamed_device 24.8 MiB 0.02 1416 456 10163 2618 5720 1825 63.8 MiB 0.04 0.00 4.17308 3.86645 -84.2581 -3.86645 3.86645 0.22 0.000202671 0.000183892 0.0159514 0.0146405 -1 -1 -1 -1 28 1275 49 6.55708e+06 180825 500653. 1732.36 0.90 0.0844012 0.0736509 21310 115450 -1 934 13 398 597 29685 9964 3.49108 3.49108 -83.5456 -3.49108 0 0 612192. 2118.31 0.02 0.02 0.06 -1 -1 0.02 0.00778562 0.00700103 73 41 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 1.53 vpr 63.84 MiB -1 -1 0.09 17600 10 0.07 -1 -1 32116 -1 -1 15 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65368 49 25 166 191 1 117 89 17 17 289 -1 unnamed_device 24.8 MiB 0.02 1324 622 9989 3281 5614 1094 63.8 MiB 0.03 0.00 4.86274 4.50214 -102.635 -4.50214 4.50214 0.22 0.000219308 0.000199911 0.0145069 0.0133229 -1 -1 -1 -1 26 1316 13 6.55708e+06 180825 477104. 1650.88 0.25 0.0398474 0.0353994 21022 109990 -1 1132 10 385 534 31434 9087 4.26174 4.26174 -104.467 -4.26174 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00671496 0.00611543 78 44 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.03 vpr 63.82 MiB -1 -1 0.10 17980 11 0.06 -1 -1 32132 -1 -1 19 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65352 57 29 198 227 1 147 105 17 17 289 -1 unnamed_device 24.2 MiB 0.03 1865 897 17148 5241 9470 2437 63.8 MiB 0.05 0.00 5.5625 4.78174 -135.819 -4.78174 4.78174 0.23 0.000309161 0.000282212 0.0222296 0.020281 -1 -1 -1 -1 30 1478 13 6.55708e+06 229045 526063. 1820.29 0.73 0.0732923 0.0644039 21886 126133 -1 1381 11 414 566 31943 8321 4.56888 4.56888 -136.747 -4.56888 0 0 666494. 2306.21 0.03 0.02 0.06 -1 -1 0.03 0.00870588 0.00791114 93 56 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.08 vpr 64.13 MiB -1 -1 0.10 17984 13 0.06 -1 -1 32136 -1 -1 20 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 65 33 224 257 1 164 118 17 17 289 -1 unnamed_device 24.8 MiB 0.03 2133 854 18036 4497 11205 2334 64.1 MiB 0.05 0.00 5.63431 5.39391 -154.533 -5.39391 5.39391 0.22 0.000289186 0.000264153 0.0195316 0.0178613 -1 -1 -1 -1 26 1787 31 6.55708e+06 241100 477104. 1650.88 0.76 0.105328 0.0921709 21022 109990 -1 1574 16 579 808 44794 13734 5.29574 5.29574 -160.248 -5.29574 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.0113832 0.0102065 107 62 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.43 vpr 65.33 MiB -1 -1 0.11 17984 19 0.07 -1 -1 32452 -1 -1 35 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66896 97 49 340 389 1 260 181 17 17 289 -1 unnamed_device 25.6 MiB 0.05 3161 1513 25731 6373 16876 2482 65.3 MiB 0.07 0.00 8.66304 7.82925 -302.074 -7.82925 7.82925 0.22 0.000446882 0.0004115 0.0244123 0.0224224 -1 -1 -1 -1 28 3205 37 6.55708e+06 421925 500653. 1732.36 0.98 0.141672 0.125872 21310 115450 -1 2662 22 887 1263 95212 33089 7.49619 7.49619 -303.373 -7.49619 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0209549 0.0189331 165 98 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.87 vpr 65.39 MiB -1 -1 0.13 18368 26 0.09 -1 -1 32528 -1 -1 41 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 129 65 453 518 1 334 235 17 17 289 -1 unnamed_device 25.6 MiB 0.05 4103 1668 39331 9780 26838 2713 65.4 MiB 0.10 0.00 12.3513 11.4335 -501.015 -11.4335 11.4335 0.22 0.000599957 0.000554309 0.0352785 0.0325073 -1 -1 -1 -1 30 3050 20 6.55708e+06 494255 526063. 1820.29 0.33 0.110151 0.099848 21886 126133 -1 2684 10 776 1028 53642 15366 11.0729 11.0729 -490.306 -11.0729 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0206695 0.0190116 210 131 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.28 abc 29.74 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30452 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25344 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.26 abc 29.74 MiB -1 -1 0.07 17300 1 0.02 -1 -1 30452 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25444 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.30 abc 29.75 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30460 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24636 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.29 abc 29.81 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30524 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 10.64 abc 29.76 MiB -1 -1 0.08 17148 1 0.02 -1 -1 30472 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.28 abc 29.69 MiB -1 -1 0.08 17156 1 0.02 -1 -1 30400 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.28 abc 29.56 MiB -1 -1 0.06 17296 1 0.02 -1 -1 30272 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25484 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.28 abc 29.83 MiB -1 -1 0.07 17296 1 0.02 -1 -1 30548 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25484 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.29 abc 29.75 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30468 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24860 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.31 abc 29.76 MiB -1 -1 0.11 17256 1 0.02 -1 -1 30472 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25096 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.30 abc 29.76 MiB -1 -1 0.08 16948 1 0.02 -1 -1 30472 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25484 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.30 abc 29.75 MiB -1 -1 0.08 17208 1 0.02 -1 -1 30464 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25248 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.31 abc 29.73 MiB -1 -1 0.09 17540 1 0.02 -1 -1 30440 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25336 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.33 abc 29.90 MiB -1 -1 0.09 17300 1 0.02 -1 -1 30620 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25108 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.30 abc 29.87 MiB -1 -1 0.09 17536 1 0.02 -1 -1 30584 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.30 abc 29.95 MiB -1 -1 0.08 17136 1 0.02 -1 -1 30672 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.30 abc 29.95 MiB -1 -1 0.09 17300 1 0.02 -1 -1 30668 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25432 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.31 abc 29.82 MiB -1 -1 0.10 17684 1 0.02 -1 -1 30540 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.32 abc 29.70 MiB -1 -1 0.10 17684 1 0.02 -1 -1 30412 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25864 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.34 abc 29.71 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30428 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.35 abc 29.98 MiB -1 -1 0.11 18452 1 0.03 -1 -1 30704 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.30 abc 29.77 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30484 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25148 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.27 abc 29.72 MiB -1 -1 0.08 17296 1 0.02 -1 -1 30432 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24720 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.34 abc 29.74 MiB -1 -1 0.13 17300 1 0.02 -1 -1 30456 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24384 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.30 abc 29.75 MiB -1 -1 0.08 17676 1 0.02 -1 -1 30460 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24624 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 10.63 abc 29.17 MiB -1 -1 0.08 17296 1 0.02 -1 -1 29872 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24712 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.27 abc 29.11 MiB -1 -1 0.07 17156 1 0.02 -1 -1 29804 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25104 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.29 abc 29.55 MiB -1 -1 0.08 17540 1 0.02 -1 -1 30260 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25104 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.27 abc 29.81 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30524 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24716 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.27 abc 29.19 MiB -1 -1 0.07 17296 1 0.02 -1 -1 29892 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25104 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.30 abc 29.74 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30452 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25104 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.29 abc 29.73 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30444 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 9.32 abc 29.75 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30464 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 10.36 abc 29.76 MiB -1 -1 0.08 17296 1 0.02 -1 -1 30472 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 8.29 abc 29.88 MiB -1 -1 0.08 16880 1 0.02 -1 -1 30592 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 7.28 abc 29.87 MiB -1 -1 0.10 17688 1 0.02 -1 -1 30584 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 5.27 abc 29.92 MiB -1 -1 0.08 17684 1 0.02 -1 -1 30636 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 6.31 abc 29.94 MiB -1 -1 0.11 17296 1 0.02 -1 -1 30660 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24632 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.40 abc 29.85 MiB -1 -1 0.08 17680 1 0.02 -1 -1 30564 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 1.48 abc 29.79 MiB -1 -1 0.08 17680 1 0.03 -1 -1 30504 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.52 abc 29.88 MiB -1 -1 0.09 17684 1 0.03 -1 -1 30600 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25096 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.57 abc 29.95 MiB -1 -1 0.10 18068 1 0.03 -1 -1 30668 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.26 vpr 63.81 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30424 -1 -1 3 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65340 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 25.2 MiB 0.01 238 83 479 97 369 13 63.8 MiB 0.00 0.00 1.07911 0.792048 -9.44301 -0.792048 0.792048 0.23 4.1383e-05 3.5744e-05 0.00119592 0.00104463 -1 -1 -1 -1 20 178 7 6.64007e+06 37674 394039. 1363.46 0.15 0.00330351 0.00295369 20530 87850 -1 166 9 50 50 2813 862 0.890248 0.890248 -11.0134 -0.890248 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00197542 0.00179352 14 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.27 vpr 63.45 MiB -1 -1 0.07 17284 1 0.02 -1 -1 30456 -1 -1 4 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64976 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 25.2 MiB 0.01 284 83 525 102 399 24 63.5 MiB 0.00 0.00 1.03642 0.803048 -11.7481 -0.803048 0.803048 0.23 4.9915e-05 4.3541e-05 0.00119267 0.00105305 -1 -1 -1 -1 20 207 16 6.64007e+06 50232 394039. 1363.46 0.15 0.00416514 0.00365116 20530 87850 -1 179 12 74 74 3381 1262 0.901248 0.901248 -13.0068 -0.901248 0 0 477104. 1650.88 0.02 0.01 0.06 -1 -1 0.02 0.0030862 0.00274485 17 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.46 vpr 63.47 MiB -1 -1 0.10 17288 1 0.02 -1 -1 30456 -1 -1 5 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64996 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 25.2 MiB 0.01 316 197 709 147 526 36 63.5 MiB 0.01 0.00 1.02974 0.825048 -16.3149 -0.825048 0.825048 0.24 5.757e-05 5.0851e-05 0.00154628 0.00138152 -1 -1 -1 -1 20 360 11 6.64007e+06 62790 394039. 1363.46 0.33 0.00741843 0.00641283 20530 87850 -1 333 9 104 104 7584 2093 1.06545 1.06545 -19.3327 -1.06545 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00229516 0.00206885 20 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.72 vpr 63.50 MiB -1 -1 0.08 17288 1 0.03 -1 -1 30444 -1 -1 4 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65020 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 25.2 MiB 0.01 380 241 747 123 590 34 63.5 MiB 0.01 0.00 1.30556 1.20253 -19.2264 -1.20253 1.20253 0.23 6.589e-05 5.8596e-05 0.00155102 0.00138614 -1 -1 -1 -1 26 408 8 6.64007e+06 50232 477104. 1650.88 0.57 0.019026 0.0157054 21682 110474 -1 377 11 93 93 6647 1593 0.943248 0.943248 -20.6462 -0.943248 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00274722 0.00246422 22 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.67 vpr 63.86 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30368 -1 -1 5 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65396 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 25.2 MiB 0.01 448 158 991 170 809 12 63.9 MiB 0.01 0.00 1.2443 1.19636 -19.9652 -1.19636 1.19636 0.23 7.3426e-05 6.5481e-05 0.00188453 0.00169911 -1 -1 -1 -1 26 294 8 6.64007e+06 62790 477104. 1650.88 0.51 0.0189528 0.0158979 21682 110474 -1 286 9 116 116 6005 2126 0.943248 0.943248 -20.7144 -0.943248 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00283558 0.00256151 25 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.48 vpr 63.48 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30472 -1 -1 5 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65008 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 25.2 MiB 0.01 540 167 1189 226 945 18 63.5 MiB 0.01 0.00 1.31656 1.20736 -22.026 -1.20736 1.20736 0.23 8.6108e-05 7.6919e-05 0.0023041 0.00208871 -1 -1 -1 -1 20 342 13 6.64007e+06 62790 394039. 1363.46 0.33 0.00978918 0.0084969 20530 87850 -1 302 9 109 109 4692 1639 1.07445 1.07445 -24.2422 -1.07445 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00314492 0.00284337 28 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.38 vpr 62.97 MiB -1 -1 0.08 17284 1 0.02 -1 -1 30528 -1 -1 6 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64480 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 24.5 MiB 0.02 588 250 1424 247 1152 25 63.0 MiB 0.01 0.00 1.53496 1.21836 -25.7297 -1.21836 1.21836 0.24 9.3886e-05 8.4894e-05 0.00269714 0.00244855 -1 -1 -1 -1 26 451 15 6.64007e+06 75348 477104. 1650.88 0.22 0.0156218 0.0133683 21682 110474 -1 439 12 142 142 8932 2498 0.976248 0.976248 -27.5487 -0.976248 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00423404 0.00375273 31 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.59 vpr 63.63 MiB -1 -1 0.09 17288 1 0.02 -1 -1 30448 -1 -1 7 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65156 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 24.8 MiB 0.01 694 363 2058 437 1445 176 63.6 MiB 0.01 0.00 1.45876 1.22936 -31.2131 -1.22936 1.22936 0.23 9.8803e-05 8.8687e-05 0.00322156 0.00291014 -1 -1 -1 -1 20 638 10 6.64007e+06 87906 394039. 1363.46 0.42 0.0137408 0.0118043 20530 87850 -1 598 12 201 201 13848 3537 0.987248 0.987248 -32.0351 -0.987248 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00375482 0.00333808 35 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.63 vpr 63.63 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30452 -1 -1 8 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65160 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 24.9 MiB 0.01 705 317 2014 346 1603 65 63.6 MiB 0.01 0.00 1.31656 1.24036 -30.9039 -1.24036 1.24036 0.23 0.000104565 9.4799e-05 0.00302151 0.0027464 -1 -1 -1 -1 22 629 14 6.64007e+06 100464 420624. 1455.45 0.49 0.0243249 0.0206114 20818 92861 -1 571 11 246 246 13610 4133 1.09645 1.09645 -34.3431 -1.09645 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.0038428 0.00342744 38 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.74 vpr 64.02 MiB -1 -1 0.11 17284 1 0.02 -1 -1 30468 -1 -1 9 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 25.2 MiB 0.01 776 319 2442 536 1861 45 64.0 MiB 0.01 0.00 1.36056 1.25136 -33.5834 -1.25136 1.25136 0.24 0.000111963 0.000101325 0.00345788 0.00313083 -1 -1 -1 -1 26 619 14 6.64007e+06 113022 477104. 1650.88 0.52 0.024544 0.0208915 21682 110474 -1 536 11 194 194 12865 3664 0.976248 0.976248 -34.5053 -0.976248 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00387396 0.00347062 41 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.85 vpr 63.66 MiB -1 -1 0.07 17284 1 0.02 -1 -1 30460 -1 -1 9 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65188 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 24.9 MiB 0.01 943 346 2825 562 2243 20 63.7 MiB 0.01 0.00 1.49176 1.26236 -35.9631 -1.26236 1.26236 0.23 0.000119374 0.000107263 0.00388458 0.00352004 -1 -1 -1 -1 32 650 14 6.64007e+06 113022 554710. 1919.41 0.68 0.0362657 0.0306325 22834 132086 -1 601 14 260 260 16740 4779 0.923248 0.923248 -35.7196 -0.923248 0 0 701300. 2426.64 0.03 0.01 0.07 -1 -1 0.03 0.00481042 0.00427476 44 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 1.77 vpr 63.59 MiB -1 -1 0.08 17032 1 0.02 -1 -1 30592 -1 -1 9 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65112 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 24.7 MiB 0.01 885 425 2624 463 2138 23 63.6 MiB 0.01 0.00 1.81907 1.62267 -41.2599 -1.62267 1.62267 0.27 0.000126365 0.000114358 0.0036587 0.00332959 -1 -1 -1 -1 26 824 14 6.64007e+06 113022 477104. 1650.88 0.56 0.0367738 0.0311986 21682 110474 -1 686 12 288 288 21074 5653 1.13845 1.13845 -42.187 -1.13845 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00463604 0.00415964 46 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.63 vpr 63.80 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30608 -1 -1 9 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65336 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 24.9 MiB 0.02 1007 336 2909 510 2379 20 63.8 MiB 0.01 0.00 2.11447 1.63367 -41.8152 -1.63367 1.63367 0.23 0.000134938 0.000122447 0.00404431 0.00367801 -1 -1 -1 -1 26 643 9 6.64007e+06 113022 477104. 1650.88 0.45 0.0344379 0.0292381 21682 110474 -1 628 11 262 262 16953 5824 1.14945 1.14945 -43.39 -1.14945 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00604138 0.00543869 49 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.43 vpr 64.22 MiB -1 -1 0.09 17288 1 0.02 -1 -1 30616 -1 -1 11 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65764 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 25.2 MiB 0.02 1092 631 6867 1848 4270 749 64.2 MiB 0.02 0.00 2.09247 1.65567 -54.3354 -1.65567 1.65567 0.23 0.000150516 0.000136788 0.00833076 0.00757099 -1 -1 -1 -1 30 954 13 6.64007e+06 138138 526063. 1820.29 0.25 0.0260082 0.0225915 22546 126617 -1 872 10 249 249 16176 4074 0.943248 0.943248 -49.4729 -0.943248 0 0 666494. 2306.21 0.03 0.01 0.07 -1 -1 0.03 0.00490753 0.00440461 55 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.73 vpr 64.02 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30008 -1 -1 13 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65560 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 24.9 MiB 0.01 1366 587 5289 1117 3980 192 64.0 MiB 0.02 0.00 2.26537 1.67767 -57.9414 -1.67767 1.67767 0.23 0.00016969 0.00015493 0.0063347 0.00577518 -1 -1 -1 -1 26 1002 14 6.64007e+06 163254 477104. 1650.88 0.57 0.0471084 0.0403237 21682 110474 -1 921 14 319 319 22239 6031 1.07325 1.07325 -54.9156 -1.07325 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00606186 0.00539542 62 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 1.93 vpr 64.08 MiB -1 -1 0.08 17668 1 0.02 -1 -1 30372 -1 -1 14 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 25.2 MiB 0.02 1511 689 9160 2319 6031 810 64.1 MiB 0.04 0.00 2.04927 1.69967 -64.4248 -1.69967 1.69967 0.24 0.000419429 0.000390405 0.0166561 0.0154299 -1 -1 -1 -1 26 1229 18 6.64007e+06 175812 477104. 1650.88 0.69 0.0630154 0.0552989 21682 110474 -1 1067 12 353 353 25032 6571 1.06425 1.06425 -60.7054 -1.06425 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00732666 0.00664302 68 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.04 vpr 64.16 MiB -1 -1 0.07 18056 1 0.02 -1 -1 30280 -1 -1 14 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65704 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 25.2 MiB 0.02 1533 741 8668 2003 6116 549 64.2 MiB 0.03 0.00 2.57476 2.07098 -72.0156 -2.07098 2.07098 0.25 0.000193021 0.000175805 0.010399 0.00949855 -1 -1 -1 -1 32 1140 10 6.64007e+06 175812 554710. 1919.41 0.75 0.0474016 0.0413394 22834 132086 -1 1085 11 316 316 21511 5658 1.08425 1.08425 -64.8593 -1.08425 0 0 701300. 2426.64 0.03 0.02 0.08 -1 -1 0.03 0.00775127 0.00697508 73 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 1.96 vpr 64.29 MiB -1 -1 0.09 17464 1 0.02 -1 -1 30488 -1 -1 18 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 25.1 MiB 0.02 1840 829 11816 2855 8450 511 64.3 MiB 0.04 0.00 2.53961 2.11498 -86.5248 -2.11498 2.11498 0.24 0.000227555 0.000207967 0.0135972 0.0124764 -1 -1 -1 -1 26 1605 40 6.64007e+06 226044 477104. 1650.88 0.66 0.078404 0.0685372 21682 110474 -1 1388 15 519 519 39851 10566 1.30145 1.30145 -82.4792 -1.30145 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00847999 0.00758602 86 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.25 vpr 64.41 MiB -1 -1 0.09 18056 1 0.02 -1 -1 30212 -1 -1 19 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 25.2 MiB 0.02 2275 1115 20995 6789 12723 1483 64.4 MiB 0.06 0.00 2.92192 2.50829 -107.042 -2.50829 2.50829 0.23 0.000269838 0.000239541 0.0200461 0.0182978 -1 -1 -1 -1 32 1796 15 6.64007e+06 238602 554710. 1919.41 0.92 0.107473 0.0944051 22834 132086 -1 1645 15 498 498 43978 10303 1.19105 1.19105 -92.1495 -1.19105 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.0090664 0.00813003 97 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 1.71 vpr 64.97 MiB -1 -1 0.09 17672 1 0.03 -1 -1 30496 -1 -1 29 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66532 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 25.2 MiB 0.03 2965 1459 32938 9485 20921 2532 65.0 MiB 0.10 0.00 3.61231 3.38291 -175.44 -3.38291 3.38291 0.23 0.000385243 0.000353671 0.0275764 0.0253627 -1 -1 -1 -1 30 2412 19 6.64007e+06 364182 526063. 1820.29 0.32 0.0742998 0.0669359 22546 126617 -1 2173 14 773 773 59114 15483 1.40705 1.40705 -136.475 -1.40705 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0130146 0.0118962 145 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.91 vpr 65.57 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30712 -1 -1 39 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67140 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 26.0 MiB 0.04 4074 2039 55365 18789 32218 4358 65.6 MiB 0.18 0.00 4.33373 4.25753 -263.369 -4.25753 4.25753 0.23 0.000546765 0.000505774 0.0441183 0.0408237 -1 -1 -1 -1 32 3283 17 6.64007e+06 489762 554710. 1919.41 0.39 0.116701 0.106346 22834 132086 -1 2968 14 1086 1086 74911 19841 1.69925 1.69925 -193.576 -1.69925 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0170589 0.0155872 193 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.30 vpr 63.25 MiB -1 -1 0.07 17284 1 0.02 -1 -1 30088 -1 -1 3 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64768 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 24.9 MiB 0.01 238 75 479 108 353 18 63.2 MiB 0.01 0.00 1.07911 0.781048 -9.33185 -0.781048 0.781048 0.25 9.357e-05 8.5036e-05 0.0024399 0.00220103 -1 -1 -1 -1 20 165 10 6.65987e+06 38034 394039. 1363.46 0.18 0.00483371 0.00434458 20530 87850 -1 139 11 76 76 3137 1197 0.781048 0.781048 -10.3022 -0.781048 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.0022405 0.00200965 14 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.26 vpr 62.95 MiB -1 -1 0.07 17280 1 0.02 -1 -1 30480 -1 -1 4 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64464 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 24.2 MiB 0.01 284 76 497 85 385 27 63.0 MiB 0.00 0.00 1.03642 0.803048 -11.5739 -0.803048 0.803048 0.23 5.1125e-05 4.4933e-05 0.00124173 0.00111098 -1 -1 -1 -1 20 201 10 6.65987e+06 50712 394039. 1363.46 0.15 0.00386556 0.0034642 20530 87850 -1 181 12 98 98 4502 1632 1.01045 1.01045 -12.8746 -1.01045 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00253061 0.00227035 17 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.58 vpr 63.66 MiB -1 -1 0.07 17284 1 0.02 -1 -1 29688 -1 -1 5 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65188 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 24.9 MiB 0.01 316 183 709 148 526 35 63.7 MiB 0.01 0.00 1.02974 0.814048 -15.1984 -0.814048 0.814048 0.23 5.689e-05 5.0305e-05 0.00165434 0.00147903 -1 -1 -1 -1 20 350 16 6.65987e+06 63390 394039. 1363.46 0.44 0.011756 0.00980949 20530 87850 -1 340 17 187 187 13401 3837 1.03245 1.03245 -17.987 -1.03245 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00334724 0.00293122 20 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.59 vpr 63.19 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30452 -1 -1 4 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64708 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 24.7 MiB 0.01 380 234 747 129 578 40 63.2 MiB 0.01 0.00 1.26156 1.17436 -18.6976 -1.17436 1.17436 0.23 7.043e-05 6.3138e-05 0.00157626 0.00141852 -1 -1 -1 -1 20 409 17 6.65987e+06 50712 394039. 1363.46 0.48 0.0115251 0.00969463 20530 87850 -1 399 16 176 176 12920 3525 1.00339 1.00339 -21.1595 -1.00339 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00358569 0.0031662 22 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.53 vpr 63.68 MiB -1 -1 0.07 17672 1 0.02 -1 -1 30380 -1 -1 5 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65204 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 24.9 MiB 0.01 448 159 847 154 684 9 63.7 MiB 0.01 0.00 1.2443 1.18536 -20.0261 -1.18536 1.18536 0.23 7.5018e-05 6.6775e-05 0.00195393 0.00177282 -1 -1 -1 -1 20 331 15 6.65987e+06 63390 394039. 1363.46 0.43 0.0112967 0.00955005 20530 87850 -1 327 14 169 169 9032 3063 1.12359 1.12359 -22.8425 -1.12359 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00363438 0.00321042 25 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.65 vpr 63.30 MiB -1 -1 0.09 16900 1 0.02 -1 -1 30436 -1 -1 5 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64820 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 24.5 MiB 0.01 540 151 1244 259 970 15 63.3 MiB 0.01 0.00 1.31656 1.19636 -21.7095 -1.19636 1.19636 0.23 8.204e-05 7.3735e-05 0.00227233 0.0020487 -1 -1 -1 -1 22 360 16 6.65987e+06 63390 420624. 1455.45 0.51 0.0229437 0.0193246 20818 92861 -1 325 15 201 201 10796 3958 1.03639 1.03639 -24.3988 -1.03639 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00394271 0.00345528 28 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.37 vpr 63.32 MiB -1 -1 0.08 16892 1 0.02 -1 -1 30556 -1 -1 6 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64840 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 24.4 MiB 0.01 588 210 1802 360 1418 24 63.3 MiB 0.01 0.00 1.53496 1.20736 -25.1457 -1.20736 1.20736 0.23 9.7396e-05 8.8372e-05 0.00306471 0.00276262 -1 -1 -1 -1 26 411 18 6.65987e+06 76068 477104. 1650.88 0.22 0.015302 0.0129969 21682 110474 -1 370 11 159 159 8428 2816 0.894189 0.894189 -25.5941 -0.894189 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00350927 0.00312858 31 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.64 vpr 63.44 MiB -1 -1 0.07 17528 1 0.02 -1 -1 30472 -1 -1 7 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64964 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 24.5 MiB 0.01 694 363 2058 427 1457 174 63.4 MiB 0.01 0.00 1.45876 1.21836 -31.2829 -1.21836 1.21836 0.28 9.8216e-05 8.8456e-05 0.00325418 0.00294842 -1 -1 -1 -1 20 621 11 6.65987e+06 88746 394039. 1363.46 0.45 0.0162828 0.0139309 20530 87850 -1 596 14 234 234 18112 4915 1.15659 1.15659 -34.2526 -1.15659 0 0 477104. 1650.88 0.02 0.01 0.06 -1 -1 0.02 0.00412277 0.00363109 35 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.54 vpr 63.44 MiB -1 -1 0.08 17672 1 0.02 -1 -1 29880 -1 -1 8 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64964 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 24.9 MiB 0.01 705 327 1850 317 1450 83 63.4 MiB 0.01 0.00 1.31656 1.22936 -31.4295 -1.22936 1.22936 0.23 0.000104692 9.4898e-05 0.00285057 0.00259403 -1 -1 -1 -1 26 585 13 6.65987e+06 101424 477104. 1650.88 0.43 0.0296487 0.0250953 21682 110474 -1 556 16 236 236 12670 3863 1.06939 1.06939 -34.3453 -1.06939 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00461984 0.00409 38 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.85 vpr 63.88 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30392 -1 -1 9 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65412 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 25.0 MiB 0.01 776 340 2350 468 1844 38 63.9 MiB 0.01 0.00 1.36056 1.24036 -33.3747 -1.24036 1.24036 0.23 0.000225576 0.000206722 0.00456996 0.00419136 -1 -1 -1 -1 26 667 29 6.65987e+06 114102 477104. 1650.88 0.62 0.0398003 0.0338321 21682 110474 -1 592 33 318 318 57453 37023 1.16759 1.16759 -37.1574 -1.16759 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.00798524 0.00687946 41 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.45 vpr 63.50 MiB -1 -1 0.08 17668 1 0.02 -1 -1 30324 -1 -1 9 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 24.9 MiB 0.01 943 326 3617 739 2832 46 63.5 MiB 0.02 0.00 1.49176 1.25136 -35.1959 -1.25136 1.25136 0.23 0.000117876 0.000106205 0.00908273 0.00834518 -1 -1 -1 -1 30 622 13 6.65987e+06 114102 526063. 1820.29 0.26 0.0265602 0.0232305 22546 126617 -1 537 10 180 180 8588 2556 0.911048 0.911048 -34.1663 -0.911048 0 0 666494. 2306.21 0.03 0.01 0.07 -1 -1 0.03 0.00399448 0.00360108 44 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 1.68 vpr 63.89 MiB -1 -1 0.07 17672 1 0.02 -1 -1 30600 -1 -1 9 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65428 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 24.9 MiB 0.01 885 432 2196 385 1786 25 63.9 MiB 0.01 0.00 1.81907 1.61167 -41.1187 -1.61167 1.61167 0.23 0.000132693 0.000120473 0.00315976 0.00287987 -1 -1 -1 -1 26 834 19 6.65987e+06 114102 477104. 1650.88 0.51 0.0356961 0.0302449 21682 110474 -1 705 14 317 317 23560 6250 1.17145 1.17145 -43.2536 -1.17145 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00504275 0.00448784 46 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.79 vpr 63.63 MiB -1 -1 0.07 17672 1 0.02 -1 -1 30592 -1 -1 9 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65156 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 24.5 MiB 0.01 1007 330 2909 508 2376 25 63.6 MiB 0.01 0.00 2.04847 1.62267 -41.4298 -1.62267 1.62267 0.23 0.000134295 0.00012209 0.00403098 0.00367535 -1 -1 -1 -1 26 681 18 6.65987e+06 114102 477104. 1650.88 0.64 0.0412286 0.0350424 21682 110474 -1 647 15 329 329 18779 6422 1.17145 1.17145 -44.3444 -1.17145 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00551528 0.00487629 49 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.74 vpr 63.64 MiB -1 -1 0.08 17280 1 0.02 -1 -1 30596 -1 -1 11 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65168 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 24.9 MiB 0.01 1092 639 7003 1923 4240 840 63.6 MiB 0.02 0.00 2.01041 1.64467 -53.6697 -1.64467 1.64467 0.25 0.000150212 0.000136199 0.00844271 0.007677 -1 -1 -1 -1 26 1009 16 6.65987e+06 139458 477104. 1650.88 0.49 0.048146 0.0409187 21682 110474 -1 950 11 341 341 27759 6824 1.07325 1.07325 -52.1893 -1.07325 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00698376 0.00620754 55 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.80 vpr 63.86 MiB -1 -1 0.10 17668 1 0.02 -1 -1 30592 -1 -1 13 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65396 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 24.5 MiB 0.01 1366 611 7027 1508 5176 343 63.9 MiB 0.03 0.00 2.18331 1.66667 -58.111 -1.66667 1.66667 0.24 0.000210513 0.000192155 0.0100442 0.00920189 -1 -1 -1 -1 28 1031 18 6.65987e+06 164814 500653. 1732.36 0.56 0.0544942 0.0468751 21970 115934 -1 951 15 335 335 22426 6142 1.04619 1.04619 -54.6103 -1.04619 0 0 612192. 2118.31 0.02 0.01 0.06 -1 -1 0.02 0.00651926 0.00581147 62 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 1.67 vpr 63.94 MiB -1 -1 0.09 17672 1 0.02 -1 -1 30652 -1 -1 14 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 24.5 MiB 0.01 1511 697 11296 3104 7159 1033 63.9 MiB 0.04 0.00 2.04927 1.68867 -64.2361 -1.68867 1.68867 0.34 0.000188214 0.000171549 0.0152014 0.0139715 -1 -1 -1 -1 30 1131 16 6.65987e+06 177492 526063. 1820.29 0.27 0.03732 0.0329728 22546 126617 -1 1055 14 400 400 26633 7013 1.13925 1.13925 -62.1121 -1.13925 0 0 666494. 2306.21 0.03 0.02 0.07 -1 -1 0.03 0.00667388 0.00597021 68 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 1.87 vpr 64.37 MiB -1 -1 0.08 17524 1 0.02 -1 -1 30472 -1 -1 14 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 24.9 MiB 0.02 1533 677 6913 1466 5163 284 64.4 MiB 0.02 0.00 2.57476 2.05998 -69.4146 -2.05998 2.05998 0.25 0.000192377 0.000174998 0.00763626 0.00696582 -1 -1 -1 -1 30 1189 15 6.65987e+06 177492 526063. 1820.29 0.64 0.0624134 0.0538212 22546 126617 -1 1060 16 417 417 26988 7388 1.18125 1.18125 -66.1732 -1.18125 0 0 666494. 2306.21 0.02 0.02 0.07 -1 -1 0.02 0.00762415 0.00679059 73 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.02 vpr 64.11 MiB -1 -1 0.09 17348 1 0.02 -1 -1 30536 -1 -1 18 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65644 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 24.9 MiB 0.02 1840 854 13768 3297 9746 725 64.1 MiB 0.05 0.00 2.47361 2.10398 -86.4997 -2.10398 2.10398 0.23 0.000223154 0.000204405 0.0189329 0.0174562 -1 -1 -1 -1 28 1546 18 6.65987e+06 228204 500653. 1732.36 0.74 0.0955569 0.084111 21970 115934 -1 1419 17 507 507 42865 11070 1.25239 1.25239 -80.7522 -1.25239 0 0 612192. 2118.31 0.02 0.02 0.06 -1 -1 0.02 0.00874457 0.00781608 86 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 1.71 vpr 64.25 MiB -1 -1 0.08 17668 1 0.02 -1 -1 30348 -1 -1 19 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 24.9 MiB 0.02 2275 1131 20995 7082 12088 1825 64.2 MiB 0.06 0.00 2.92192 2.49729 -107.815 -2.49729 2.49729 0.23 0.000269954 0.000247525 0.0201729 0.0184865 -1 -1 -1 -1 32 1743 15 6.65987e+06 240882 554710. 1919.41 0.29 0.0503597 0.0448846 22834 132086 -1 1620 14 569 569 45398 11707 1.21819 1.21819 -93.4248 -1.21819 0 0 701300. 2426.64 0.04 0.04 0.12 -1 -1 0.04 0.0141501 0.012611 97 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 1.77 vpr 65.01 MiB -1 -1 0.10 17840 1 0.03 -1 -1 30556 -1 -1 29 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66572 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 24.9 MiB 0.03 2965 1462 32449 8975 21210 2264 65.0 MiB 0.12 0.00 3.61231 3.37191 -174.437 -3.37191 3.37191 0.23 0.000459966 0.000422715 0.0326052 0.0300627 -1 -1 -1 -1 32 2473 14 6.65987e+06 367662 554710. 1919.41 0.34 0.0846952 0.0763662 22834 132086 -1 2267 29 841 841 81945 29869 1.75665 1.75665 -153.182 -1.75665 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0216654 0.0193591 145 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.97 vpr 65.41 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30724 -1 -1 39 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66976 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 26.0 MiB 0.03 4074 1915 54649 18722 31811 4116 65.4 MiB 0.18 0.00 4.32293 4.24653 -259.209 -4.24653 4.24653 0.23 0.00053656 0.000495434 0.0438384 0.040529 -1 -1 -1 -1 32 3348 36 6.65987e+06 494442 554710. 1919.41 0.44 0.136419 0.124283 22834 132086 -1 2938 16 1194 1194 86245 23562 1.69925 1.69925 -191.229 -1.69925 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0204713 0.0188238 193 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 1.71 vpr 64.13 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30164 -1 -1 1 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 25.2 MiB 0.02 186 45 267 64 189 14 64.1 MiB 0.00 0.00 0.942216 0.723895 -9.92048 -0.723895 0.723895 0.24 4.1269e-05 3.5581e-05 0.000857532 0.000748933 -1 -1 -1 -1 26 113 8 6.95648e+06 14475.7 503264. 1741.40 0.48 0.0145841 0.0120035 24322 120374 -1 105 4 30 30 1645 514 0.723895 0.723895 -10.6007 -0.723895 0 0 618332. 2139.56 0.03 0.01 0.08 -1 -1 0.03 0.00235455 0.00212702 7 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 1.49 vpr 64.07 MiB -1 -1 0.07 17292 1 0.02 -1 -1 30244 -1 -1 1 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65612 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 25.2 MiB 0.02 208 70 432 93 307 32 64.1 MiB 0.00 0.00 1.08519 0.701895 -12.2465 -0.701895 0.701895 0.25 4.9405e-05 4.3283e-05 0.00122396 0.00107876 -1 -1 -1 -1 18 161 11 6.95648e+06 14475.7 376052. 1301.22 0.30 0.00523097 0.00453765 22882 88689 -1 141 12 69 69 3460 1174 0.74674 0.74674 -13.0673 -0.74674 0 0 470940. 1629.55 0.02 0.01 0.05 -1 -1 0.02 0.00346806 0.00310217 8 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 1.52 vpr 64.15 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30304 -1 -1 2 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65688 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 25.6 MiB 0.02 291 81 682 180 493 9 64.1 MiB 0.01 0.00 1.08519 0.802432 -14.3707 -0.802432 0.802432 0.24 5.7337e-05 5.0675e-05 0.00163514 0.00145269 -1 -1 -1 -1 20 195 11 6.95648e+06 28951.4 414966. 1435.87 0.33 0.00618855 0.00536814 23170 95770 -1 179 10 70 70 3667 1262 0.74674 0.74674 -15.5357 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00276647 0.00248845 10 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 1.44 vpr 64.15 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30108 -1 -1 2 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 26.0 MiB 0.02 415 108 1105 286 650 169 64.2 MiB 0.01 0.00 1.32908 0.841632 -16.8874 -0.841632 0.841632 0.24 6.9614e-05 6.1942e-05 0.00236817 0.00210352 -1 -1 -1 -1 26 261 20 6.95648e+06 28951.4 503264. 1741.40 0.23 0.0118783 0.0100431 24322 120374 -1 194 17 182 182 7678 2912 1.17833 1.17833 -17.5037 -1.17833 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00353747 0.00310566 11 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 2.04 vpr 64.20 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30412 -1 -1 2 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 25.8 MiB 0.02 414 113 1330 462 761 107 64.2 MiB 0.01 0.00 1.08519 0.863632 -19.4655 -0.863632 0.863632 0.24 7.1492e-05 6.3673e-05 0.00271864 0.0024388 -1 -1 -1 -1 36 227 19 6.95648e+06 28951.4 648988. 2245.63 0.80 0.0273823 0.0226313 26050 158493 -1 204 24 240 240 9992 3588 0.960732 0.960732 -19.2807 -0.960732 0 0 828058. 2865.25 0.03 0.01 0.09 -1 -1 0.03 0.00475944 0.00413697 13 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 1.82 vpr 64.22 MiB -1 -1 0.07 17676 1 0.02 -1 -1 30504 -1 -1 4 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65760 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 26.0 MiB 0.01 576 162 1437 270 1089 78 64.2 MiB 0.01 0.00 1.21049 0.942216 -22.8893 -0.942216 0.942216 0.25 8.0589e-05 7.247e-05 0.00288505 0.00260561 -1 -1 -1 -1 28 407 14 6.95648e+06 57902.7 531479. 1839.03 0.62 0.0268499 0.0224668 24610 126494 -1 347 11 183 183 9263 3101 1.12523 1.12523 -26.3721 -1.12523 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00342604 0.00307793 15 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 1.86 vpr 64.23 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30580 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65776 21 11 76 77 1 49 36 17 17 289 -1 unnamed_device 26.0 MiB 0.01 520 184 2337 519 1327 491 64.2 MiB 0.02 0.00 1.24794 0.885632 -25.2091 -0.885632 0.885632 0.27 0.000211409 0.000196055 0.00901202 0.00834241 -1 -1 -1 -1 26 462 18 6.95648e+06 57902.7 503264. 1741.40 0.63 0.0323948 0.027762 24322 120374 -1 400 8 187 187 10890 3344 1.13623 1.13623 -29.2443 -1.13623 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00323174 0.00292301 17 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 1.83 vpr 64.69 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30460 -1 -1 4 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66244 23 12 83 84 1 55 39 17 17 289 -1 unnamed_device 26.0 MiB 0.01 534 277 1359 266 994 99 64.7 MiB 0.01 0.00 1.21049 0.896632 -29.2681 -0.896632 0.896632 0.24 0.000102723 9.3049e-05 0.00248701 0.00226248 -1 -1 -1 -1 26 624 17 6.95648e+06 57902.7 503264. 1741.40 0.62 0.0269366 0.0225295 24322 120374 -1 566 15 301 301 22333 5932 1.14723 1.14723 -34.2934 -1.14723 0 0 618332. 2139.56 0.02 0.02 0.07 -1 -1 0.02 0.00643446 0.005649 18 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 1.96 vpr 64.30 MiB -1 -1 0.08 17276 1 0.02 -1 -1 30472 -1 -1 5 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 26.0 MiB 0.01 605 254 1693 316 1360 17 64.3 MiB 0.01 0.00 1.21049 0.918632 -30.3075 -0.918632 0.918632 0.24 0.000103531 9.3425e-05 0.00284467 0.00258122 -1 -1 -1 -1 32 569 15 6.95648e+06 72378.4 586450. 2029.24 0.77 0.0325078 0.0272267 25474 144626 -1 506 14 285 285 22039 5984 1.22853 1.22853 -34.5992 -1.22853 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.00436826 0.00387944 20 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 1.82 vpr 64.32 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30468 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 26.0 MiB 0.01 744 314 2178 458 1695 25 64.3 MiB 0.01 0.00 1.21049 0.951632 -33.9892 -0.951632 0.951632 0.24 0.000114819 0.000103699 0.00366722 0.0033457 -1 -1 -1 -1 28 729 30 6.95648e+06 72378.4 531479. 1839.03 0.59 0.0449713 0.0380416 24610 126494 -1 631 18 403 403 32027 8373 1.22233 1.22233 -40.2654 -1.22233 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00544327 0.00480754 21 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 2.39 vpr 64.40 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30476 -1 -1 5 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 29 15 104 105 1 72 49 17 17 289 -1 unnamed_device 26.0 MiB 0.01 715 246 2719 848 1471 400 64.4 MiB 0.01 0.00 1.08519 0.951632 -35.364 -0.951632 0.951632 0.24 0.000119985 0.00010813 0.00428954 0.00389556 -1 -1 -1 -1 44 533 17 6.95648e+06 72378.4 787024. 2723.27 1.08 0.0446344 0.0377658 27778 195446 -1 386 18 374 374 20041 6339 1.17403 1.17403 -35.3751 -1.17403 0 0 997811. 3452.63 0.04 0.02 0.11 -1 -1 0.04 0.00650777 0.0057225 23 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 1.98 vpr 64.38 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30580 -1 -1 5 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 26.0 MiB 0.02 947 386 4223 898 3239 86 64.4 MiB 0.02 0.00 1.51236 1.33396 -39.9535 -1.33396 1.33396 0.25 0.000125213 0.000113182 0.00606356 0.00550845 -1 -1 -1 -1 32 807 18 6.95648e+06 72378.4 586450. 2029.24 0.72 0.0494094 0.0418264 25474 144626 -1 659 15 387 387 24365 6245 1.18923 1.18923 -44.8721 -1.18923 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.00532077 0.00472633 24 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_016bits.v common 1.92 vpr 63.99 MiB -1 -1 0.07 17292 1 0.02 -1 -1 30592 -1 -1 5 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65524 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 25.5 MiB 0.03 897 292 5359 1572 3749 38 64.0 MiB 0.02 0.00 1.42436 1.34496 -41.6298 -1.34496 1.34496 0.24 0.000146972 0.000133743 0.00895157 0.00818407 -1 -1 -1 -1 28 855 20 6.95648e+06 72378.4 531479. 1839.03 0.68 0.0429958 0.0368254 24610 126494 -1 680 15 441 441 27345 8654 1.25523 1.25523 -49.8608 -1.25523 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00570309 0.00508006 25 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_018bits.v common 1.59 vpr 64.45 MiB -1 -1 0.08 16972 1 0.02 -1 -1 30596 -1 -1 5 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 26.0 MiB 0.04 989 557 3661 811 2737 113 64.4 MiB 0.01 0.00 1.38402 1.36696 -53.7585 -1.36696 1.36696 0.24 0.000151196 0.000137918 0.0054351 0.00496446 -1 -1 -1 -1 32 984 16 6.95648e+06 72378.4 586450. 2029.24 0.28 0.0245897 0.0212458 25474 144626 -1 928 14 431 431 37485 8753 1.19403 1.19403 -57.1717 -1.19403 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00601895 0.00536247 28 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 2.18 vpr 64.49 MiB -1 -1 0.09 17292 1 0.02 -1 -1 30612 -1 -1 5 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 41 21 146 147 1 95 67 17 17 289 -1 unnamed_device 25.6 MiB 0.05 1132 525 3467 777 2624 66 64.5 MiB 0.01 0.00 1.51426 1.38896 -57.0848 -1.38896 1.38896 0.26 0.000165315 0.000150428 0.00501244 0.00458007 -1 -1 -1 -1 32 1043 16 6.95648e+06 72378.4 586450. 2029.24 0.86 0.0505249 0.043321 25474 144626 -1 950 14 459 459 34737 8669 1.26433 1.26433 -61.56 -1.26433 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00639534 0.00570402 31 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 2.13 vpr 64.66 MiB -1 -1 0.08 18056 1 0.02 -1 -1 30392 -1 -1 6 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 45 23 160 161 1 107 74 17 17 289 -1 unnamed_device 26.0 MiB 0.06 1395 720 9374 2928 5809 637 64.7 MiB 0.03 0.00 1.94326 1.41096 -67.4934 -1.41096 1.41096 0.24 0.000179143 0.000161835 0.0118445 0.0107473 -1 -1 -1 -1 32 1231 22 6.95648e+06 86854.1 586450. 2029.24 0.83 0.0574222 0.0494085 25474 144626 -1 1160 21 653 653 58712 13516 1.14573 1.14573 -69.9279 -1.14573 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00885175 0.00782168 34 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_024bits.v common 2.11 vpr 65.07 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30272 -1 -1 8 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 49 25 174 175 1 119 82 17 17 289 -1 unnamed_device 26.0 MiB 0.02 1602 875 11296 4663 6552 81 65.1 MiB 0.03 0.00 1.65536 1.43296 -76.7183 -1.43296 1.43296 0.24 0.000189893 0.000172131 0.0130603 0.0118943 -1 -1 -1 -1 30 1506 17 6.95648e+06 115805 556674. 1926.21 0.83 0.0582935 0.050607 25186 138497 -1 1370 17 571 571 54770 11916 1.28823 1.28823 -81.6474 -1.28823 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00827919 0.00738448 38 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_028bits.v common 2.09 vpr 64.95 MiB -1 -1 0.08 17524 1 0.02 -1 -1 30408 -1 -1 9 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 57 29 202 203 1 142 95 17 17 289 -1 unnamed_device 25.8 MiB 0.03 1871 751 14351 6043 8202 106 64.9 MiB 0.05 0.00 1.69936 1.47696 -84.2177 -1.47696 1.47696 0.26 0.00025281 0.000232884 0.0189336 0.0173294 -1 -1 -1 -1 36 1780 37 6.95648e+06 130281 648988. 2245.63 0.68 0.0738443 0.0650373 26050 158493 -1 1305 15 703 703 67106 17088 1.38723 1.38723 -87.9196 -1.38723 0 0 828058. 2865.25 0.03 0.02 0.08 -1 -1 0.03 0.00845282 0.00760553 44 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_032bits.v common 3.60 vpr 64.95 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30488 -1 -1 9 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66512 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 25.6 MiB 0.04 2158 934 16805 5000 11266 539 65.0 MiB 0.05 0.00 2.38249 1.88129 -98.7696 -1.88129 1.88129 0.24 0.000303935 0.000278354 0.0207064 0.0189746 -1 -1 -1 -1 38 1674 26 6.95648e+06 130281 678818. 2348.85 2.21 0.140338 0.12286 26626 170182 -1 1466 19 712 712 60228 14581 1.42923 1.42923 -101.586 -1.42923 0 0 902133. 3121.57 0.03 0.03 0.09 -1 -1 0.03 0.0124642 0.0111288 50 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 5.32 vpr 65.69 MiB -1 -1 0.09 18056 1 0.03 -1 -1 30676 -1 -1 14 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 26.0 MiB 0.05 3293 1259 31408 11237 18751 1420 65.7 MiB 0.12 0.00 3.01593 2.41762 -155.703 -2.41762 2.41762 0.24 0.000535888 0.000504263 0.0416623 0.0386032 -1 -1 -1 -1 44 2684 47 6.95648e+06 202660 787024. 2723.27 3.76 0.245906 0.220222 27778 195446 -1 1982 16 1061 1061 74106 21007 1.49803 1.49803 -146.918 -1.49803 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0198303 0.0181925 74 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 6.94 vpr 66.18 MiB -1 -1 0.11 18060 1 0.03 -1 -1 31072 -1 -1 19 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67772 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 26.7 MiB 0.07 3762 2182 38948 14587 22700 1661 66.2 MiB 0.13 0.00 3.20455 2.95395 -240.326 -2.95395 2.95395 0.26 0.000547665 0.000501165 0.0444461 0.0412839 -1 -1 -1 -1 50 3474 25 6.95648e+06 275038 902133. 3121.57 5.29 0.304726 0.275791 28642 213929 -1 3073 18 1288 1288 126497 27318 1.73803 1.73803 -210.594 -1.73803 0 0 1.08113e+06 3740.92 0.04 0.05 0.12 -1 -1 0.04 0.0218877 0.0200306 98 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_004bits.v common 1.76 vpr 63.88 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30452 -1 -1 1 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 25.2 MiB 0.01 186 45 267 64 194 9 63.9 MiB 0.01 0.00 0.942216 0.583992 -8.95387 -0.583992 0.583992 0.27 9.642e-05 8.6132e-05 0.00173469 0.00157219 -1 -1 -1 -1 26 120 11 6.99608e+06 14715.7 503264. 1741.40 0.55 0.0162204 0.0134467 24322 120374 -1 101 6 38 38 2806 921 0.62144 0.62144 -9.63407 -0.62144 0 0 618332. 2139.56 0.02 0.00 0.06 -1 -1 0.02 0.00190368 0.00176174 7 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_005bits.v common 1.53 vpr 63.97 MiB -1 -1 0.09 17280 1 0.02 -1 -1 30452 -1 -1 1 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65508 11 6 41 42 1 19 18 17 17 289 -1 unnamed_device 25.2 MiB 0.01 206 60 386 72 298 16 64.0 MiB 0.00 0.00 1.08519 0.688132 -11.7579 -0.688132 0.688132 0.24 4.9355e-05 4.3273e-05 0.00110663 0.000977756 -1 -1 -1 -1 20 177 10 6.99608e+06 14715.7 414966. 1435.87 0.36 0.0132997 0.0108769 23170 95770 -1 128 8 54 54 2540 835 0.688132 0.688132 -12.43 -0.688132 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00224508 0.00204327 8 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_006bits.v common 1.74 vpr 64.00 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30444 -1 -1 2 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65540 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 25.2 MiB 0.01 291 91 802 202 586 14 64.0 MiB 0.01 0.00 1.08519 0.791432 -14.38 -0.791432 0.791432 0.24 5.7432e-05 5.0618e-05 0.00186067 0.0016455 -1 -1 -1 -1 24 211 13 6.99608e+06 29431.4 470940. 1629.55 0.58 0.0141922 0.0118181 24034 113901 -1 186 9 62 62 4604 1471 0.74674 0.74674 -15.8342 -0.74674 0 0 586450. 2029.24 0.02 0.01 0.06 -1 -1 0.02 0.00248933 0.00225819 10 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_007bits.v common 1.41 vpr 63.98 MiB -1 -1 0.07 17148 1 0.02 -1 -1 30384 -1 -1 2 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65520 15 8 55 56 1 31 25 17 17 289 -1 unnamed_device 25.2 MiB 0.01 413 101 1141 323 690 128 64.0 MiB 0.01 0.00 1.32908 0.813432 -17.1707 -0.813432 0.813432 0.24 6.8128e-05 6.0125e-05 0.00245567 0.00217768 -1 -1 -1 -1 26 236 14 6.99608e+06 29431.4 503264. 1741.40 0.24 0.0112923 0.00955798 24322 120374 -1 213 10 123 123 5123 1883 1.05303 1.05303 -17.8815 -1.05303 0 0 618332. 2139.56 0.02 0.01 0.07 -1 -1 0.02 0.00287929 0.00258091 11 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 2.02 vpr 63.92 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30296 -1 -1 2 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65456 17 9 62 63 1 36 28 17 17 289 -1 unnamed_device 25.2 MiB 0.01 412 114 1036 306 641 89 63.9 MiB 0.01 0.00 1.08519 0.835432 -18.9954 -0.835432 0.835432 0.24 7.2216e-05 6.4252e-05 0.00218686 0.00196004 -1 -1 -1 -1 34 284 21 6.99608e+06 29431.4 618332. 2139.56 0.78 0.0217316 0.0180549 25762 151098 -1 205 20 201 201 7279 2639 1.07503 1.07503 -18.5674 -1.07503 0 0 787024. 2723.27 0.03 0.01 0.08 -1 -1 0.03 0.0047822 0.0041629 13 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_009bits.v common 1.68 vpr 64.01 MiB -1 -1 0.08 17176 1 0.02 -1 -1 30448 -1 -1 4 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65544 19 10 69 70 1 43 33 17 17 289 -1 unnamed_device 25.6 MiB 0.01 574 154 1021 173 815 33 64.0 MiB 0.01 0.00 1.21049 0.846432 -22.178 -0.846432 0.846432 0.24 8.0462e-05 7.2111e-05 0.0020042 0.00180492 -1 -1 -1 -1 26 362 13 6.99608e+06 58862.7 503264. 1741.40 0.45 0.0218403 0.0182256 24322 120374 -1 330 13 193 193 10182 3468 0.949732 0.949732 -24.4664 -0.949732 0 0 618332. 2139.56 0.03 0.01 0.07 -1 -1 0.03 0.00473314 0.00420055 15 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_010bits.v common 1.97 vpr 63.70 MiB -1 -1 0.10 17292 1 0.02 -1 -1 29980 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65232 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.9 MiB 0.01 544 162 2809 951 1377 481 63.7 MiB 0.01 0.00 1.28156 0.868432 -24.3114 -0.868432 0.868432 0.24 8.8769e-05 7.9646e-05 0.00476361 0.00427393 -1 -1 -1 -1 28 474 31 6.99608e+06 58862.7 531479. 1839.03 0.72 0.0313156 0.026165 24610 126494 -1 395 21 314 314 24439 8382 1.18933 1.18933 -28.8206 -1.18933 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00500055 0.00434835 17 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 1.83 vpr 64.16 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30468 -1 -1 4 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65700 23 12 83 84 1 54 39 17 17 289 -1 unnamed_device 25.2 MiB 0.02 532 273 1689 330 1171 188 64.2 MiB 0.01 0.00 1.21049 0.879432 -28.131 -0.879432 0.879432 0.25 9.8313e-05 8.8651e-05 0.00296163 0.00268092 -1 -1 -1 -1 26 623 18 6.99608e+06 58862.7 503264. 1741.40 0.58 0.0264777 0.0222433 24322 120374 -1 544 11 270 270 18431 5072 1.06403 1.06403 -32.3971 -1.06403 0 0 618332. 2139.56 0.03 0.01 0.06 -1 -1 0.03 0.00372252 0.00333072 18 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 1.49 vpr 63.78 MiB -1 -1 0.09 17532 1 0.02 -1 -1 29624 -1 -1 5 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65308 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 25.2 MiB 0.01 605 273 1918 408 1463 47 63.8 MiB 0.01 0.00 1.21049 0.901432 -30.2851 -0.901432 0.901432 0.24 0.000122347 0.00010992 0.00370936 0.00334849 -1 -1 -1 -1 30 586 14 6.99608e+06 73578.4 556674. 1926.21 0.26 0.0184953 0.0158493 25186 138497 -1 510 14 299 299 21856 6077 0.960732 0.960732 -33.5462 -0.960732 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00446628 0.00395407 20 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 1.54 vpr 64.18 MiB -1 -1 0.08 17532 1 0.02 -1 -1 29884 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 25.2 MiB 0.01 744 364 2014 346 1605 63 64.2 MiB 0.01 0.00 1.21049 0.912432 -34.6536 -0.912432 0.912432 0.25 0.000108566 9.8528e-05 0.00327897 0.00298316 -1 -1 -1 -1 30 765 14 6.99608e+06 73578.4 556674. 1926.21 0.30 0.0179499 0.0154263 25186 138497 -1 657 19 383 383 37818 8969 0.982732 0.982732 -38.8617 -0.982732 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00548102 0.00480409 21 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_014bits.v common 2.12 vpr 64.19 MiB -1 -1 0.08 17288 1 0.02 -1 -1 29860 -1 -1 5 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65732 29 15 104 105 1 72 49 17 17 289 -1 unnamed_device 25.2 MiB 0.01 715 308 2897 867 1495 535 64.2 MiB 0.01 0.00 1.08519 0.934432 -37.2603 -0.934432 0.934432 0.33 0.000116353 0.000104472 0.00436136 0.00394087 -1 -1 -1 -1 32 659 19 6.99608e+06 73578.4 586450. 2029.24 0.80 0.0405173 0.0342335 25474 144626 -1 503 15 316 316 16770 4951 1.16303 1.16303 -40.3804 -1.16303 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.0051829 0.00463108 23 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_015bits.v common 1.80 vpr 64.21 MiB -1 -1 0.09 17292 1 0.02 -1 -1 30580 -1 -1 5 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65752 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 25.6 MiB 0.02 947 388 3253 747 2424 82 64.2 MiB 0.01 0.00 1.42821 1.30576 -39.7527 -1.30576 1.30576 0.25 0.000129015 0.00011721 0.00479255 0.00434749 -1 -1 -1 -1 28 808 13 6.99608e+06 73578.4 531479. 1839.03 0.56 0.0401269 0.0342676 24610 126494 -1 760 16 423 423 35677 9110 1.21603 1.21603 -47.1369 -1.21603 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00554708 0.00489858 24 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_016bits.v common 1.56 vpr 64.61 MiB -1 -1 0.08 17208 1 0.02 -1 -1 30504 -1 -1 5 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66164 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 25.6 MiB 0.02 897 288 5359 1501 3812 46 64.6 MiB 0.02 0.00 1.30576 1.30576 -40.7923 -1.30576 1.30576 0.25 0.000132561 0.000119799 0.00752722 0.00683641 -1 -1 -1 -1 30 796 21 6.99608e+06 73578.4 556674. 1926.21 0.29 0.0264633 0.0229296 25186 138497 -1 638 17 446 446 28249 8724 1.18303 1.18303 -46.7155 -1.18303 0 0 706193. 2443.58 0.03 0.02 0.08 -1 -1 0.03 0.00605321 0.00534917 25 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_018bits.v common 1.61 vpr 64.26 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30600 -1 -1 5 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65804 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 25.8 MiB 0.02 989 450 4021 893 3044 84 64.3 MiB 0.03 0.00 1.32776 1.32776 -49.3309 -1.32776 1.32776 0.26 0.000194239 0.000178028 0.0126807 0.0117646 -1 -1 -1 -1 32 953 19 6.99608e+06 73578.4 586450. 2029.24 0.31 0.034915 0.0307218 25474 144626 -1 817 18 437 437 34491 8677 1.20503 1.20503 -54.2468 -1.20503 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00691724 0.00608941 28 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 1.98 vpr 64.36 MiB -1 -1 0.09 17672 1 0.02 -1 -1 30592 -1 -1 5 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 41 21 146 147 1 94 67 17 17 289 -1 unnamed_device 25.6 MiB 0.02 1130 644 6459 1750 4153 556 64.4 MiB 0.02 0.00 1.37991 1.36076 -60.916 -1.36076 1.36076 0.24 0.000186114 0.000159098 0.00851737 0.00776238 -1 -1 -1 -1 28 1184 20 6.99608e+06 73578.4 531479. 1839.03 0.70 0.0567692 0.0484959 24610 126494 -1 1093 14 462 462 43065 9987 1.23803 1.23803 -65.8346 -1.23803 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00635108 0.00565899 31 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 1.62 vpr 63.93 MiB -1 -1 0.11 17148 1 0.02 -1 -1 30656 -1 -1 6 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65460 45 23 160 161 1 108 74 17 17 289 -1 unnamed_device 24.9 MiB 0.03 1397 728 9374 2538 6055 781 63.9 MiB 0.03 0.00 1.83711 1.38276 -66.0973 -1.38276 1.38276 0.24 0.000421305 0.000392051 0.0145023 0.0133388 -1 -1 -1 -1 30 1267 16 6.99608e+06 88294.1 556674. 1926.21 0.31 0.0443588 0.0391372 25186 138497 -1 1146 13 440 440 28479 7142 1.15673 1.15673 -68.519 -1.15673 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00717088 0.00635823 34 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 2.14 vpr 64.93 MiB -1 -1 0.09 17676 1 0.02 -1 -1 30288 -1 -1 8 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66484 49 25 174 175 1 118 82 17 17 289 -1 unnamed_device 25.7 MiB 0.02 1600 609 11118 4682 6348 88 64.9 MiB 0.03 0.00 1.65536 1.40476 -68.6076 -1.40476 1.40476 0.24 0.000192685 0.000175179 0.013002 0.0118038 -1 -1 -1 -1 30 1317 28 6.99608e+06 117725 556674. 1926.21 0.88 0.0663127 0.0573583 25186 138497 -1 982 17 599 599 43750 10782 1.16103 1.16103 -67.9571 -1.16103 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00887636 0.00795704 38 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 2.51 vpr 65.07 MiB -1 -1 0.10 17912 1 0.02 -1 -1 30284 -1 -1 9 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 57 29 202 203 1 141 95 17 17 289 -1 unnamed_device 25.6 MiB 0.02 1869 719 13271 4497 7728 1046 65.1 MiB 0.04 0.00 1.58221 1.43776 -79.3712 -1.43776 1.43776 0.24 0.000217566 0.000198096 0.0173582 0.0159508 -1 -1 -1 -1 34 1601 28 6.99608e+06 132441 618332. 2139.56 1.19 0.099017 0.0862434 25762 151098 -1 1295 17 702 702 53061 13956 1.37433 1.37433 -84.6639 -1.37433 0 0 787024. 2723.27 0.03 0.02 0.08 -1 -1 0.03 0.00914594 0.00817613 44 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 2.77 vpr 65.24 MiB -1 -1 0.08 18056 1 0.02 -1 -1 30492 -1 -1 9 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66804 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 25.6 MiB 0.03 2158 1080 17058 5311 10070 1677 65.2 MiB 0.05 0.00 2.34329 1.84209 -99.1139 -1.84209 1.84209 0.24 0.000250746 0.000228637 0.018226 0.0166736 -1 -1 -1 -1 36 1981 22 6.99608e+06 132441 648988. 2245.63 1.44 0.11215 0.0976804 26050 158493 -1 1764 16 796 796 77458 17982 1.37903 1.37903 -104.657 -1.37903 0 0 828058. 2865.25 0.03 0.03 0.08 -1 -1 0.03 0.00997723 0.00895521 50 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_048bits.v common 3.12 vpr 65.53 MiB -1 -1 0.10 17672 1 0.03 -1 -1 30532 -1 -1 14 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67100 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 25.6 MiB 0.05 3293 1263 31408 11283 18785 1340 65.5 MiB 0.10 0.00 2.89877 2.37842 -153.027 -2.37842 2.37842 0.26 0.000379941 0.000348214 0.0356847 0.033099 -1 -1 -1 -1 50 2197 19 6.99608e+06 206020 902133. 3121.57 1.49 0.152329 0.136311 28642 213929 -1 2047 17 1015 1015 78973 21212 1.47368 1.47368 -147.234 -1.47368 0 0 1.08113e+06 3740.92 0.04 0.03 0.17 -1 -1 0.04 0.0150746 0.0136766 74 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_064bits.v common 3.03 vpr 65.97 MiB -1 -1 0.10 18060 1 0.03 -1 -1 30700 -1 -1 19 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67556 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 26.0 MiB 0.05 3762 2182 38948 13884 22833 2231 66.0 MiB 0.12 0.00 3.16535 2.91475 -237.268 -2.91475 2.91475 0.24 0.000532882 0.000491782 0.0366132 0.0339179 -1 -1 -1 -1 46 3578 33 6.99608e+06 279598 828058. 2865.25 1.39 0.226092 0.205022 28066 200906 -1 3173 24 1362 1362 170597 51692 1.82318 1.82318 -216.988 -1.82318 0 0 1.01997e+06 3529.29 0.03 0.07 0.11 -1 -1 0.03 0.0289523 0.0263375 98 2 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_004bits.v common 1.36 vpr 63.47 MiB -1 -1 0.08 17672 2 0.04 -1 -1 32076 -1 -1 1 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64992 9 5 28 33 1 16 15 17 17 289 -1 unnamed_device 25.2 MiB 0.01 190 69 267 63 197 7 63.5 MiB 0.00 0.00 0.959892 0.808785 -10.8404 -0.808785 0.808785 0.24 4.0591e-05 3.4926e-05 0.000844916 0.000740121 -1 -1 -1 -1 20 125 6 6.79088e+06 13472 414966. 1435.87 0.18 0.00616629 0.00514699 22510 95286 -1 114 5 38 38 1680 588 0.808785 0.808785 -10.5741 -0.808785 0 0 503264. 1741.40 0.02 0.00 0.05 -1 -1 0.02 0.00198176 0.00182255 8 6 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_005bits.v common 1.49 vpr 63.48 MiB -1 -1 0.08 17676 2 0.04 -1 -1 31880 -1 -1 2 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65000 11 6 34 40 1 22 19 17 17 289 -1 unnamed_device 25.2 MiB 0.01 237 124 294 77 210 7 63.5 MiB 0.00 0.00 1.08519 0.895372 -14.2654 -0.895372 0.895372 0.25 5.1318e-05 4.36e-05 0.000887019 0.00078346 -1 -1 -1 -1 20 223 7 6.79088e+06 26944 414966. 1435.87 0.32 0.00407653 0.00359076 22510 95286 -1 197 9 74 88 4199 1287 0.847985 0.847985 -14.325 -0.847985 0 0 503264. 1741.40 0.03 0.01 0.05 -1 -1 0.03 0.0043613 0.00391642 10 7 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_006bits.v common 1.49 vpr 63.49 MiB -1 -1 0.08 17288 3 0.04 -1 -1 31772 -1 -1 2 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65012 13 7 41 48 1 29 22 17 17 289 -1 unnamed_device 24.9 MiB 0.01 297 103 502 102 394 6 63.5 MiB 0.00 0.00 1.31004 1.18474 -16.2273 -1.18474 1.18474 0.25 5.7959e-05 5.086e-05 0.00129722 0.0011576 -1 -1 -1 -1 20 283 14 6.79088e+06 26944 414966. 1435.87 0.32 0.00607195 0.00526806 22510 95286 -1 218 8 98 101 4560 1562 1.0952 1.0952 -17.4931 -1.0952 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00275122 0.00250367 11 9 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_007bits.v common 1.91 vpr 63.89 MiB -1 -1 0.07 17284 3 0.04 -1 -1 31928 -1 -1 2 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65428 15 8 47 55 1 35 25 17 17 289 -1 unnamed_device 25.2 MiB 0.03 389 109 1105 258 733 114 63.9 MiB 0.01 0.00 1.27433 1.27433 -19.2536 -1.27433 1.27433 0.24 6.8729e-05 6.0936e-05 0.0024328 0.00217642 -1 -1 -1 -1 32 295 19 6.79088e+06 26944 586450. 2029.24 0.68 0.0217585 0.018043 24814 144142 -1 212 12 156 171 7381 2715 1.27433 1.27433 -19.107 -1.27433 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.0030553 0.00271194 13 10 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_008bits.v common 1.44 vpr 63.89 MiB -1 -1 0.08 17288 3 0.04 -1 -1 31768 -1 -1 4 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65420 17 9 56 65 1 41 30 17 17 289 -1 unnamed_device 25.2 MiB 0.04 528 162 904 175 711 18 63.9 MiB 0.01 0.00 2.22292 1.77558 -23.4463 -1.77558 1.77558 0.24 8.5703e-05 7.68e-05 0.00204702 0.0018497 -1 -1 -1 -1 26 384 8 6.79088e+06 53888 503264. 1741.40 0.22 0.0119036 0.0101708 23662 119890 -1 313 8 128 171 7108 2250 1.52498 1.52498 -24.0319 -1.52498 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.0031214 0.00284335 16 14 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_009bits.v common 1.84 vpr 63.89 MiB -1 -1 0.08 17144 4 0.05 -1 -1 31972 -1 -1 3 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65420 19 10 60 70 1 46 32 17 17 289 -1 unnamed_device 25.2 MiB 0.05 575 149 1332 372 880 80 63.9 MiB 0.01 0.00 2.02618 1.65028 -26.6546 -1.65028 1.65028 0.24 0.000198805 0.000183359 0.00372621 0.00341121 -1 -1 -1 -1 26 487 47 6.79088e+06 40416 503264. 1741.40 0.57 0.0391972 0.0328016 23662 119890 -1 356 12 222 252 10601 3951 1.56413 1.56413 -27.5075 -1.56413 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00371953 0.00332621 17 13 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_010bits.v common 1.93 vpr 63.59 MiB -1 -1 0.07 17284 4 0.04 -1 -1 32008 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65112 21 11 69 80 1 55 36 17 17 289 -1 unnamed_device 24.9 MiB 0.07 708 319 1334 274 1048 12 63.6 MiB 0.01 0.00 2.17674 1.77558 -33.7347 -1.77558 1.77558 0.24 9.831e-05 8.865e-05 0.00273705 0.00248438 -1 -1 -1 -1 26 585 13 6.79088e+06 53888 503264. 1741.40 0.68 0.0343214 0.0289106 23662 119890 -1 532 19 211 275 14877 3813 1.72868 1.72868 -33.9654 -1.72868 0 0 618332. 2139.56 0.02 0.02 0.07 -1 -1 0.02 0.00698685 0.00606662 21 17 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_011bits.v common 1.44 vpr 63.59 MiB -1 -1 0.09 17288 5 0.04 -1 -1 31996 -1 -1 4 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65112 23 12 76 88 1 59 39 17 17 289 -1 unnamed_device 25.1 MiB 0.04 647 309 2349 586 1604 159 63.6 MiB 0.01 0.00 2.04408 1.90432 -35.544 -1.90432 1.90432 0.24 0.000118238 0.000107457 0.00490813 0.00447316 -1 -1 -1 -1 26 651 11 6.79088e+06 53888 503264. 1741.40 0.23 0.0188926 0.0162985 23662 119890 -1 557 13 225 288 14298 4157 1.72868 1.72868 -36.0207 -1.72868 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.0045407 0.0040569 23 19 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_012bits.v common 1.82 vpr 63.65 MiB -1 -1 0.08 17516 5 0.05 -1 -1 31860 -1 -1 4 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65180 25 13 83 96 1 65 42 17 17 289 -1 unnamed_device 25.2 MiB 0.07 871 230 2202 525 1546 131 63.7 MiB 0.01 0.00 2.31598 1.85398 -36.7003 -1.85398 1.85398 0.25 0.000112926 0.000101939 0.00483927 0.00441732 -1 -1 -1 -1 20 809 29 6.79088e+06 53888 414966. 1435.87 0.54 0.033559 0.0286641 22510 95286 -1 597 14 328 396 18535 6435 2.01504 2.01504 -43.369 -2.01504 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00495567 0.00441734 24 21 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_013bits.v common 1.99 vpr 63.71 MiB -1 -1 0.08 17672 5 0.05 -1 -1 31776 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65236 27 14 91 105 1 70 46 17 17 289 -1 unnamed_device 24.9 MiB 0.06 882 344 1932 345 1559 28 63.7 MiB 0.01 0.00 2.6855 2.15497 -44.0983 -2.15497 2.15497 0.26 0.00012923 0.000116991 0.00634604 0.00588021 -1 -1 -1 -1 26 843 14 6.79088e+06 67360 503264. 1741.40 0.65 0.046643 0.0397556 23662 119890 -1 678 12 273 372 26621 7251 1.97933 1.97933 -46.0263 -1.97933 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00500649 0.00451197 28 24 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_014bits.v common 1.58 vpr 64.08 MiB -1 -1 0.09 17668 6 0.05 -1 -1 32044 -1 -1 5 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 29 15 95 110 1 77 49 17 17 289 -1 unnamed_device 25.3 MiB 0.05 1027 432 5478 2270 3186 22 64.1 MiB 0.02 0.00 3.53332 2.40562 -50.8745 -2.40562 2.40562 0.24 0.00012953 0.000116903 0.00875141 0.00792578 -1 -1 -1 -1 26 972 22 6.79088e+06 67360 503264. 1741.40 0.27 0.026757 0.0231561 23662 119890 -1 813 31 380 500 68442 36152 2.34404 2.34404 -53.3106 -2.34404 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.00949754 0.00825964 29 23 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_015bits.v common 1.96 vpr 63.75 MiB -1 -1 0.08 17668 6 0.05 -1 -1 32072 -1 -1 6 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65280 31 16 104 120 1 82 53 17 17 289 -1 unnamed_device 25.2 MiB 0.05 1014 332 2825 621 2166 38 63.8 MiB 0.01 0.00 2.52053 2.31609 -50.7794 -2.31609 2.31609 0.24 0.000146686 0.000133027 0.00493021 0.0044852 -1 -1 -1 -1 28 819 17 6.79088e+06 80832 531479. 1839.03 0.68 0.0346292 0.0295211 23950 126010 -1 700 16 321 385 20195 6380 2.14045 2.14045 -51.9148 -2.14045 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00685052 0.00607808 32 27 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_016bits.v common 2.08 vpr 64.12 MiB -1 -1 0.09 17284 7 0.05 -1 -1 31992 -1 -1 6 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65664 33 17 112 129 1 84 56 17 17 289 -1 unnamed_device 25.2 MiB 0.05 981 364 5834 2362 3388 84 64.1 MiB 0.02 0.00 3.03218 2.65628 -57.1434 -2.65628 2.65628 0.24 0.000153552 0.000139165 0.00916918 0.00832645 -1 -1 -1 -1 28 825 26 6.79088e+06 80832 531479. 1839.03 0.76 0.0497422 0.0426136 23950 126010 -1 754 12 389 525 31208 9149 2.35534 2.35534 -56.5683 -2.35534 0 0 648988. 2245.63 0.03 0.02 0.08 -1 -1 0.03 0.00611811 0.00546681 33 30 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_018bits.v common 2.04 vpr 63.85 MiB -1 -1 0.09 17676 7 0.05 -1 -1 32128 -1 -1 8 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65380 37 19 127 146 1 96 64 17 17 289 -1 unnamed_device 25.2 MiB 0.13 1255 408 5906 1307 4456 143 63.8 MiB 0.02 0.00 3.06794 2.69204 -66.697 -2.69204 2.69204 0.24 0.000169757 0.000154163 0.00883051 0.00803267 -1 -1 -1 -1 26 850 20 6.79088e+06 107776 503264. 1741.40 0.64 0.061747 0.0530635 23662 119890 -1 828 12 334 421 23186 6922 2.56674 2.56674 -68.0786 -2.56674 0 0 618332. 2139.56 0.02 0.01 0.07 -1 -1 0.02 0.00646752 0.00580998 38 35 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_020bits.v common 2.29 vpr 63.94 MiB -1 -1 0.09 18052 8 0.05 -1 -1 31900 -1 -1 9 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65472 41 21 139 160 1 108 71 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1178 630 4451 946 3195 310 63.9 MiB 0.02 0.00 3.80452 2.99647 -79.4241 -2.99647 2.99647 0.24 0.000199504 0.000182052 0.00819958 0.00754271 -1 -1 -1 -1 34 1193 25 6.79088e+06 121248 618332. 2139.56 0.97 0.0654025 0.0565595 25102 150614 -1 1046 11 350 457 27043 7039 2.68439 2.68439 -78.9303 -2.68439 0 0 787024. 2723.27 0.03 0.01 0.08 -1 -1 0.03 0.00654397 0.00592552 42 37 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_022bits.v common 2.15 vpr 64.02 MiB -1 -1 0.10 17528 9 0.08 -1 -1 31888 -1 -1 9 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65556 45 23 153 176 1 118 77 17 17 289 -1 unnamed_device 24.9 MiB 0.11 1410 509 4641 949 3407 285 64.0 MiB 0.02 0.00 3.62894 3.32208 -86.6758 -3.32208 3.32208 0.25 0.000206959 0.000188772 0.00822889 0.00760191 -1 -1 -1 -1 28 1187 12 6.79088e+06 121248 531479. 1839.03 0.71 0.0623315 0.0544139 23950 126010 -1 1044 12 432 572 31808 9303 3.14645 3.14645 -89.0297 -3.14645 0 0 648988. 2245.63 0.02 0.02 0.06 -1 -1 0.02 0.00724595 0.00656483 45 41 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_024bits.v common 2.47 vpr 64.10 MiB -1 -1 0.10 17668 10 0.05 -1 -1 32108 -1 -1 10 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65640 49 25 166 191 1 129 84 17 17 289 -1 unnamed_device 24.9 MiB 0.14 1438 732 6672 1366 5033 273 64.1 MiB 0.03 0.00 3.77644 3.52584 -100.737 -3.52584 3.52584 0.24 0.000258531 0.000234864 0.0107348 0.00981197 -1 -1 -1 -1 30 1449 21 6.79088e+06 134720 556674. 1926.21 1.01 0.0803002 0.0698811 24526 138013 -1 1282 14 482 592 37126 9650 3.311 3.311 -102.297 -3.311 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00930377 0.00838084 48 44 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_028bits.v common 2.33 vpr 64.77 MiB -1 -1 0.10 18056 11 0.06 -1 -1 32128 -1 -1 12 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 57 29 198 227 1 154 98 17 17 289 -1 unnamed_device 25.3 MiB 0.17 1929 864 14273 4814 7513 1946 64.8 MiB 0.04 0.00 4.41418 4.16358 -131.462 -4.16358 4.16358 0.24 0.000334761 0.000292296 0.0189418 0.0173284 -1 -1 -1 -1 30 1685 14 6.79088e+06 161664 556674. 1926.21 0.85 0.0902499 0.078844 24526 138013 -1 1424 16 536 704 44687 11240 3.73734 3.73734 -125.06 -3.73734 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.0107723 0.0097122 57 56 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_032bits.v common 1.87 vpr 64.51 MiB -1 -1 0.09 17660 13 0.06 -1 -1 32132 -1 -1 11 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 65 33 224 257 1 173 109 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2161 889 19609 6448 11466 1695 64.5 MiB 0.06 0.00 5.29144 4.91554 -155.687 -4.91554 4.91554 0.24 0.000288751 0.000263615 0.0251435 0.0229999 -1 -1 -1 -1 30 1948 14 6.79088e+06 148192 556674. 1926.21 0.33 0.0638136 0.0568969 24526 138013 -1 1598 11 671 898 50938 14191 4.4893 4.4893 -151.306 -4.4893 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00966942 0.00884341 68 62 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_048bits.v common 2.90 vpr 65.67 MiB -1 -1 0.12 18056 19 0.08 -1 -1 32564 -1 -1 19 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67248 97 49 340 389 1 266 165 17 17 289 -1 unnamed_device 25.6 MiB 0.25 3053 1349 31805 8586 20513 2706 65.7 MiB 0.08 0.00 7.2345 7.17824 -291.108 -7.17824 7.17824 0.24 0.000445752 0.000409263 0.0340212 0.0312669 -1 -1 -1 -1 30 2935 26 6.79088e+06 255968 556674. 1926.21 1.17 0.163293 0.145885 24526 138013 -1 2347 17 983 1280 75466 20764 6.76314 6.76314 -281.839 -6.76314 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0192748 0.0176258 102 98 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_064bits.v common 3.38 vpr 65.30 MiB -1 -1 0.13 18444 26 0.09 -1 -1 32720 -1 -1 25 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66872 129 65 453 518 1 343 219 17 17 289 -1 unnamed_device 25.9 MiB 0.39 4118 1975 48985 14791 29668 4526 65.3 MiB 0.16 0.00 10.9476 10.5717 -512.006 -10.5717 10.5717 0.27 0.000604211 0.000557155 0.0690468 0.0640997 -1 -1 -1 -1 32 4167 26 6.79088e+06 336800 586450. 2029.24 1.29 0.293841 0.266364 24814 144142 -1 3407 11 1203 1624 102575 26684 9.9346 9.9346 -497.018 -9.9346 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0205197 0.0190707 133 131 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_004bits.v common 1.72 vpr 63.71 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30456 -1 -1 2 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65240 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 25.2 MiB 0.03 212 56 376 68 294 14 63.7 MiB 0.00 0.00 1.23249 0.789073 -10.0558 -0.789073 0.789073 0.24 4.1776e-05 3.6353e-05 0.00100959 0.000882855 -1 -1 -1 -1 22 155 9 6.87369e+06 27947.7 443629. 1535.05 0.54 0.00905167 0.00747639 23458 102101 -1 113 8 44 44 2021 661 0.663773 0.663773 -10.1705 -0.663773 0 0 531479. 1839.03 0.02 0.01 0.05 -1 -1 0.02 0.00193781 0.00176492 10 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_005bits.v common 1.79 vpr 63.85 MiB -1 -1 0.08 17676 1 0.02 -1 -1 30368 -1 -1 3 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65384 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 25.6 MiB 0.03 337 201 668 148 451 69 63.9 MiB 0.01 0.00 1.11738 0.811073 -14.6592 -0.811073 0.811073 0.25 5.759e-05 5.0553e-05 0.00200373 0.00176382 -1 -1 -1 -1 30 309 9 6.87369e+06 41921.5 556674. 1926.21 0.54 0.0204044 0.0166664 25186 138497 -1 287 8 80 80 5048 1229 0.936373 0.936373 -16.691 -0.936373 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00219224 0.00198208 13 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_006bits.v common 1.63 vpr 63.92 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30476 -1 -1 4 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65456 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 25.3 MiB 0.03 296 154 738 162 543 33 63.9 MiB 0.00 0.00 0.981892 1.03835 -16.7722 -1.03835 1.03835 0.24 5.7593e-05 5.0774e-05 0.00155182 0.0013753 -1 -1 -1 -1 20 381 15 6.87369e+06 55895.4 414966. 1435.87 0.48 0.00782866 0.00668543 23170 95770 -1 331 11 113 113 8617 2387 1.08367 1.08367 -19.4324 -1.08367 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00256891 0.00229214 15 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_007bits.v common 2.01 vpr 63.78 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30452 -1 -1 3 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65308 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 25.0 MiB 0.04 404 127 824 169 639 16 63.8 MiB 0.01 0.00 1.27304 1.2044 -18.2318 -1.2044 1.2044 0.25 9.0894e-05 7.8934e-05 0.00274558 0.00249615 -1 -1 -1 -1 30 286 12 6.87369e+06 41921.5 556674. 1926.21 0.76 0.0250763 0.0208659 25186 138497 -1 237 11 140 140 5141 1808 0.989373 0.989373 -19.8349 -0.989373 0 0 706193. 2443.58 0.03 0.01 0.08 -1 -1 0.03 0.00277701 0.00249233 16 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_008bits.v common 1.44 vpr 63.88 MiB -1 -1 0.07 17184 1 0.02 -1 -1 30432 -1 -1 3 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65416 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 25.6 MiB 0.04 469 149 997 232 705 60 63.9 MiB 0.01 0.00 1.3407 1.2154 -21.0785 -1.2154 1.2154 0.24 7.2964e-05 6.5122e-05 0.0020257 0.00181191 -1 -1 -1 -1 26 301 14 6.87369e+06 41921.5 503264. 1741.40 0.22 0.0115931 0.00981649 24322 120374 -1 267 14 141 141 5701 2184 0.978373 0.978373 -22.318 -0.978373 0 0 618332. 2139.56 0.02 0.01 0.07 -1 -1 0.02 0.00381328 0.00334326 19 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_009bits.v common 1.50 vpr 63.88 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30356 -1 -1 3 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65416 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 25.6 MiB 0.04 599 160 2832 1028 1250 554 63.9 MiB 0.01 0.00 1.68574 1.2264 -24.1659 -1.2264 1.2264 0.24 8.1862e-05 7.2582e-05 0.00499751 0.00445979 -1 -1 -1 -1 32 342 9 6.87369e+06 41921.5 586450. 2029.24 0.27 0.0174207 0.0148924 25474 144626 -1 282 13 175 175 10291 3253 1.01137 1.01137 -24.6383 -1.01137 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.00353222 0.00312488 20 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_010bits.v common 1.98 vpr 63.95 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30540 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65484 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 25.6 MiB 0.04 623 242 2691 801 1272 618 63.9 MiB 0.01 0.00 1.5583 1.2374 -27.5669 -1.2374 1.2374 0.24 8.9243e-05 7.9874e-05 0.00452405 0.00406905 -1 -1 -1 -1 32 469 18 6.87369e+06 55895.4 586450. 2029.24 0.75 0.0254886 0.0214091 25474 144626 -1 417 16 245 245 15919 4276 1.11467 1.11467 -29.6904 -1.11467 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.00414876 0.00363803 22 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_011bits.v common 1.80 vpr 63.95 MiB -1 -1 0.08 17272 1 0.02 -1 -1 30444 -1 -1 5 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65480 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 25.2 MiB 0.04 816 226 1740 328 1393 19 63.9 MiB 0.01 0.00 1.6243 1.2484 -31.1833 -1.2484 1.2484 0.26 0.000189975 0.000173605 0.00398219 0.00362859 -1 -1 -1 -1 30 420 17 6.87369e+06 69869.2 556674. 1926.21 0.52 0.0273873 0.0231806 25186 138497 -1 374 10 175 175 9634 2666 0.886073 0.886073 -29.465 -0.886073 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00346491 0.00310787 24 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_012bits.v common 1.93 vpr 64.02 MiB -1 -1 0.09 17284 1 0.02 -1 -1 30448 -1 -1 5 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 25.6 MiB 0.04 697 203 1918 378 1524 16 64.0 MiB 0.01 0.00 1.31566 1.2594 -32.0153 -1.2594 1.2594 0.25 0.000103272 9.2986e-05 0.00311303 0.00281427 -1 -1 -1 -1 28 507 20 6.87369e+06 69869.2 531479. 1839.03 0.66 0.0324221 0.0271882 24610 126494 -1 465 16 290 290 16133 5368 1.15867 1.15867 -36.1502 -1.15867 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00457912 0.00402788 26 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_013bits.v common 1.57 vpr 64.03 MiB -1 -1 0.13 17532 1 0.03 -1 -1 30440 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65564 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 25.6 MiB 0.04 813 341 1686 290 1386 10 64.0 MiB 0.01 0.00 1.32666 1.2704 -36.5095 -1.2704 1.2704 0.24 0.000109773 9.9396e-05 0.00290007 0.00263813 -1 -1 -1 -1 30 655 12 6.87369e+06 69869.2 556674. 1926.21 0.27 0.018653 0.0160027 25186 138497 -1 554 13 288 288 13777 4010 1.18067 1.18067 -39.3299 -1.18067 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00549287 0.00483231 28 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 2.02 vpr 64.45 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30460 -1 -1 7 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 25.6 MiB 0.05 813 369 2307 425 1796 86 64.4 MiB 0.01 0.00 1.2814 1.2814 -39.6325 -1.2814 1.2814 0.26 0.000117386 0.000106447 0.00385623 0.00350852 -1 -1 -1 -1 30 719 15 6.87369e+06 97816.9 556674. 1926.21 0.74 0.0328918 0.027949 25186 138497 -1 664 16 345 345 22747 5958 1.06637 1.06637 -41.9394 -1.06637 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00503821 0.00443319 31 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 1.87 vpr 64.09 MiB -1 -1 0.07 17292 1 0.02 -1 -1 30596 -1 -1 6 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65628 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 25.6 MiB 0.06 982 485 5399 1393 3244 762 64.1 MiB 0.03 0.00 2.02863 1.65273 -45.9173 -1.65273 1.65273 0.26 0.000164789 0.000150791 0.0115039 0.0105091 -1 -1 -1 -1 30 862 17 6.87369e+06 83843 556674. 1926.21 0.57 0.0508753 0.0437617 25186 138497 -1 828 15 387 387 32478 7816 1.18967 1.18967 -48.8843 -1.18967 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00535564 0.00471064 32 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 1.54 vpr 64.53 MiB -1 -1 0.08 17676 1 0.02 -1 -1 30332 -1 -1 6 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 25.6 MiB 0.06 1128 462 6690 1697 4688 305 64.5 MiB 0.02 0.00 2.29023 1.66373 -49.0046 -1.66373 1.66373 0.24 0.000139914 0.000125894 0.00936706 0.00845406 -1 -1 -1 -1 30 869 12 6.87369e+06 83843 556674. 1926.21 0.29 0.0340396 0.0295893 25186 138497 -1 806 15 402 402 29736 7468 1.06437 1.06437 -48.4603 -1.06437 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00592819 0.00525594 35 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 2.13 vpr 64.18 MiB -1 -1 0.07 17292 1 0.02 -1 -1 30440 -1 -1 7 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65720 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 25.6 MiB 0.06 990 533 3188 655 2384 149 64.2 MiB 0.01 0.00 1.74199 1.68573 -55.8065 -1.68573 1.68573 0.24 0.00015175 0.000137814 0.00450851 0.00411922 -1 -1 -1 -1 32 956 12 6.87369e+06 97816.9 586450. 2029.24 0.88 0.0448108 0.0381352 25474 144626 -1 907 16 422 422 33967 8194 1.13037 1.13037 -56.5331 -1.13037 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00619556 0.00545455 38 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 1.89 vpr 63.81 MiB -1 -1 0.08 17676 1 0.02 -1 -1 30580 -1 -1 8 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65344 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 25.2 MiB 0.06 1415 439 3814 728 2915 171 63.8 MiB 0.02 0.00 1.7716 1.70773 -58.9105 -1.70773 1.70773 0.24 0.000165807 0.000151395 0.00509435 0.00466484 -1 -1 -1 -1 30 943 12 6.87369e+06 111791 556674. 1926.21 0.58 0.042865 0.0367532 25186 138497 -1 817 11 419 419 21319 6697 1.26667 1.26667 -61.1999 -1.26667 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00538129 0.0048225 42 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 2.18 vpr 64.32 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30296 -1 -1 10 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 25.6 MiB 0.08 1570 650 10204 2666 7106 432 64.3 MiB 0.04 0.00 2.07263 1.72973 -70.7265 -1.72973 1.72973 0.24 0.000180482 0.000164557 0.0121811 0.0110423 -1 -1 -1 -1 28 1331 15 6.87369e+06 139738 531479. 1839.03 0.84 0.0675135 0.0586636 24610 126494 -1 1186 15 555 555 41077 10421 1.18067 1.18067 -69.0636 -1.18067 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00682274 0.00605597 47 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 2.13 vpr 64.50 MiB -1 -1 0.10 18060 1 0.02 -1 -1 30260 -1 -1 9 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 25.6 MiB 0.06 1728 753 10163 2514 7290 359 64.5 MiB 0.03 0.00 2.60897 2.11206 -79.0843 -2.11206 2.11206 0.24 0.000198774 0.00018064 0.0116708 0.0106316 -1 -1 -1 -1 28 1443 22 6.87369e+06 125765 531479. 1839.03 0.83 0.0743601 0.0644676 24610 126494 -1 1279 14 625 625 48859 12537 1.21637 1.21637 -75.9973 -1.21637 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00703586 0.00628228 51 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 1.72 vpr 63.97 MiB -1 -1 0.09 18060 1 0.02 -1 -1 30424 -1 -1 11 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65508 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1802 821 10309 2515 7055 739 64.0 MiB 0.04 0.00 2.40666 2.15606 -92.7202 -2.15606 2.15606 0.27 0.000228156 0.000208111 0.0115492 0.0105766 -1 -1 -1 -1 32 1566 13 6.87369e+06 153712 586450. 2029.24 0.34 0.0482663 0.0427322 25474 144626 -1 1367 16 629 629 42642 11312 1.38567 1.38567 -90.5462 -1.38567 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00844629 0.00753366 58 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 1.73 vpr 64.96 MiB -1 -1 0.08 18060 1 0.02 -1 -1 30500 -1 -1 12 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66524 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 25.2 MiB 0.07 1930 880 15627 3694 10983 950 65.0 MiB 0.05 0.00 2.65269 2.56039 -107.701 -2.56039 2.56039 0.24 0.000253236 0.00023166 0.0162425 0.0148662 -1 -1 -1 -1 32 1756 16 6.87369e+06 167686 586450. 2029.24 0.33 0.047179 0.0417844 25474 144626 -1 1493 16 685 685 50430 12966 1.32437 1.32437 -97.9203 -1.32437 0 0 744469. 2576.02 0.03 0.03 0.09 -1 -1 0.03 0.0106361 0.00952148 67 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 1.85 vpr 64.89 MiB -1 -1 0.09 17672 1 0.03 -1 -1 30508 -1 -1 18 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66448 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3166 1519 32420 11737 18188 2495 64.9 MiB 0.10 0.00 3.83296 3.45705 -190.27 -3.45705 3.45705 0.24 0.000392513 0.000360602 0.0298853 0.0274653 -1 -1 -1 -1 32 2673 32 6.87369e+06 251529 586450. 2029.24 0.40 0.093092 0.0839451 25474 144626 -1 2346 12 984 984 82123 21073 1.47437 1.47437 -151.051 -1.47437 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0121083 0.0110706 99 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 3.03 vpr 65.89 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30700 -1 -1 24 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67476 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 26.4 MiB 0.09 4215 1893 53273 19656 30087 3530 65.9 MiB 0.17 0.00 4.72962 4.35372 -277.877 -4.35372 4.35372 0.24 0.000536461 0.000495991 0.0453219 0.0419007 -1 -1 -1 -1 36 3520 23 6.87369e+06 335372 648988. 2245.63 1.40 0.224535 0.203023 26050 158493 -1 2967 15 1307 1307 101615 26086 1.75637 1.75637 -205.78 -1.75637 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0180671 0.0165087 131 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_004bits.v common 1.27 vpr 63.64 MiB -1 -1 0.08 17296 1 0.02 -1 -1 30428 -1 -1 2 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65172 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 24.8 MiB 0.02 212 58 396 77 301 18 63.6 MiB 0.00 0.00 1.23249 0.789073 -10.1079 -0.789073 0.789073 0.24 4.1089e-05 3.5592e-05 0.0010285 0.000897184 -1 -1 -1 -1 20 157 10 6.89349e+06 28187.7 414966. 1435.87 0.16 0.00332141 0.00293392 23170 95770 -1 126 11 47 47 2750 988 0.91632 0.91632 -11.0957 -0.91632 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00207966 0.00187057 10 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 1.95 vpr 63.29 MiB -1 -1 0.07 17676 1 0.02 -1 -1 30456 -1 -1 3 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64808 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 24.5 MiB 0.02 337 201 668 159 420 89 63.3 MiB 0.01 0.00 1.12358 0.817273 -14.7188 -0.817273 0.817273 0.25 4.9791e-05 4.3821e-05 0.0019764 0.0017713 -1 -1 -1 -1 30 320 35 6.89349e+06 42281.5 556674. 1926.21 0.73 0.0226418 0.0187298 25186 138497 -1 287 8 86 86 6447 1544 0.936373 0.936373 -16.8555 -0.936373 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00218328 0.00194766 13 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 1.69 vpr 63.15 MiB -1 -1 0.06 17676 1 0.02 -1 -1 30428 -1 -1 4 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64664 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 25.0 MiB 0.03 296 177 636 142 467 27 63.1 MiB 0.00 0.00 0.981892 0.981892 -17.0458 -0.981892 0.981892 0.25 5.9479e-05 5.0802e-05 0.0013981 0.00123754 -1 -1 -1 -1 22 371 12 6.89349e+06 56375.4 443629. 1535.05 0.47 0.0124495 0.0102737 23458 102101 -1 312 10 102 102 6620 1815 1.06362 1.06362 -18.462 -1.06362 0 0 531479. 1839.03 0.02 0.01 0.05 -1 -1 0.02 0.00244682 0.00219573 15 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 1.76 vpr 63.79 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30472 -1 -1 3 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65316 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 25.6 MiB 0.03 404 129 786 171 602 13 63.8 MiB 0.01 0.00 1.27304 1.2044 -18.4111 -1.2044 1.2044 0.24 6.7188e-05 5.9544e-05 0.00170875 0.00152223 -1 -1 -1 -1 24 319 15 6.89349e+06 42281.5 470940. 1629.55 0.52 0.0194585 0.0159981 24034 113901 -1 306 8 149 149 9436 3202 0.989373 0.989373 -21.4638 -0.989373 0 0 586450. 2029.24 0.02 0.01 0.07 -1 -1 0.02 0.00251805 0.00227062 16 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 1.48 vpr 63.77 MiB -1 -1 0.08 17284 1 0.02 -1 -1 30360 -1 -1 3 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 25.1 MiB 0.03 469 149 997 246 695 56 63.8 MiB 0.01 0.00 1.23249 1.2154 -21.0401 -1.2154 1.2154 0.26 7.6619e-05 6.8311e-05 0.00318806 0.00289838 -1 -1 -1 -1 26 339 10 6.89349e+06 42281.5 503264. 1741.40 0.23 0.0125029 0.0106788 24322 120374 -1 242 13 140 140 5387 2137 0.989373 0.989373 -22.2587 -0.989373 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00322621 0.00286052 19 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 2.08 vpr 63.78 MiB -1 -1 0.11 17284 1 0.02 -1 -1 30136 -1 -1 3 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65308 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 25.2 MiB 0.03 599 160 2832 996 1143 693 63.8 MiB 0.01 0.00 1.65894 1.2264 -24.2203 -1.2264 1.2264 0.24 8.0585e-05 7.2032e-05 0.00504873 0.00451425 -1 -1 -1 -1 32 320 13 6.89349e+06 42281.5 586450. 2029.24 0.72 0.031913 0.0266647 25474 144626 -1 244 13 147 147 6076 2054 0.84402 0.84402 -21.7627 -0.84402 0 0 744469. 2576.02 0.03 0.01 0.09 -1 -1 0.03 0.0037204 0.00328399 20 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 2.08 vpr 63.39 MiB -1 -1 0.12 17292 1 0.02 -1 -1 30352 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64912 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.5 MiB 0.03 623 175 2691 919 1290 482 63.4 MiB 0.01 0.00 1.4832 1.2374 -27.1082 -1.2374 1.2374 0.24 8.8467e-05 7.9346e-05 0.00452108 0.00406212 -1 -1 -1 -1 32 382 18 6.89349e+06 56375.4 586450. 2029.24 0.73 0.0326297 0.0272524 25474 144626 -1 292 10 145 145 6986 2360 0.88802 0.88802 -25.1184 -0.88802 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.0032407 0.00290434 22 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 1.94 vpr 63.50 MiB -1 -1 0.10 17284 1 0.02 -1 -1 30488 -1 -1 5 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 24.8 MiB 0.03 816 189 1604 298 1238 68 63.5 MiB 0.01 0.00 1.6243 1.2484 -30.1698 -1.2484 1.2484 0.25 9.8357e-05 8.8621e-05 0.00279691 0.00253145 -1 -1 -1 -1 26 507 22 6.89349e+06 70469.2 503264. 1741.40 0.60 0.0255841 0.0213855 24322 120374 -1 438 15 281 281 16169 5271 1.14287 1.14287 -32.7732 -1.14287 0 0 618332. 2139.56 0.03 0.01 0.07 -1 -1 0.03 0.00442084 0.00391521 24 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 1.99 vpr 64.18 MiB -1 -1 0.11 17292 1 0.02 -1 -1 30488 -1 -1 5 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65716 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 25.2 MiB 0.03 697 206 1918 387 1516 15 64.2 MiB 0.01 0.00 1.31566 1.2594 -32.1458 -1.2594 1.2594 0.24 0.000103974 9.3764e-05 0.00313121 0.00283186 -1 -1 -1 -1 28 544 24 6.89349e+06 70469.2 531479. 1839.03 0.64 0.0307663 0.0257498 24610 126494 -1 448 15 267 267 13804 4654 1.15867 1.15867 -35.9015 -1.15867 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00479109 0.00417829 26 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 1.94 vpr 63.93 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29900 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65460 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 25.6 MiB 0.04 813 321 1850 346 1493 11 63.9 MiB 0.01 0.00 1.32666 1.2704 -36.4307 -1.2704 1.2704 0.24 0.000110104 9.961e-05 0.00295105 0.00267871 -1 -1 -1 -1 30 565 14 6.89349e+06 70469.2 556674. 1926.21 0.60 0.0313754 0.0264468 25186 138497 -1 530 12 247 247 12350 3589 1.01137 1.01137 -36.0238 -1.01137 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00411258 0.0036678 28 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 1.93 vpr 63.96 MiB -1 -1 0.10 17288 1 0.02 -1 -1 30552 -1 -1 7 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65492 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 25.2 MiB 0.04 813 384 2495 473 1933 89 64.0 MiB 0.01 0.00 1.2814 1.2814 -40.976 -1.2814 1.2814 0.24 0.000117993 0.000106213 0.00363177 0.00329301 -1 -1 -1 -1 26 810 14 6.89349e+06 98656.9 503264. 1741.40 0.57 0.0258483 0.021987 24322 120374 -1 746 17 370 370 30180 8245 1.06832 1.06832 -43.5975 -1.06832 0 0 618332. 2139.56 0.02 0.01 0.07 -1 -1 0.02 0.00519978 0.00457024 31 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 2.20 vpr 64.34 MiB -1 -1 0.10 17292 1 0.02 -1 -1 30588 -1 -1 6 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 25.6 MiB 0.05 982 503 3518 892 2197 429 64.3 MiB 0.02 0.00 2.02863 1.65273 -45.7068 -1.65273 1.65273 0.24 0.000135696 0.000123138 0.00665055 0.00611328 -1 -1 -1 -1 32 883 18 6.89349e+06 84563 586450. 2029.24 0.78 0.0483766 0.0414011 25474 144626 -1 792 14 329 329 23739 6157 1.22267 1.22267 -49.194 -1.22267 0 0 744469. 2576.02 0.03 0.02 0.09 -1 -1 0.03 0.00577121 0.00508213 32 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 1.99 vpr 64.39 MiB -1 -1 0.11 17292 1 0.02 -1 -1 30024 -1 -1 6 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 25.6 MiB 0.05 1128 419 4229 1016 3090 123 64.4 MiB 0.02 0.00 2.29023 1.66373 -48.1052 -1.66373 1.66373 0.24 0.000164621 0.000150187 0.00610199 0.00553404 -1 -1 -1 -1 28 877 22 6.89349e+06 84563 531479. 1839.03 0.58 0.0431659 0.0366672 24610 126494 -1 727 15 348 348 22785 6153 0.98502 0.98502 -45.8259 -0.98502 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00531759 0.00470243 35 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 1.75 vpr 64.40 MiB -1 -1 0.11 17292 1 0.03 -1 -1 30588 -1 -1 7 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 25.6 MiB 0.05 990 527 3813 762 2889 162 64.4 MiB 0.02 0.00 1.74199 1.68573 -55.4954 -1.68573 1.68573 0.24 0.000178041 0.000161664 0.00707604 0.00648495 -1 -1 -1 -1 30 934 16 6.89349e+06 98656.9 556674. 1926.21 0.30 0.0327715 0.0284548 25186 138497 -1 844 17 347 347 24553 5924 0.98502 0.98502 -52.8184 -0.98502 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00792233 0.00685172 38 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 2.00 vpr 64.10 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29992 -1 -1 8 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65640 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 25.2 MiB 0.05 1415 379 3958 843 3047 68 64.1 MiB 0.02 0.00 1.7778 1.70773 -57.6396 -1.70773 1.70773 0.24 0.000164211 0.000149579 0.00520346 0.00475169 -1 -1 -1 -1 30 883 21 6.89349e+06 112751 556674. 1926.21 0.59 0.0441693 0.037646 25186 138497 -1 707 16 445 445 24688 7831 1.13037 1.13037 -55.7432 -1.13037 0 0 706193. 2443.58 0.03 0.02 0.08 -1 -1 0.03 0.00739954 0.00651301 42 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 2.21 vpr 64.19 MiB -1 -1 0.12 17148 1 0.02 -1 -1 30296 -1 -1 10 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 25.2 MiB 0.06 1570 705 9540 2422 6707 411 64.2 MiB 0.03 0.00 1.94928 1.72973 -71.7939 -1.72973 1.72973 0.25 0.000186686 0.000170542 0.0120996 0.011037 -1 -1 -1 -1 32 1241 15 6.89349e+06 140938 586450. 2029.24 0.79 0.0763367 0.0663004 25474 144626 -1 1115 15 480 480 36716 8990 1.28867 1.28867 -71.8206 -1.28867 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.0067221 0.00597853 47 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 1.84 vpr 64.27 MiB -1 -1 0.13 18060 1 0.02 -1 -1 30428 -1 -1 9 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65812 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 25.0 MiB 0.05 1728 728 7103 1612 5339 152 64.3 MiB 0.03 0.00 2.48562 2.11206 -79.3567 -2.11206 2.11206 0.24 0.000195811 0.000179353 0.0083201 0.0075881 -1 -1 -1 -1 32 1358 40 6.89349e+06 126845 586450. 2029.24 0.39 0.0473056 0.0409139 25474 144626 -1 1164 15 521 521 41703 10584 1.18337 1.18337 -72.8866 -1.18337 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00721607 0.00641475 51 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 1.77 vpr 64.53 MiB -1 -1 0.12 17532 1 0.03 -1 -1 30508 -1 -1 11 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 25.4 MiB 0.06 1802 814 11641 2975 7882 784 64.5 MiB 0.04 0.00 2.40666 2.15606 -91.4368 -2.15606 2.15606 0.24 0.000220052 0.000200768 0.0124409 0.0113433 -1 -1 -1 -1 32 1545 15 6.89349e+06 155032 586450. 2029.24 0.29 0.0377863 0.0333776 25474 144626 -1 1324 19 534 534 42118 11208 1.26037 1.26037 -85.4089 -1.26037 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00944336 0.00835962 58 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 2.47 vpr 64.65 MiB -1 -1 0.14 17676 1 0.03 -1 -1 30504 -1 -1 12 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 25.6 MiB 0.06 1930 880 15627 3739 10944 944 64.7 MiB 0.08 0.00 2.56039 2.56039 -107.805 -2.56039 2.56039 0.24 0.000368579 0.000338259 0.0265098 0.0245221 -1 -1 -1 -1 32 1748 15 6.89349e+06 169126 586450. 2029.24 0.94 0.0917662 0.0811116 25474 144626 -1 1533 14 690 690 51852 13576 1.31337 1.31337 -98.3301 -1.31337 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00873069 0.00781067 67 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 2.00 vpr 64.76 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30692 -1 -1 18 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 24.9 MiB 0.07 3166 1546 32420 11579 18441 2400 64.8 MiB 0.11 0.00 3.83296 3.45705 -190.966 -3.45705 3.45705 0.24 0.000935119 0.000875924 0.0327955 0.0302908 -1 -1 -1 -1 32 2917 31 6.89349e+06 253689 586450. 2029.24 0.41 0.0903366 0.0815299 25474 144626 -1 2433 16 997 997 83200 20511 1.65467 1.65467 -160.881 -1.65467 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.013649 0.012318 99 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 2.35 vpr 65.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30136 -1 -1 24 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67316 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 26.4 MiB 0.07 4215 1897 53273 20437 29644 3192 65.7 MiB 0.17 0.00 4.72962 4.35372 -277.996 -4.35372 4.35372 0.24 0.000538663 0.000498151 0.0466986 0.0432372 -1 -1 -1 -1 32 3892 20 6.89349e+06 338252 586450. 2029.24 0.66 0.134776 0.122282 25474 144626 -1 3201 21 1413 1413 124031 31705 1.75832 1.75832 -211.545 -1.75832 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0230991 0.0209535 131 2 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt index 8d0853d10c4..68bca7c32e2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt @@ -1,1025 +1,1025 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 3.42 vpr 62.79 MiB -1 -1 0.38 18688 14 0.25 -1 -1 32944 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64300 32 32 277 309 1 202 103 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1547 9502 2152 6495 855 62.8 MiB 0.09 0.00 8.07544 -169.743 -8.07544 8.07544 0.32 0.000899886 0.000831959 0.0389219 0.0360116 -1 -1 -1 -1 28 3643 25 6.55708e+06 470145 500653. 1732.36 0.98 0.157731 0.138292 21310 115450 -1 3135 20 1428 5029 257339 61759 6.9613 6.9613 -157.642 -6.9613 0 0 612192. 2118.31 0.03 0.10 0.10 -1 -1 0.03 0.0374491 0.0327568 193 183 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 3.20 vpr 63.32 MiB -1 -1 0.41 18644 14 0.27 -1 -1 32760 -1 -1 39 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 30 32 272 304 1 193 101 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1322 7151 1527 4686 938 63.3 MiB 0.08 0.00 8.01406 -160.585 -8.01406 8.01406 0.31 0.000946647 0.000878015 0.0319553 0.0296902 -1 -1 -1 -1 28 3435 28 6.55708e+06 470145 500653. 1732.36 0.76 0.156061 0.136801 21310 115450 -1 2820 19 1177 3615 175609 44433 6.94704 6.94704 -150.651 -6.94704 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0360537 0.0316786 194 184 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 3.34 vpr 62.70 MiB -1 -1 0.34 18168 11 0.24 -1 -1 32492 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64200 32 32 280 312 1 190 104 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1349 9132 2022 6010 1100 62.7 MiB 0.09 0.00 6.82588 -135.752 -6.82588 6.82588 0.32 0.000906573 0.000836187 0.037231 0.0344479 -1 -1 -1 -1 26 3939 32 6.55708e+06 482200 477104. 1650.88 0.95 0.168247 0.147065 21022 109990 -1 3066 20 1319 4861 248158 60039 6.13352 6.13352 -135.053 -6.13352 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0380961 0.0333989 194 186 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_004.v common 3.31 vpr 63.41 MiB -1 -1 0.36 18248 12 0.31 -1 -1 32832 -1 -1 41 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64932 29 32 275 307 1 193 102 17 17 289 -1 unnamed_device 23.8 MiB 0.09 1321 8432 1770 5951 711 63.4 MiB 0.08 0.00 7.97532 -148.743 -7.97532 7.97532 0.32 0.000904317 0.000838587 0.0356923 0.0329942 -1 -1 -1 -1 22 3603 44 6.55708e+06 494255 420624. 1455.45 0.94 0.186163 0.162104 20158 92377 -1 3227 16 1177 3853 213521 52797 7.1599 7.1599 -148.544 -7.1599 0 0 500653. 1732.36 0.02 0.08 0.08 -1 -1 0.02 0.0323126 0.0284639 200 190 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_005.v common 3.37 vpr 62.98 MiB -1 -1 0.38 18384 13 0.27 -1 -1 32848 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64488 32 32 302 334 1 214 106 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1672 9856 2131 7054 671 63.0 MiB 0.11 0.00 8.06277 -168.566 -8.06277 8.06277 0.32 0.00100468 0.000929012 0.0474751 0.0438051 -1 -1 -1 -1 32 3848 27 6.55708e+06 506310 554710. 1919.41 0.76 0.185353 0.162891 22174 131602 -1 3263 16 1310 4212 205623 50945 7.27044 7.27044 -162.359 -7.27044 0 0 701300. 2426.64 0.04 0.09 0.11 -1 -1 0.04 0.0385923 0.0343556 217 208 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 3.24 vpr 62.84 MiB -1 -1 0.39 18616 13 0.24 -1 -1 32908 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 32 32 292 324 1 214 105 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1522 10479 2742 6826 911 62.8 MiB 0.11 0.00 8.0037 -160.293 -8.0037 8.0037 0.32 0.000938065 0.000869644 0.0437923 0.0405003 -1 -1 -1 -1 30 3477 18 6.55708e+06 494255 526063. 1820.29 0.74 0.158732 0.139622 21886 126133 -1 2963 16 1237 4638 205817 50427 6.61036 6.61036 -146.138 -6.61036 0 0 666494. 2306.21 0.03 0.09 0.12 -1 -1 0.03 0.0341773 0.0301008 207 198 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 2.76 vpr 62.60 MiB -1 -1 0.28 17976 12 0.19 -1 -1 32644 -1 -1 38 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 27 32 229 261 1 167 97 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1076 6757 1422 4783 552 62.6 MiB 0.06 0.00 7.57737 -131.413 -7.57737 7.57737 0.35 0.000740353 0.000687695 0.0254221 0.0235468 -1 -1 -1 -1 30 2249 15 6.55708e+06 458090 526063. 1820.29 0.51 0.107135 0.0937171 21886 126133 -1 1995 16 754 2397 101760 26051 6.58844 6.58844 -121.637 -6.58844 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0301412 0.0274345 162 150 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 3.27 vpr 62.58 MiB -1 -1 0.30 18408 12 0.19 -1 -1 32680 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64080 31 32 229 261 1 172 96 17 17 289 -1 unnamed_device 23.3 MiB 0.11 1185 7761 1749 4997 1015 62.6 MiB 0.07 0.00 6.59345 -131.227 -6.59345 6.59345 0.32 0.000740267 0.000683218 0.0287775 0.0266122 -1 -1 -1 -1 26 3514 29 6.55708e+06 397815 477104. 1650.88 0.94 0.134112 0.117297 21022 109990 -1 2674 30 1375 5142 317498 101013 5.83766 5.83766 -127.871 -5.83766 0 0 585099. 2024.56 0.03 0.13 0.09 -1 -1 0.03 0.0413928 0.0359352 148 138 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 3.39 vpr 62.46 MiB -1 -1 0.35 18288 12 0.17 -1 -1 32580 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 31 32 235 267 1 170 98 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1150 5948 1022 4676 250 62.5 MiB 0.06 0.00 6.96335 -140.158 -6.96335 6.96335 0.31 0.000753943 0.000699553 0.0226974 0.0210228 -1 -1 -1 -1 26 3167 48 6.55708e+06 421925 477104. 1650.88 1.10 0.149191 0.129498 21022 109990 -1 2456 16 1013 3172 157031 38959 6.14378 6.14378 -136.577 -6.14378 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0266218 0.0234099 156 144 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_010.v common 3.30 vpr 62.71 MiB -1 -1 0.34 18364 13 0.18 -1 -1 32684 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64212 32 32 250 282 1 185 101 17 17 289 -1 unnamed_device 23.5 MiB 0.13 1310 8561 1766 6158 637 62.7 MiB 0.08 0.00 7.32681 -164.785 -7.32681 7.32681 0.32 0.000806421 0.000748231 0.032678 0.0302492 -1 -1 -1 -1 22 3707 41 6.55708e+06 446035 420624. 1455.45 0.96 0.159714 0.139055 20158 92377 -1 3144 22 1536 4703 302925 83797 7.11044 7.11044 -169.479 -7.11044 0 0 500653. 1732.36 0.02 0.12 0.08 -1 -1 0.02 0.0377263 0.0330363 169 156 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 3.04 vpr 62.66 MiB -1 -1 0.32 18360 12 0.18 -1 -1 32500 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64904 32 32 288 320 1 207 102 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1453 7242 1384 5338 520 63.4 MiB 0.08 0.00 7.59394 -155.783 -7.59394 7.59394 0.29 0.000912161 0.000844874 0.0323359 0.0298935 -1 -1 -1 -1 26 3629 20 6.55708e+06 458090 477104. 1650.88 0.92 0.149908 0.131327 21022 109990 -1 3193 16 1125 4133 211646 50831 6.78904 6.78904 -148.172 -6.78904 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0325848 0.0286863 203 194 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_112.v common 3.18 vpr 63.54 MiB -1 -1 0.41 18664 13 0.28 -1 -1 32844 -1 -1 44 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 31 32 282 314 1 195 107 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1373 8203 1549 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 25 32 183 215 1 133 89 17 17 289 -1 unnamed_device 22.9 MiB 0.07 884 9791 2362 5778 1651 62.6 MiB 0.07 0.00 5.75805 -100.808 -5.75805 5.75805 0.32 0.000611445 0.000567323 0.0322947 0.0299355 -1 -1 -1 -1 24 2013 19 6.55708e+06 385760 448715. 1552.65 0.49 0.102962 0.090186 20734 103517 -1 1761 18 600 1915 90275 23115 5.08326 5.08326 -98.1946 -5.08326 0 0 554710. 1919.41 0.02 0.03 0.06 -1 -1 0.02 0.0141287 0.0126477 118 110 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_127.v common 3.59 vpr 63.02 MiB -1 -1 0.31 18608 12 0.28 -1 -1 32768 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64528 32 32 300 332 1 216 104 17 17 289 -1 unnamed_device 23.9 MiB 0.13 1605 6936 1239 5241 456 63.0 MiB 0.08 0.00 7.69496 -166.719 -7.69496 7.69496 0.31 0.000958724 0.000888992 0.0307105 0.0284931 -1 -1 -1 -1 26 4186 35 6.55708e+06 482200 477104. 1650.88 1.04 0.170469 0.148547 21022 109990 -1 3459 25 1445 4477 264666 74433 6.75244 6.75244 -160.935 -6.75244 0 0 585099. 2024.56 0.03 0.12 0.09 -1 -1 0.03 0.0470212 0.0410556 213 206 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_128.v common 4.23 vpr 63.35 MiB -1 -1 0.43 18768 13 0.33 -1 -1 32756 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 31 32 290 322 1 209 102 17 17 289 -1 unnamed_device 23.6 MiB 0.13 1489 11050 2752 7035 1263 63.3 MiB 0.11 0.00 8.23989 -170.094 -8.23989 8.23989 0.32 0.000950408 0.000879111 0.0481654 0.0445422 -1 -1 -1 -1 26 4169 46 6.55708e+06 470145 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 299 247 1 188 95 17 17 289 -1 unnamed_device 23.6 MiB 0.21 995 8519 1888 6283 348 62.8 MiB 0.09 0.00 4.69952 -119.793 -4.69952 4.69952 0.32 0.000629047 0.000585652 0.0270416 0.0251595 -1 -1 -1 -1 26 2703 22 6.64007e+06 389298 477104. 1650.88 0.59 0.103803 0.0908653 21682 110474 -1 2071 19 1134 1713 100741 25334 3.82002 3.82002 -121.448 -3.82002 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0245892 0.021454 129 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.64 vpr 62.60 MiB -1 -1 0.24 18320 1 0.03 -1 -1 30340 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 23.5 MiB 0.07 1008 16445 5394 8747 2304 62.6 MiB 0.16 0.00 4.53207 -121.894 -4.53207 4.53207 0.31 0.000634108 0.000588823 0.0522809 0.04853 -1 -1 -1 -1 32 2067 22 6.64007e+06 389298 554710. 1919.41 0.54 0.127898 0.113171 22834 132086 -1 1877 23 1086 2225 141232 33078 3.54423 3.54423 -113.215 -3.54423 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0281235 0.0244222 132 31 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.70 vpr 62.80 MiB -1 -1 0.23 18252 1 0.03 -1 -1 30416 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1067 12098 3452 7701 945 62.8 MiB 0.13 0.00 4.58601 -133.697 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23651 3.05137 3.05137 -112.229 -3.05137 0 0 701300. 2426.64 0.03 0.06 0.10 -1 -1 0.03 0.0301609 0.0264063 145 58 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.43 vpr 63.12 MiB -1 -1 0.23 18080 1 0.03 -1 -1 30572 -1 -1 21 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64636 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 23.5 MiB 0.08 751 11948 4103 6020 1825 63.1 MiB 0.10 0.00 3.76738 -102.601 -3.76738 3.76738 0.32 0.000553592 0.000515184 0.0404029 0.0376175 -1 -1 -1 -1 28 1527 20 6.64007e+06 263718 500653. 1732.36 0.48 0.10499 0.0926546 21970 115934 -1 1471 20 917 1568 101266 24667 2.74477 2.74477 -95.077 -2.74477 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0224191 0.0194903 97 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 31 32 317 271 1 168 87 17 17 289 -1 unnamed_device 23.5 MiB 0.16 906 5655 1194 4208 253 62.7 MiB 0.07 0.00 3.60222 -117.559 -3.60222 3.60222 0.32 0.000639636 0.000594878 0.0209485 0.0195041 -1 -1 -1 -1 28 2705 33 6.64007e+06 301392 500653. 1732.36 0.81 0.108644 0.0943614 21970 115934 -1 2030 20 1272 1882 135466 32452 3.48643 3.48643 -121.992 -3.48643 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0250351 0.0217808 117 64 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.55 vpr 62.54 MiB -1 -1 0.23 18256 1 0.03 -1 -1 30068 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64036 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 23.5 MiB 0.13 936 12323 3600 6804 1919 62.5 MiB 0.12 0.00 3.85841 -126.873 -3.85841 3.85841 0.32 0.000619093 0.000576413 0.0446968 0.0416188 -1 -1 -1 -1 32 1786 19 6.64007e+06 238602 554710. 1919.41 0.52 0.11678 0.103252 22834 132086 -1 1612 19 841 1348 82679 19678 2.65457 2.65457 -110.251 -2.65457 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0229212 0.0201044 115 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.54 vpr 62.74 MiB -1 -1 0.25 18388 1 0.03 -1 -1 30384 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.6 MiB 0.12 895 11106 3427 6381 1298 62.7 MiB 0.11 0.00 3.83641 -113.668 -3.83641 3.83641 0.32 0.00061658 0.000573067 0.0411971 0.0383264 -1 -1 -1 -1 32 1647 21 6.64007e+06 238602 554710. 1919.41 0.50 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fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 2.65 vpr 62.78 MiB -1 -1 0.13 18376 1 0.03 -1 -1 30344 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64284 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 23.8 MiB 0.21 1145 10803 2724 7364 715 62.8 MiB 0.12 0.00 4.40284 -140.386 -4.40284 4.40284 0.32 0.000709355 0.000659531 0.0383752 0.035603 -1 -1 -1 -1 30 2401 22 6.64007e+06 364182 526063. 1820.29 0.58 0.122776 0.107981 22546 126617 -1 2127 21 1359 2094 110426 27165 3.25703 3.25703 -124.202 -3.25703 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0291253 0.0254331 147 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.80 vpr 63.43 MiB -1 -1 0.16 18368 1 0.03 -1 -1 30268 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.13 989 17873 5923 8850 3100 63.4 MiB 0.17 0.00 4.77444 -137.586 -4.77444 4.77444 0.32 0.000712912 0.000662078 0.0594743 0.0552107 -1 -1 -1 -1 28 2617 24 6.64007e+06 426972 500653. 1732.36 0.75 0.150152 0.13295 21970 115934 -1 2048 20 1394 2351 145782 36264 4.26142 4.26142 -132.668 -4.26142 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.028755 0.0251025 139 61 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.41 vpr 62.78 MiB -1 -1 0.22 18068 1 0.03 -1 -1 30400 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64288 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 23.2 MiB 0.08 694 9234 2301 6256 677 62.8 MiB 0.08 0.00 3.09179 -89.0655 -3.09179 3.09179 0.32 0.000541072 0.000503614 0.0294454 0.0273744 -1 -1 -1 -1 28 1661 20 6.64007e+06 288834 500653. 1732.36 0.48 0.0926557 0.0812293 21970 115934 -1 1471 17 793 1316 76428 19287 2.75777 2.75777 -91.0915 -2.75777 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0192396 0.0167673 103 27 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 2.66 vpr 62.93 MiB -1 -1 0.26 18448 1 0.03 -1 -1 30352 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64440 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 23.9 MiB 0.13 1107 16003 5012 8992 1999 62.9 MiB 0.17 0.00 4.0781 -126.952 -4.0781 4.0781 0.32 0.000726709 0.000675037 0.05991 0.0556514 -1 -1 -1 -1 32 2297 19 6.64007e+06 339066 554710. 1919.41 0.57 0.144057 0.127765 22834 132086 -1 2105 20 1422 2537 151704 36359 3.12737 3.12737 -118.814 -3.12737 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0289797 0.0252666 138 58 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 2.89 vpr 62.89 MiB -1 -1 0.26 18396 1 0.03 -1 -1 30152 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64400 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 23.8 MiB 0.23 1061 17066 4730 9821 2515 62.9 MiB 0.17 0.00 4.48406 -140.639 -4.48406 4.48406 0.32 0.000693042 0.000644226 0.059948 0.0557361 -1 -1 -1 -1 32 2314 40 6.64007e+06 351624 554710. 1919.41 0.63 0.161734 0.142937 22834 132086 -1 1983 22 1194 1762 113331 28176 3.19063 3.19063 -122.439 -3.19063 0 0 701300. 2426.64 0.03 0.07 0.11 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 23.6 MiB 0.06 532 9543 2250 6629 664 62.8 MiB 0.07 0.00 2.4343 -77.8363 -2.4343 2.4343 0.31 0.000498159 0.00046299 0.0295526 0.0274642 -1 -1 -1 -1 28 1401 21 6.64007e+06 213486 500653. 1732.36 0.51 0.087921 0.0771578 21970 115934 -1 1137 19 688 980 63827 17614 1.86811 1.86811 -77.6028 -1.86811 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0187935 0.0163088 85 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 2.70 vpr 62.58 MiB -1 -1 0.24 18244 1 0.03 -1 -1 30440 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 31 32 291 243 1 171 88 17 17 289 -1 unnamed_device 23.5 MiB 0.24 847 10423 2562 6326 1535 62.6 MiB 0.10 0.00 5.02597 -142.893 -5.02597 5.02597 0.32 0.000610921 0.000568644 0.0349955 0.0325792 -1 -1 -1 -1 30 1856 17 6.64007e+06 313950 526063. 1820.29 0.53 0.103641 0.09137 22546 126617 -1 1527 13 585 825 49033 12151 3.62042 3.62042 -128.198 -3.62042 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.0183956 0.0162745 127 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 2.66 vpr 62.75 MiB -1 -1 0.24 18256 1 0.03 -1 -1 30520 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 23.8 MiB 0.07 1134 18196 5105 11197 1894 62.7 MiB 0.17 0.00 4.17176 -133.816 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28953 3.90649 3.90649 -129.764 -3.90649 0 0 701300. 2426.64 0.03 0.06 0.09 -1 -1 0.03 0.0257533 0.0225868 151 62 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.44 vpr 62.62 MiB -1 -1 0.21 18080 1 0.03 -1 -1 30528 -1 -1 20 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 23.2 MiB 0.09 426 10536 3993 4440 2103 62.6 MiB 0.07 0.00 2.50053 -67.6186 -2.50053 2.50053 0.32 0.000436929 0.000400303 0.0290515 0.0268679 -1 -1 -1 -1 32 1026 22 6.64007e+06 251160 554710. 1919.41 0.51 0.0817182 0.0716779 22834 132086 -1 874 18 548 811 45228 13433 1.97731 1.97731 -65.3841 -1.97731 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0152356 0.0132622 81 30 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.53 vpr 62.68 MiB -1 -1 0.22 17864 1 0.03 -1 -1 30276 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 23.6 MiB 0.07 962 6821 1380 5168 273 62.7 MiB 0.08 0.00 4.45587 -122.025 -4.45587 4.45587 0.32 0.000632837 0.000579639 0.0236586 0.0219696 -1 -1 -1 -1 32 2155 19 6.64007e+06 313950 554710. 1919.41 0.55 0.0955033 0.0835082 22834 132086 -1 1903 22 1221 2303 145599 33656 3.56023 3.56023 -116.407 -3.56023 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0269469 0.0234776 125 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.40 vpr 62.68 MiB -1 -1 0.20 17616 1 0.02 -1 -1 30032 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 23.4 MiB 0.05 506 11281 3424 5287 2570 62.7 MiB 0.07 0.00 2.72793 -76.1863 -2.72793 2.72793 0.31 0.000420089 0.000389775 0.0287434 0.0267156 -1 -1 -1 -1 26 1285 37 6.64007e+06 213486 477104. 1650.88 0.54 0.0765327 0.06757 21682 110474 -1 1002 13 438 511 40350 12151 2.30171 2.30171 -75.5155 -2.30171 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0124532 0.0109542 82 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.69 vpr 62.73 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30024 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 23.6 MiB 0.07 883 10031 2317 7175 539 62.7 MiB 0.10 0.00 4.605 -123.934 -4.605 4.605 0.32 0.000638244 0.000593242 0.0318232 0.0295403 -1 -1 -1 -1 26 2558 30 6.64007e+06 389298 477104. 1650.88 0.70 0.116775 0.102232 21682 110474 -1 1879 19 1105 1890 131855 36211 3.61243 3.61243 -115.665 -3.61243 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.024099 0.0210298 126 24 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.58 vpr 62.74 MiB -1 -1 0.23 17940 1 0.03 -1 -1 30444 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64244 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 23.5 MiB 0.06 983 19624 5667 10714 3243 62.7 MiB 0.17 0.00 3.74367 -107.154 -3.74367 3.74367 0.31 0.000643124 0.000596512 0.0541517 0.0501652 -1 -1 -1 -1 30 2029 21 6.64007e+06 489762 526063. 1820.29 0.55 0.129395 0.114647 22546 126617 -1 1826 21 1025 1901 115566 26955 2.81677 2.81677 -97.3789 -2.81677 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0265257 0.0230983 136 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.66 vpr 62.79 MiB -1 -1 0.24 18376 1 0.03 -1 -1 30248 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 32 32 338 277 1 179 99 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1102 15147 4066 9723 1358 62.8 MiB 0.15 0.00 4.9076 -137.928 -4.9076 4.9076 0.32 0.000693713 0.000642192 0.0478832 0.0443651 -1 -1 -1 -1 30 2217 21 6.64007e+06 439530 526063. 1820.29 0.53 0.127985 0.112974 22546 126617 -1 1976 19 975 1710 85252 20817 3.73962 3.73962 -125.26 -3.73962 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0265032 0.0231786 133 50 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.44 vpr 63.14 MiB -1 -1 0.22 18024 1 0.03 -1 -1 30044 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 23.3 MiB 0.07 891 9943 2356 6701 886 63.1 MiB 0.10 0.00 3.06979 -104.718 -3.06979 3.06979 0.31 0.000603833 0.000560397 0.0349301 0.0324289 -1 -1 -1 -1 32 1751 17 6.64007e+06 263718 554710. 1919.41 0.49 0.1021 0.0898442 22834 132086 -1 1528 20 825 1366 74902 18215 2.59557 2.59557 -98.7069 -2.59557 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0250366 0.0217718 107 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.20 vpr 62.54 MiB -1 -1 0.22 18104 1 0.03 -1 -1 30208 -1 -1 28 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64044 30 32 262 227 1 135 90 17 17 289 -1 unnamed_device 23.2 MiB 0.04 680 8733 1889 6137 707 62.5 MiB 0.08 0.00 3.24119 -95.6654 -3.24119 3.24119 0.24 0.000566872 0.000527984 0.0264591 0.0246154 -1 -1 -1 -1 32 1467 24 6.64007e+06 351624 554710. 1919.41 0.50 0.0951258 0.0831051 22834 132086 -1 1268 15 541 823 48367 12287 2.78097 2.78097 -89.3799 -2.78097 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0180998 0.0158592 100 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 2.42 vpr 62.76 MiB -1 -1 0.23 18080 1 0.03 -1 -1 30176 -1 -1 27 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64264 28 32 260 223 1 140 87 17 17 289 -1 unnamed_device 23.4 MiB 0.07 639 10263 2494 7193 576 62.8 MiB 0.09 0.00 3.42827 -93.8875 -3.42827 3.42827 0.32 0.00043274 0.000391438 0.0289215 0.0266058 -1 -1 -1 -1 32 1562 21 6.64007e+06 339066 554710. 1919.41 0.47 0.0861484 0.0753885 22834 132086 -1 1318 18 753 1299 69501 18303 2.71057 2.71057 -90.431 -2.71057 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0204961 0.0178339 104 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 2.53 vpr 62.58 MiB -1 -1 0.20 17912 1 0.03 -1 -1 30252 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 23.2 MiB 0.07 756 14035 4673 6434 2928 62.6 MiB 0.13 0.00 3.79135 -111.266 -3.79135 3.79135 0.32 0.000574842 0.000528617 0.0450144 0.0417314 -1 -1 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1231 12606 3242 8430 934 63.5 MiB 0.13 0.00 4.47716 -125.986 -4.47716 4.47716 0.34 0.000742465 0.000690503 0.040033 0.0371622 -1 -1 -1 -1 30 2392 22 6.64007e+06 527436 526063. 1820.29 0.57 0.121338 0.107295 22546 126617 -1 2206 21 1094 2094 127085 27888 3.60143 3.60143 -119.17 -3.60143 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0305183 0.026678 158 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.79 vpr 63.49 MiB -1 -1 0.25 18340 1 0.04 -1 -1 30180 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65012 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1118 12208 2919 8273 1016 63.5 MiB 0.17 0.00 3.91238 -131.369 -3.91238 3.91238 0.32 0.000761885 0.000699352 0.055694 0.0515452 -1 -1 -1 -1 28 2461 21 6.64007e+06 514878 500653. 1732.36 0.57 0.144934 0.12814 21970 115934 -1 2208 19 1586 2620 148161 36739 2.95517 2.95517 -121.08 -2.95517 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0289413 0.0253146 150 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.72 vpr 62.75 MiB -1 -1 0.22 18372 1 0.03 -1 -1 30040 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 23.6 MiB 0.18 947 12938 4038 6585 2315 62.7 MiB 0.13 0.00 4.39563 -129.442 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common 2.98 vpr 62.88 MiB -1 -1 0.25 18228 1 0.03 -1 -1 30372 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 23.8 MiB 0.31 1234 12191 3319 7524 1348 62.9 MiB 0.14 0.00 5.10379 -154.62 -5.10379 5.10379 0.32 0.000745353 0.000692519 0.0442067 0.0410231 -1 -1 -1 -1 30 2528 23 6.64007e+06 401856 526063. 1820.29 0.56 0.134313 0.118402 22546 126617 -1 2128 20 1112 1738 94826 23161 4.27288 4.27288 -144.151 -4.27288 0 0 666494. 2306.21 0.04 0.08 0.11 -1 -1 0.04 0.0377662 0.0337785 167 64 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.73 vpr 62.80 MiB -1 -1 0.26 18420 1 0.03 -1 -1 30316 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1115 12860 3466 8442 952 62.8 MiB 0.13 0.00 4.70003 -136.748 -4.70003 4.70003 0.32 0.000715122 0.000665654 0.0417528 0.038773 -1 -1 -1 -1 26 2605 23 6.64007e+06 464646 477104. 1650.88 0.58 0.127608 0.112186 21682 110474 -1 2250 19 1232 2113 125509 30102 3.32883 3.32883 -120.962 -3.32883 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0270422 0.0236199 140 55 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.71 vpr 62.82 MiB -1 -1 0.24 18288 1 0.03 -1 -1 30260 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64332 32 32 291 242 1 179 93 17 17 289 -1 unnamed_device 23.7 MiB 0.17 1061 8073 1866 5827 380 62.8 MiB 0.09 0.00 4.40233 -117.896 -4.40233 4.40233 0.32 0.000615341 0.000573051 0.0259548 0.0241356 -1 -1 -1 -1 26 2518 23 6.64007e+06 364182 477104. 1650.88 0.66 0.102146 0.0893417 21682 110474 -1 2137 18 962 1522 106494 23971 3.50942 3.50942 -116.943 -3.50942 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0231839 0.0203345 125 27 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 3.03 vpr 63.46 MiB -1 -1 0.27 18732 1 0.03 -1 -1 30432 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 24.6 MiB 0.16 1312 16552 4366 10580 1606 63.5 MiB 0.18 0.00 5.1085 -163.706 -5.1085 5.1085 0.32 0.000866276 0.000805627 0.0599784 0.0556569 -1 -1 -1 -1 26 3108 25 6.64007e+06 539994 477104. 1650.88 0.74 0.169209 0.149122 21682 110474 -1 2610 21 1586 2418 149034 35187 4.18489 4.18489 -152.922 -4.18489 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0364613 0.0317981 176 87 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.51 vpr 62.67 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30204 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64176 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 23.4 MiB 0.08 705 8213 2081 5243 889 62.7 MiB 0.08 0.00 3.75024 -98.8591 -3.75024 3.75024 0.32 0.0005679 0.000526595 0.0263248 0.0244408 -1 -1 -1 -1 32 1549 22 6.64007e+06 288834 554710. 1919.41 0.53 0.100546 0.0878178 22834 132086 -1 1406 19 899 1604 92734 23078 2.74057 2.74057 -95.4429 -2.74057 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0216482 0.0188058 104 28 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 2.78 vpr 62.98 MiB -1 -1 0.25 18292 1 0.03 -1 -1 30248 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 24.0 MiB 0.22 1232 11863 3185 7621 1057 63.0 MiB 0.13 0.00 5.0773 -152.378 -5.0773 5.0773 0.32 0.000685702 0.000638075 0.0388617 0.0361442 -1 -1 -1 -1 30 2607 19 6.64007e+06 426972 526063. 1820.29 0.54 0.117632 0.103629 22546 126617 -1 2248 21 1248 1852 100468 23985 3.96729 3.96729 -135.475 -3.96729 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0289625 0.0253341 149 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.99 vpr 62.95 MiB -1 -1 0.17 18472 1 0.03 -1 -1 30352 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64456 32 32 349 284 1 183 102 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1221 11764 2967 7709 1088 62.9 MiB 0.12 0.00 3.95307 -117.525 -3.95307 3.95307 0.32 0.000696024 0.000644408 0.0366916 0.0340243 -1 -1 -1 -1 22 3240 30 6.64007e+06 477204 420624. 1455.45 0.98 0.131608 0.11527 20818 92861 -1 2548 19 1326 2488 176484 42475 3.19957 3.19957 -118.379 -3.19957 0 0 500653. 1732.36 0.02 0.07 0.08 -1 -1 0.02 0.0262585 0.0229142 137 53 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 2.58 vpr 62.59 MiB -1 -1 0.23 17800 1 0.03 -1 -1 30212 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64096 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 23.5 MiB 0.07 900 13147 4476 6141 2530 62.6 MiB 0.13 0.00 4.20356 -122.292 -4.20356 4.20356 0.31 0.000620913 0.00057678 0.0422596 0.0392478 -1 -1 -1 -1 32 2124 24 6.64007e+06 339066 554710. 1919.41 0.57 0.118883 0.104795 22834 132086 -1 1774 20 1016 2010 121136 29266 3.34003 3.34003 -110.91 -3.34003 0 0 701300. 2426.64 0.03 0.06 0.12 -1 -1 0.03 0.0252076 0.0219955 127 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.84 vpr 63.38 MiB -1 -1 0.23 18376 1 0.03 -1 -1 30420 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64904 32 32 353 287 1 198 94 17 17 289 -1 unnamed_device 23.8 MiB 0.24 1217 9679 2220 6521 938 63.4 MiB 0.12 0.00 4.87535 -142.566 -4.87535 4.87535 0.32 0.00070198 0.000652914 0.0343575 0.0319558 -1 -1 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64216 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 23.6 MiB 0.07 1023 10540 2564 7150 826 62.7 MiB 0.10 0.00 4.27093 -125.084 -4.27093 4.27093 0.30 0.000635854 0.000590624 0.0312502 0.0290072 -1 -1 -1 -1 32 2034 20 6.64007e+06 452088 554710. 1919.41 0.53 0.105906 0.0929137 22834 132086 -1 1819 20 1043 1996 118484 27523 3.47223 3.47223 -116.792 -3.47223 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0255077 0.0222584 127 24 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.67 vpr 62.80 MiB -1 -1 0.14 18480 1 0.03 -1 -1 30144 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 319 257 1 198 93 17 17 289 -1 unnamed_device 23.8 MiB 0.21 1094 10173 2429 6748 996 62.8 MiB 0.11 0.00 5.10621 -136.906 -5.10621 5.10621 0.32 0.000655901 0.000609938 0.0340695 0.0316782 -1 -1 -1 -1 32 2080 22 6.64007e+06 364182 554710. 1919.41 0.54 0.113192 0.0993888 22834 132086 -1 1862 19 1043 1542 79123 20468 3.86682 3.86682 -126.192 -3.86682 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0252548 0.0221089 138 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 3.08 vpr 62.86 MiB -1 -1 0.27 18376 1 0.03 -1 -1 30320 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 23.8 MiB 0.20 1155 14373 4323 8054 1996 62.9 MiB 0.17 0.00 5.05909 -147.227 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32357 3.63163 3.63163 -128.953 -3.63163 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0246587 0.0216156 141 77 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 2.63 vpr 63.07 MiB -1 -1 0.22 18120 1 0.03 -1 -1 30300 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 251 219 1 140 94 17 17 289 -1 unnamed_device 23.3 MiB 0.08 923 15643 4702 9042 1899 63.1 MiB 0.13 0.00 3.5543 -104.7 -3.5543 3.5543 0.32 0.00055848 0.000519887 0.0433436 0.0403444 -1 -1 -1 -1 28 1834 21 6.64007e+06 376740 500653. 1732.36 0.56 0.108027 0.0957526 21970 115934 -1 1668 22 937 1393 89639 21079 2.65657 2.65657 -97.5617 -2.65657 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0239942 0.0208508 101 23 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.67 vpr 63.50 MiB -1 -1 0.16 18272 1 0.03 -1 -1 30040 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65020 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 23.9 MiB 0.19 1003 17023 5521 9148 2354 63.5 MiB 0.17 0.00 4.05053 -136.563 -4.05053 4.05053 0.32 0.000667134 0.000619094 0.0589093 0.0547082 -1 -1 -1 -1 32 2363 20 6.64007e+06 339066 554710. 1919.41 0.56 0.140709 0.125069 22834 132086 -1 2016 20 1250 1804 125844 29633 3.39003 3.39003 -130.188 -3.39003 0 0 701300. 2426.64 0.03 0.07 0.09 -1 -1 0.03 0.02694 0.0234839 133 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.84 vpr 62.91 MiB -1 -1 0.26 18464 1 0.03 -1 -1 30344 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 32 32 387 293 1 234 99 17 17 289 -1 unnamed_device 24.0 MiB 0.21 1435 16059 4481 10134 1444 62.9 MiB 0.17 0.00 5.58406 -162.308 -5.58406 5.58406 0.31 0.000764097 0.000710561 0.0566155 0.0526078 -1 -1 -1 -1 32 3124 21 6.64007e+06 439530 554710. 1919.41 0.58 0.147297 0.130581 22834 132086 -1 2675 22 1593 2519 150795 35527 4.87408 4.87408 -154.358 -4.87408 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0330463 0.028895 174 31 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 2.56 vpr 63.39 MiB -1 -1 0.17 18576 1 0.03 -1 -1 30528 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1083 12240 2973 8199 1068 63.4 MiB 0.12 0.00 4.33282 -136.421 -4.33282 4.33282 0.32 0.000691046 0.000642837 0.0380761 0.0353909 -1 -1 -1 -1 32 2036 19 6.64007e+06 477204 554710. 1919.41 0.54 0.117898 0.103855 22834 132086 -1 1889 22 1182 1950 109230 27017 2.85617 2.85617 -116.634 -2.85617 0 0 701300. 2426.64 0.03 0.07 0.10 -1 -1 0.03 0.0294348 0.0256088 141 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.47 vpr 62.55 MiB -1 -1 0.24 18040 1 0.03 -1 -1 30292 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64052 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 23.5 MiB 0.05 787 15647 4513 8348 2786 62.6 MiB 0.13 0.00 3.51327 -106.246 -3.51327 3.51327 0.32 0.000603837 0.000561213 0.0453604 0.0421794 -1 -1 -1 -1 32 1767 19 6.64007e+06 414414 554710. 1919.41 0.51 0.113315 0.100197 22834 132086 -1 1434 19 732 1177 64731 16326 2.73257 2.73257 -98.3112 -2.73257 0 0 701300. 2426.64 0.03 0.04 0.12 -1 -1 0.03 0.0169393 0.0148555 111 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.53 vpr 63.23 MiB -1 -1 0.26 18632 1 0.03 -1 -1 30244 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64744 32 32 431 332 1 235 97 17 17 289 -1 unnamed_device 24.4 MiB 0.31 1370 17635 5043 10114 2478 63.2 MiB 0.21 0.00 6.37067 -183.955 -6.37067 6.37067 0.32 0.000827281 0.000769095 0.0686146 0.0637394 -1 -1 -1 -1 26 3739 28 6.64007e+06 414414 477104. 1650.88 1.06 0.183963 0.163024 21682 110474 -1 2914 23 2106 3156 231468 52338 5.05174 5.05174 -171.67 -5.05174 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0364787 0.031749 177 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.78 vpr 62.80 MiB -1 -1 0.24 18536 1 0.03 -1 -1 30456 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1059 19142 5710 10959 2473 62.8 MiB 0.17 0.00 4.53287 -137.071 -4.53287 4.53287 0.35 0.000694142 0.000645825 0.0585836 0.0543714 -1 -1 -1 -1 32 2159 21 6.64007e+06 477204 554710. 1919.41 0.56 0.141425 0.1254 22834 132086 -1 1899 16 1017 1621 90851 21605 3.65443 3.65443 -127.571 -3.65443 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0232201 0.0203952 136 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.57 vpr 62.96 MiB -1 -1 0.21 17880 1 0.05 -1 -1 30276 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 231 199 1 140 93 17 17 289 -1 unnamed_device 23.4 MiB 0.06 697 14793 4064 8312 2417 63.0 MiB 0.12 0.00 3.58247 -96.388 -3.58247 3.58247 0.34 0.000536007 0.000498696 0.0399856 0.0372164 -1 -1 -1 -1 30 1597 22 6.64007e+06 364182 526063. 1820.29 0.51 0.104438 0.0921129 22546 126617 -1 1300 17 603 1018 57376 14793 2.68557 2.68557 -89.2135 -2.68557 0 0 666494. 2306.21 0.03 0.05 0.09 -1 -1 0.03 0.0188683 0.0164977 103 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.72 vpr 63.45 MiB -1 -1 0.13 18472 1 0.03 -1 -1 30204 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1247 19624 5520 11864 2240 63.4 MiB 0.19 0.00 5.68826 -140.03 -5.68826 5.68826 0.39 0.000705253 0.000655769 0.0593179 0.0551102 -1 -1 -1 -1 32 2366 18 6.64007e+06 502320 554710. 1919.41 0.54 0.139797 0.12415 22834 132086 -1 2129 14 824 1693 109078 25009 4.42708 4.42708 -129.323 -4.42708 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.021665 0.0190537 147 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.60 vpr 62.49 MiB -1 -1 0.22 17892 1 0.03 -1 -1 30152 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63992 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 23.2 MiB 0.07 838 15831 5106 8362 2363 62.5 MiB 0.13 0.00 3.5273 -107.609 -3.5273 3.5273 0.34 0.000557504 0.000519197 0.0480485 0.0446917 -1 -1 -1 -1 28 1874 20 6.64007e+06 288834 500653. 1732.36 0.55 0.114684 0.101665 21970 115934 -1 1689 20 1084 1860 116033 27873 2.77177 2.77177 -103.603 -2.77177 0 0 612192. 2118.31 0.03 0.06 0.11 -1 -1 0.03 0.0221893 0.0192968 107 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.88 vpr 62.60 MiB -1 -1 0.26 18212 1 0.02 -1 -1 30088 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 23.5 MiB 0.11 893 14252 4195 7695 2362 62.6 MiB 0.12 0.00 4.06561 -110.624 -4.06561 4.06561 0.32 0.000598189 0.000554889 0.0387015 0.0359501 -1 -1 -1 -1 28 2003 16 6.64007e+06 477204 500653. 1732.36 0.52 0.105135 0.0927138 21970 115934 -1 1666 21 1086 2090 130293 30391 2.82057 2.82057 -103.094 -2.82057 0 0 612192. 2118.31 0.03 0.07 0.13 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64348 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 23.8 MiB 0.11 925 11719 2758 8119 842 62.8 MiB 0.12 0.00 4.42033 -138.276 -4.42033 4.42033 0.32 0.00071589 0.000664168 0.0433359 0.0402562 -1 -1 -1 -1 32 2161 23 6.64007e+06 339066 554710. 1919.41 0.57 0.129395 0.113987 22834 132086 -1 1727 20 1284 1944 114196 28932 3.78702 3.78702 -131.455 -3.78702 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0279344 0.02439 135 54 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.92 vpr 62.80 MiB -1 -1 0.21 18364 1 0.03 -1 -1 30232 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1091 11798 3080 7487 1231 62.8 MiB 0.13 0.00 4.78258 -142.686 -4.78258 4.78258 0.32 0.000714923 0.00066408 0.0396764 0.0368336 -1 -1 -1 -1 32 2192 17 6.64007e+06 426972 554710. 1919.41 0.80 0.12021 0.105957 22834 132086 -1 2011 16 897 1626 93283 22441 3.62362 3.62362 -128.218 -3.62362 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0237017 0.020821 136 51 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.70 vpr 62.63 MiB -1 -1 0.23 18024 1 0.03 -1 -1 30240 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64136 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 23.5 MiB 0.22 888 6701 1459 4931 311 62.6 MiB 0.08 0.00 4.75515 -130.083 -4.75515 4.75515 0.32 0.00061059 0.000568906 0.023214 0.021603 -1 -1 -1 -1 32 1842 19 6.64007e+06 276276 554710. 1919.41 0.51 0.0918828 0.0803618 22834 132086 -1 1618 15 639 896 58501 14060 3.29883 3.29883 -115.297 -3.29883 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0190421 0.0167372 107 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 3.10 vpr 63.02 MiB -1 -1 0.24 18248 1 0.03 -1 -1 30368 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 31 32 319 272 1 169 88 17 17 289 -1 unnamed_device 23.9 MiB 0.18 793 16078 4554 9333 2191 63.0 MiB 0.15 0.00 4.00036 -122.569 -4.00036 4.00036 0.35 0.000662037 0.000616691 0.0553256 0.0514457 -1 -1 -1 -1 26 2534 43 6.64007e+06 313950 477104. 1650.88 0.88 0.155968 0.137486 21682 110474 -1 1828 21 1216 1787 118458 32053 3.24903 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62.76 MiB -1 -1 0.22 18036 1 0.03 -1 -1 30368 -1 -1 39 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 23.6 MiB 0.07 826 16971 4935 9183 2853 62.8 MiB 0.13 0.00 4.21293 -101.023 -4.21293 4.21293 0.33 0.000596135 0.000555002 0.0460918 0.0427488 -1 -1 -1 -1 28 1907 22 6.64007e+06 489762 500653. 1732.36 0.56 0.117192 0.10326 21970 115934 -1 1601 16 895 1627 90491 22777 3.47223 3.47223 -98.8073 -3.47223 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0195628 0.0171324 122 27 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 2.69 vpr 62.73 MiB -1 -1 0.24 18280 1 0.03 -1 -1 30360 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64232 30 32 317 269 1 152 84 17 17 289 -1 unnamed_device 23.6 MiB 0.13 892 13809 4602 7006 2201 62.7 MiB 0.14 0.00 3.90078 -115.622 -3.90078 3.90078 0.33 0.000645832 0.000599449 0.050946 0.0472279 -1 -1 -1 -1 32 1908 21 6.64007e+06 276276 554710. 1919.41 0.55 0.126734 0.111982 22834 132086 -1 1778 20 1210 2120 133437 31075 2.88777 2.88777 -110.499 -2.88777 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0256155 0.0222677 115 63 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 2.70 vpr 63.13 MiB -1 -1 0.23 18464 1 0.03 -1 -1 30084 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 24.2 MiB 0.20 1023 8934 2025 6373 536 63.1 MiB 0.10 0.00 4.0127 -132.01 -4.0127 4.0127 0.32 0.000666492 0.000619785 0.0319045 0.0296427 -1 -1 -1 -1 32 2101 18 6.64007e+06 326508 554710. 1919.41 0.51 0.108114 0.0949131 22834 132086 -1 1856 21 999 1501 89591 21554 3.43523 3.43523 -127.963 -3.43523 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0271682 0.0236631 127 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.58 vpr 62.80 MiB -1 -1 0.24 17836 1 0.03 -1 -1 30480 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 23.7 MiB 0.07 1062 14252 3702 8136 2414 62.8 MiB 0.13 0.00 4.61901 -130.215 -4.61901 4.61901 0.32 0.00064055 0.000596427 0.041619 0.0387028 -1 -1 -1 -1 32 2215 21 6.64007e+06 464646 554710. 1919.41 0.54 0.116815 0.103213 22834 132086 -1 1898 17 890 1636 102846 23210 3.48123 3.48123 -116.227 -3.48123 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0230624 0.0202398 134 4 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 2.84 vpr 62.77 MiB -1 -1 0.24 18520 1 0.03 -1 -1 30404 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 32 32 350 275 1 209 94 17 17 289 -1 unnamed_device 23.7 MiB 0.24 1264 11809 2906 7681 1222 62.8 MiB 0.15 0.00 5.33287 -167.061 -5.33287 5.33287 0.32 0.000711346 0.000661641 0.0419297 0.0389822 -1 -1 -1 -1 32 2723 21 6.64007e+06 376740 554710. 1919.41 0.55 0.127635 0.112686 22834 132086 -1 2415 23 1397 2174 128896 30488 4.21368 4.21368 -151.829 -4.21368 0 0 701300. 2426.64 0.03 0.08 0.13 -1 -1 0.03 0.0317654 0.0277194 151 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 2.72 vpr 62.87 MiB -1 -1 0.26 18388 1 0.03 -1 -1 30268 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64380 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1057 12556 3111 8883 562 62.9 MiB 0.13 0.00 4.57304 -141.272 -4.57304 4.57304 0.31 0.000744694 0.000690509 0.0434462 0.0401677 -1 -1 -1 -1 32 2404 16 6.64007e+06 464646 554710. 1919.41 0.58 0.125349 0.110487 22834 132086 -1 2052 22 1123 2086 137496 32021 3.42483 3.42483 -130.344 -3.42483 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.029294 0.0260026 143 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 3.17 vpr 63.51 MiB -1 -1 0.26 18504 1 0.03 -1 -1 30284 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1171 22877 7507 12807 2563 63.5 MiB 0.23 0.00 4.50063 -140.698 -4.50063 4.50063 0.32 0.000749823 0.000696543 0.0707641 0.0655291 -1 -1 -1 -1 28 2865 24 6.64007e+06 539994 500653. 1732.36 0.90 0.167847 0.148857 21970 115934 -1 2354 20 1509 2767 177950 42009 3.57023 3.57023 -133.916 -3.57023 0 0 612192. 2118.31 0.03 0.08 0.12 -1 -1 0.03 0.0272378 0.0238892 147 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 2.60 vpr 62.66 MiB -1 -1 0.23 18124 1 0.03 -1 -1 30212 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64160 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 23.3 MiB 0.11 713 13403 2936 9754 713 62.7 MiB 0.13 0.00 3.93272 -112.862 -3.93272 3.93272 0.31 0.000588042 0.00054711 0.0455557 0.0424041 -1 -1 -1 -1 32 1671 23 6.64007e+06 263718 554710. 1919.41 0.52 0.115722 0.102349 22834 132086 -1 1388 20 927 1637 89572 23518 2.75957 2.75957 -98.8479 -2.75957 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0231273 0.0201238 109 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 3.00 vpr 62.96 MiB -1 -1 0.15 18372 1 0.03 -1 -1 30400 -1 -1 27 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 23.9 MiB 0.14 908 7613 1681 5486 446 63.0 MiB 0.10 0.00 4.75724 -137.047 -4.75724 4.75724 0.33 0.000703115 0.000651164 0.0304087 0.0282733 -1 -1 -1 -1 30 2039 24 6.64007e+06 339066 526063. 1820.29 0.56 0.119796 0.104771 22546 126617 -1 1732 22 1329 2144 119677 29049 3.74463 3.74463 -129.51 -3.74463 0 0 666494. 2306.21 0.03 0.07 0.11 -1 -1 0.03 0.0308961 0.0269019 147 63 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 3.26 vpr 62.89 MiB -1 -1 0.25 18264 1 0.03 -1 -1 30268 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64404 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 23.9 MiB 0.15 1241 16708 5056 9561 2091 62.9 MiB 0.17 0.00 5.42161 -159.498 -5.42161 5.42161 0.32 0.000693499 0.000644788 0.0566391 0.0526498 -1 -1 -1 -1 26 3049 24 6.64007e+06 376740 477104. 1650.88 0.83 0.146388 0.129818 21682 110474 -1 2440 19 1446 2309 162344 36787 4.11869 4.11869 -142.164 -4.11869 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0265234 0.0231856 145 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 3.11 vpr 62.77 MiB -1 -1 0.22 18420 1 0.03 -1 -1 30276 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 23.8 MiB 0.19 1123 13148 3656 8360 1132 62.8 MiB 0.13 0.00 5.23915 -149.423 -5.23915 5.23915 0.31 0.000682659 0.00063482 0.0427424 0.0397167 -1 -1 -1 -1 32 2371 21 6.64007e+06 439530 554710. 1919.41 0.54 0.123323 0.108794 22834 132086 -1 2007 20 1118 1785 91779 24235 4.30908 4.30908 -140.1 -4.30908 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0272733 0.0238268 151 47 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.71 vpr 62.93 MiB -1 -1 0.16 18440 1 0.03 -1 -1 30492 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64440 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 23.9 MiB 0.22 1096 17964 4891 10960 2113 62.9 MiB 0.18 0.00 4.57324 -135.589 -4.57324 4.57324 0.32 0.000715024 0.000664031 0.0584301 0.0540634 -1 -1 -1 -1 32 2160 21 6.64007e+06 477204 554710. 1919.41 0.53 0.142222 0.125744 22834 132086 -1 1911 16 768 1346 77420 19006 3.06843 3.06843 -112.699 -3.06843 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0244076 0.0214461 144 83 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 3.14 vpr 62.87 MiB -1 -1 0.23 18512 1 0.03 -1 -1 30348 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64376 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1118 14939 4252 9072 1615 62.9 MiB 0.17 0.00 5.0668 -145.309 -5.0668 5.0668 0.32 0.000833667 0.000783031 0.0571683 0.0531632 -1 -1 -1 -1 26 2741 21 6.64007e+06 313950 477104. 1650.88 0.64 0.143122 0.126843 21682 110474 -1 2256 19 1322 2385 155087 35915 4.12322 4.12322 -139.521 -4.12322 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0275269 0.0240294 141 57 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 2.60 vpr 63.55 MiB -1 -1 0.22 18320 1 0.02 -1 -1 30212 -1 -1 39 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 29 32 378 310 1 177 100 17 17 289 -1 unnamed_device 23.9 MiB 0.12 968 16340 4628 9035 2677 63.5 MiB 0.15 0.00 4.31346 -118.41 -4.31346 4.31346 0.31 0.000717563 0.00066644 0.0530808 0.0492922 -1 -1 -1 -1 32 1959 22 6.64007e+06 489762 554710. 1919.41 0.57 0.138299 0.122133 22834 132086 -1 1772 19 1170 1904 102752 26149 2.95097 2.95097 -104.469 -2.95097 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0278536 0.0243207 137 85 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 2.35 vpr 62.90 MiB -1 -1 0.10 17788 1 0.03 -1 -1 30348 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64408 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 23.3 MiB 0.06 738 6563 1553 4423 587 62.9 MiB 0.07 0.00 3.86158 -110.86 -3.86158 3.86158 0.32 0.000556995 0.000519146 0.022238 0.0207307 -1 -1 -1 -1 28 1730 21 6.64007e+06 238602 500653. 1732.36 0.48 0.0882531 0.0772055 21970 115934 -1 1495 19 780 1190 73911 18771 2.91797 2.91797 -103.429 -2.91797 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0189262 0.0167874 99 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 2.89 vpr 62.98 MiB -1 -1 0.25 18504 1 0.03 -1 -1 30276 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 23.9 MiB 0.20 1044 14235 4068 7633 2534 63.0 MiB 0.16 0.00 4.71503 -140.381 -4.71503 4.71503 0.32 0.000736638 0.000684303 0.0542958 0.0503407 -1 -1 -1 -1 32 2187 20 6.64007e+06 439530 554710. 1919.41 0.64 0.16213 0.14341 22834 132086 -1 1906 20 1054 1793 106697 26383 3.63163 3.63163 -128.238 -3.63163 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0285345 0.0249014 135 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 2.91 vpr 62.84 MiB -1 -1 0.16 18280 1 0.03 -1 -1 30280 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 23.8 MiB 0.15 1159 10979 2643 7096 1240 62.8 MiB 0.13 0.00 4.8332 -152.333 -4.8332 4.8332 0.31 0.000764668 0.000709401 0.0465756 0.0431972 -1 -1 -1 -1 32 2514 24 6.64007e+06 313950 554710. 1919.41 0.63 0.140961 0.124202 22834 132086 -1 2265 22 1721 2851 169988 41091 3.69343 3.69343 -141.542 -3.69343 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0324477 0.0282823 155 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.86 vpr 62.62 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30408 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64128 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 23.6 MiB 0.19 1035 13157 3525 7788 1844 62.6 MiB 0.12 0.00 4.01361 -116.472 -4.01361 4.01361 0.32 0.000582519 0.00054112 0.0410765 0.0382132 -1 -1 -1 -1 26 2306 22 6.64007e+06 313950 477104. 1650.88 0.58 0.111377 0.0982278 21682 110474 -1 1974 17 851 1156 77563 18531 3.24903 3.24903 -111.931 -3.24903 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0206446 0.0180703 117 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 2.45 vpr 62.66 MiB -1 -1 0.23 17704 1 0.03 -1 -1 30328 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 31 32 245 205 1 150 86 17 17 289 -1 unnamed_device 23.4 MiB 0.06 846 9725 2485 6513 727 62.7 MiB 0.09 0.00 3.92438 -112.401 -3.92438 3.92438 0.32 0.000560266 0.000521845 0.0308085 0.0286528 -1 -1 -1 -1 26 1894 21 6.64007e+06 288834 477104. 1650.88 0.49 0.0963775 0.0845534 21682 110474 -1 1562 19 974 1584 90066 21476 3.02517 3.02517 -107.603 -3.02517 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0214189 0.018672 110 4 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 2.92 vpr 63.04 MiB -1 -1 0.25 18416 1 0.03 -1 -1 30548 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 348 274 1 211 95 17 17 289 -1 unnamed_device 23.9 MiB 0.21 1202 16295 5063 8969 2263 63.0 MiB 0.17 0.00 4.9923 -151.371 -4.9923 4.9923 0.32 0.000724101 0.000665988 0.0564527 0.0523689 -1 -1 -1 -1 28 2863 20 6.64007e+06 389298 500653. 1732.36 0.61 0.14137 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fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.83 vpr 63.50 MiB -1 -1 0.22 18104 1 0.03 -1 -1 30128 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 23.8 MiB 0.08 1267 17817 5114 10804 1899 63.5 MiB 0.17 0.00 5.50127 -148.27 -5.50127 5.50127 0.32 0.000728707 0.000677247 0.0534885 0.0496414 -1 -1 -1 -1 26 3165 21 6.64007e+06 539994 477104. 1650.88 0.75 0.150128 0.133373 21682 110474 -1 2620 21 1637 3007 196047 46131 4.58248 4.58248 -146.607 -4.58248 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0303632 0.0265432 162 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 2.47 vpr 63.33 MiB -1 -1 0.16 18544 1 0.03 -1 -1 30320 -1 -1 35 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 30 32 316 264 1 162 97 17 17 289 -1 unnamed_device 23.6 MiB 0.11 960 10531 2688 6948 895 63.3 MiB 0.10 0.00 3.53527 -104.629 -3.53527 3.53527 0.31 0.000642209 0.000597715 0.0327903 0.0304946 -1 -1 -1 -1 32 2029 21 6.64007e+06 439530 554710. 1919.41 0.53 0.108188 0.0949357 22834 132086 -1 1762 19 983 1688 92821 22824 2.84297 2.84297 -99.6625 -2.84297 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0302453 0.0267024 124 52 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.41 vpr 62.96 MiB -1 -1 0.21 18040 1 0.04 -1 -1 30284 -1 -1 25 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64472 27 32 255 219 1 132 84 17 17 289 -1 unnamed_device 23.4 MiB 0.06 787 11430 3535 6029 1866 63.0 MiB 0.09 0.00 3.4653 -96.8105 -3.4653 3.4653 0.31 0.000547949 0.000510433 0.0361061 0.0336224 -1 -1 -1 -1 26 1657 21 6.64007e+06 313950 477104. 1650.88 0.51 0.100455 0.088336 21682 110474 -1 1422 19 813 1258 87749 20598 2.78277 2.78277 -93.1625 -2.78277 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0211257 0.0183388 100 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 3.07 vpr 63.09 MiB -1 -1 0.27 18656 1 0.03 -1 -1 30364 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64600 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 24.1 MiB 0.23 1365 11573 2824 7922 827 63.1 MiB 0.14 0.00 4.52455 -140.933 -4.52455 4.52455 0.32 0.000801412 0.000743847 0.044303 0.0411451 -1 -1 -1 -1 28 3529 23 6.64007e+06 426972 500653. 1732.36 0.77 0.146905 0.129572 21970 115934 -1 2746 20 1678 2838 184848 42937 3.85503 3.85503 -135.927 -3.85503 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0325576 0.02856 176 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 2.99 vpr 62.80 MiB -1 -1 0.26 18276 1 0.04 -1 -1 30228 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 23.8 MiB 0.39 1024 16371 4802 8876 2693 62.8 MiB 0.16 0.00 5.51727 -159.864 -5.51727 5.51727 0.34 0.000713016 0.000661963 0.0620014 0.0576154 -1 -1 -1 -1 32 2133 17 6.64007e+06 339066 554710. 1919.41 0.54 0.143857 0.128081 22834 132086 -1 1963 20 1100 1863 103525 26373 4.38608 4.38608 -146.744 -4.38608 0 0 701300. 2426.64 0.03 0.08 0.12 -1 -1 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1105 13092 3416 8740 936 63.4 MiB 0.13 0.00 5.28888 -136.917 -5.28888 5.28888 0.32 0.000682744 0.000636151 0.0406021 0.0377399 -1 -1 -1 -1 26 2483 21 6.64007e+06 452088 477104. 1650.88 0.57 0.121401 0.10708 21682 110474 -1 2105 18 1009 1726 98465 23986 3.85982 3.85982 -125.513 -3.85982 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0247052 0.0216352 133 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 3.03 vpr 63.57 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30372 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 31 32 373 294 1 196 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1122 12321 3316 8274 731 63.6 MiB 0.13 0.00 4.92332 -128.094 -4.92332 4.92332 0.34 0.00073579 0.000681292 0.0411424 0.0381693 -1 -1 -1 -1 26 2511 21 6.64007e+06 477204 477104. 1650.88 0.52 0.127987 0.112686 21682 110474 -1 2210 19 1199 1943 114142 28132 3.83382 3.83382 -125.259 -3.83382 0 0 585099. 2024.56 0.03 0.07 0.08 -1 -1 0.03 0.0283169 0.0247367 151 50 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.79 vpr 63.06 MiB -1 -1 0.21 18440 1 0.03 -1 -1 30380 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 23.9 MiB 0.12 937 16973 5746 8109 3118 63.1 MiB 0.15 0.00 3.65167 -103.348 -3.65167 3.65167 0.31 0.000656815 0.000608992 0.0517459 0.048035 -1 -1 -1 -1 30 2391 26 6.64007e+06 452088 526063. 1820.29 0.71 0.136006 0.120034 22546 126617 -1 1842 21 1098 2007 113299 28167 2.97317 2.97317 -100.808 -2.97317 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0272394 0.0237126 130 51 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 2.84 vpr 62.82 MiB -1 -1 0.16 18264 1 0.03 -1 -1 30432 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64328 32 32 350 275 1 215 95 17 17 289 -1 unnamed_device 23.8 MiB 0.20 1238 11759 3130 7729 900 62.8 MiB 0.14 0.00 5.12264 -157.121 -5.12264 5.12264 0.31 0.000705322 0.000655159 0.0413169 0.0383528 -1 -1 -1 -1 30 2872 20 6.64007e+06 389298 526063. 1820.29 0.68 0.124517 0.109659 22546 126617 -1 2332 20 1512 2420 128301 30561 4.07588 4.07588 -141.785 -4.07588 0 0 666494. 2306.21 0.03 0.07 0.12 -1 -1 0.03 0.0280318 0.024467 157 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 2.75 vpr 63.51 MiB -1 -1 0.16 18348 1 0.03 -1 -1 30076 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1118 16856 4639 9867 2350 63.5 MiB 0.19 0.00 4.29207 -131.028 -4.29207 4.29207 0.31 0.000745147 0.000691805 0.0590137 0.0547729 -1 -1 -1 -1 28 2771 25 6.64007e+06 527436 500653. 1732.36 0.64 0.152811 0.135193 21970 115934 -1 2232 22 1473 2458 171773 41912 3.24756 3.24756 -122.119 -3.24756 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0326766 0.0284409 151 62 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 310 266 1 176 89 17 17 289 -1 unnamed_device 23.7 MiB 0.18 1008 13949 3776 8315 1858 62.8 MiB 0.13 0.00 4.57978 -129.405 -4.57978 4.57978 0.32 0.00063151 0.000586933 0.0463927 0.0431298 -1 -1 -1 -1 26 2049 24 6.64007e+06 313950 477104. 1650.88 0.57 0.124264 0.109558 21682 110474 -1 1787 23 1119 1542 99717 24464 3.33023 3.33023 -121.141 -3.33023 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0277593 0.0240193 122 58 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.76 vpr 62.94 MiB -1 -1 0.23 18416 1 0.03 -1 -1 30536 -1 -1 42 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64452 31 32 326 261 1 177 105 17 17 289 -1 unnamed_device 23.9 MiB 0.07 1024 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 23.7 MiB 0.16 891 10033 2595 6630 808 62.7 MiB 0.10 0.00 4.05756 -122.47 -4.05756 4.05756 0.32 0.000576971 0.000536748 0.0317137 0.029489 -1 -1 -1 -1 26 2157 24 6.64007e+06 313950 477104. 1650.88 0.58 0.107628 0.0941218 21682 110474 -1 1791 17 1028 1508 93693 23016 3.14183 3.14183 -112.031 -3.14183 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0322542 0.0280416 115 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.61 vpr 62.85 MiB -1 -1 0.23 18464 1 0.03 -1 -1 30032 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 928 11851 2930 8165 756 62.8 MiB 0.12 0.00 3.6645 -107.626 -3.6645 3.6645 0.32 0.000692969 0.000644427 0.0379377 0.035255 -1 -1 -1 -1 32 2115 19 6.64007e+06 464646 554710. 1919.41 0.53 0.122566 0.10828 22834 132086 -1 1665 19 935 1662 86651 22815 2.90897 2.90897 -104.818 -2.90897 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0268623 0.0234903 131 57 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.93 vpr 63.59 MiB -1 -1 0.27 18448 1 0.03 -1 -1 30300 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65116 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 23.9 MiB 0.22 976 13095 3017 8881 1197 63.6 MiB 0.16 0.00 4.0221 -123.818 -4.0221 4.0221 0.32 0.000756213 0.000702112 0.0516439 0.047975 -1 -1 -1 -1 30 2145 22 6.64007e+06 452088 526063. 1820.29 0.63 0.143583 0.126812 22546 126617 -1 1877 17 1096 1732 88550 22588 3.14957 3.14957 -120.621 -3.14957 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0260509 0.0228149 145 91 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.56 vpr 62.58 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30280 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 23.5 MiB 0.10 960 12162 3264 7675 1223 62.6 MiB 0.11 0.00 3.3869 -105.779 -3.3869 3.3869 0.32 0.000614672 0.000570831 0.0427904 0.0397298 -1 -1 -1 -1 30 1894 19 6.64007e+06 251160 526063. 1820.29 0.50 0.116751 0.103215 22546 126617 -1 1629 18 769 1207 61799 15365 2.74977 2.74977 -103.907 -2.74977 0 0 666494. 2306.21 0.03 0.05 0.12 -1 -1 0.03 0.0225046 0.0195903 111 57 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.56 vpr 62.65 MiB -1 -1 0.23 18312 1 0.02 -1 -1 30292 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64152 32 32 290 244 1 177 90 17 17 289 -1 unnamed_device 23.5 MiB 0.19 925 8532 1785 6264 483 62.6 MiB 0.09 0.00 4.36984 -131.165 -4.36984 4.36984 0.31 0.00061324 0.000570288 0.0280339 0.026075 -1 -1 -1 -1 28 2708 24 6.64007e+06 326508 500653. 1732.36 0.64 0.104096 0.0910882 21970 115934 -1 1954 20 1359 2003 122646 30886 3.38923 3.38923 -122.625 -3.38923 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0135228 0.0119375 124 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.77 vpr 62.77 MiB -1 -1 0.23 18380 1 0.03 -1 -1 30208 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 32 32 318 257 1 194 92 17 17 289 -1 unnamed_device 23.8 MiB 0.22 1138 15617 4303 9234 2080 62.8 MiB 0.15 0.00 4.77964 -132.452 -4.77964 4.77964 0.34 0.000658273 0.000609711 0.0519544 0.0481265 -1 -1 -1 -1 32 2299 20 6.64007e+06 351624 554710. 1919.41 0.55 0.12943 0.114511 22834 132086 -1 2021 21 1045 1511 98148 22991 3.72382 3.72382 -126.429 -3.72382 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0269217 0.0234482 138 30 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.61 vpr 63.38 MiB -1 -1 0.25 18340 1 0.03 -1 -1 30112 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 23.9 MiB 0.14 1027 8089 1720 5536 833 63.4 MiB 0.08 0.00 4.38084 -119.914 -4.38084 4.38084 0.31 0.00065193 0.000606249 0.0259897 0.0241864 -1 -1 -1 -1 28 2224 20 6.64007e+06 452088 500653. 1732.36 0.49 0.101951 0.0892092 21970 115934 -1 1875 18 849 1396 79670 19823 3.16663 3.16663 -107.118 -3.16663 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0240837 0.0210767 129 55 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 3.04 vpr 63.07 MiB -1 -1 0.24 18336 1 0.03 -1 -1 30404 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 32 32 393 312 1 213 94 17 17 289 -1 unnamed_device 23.9 MiB 0.24 1101 8401 1796 6209 396 63.1 MiB 0.11 0.00 5.62095 -173.541 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2.88697 2.88697 -102.774 -2.88697 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0204358 0.0177958 100 4 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 2.71 vpr 63.67 MiB -1 -1 0.30 18344 1 0.03 -1 -1 30260 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1132 12791 3491 8287 1013 63.7 MiB 0.15 0.00 4.42516 -144.482 -4.42516 4.42516 0.32 0.000777421 0.000722358 0.0449905 0.0417837 -1 -1 -1 -1 32 2175 23 6.64007e+06 464646 554710. 1919.41 0.56 0.138643 0.121972 22834 132086 -1 1928 20 1161 1813 106830 26306 3.76183 3.76183 -135.978 -3.76183 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0308308 0.0269198 146 90 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.52 vpr 62.92 MiB -1 -1 0.16 18316 1 0.03 -1 -1 30184 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 32 32 376 318 1 155 82 17 17 289 -1 unnamed_device 23.7 MiB 0.14 961 14678 5153 7870 1655 62.9 MiB 0.15 0.00 3.5251 -126.262 -3.5251 3.5251 0.32 0.000716805 0.000665017 0.061699 0.0573065 -1 -1 -1 -1 32 1789 17 6.64007e+06 226044 554710. 1919.41 0.53 0.141368 0.125423 22834 132086 -1 1636 19 1061 1511 101615 23343 2.65957 2.65957 -115.251 -2.65957 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0272319 0.0237407 116 96 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.68 vpr 63.50 MiB -1 -1 0.15 18392 1 0.03 -1 -1 30252 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1040 16059 4498 9094 2467 63.5 MiB 0.16 0.00 4.08563 -122.248 -4.08563 4.08563 0.32 0.000711584 0.000660221 0.0536532 0.0496695 -1 -1 -1 -1 32 2147 19 6.64007e+06 439530 554710. 1919.41 0.54 0.135243 0.119692 22834 132086 -1 1808 17 868 1394 77233 19535 2.86797 2.86797 -103.409 -2.86797 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0262874 0.0231714 134 60 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.76 vpr 63.12 MiB -1 -1 0.24 18356 1 0.05 -1 -1 30316 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 32 32 396 299 1 236 98 17 17 289 -1 unnamed_device 24.1 MiB 0.28 1248 18773 5780 9423 3570 63.1 MiB 0.20 0.00 6.37984 -185.995 -6.37984 6.37984 0.31 0.000780551 0.00072581 0.0680795 0.0632119 -1 -1 -1 -1 36 2761 19 6.64007e+06 426972 612192. 2118.31 1.34 0.222467 0.195692 23410 145293 -1 2234 16 1457 2063 137885 35563 4.99954 4.99954 -163.566 -4.99954 0 0 782063. 2706.10 0.03 0.07 0.12 -1 -1 0.03 0.0263971 0.0232455 177 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.60 vpr 62.75 MiB -1 -1 0.13 18124 1 0.03 -1 -1 30072 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 30 32 224 207 1 138 84 17 17 289 -1 unnamed_device 23.3 MiB 0.14 875 9783 2760 6082 941 62.7 MiB 0.08 0.00 3.31687 -101.206 -3.31687 3.31687 0.32 0.000501429 0.000467021 0.028543 0.0265577 -1 -1 -1 -1 26 1635 15 6.64007e+06 276276 477104. 1650.88 0.53 0.0837799 0.0736315 21682 110474 -1 1407 13 573 768 44589 11004 2.27497 2.27497 -90.5889 -2.27497 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0147089 0.0129252 92 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.45 vpr 62.72 MiB -1 -1 0.23 18136 1 0.03 -1 -1 30324 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 23.3 MiB 0.06 689 6731 1618 4756 357 62.7 MiB 0.08 0.00 4.09512 -115.35 -4.09512 4.09512 0.32 0.000599086 0.000557828 0.0252094 0.023468 -1 -1 -1 -1 30 1441 21 6.64007e+06 238602 526063. 1820.29 0.50 0.0996073 0.0873472 22546 126617 -1 1294 18 678 1174 70897 17025 2.86577 2.86577 -104.274 -2.86577 0 0 666494. 2306.21 0.03 0.05 0.11 -1 -1 0.03 0.0219962 0.0192113 95 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 2.63 vpr 62.67 MiB -1 -1 0.22 18180 1 0.03 -1 -1 30216 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64172 32 32 296 247 1 157 90 17 17 289 -1 unnamed_device 23.6 MiB 0.08 942 12552 3467 7974 1111 62.7 MiB 0.12 0.00 3.49427 -115.718 -3.49427 3.49427 0.32 0.000632151 0.000578248 0.041451 0.0384616 -1 -1 -1 -1 32 2080 20 6.64007e+06 326508 554710. 1919.41 0.62 0.114609 0.101229 22834 132086 -1 1868 22 1056 2009 127408 29897 2.69957 2.69957 -109.166 -2.69957 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0268929 0.0233414 119 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 2.61 vpr 62.79 MiB -1 -1 0.22 18028 1 0.03 -1 -1 30192 -1 -1 31 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 23.3 MiB 0.06 601 13543 4375 6504 2664 62.8 MiB 0.10 0.00 3.43127 -79.9 -3.43127 3.43127 0.32 0.000479119 0.000444893 0.0348322 0.0323139 -1 -1 -1 -1 32 1432 18 6.64007e+06 389298 554710. 1919.41 0.70 0.0896739 0.0790814 22834 132086 -1 1208 16 588 1034 67545 16020 2.66257 2.66257 -76.6177 -2.66257 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0163147 0.0142554 93 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 2.82 vpr 63.04 MiB -1 -1 0.25 18376 1 0.03 -1 -1 30224 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 376 307 1 185 88 17 17 289 -1 unnamed_device 24.0 MiB 0.16 989 17053 6066 7937 3050 63.0 MiB 0.18 0.00 4.31092 -130.251 -4.31092 4.31092 0.31 0.000731429 0.000679409 0.0669288 0.0621536 -1 -1 -1 -1 32 2483 22 6.64007e+06 301392 554710. 1919.41 0.58 0.153804 0.136564 22834 132086 -1 2014 19 1216 2250 133235 32112 3.97023 3.97023 -123.415 -3.97023 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0284099 0.0246596 137 72 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 2.87 vpr 62.98 MiB -1 -1 0.26 18340 1 0.03 -1 -1 30340 -1 -1 42 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64496 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 23.8 MiB 0.14 990 19124 5738 10202 3184 63.0 MiB 0.18 0.00 4.03784 -128.727 -4.03784 4.03784 0.32 0.000592896 0.000545424 0.0601703 0.0557054 -1 -1 -1 -1 30 2237 23 6.64007e+06 527436 526063. 1820.29 0.61 0.143789 0.127519 22546 126617 -1 1757 16 1113 1717 94449 22971 2.92383 2.92383 -113.587 -2.92383 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0263136 0.0230906 148 90 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 2.83 vpr 63.59 MiB -1 -1 0.25 18348 1 0.03 -1 -1 30064 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65120 32 32 354 285 1 202 99 17 17 289 -1 unnamed_device 24.2 MiB 0.17 1293 16743 4634 10568 1541 63.6 MiB 0.10 0.00 5.566 -161.813 -5.566 5.566 0.34 0.000331358 0.000304875 0.025734 0.0237042 -1 -1 -1 -1 32 2763 22 6.65987e+06 443730 554710. 1919.41 0.57 0.112732 0.0983887 22834 132086 -1 2449 19 1084 1699 139737 30053 4.09762 4.09762 -142.938 -4.09762 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0279861 0.0245724 153 50 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.75 vpr 63.43 MiB -1 -1 0.26 18392 1 0.03 -1 -1 30440 -1 -1 30 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 23.7 MiB 0.09 1161 17066 4950 10267 1849 63.4 MiB 0.18 0.00 4.92316 -142.534 -4.92316 4.92316 0.32 0.000711495 0.000661377 0.0607483 0.05633 -1 -1 -1 -1 32 2317 19 6.65987e+06 380340 554710. 1919.41 0.56 0.14224 0.126171 22834 132086 -1 2201 20 1285 1969 141789 31778 3.96643 3.96643 -135.327 -3.96643 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0286017 0.0250073 147 63 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.92 vpr 62.58 MiB -1 -1 0.23 18252 1 0.03 -1 -1 30424 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 32 32 299 247 1 188 95 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1005 7223 1515 5389 319 62.6 MiB 0.08 0.00 4.5072 -115.093 -4.5072 4.5072 0.32 0.000638459 0.000593954 0.023343 0.021723 -1 -1 -1 -1 26 2482 19 6.65987e+06 393018 477104. 1650.88 0.57 0.096452 0.084355 21682 110474 -1 2175 22 1225 1807 128173 38231 3.65077 3.65077 -115.591 -3.65077 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0283391 0.0248207 129 29 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.43 vpr 63.12 MiB -1 -1 0.17 18364 1 0.04 -1 -1 30272 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 23.3 MiB 0.04 1008 16445 5063 9076 2306 63.1 MiB 0.16 0.00 4.28955 -115.789 -4.28955 4.28955 0.31 0.000630792 0.000586242 0.0527628 0.0490015 -1 -1 -1 -1 32 2107 21 6.65987e+06 393018 554710. 1919.41 0.54 0.127475 0.112807 22834 132086 -1 1923 24 1162 2468 162514 37920 3.42191 3.42191 -111.417 -3.42191 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0300343 0.0260368 132 31 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.88 vpr 62.64 MiB -1 -1 0.23 18404 1 0.03 -1 -1 30412 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64144 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 23.6 MiB 0.06 926 17066 4722 10092 2252 62.6 MiB 0.18 0.00 4.32246 -124.084 -4.32246 4.32246 0.31 0.000682381 0.000633432 0.0584903 0.0542653 -1 -1 -1 -1 28 2659 35 6.65987e+06 354984 500653. 1732.36 0.85 0.156528 0.138194 21970 115934 -1 1952 22 1359 2592 155691 39529 3.65631 3.65631 -123.935 -3.65631 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0292856 0.0255564 134 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.51 vpr 62.75 MiB -1 -1 0.15 18452 1 0.03 -1 -1 30268 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 23.6 MiB 0.08 1006 10707 2558 7056 1093 62.7 MiB 0.11 0.00 3.2981 -110.874 -3.2981 3.2981 0.32 0.000715102 0.000664192 0.0344872 0.0320276 -1 -1 -1 -1 32 2059 17 6.65987e+06 494442 554710. 1919.41 0.52 0.114776 0.10094 22834 132086 -1 1766 16 1009 1653 81293 21469 2.93011 2.93011 -107.664 -2.93011 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0244838 0.0214969 145 58 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.33 vpr 62.35 MiB -1 -1 0.16 18212 1 0.03 -1 -1 30572 -1 -1 21 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63844 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 23.0 MiB 0.05 662 8508 2183 5532 793 62.3 MiB 0.08 0.00 3.64612 -97.2036 -3.64612 3.64612 0.32 0.000556352 0.000518731 0.02948 0.0274761 -1 -1 -1 -1 26 1488 20 6.65987e+06 266238 477104. 1650.88 0.46 0.0948889 0.0832974 21682 110474 -1 1285 19 839 1443 84061 21350 2.55211 2.55211 -89.8292 -2.55211 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0217986 0.0189775 97 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.55 vpr 62.41 MiB -1 -1 0.22 17868 1 0.03 -1 -1 30072 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63904 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 23.4 MiB 0.05 879 17198 5694 8745 2759 62.4 MiB 0.14 0.00 3.28184 -95.5565 -3.28184 3.28184 0.36 0.000595736 0.000552841 0.0478346 0.044364 -1 -1 -1 -1 32 2096 17 6.65987e+06 443730 554710. 1919.41 0.52 0.110623 0.0981322 22834 132086 -1 1775 20 943 1802 114464 28225 2.55445 2.55445 -90.648 -2.55445 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0241442 0.0210605 123 4 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.40 vpr 62.57 MiB -1 -1 0.15 18384 1 0.03 -1 -1 30052 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 31 32 317 271 1 168 87 17 17 289 -1 unnamed_device 23.4 MiB 0.09 925 6807 1453 4944 410 62.6 MiB 0.08 0.00 3.3699 -114.313 -3.3699 3.3699 0.32 0.000493922 0.000454414 0.024486 0.0227415 -1 -1 -1 -1 28 2084 19 6.65987e+06 304272 500653. 1732.36 0.51 0.0981972 0.0857413 21970 115934 -1 1840 15 921 1353 95741 23607 2.83031 2.83031 -109.983 -2.83031 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0207326 0.0181803 117 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.56 vpr 62.51 MiB -1 -1 0.22 18156 1 0.03 -1 -1 30016 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 23.4 MiB 0.09 817 6383 1432 4490 461 62.5 MiB 0.08 0.00 3.76232 -120.722 -3.76232 3.76232 0.32 0.000636848 0.000593635 0.024309 0.0226498 -1 -1 -1 -1 26 2054 21 6.65987e+06 240882 477104. 1650.88 0.54 0.0984567 0.0861078 21682 110474 -1 1799 19 1068 1672 105244 26336 2.74751 2.74751 -112.355 -2.74751 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.024046 0.0210051 115 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.55 vpr 62.52 MiB -1 -1 0.20 18352 1 0.03 -1 -1 30424 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.4 MiB 0.12 855 11106 3144 6574 1388 62.5 MiB 0.10 0.00 3.77152 -110.328 -3.77152 3.77152 0.34 0.000678385 0.000627002 0.0360956 0.0334026 -1 -1 -1 -1 32 1610 20 6.65987e+06 240882 554710. 1919.41 0.50 0.106565 0.093619 22834 132086 -1 1486 18 705 1168 66043 16527 2.64251 2.64251 -96.0214 -2.64251 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0227846 0.019903 101 63 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.74 vpr 62.46 MiB -1 -1 0.23 18072 1 0.03 -1 -1 30144 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63964 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 23.4 MiB 0.09 923 15063 4954 7940 2169 62.5 MiB 0.14 0.00 3.60095 -114.988 -3.60095 3.60095 0.32 0.000589529 0.000548359 0.048608 0.0452215 -1 -1 -1 -1 28 2245 30 6.65987e+06 291594 500653. 1732.36 0.75 0.136128 0.120028 21970 115934 -1 1857 21 1021 1396 110915 26979 3.05825 3.05825 -111.367 -3.05825 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.024645 0.0214555 111 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 2.79 vpr 62.86 MiB -1 -1 0.24 18380 1 0.08 -1 -1 30308 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1172 12063 3279 7731 1053 62.9 MiB 0.16 0.00 4.32078 -139.492 -4.32078 4.32078 0.33 0.000703373 0.000645846 0.0505267 0.04694 -1 -1 -1 -1 32 2466 23 6.65987e+06 367662 554710. 1919.41 0.56 0.135329 0.119646 22834 132086 -1 2158 23 1534 2364 144012 35379 3.01857 3.01857 -118.122 -3.01857 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0312134 0.027204 147 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.74 vpr 62.80 MiB -1 -1 0.24 18376 1 0.03 -1 -1 30196 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64308 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.10 971 17873 5392 9032 3449 62.8 MiB 0.19 0.00 4.50383 -130.941 -4.50383 4.50383 0.33 0.000717123 0.000666062 0.0669834 0.0620637 -1 -1 -1 -1 32 2088 18 6.65987e+06 431052 554710. 1919.41 0.57 0.148521 0.131949 22834 132086 -1 1825 20 1420 2352 139941 35041 3.57251 3.57251 -121.811 -3.57251 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0286098 0.0250144 139 61 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.47 vpr 62.38 MiB -1 -1 0.22 18052 1 0.03 -1 -1 30508 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63872 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 23.3 MiB 0.10 694 9600 2464 6430 706 62.4 MiB 0.08 0.00 2.92253 -85.631 -2.92253 2.92253 0.32 0.000543549 0.000506216 0.0305384 0.0284177 -1 -1 -1 -1 26 1711 20 6.65987e+06 291594 477104. 1650.88 0.48 0.0942953 0.0827929 21682 110474 -1 1601 22 1045 1797 119370 29179 2.51431 2.51431 -87.2887 -2.51431 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0234018 0.0202863 103 27 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 2.88 vpr 63.29 MiB -1 -1 0.27 18480 1 0.03 -1 -1 30296 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1152 16003 4822 9403 1778 63.3 MiB 0.16 0.00 4.09572 -126.446 -4.09572 4.09572 0.32 0.000716587 0.000665383 0.0595422 0.055318 -1 -1 -1 -1 32 2400 19 6.65987e+06 342306 554710. 1919.41 0.55 0.143212 0.12709 22834 132086 -1 2078 18 1135 2087 142666 37845 3.04917 3.04917 -116.306 -3.04917 0 0 701300. 2426.64 0.03 0.09 0.11 -1 -1 0.03 0.0348576 0.0302735 138 58 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 2.65 vpr 62.60 MiB -1 -1 0.24 18544 1 0.03 -1 -1 30216 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1125 12926 3639 7674 1613 62.6 MiB 0.14 0.00 4.394 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1444 83127 19598 2.00611 2.00611 -93.9149 -2.00611 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0208125 0.0182876 115 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 2.38 vpr 62.62 MiB -1 -1 0.21 18120 1 0.03 -1 -1 30240 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 23.1 MiB 0.05 693 9543 2321 6568 654 62.6 MiB 0.08 0.00 2.23087 -76.8517 -2.23087 2.23087 0.32 0.000503255 0.000468022 0.0298973 0.0278301 -1 -1 -1 -1 28 1420 15 6.65987e+06 215526 500653. 1732.36 0.50 0.0841738 0.0740953 21970 115934 -1 1307 22 674 1015 82701 19377 1.74665 1.74665 -75.5759 -1.74665 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0211611 0.0183274 85 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 2.98 vpr 62.58 MiB -1 -1 0.24 18392 1 0.03 -1 -1 30432 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64080 31 32 291 243 1 171 88 17 17 289 -1 unnamed_device 23.4 MiB 0.20 786 13738 3441 7180 3117 62.6 MiB 0.12 0.00 4.80308 -136.113 -4.80308 4.80308 0.31 0.000610132 0.000568245 0.0452547 0.0421109 -1 -1 -1 -1 32 2211 46 6.65987e+06 316950 554710. 1919.41 0.80 0.142447 0.124997 22834 132086 -1 1576 21 899 1285 88683 23465 3.84671 3.84671 -129.866 -3.84671 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0258407 0.0225526 127 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 3.39 vpr 63.26 MiB -1 -1 0.23 18456 1 0.03 -1 -1 30396 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 23.6 MiB 0.07 1092 18196 6057 9791 2348 63.3 MiB 0.17 0.00 4.25196 -133.154 -4.25196 4.25196 0.31 0.000696776 0.000647631 0.0565156 0.0524726 -1 -1 -1 -1 28 2596 21 6.65987e+06 469086 500653. 1732.36 0.78 0.140877 0.125047 21970 115934 -1 2180 20 1359 2318 167321 39385 3.69683 3.69683 -128.953 -3.69683 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0280309 0.0245652 140 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 3.33 vpr 62.74 MiB -1 -1 0.25 18336 1 0.03 -1 -1 30284 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 23.9 MiB 0.10 1229 17591 4978 10084 2529 62.7 MiB 0.19 0.00 4.43635 -136.819 -4.43635 4.43635 0.31 0.000723595 0.000672722 0.061937 0.0574339 -1 -1 -1 -1 32 2470 18 6.65987e+06 393018 554710. 1919.41 0.54 0.143942 0.127773 22834 132086 -1 2229 19 1285 1974 116123 28589 3.51771 3.51771 -123.874 -3.51771 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0285167 0.0249981 151 62 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.43 vpr 62.46 MiB -1 -1 0.14 18020 1 0.02 -1 -1 30524 -1 -1 20 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63960 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 23.1 MiB 0.07 431 10536 3837 3941 2758 62.5 MiB 0.07 0.00 2.35224 -64.6209 -2.35224 2.35224 0.32 0.000426133 0.000395077 0.0283186 0.0262801 -1 -1 -1 -1 28 1419 31 6.65987e+06 253560 500653. 1732.36 0.63 0.086015 0.075317 21970 115934 -1 1051 21 675 978 69553 19630 2.18965 2.18965 -68.0366 -2.18965 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0179993 0.0156342 81 30 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.46 vpr 63.06 MiB -1 -1 0.19 17944 1 0.03 -1 -1 30196 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 23.4 MiB 0.07 931 6623 1375 5033 215 63.1 MiB 0.07 0.00 4.36895 -119.052 -4.36895 4.36895 0.31 0.000615417 0.000572427 0.0229543 0.0213581 -1 -1 -1 -1 32 2111 24 6.65987e+06 316950 554710. 1919.41 0.56 0.0927906 0.081303 22834 132086 -1 1798 22 1076 2092 127185 31396 3.57251 3.57251 -117.08 -3.57251 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0267629 0.0233198 125 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.41 vpr 62.42 MiB -1 -1 0.16 17732 1 0.02 -1 -1 29972 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63916 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 23.0 MiB 0.04 493 11281 3421 5023 2837 62.4 MiB 0.09 0.00 2.48647 -71.166 -2.48647 2.48647 0.32 0.000878455 0.000815259 0.0342384 0.0317749 -1 -1 -1 -1 26 1361 33 6.65987e+06 215526 477104. 1650.88 0.65 0.0940299 0.082807 21682 110474 -1 922 14 531 645 59854 21541 1.95531 1.95531 -69.4327 -1.95531 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0133639 0.0117264 82 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.59 vpr 62.60 MiB -1 -1 0.16 18212 1 0.03 -1 -1 30044 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 23.5 MiB 0.09 898 10247 2366 7380 501 62.6 MiB 0.10 0.00 4.32789 -118.536 -4.32789 4.32789 0.32 0.000639255 0.000594623 0.0326551 0.0303542 -1 -1 -1 -1 26 2424 21 6.65987e+06 393018 477104. 1650.88 0.66 0.109099 0.0958696 21682 110474 -1 1959 20 1096 1916 134943 33891 3.50931 3.50931 -114.521 -3.50931 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0257508 0.0224904 126 24 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.57 vpr 62.66 MiB -1 -1 0.18 17776 1 0.03 -1 -1 30360 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 23.7 MiB 0.06 986 15527 4364 9095 2068 62.7 MiB 0.15 0.00 3.58941 -102.662 -3.58941 3.58941 0.32 0.00064423 0.000597693 0.0438764 0.0407061 -1 -1 -1 -1 32 2052 20 6.65987e+06 494442 554710. 1919.41 0.53 0.118788 0.104869 22834 132086 -1 1757 21 995 1984 121842 28850 2.78377 2.78377 -93.9889 -2.78377 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0253086 0.0224502 136 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 3.09 vpr 63.31 MiB -1 -1 0.15 18280 1 0.03 -1 -1 30412 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 338 277 1 179 99 17 17 289 -1 unnamed_device 23.7 MiB 0.08 1132 18339 5277 10722 2340 63.3 MiB 0.17 0.00 4.42603 -127.033 -4.42603 4.42603 0.32 0.000658681 0.000604043 0.0579563 0.0536309 -1 -1 -1 -1 26 2599 48 6.65987e+06 443730 477104. 1650.88 0.99 0.178629 0.157321 21682 110474 -1 2284 20 1343 2439 160763 40074 3.65545 3.65545 -127.111 -3.65545 0 0 585099. 2024.56 0.03 0.08 0.12 -1 -1 0.03 0.0273421 0.0238611 133 50 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.53 vpr 62.61 MiB -1 -1 0.21 17996 1 0.03 -1 -1 30100 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 23.5 MiB 0.06 916 11803 2959 7646 1198 62.6 MiB 0.11 0.00 3.02073 -105.462 -3.02073 3.02073 0.32 0.000596715 0.000554699 0.0399084 0.0371012 -1 -1 -1 -1 32 1826 19 6.65987e+06 266238 554710. 1919.41 0.51 0.109723 0.0968338 22834 132086 -1 1610 19 733 1113 70945 17055 2.33411 2.33411 -97.2001 -2.33411 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0233963 0.0204376 107 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.53 vpr 62.37 MiB -1 -1 0.23 18032 1 0.03 -1 -1 30212 -1 -1 28 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63864 30 32 262 227 1 135 90 17 17 289 -1 unnamed_device 23.1 MiB 0.07 668 7728 1645 5488 595 62.4 MiB 0.07 0.00 3.03787 -91.3278 -3.03787 3.03787 0.32 0.000583853 0.000535279 0.0239436 0.0222426 -1 -1 -1 -1 32 1487 23 6.65987e+06 354984 554710. 1919.41 0.52 0.092815 0.0810119 22834 132086 -1 1290 21 811 1389 92421 23927 2.68165 2.68165 -88.0109 -2.68165 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0236845 0.0205772 100 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 2.47 vpr 62.33 MiB -1 -1 0.22 18144 1 0.03 -1 -1 30148 -1 -1 27 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63824 28 32 260 223 1 140 87 17 17 289 -1 unnamed_device 23.3 MiB 0.06 623 10647 2615 7437 595 62.3 MiB 0.07 0.00 3.37407 -92.2897 -3.37407 3.37407 0.27 0.000565958 0.000526854 0.0191172 0.0175962 -1 -1 -1 -1 32 1558 18 6.65987e+06 342306 554710. 1919.41 0.52 0.0829422 0.0719943 22834 132086 -1 1314 21 834 1522 86562 22322 2.71857 2.71857 -89.5843 -2.71857 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0232677 0.0202501 104 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 2.70 vpr 62.44 MiB -1 -1 0.22 17840 1 0.03 -1 -1 30232 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 23.4 MiB 0.07 733 14035 5318 6638 2079 62.4 MiB 0.12 0.00 3.67009 -108.082 -3.67009 3.67009 0.32 0.000572926 0.000532536 0.0451769 0.0419649 -1 -1 -1 -1 32 1862 31 6.65987e+06 266238 554710. 1919.41 0.57 0.122063 0.107575 22834 132086 -1 1508 20 909 1486 90599 23830 2.64951 2.64951 -100.091 -2.64951 0 0 701300. 2426.64 0.04 0.06 0.10 -1 -1 0.04 0.0273808 0.0243873 116 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.57 vpr 62.43 MiB -1 -1 0.24 18192 1 0.03 -1 -1 30544 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63928 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 23.3 MiB 0.06 765 8199 1674 6237 288 62.4 MiB 0.08 0.00 3.38101 -98.7431 -3.38101 3.38101 0.32 0.000579578 0.000540067 0.0238147 0.0221697 -1 -1 -1 -1 26 1967 21 6.65987e+06 418374 477104. 1650.88 0.55 0.0977505 0.0853359 21682 110474 -1 1633 20 906 1519 84512 22222 2.82071 2.82071 -102.673 -2.82071 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0264682 0.0233523 111 30 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.70 vpr 62.84 MiB -1 -1 0.23 18384 1 0.03 -1 -1 30436 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 919 13961 3585 8809 1567 62.8 MiB 0.12 0.00 3.21564 -100.645 -3.21564 3.21564 0.32 0.000613384 0.000576201 0.0431614 0.0401718 -1 -1 -1 -1 32 1766 19 6.65987e+06 393018 554710. 1919.41 0.53 0.118447 0.104519 22834 132086 -1 1642 21 969 1515 100684 24375 2.21971 2.21971 -90.7495 -2.21971 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0246998 0.0214307 112 54 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 3.00 vpr 63.46 MiB -1 -1 0.24 18424 1 0.03 -1 -1 30404 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64988 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1278 14856 3856 9597 1403 63.5 MiB 0.14 0.00 4.04849 -118.625 -4.04849 4.04849 0.32 0.000738507 0.000685273 0.0468637 0.0434722 -1 -1 -1 -1 32 2520 23 6.65987e+06 532476 554710. 1919.41 0.66 0.128972 0.114192 22834 132086 -1 2343 20 1119 2110 130139 30403 3.27779 3.27779 -111.806 -3.27779 0 0 701300. 2426.64 0.04 0.07 0.11 -1 -1 0.04 0.0316226 0.0278407 158 29 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.84 vpr 63.34 MiB -1 -1 0.25 18416 1 0.03 -1 -1 30184 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 23.6 MiB 0.12 1103 11467 2726 7797 944 63.3 MiB 0.13 0.00 3.86972 -129.413 -3.86972 3.86972 0.32 0.000757179 0.000703981 0.0381411 0.0354271 -1 -1 -1 -1 28 2395 30 6.65987e+06 519798 500653. 1732.36 0.64 0.13815 0.121188 21970 115934 -1 2157 18 1571 2541 147293 36924 2.81751 2.81751 -115.433 -2.81751 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0280166 0.0245656 150 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.53 vpr 62.52 MiB -1 -1 0.22 18272 1 0.03 -1 -1 30232 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 23.4 MiB 0.09 916 12938 4123 6955 1860 62.5 MiB 0.12 0.00 4.11632 -122.804 -4.11632 4.11632 0.32 0.000592092 0.000550918 0.0429113 0.0399086 -1 -1 -1 -1 32 1802 19 6.65987e+06 291594 554710. 1919.41 0.50 0.112424 0.099407 22834 132086 -1 1621 21 899 1293 89858 21635 2.75411 2.75411 -103.631 -2.75411 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0251542 0.0219007 114 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.66 vpr 62.81 MiB -1 -1 0.25 18388 1 0.03 -1 -1 30428 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64316 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 962 14375 4628 7389 2358 62.8 MiB 0.15 0.00 4.01529 -116.343 -4.01529 4.01529 0.31 0.000715968 0.000664875 0.0525152 0.0487842 -1 -1 -1 -1 32 2097 20 6.65987e+06 367662 554710. 1919.41 0.55 0.136711 0.120978 22834 132086 -1 1740 19 953 1608 91219 23548 2.83077 2.83077 -103.661 -2.83077 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0283605 0.0250845 145 61 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.65 vpr 62.97 MiB -1 -1 0.26 18260 1 0.03 -1 -1 30408 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64480 31 32 377 302 1 234 99 17 17 289 -1 unnamed_device 24.1 MiB 0.07 1386 11043 2787 7293 963 63.0 MiB 0.13 0.00 5.91489 -170.972 -5.91489 5.91489 0.32 0.000736886 0.000685819 0.0385686 0.0358586 -1 -1 -1 -1 32 2873 20 6.65987e+06 456408 554710. 1919.41 0.57 0.124678 0.109747 22834 132086 -1 2486 19 1319 1924 126550 30073 4.39548 4.39548 -152.161 -4.39548 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0287112 0.0251583 178 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 3.22 vpr 63.42 MiB -1 -1 0.26 18348 1 0.03 -1 -1 30388 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 23.9 MiB 0.62 1238 16511 4791 9794 1926 63.4 MiB 0.18 0.00 4.89912 -151.132 -4.89912 4.89912 0.31 0.000738637 0.000685826 0.0591119 0.0549134 -1 -1 -1 -1 30 2429 21 6.65987e+06 405696 526063. 1820.29 0.55 0.146965 0.130343 22546 126617 -1 2186 20 1080 1696 96861 24644 4.08163 4.08163 -142.785 -4.08163 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0299256 0.026234 167 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.87 vpr 62.71 MiB -1 -1 0.19 18260 1 0.03 -1 -1 30456 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64216 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1124 12628 3322 8289 1017 62.7 MiB 0.13 0.00 4.44275 -130.243 -4.44275 4.44275 0.32 0.000707565 0.000658454 0.0406386 0.0377729 -1 -1 -1 -1 26 2643 23 6.65987e+06 469086 477104. 1650.88 0.59 0.126404 0.111239 21682 110474 -1 2328 21 1374 2327 147048 36129 3.16471 3.16471 -119.273 -3.16471 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0291973 0.0254676 140 55 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.83 vpr 62.69 MiB -1 -1 0.19 18456 1 0.03 -1 -1 30480 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 32 32 291 242 1 179 93 17 17 289 -1 unnamed_device 23.5 MiB 0.09 1082 11013 2473 7884 656 62.7 MiB 0.12 0.00 4.18181 -113.104 -4.18181 4.18181 0.32 0.000616948 0.000573587 0.03467 0.0322542 -1 -1 -1 -1 26 2738 25 6.65987e+06 367662 477104. 1650.88 0.84 0.114082 0.100194 21682 110474 -1 2132 19 1206 1813 126827 31200 3.29585 3.29585 -115.875 -3.29585 0 0 585099. 2024.56 0.03 0.06 0.11 -1 -1 0.03 0.024271 0.0212067 125 27 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 3.21 vpr 63.68 MiB -1 -1 0.27 18528 1 0.05 -1 -1 30400 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65204 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 24.1 MiB 0.22 1325 20094 5499 11953 2642 63.7 MiB 0.21 0.00 4.90518 -159.197 -4.90518 4.90518 0.32 0.000863265 0.00080313 0.0721534 0.0670195 -1 -1 -1 -1 26 3343 24 6.65987e+06 545154 477104. 1650.88 0.81 0.185067 0.163997 21682 110474 -1 2628 21 1646 2583 167664 39327 3.86217 3.86217 -144.748 -3.86217 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0362174 0.0316235 176 87 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.49 vpr 62.46 MiB -1 -1 0.23 18112 1 0.03 -1 -1 30172 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 23.4 MiB 0.09 737 9536 2387 5857 1292 62.5 MiB 0.09 0.00 3.48098 -96.6191 -3.48098 3.48098 0.32 0.000575726 0.000535589 0.0306291 0.0284653 -1 -1 -1 -1 30 1612 20 6.65987e+06 291594 526063. 1820.29 0.52 0.0958834 0.0841792 22546 126617 -1 1405 22 877 1491 83669 20744 2.47931 2.47931 -90.4761 -2.47931 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0247778 0.0215726 104 28 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 3.00 vpr 62.80 MiB -1 -1 0.26 18284 1 0.03 -1 -1 30132 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 23.8 MiB 0.08 1249 13195 3658 8262 1275 62.8 MiB 0.14 0.00 4.79192 -144.824 -4.79192 4.79192 0.34 0.000683955 0.000635929 0.0433617 0.0402853 -1 -1 -1 -1 24 3134 28 6.65987e+06 431052 448715. 1552.65 0.88 0.138378 0.12188 21394 104001 -1 2453 22 1503 2172 141924 34169 4.03451 4.03451 -135.006 -4.03451 0 0 554710. 1919.41 0.02 0.07 0.11 -1 -1 0.02 0.0296631 0.0258945 149 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.75 vpr 62.68 MiB -1 -1 0.24 18408 1 0.03 -1 -1 30420 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 349 284 1 183 102 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1155 13906 3407 9168 1331 62.7 MiB 0.13 0.00 3.8576 -113.911 -3.8576 3.8576 0.32 0.00069067 0.000641422 0.0431406 0.0400046 -1 -1 -1 -1 26 2941 21 6.65987e+06 481764 477104. 1650.88 0.66 0.128273 0.112978 21682 110474 -1 2377 20 1326 2410 166916 39546 3.17931 3.17931 -112.137 -3.17931 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0274615 0.0239703 137 53 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 2.85 vpr 62.54 MiB -1 -1 0.22 17876 1 0.03 -1 -1 30064 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 23.4 MiB 0.26 876 13147 4503 6169 2475 62.5 MiB 0.13 0.00 3.99841 -117.898 -3.99841 3.99841 0.32 0.000626788 0.000582687 0.043224 0.0401879 -1 -1 -1 -1 32 2071 32 6.65987e+06 342306 554710. 1919.41 0.59 0.127699 0.11235 22834 132086 -1 1695 23 1165 2183 127461 31331 3.47345 3.47345 -112.519 -3.47345 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0280871 0.0244558 127 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.78 vpr 62.70 MiB -1 -1 0.25 18404 1 0.03 -1 -1 30280 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64204 32 32 353 287 1 198 94 17 17 289 -1 unnamed_device 23.6 MiB 0.17 1224 8827 1935 6242 650 62.7 MiB 0.11 0.00 4.61566 -135.209 -4.61566 4.61566 0.31 0.000712229 0.000661663 0.0318336 0.0295804 -1 -1 -1 -1 30 2511 23 6.65987e+06 380340 526063. 1820.29 0.53 0.117116 0.102706 22546 126617 -1 2136 19 928 1310 71774 17944 3.20951 3.20951 -118.608 -3.20951 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0274664 0.0240917 142 55 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 2.77 vpr 63.24 MiB -1 -1 0.24 18424 1 0.03 -1 -1 30248 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1054 11189 2726 7692 771 63.2 MiB 0.11 0.00 3.80886 -119.733 -3.80886 3.80886 0.32 0.000712435 0.000662528 0.0358288 0.03325 -1 -1 -1 -1 26 2598 27 6.65987e+06 494442 477104. 1650.88 0.67 0.129506 0.113587 21682 110474 -1 2114 19 1188 2061 125664 30609 3.03311 3.03311 -114.46 -3.03311 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0230767 0.020264 139 55 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.81 vpr 62.77 MiB -1 -1 0.25 18280 1 0.03 -1 -1 30352 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1186 14744 3810 9393 1541 62.8 MiB 0.15 0.00 4.08875 -126.488 -4.08875 4.08875 0.32 0.000742546 0.000689999 0.0475827 0.0441969 -1 -1 -1 -1 26 2813 24 6.65987e+06 507120 477104. 1650.88 0.66 0.141553 0.124844 21682 110474 -1 2375 21 1537 2519 161666 39095 3.04491 3.04491 -117.668 -3.04491 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0308635 0.0269302 149 62 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 2.60 vpr 62.52 MiB -1 -1 0.22 17992 1 0.03 -1 -1 30320 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 23.4 MiB 0.09 1036 11932 2960 7977 995 62.5 MiB 0.11 0.00 3.95041 -117.901 -3.95041 3.95041 0.32 0.000629355 0.000583689 0.0352423 0.0326696 -1 -1 -1 -1 32 2001 21 6.65987e+06 456408 554710. 1919.41 0.54 0.112167 0.0985244 22834 132086 -1 1850 20 1003 1814 115866 27374 3.08765 3.08765 -108.602 -3.08765 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0250013 0.0219994 127 24 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.52 vpr 63.28 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30132 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64800 32 32 319 257 1 198 93 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1087 10383 2461 6851 1071 63.3 MiB 0.12 0.00 4.72526 -131.624 -4.72526 4.72526 0.32 0.000654215 0.000608358 0.0348778 0.0324333 -1 -1 -1 -1 32 2215 22 6.65987e+06 367662 554710. 1919.41 0.53 0.113498 0.0997649 22834 132086 -1 1949 19 1182 1681 99807 25080 3.68471 3.68471 -122.409 -3.68471 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.020965 0.0184721 138 29 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 2.78 vpr 62.82 MiB -1 -1 0.26 18340 1 0.03 -1 -1 30256 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64324 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 24.0 MiB 0.10 1150 17733 5210 9615 2908 62.8 MiB 0.19 0.00 4.69532 -137.386 -4.69532 4.69532 0.32 0.000727343 0.000676045 0.0638798 0.0592796 -1 -1 -1 -1 32 2496 21 6.65987e+06 380340 554710. 1919.41 0.58 0.150245 0.133328 22834 132086 -1 2250 20 1300 2007 143463 32554 3.78891 3.78891 -127.851 -3.78891 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.029378 0.0257092 152 62 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.75 vpr 63.07 MiB -1 -1 0.26 18400 1 0.03 -1 -1 30340 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 24.0 MiB 0.10 1167 14147 4331 7961 1855 63.1 MiB 0.16 0.00 3.97858 -128.122 -3.97858 3.97858 0.31 0.000748689 0.000687482 0.05575 0.05163 -1 -1 -1 -1 32 2577 21 6.65987e+06 316950 554710. 1919.41 0.57 0.143557 0.126963 22834 132086 -1 2276 19 1356 2418 159825 36180 3.35705 3.35705 -121.283 -3.35705 0 0 701300. 2426.64 0.03 0.07 0.10 -1 -1 0.03 0.0287086 0.0251227 141 77 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 2.28 vpr 62.30 MiB -1 -1 0.14 17988 1 0.03 -1 -1 30336 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63796 32 32 251 219 1 140 94 17 17 289 -1 unnamed_device 23.0 MiB 0.06 913 15643 4415 9418 1810 62.3 MiB 0.12 0.00 3.35098 -100.668 -3.35098 3.35098 0.32 0.000559149 0.0005199 0.0431236 0.0401111 -1 -1 -1 -1 32 1760 21 6.65987e+06 380340 554710. 1919.41 0.50 0.109026 0.0963947 22834 132086 -1 1658 17 804 1267 80945 19430 2.45125 2.45125 -90.1739 -2.45125 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0198175 0.0173259 101 23 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.75 vpr 62.68 MiB -1 -1 0.25 18244 1 0.03 -1 -1 30092 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64188 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 23.7 MiB 0.08 996 17023 5758 8918 2347 62.7 MiB 0.17 0.00 3.96847 -134.773 -3.96847 3.96847 0.32 0.000673933 0.000625952 0.0586522 0.0544351 -1 -1 -1 -1 28 2722 23 6.65987e+06 342306 500653. 1732.36 0.70 0.142328 0.126048 21970 115934 -1 2070 19 1306 1855 127035 31021 3.38897 3.38897 -128.298 -3.38897 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0258283 0.0225418 133 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.77 vpr 62.88 MiB -1 -1 0.24 18520 1 0.03 -1 -1 30352 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64392 32 32 387 293 1 234 99 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1433 14463 4059 9245 1159 62.9 MiB 0.16 0.00 5.18108 -151.87 -5.18108 5.18108 0.32 0.000764555 0.000710159 0.0512314 0.0475868 -1 -1 -1 -1 32 3076 23 6.65987e+06 443730 554710. 1919.41 0.58 0.144273 0.127505 22834 132086 -1 2769 21 1634 2613 161131 38979 4.04551 4.04551 -142.419 -4.04551 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.032354 0.0283413 174 31 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 2.52 vpr 62.75 MiB -1 -1 0.24 18392 1 0.03 -1 -1 30380 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64256 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 23.7 MiB 0.08 1064 9622 2158 6803 661 62.8 MiB 0.10 0.00 4.25077 -131.82 -4.25077 4.25077 0.32 0.000689443 0.000641753 0.030528 0.0283813 -1 -1 -1 -1 26 2445 19 6.65987e+06 481764 477104. 1650.88 0.54 0.111197 0.0976738 21682 110474 -1 2100 20 1180 2009 122888 30587 2.98991 2.98991 -119.17 -2.98991 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0282445 0.0247036 141 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.97 vpr 62.47 MiB -1 -1 0.22 18020 1 0.02 -1 -1 30388 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 23.4 MiB 0.06 873 7655 1741 5556 358 62.5 MiB 0.08 0.00 3.46801 -106.861 -3.46801 3.46801 0.29 0.000592529 0.000551119 0.0230086 0.0213939 -1 -1 -1 -1 26 1985 22 6.65987e+06 418374 477104. 1650.88 1.09 0.101588 0.0889863 21682 110474 -1 1566 19 872 1628 93100 23067 2.89891 2.89891 -101.232 -2.89891 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0227936 0.0198726 111 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.74 vpr 63.60 MiB -1 -1 0.27 18632 1 0.03 -1 -1 30348 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 32 32 431 332 1 235 97 17 17 289 -1 unnamed_device 24.1 MiB 0.16 1373 17857 5541 9729 2587 63.6 MiB 0.21 0.00 6.00689 -175.284 -6.00689 6.00689 0.32 0.000829838 0.000770463 0.0699701 0.065028 -1 -1 -1 -1 26 3848 37 6.65987e+06 418374 477104. 1650.88 1.45 0.197086 0.174141 21682 110474 -1 3002 21 1997 2930 217962 52054 5.28897 5.28897 -171.079 -5.28897 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0353896 0.0309506 177 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.72 vpr 62.68 MiB -1 -1 0.23 18428 1 0.03 -1 -1 30384 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 23.7 MiB 0.11 1017 19142 6169 10401 2572 62.7 MiB 0.18 0.00 4.49092 -134.922 -4.49092 4.49092 0.32 0.000688964 0.000639258 0.058669 0.0542224 -1 -1 -1 -1 32 2057 20 6.65987e+06 481764 554710. 1919.41 0.55 0.138961 0.123175 22834 132086 -1 1855 18 1006 1647 91104 22583 3.46031 3.46031 -122.488 -3.46031 0 0 701300. 2426.64 0.05 0.07 0.08 -1 -1 0.05 0.027125 0.0239429 136 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.42 vpr 62.38 MiB -1 -1 0.20 17912 1 0.05 -1 -1 30352 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63880 32 32 231 199 1 140 93 17 17 289 -1 unnamed_device 23.1 MiB 0.06 757 14793 4373 7837 2583 62.4 MiB 0.13 0.00 3.29469 -92.947 -3.29469 3.29469 0.32 0.000538264 0.000501659 0.0461663 0.0429533 -1 -1 -1 -1 30 1671 23 6.65987e+06 367662 526063. 1820.29 0.50 0.111364 0.098657 22546 126617 -1 1389 20 700 1220 66685 16954 2.41305 2.41305 -85.9205 -2.41305 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.021408 0.0186665 103 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.75 vpr 63.34 MiB -1 -1 0.23 18472 1 0.04 -1 -1 30316 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1150 19624 5000 12637 1987 63.3 MiB 0.19 0.00 5.1064 -126.138 -5.1064 5.1064 0.32 0.000704936 0.000655185 0.059793 0.055533 -1 -1 -1 -1 28 2459 23 6.65987e+06 507120 500653. 1732.36 0.57 0.147213 0.130679 21970 115934 -1 2168 22 1287 2791 166610 39959 3.96919 3.96919 -118.971 -3.96919 0 0 612192. 2118.31 0.03 0.08 0.12 -1 -1 0.03 0.0303989 0.0264907 147 29 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.52 vpr 63.21 MiB -1 -1 0.22 17964 1 0.03 -1 -1 30112 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64728 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 23.4 MiB 0.06 872 15831 4931 8734 2166 63.2 MiB 0.14 0.00 3.5083 -107.383 -3.5083 3.5083 0.32 0.000561581 0.00052297 0.050766 0.0471046 -1 -1 -1 -1 32 1802 23 6.65987e+06 291594 554710. 1919.41 0.51 0.118787 0.105164 22834 132086 -1 1692 22 1001 1708 115538 28004 2.61951 2.61951 -100.831 -2.61951 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0241798 0.0210207 107 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.78 vpr 62.54 MiB -1 -1 0.24 18124 1 0.03 -1 -1 30336 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 23.4 MiB 0.11 879 14252 3836 8169 2247 62.5 MiB 0.12 0.00 4.01069 -108.355 -4.01069 4.01069 0.34 0.000599354 0.000550843 0.0387901 0.0359731 -1 -1 -1 -1 26 2025 24 6.65987e+06 481764 477104. 1650.88 0.69 0.11377 0.100057 21682 110474 -1 1739 19 906 1763 110431 27178 2.97191 2.97191 -105.651 -2.97191 0 0 585099. 2024.56 0.03 0.06 0.07 -1 -1 0.03 0.0225145 0.0196321 110 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 3.39 vpr 63.42 MiB -1 -1 0.25 18252 1 0.03 -1 -1 30480 -1 -1 32 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 29 32 355 287 1 198 93 17 17 289 -1 unnamed_device 23.7 MiB 0.10 935 10383 2371 7436 576 63.4 MiB 0.12 0.00 4.5774 -127.327 -4.5774 4.5774 0.32 0.000695523 0.000647079 0.0369925 0.0343684 -1 -1 -1 -1 26 3076 43 6.65987e+06 405696 477104. 1650.88 1.04 0.149016 0.130089 21682 110474 -1 2152 21 1391 2137 138462 37475 3.39717 3.39717 -116.441 -3.39717 0 0 585099. 2024.56 0.04 0.09 0.10 -1 -1 0.04 0.0365452 0.031807 146 62 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 2.56 vpr 62.78 MiB -1 -1 0.24 18248 1 0.03 -1 -1 30348 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64288 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 23.8 MiB 0.09 929 8251 1789 6085 377 62.8 MiB 0.10 0.00 4.29907 -134.356 -4.29907 4.29907 0.32 0.000692743 0.000642667 0.0308125 0.0285985 -1 -1 -1 -1 32 2220 22 6.65987e+06 342306 554710. 1919.41 0.56 0.116133 0.101656 22834 132086 -1 1882 22 1411 2117 134488 33129 3.89817 3.89817 -131.246 -3.89817 0 0 701300. 2426.64 0.03 0.07 0.08 -1 -1 0.03 0.0309356 0.0270608 135 54 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.62 vpr 63.35 MiB -1 -1 0.23 18572 1 0.04 -1 -1 30276 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 23.7 MiB 0.11 1075 15173 3870 9435 1868 63.3 MiB 0.15 0.00 4.58626 -136.867 -4.58626 4.58626 0.32 0.000705923 0.000655882 0.0503308 0.046744 -1 -1 -1 -1 32 2211 20 6.65987e+06 431052 554710. 1919.41 0.55 0.132979 0.11753 22834 132086 -1 1968 17 847 1531 91027 22240 3.35191 3.35191 -122.638 -3.35191 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0253636 0.0223258 136 51 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.47 vpr 63.35 MiB -1 -1 0.25 18168 1 0.04 -1 -1 30140 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 23.7 MiB 0.10 901 6701 1571 4713 417 63.4 MiB 0.08 0.00 4.569 -127.264 -4.569 4.569 0.32 0.000598546 0.000556821 0.0231644 0.0215639 -1 -1 -1 -1 26 2033 20 6.65987e+06 278916 477104. 1650.88 0.48 0.0923268 0.0807068 21682 110474 -1 1721 21 882 1189 70078 18621 3.26691 3.26691 -112.036 -3.26691 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0140382 0.0124423 107 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.64 vpr 62.48 MiB -1 -1 0.20 18340 1 0.03 -1 -1 30296 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63980 31 32 319 272 1 169 88 17 17 289 -1 unnamed_device 23.6 MiB 0.09 802 16273 4920 8724 2629 62.5 MiB 0.15 0.00 3.75784 -117.415 -3.75784 3.75784 0.32 0.000637111 0.000591828 0.0557216 0.0517767 -1 -1 -1 -1 32 1992 22 6.65987e+06 316950 554710. 1919.41 0.53 0.132251 0.11715 22834 132086 -1 1605 18 979 1470 76824 20417 2.97351 2.97351 -106.635 -2.97351 0 0 701300. 2426.64 0.03 0.06 0.08 -1 -1 0.03 0.0249297 0.0217531 117 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.60 vpr 63.22 MiB -1 -1 0.24 18344 1 0.03 -1 -1 30272 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 23.6 MiB 0.10 889 16973 4879 9089 3005 63.2 MiB 0.15 0.00 3.33409 -93.1785 -3.33409 3.33409 0.32 0.000660544 0.000613972 0.0523942 0.048655 -1 -1 -1 -1 28 2254 24 6.65987e+06 456408 500653. 1732.36 0.56 0.134436 0.118707 21970 115934 -1 1914 19 1124 2027 125753 32278 2.56839 2.56839 -91.7219 -2.56839 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0254975 0.0222664 128 57 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.70 vpr 63.16 MiB -1 -1 0.14 18152 1 0.03 -1 -1 30384 -1 -1 39 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 23.5 MiB 0.07 817 17427 4857 10073 2497 63.2 MiB 0.14 0.00 3.74992 -95.3542 -3.74992 3.74992 0.32 0.00058808 0.000547246 0.0470504 0.0437117 -1 -1 -1 -1 26 2053 33 6.65987e+06 494442 477104. 1650.88 0.77 0.128498 0.112971 21682 110474 -1 1725 24 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 3.24 vpr 62.56 MiB -1 -1 0.26 18272 1 0.03 -1 -1 30104 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64064 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 23.6 MiB 0.10 976 8532 1791 6388 353 62.6 MiB 0.05 0.00 3.80404 -125.955 -3.80404 3.80404 0.33 0.000297142 0.000274077 0.0143566 0.0132378 -1 -1 -1 -1 32 2168 21 6.65987e+06 329628 554710. 1919.41 0.48 0.0866732 0.0751553 22834 132086 -1 1736 19 958 1411 91359 22142 3.07251 3.07251 -120.561 -3.07251 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0252589 0.022049 127 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 3.11 vpr 62.89 MiB -1 -1 0.22 17928 1 0.03 -1 -1 30320 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64396 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 23.7 MiB 0.06 1091 10540 2548 6838 1154 62.9 MiB 0.11 0.00 4.26866 -122.654 -4.26866 4.26866 0.29 0.000634407 0.000589944 0.031125 0.0289309 -1 -1 -1 -1 28 2517 21 6.65987e+06 469086 500653. 1732.36 0.62 0.10807 0.0950411 21970 115934 -1 2180 23 1405 2540 172113 40649 3.40705 3.40705 -114.855 -3.40705 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0283837 0.0247165 134 4 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 3.53 vpr 62.97 MiB -1 -1 0.23 18332 1 0.07 -1 -1 30300 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64484 32 32 350 275 1 209 94 17 17 289 -1 unnamed_device 24.2 MiB 0.12 1246 10957 2695 7343 919 63.0 MiB 0.14 0.00 4.99112 -158.75 -4.99112 4.99112 0.32 0.000702283 0.000653206 0.0389072 0.0361679 -1 -1 -1 -1 32 2654 21 6.65987e+06 380340 554710. 1919.41 0.57 0.124134 0.10938 22834 132086 -1 2391 19 1400 2095 119781 30173 3.76891 3.76891 -138.842 -3.76891 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0273598 0.0240069 151 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 3.66 vpr 62.86 MiB -1 -1 0.15 18304 1 0.03 -1 -1 30268 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1079 12086 3142 8350 594 62.9 MiB 0.13 0.00 4.38712 -137.823 -4.38712 4.38712 0.34 0.000739796 0.000684245 0.0423435 0.0392 -1 -1 -1 -1 26 3085 30 6.65987e+06 469086 477104. 1650.88 0.90 0.14435 0.126948 21682 110474 -1 2287 20 1476 2654 180213 42690 3.41471 3.41471 -132.144 -3.41471 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0171805 0.0153037 143 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 3.43 vpr 63.40 MiB -1 -1 0.25 18444 1 0.03 -1 -1 30348 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 23.6 MiB 0.12 1123 22877 7503 11320 4054 63.4 MiB 0.18 0.00 4.30832 -134.467 -4.30832 4.30832 0.31 0.000750956 0.000697579 0.0704916 0.0653897 -1 -1 -1 -1 30 3178 41 6.65987e+06 545154 526063. 1820.29 1.23 0.194275 0.172022 22546 126617 -1 2210 20 1341 2401 169392 39910 3.57111 3.57111 -125.638 -3.57111 0 0 666494. 2306.21 0.03 0.08 0.10 -1 -1 0.03 0.0298434 0.0261358 147 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 2.59 vpr 63.26 MiB -1 -1 0.23 18128 1 0.03 -1 -1 30188 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 23.7 MiB 0.11 704 8363 1755 6223 385 63.3 MiB 0.09 0.00 3.74343 -108.246 -3.74343 3.74343 0.31 0.000579714 0.000539557 0.0290906 0.0270951 -1 -1 -1 -1 32 1650 19 6.65987e+06 266238 554710. 1919.41 0.52 0.0923774 0.0813121 22834 132086 -1 1345 19 836 1444 76832 20508 2.45585 2.45585 -90.9532 -2.45585 0 0 701300. 2426.64 0.04 0.06 0.13 -1 -1 0.04 0.0289157 0.0251587 109 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 2.81 vpr 62.67 MiB -1 -1 0.26 18508 1 0.03 -1 -1 30404 -1 -1 27 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64176 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 23.6 MiB 0.13 1064 12365 3291 6967 2107 62.7 MiB 0.13 0.00 4.67895 -138.029 -4.67895 4.67895 0.31 0.000725007 0.000674131 0.0480908 0.0447495 -1 -1 -1 -1 28 2343 23 6.65987e+06 342306 500653. 1732.36 0.62 0.136452 0.120796 21970 115934 -1 1980 22 1486 2399 145841 36399 3.50937 3.50937 -127.985 -3.50937 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0317457 0.027759 147 63 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 2.65 vpr 63.50 MiB -1 -1 0.23 18316 1 0.03 -1 -1 30344 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1145 13939 3986 8000 1953 63.5 MiB 0.15 0.00 5.09463 -149.184 -5.09463 5.09463 0.29 0.000696151 0.000641679 0.0475882 0.0442297 -1 -1 -1 -1 30 2536 25 6.65987e+06 380340 526063. 1820.29 0.55 0.133121 0.117514 22546 126617 -1 2135 21 1195 1902 103374 25035 3.52651 3.52651 -127.669 -3.52651 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0288516 0.0252219 145 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 3.16 vpr 62.95 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30256 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64464 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 23.9 MiB 0.18 1110 13148 3427 8545 1176 63.0 MiB 0.13 0.00 5.06667 -144.178 -5.06667 5.06667 0.32 0.000692547 0.00064179 0.0430229 0.0399631 -1 -1 -1 -1 34 2291 34 6.65987e+06 443730 585099. 2024.56 0.95 0.190217 0.165664 23122 138558 -1 2068 20 1254 2153 127671 32495 3.93437 3.93437 -132.32 -3.93437 0 0 742403. 2568.87 0.03 0.07 0.11 -1 -1 0.03 0.0277139 0.0242435 151 47 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 3.18 vpr 63.29 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30392 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64808 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 23.6 MiB 0.48 1101 17500 4849 10565 2086 63.3 MiB 0.18 0.00 4.57218 -136.411 -4.57218 4.57218 0.32 0.000708472 0.000656727 0.0563314 0.0522355 -1 -1 -1 -1 32 2218 20 6.65987e+06 481764 554710. 1919.41 0.57 0.140582 0.124466 22834 132086 -1 1948 18 856 1457 86125 21283 2.99737 2.99737 -113.429 -2.99737 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0270237 0.0236907 144 83 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 2.62 vpr 62.48 MiB -1 -1 0.23 18356 1 0.03 -1 -1 30296 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63980 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 23.5 MiB 0.06 1122 13553 4012 8179 1362 62.5 MiB 0.15 0.00 4.81329 -139.106 -4.81329 4.81329 0.32 0.000714193 0.000663522 0.0516073 0.0479635 -1 -1 -1 -1 32 2281 22 6.65987e+06 316950 554710. 1919.41 0.55 0.136853 0.120971 22834 132086 -1 2146 22 1289 2236 137417 32546 3.53711 3.53711 -130.489 -3.53711 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0309713 0.0270326 141 57 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 2.70 vpr 62.69 MiB -1 -1 0.27 18380 1 0.03 -1 -1 30324 -1 -1 39 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 29 32 378 310 1 177 100 17 17 289 -1 unnamed_device 23.6 MiB 0.10 929 10076 2437 6533 1106 62.7 MiB 0.11 0.00 4.01172 -111.251 -4.01172 4.01172 0.31 0.000712445 0.000662323 0.0336174 0.0312492 -1 -1 -1 -1 30 1926 20 6.65987e+06 494442 526063. 1820.29 0.52 0.116714 0.10236 22546 126617 -1 1620 16 857 1390 66199 17216 2.81965 2.81965 -101.818 -2.81965 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0244566 0.0214747 137 85 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 2.43 vpr 62.31 MiB -1 -1 0.21 17984 1 0.02 -1 -1 30384 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63808 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 23.1 MiB 0.10 885 6923 1715 4767 441 62.3 MiB 0.07 0.00 3.77952 -113.03 -3.77952 3.77952 0.32 0.000553392 0.000515609 0.0230724 0.0214826 -1 -1 -1 -1 26 1838 17 6.65987e+06 240882 477104. 1650.88 0.52 0.0857542 0.0752007 21682 110474 -1 1658 19 797 1244 78852 19566 2.69545 2.69545 -103.315 -2.69545 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0288758 0.0251878 99 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 2.84 vpr 62.77 MiB -1 -1 0.25 18268 1 0.04 -1 -1 30308 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 23.7 MiB 0.14 1014 14691 4446 7278 2967 62.8 MiB 0.14 0.00 4.39152 -132.525 -4.39152 4.39152 0.32 0.000727586 0.00067249 0.0500078 0.046285 -1 -1 -1 -1 32 2332 30 6.65987e+06 443730 554710. 1919.41 0.69 0.146265 0.128769 22834 132086 -1 1872 23 1191 1892 138049 33056 3.67671 3.67671 -122.883 -3.67671 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0328304 0.0289108 135 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 2.92 vpr 62.82 MiB -1 -1 0.27 18284 1 0.04 -1 -1 30228 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64324 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 23.9 MiB 0.24 1125 9989 2357 6341 1291 62.8 MiB 0.12 0.00 4.65798 -147.06 -4.65798 4.65798 0.32 0.000769917 0.000714125 0.0415759 0.0386249 -1 -1 -1 -1 32 2196 23 6.65987e+06 316950 554710. 1919.41 0.57 0.134357 0.118291 22834 132086 -1 1980 20 1409 2358 138276 34236 3.43517 3.43517 -131.636 -3.43517 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0306802 0.0268235 155 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.71 vpr 62.58 MiB -1 -1 0.12 18084 1 0.03 -1 -1 30480 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 23.5 MiB 0.10 914 12761 3862 6624 2275 62.6 MiB 0.11 0.00 3.89235 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919 1562 92559 23224 2.59051 2.59051 -97.3557 -2.59051 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0214232 0.0186898 110 4 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 2.94 vpr 62.69 MiB -1 -1 0.25 18408 1 0.05 -1 -1 30416 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64196 32 32 348 274 1 211 95 17 17 289 -1 unnamed_device 23.9 MiB 0.08 1109 10031 2519 6610 902 62.7 MiB 0.11 0.00 4.87104 -146.551 -4.87104 4.87104 0.29 0.000698444 0.00064888 0.0352578 0.0327197 -1 -1 -1 -1 28 2980 22 6.65987e+06 393018 500653. 1732.36 0.73 0.127295 0.112131 21970 115934 -1 2316 20 1466 1984 138805 34064 3.84923 3.84923 -141.858 -3.84923 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0282332 0.0247056 151 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 3.22 vpr 63.35 MiB -1 -1 0.23 18512 1 0.03 -1 -1 30308 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 23.9 MiB 0.18 1270 17021 5150 9608 2263 63.3 MiB 0.16 0.00 5.06049 -146.913 -5.06049 5.06049 0.32 0.000326262 0.000301131 0.0486664 0.0450209 -1 -1 -1 -1 26 2988 41 6.65987e+06 469086 477104. 1650.88 0.74 0.159099 0.140044 21682 110474 -1 2434 19 1509 2359 161130 37560 4.17677 4.17677 -139.903 -4.17677 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0275016 0.0240929 157 56 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 3.13 vpr 63.51 MiB -1 -1 0.16 18148 1 0.03 -1 -1 30108 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 24.0 MiB 0.09 1310 18070 5249 10836 1985 63.5 MiB 0.18 0.00 5.25009 -142.167 -5.25009 5.25009 0.33 0.000717635 0.000666772 0.0540006 0.0501412 -1 -1 -1 -1 30 2632 26 6.65987e+06 545154 526063. 1820.29 0.63 0.147014 0.130114 22546 126617 -1 2281 21 1345 2651 147508 35512 4.20957 4.20957 -132.922 -4.20957 0 0 666494. 2306.21 0.03 0.08 0.10 -1 -1 0.03 0.0303179 0.0265724 162 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 2.58 vpr 62.57 MiB -1 -1 0.24 18272 1 0.03 -1 -1 30508 -1 -1 35 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64072 30 32 316 264 1 162 97 17 17 289 -1 unnamed_device 23.4 MiB 0.09 934 10531 2543 7170 818 62.6 MiB 0.10 0.00 3.47521 -102.746 -3.47521 3.47521 0.31 0.000642962 0.000598177 0.0327091 0.0304142 -1 -1 -1 -1 26 2134 21 6.65987e+06 443730 477104. 1650.88 0.52 0.108155 0.0949242 21682 110474 -1 1889 19 1136 2017 124547 30766 2.91491 2.91491 -103.283 -2.91491 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.025205 0.0220948 124 52 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.44 vpr 62.41 MiB -1 -1 0.23 18092 1 0.03 -1 -1 30328 -1 -1 25 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63912 27 32 255 219 1 132 84 17 17 289 -1 unnamed_device 23.1 MiB 0.06 785 11430 3670 6156 1604 62.4 MiB 0.09 0.00 3.4653 -96.6417 -3.4653 3.4653 0.32 0.00055453 0.000517011 0.0363306 0.0338398 -1 -1 -1 -1 28 1602 21 6.65987e+06 316950 500653. 1732.36 0.48 0.101316 0.0892106 21970 115934 -1 1425 17 804 1293 92891 21943 2.58157 2.58157 -90.7565 -2.58157 0 0 612192. 2118.31 0.03 0.05 0.12 -1 -1 0.03 0.0197648 0.0172594 100 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 3.26 vpr 63.04 MiB -1 -1 0.26 18600 1 0.03 -1 -1 30316 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64556 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 24.2 MiB 0.11 1363 12248 2996 8404 848 63.0 MiB 0.15 0.00 4.3132 -136.557 -4.3132 4.3132 0.33 0.000803131 0.000747134 0.0468158 0.0435051 -1 -1 -1 -1 26 3971 29 6.65987e+06 431052 477104. 1650.88 1.11 0.159017 0.14008 21682 110474 -1 2900 23 2053 3629 243596 58549 3.77365 3.77365 -132.773 -3.77365 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0224005 0.0199829 176 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 3.09 vpr 62.79 MiB -1 -1 0.27 18324 1 0.03 -1 -1 30420 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 23.7 MiB 0.44 973 17175 6014 8082 3079 62.8 MiB 0.17 0.00 5.18035 -150.464 -5.18035 5.18035 0.32 0.00070932 0.00065886 0.0637335 0.0591838 -1 -1 -1 -1 30 2403 24 6.65987e+06 342306 526063. 1820.29 0.64 0.151557 0.134524 22546 126617 -1 1847 18 1178 1814 98515 25469 4.49437 4.49437 -139.894 -4.49437 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0266933 0.0234329 151 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 2.91 vpr 63.18 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30424 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 32 32 331 280 1 175 87 17 17 289 -1 unnamed_device 23.4 MiB 0.40 1020 11991 3560 6392 2039 63.2 MiB 0.15 0.00 4.25169 -136.039 -4.25169 4.25169 0.32 0.000864673 0.000803635 0.0533516 0.0496012 -1 -1 -1 -1 32 2019 16 6.65987e+06 291594 554710. 1919.41 0.53 0.127172 0.112926 22834 132086 -1 1798 18 782 1100 71252 17324 3.25897 3.25897 -123.619 -3.25897 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0245208 0.0215202 131 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.95 vpr 62.66 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30324 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 23.7 MiB 0.09 1117 12164 3459 7844 861 62.7 MiB 0.12 0.00 4.92174 -128.183 -4.92174 4.92174 0.31 0.00066283 0.000615913 0.0374864 0.0347847 -1 -1 -1 -1 26 2516 22 6.65987e+06 456408 477104. 1650.88 0.54 0.119342 0.104951 21682 110474 -1 2181 18 1043 1793 114022 27754 3.30585 3.30585 -116.367 -3.30585 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0251273 0.0220676 133 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 3.01 vpr 63.32 MiB -1 -1 0.20 18484 1 0.04 -1 -1 30424 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 31 32 373 294 1 196 101 17 17 289 -1 unnamed_device 23.8 MiB 0.09 1058 9971 2285 7156 530 63.3 MiB 0.12 0.00 4.48315 -116.972 -4.48315 4.48315 0.31 0.000741538 0.000688786 0.0339044 0.0314509 -1 -1 -1 -1 26 2520 24 6.65987e+06 481764 477104. 1650.88 0.66 0.124359 0.108952 21682 110474 -1 2232 24 1463 2428 150433 38162 3.79065 3.79065 -118.424 -3.79065 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0340227 0.0296695 151 50 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 3.16 vpr 63.19 MiB -1 -1 0.26 18300 1 0.04 -1 -1 30248 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 23.7 MiB 0.05 942 16973 5403 7874 3696 63.2 MiB 0.16 0.00 3.53041 -100.229 -3.53041 3.53041 0.32 0.000653301 0.000605919 0.0516592 0.0479737 -1 -1 -1 -1 30 2372 36 6.65987e+06 456408 526063. 1820.29 0.98 0.16203 0.144241 22546 126617 -1 1915 21 1116 2063 128410 33008 2.85691 2.85691 -95.9916 -2.85691 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0273585 0.023878 130 51 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 3.26 vpr 62.72 MiB -1 -1 0.21 18384 1 0.38 -1 -1 30292 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 32 32 350 275 1 215 95 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1172 11111 2816 7554 741 62.7 MiB 0.13 0.00 4.87932 -149.985 -4.87932 4.87932 0.31 0.000704536 0.000655125 0.039028 0.0362615 -1 -1 -1 -1 30 2465 23 6.65987e+06 393018 526063. 1820.29 0.61 0.12583 0.110773 22546 126617 -1 2098 20 1422 2275 121154 29090 3.80811 3.80811 -133.242 -3.80811 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0288944 0.0253451 157 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 2.80 vpr 63.50 MiB -1 -1 0.25 18400 1 0.03 -1 -1 30040 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 24.0 MiB 0.11 1068 16856 4579 8928 3349 63.5 MiB 0.14 0.00 4.17081 -125.313 -4.17081 4.17081 0.32 0.000746376 0.000693057 0.0533797 0.0495831 -1 -1 -1 -1 32 2577 35 6.65987e+06 532476 554710. 1919.41 0.67 0.159111 0.140204 22834 132086 -1 2028 24 1434 2300 146117 37601 2.97097 2.97097 -114.135 -2.97097 0 0 701300. 2426.64 0.03 0.09 0.11 -1 -1 0.03 0.034841 0.0304283 151 62 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.34 vpr 62.36 MiB -1 -1 0.11 18144 1 0.03 -1 -1 30284 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63860 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 23.4 MiB 0.05 783 14184 4630 8014 1540 62.4 MiB 0.12 0.00 4.07075 -112.394 -4.07075 4.07075 0.32 0.000576339 0.000535755 0.0495872 0.0461609 -1 -1 -1 -1 32 1449 20 6.65987e+06 240882 554710. 1919.41 0.49 0.116661 0.103432 22834 132086 -1 1346 20 716 1069 69828 16923 2.81477 2.81477 -95.7948 -2.81477 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0229956 0.0200317 93 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.80 vpr 62.46 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30332 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63964 32 32 310 266 1 175 89 17 17 289 -1 unnamed_device 23.3 MiB 0.08 1007 13949 3952 8258 1739 62.5 MiB 0.12 0.00 4.24766 -126.418 -4.24766 4.24766 0.32 0.000481589 0.000443594 0.0432888 0.0401085 -1 -1 -1 -1 32 1793 18 6.65987e+06 316950 554710. 1919.41 0.52 0.11537 0.101824 22834 132086 -1 1672 14 756 1020 62601 15811 3.06877 3.06877 -112.763 -3.06877 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0198489 0.017478 122 58 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 3.17 vpr 63.25 MiB -1 -1 0.14 18252 1 0.03 -1 -1 30304 -1 -1 42 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 31 32 326 261 1 177 105 17 17 289 -1 unnamed_device 23.7 MiB 0.08 926 12208 3208 7327 1673 63.2 MiB 0.12 0.00 4.58372 -118.506 -4.58372 4.58372 0.32 0.000667937 0.000620673 0.0353145 0.0327327 -1 -1 -1 -1 26 2937 44 6.65987e+06 532476 477104. 1650.88 1.20 0.138033 0.120779 21682 110474 -1 2199 22 1468 2656 200310 48980 3.35491 3.35491 -114.974 -3.35491 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0289022 0.0251966 137 33 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 2.43 vpr 62.43 MiB -1 -1 0.25 18116 1 0.03 -1 -1 30216 -1 -1 27 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63924 29 32 262 224 1 168 88 17 17 289 -1 unnamed_device 23.3 MiB 0.07 896 15103 4215 9146 1742 62.4 MiB 0.13 0.00 4.17458 -112.81 -4.17458 4.17458 0.32 0.000565255 0.00052655 0.0458425 0.0426624 -1 -1 -1 -1 26 2150 22 6.65987e+06 342306 477104. 1650.88 0.56 0.115868 0.102438 21682 110474 -1 1818 17 869 1145 81501 19964 3.11697 3.11697 -104.705 -3.11697 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0201079 0.0175635 116 31 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.77 vpr 62.43 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30128 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63924 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 23.4 MiB 0.11 798 11243 4185 5675 1383 62.4 MiB 0.11 0.00 3.71146 -112.967 -3.71146 3.71146 0.31 0.000604244 0.000562734 0.0399845 0.0372544 -1 -1 -1 -1 28 2050 48 6.65987e+06 240882 500653. 1732.36 0.81 0.135941 0.119249 21970 115934 -1 1636 23 1302 2195 133693 34634 2.95805 2.95805 -111.835 -2.95805 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0268582 0.0233235 111 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.34 vpr 63.27 MiB -1 -1 0.25 18380 1 0.03 -1 -1 30168 -1 -1 40 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64788 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 23.6 MiB 0.11 943 8779 1827 6626 326 63.3 MiB 0.06 0.00 4.01172 -118.652 -4.01172 4.01172 0.29 0.000338799 0.000305712 0.0146354 0.0133262 -1 -1 -1 -1 30 1947 20 6.65987e+06 507120 526063. 1820.29 0.43 0.0819746 0.0711925 22546 126617 -1 1728 19 1148 1951 98929 24137 3.06517 3.06517 -108.924 -3.06517 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0279109 0.024443 141 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.43 vpr 62.47 MiB -1 -1 0.23 18124 1 0.03 -1 -1 30340 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 23.3 MiB 0.07 930 10228 2669 6535 1024 62.5 MiB 0.10 0.00 3.8161 -117.091 -3.8161 3.8161 0.32 0.000591034 0.000543686 0.0323042 0.0300571 -1 -1 -1 -1 32 1836 21 6.65987e+06 316950 554710. 1919.41 0.49 0.100283 0.0881994 22834 132086 -1 1638 17 808 1220 76603 18529 2.93457 2.93457 -107.171 -2.93457 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0213134 0.0187932 115 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.63 vpr 62.65 MiB -1 -1 0.23 18412 1 0.03 -1 -1 30008 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64156 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1077 18196 4934 11069 2193 62.7 MiB 0.16 0.00 3.54324 -109.963 -3.54324 3.54324 0.32 0.000538895 0.000495325 0.0514617 0.0475687 -1 -1 -1 -1 32 2182 22 6.65987e+06 469086 554710. 1919.41 0.56 0.134851 0.118993 22834 132086 -1 1852 21 982 1748 107334 25210 2.76771 2.76771 -104.243 -2.76771 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0290857 0.025433 131 57 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.95 vpr 63.34 MiB -1 -1 0.25 18248 1 0.03 -1 -1 30416 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 23.6 MiB 0.43 972 13779 3191 9639 949 63.3 MiB 0.14 0.00 3.95996 -122.236 -3.95996 3.95996 0.32 0.000747206 0.000693562 0.0474696 0.044021 -1 -1 -1 -1 28 2311 22 6.65987e+06 456408 500653. 1732.36 0.56 0.141858 0.125311 21970 115934 -1 2026 23 1471 2170 141402 36233 3.06423 3.06423 -122.172 -3.06423 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0405449 0.0360275 145 91 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.71 vpr 62.60 MiB -1 -1 0.24 18320 1 0.03 -1 -1 30252 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 23.5 MiB 0.11 931 10149 2799 6536 814 62.6 MiB 0.10 0.00 3.26564 -102.038 -3.26564 3.26564 0.31 0.000623729 0.00058006 0.0365945 0.0339944 -1 -1 -1 -1 32 1792 21 6.65987e+06 253560 554710. 1919.41 0.51 0.112588 0.0993539 22834 132086 -1 1603 17 732 1143 64605 16743 2.62971 2.62971 -101.046 -2.62971 0 0 701300. 2426.64 0.03 0.05 0.12 -1 -1 0.03 0.0221088 0.0193181 111 57 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.48 vpr 62.46 MiB -1 -1 0.22 18348 1 0.02 -1 -1 30420 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 32 32 290 244 1 177 90 17 17 289 -1 unnamed_device 23.3 MiB 0.08 852 6924 1415 4674 835 62.5 MiB 0.07 0.00 4.16652 -123.951 -4.16652 4.16652 0.32 0.000611583 0.00056898 0.0232007 0.0215469 -1 -1 -1 -1 30 2146 23 6.65987e+06 329628 526063. 1820.29 0.60 0.0975585 0.0850677 22546 126617 -1 1676 20 1036 1560 84668 22482 3.03051 3.03051 -112.2 -3.03051 0 0 666494. 2306.21 0.03 0.06 0.09 -1 -1 0.03 0.0244389 0.0213206 124 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.98 vpr 62.71 MiB -1 -1 0.24 18244 1 0.03 -1 -1 30184 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64212 32 32 318 257 1 194 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1091 8579 1943 6143 493 62.7 MiB 0.09 0.00 4.54938 -126.236 -4.54938 4.54938 0.36 0.000668476 0.000621141 0.0296112 0.0275522 -1 -1 -1 -1 26 2549 22 6.65987e+06 354984 477104. 1650.88 0.56 0.111992 0.0982032 21682 110474 -1 2178 22 1223 1795 118510 28680 3.58451 3.58451 -120.815 -3.58451 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0288121 0.0251317 138 30 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.56 vpr 62.76 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30248 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 23.5 MiB 0.11 1042 6535 1424 4454 657 62.8 MiB 0.07 0.00 4.20872 -115.808 -4.20872 4.20872 0.31 0.000653114 0.000605773 0.021466 0.0199964 -1 -1 -1 -1 30 1967 16 6.65987e+06 456408 526063. 1820.29 0.50 0.0934942 0.0815178 22546 126617 -1 1808 19 714 1267 68406 16641 2.71491 2.71491 -97.6025 -2.71491 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0257432 0.0225677 129 55 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 2.87 vpr 63.45 MiB -1 -1 0.23 18276 1 0.03 -1 -1 30480 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 393 312 1 213 94 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1136 17773 5438 9801 2534 63.4 MiB 0.19 0.00 5.18709 -160.79 -5.18709 5.18709 0.32 0.000751899 0.000698984 0.0661306 0.0614276 -1 -1 -1 -1 32 2400 22 6.65987e+06 380340 554710. 1919.41 0.61 0.167742 0.148709 22834 132086 -1 2213 22 1428 1987 125431 30881 3.96237 3.96237 -142.636 -3.96237 0 0 701300. 2426.64 0.04 0.10 0.11 -1 -1 0.04 0.0400136 0.0353947 159 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.46 vpr 62.59 MiB -1 -1 0.23 17952 1 0.03 -1 -1 30084 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 23.3 MiB 0.07 877 10515 2651 6990 874 62.6 MiB 0.10 0.00 3.28101 -98.7222 -3.28101 3.28101 0.34 0.000534255 0.000496925 0.0325397 0.0303173 -1 -1 -1 -1 26 1877 19 6.65987e+06 266238 477104. 1650.88 0.50 0.0939242 0.0826791 21682 110474 -1 1635 20 877 1459 98976 23834 2.63371 2.63371 -97.6023 -2.63371 0 0 585099. 2024.56 0.03 0.05 0.10 -1 -1 0.03 0.0218513 0.0190899 100 4 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 2.65 vpr 62.72 MiB -1 -1 0.24 18344 1 0.03 -1 -1 30248 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 23.8 MiB 0.09 1128 13026 3490 8482 1054 62.7 MiB 0.15 0.00 4.18264 -138.84 -4.18264 4.18264 0.32 0.00077668 0.000721567 0.0462737 0.0429443 -1 -1 -1 -1 32 2113 19 6.65987e+06 469086 554710. 1919.41 0.54 0.135721 0.119721 22834 132086 -1 1946 19 1104 1594 96411 24003 3.39911 3.39911 -128.845 -3.39911 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0296925 0.0260202 146 90 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.64 vpr 62.69 MiB -1 -1 0.24 18448 1 0.03 -1 -1 30108 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 32 32 376 318 1 156 82 17 17 289 -1 unnamed_device 23.7 MiB 0.11 914 11474 3086 6952 1436 62.7 MiB 0.13 0.00 3.54227 -124.771 -3.54227 3.54227 0.32 0.000718606 0.000667277 0.049602 0.046095 -1 -1 -1 -1 32 1720 17 6.65987e+06 228204 554710. 1919.41 0.53 0.129159 0.114224 22834 132086 -1 1578 21 1236 1858 105693 26868 2.87077 2.87077 -119.337 -2.87077 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0294216 0.0256661 117 96 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.69 vpr 63.28 MiB -1 -1 0.15 18304 1 0.03 -1 -1 30320 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 23.6 MiB 0.09 987 16059 4384 8773 2902 63.3 MiB 0.15 0.00 3.84552 -115.819 -3.84552 3.84552 0.33 0.000588113 0.000522126 0.0529609 0.0491666 -1 -1 -1 -1 32 2087 20 6.65987e+06 443730 554710. 1919.41 0.55 0.136764 0.121046 22834 132086 -1 1731 18 919 1426 73695 19390 2.62331 2.62331 -97.5338 -2.62331 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0269736 0.023685 134 60 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.78 vpr 63.52 MiB -1 -1 0.15 18496 1 0.03 -1 -1 30488 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65040 32 32 396 299 1 236 98 17 17 289 -1 unnamed_device 23.9 MiB 0.16 1229 18773 5439 9701 3633 63.5 MiB 0.18 0.00 6.00689 -176.035 -6.00689 6.00689 0.34 0.000348158 0.00032017 0.0661284 0.0613889 -1 -1 -1 -1 36 2968 23 6.65987e+06 431052 612192. 2118.31 1.43 0.227075 0.199663 23410 145293 -1 2288 21 1763 2474 164498 42055 4.85537 4.85537 -153.246 -4.85537 0 0 782063. 2706.10 0.04 0.07 0.11 -1 -1 0.04 0.0231769 0.0207501 177 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.52 vpr 62.36 MiB -1 -1 0.16 18020 1 0.03 -1 -1 30244 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63860 30 32 224 207 1 138 84 17 17 289 -1 unnamed_device 23.1 MiB 0.06 852 12894 3845 7396 1653 62.4 MiB 0.10 0.00 3.23481 -100.258 -3.23481 3.23481 0.34 0.000510384 0.000474865 0.0371748 0.0345906 -1 -1 -1 -1 26 1611 17 6.65987e+06 278916 477104. 1650.88 0.51 0.0938904 0.0829793 21682 110474 -1 1486 21 811 1082 72254 17229 2.47811 2.47811 -92.0662 -2.47811 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0207099 0.0179707 92 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.53 vpr 62.52 MiB -1 -1 0.22 18088 1 0.03 -1 -1 30344 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 23.4 MiB 0.13 726 6206 1469 4338 399 62.5 MiB 0.07 0.00 3.83543 -111.011 -3.83543 3.83543 0.37 0.000605709 0.000564518 0.0236706 0.0220708 -1 -1 -1 -1 26 1610 20 6.65987e+06 240882 477104. 1650.88 0.53 0.0949303 0.0830353 21682 110474 -1 1409 23 974 1626 100425 25629 2.75671 2.75671 -100.414 -2.75671 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0268728 0.0233444 95 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 2.42 vpr 62.57 MiB -1 -1 0.22 18080 1 0.03 -1 -1 30224 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 32 32 296 247 1 157 90 17 17 289 -1 unnamed_device 23.4 MiB 0.04 895 10743 2661 7468 614 62.6 MiB 0.11 0.00 3.40601 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65588 32 32 354 285 1 191 88 17 17 289 -1 unnamed_device 24.5 MiB 1.20 903 15298 5538 7704 2056 64.1 MiB 0.13 0.00 5.15265 -149.781 -5.15265 5.15265 0.35 0.000701928 0.000652099 0.0579569 0.0538537 -1 -1 -1 -1 40 2487 22 6.95648e+06 347416 706193. 2443.58 8.24 0.381864 0.330066 26914 176310 -1 2069 20 1681 2521 193589 46028 4.70236 4.70236 -152.72 -4.70236 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0283789 0.0248703 85 50 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 6.23 vpr 63.55 MiB -1 -1 0.25 18552 1 0.03 -1 -1 30328 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 30 32 363 293 1 187 80 17 17 289 -1 unnamed_device 24.5 MiB 1.72 822 9540 3866 5233 441 63.5 MiB 0.10 0.00 4.21658 -127.866 -4.21658 4.21658 0.35 0.000715716 0.00066455 0.0428595 0.0398403 -1 -1 -1 -1 40 2503 31 6.95648e+06 260562 706193. 2443.58 1.90 0.201124 0.174937 26914 176310 -1 2075 22 1955 2787 228608 53991 4.26192 4.26192 -142.656 -4.26192 0 0 926341. 3205.33 0.04 0.09 0.15 -1 -1 0.04 0.0315981 0.0277047 79 63 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_003.v common 9.49 vpr 63.92 MiB -1 -1 0.12 18316 1 0.03 -1 -1 30420 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65456 32 32 299 247 1 182 82 17 17 289 -1 unnamed_device 24.2 MiB 0.81 857 12542 4298 6587 1657 63.9 MiB 0.11 0.00 3.78245 -113.708 -3.78245 3.78245 0.33 0.000620895 0.000576964 0.0461334 0.0428945 -1 -1 -1 -1 38 2559 29 6.95648e+06 260562 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fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 4.13 vpr 63.91 MiB -1 -1 0.24 18416 1 0.03 -1 -1 30432 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65440 32 32 336 268 1 167 85 17 17 289 -1 unnamed_device 24.2 MiB 0.30 799 12919 4266 6230 2423 63.9 MiB 0.14 0.00 3.92082 -123.639 -3.92082 3.92082 0.33 0.000689843 0.000640891 0.0579711 0.053704 -1 -1 -1 -1 40 2419 26 6.95648e+06 303989 706193. 2443.58 1.73 0.195597 0.171434 26914 176310 -1 1974 23 1432 2633 220972 49560 4.01942 4.01942 -133.562 -4.01942 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0306242 0.026712 76 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_006.v common 4.55 vpr 63.35 MiB -1 -1 0.25 18324 1 0.03 -1 -1 30296 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 366 295 1 182 89 17 17 289 -1 unnamed_device 24.5 MiB 0.40 1004 13949 3867 8912 1170 63.3 MiB 0.13 0.00 3.1127 -117.428 -3.1127 3.1127 0.33 0.000898578 0.000838343 0.0537559 0.0498994 -1 -1 -1 -1 34 2773 40 6.95648e+06 361892 618332. 2139.56 2.07 0.217268 0.189412 25762 151098 -1 2255 18 1337 2010 155622 35041 3.22637 3.22637 -127.705 -3.22637 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0266073 0.0233266 81 58 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_007.v common 6.63 vpr 63.88 MiB -1 -1 0.23 18196 1 0.03 -1 -1 30616 -1 -1 14 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65412 27 32 259 221 1 124 73 17 17 289 -1 unnamed_device 24.3 MiB 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65216 30 32 303 262 1 135 75 17 17 289 -1 unnamed_device 24.3 MiB 0.89 501 7975 2162 4189 1624 63.7 MiB 0.07 0.00 3.32418 -98.7921 -3.32418 3.32418 0.33 0.000626842 0.000583299 0.033361 0.031035 -1 -1 -1 -1 42 1361 50 6.95648e+06 188184 744469. 2576.02 1.38 0.180268 0.155588 27202 183097 -1 1018 21 1057 1561 93379 26253 2.99162 2.99162 -104.394 -2.99162 0 0 949917. 3286.91 0.04 0.06 0.15 -1 -1 0.04 0.0261378 0.022782 54 63 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_012.v common 4.57 vpr 63.32 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30204 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 276 237 1 161 77 17 17 289 -1 unnamed_device 24.3 MiB 1.18 717 11487 4799 6349 339 63.3 MiB 0.05 0.00 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65720 32 32 370 297 1 178 81 17 17 289 -1 unnamed_device 24.6 MiB 0.55 1116 11456 4128 5618 1710 64.2 MiB 0.11 0.00 3.1427 -121.494 -3.1427 3.1427 0.33 0.000717433 0.000666227 0.0497802 0.0462674 -1 -1 -1 -1 38 2695 25 6.95648e+06 246087 678818. 2348.85 7.13 0.321783 0.277821 26626 170182 -1 2317 20 1511 2426 195538 40467 3.13107 3.13107 -128.649 -3.13107 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.029045 0.0253744 77 58 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 5.39 vpr 64.05 MiB -1 -1 0.23 18332 1 0.03 -1 -1 30084 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65592 32 32 338 269 1 190 81 17 17 289 -1 unnamed_device 24.2 MiB 1.49 1015 13031 4708 5937 2386 64.1 MiB 0.12 0.00 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/home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 342 271 1 172 91 17 17 289 -1 unnamed_device 24.5 MiB 0.23 777 13351 4773 6428 2150 63.5 MiB 0.11 0.00 3.69009 -122.34 -3.69009 3.69009 0.33 0.000688999 0.000639455 0.047794 0.0443687 -1 -1 -1 -1 40 2451 40 6.95648e+06 390843 706193. 2443.58 2.28 0.208193 0.181318 26914 176310 -1 1989 23 1600 2424 223141 68263 3.89406 3.89406 -135.843 -3.89406 0 0 926341. 3205.33 0.04 0.12 0.15 -1 -1 0.04 0.0334966 0.029147 79 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_022.v common 4.94 vpr 63.62 MiB -1 -1 0.25 18268 1 0.03 -1 -1 30280 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65148 32 32 372 300 1 200 80 17 17 289 -1 unnamed_device 24.6 MiB 1.09 929 10228 2968 5474 1786 63.6 MiB 0.10 0.00 4.43786 -126.086 -4.43786 4.43786 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 23.8 MiB 0.10 456 10459 4198 5595 666 63.1 MiB 0.07 0.00 2.13126 -69.3153 -2.13126 2.13126 0.31 0.00042468 0.000394535 0.0302253 0.0280834 -1 -1 -1 -1 36 1204 23 6.95648e+06 144757 648988. 2245.63 0.91 0.11542 0.100517 26050 158493 -1 915 21 632 749 65534 16835 2.05118 2.05118 -75.2428 -2.05118 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0176879 0.0153969 43 3 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_026.v common 3.91 vpr 63.34 MiB -1 -1 0.23 18124 1 0.03 -1 -1 30152 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 32 32 300 245 1 159 83 17 17 289 -1 unnamed_device 24.2 MiB 0.46 705 11063 3344 5374 2345 63.3 MiB 0.09 0.00 4.42909 -119.059 -4.42909 4.42909 0.34 0.000632235 0.000588523 0.0414738 0.0385764 -1 -1 -1 -1 42 1926 27 6.95648e+06 275038 744469. 2576.02 1.35 0.176041 0.153466 27202 183097 -1 1512 20 1112 1881 126839 32424 3.69636 3.69636 -116.75 -3.69636 0 0 949917. 3286.91 0.04 0.07 0.15 -1 -1 0.04 0.0258126 0.0225697 67 24 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_027.v common 3.35 vpr 63.43 MiB -1 -1 0.22 17828 1 0.03 -1 -1 30316 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 24.2 MiB 0.18 1111 14983 4654 8769 1560 63.4 MiB 0.12 0.00 2.9965 -108.481 -2.9965 2.9965 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65108 30 32 262 227 1 134 84 17 17 289 -1 unnamed_device 24.0 MiB 0.24 598 12894 4167 6970 1757 63.6 MiB 0.10 0.00 3.17414 -94.0877 -3.17414 3.17414 0.34 0.000573241 0.00052658 0.0418466 0.0387546 -1 -1 -1 -1 38 1729 50 6.95648e+06 318465 678818. 2348.85 1.28 0.180547 0.156592 26626 170182 -1 1167 20 965 1502 93858 23736 2.85952 2.85952 -93.9328 -2.85952 0 0 902133. 3121.57 0.04 0.06 0.14 -1 -1 0.04 0.0228669 0.0198687 60 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_031.v common 3.67 vpr 63.50 MiB -1 -1 0.17 18060 1 0.03 -1 -1 30096 -1 -1 21 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 28 32 260 223 1 135 81 17 17 289 -1 unnamed_device 23.9 MiB 0.20 526 9881 3467 4910 1504 63.5 MiB 0.08 0.00 2.9041 -89.8524 -2.9041 2.9041 0.35 0.000561846 0.000519378 0.0338285 0.0314291 -1 -1 -1 -1 44 1510 25 6.95648e+06 303989 787024. 2723.27 1.54 0.153363 0.133271 27778 195446 -1 1252 20 976 1638 120916 31896 3.14012 3.14012 -100.347 -3.14012 0 0 997811. 3452.63 0.04 0.06 0.16 -1 -1 0.04 0.0226749 0.0197469 60 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_032.v common 3.36 vpr 63.54 MiB -1 -1 0.20 17740 1 0.02 -1 -1 30304 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65060 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 23.9 MiB 0.12 872 7412 1986 4690 736 63.5 MiB 0.07 0.00 3.33963 -114.641 -3.33963 3.33963 0.34 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/home/elgamma8/research/release/vtr-verilog-to-routing 64840 32 32 336 268 1 169 89 17 17 289 -1 unnamed_device 24.4 MiB 0.98 769 14543 4279 7650 2614 63.3 MiB 0.13 0.00 4.37605 -128.976 -4.37605 4.37605 0.33 0.00068609 0.000637719 0.0529336 0.0491554 -1 -1 -1 -1 36 2640 45 6.95648e+06 361892 648988. 2245.63 1.95 0.220043 0.191748 26050 158493 -1 1899 19 1368 2103 168161 39340 4.52236 4.52236 -147.419 -4.52236 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0268261 0.0234869 75 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_062.v common 3.23 vpr 63.44 MiB -1 -1 0.21 17720 1 0.03 -1 -1 30332 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64964 32 32 231 199 1 136 81 17 17 289 -1 unnamed_device 23.9 MiB 0.17 862 10581 3669 5472 1440 63.4 MiB 0.08 0.00 2.966 -103.091 -2.966 2.966 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 30 32 278 235 1 141 87 17 17 289 -1 unnamed_device 24.3 MiB 0.57 775 12567 4624 6004 1939 63.8 MiB 0.10 0.00 3.23198 -106.153 -3.23198 3.23198 0.35 0.000590718 0.000549282 0.0409618 0.0381017 -1 -1 -1 -1 36 1945 49 6.95648e+06 361892 648988. 2245.63 1.58 0.19865 0.172724 26050 158493 -1 1651 24 1219 1928 159003 35682 3.51472 3.51472 -122.539 -3.51472 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0269613 0.0233639 64 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_066.v common 5.16 vpr 63.41 MiB -1 -1 0.25 18380 1 0.03 -1 -1 30368 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64936 29 32 355 287 1 191 80 17 17 289 -1 unnamed_device 24.5 MiB 1.05 862 13840 5371 6156 2313 63.4 MiB 0.13 0.00 3.49789 -109.385 -3.49789 3.49789 0.33 0.000692113 0.000642977 0.05874 0.0545889 -1 -1 -1 -1 42 2967 32 6.95648e+06 275038 744469. 2576.02 1.93 0.213693 0.18699 27202 183097 -1 2258 20 1883 2806 223583 51789 3.35977 3.35977 -120.027 -3.35977 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0279475 0.0244354 81 62 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_067.v common 3.65 vpr 63.48 MiB -1 -1 0.25 18396 1 0.03 -1 -1 30320 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 358 289 1 171 83 17 17 289 -1 unnamed_device 24.5 MiB 0.52 803 13763 3951 8222 1590 63.5 MiB 0.13 0.00 4.16158 -131.727 -4.16158 4.16158 0.33 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/home/elgamma8/research/release/vtr-verilog-to-routing 65264 32 32 299 247 1 182 82 17 17 289 -1 unnamed_device 24.1 MiB 0.41 783 13254 4112 6373 2769 63.7 MiB 0.11 0.00 3.72729 -109.674 -3.72729 3.72729 0.33 0.000625596 0.000581673 0.0488825 0.0454632 -1 -1 -1 -1 44 2136 24 6.99608e+06 264882 787024. 2723.27 1.30 0.177479 0.155179 27778 195446 -1 1563 22 1258 1664 102584 26082 4.32016 4.32016 -116.534 -4.32016 0 0 997811. 3452.63 0.04 0.06 0.15 -1 -1 0.04 0.0269732 0.0235055 75 29 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_004.v common 3.90 vpr 63.93 MiB -1 -1 0.24 18404 1 0.03 -1 -1 30412 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65460 29 32 308 248 1 182 80 17 17 289 -1 unnamed_device 24.2 MiB 0.33 873 14700 6300 7739 661 63.9 MiB 0.13 0.00 4.12218 -119.396 -4.12218 4.12218 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/home/elgamma8/research/release/vtr-verilog-to-routing 65220 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 24.4 MiB 0.17 727 10140 3383 5019 1738 63.7 MiB 0.08 0.00 2.73675 -88.7663 -2.73675 2.73675 0.33 0.000595211 0.00055369 0.0323175 0.030008 -1 -1 -1 -1 38 2221 27 6.99608e+06 397324 678818. 2348.85 1.89 0.157817 0.136976 26626 170182 -1 1662 18 1028 1750 116894 29647 3.01977 3.01977 -98.9875 -3.01977 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0219675 0.0191938 69 4 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_009.v common 4.50 vpr 63.79 MiB -1 -1 0.25 18444 1 0.03 -1 -1 30152 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65320 31 32 317 271 1 204 81 17 17 289 -1 unnamed_device 24.0 MiB 0.38 980 13556 5192 6525 1839 63.8 MiB 0.12 0.00 3.3916 -120.616 -3.3916 3.3916 0.33 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/home/elgamma8/research/release/vtr-verilog-to-routing 65556 32 32 344 272 1 201 82 17 17 289 -1 unnamed_device 24.4 MiB 0.42 989 13788 5751 7551 486 64.0 MiB 0.13 0.00 3.85182 -127.119 -3.85182 3.85182 0.33 0.000695996 0.000645706 0.056467 0.0525052 -1 -1 -1 -1 40 2714 27 6.99608e+06 264882 706193. 2443.58 8.55 0.342056 0.295528 26914 176310 -1 2180 20 1618 2438 198461 44961 3.37586 3.37586 -121.862 -3.37586 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0280737 0.0245708 85 34 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_014.v common 4.89 vpr 63.34 MiB -1 -1 0.23 18476 1 0.03 -1 -1 30296 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 32 32 363 295 1 228 85 17 17 289 -1 unnamed_device 24.3 MiB 0.49 1022 13849 4401 6534 2914 63.3 MiB 0.13 0.00 4.71142 -142.574 -4.71142 4.71142 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 23.9 MiB 0.21 869 10835 2990 6954 891 63.4 MiB 0.09 0.00 3.30043 -111.689 -3.30043 3.30043 0.33 0.000571124 0.000531379 0.0397191 0.036997 -1 -1 -1 -1 38 1933 22 6.99608e+06 191304 678818. 2348.85 1.28 0.154408 0.134664 26626 170182 -1 1681 20 1206 1902 143421 30990 3.03062 3.03062 -114.764 -3.03062 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0227464 0.0198249 59 3 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_033.v common 3.57 vpr 63.41 MiB -1 -1 0.14 18096 1 0.03 -1 -1 30152 -1 -1 15 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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30084 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65440 31 32 340 275 1 195 82 17 17 289 -1 unnamed_device 24.4 MiB 0.61 919 7736 2635 4162 939 63.9 MiB 0.08 0.00 5.0765 -140.835 -5.0765 5.0765 0.34 0.000683595 0.000635788 0.0323016 0.0300513 -1 -1 -1 -1 40 2827 34 6.99608e+06 279598 706193. 2443.58 2.01 0.183624 0.159375 26914 176310 -1 1996 18 1403 2053 154708 36864 4.34151 4.34151 -139.438 -4.34151 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0256852 0.022549 87 47 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_083.v common 4.34 vpr 64.08 MiB -1 -1 0.26 18548 1 0.03 -1 -1 30088 -1 -1 24 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65648 32 32 373 302 1 234 85 17 17 289 -1 unnamed_device 24.4 MiB 0.27 1243 16081 5953 7939 2189 64.1 MiB 0.16 0.00 4.8168 -157 -4.8168 4.8168 0.26 0.000731852 0.000679799 0.0658794 0.0611482 -1 -1 -1 -1 40 2915 24 6.99608e+06 309029 706193. 2443.58 1.51 0.221118 0.194285 26914 176310 -1 2455 21 1930 2730 203339 43779 5.01301 5.01301 -164.294 -5.01301 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.030157 0.026347 99 65 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_088.v common 5.66 vpr 64.08 MiB -1 -1 0.24 18396 1 0.03 -1 -1 30260 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 386 307 1 240 85 17 17 289 -1 unnamed_device 24.5 MiB 0.41 1172 14779 4944 7940 1895 64.2 MiB 0.14 0.00 3.49383 -123.038 -3.49383 3.49383 0.35 0.000744675 0.000690682 0.0623874 0.0579082 -1 -1 -1 -1 38 3062 42 6.99608e+06 309029 678818. 2348.85 7.53 0.401185 0.347255 26626 170182 -1 2503 21 2030 2756 207605 45774 3.22392 3.22392 -130.363 -3.22392 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0313101 0.0274444 101 62 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 3.37 vpr 63.54 MiB -1 -1 0.22 18176 1 0.03 -1 -1 30312 -1 -1 17 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 29 32 269 229 1 166 78 17 17 289 -1 unnamed_device 23.9 MiB 0.27 653 11698 4829 5917 952 63.5 MiB 0.10 0.00 3.87612 -110.458 -3.87612 3.87612 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30324 -1 -1 16 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 29 32 262 224 1 162 77 17 17 289 -1 unnamed_device 23.8 MiB 0.36 695 10346 4286 5606 454 63.4 MiB 0.09 0.00 3.75967 -107.452 -3.75967 3.75967 0.33 0.000564484 0.000525149 0.0379166 0.0352817 -1 -1 -1 -1 42 2064 29 6.99608e+06 235451 744469. 2576.02 1.18 0.155295 0.134907 27202 183097 -1 1555 21 1113 1458 123164 29262 3.29971 3.29971 -107.37 -3.29971 0 0 949917. 3286.91 0.04 0.06 0.15 -1 -1 0.04 0.0233802 0.0203302 67 31 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_108.v common 3.91 vpr 63.50 MiB -1 -1 0.23 18172 1 0.03 -1 -1 30120 -1 -1 15 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65044 32 32 376 307 1 230 83 17 17 289 -1 unnamed_device 24.4 MiB 0.51 1070 13583 5650 7491 442 63.5 MiB 0.13 0.00 4.04452 -130.09 -4.04452 4.04452 0.34 0.000728734 0.000675996 0.0578889 0.0536675 -1 -1 -1 -1 40 3557 32 6.99608e+06 279598 706193. 2443.58 3.62 0.22235 0.194456 26914 176310 -1 2744 21 2050 3040 252988 64010 4.43451 4.43451 -145.309 -4.43451 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0305214 0.0266633 100 72 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_128.v common 4.47 vpr 63.53 MiB -1 -1 0.26 18432 1 0.03 -1 -1 30404 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65052 31 32 409 331 1 257 87 17 17 289 -1 unnamed_device 24.6 MiB 0.47 1269 16023 5206 8626 2191 63.5 MiB 0.16 0.00 4.27167 -145.144 -4.27167 4.27167 0.34 0.000768802 0.000713617 0.0673126 0.0624982 -1 -1 -1 -1 38 3325 48 6.99608e+06 353176 678818. 2348.85 1.74 0.259733 0.227383 26626 170182 -1 2713 23 2420 3261 279104 64299 3.9869 3.9869 -150.259 -3.9869 0 0 902133. 3121.57 0.04 0.11 0.14 -1 -1 0.04 0.035037 0.0305796 115 90 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml mult_001.v common 5.45 vpr 63.17 MiB -1 -1 0.37 18628 14 0.27 -1 -1 32696 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 32 32 277 309 1 198 86 17 17 289 -1 unnamed_device 23.9 MiB 1.02 1216 8402 2148 5464 790 63.2 MiB 0.10 0.00 8.60211 -177.555 -8.60211 8.60211 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 317 271 1 175 83 17 17 289 -1 unnamed_device 24.0 MiB 1.95 910 8723 2060 6322 341 63.1 MiB 0.09 0.00 3.31917 -111.486 -3.31917 3.31917 0.34 0.00063441 0.000590038 0.0329474 0.0306471 -1 -1 -1 -1 32 2150 19 6.87369e+06 279477 586450. 2029.24 0.58 0.106092 0.093061 25474 144626 -1 1748 20 1043 1565 98545 24803 2.91151 2.91151 -112.578 -2.91151 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0244429 0.0212104 110 64 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_010.v common 6.12 vpr 63.35 MiB -1 -1 0.22 18120 1 0.03 -1 -1 30076 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 32 32 298 248 1 162 81 17 17 289 -1 unnamed_device 23.6 MiB 3.62 974 4631 910 3488 233 63.4 MiB 0.06 0.00 3.98344 -131.884 -3.98344 3.98344 0.33 0.000626678 0.000583326 0.0185195 0.0172494 -1 -1 -1 -1 30 2081 18 6.87369e+06 237555 556674. 1926.21 0.54 0.0883308 0.0768845 25186 138497 -1 1827 21 1179 2019 124096 30001 2.82686 2.82686 -118.966 -2.82686 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0253455 0.0219646 107 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_011.v common 5.19 vpr 63.25 MiB -1 -1 0.25 18396 1 0.03 -1 -1 30308 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 30 32 303 262 1 148 80 17 17 289 -1 unnamed_device 23.6 MiB 2.64 812 9368 2251 6434 683 63.2 MiB 0.10 0.00 3.87398 -114.403 -3.87398 3.87398 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 23.9 MiB 2.12 926 9599 2091 6833 675 63.1 MiB 0.11 0.00 4.83358 -141.45 -4.83358 4.83358 0.33 0.000713803 0.000663884 0.0340711 0.0316564 -1 -1 -1 -1 30 2718 27 6.87369e+06 433189 556674. 1926.21 0.65 0.123589 0.10815 25186 138497 -1 1936 20 1247 1954 117467 30151 4.17226 4.17226 -144.094 -4.17226 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.014747 0.0130134 133 61 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_015.v common 4.22 vpr 63.17 MiB -1 -1 0.23 18132 1 0.03 -1 -1 30400 -1 -1 21 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 29 32 248 215 1 142 82 17 17 289 -1 unnamed_device 23.9 MiB 1.70 711 8982 2096 6475 411 63.2 MiB 0.08 0.00 3.07868 -92.9683 -3.07868 3.07868 0.33 0.000544701 0.000507131 0.0291861 0.0271418 -1 -1 -1 -1 30 1671 24 6.87369e+06 293451 556674. 1926.21 0.54 0.09513 0.0832085 25186 138497 -1 1338 20 791 1267 69154 17413 2.61566 2.61566 -91.2171 -2.61566 0 0 706193. 2443.58 0.04 0.06 0.11 -1 -1 0.04 0.0269583 0.0234237 94 27 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 5.24 vpr 63.32 MiB -1 -1 0.24 18324 1 0.03 -1 -1 30280 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 370 297 1 191 88 17 17 289 -1 unnamed_device 24.0 MiB 1.91 1084 8668 1982 6147 539 63.3 MiB 0.10 0.00 3.90567 -127.707 -3.90567 3.90567 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 23.7 MiB 0.66 689 12139 3691 7050 1398 63.0 MiB 0.09 0.00 2.38778 -83.5564 -2.38778 2.38778 0.34 0.000495747 0.000461876 0.038516 0.0358607 -1 -1 -1 -1 32 1442 23 6.87369e+06 209608 586450. 2029.24 0.50 0.0985935 0.0870204 25474 144626 -1 1219 18 585 811 57943 14080 2.01382 2.01382 -84.6315 -2.01382 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0179977 0.0155952 71 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 5.39 vpr 63.12 MiB -1 -1 0.24 18340 1 0.03 -1 -1 30384 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 291 243 1 178 84 17 17 289 -1 unnamed_device 24.1 MiB 2.65 926 13626 5074 6419 2133 63.1 MiB 0.14 0.00 4.99433 -147.969 -4.99433 4.99433 0.33 0.00061624 0.000572644 0.0477352 0.04437 -1 -1 -1 -1 32 2269 22 6.87369e+06 293451 586450. 2029.24 0.61 0.120075 0.105959 25474 144626 -1 1823 19 1094 1607 107959 26850 3.64821 3.64821 -133.065 -3.64821 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0229829 0.0199895 114 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 3.77 vpr 63.66 MiB -1 -1 0.24 18488 1 0.03 -1 -1 30524 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65192 32 32 342 271 1 181 99 17 17 289 -1 unnamed_device 23.9 MiB 0.98 1087 13779 3849 8710 1220 63.7 MiB 0.14 0.00 4.23509 -137.221 -4.23509 4.23509 0.41 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744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0238439 0.020874 138 62 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_023.v common 4.12 vpr 62.94 MiB -1 -1 0.22 18228 1 0.02 -1 -1 30548 -1 -1 17 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64448 26 32 190 182 1 108 75 17 17 289 -1 unnamed_device 23.6 MiB 1.58 480 8133 3281 4323 529 62.9 MiB 0.06 0.00 2.38158 -69.4238 -2.38158 2.38158 0.34 0.00047137 0.000434655 0.0191877 0.0175956 -1 -1 -1 -1 28 1220 24 6.87369e+06 237555 531479. 1839.03 0.52 0.0720773 0.0625468 24610 126494 -1 1036 17 707 988 65067 17945 2.18312 2.18312 -75.9258 -2.18312 0 0 648988. 2245.63 0.03 0.04 0.10 -1 -1 0.03 0.014802 0.0128753 67 30 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 3.76 vpr 63.39 MiB -1 -1 0.22 17868 1 0.03 -1 -1 30344 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 285 227 1 169 87 17 17 289 -1 unnamed_device 23.8 MiB 1.15 1002 13719 4614 6837 2268 63.4 MiB 0.14 0.00 4.57022 -130.066 -4.57022 4.57022 0.33 0.00061934 0.000575759 0.0461905 0.0429273 -1 -1 -1 -1 30 2201 25 6.87369e+06 321398 556674. 1926.21 0.60 0.122115 0.10779 25186 138497 -1 1821 21 1157 2162 119285 29514 3.7041 3.7041 -123.476 -3.7041 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0254677 0.0220817 119 3 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 2.97 vpr 63.02 MiB -1 -1 0.12 17552 1 0.02 -1 -1 30008 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 23.8 MiB 0.62 529 9036 3698 5030 308 63.0 MiB 0.07 0.00 2.64533 -79.7813 -2.64533 2.64533 0.34 0.000423617 0.000392859 0.0254041 0.0235785 -1 -1 -1 -1 28 1296 30 6.87369e+06 167686 531479. 1839.03 0.56 0.0819974 0.0717561 24610 126494 -1 1030 14 522 612 45566 12360 2.19737 2.19737 -79.5748 -2.19737 0 0 648988. 2245.63 0.03 0.05 0.10 -1 -1 0.03 0.0206278 0.0179992 65 3 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 3.58 vpr 63.64 MiB -1 -1 0.23 18288 1 0.03 -1 -1 30140 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65172 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 24.0 MiB 0.98 1049 16069 4575 9607 1887 63.6 MiB 0.15 0.00 4.58208 -129.699 -4.58208 4.58208 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 284 241 1 148 82 17 17 289 -1 unnamed_device 23.7 MiB 0.94 856 12720 4032 6930 1758 63.3 MiB 0.12 0.00 3.07458 -105.313 -3.07458 3.07458 0.33 0.000608 0.000559447 0.0450373 0.0417759 -1 -1 -1 -1 32 1770 20 6.87369e+06 251529 586450. 2029.24 0.53 0.114315 0.100881 25474 144626 -1 1498 21 757 1288 84508 20239 2.64866 2.64866 -104.259 -2.64866 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0130009 0.0114168 101 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_030.v common 3.53 vpr 63.14 MiB -1 -1 0.14 18236 1 0.03 -1 -1 30272 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 30 32 262 227 1 138 87 17 17 289 -1 unnamed_device 23.6 MiB 1.11 850 14103 4319 8139 1645 63.1 MiB 0.12 0.00 3.14772 -102.363 -3.14772 3.14772 0.33 0.00056828 0.000529209 0.0435607 0.0405281 -1 -1 -1 -1 32 1755 31 6.87369e+06 349346 586450. 2029.24 0.57 0.118019 0.103831 25474 144626 -1 1498 19 881 1432 93880 22924 2.79396 2.79396 -97.0612 -2.79396 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0210251 0.018223 97 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_031.v common 3.40 vpr 63.08 MiB -1 -1 0.16 18000 1 0.02 -1 -1 30160 -1 -1 24 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64596 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 23.5 MiB 0.98 762 14175 5132 6824 2219 63.1 MiB 0.12 0.00 3.46791 -98.5079 -3.46791 3.46791 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64712 29 32 291 250 1 154 86 17 17 289 -1 unnamed_device 23.6 MiB 2.42 855 9536 2217 6358 961 63.2 MiB 0.09 0.00 3.08002 -99.9202 -3.08002 3.08002 0.34 0.000605347 0.000562439 0.0322847 0.0300207 -1 -1 -1 -1 32 1836 20 6.87369e+06 349346 586450. 2029.24 0.54 0.101683 0.0890847 25474 144626 -1 1618 17 896 1401 87699 22004 2.36147 2.36147 -96.2223 -2.36147 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0208019 0.0180997 105 54 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_035.v common 5.60 vpr 63.82 MiB -1 -1 0.22 18412 1 0.04 -1 -1 30340 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 32 32 367 282 1 201 104 17 17 289 -1 unnamed_device 24.2 MiB 2.99 1201 11572 2628 7875 1069 63.8 MiB 0.12 0.00 4.28409 -125.895 -4.28409 4.28409 0.33 0.000745621 0.000691639 0.0376247 0.0349383 -1 -1 -1 -1 32 2850 21 6.87369e+06 558954 586450. 2029.24 0.60 0.123608 0.108597 25474 144626 -1 2283 22 1202 2387 140467 34356 3.5931 3.5931 -122.354 -3.5931 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0309075 0.0268465 156 29 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_036.v common 5.65 vpr 63.77 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30256 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 32 32 391 311 1 194 104 17 17 289 -1 unnamed_device 24.1 MiB 2.85 1115 17428 4398 11199 1831 63.8 MiB 0.18 0.00 4.01296 -135.521 -4.01296 4.01296 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29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 31 32 377 302 1 237 92 17 17 289 -1 unnamed_device 24.3 MiB 3.21 1226 11477 3074 7440 963 63.3 MiB 0.14 0.00 5.94301 -174.677 -5.94301 5.94301 0.33 0.000740882 0.00068947 0.0435873 0.0404978 -1 -1 -1 -1 32 3381 27 6.87369e+06 405241 586450. 2029.24 0.86 0.135821 0.119293 25474 144626 -1 2594 21 2065 3065 259228 59072 4.91379 4.91379 -168.168 -4.91379 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.030074 0.0261518 156 64 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_040.v common 10.36 vpr 63.25 MiB -1 -1 0.13 18256 1 0.03 -1 -1 30432 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64772 31 32 383 305 1 212 91 17 17 289 -1 unnamed_device 24.2 MiB 3.73 1111 18247 5857 8950 3440 63.3 MiB 0.17 0.00 5.17369 -157.317 -5.17369 5.17369 0.34 0.000735997 0.000683017 0.0685617 0.0636389 -1 -1 -1 -1 32 3441 45 6.87369e+06 391268 586450. 2029.24 4.57 0.366723 0.317795 25474 144626 -1 2256 24 1622 2535 185379 47271 4.9157 4.9157 -166.109 -4.9157 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0333739 0.0289693 151 64 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_041.v common 5.01 vpr 63.19 MiB -1 -1 0.19 18320 1 0.03 -1 -1 30352 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 31 32 352 285 1 186 91 17 17 289 -1 unnamed_device 24.0 MiB 2.47 1131 11311 2943 7349 1019 63.2 MiB 0.13 0.00 4.13563 -130.877 -4.13563 4.13563 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22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 387 315 1 194 86 17 17 289 -1 unnamed_device 24.2 MiB 2.41 1107 13883 4421 7374 2088 63.3 MiB 0.15 0.00 4.4264 -134.375 -4.4264 4.4264 0.34 0.00074745 0.000694485 0.0572042 0.0531062 -1 -1 -1 -1 32 2766 23 6.87369e+06 307425 586450. 2029.24 0.63 0.14684 0.129797 25474 144626 -1 2283 20 1421 2543 162506 40189 3.63536 3.63536 -132.707 -3.63536 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0293206 0.0255442 134 77 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_055.v common 3.49 vpr 63.16 MiB -1 -1 0.22 18112 1 0.03 -1 -1 30340 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 251 219 1 141 87 17 17 289 -1 unnamed_device 23.7 MiB 0.88 781 8151 1829 5687 635 63.2 MiB 0.08 0.00 3.42581 -102.974 -3.42581 3.42581 0.41 0.000559902 0.000521562 0.0254085 0.0236473 -1 -1 -1 -1 28 1904 23 6.87369e+06 321398 531479. 1839.03 0.53 0.0929223 0.0810831 24610 126494 -1 1688 22 1081 1762 117647 29623 2.79596 2.79596 -101.105 -2.79596 0 0 648988. 2245.63 0.03 0.06 0.10 -1 -1 0.03 0.0233409 0.0201884 93 23 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_056.v common 4.41 vpr 63.22 MiB -1 -1 0.25 18552 1 0.03 -1 -1 30108 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 341 285 1 188 84 17 17 289 -1 unnamed_device 24.0 MiB 1.74 910 13260 3607 7806 1847 63.2 MiB 0.14 0.00 3.77904 -129.086 -3.77904 3.77904 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/home/elgamma8/research/release/vtr-verilog-to-routing 64956 32 32 431 332 1 239 91 17 17 289 -1 unnamed_device 24.5 MiB 4.02 1420 13147 3569 8315 1263 63.4 MiB 0.16 0.00 5.92629 -174.407 -5.92629 5.92629 0.34 0.000833342 0.00077516 0.0564343 0.0524045 -1 -1 -1 -1 32 3147 27 6.87369e+06 377294 586450. 2029.24 0.69 0.163689 0.144051 25474 144626 -1 2602 19 1701 2677 174677 41715 4.7336 4.7336 -161.132 -4.7336 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0308763 0.0269051 166 65 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_061.v common 5.42 vpr 63.79 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30364 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65316 32 32 336 268 1 182 99 17 17 289 -1 unnamed_device 24.0 MiB 2.76 1022 11043 2817 7461 765 63.8 MiB 0.11 0.00 4.68232 -141.336 -4.68232 4.68232 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64592 32 32 335 282 1 189 84 17 17 289 -1 unnamed_device 23.9 MiB 2.01 1004 6855 1530 4961 364 63.1 MiB 0.08 0.00 3.6946 -124.308 -3.6946 3.6946 0.33 0.000666465 0.000620289 0.0269554 0.0250659 -1 -1 -1 -1 28 2476 23 6.87369e+06 279477 531479. 1839.03 0.58 0.106325 0.0927977 24610 126494 -1 2194 23 1488 2178 170330 42033 3.28611 3.28611 -130.137 -3.28611 0 0 648988. 2245.63 0.03 0.08 0.12 -1 -1 0.03 0.0285581 0.0246782 118 65 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_075.v common 3.51 vpr 63.07 MiB -1 -1 0.24 17948 1 0.03 -1 -1 30292 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 31 32 293 230 1 175 96 17 17 289 -1 unnamed_device 24.0 MiB 0.92 1091 9075 2015 6280 780 63.1 MiB 0.10 0.00 4.61548 -132.875 -4.61548 4.61548 0.33 0.000631977 0.000587553 0.028804 0.0267387 -1 -1 -1 -1 26 2616 23 6.87369e+06 461137 503264. 1741.40 0.69 0.105235 0.0920603 24322 120374 -1 2293 21 1418 2488 166028 39907 3.8604 3.8604 -130.723 -3.8604 0 0 618332. 2139.56 0.02 0.04 0.07 -1 -1 0.02 0.0137315 0.012053 130 4 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_076.v common 5.58 vpr 63.24 MiB -1 -1 0.15 18428 1 0.03 -1 -1 30448 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 32 32 350 275 1 214 89 17 17 289 -1 unnamed_device 24.3 MiB 2.94 1200 15731 4693 8579 2459 63.2 MiB 0.17 0.00 4.80258 -153.363 -4.80258 4.80258 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64748 30 32 272 232 1 151 80 17 17 289 -1 unnamed_device 23.6 MiB 2.20 813 9024 2370 5899 755 63.2 MiB 0.10 0.00 3.89188 -117.262 -3.89188 3.89188 0.33 0.000584829 0.000544928 0.0324753 0.0302551 -1 -1 -1 -1 32 1912 21 6.87369e+06 251529 586450. 2029.24 0.55 0.100521 0.0882835 25474 144626 -1 1652 20 1057 1880 121709 29083 2.97696 2.97696 -107.258 -2.97696 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226212 0.0196254 99 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_080.v common 5.57 vpr 63.89 MiB -1 -1 0.14 18284 1 0.02 -1 -1 30372 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65016 29 32 378 310 1 179 90 17 17 289 -1 unnamed_device 24.2 MiB 2.28 945 16170 4095 11127 948 63.5 MiB 0.16 0.00 4.12999 -122.875 -4.12999 4.12999 0.33 0.000715356 0.000664292 0.0600459 0.055713 -1 -1 -1 -1 32 2398 22 6.87369e+06 405241 586450. 2029.24 0.61 0.145064 0.128358 25474 144626 -1 1959 21 1386 2247 136731 34828 3.12181 3.12181 -115.774 -3.12181 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0291387 0.025244 132 85 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 3.69 vpr 63.22 MiB -1 -1 0.21 17864 1 0.03 -1 -1 30328 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 23.6 MiB 1.07 892 12542 3412 7235 1895 63.2 MiB 0.11 0.00 3.98264 -119.291 -3.98264 3.98264 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65128 32 32 269 231 1 170 82 17 17 289 -1 unnamed_device 23.9 MiB 2.13 994 9694 2678 5995 1021 63.6 MiB 0.10 0.00 4.37292 -124.998 -4.37292 4.37292 0.33 0.00058825 0.000548397 0.0336292 0.0313019 -1 -1 -1 -1 26 2325 22 6.87369e+06 251529 503264. 1741.40 0.62 0.103077 0.090504 24322 120374 -1 2098 22 1212 1576 117648 28606 3.4928 3.4928 -124.305 -3.4928 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0245323 0.0212581 103 29 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_090.v common 3.70 vpr 63.16 MiB -1 -1 0.23 17880 1 0.03 -1 -1 30368 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64680 31 32 245 205 1 153 84 17 17 289 -1 unnamed_device 23.7 MiB 1.09 879 14358 4211 8419 1728 63.2 MiB 0.13 0.00 3.81898 -115.032 -3.81898 3.81898 0.33 0.000551096 0.000512803 0.0451184 0.0419713 -1 -1 -1 -1 32 1927 21 6.87369e+06 293451 586450. 2029.24 0.58 0.11685 0.103169 25474 144626 -1 1705 21 1147 1895 134417 30219 2.80196 2.80196 -107.148 -2.80196 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226517 0.0196196 100 4 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_091.v common 5.14 vpr 63.21 MiB -1 -1 0.24 18416 1 0.03 -1 -1 30464 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 24.0 MiB 2.49 1167 13738 4717 6121 2900 63.2 MiB 0.14 0.00 4.82535 -151.45 -4.82535 4.82535 0.34 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/home/elgamma8/research/release/vtr-verilog-to-routing 64720 27 32 255 219 1 139 83 17 17 289 -1 unnamed_device 23.6 MiB 0.98 659 7643 1786 5184 673 63.2 MiB 0.07 0.00 3.59463 -97.3218 -3.59463 3.59463 0.34 0.000551197 0.000513497 0.0250754 0.0233186 -1 -1 -1 -1 30 1508 21 6.87369e+06 335372 556674. 1926.21 0.53 0.0893672 0.0779488 25186 138497 -1 1307 22 912 1404 85222 19958 2.71066 2.71066 -92.8097 -2.71066 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0229535 0.0198213 97 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_096.v common 5.57 vpr 63.50 MiB -1 -1 0.26 18408 1 0.03 -1 -1 30300 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65020 32 32 421 327 1 233 90 17 17 289 -1 unnamed_device 24.5 MiB 2.67 1401 16170 4964 9023 2183 63.5 MiB 0.19 0.00 4.57338 -144.339 -4.57338 4.57338 0.34 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 29 32 269 229 1 150 81 17 17 289 -1 unnamed_device 23.5 MiB 1.73 676 13381 4841 5719 2821 63.2 MiB 0.12 0.00 3.95844 -115.993 -3.95844 3.95844 0.33 0.000576391 0.00053603 0.0458306 0.0426133 -1 -1 -1 -1 32 1602 21 6.87369e+06 279477 586450. 2029.24 0.54 0.11245 0.0993597 25474 144626 -1 1303 20 1078 1620 101124 24300 3.02726 3.02726 -105.477 -3.02726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226321 0.0196502 101 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 4.33 vpr 63.11 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30284 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64624 32 32 310 266 1 175 84 17 17 289 -1 unnamed_device 24.0 MiB 1.51 1025 15456 4644 9539 1273 63.1 MiB 0.15 0.00 3.98516 -120.978 -3.98516 3.98516 0.33 0.000629119 0.000584837 0.0550716 0.051179 -1 -1 -1 -1 26 2517 27 6.87369e+06 279477 503264. 1741.40 0.77 0.135191 0.119354 24322 120374 -1 2108 22 1426 1967 170507 40619 3.43941 3.43941 -126.369 -3.43941 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0266223 0.0230652 108 58 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 4.68 vpr 63.76 MiB -1 -1 0.15 18476 1 0.03 -1 -1 30344 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65292 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 24.0 MiB 1.43 987 18428 5110 10243 3075 63.8 MiB 0.17 0.00 4.59612 -128.416 -4.59612 4.59612 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65392 31 32 373 300 1 185 101 17 17 289 -1 unnamed_device 24.3 MiB 2.52 996 8326 1655 6069 602 63.9 MiB 0.09 0.00 3.95528 -124.82 -3.95528 3.95528 0.33 0.00073019 0.000672729 0.028011 0.0259846 -1 -1 -1 -1 30 2187 19 6.87369e+06 531006 556674. 1926.21 0.58 0.110267 0.0962367 25186 138497 -1 1812 19 1272 2135 103364 26073 2.96596 2.96596 -116.595 -2.96596 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0270136 0.0235073 142 64 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 4.45 vpr 63.19 MiB -1 -1 0.23 18184 1 0.03 -1 -1 30328 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 31 32 265 230 1 169 81 17 17 289 -1 unnamed_device 23.5 MiB 1.98 964 7606 1989 5205 412 63.2 MiB 0.08 0.00 3.71466 -116.831 -3.71466 3.71466 0.33 0.00058092 0.000541652 0.026736 0.0248919 -1 -1 -1 -1 30 2104 20 6.87369e+06 251529 556674. 1926.21 0.54 0.0928595 0.0811791 25186 138497 -1 1736 21 950 1365 79050 19847 3.06461 3.06461 -112.199 -3.06461 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0278341 0.0244082 101 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 5.45 vpr 63.81 MiB -1 -1 0.25 18348 1 0.03 -1 -1 29996 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65340 32 32 349 286 1 177 96 17 17 289 -1 unnamed_device 24.1 MiB 2.52 1048 13455 3508 9157 790 63.8 MiB 0.13 0.00 3.8199 -117.926 -3.8199 3.8199 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 24.0 MiB 1.70 868 9623 2653 6092 878 63.0 MiB 0.10 0.00 4.12463 -125.158 -4.12463 4.12463 0.29 0.000611296 0.000568942 0.0346504 0.0322298 -1 -1 -1 -1 28 2577 24 6.87369e+06 265503 531479. 1839.03 0.64 0.108794 0.0953846 24610 126494 -1 2089 21 1614 2365 175909 43157 3.21861 3.21861 -122.623 -3.21861 0 0 648988. 2245.63 0.03 0.08 0.07 -1 -1 0.03 0.0247676 0.021436 110 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 4.68 vpr 63.23 MiB -1 -1 0.12 18288 1 0.03 -1 -1 30172 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 32 32 318 257 1 196 86 17 17 289 -1 unnamed_device 24.1 MiB 2.03 1052 5567 1101 4155 311 63.2 MiB 0.07 0.00 4.84388 -137.106 -4.84388 4.84388 0.33 0.000657365 0.000611273 0.0214686 0.0199696 -1 -1 -1 -1 26 2782 21 6.87369e+06 307425 503264. 1741.40 0.77 0.101909 0.0887736 24322 120374 -1 2258 23 1745 2467 162233 39815 4.05606 4.05606 -137.797 -4.05606 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0293776 0.0254551 128 30 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 5.13 vpr 63.11 MiB -1 -1 0.25 18372 1 0.03 -1 -1 30196 -1 -1 29 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64624 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 24.0 MiB 2.37 1060 14562 4184 8868 1510 63.1 MiB 0.14 0.00 4.11363 -115.792 -4.11363 4.11363 0.34 0.000654586 0.000608681 0.0494721 0.0459961 -1 -1 -1 -1 30 2285 32 6.87369e+06 405241 556674. 1926.21 0.70 0.138159 0.121704 25186 138497 -1 1890 18 982 1734 104165 24665 3.11651 3.11651 -108.645 -3.11651 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.023576 0.0205441 123 55 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 6.17 vpr 64.10 MiB -1 -1 0.26 18404 1 0.03 -1 -1 30556 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65640 32 32 393 312 1 215 88 17 17 289 -1 unnamed_device 24.4 MiB 2.82 1203 9838 2479 6641 718 64.1 MiB 0.07 0.00 5.21116 -164.931 -5.21116 5.21116 0.32 0.000342348 0.000315851 0.0195076 0.017971 -1 -1 -1 -1 26 3413 41 6.87369e+06 335372 503264. 1741.40 1.24 0.136273 0.117963 24322 120374 -1 2693 21 2122 3152 243393 57965 4.48486 4.48486 -163.249 -4.48486 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 32 32 300 245 1 187 86 17 17 289 -1 unnamed_device 23.8 MiB 1.33 1053 11993 3304 7573 1116 63.2 MiB 0.13 0.00 4.96363 -136.721 -4.96363 4.96363 0.33 0.000634294 0.000590454 0.0424028 0.0394305 -1 -1 -1 -1 26 2626 25 6.89349e+06 310065 503264. 1741.40 0.71 0.126284 0.111236 24322 120374 -1 2255 19 1275 1846 130434 31937 4.03626 4.03626 -132.507 -4.03626 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0237551 0.0206724 121 24 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 4.10 vpr 63.39 MiB -1 -1 0.13 17964 1 0.03 -1 -1 30384 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 28 32 260 223 1 163 85 17 17 289 -1 unnamed_device 23.6 MiB 1.23 910 14593 5077 7414 2102 63.1 MiB 0.13 0.00 4.29929 -120.332 -4.29929 4.29929 0.34 0.000557357 0.000518617 0.0461162 0.0428912 -1 -1 -1 -1 32 2100 20 6.89349e+06 352346 586450. 2029.24 0.56 0.111197 0.098241 25474 144626 -1 1696 21 895 1529 95985 22999 3.23235 3.23235 -110.54 -3.23235 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0122668 0.0107644 108 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_032.v common 3.76 vpr 63.04 MiB -1 -1 0.23 17900 1 0.03 -1 -1 30224 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 23.5 MiB 1.06 749 9160 2232 6447 481 63.0 MiB 0.09 0.00 3.86328 -116.366 -3.86328 3.86328 0.33 0.000573773 0.000532341 0.031373 0.0291874 -1 -1 -1 -1 28 2273 28 6.89349e+06 253689 531479. 1839.03 0.68 0.104099 0.0910894 24610 126494 -1 1785 34 1750 3035 275769 99959 2.87716 2.87716 -113.369 -2.87716 0 0 648988. 2245.63 0.03 0.12 0.10 -1 -1 0.03 0.0338085 0.0290584 101 3 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 3.63 vpr 63.10 MiB -1 -1 0.24 18240 1 0.03 -1 -1 30132 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 31 32 271 231 1 172 84 17 17 289 -1 unnamed_device 23.5 MiB 1.03 896 7770 1848 5501 421 63.1 MiB 0.09 0.00 3.62655 -110.965 -3.62655 3.62655 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64628 32 32 391 311 1 250 93 17 17 289 -1 unnamed_device 24.1 MiB 1.73 1433 15423 4226 9063 2134 63.1 MiB 0.18 0.00 4.56723 -154.163 -4.56723 4.56723 0.33 0.000759097 0.000705105 0.0586858 0.0546043 -1 -1 -1 -1 30 3141 34 6.89349e+06 408721 556674. 1926.21 0.84 0.164331 0.145039 25186 138497 -1 2546 22 2111 2906 187308 44776 3.63025 3.63025 -138.661 -3.63025 0 0 706193. 2443.58 0.03 0.09 0.11 -1 -1 0.03 0.0322373 0.0280504 162 65 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_037.v common 3.71 vpr 63.12 MiB -1 -1 0.24 18508 1 0.03 -1 -1 30236 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 23.6 MiB 1.01 863 12331 3145 7318 1868 63.1 MiB 0.12 0.00 4.00748 -119.789 -4.00748 4.00748 0.34 0.000603096 0.000561509 0.0437123 0.0406478 -1 -1 -1 -1 32 1949 21 6.89349e+06 253689 586450. 2029.24 0.58 0.11396 0.100554 25474 144626 -1 1645 19 873 1326 100623 24502 3.22455 3.22455 -109.63 -3.22455 0 0 744469. 2576.02 0.03 0.06 0.14 -1 -1 0.03 0.0229871 0.0200214 106 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 4.53 vpr 63.14 MiB -1 -1 0.28 18500 1 0.03 -1 -1 30392 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 31 32 370 297 1 235 91 17 17 289 -1 unnamed_device 24.2 MiB 1.85 1334 16615 5524 9183 1908 63.1 MiB 0.18 0.00 4.35803 -138.286 -4.35803 4.35803 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/home/elgamma8/research/release/vtr-verilog-to-routing 64796 32 32 291 242 1 188 86 17 17 289 -1 unnamed_device 23.7 MiB 1.37 1096 9347 2440 6352 555 63.3 MiB 0.10 0.00 4.52484 -122.151 -4.52484 4.52484 0.34 0.000629764 0.000586024 0.0325575 0.0302635 -1 -1 -1 -1 26 2789 28 6.89349e+06 310065 503264. 1741.40 0.59 0.119867 0.104736 24322 120374 -1 2323 23 1271 1766 129816 31818 4.20376 4.20376 -129.093 -4.20376 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0269782 0.0233675 114 27 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_043.v common 5.49 vpr 63.48 MiB -1 -1 0.28 18520 1 0.03 -1 -1 30440 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 457 356 1 296 99 17 17 289 -1 unnamed_device 24.4 MiB 2.27 1650 16971 5334 10464 1173 63.5 MiB 0.21 0.00 5.33145 -171.907 -5.33145 5.33145 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 32 32 349 286 1 221 89 17 17 289 -1 unnamed_device 23.8 MiB 1.50 1245 11969 3140 7616 1213 63.1 MiB 0.13 0.00 4.39413 -130.035 -4.39413 4.39413 0.34 0.000697558 0.00064848 0.0442265 0.0410941 -1 -1 -1 -1 30 2800 29 6.89349e+06 352346 556674. 1926.21 0.70 0.136708 0.120083 25186 138497 -1 2259 17 1056 1557 104303 24463 3.1503 3.1503 -117.968 -3.1503 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0240403 0.021017 142 57 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_112.v common 5.19 vpr 63.09 MiB -1 -1 0.29 18380 1 0.03 -1 -1 30260 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 31 32 396 325 1 259 93 17 17 289 -1 unnamed_device 24.0 MiB 2.12 1311 17313 4833 10070 2410 63.1 MiB 0.19 0.00 4.94622 -159.495 -4.94622 4.94622 0.33 0.000741991 0.000685776 0.0638633 0.0592945 -1 -1 -1 -1 32 3396 38 6.89349e+06 422815 586450. 2029.24 0.81 0.172103 0.15195 25474 144626 -1 2671 23 1970 2785 193766 45890 4.04249 4.04249 -151.176 -4.04249 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0322965 0.0279992 166 91 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_113.v common 4.65 vpr 63.05 MiB -1 -1 0.25 18472 1 0.03 -1 -1 30280 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 32 32 303 262 1 200 85 17 17 289 -1 unnamed_device 23.9 MiB 1.42 1134 7153 1649 5156 348 63.0 MiB 0.09 0.00 3.69791 -119.314 -3.69791 3.69791 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/home/elgamma8/research/release/vtr-verilog-to-routing 64684 32 32 393 312 1 243 90 17 17 289 -1 unnamed_device 24.1 MiB 2.00 1197 8532 1944 6080 508 63.2 MiB 0.11 0.00 5.6615 -176.256 -5.6615 5.6615 0.33 0.000765182 0.000711071 0.034673 0.0322116 -1 -1 -1 -1 32 3572 28 6.89349e+06 366440 586450. 2029.24 0.87 0.132281 0.11584 25474 144626 -1 2640 22 1876 2860 206960 49868 4.38809 4.38809 -163.546 -4.38809 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0314949 0.0273942 161 65 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_118.v common 3.73 vpr 63.07 MiB -1 -1 0.23 17908 1 0.03 -1 -1 30152 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 23.5 MiB 0.88 858 12156 3731 6704 1721 63.1 MiB 0.11 0.00 3.31865 -102.092 -3.31865 3.31865 0.33 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0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 32 32 360 293 1 226 91 17 17 289 -1 unnamed_device 23.8 MiB 1.40 1307 13759 4403 8202 1154 63.0 MiB 0.17 0.00 4.10168 -130.557 -4.10168 4.10168 0.33 0.000711311 0.00066117 0.0570836 0.0530446 -1 -1 -1 -1 32 2791 48 6.89349e+06 380534 586450. 2029.24 0.71 0.169513 0.148957 25474 144626 -1 2228 17 1439 1975 125236 30124 2.97891 2.97891 -117.401 -2.97891 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0245511 0.0214454 147 60 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 5.73 vpr 63.15 MiB -1 -1 0.14 18740 1 0.03 -1 -1 30328 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64668 32 32 396 299 1 240 92 17 17 289 -1 unnamed_device 24.1 MiB 2.03 1350 12098 3111 7804 1183 63.2 MiB 0.17 0.00 5.93815 -178.759 -5.93815 5.93815 0.34 0.000774961 0.000720753 0.0484735 0.0450489 -1 -1 -1 -1 30 3179 30 6.89349e+06 394628 556674. 1926.21 1.07 0.154751 0.136253 25186 138497 -1 2629 22 1591 2517 184543 45433 4.56655 4.56655 -159.834 -4.56655 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0173111 0.0152944 167 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 3.42 vpr 63.09 MiB -1 -1 0.18 18056 1 0.03 -1 -1 30168 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 30 32 224 207 1 138 79 17 17 289 -1 unnamed_device 23.6 MiB 0.86 744 11064 2972 6586 1506 63.1 MiB 0.09 0.00 3.06986 -93.837 -3.06986 3.06986 0.33 0.00050022 0.000465468 0.0342512 0.0318795 -1 -1 -1 -1 32 1608 21 6.89349e+06 239595 586450. 2029.24 0.51 0.0930254 0.0819585 25474 144626 -1 1362 19 746 975 64274 15732 2.15637 2.15637 -86.663 -2.15637 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0186802 0.0161973 80 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 4.09 vpr 63.19 MiB -1 -1 0.24 18064 1 0.03 -1 -1 30332 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 30 32 286 239 1 176 85 17 17 289 -1 unnamed_device 23.6 MiB 1.17 970 14221 4684 7353 2184 63.2 MiB 0.13 0.00 4.47457 -139.461 -4.47457 4.47457 0.33 0.000598059 0.000556233 0.0476839 0.0443531 -1 -1 -1 -1 32 2088 19 6.89349e+06 324158 586450. 2029.24 0.57 0.116239 0.102831 25474 144626 -1 1798 19 1209 1755 123419 28254 3.20405 3.20405 -123.196 -3.20405 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0213811 0.0188746 120 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 4.64 vpr 63.24 MiB -1 -1 0.14 18164 1 0.04 -1 -1 30036 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 32 32 296 247 1 187 89 17 17 289 -1 unnamed_device 23.9 MiB 1.81 1127 15137 4309 8906 1922 63.2 MiB 0.15 0.00 4.30299 -142.144 -4.30299 4.30299 0.33 0.000624179 0.000580082 0.0500647 0.0464926 -1 -1 -1 -1 32 2632 22 6.89349e+06 352346 586450. 2029.24 0.65 0.124241 0.109743 25474 144626 -1 2086 21 1194 2198 152487 35249 3.2979 3.2979 -129.639 -3.2979 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0252727 0.0218883 119 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 3.81 vpr 63.04 MiB -1 -1 0.23 18076 1 0.03 -1 -1 30284 -1 -1 22 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 25 32 216 194 1 138 79 17 17 289 -1 unnamed_device 23.6 MiB 0.97 598 9881 3477 4123 2281 63.0 MiB 0.07 0.00 3.7089 -85.4656 -3.7089 3.7089 0.33 0.000478077 0.000444482 0.0293864 0.0272887 -1 -1 -1 -1 36 1448 42 6.89349e+06 310065 648988. 2245.63 1.04 0.136492 0.117908 26050 158493 -1 1138 18 657 975 59260 15977 2.93981 2.93981 -80.0624 -2.93981 0 0 828058. 2865.25 0.03 0.03 0.09 -1 -1 0.03 0.00980015 0.00865384 88 29 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 4.99 vpr 63.14 MiB -1 -1 0.15 18352 1 0.03 -1 -1 30352 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64660 32 32 376 307 1 242 90 17 17 289 -1 unnamed_device 24.1 MiB 2.30 1430 16170 4616 9563 1991 63.1 MiB 0.18 0.00 4.51899 -138.857 -4.51899 4.51899 0.33 0.000721273 0.000669662 0.0603201 0.0559474 -1 -1 -1 -1 32 3301 26 6.89349e+06 366440 586450. 2029.24 0.66 0.151815 0.134188 25474 144626 -1 2662 22 1825 2779 185735 42367 3.63286 3.63286 -129.152 -3.63286 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164302 0.0144632 156 72 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 5.19 vpr 63.29 MiB -1 -1 0.27 18404 1 0.03 -1 -1 30280 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 31 32 409 331 1 264 96 17 17 289 -1 unnamed_device 24.2 MiB 2.08 1431 11703 3152 7474 1077 63.3 MiB 0.14 0.00 4.84775 -156.008 -4.84775 4.84775 0.33 0.000772559 0.000718063 0.0435525 0.0403604 -1 -1 -1 -1 26 3450 37 6.89349e+06 465097 503264. 1741.40 0.87 0.155585 0.13616 24322 120374 -1 3021 21 2266 3099 239025 58139 4.43869 4.43869 -159.514 -4.43869 0 0 618332. 2139.56 0.03 0.09 0.10 -1 -1 0.03 0.0309079 0.0268354 175 90 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 4.14 vpr 64.34 MiB -1 -1 0.19 18372 14 0.23 -1 -1 32420 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 277 309 1 203 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3169 1468 11328 2379 7541 1408 64.3 MiB 0.07 0.00 10.3228 8.34809 -172.958 -8.34809 8.34809 0.24 0.000458019 0.000420977 0.0267514 0.024586 -1 -1 -1 -1 26 4102 40 6.55708e+06 482200 477104. 1650.88 2.34 0.198273 0.175014 21022 109990 -1 3183 21 1415 4612 232092 56261 7.86483 7.86483 -171.918 -7.86483 0 0 585099. 2024.56 0.05 0.08 0.06 -1 -1 0.05 0.0346821 0.0278328 194 183 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 2.82 vpr 64.72 MiB -1 -1 0.19 18608 14 0.26 -1 -1 32020 -1 -1 39 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66272 30 32 272 304 1 192 101 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2855 1327 6211 1127 4807 277 64.7 MiB 0.04 0.00 10.4229 7.81577 -157.932 -7.81577 7.81577 0.25 0.00044353 0.000407199 0.0145115 0.013339 -1 -1 -1 -1 26 3276 21 6.55708e+06 470145 477104. 1650.88 1.03 0.138339 0.121807 21022 109990 -1 2977 18 1223 3838 191983 48311 7.09678 7.09678 -155.225 -7.09678 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0222913 0.0201627 191 184 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 2.79 vpr 64.70 MiB -1 -1 0.14 17972 11 0.20 -1 -1 32500 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 280 312 1 187 103 17 17 289 -1 unnamed_device 24.7 MiB 0.06 2827 1361 6128 1131 4405 592 64.7 MiB 0.04 0.00 8.30478 6.65392 -136.28 -6.65392 6.65392 0.23 0.000444217 0.000407628 0.0153173 0.0140577 -1 -1 -1 -1 28 3532 22 6.55708e+06 470145 500653. 1732.36 1.13 0.141601 0.124216 21310 115450 -1 2893 19 1295 4984 238971 59050 5.81978 5.81978 -132.978 -5.81978 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.022413 0.0200969 193 186 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_004.v common 2.40 vpr 64.21 MiB -1 -1 0.16 18368 12 0.29 -1 -1 32700 -1 -1 40 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 29 32 275 307 1 194 101 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2959 1244 8326 1689 5934 703 64.2 MiB 0.05 0.00 9.98698 7.42963 -136.806 -7.42963 7.42963 0.33 0.000442208 0.000402322 0.0186625 0.0171344 -1 -1 -1 -1 22 3463 27 6.55708e+06 482200 420624. 1455.45 0.62 0.111711 0.100638 20158 92377 -1 3149 20 1718 5783 304181 76974 6.67344 6.67344 -140.022 -6.67344 0 0 500653. 1732.36 0.02 0.08 0.05 -1 -1 0.02 0.0253416 0.0228426 200 190 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_005.v common 2.59 vpr 64.82 MiB -1 -1 0.18 18364 13 0.24 -1 -1 31812 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 32 32 302 334 1 214 106 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3277 1472 9856 1982 7031 843 64.8 MiB 0.05 0.00 10.9395 7.98333 -168.064 -7.98333 7.98333 0.23 0.000470534 0.000431442 0.0218695 0.0200206 -1 -1 -1 -1 26 3770 18 6.55708e+06 506310 477104. 1650.88 0.93 0.134458 0.118969 21022 109990 -1 3230 16 1274 3900 187211 47077 7.22463 7.22463 -162.98 -7.22463 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.021449 0.0195803 217 208 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 2.56 vpr 64.45 MiB -1 -1 0.25 18364 13 0.23 -1 -1 32448 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 292 324 1 212 106 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2866 1500 7356 1329 5608 419 64.4 MiB 0.06 0.00 9.67796 7.98192 -159.937 -7.98192 7.98192 0.24 0.0011069 0.0010281 0.0237148 0.0219451 -1 -1 -1 -1 30 3231 22 6.55708e+06 506310 526063. 1820.29 0.67 0.135582 0.121368 21886 126133 -1 2914 15 1161 4203 188301 46205 6.76976 6.76976 -150.378 -6.76976 0 0 666494. 2306.21 0.03 0.06 0.07 -1 -1 0.03 0.0231856 0.0211083 204 198 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 2.26 vpr 64.33 MiB -1 -1 0.17 17984 12 0.18 -1 -1 32260 -1 -1 38 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 27 32 229 261 1 167 97 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2337 1007 8533 2013 5783 737 64.3 MiB 0.04 0.00 9.40566 7.49882 -132.896 -7.49882 7.49882 0.23 0.000357417 0.000327606 0.0166803 0.0152855 -1 -1 -1 -1 22 2846 33 6.55708e+06 458090 420624. 1455.45 0.73 0.0961015 0.0844727 20158 92377 -1 2495 21 936 2825 151732 38675 7.10844 7.10844 -133.129 -7.10844 0 0 500653. 1732.36 0.02 0.05 0.05 -1 -1 0.02 0.0221263 0.0200669 162 150 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 2.26 vpr 63.80 MiB -1 -1 0.15 17980 12 0.16 -1 -1 32388 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65328 31 32 229 261 1 172 99 17 17 289 -1 unnamed_device 24.0 MiB 0.09 2493 1182 11499 2779 7797 923 63.8 MiB 0.05 0.00 7.48917 6.1978 -123.822 -6.1978 6.1978 0.23 0.000357937 0.00032045 0.0200933 0.0182708 -1 -1 -1 -1 26 3022 23 6.55708e+06 433980 477104. 1650.88 0.68 0.0929068 0.0826701 21022 109990 -1 2558 15 983 3146 160300 39339 5.61152 5.61152 -124 -5.61152 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0152523 0.0138522 153 138 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 2.12 vpr 64.02 MiB -1 -1 0.18 18368 12 0.15 -1 -1 32260 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 31 32 235 267 1 170 98 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2607 1194 6398 1155 4738 505 64.0 MiB 0.03 0.00 8.76355 7.13011 -140.761 -7.13011 7.13011 0.24 0.000359813 0.000329497 0.0130808 0.0120095 -1 -1 -1 -1 26 2823 45 6.55708e+06 421925 477104. 1650.88 0.53 0.0813171 0.0719305 21022 109990 -1 2481 18 878 2720 142628 35086 6.35464 6.35464 -138.252 -6.35464 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.026961 0.024312 155 144 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_010.v common 2.73 vpr 64.53 MiB -1 -1 0.17 17972 13 0.23 -1 -1 32340 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 250 282 1 190 99 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2595 1285 6255 1073 4701 481 64.5 MiB 0.04 0.00 9.61062 7.56812 -165.213 -7.56812 7.56812 0.26 0.000386406 0.000353879 0.0145749 0.0134141 -1 -1 -1 -1 26 3258 24 6.55708e+06 421925 477104. 1650.88 1.03 0.151248 0.131586 21022 109990 -1 2743 21 1276 3790 183407 45756 6.89358 6.89358 -162.183 -6.89358 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.0293242 0.0262182 166 156 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 2.49 vpr 64.09 MiB -1 -1 0.15 17980 12 0.16 -1 -1 32496 -1 -1 33 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 30 32 216 248 1 160 95 17 17 289 -1 unnamed_device 24.2 MiB 0.07 2363 1089 9383 1996 6576 811 64.1 MiB 0.04 0.00 8.78898 6.99514 -141.661 -6.99514 6.99514 0.25 0.00034128 0.000311808 0.0166983 0.0152604 -1 -1 -1 -1 28 2591 19 6.55708e+06 397815 500653. 1732.36 0.90 0.101924 0.0897543 21310 115450 -1 2231 16 835 2644 129323 32207 6.02864 6.02864 -134.773 -6.02864 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0171828 0.0155916 140 128 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 2.27 vpr 63.82 MiB -1 -1 0.14 17980 12 0.13 -1 -1 32248 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65348 32 32 236 268 1 171 97 17 17 289 -1 unnamed_device 24.0 MiB 0.07 2486 1250 7201 1363 5333 505 63.8 MiB 0.04 0.00 7.92826 6.93051 -150.969 -6.93051 6.93051 0.24 0.000362163 0.000323716 0.0139954 0.0127661 -1 -1 -1 -1 22 3133 21 6.55708e+06 397815 420624. 1455.45 0.80 0.105874 0.0929435 20158 92377 -1 2873 18 1055 3139 174475 42904 6.04852 6.04852 -151.719 -6.04852 0 0 500653. 1732.36 0.02 0.05 0.05 -1 -1 0.02 0.0177045 0.0160033 148 142 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_013.v common 2.11 vpr 64.77 MiB -1 -1 0.17 17904 13 0.22 -1 -1 32380 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 32 32 283 315 1 206 102 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2918 1396 8432 1576 6264 592 64.8 MiB 0.05 0.00 10.5047 7.90793 -163.623 -7.90793 7.90793 0.24 0.000463543 0.000426506 0.0209377 0.0192839 -1 -1 -1 -1 26 3470 21 6.55708e+06 458090 477104. 1650.88 0.49 0.0961944 0.0860277 21022 109990 -1 2987 16 1182 3603 185734 44882 6.92916 6.92916 -156.223 -6.92916 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0219292 0.0199363 197 189 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_014.v common 2.97 vpr 64.87 MiB -1 -1 0.17 18364 14 0.28 -1 -1 32428 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66428 32 32 303 335 1 216 103 17 17 289 -1 unnamed_device 25.2 MiB 0.11 3288 1474 6128 1054 4658 416 64.9 MiB 0.04 0.00 12.0727 8.81606 -181.273 -8.81606 8.81606 0.24 0.000504434 0.000449507 0.0154959 0.0142237 -1 -1 -1 -1 28 3839 27 6.55708e+06 470145 500653. 1732.36 1.22 0.163212 0.143995 21310 115450 -1 3197 18 1484 4767 234549 57799 7.60916 7.60916 -170.785 -7.60916 0 0 612192. 2118.31 0.02 0.07 0.06 -1 -1 0.02 0.0274708 0.0249197 214 209 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_015.v common 2.39 vpr 64.35 MiB -1 -1 0.14 17980 11 0.15 -1 -1 32280 -1 -1 39 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 29 32 225 257 1 164 100 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2302 1071 8684 1857 6075 752 64.3 MiB 0.04 0.00 8.12271 6.84055 -135.697 -6.84055 6.84055 0.23 0.000349214 0.000319509 0.0150334 0.013758 -1 -1 -1 -1 30 2348 30 6.55708e+06 470145 526063. 1820.29 0.91 0.137917 0.121515 21886 126133 -1 2011 13 693 2200 90643 23004 5.99144 5.99144 -125.931 -5.99144 0 0 666494. 2306.21 0.02 0.03 0.07 -1 -1 0.02 0.013831 0.012644 154 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_016.v common 3.46 vpr 64.83 MiB -1 -1 0.25 18748 12 0.25 -1 -1 32680 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 32 32 301 333 1 214 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3731 1580 10108 2123 7160 825 64.8 MiB 0.06 0.00 10.4215 7.69506 -165.69 -7.69506 7.69506 0.23 0.00048124 0.000442319 0.023123 0.0211923 -1 -1 -1 -1 28 4238 23 6.55708e+06 482200 500653. 1732.36 1.51 0.193497 0.172492 21310 115450 -1 3402 20 1337 4577 232126 56137 6.59044 6.59044 -157.099 -6.59044 0 0 612192. 2118.31 0.04 0.11 0.11 -1 -1 0.04 0.0451348 0.0409865 211 207 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_017.v common 2.31 vpr 64.70 MiB -1 -1 0.17 18368 14 0.22 -1 -1 32384 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 277 309 1 206 102 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3035 1443 6528 1220 4877 431 64.7 MiB 0.04 0.00 10.0543 7.86974 -166.415 -7.86974 7.86974 0.24 0.000429846 0.000392749 0.0174185 0.0160311 -1 -1 -1 -1 30 3432 26 6.55708e+06 458090 526063. 1820.29 0.64 0.10171 0.0899918 21886 126133 -1 2807 16 1180 4013 184856 44602 6.94704 6.94704 -156.04 -6.94704 0 0 666494. 2306.21 0.03 0.05 0.08 -1 -1 0.03 0.0206573 0.018835 193 183 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_018.v common 2.73 vpr 64.29 MiB -1 -1 0.20 18360 12 0.14 -1 -1 32224 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 227 259 1 155 96 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2590 1167 9951 2256 6821 874 64.3 MiB 0.07 0.00 9.34738 6.87555 -150.994 -6.87555 6.87555 0.24 0.000849311 0.000790944 0.0342931 0.0321893 -1 -1 -1 -1 26 2790 20 6.55708e+06 385760 477104. 1650.88 1.03 0.160074 0.142578 21022 109990 -1 2381 19 920 3114 159590 38534 6.18098 6.18098 -145.131 -6.18098 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0283522 0.025653 145 133 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_019.v common 1.73 vpr 63.68 MiB -1 -1 0.13 17984 10 0.08 -1 -1 31720 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65204 30 32 175 207 1 133 87 17 17 289 -1 unnamed_device 24.1 MiB 0.04 1817 875 6615 1509 4517 589 63.7 MiB 0.03 0.00 6.36477 5.54003 -124.848 -5.54003 5.54003 0.24 0.000273145 0.000250213 0.0117929 0.0108481 -1 -1 -1 -1 26 1892 14 6.55708e+06 301375 477104. 1650.88 0.37 0.0455235 0.0402896 21022 109990 -1 1707 15 580 1538 75173 19570 4.68146 4.68146 -118.937 -4.68146 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.011085 0.00998996 100 87 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_020.v common 2.61 vpr 64.34 MiB -1 -1 0.26 18368 13 0.16 -1 -1 32248 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 31 32 231 263 1 172 96 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2551 1219 5133 882 3910 341 64.3 MiB 0.03 0.00 9.56848 7.51354 -158.515 -7.51354 7.51354 0.25 0.00037534 0.000342742 0.011147 0.0102689 -1 -1 -1 -1 26 2914 16 6.55708e+06 397815 477104. 1650.88 0.93 0.10781 0.0949072 21022 109990 -1 2616 16 912 2770 141635 35169 6.50744 6.50744 -149.665 -6.50744 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0166308 0.0151505 151 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_021.v common 3.59 vpr 64.70 MiB -1 -1 0.25 18364 13 0.24 -1 -1 33084 -1 -1 45 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 32 32 304 336 1 215 109 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3300 1520 9729 2088 6855 786 64.7 MiB 0.05 0.00 11.3205 8.3687 -170.208 -8.3687 8.3687 0.36 0.000468055 0.00042951 0.021122 0.0193255 -1 -1 -1 -1 26 4144 38 6.55708e+06 542475 477104. 1650.88 1.62 0.168739 0.149499 21022 109990 -1 3324 16 1386 4558 227561 55685 7.37076 7.37076 -163.235 -7.37076 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0248103 0.0223431 222 210 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_022.v common 3.26 vpr 65.14 MiB -1 -1 0.17 18364 13 0.32 -1 -1 32320 -1 -1 46 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66700 32 32 288 320 1 212 110 17 17 289 -1 unnamed_device 25.2 MiB 0.08 3011 1549 9841 1986 7037 818 65.1 MiB 0.06 0.00 9.94628 8.09001 -170.835 -8.09001 8.09001 0.25 0.000783059 0.000709901 0.0240612 0.0222191 -1 -1 -1 -1 34 3785 46 6.55708e+06 554530 585099. 2024.56 1.41 0.194299 0.171381 22462 138074 -1 3315 18 1268 4764 252706 59815 6.97197 6.97197 -158.757 -6.97197 0 0 742403. 2568.87 0.03 0.07 0.08 -1 -1 0.03 0.0266895 0.0242846 209 194 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_023.v common 1.70 vpr 63.59 MiB -1 -1 0.12 17600 9 0.08 -1 -1 32016 -1 -1 30 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65120 26 32 152 184 1 110 88 17 17 289 -1 unnamed_device 24.0 MiB 0.03 1535 711 7888 1985 4791 1112 63.6 MiB 0.03 0.00 5.98374 4.84 -87.8657 -4.84 4.84 0.23 0.000243053 0.000222729 0.0112522 0.0102964 -1 -1 -1 -1 26 1557 15 6.55708e+06 361650 477104. 1650.88 0.33 0.0419996 0.0368842 21022 109990 -1 1389 17 478 1412 69242 17472 4.2322 4.2322 -86.9531 -4.2322 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0156673 0.0139829 95 76 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_024.v common 2.28 vpr 64.75 MiB -1 -1 0.16 18220 13 0.25 -1 -1 32356 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 287 319 1 209 106 17 17 289 -1 unnamed_device 25.0 MiB 0.07 3188 1475 7356 1240 5841 275 64.8 MiB 0.04 0.00 10.9129 8.3667 -168.117 -8.3667 8.3667 0.24 0.000456208 0.00041319 0.0164859 0.015092 -1 -1 -1 -1 26 3835 20 6.55708e+06 506310 477104. 1650.88 0.65 0.0893791 0.0794058 21022 109990 -1 3121 17 1250 3890 189718 46969 7.40996 7.40996 -160.049 -7.40996 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0207467 0.0188691 204 193 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_025.v common 1.68 vpr 63.57 MiB -1 -1 0.13 17600 8 0.07 -1 -1 32016 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65092 32 32 154 186 1 117 91 17 17 289 -1 unnamed_device 24.0 MiB 0.04 1504 839 6823 1506 4714 603 63.6 MiB 0.03 0.00 4.86674 4.14794 -97.1492 -4.14794 4.14794 0.23 0.000245642 0.000219086 0.00957985 0.00875471 -1 -1 -1 -1 26 1708 16 6.55708e+06 325485 477104. 1650.88 0.35 0.040037 0.0351673 21022 109990 -1 1465 13 445 1124 51583 13618 3.90514 3.90514 -96.8068 -3.90514 0 0 585099. 2024.56 0.02 0.02 0.08 -1 -1 0.02 0.00901111 0.00814501 83 60 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_026.v common 2.70 vpr 64.62 MiB -1 -1 0.19 17980 15 0.21 -1 -1 32384 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 32 32 254 286 1 184 108 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2794 1289 8846 1673 6391 782 64.6 MiB 0.04 0.00 11.4269 8.91249 -179.898 -8.91249 8.91249 0.24 0.000411792 0.000376479 0.0166773 0.0152536 -1 -1 -1 -1 28 3141 22 6.55708e+06 530420 500653. 1732.36 1.05 0.133835 0.117718 21310 115450 -1 2703 19 1085 3420 169095 41588 7.75229 7.75229 -168.555 -7.75229 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0202997 0.0183246 178 160 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_027.v common 3.32 vpr 64.26 MiB -1 -1 0.28 18368 13 0.20 -1 -1 32396 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 32 32 260 292 1 185 101 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2553 1218 6446 1181 4503 762 64.3 MiB 0.04 0.00 8.41804 7.47895 -148.299 -7.47895 7.47895 0.35 0.000420455 0.000384763 0.0146573 0.0134158 -1 -1 -1 -1 28 3650 32 6.55708e+06 446035 500653. 1732.36 1.30 0.141603 0.124407 21310 115450 -1 2721 15 1115 3669 183849 47689 6.42904 6.42904 -144.643 -6.42904 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0184911 0.0168997 177 166 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_028.v common 2.89 vpr 64.74 MiB -1 -1 0.17 18368 13 0.24 -1 -1 32460 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 279 311 1 203 102 17 17 289 -1 unnamed_device 24.8 MiB 0.11 2785 1427 7242 1418 5129 695 64.7 MiB 0.07 0.00 9.58507 7.90558 -164.249 -7.90558 7.90558 0.44 0.000817344 0.000732132 0.0296013 0.0270257 -1 -1 -1 -1 28 3858 46 6.55708e+06 458090 500653. 1732.36 0.87 0.129441 0.116272 21310 115450 -1 3094 16 1193 4031 204357 49925 6.90524 6.90524 -156.112 -6.90524 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0215907 0.0197086 194 185 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_029.v common 2.58 vpr 63.68 MiB -1 -1 0.14 17984 12 0.15 -1 -1 32200 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65212 32 32 238 270 1 175 98 17 17 289 -1 unnamed_device 24.1 MiB 0.07 2532 1229 6623 1196 5108 319 63.7 MiB 0.05 0.00 8.83794 6.95354 -149.945 -6.95354 6.95354 0.34 0.000362825 0.000331699 0.0207453 0.0191131 -1 -1 -1 -1 26 3231 30 6.55708e+06 409870 477104. 1650.88 0.76 0.0914983 0.0816512 21022 109990 -1 2625 20 1044 3327 165434 41832 6.25938 6.25938 -147.249 -6.25938 0 0 585099. 2024.56 0.03 0.08 0.10 -1 -1 0.03 0.0311287 0.0280935 151 144 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_030.v common 2.42 vpr 64.23 MiB -1 -1 0.14 17980 11 0.18 -1 -1 32228 -1 -1 32 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 30 32 213 245 1 156 94 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2070 1033 7549 1505 5428 616 64.2 MiB 0.04 0.00 8.27041 6.08486 -132.558 -6.08486 6.08486 0.24 0.00033254 0.000298034 0.0137224 0.0125369 -1 -1 -1 -1 26 2273 36 6.55708e+06 385760 477104. 1650.88 0.75 0.10972 0.0956295 21022 109990 -1 2055 14 763 2181 98833 26461 5.43986 5.43986 -127.04 -5.43986 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0168096 0.0153762 136 125 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_031.v common 2.06 vpr 64.36 MiB -1 -1 0.18 17820 11 0.15 -1 -1 32252 -1 -1 38 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 28 32 227 259 1 163 98 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2167 1077 9098 1974 6271 853 64.4 MiB 0.05 0.00 7.98015 6.78919 -130.953 -6.78919 6.78919 0.25 0.000476822 0.000447209 0.0226207 0.0209058 -1 -1 -1 -1 26 2605 24 6.55708e+06 458090 477104. 1650.88 0.46 0.0935539 0.083392 21022 109990 -1 2357 15 882 2746 133141 33518 6.11266 6.11266 -125.603 -6.11266 0 0 585099. 2024.56 0.03 0.05 0.06 -1 -1 0.03 0.0199283 0.0181338 155 145 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_032.v common 2.69 vpr 64.65 MiB -1 -1 0.19 17980 12 0.19 -1 -1 32280 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 32 32 274 306 1 199 103 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3018 1411 6128 1033 4730 365 64.7 MiB 0.04 0.00 9.91223 7.35615 -165.077 -7.35615 7.35615 0.24 0.000661124 0.000624461 0.0141509 0.0130367 -1 -1 -1 -1 28 3428 19 6.55708e+06 470145 500653. 1732.36 1.00 0.123875 0.108623 21310 115450 -1 2862 17 1149 3414 164768 41668 6.35004 6.35004 -156.285 -6.35004 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0208 0.0188528 188 180 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_033.v common 1.97 vpr 64.18 MiB -1 -1 0.14 17976 12 0.14 -1 -1 32240 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 31 32 237 269 1 165 98 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2339 1152 7973 1666 5519 788 64.2 MiB 0.04 0.00 8.83795 7.15214 -144.041 -7.15214 7.15214 0.24 0.000360413 0.000326731 0.0152974 0.0139203 -1 -1 -1 -1 26 2785 21 6.55708e+06 421925 477104. 1650.88 0.42 0.0710706 0.0628035 21022 109990 -1 2478 19 1052 3111 153968 38476 6.22984 6.22984 -139.914 -6.22984 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0257539 0.0230039 161 146 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_034.v common 1.80 vpr 64.32 MiB -1 -1 0.18 17984 10 0.12 -1 -1 32220 -1 -1 33 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 220 252 1 154 94 17 17 289 -1 unnamed_device 24.8 MiB 0.05 2111 1030 5206 950 3856 400 64.3 MiB 0.03 0.00 7.90072 6.31249 -127.587 -6.31249 6.31249 0.23 0.000341905 0.000312898 0.0105515 0.00968785 -1 -1 -1 -1 26 2457 16 6.55708e+06 397815 477104. 1650.88 0.30 0.0550495 0.0487275 21022 109990 -1 2196 16 763 2669 127482 31451 5.50298 5.50298 -123.617 -5.50298 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.015236 0.0138402 146 135 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_035.v common 2.56 vpr 64.93 MiB -1 -1 0.18 18748 13 0.35 -1 -1 32504 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66488 32 32 315 347 1 220 104 17 17 289 -1 unnamed_device 25.5 MiB 0.09 3359 1629 9132 2182 5924 1026 64.9 MiB 0.05 0.00 10.2396 8.33236 -170.529 -8.33236 8.33236 0.23 0.000496726 0.000454774 0.0221698 0.0202728 -1 -1 -1 -1 26 4005 19 6.55708e+06 482200 477104. 1650.88 0.70 0.0969603 0.0867237 21022 109990 -1 3407 16 1525 5269 261204 63091 6.78964 6.78964 -154.084 -6.78964 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0222822 0.0202409 231 221 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_036.v common 2.68 vpr 64.77 MiB -1 -1 0.17 18752 14 0.34 -1 -1 32288 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 32 32 282 314 1 219 107 17 17 289 -1 unnamed_device 24.8 MiB 0.13 3309 1501 7444 1465 5350 629 64.8 MiB 0.04 0.00 9.01512 7.882 -167.76 -7.882 7.882 0.23 0.000457104 0.000413096 0.0160806 0.0147011 -1 -1 -1 -1 30 3451 21 6.55708e+06 518365 526063. 1820.29 0.63 0.114441 0.102052 21886 126133 -1 3012 19 1353 4471 189705 48631 6.82684 6.82684 -156.723 -6.82684 0 0 666494. 2306.21 0.03 0.07 0.08 -1 -1 0.03 0.0272279 0.0246689 199 188 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_037.v common 2.55 vpr 64.40 MiB -1 -1 0.15 17984 12 0.13 -1 -1 32280 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 31 32 241 273 1 176 97 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2615 1203 10087 2397 6601 1089 64.4 MiB 0.07 0.00 10.1954 7.8818 -157.766 -7.8818 7.8818 0.25 0.000373792 0.000342257 0.0315957 0.0290482 -1 -1 -1 -1 26 2814 23 6.55708e+06 409870 477104. 1650.88 0.99 0.145263 0.128418 21022 109990 -1 2492 19 1059 3340 167020 41325 6.94904 6.94904 -150.445 -6.94904 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0178526 0.0160758 161 150 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_038.v common 3.38 vpr 64.19 MiB -1 -1 0.18 18604 12 0.24 -1 -1 32444 -1 -1 42 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65732 31 32 307 339 1 218 105 17 17 289 -1 unnamed_device 25.2 MiB 0.12 3531 1406 11961 2747 8126 1088 64.2 MiB 0.07 0.00 9.67644 7.34358 -149.686 -7.34358 7.34358 0.23 0.000477874 0.000430677 0.0279143 0.0255112 -1 -1 -1 -1 26 4060 37 6.55708e+06 506310 477104. 1650.88 1.57 0.230868 0.204995 21022 109990 -1 3110 21 1514 5290 250090 63272 6.71064 6.71064 -148.302 -6.71064 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.031789 0.0285672 222 216 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_039.v common 3.01 vpr 64.46 MiB -1 -1 0.19 18748 14 0.30 -1 -1 33004 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 293 325 1 209 103 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3249 1483 8056 1615 5882 559 64.5 MiB 0.10 0.00 11.3501 8.401 -168.472 -8.401 8.401 0.32 0.00120517 0.0011155 0.0430016 0.0397087 -1 -1 -1 -1 24 4160 43 6.55708e+06 482200 448715. 1552.65 1.10 0.163162 0.145601 20734 103517 -1 3341 29 1546 4981 334492 116243 7.72936 7.72936 -165.676 -7.72936 0 0 554710. 1919.41 0.02 0.12 0.06 -1 -1 0.02 0.0390517 0.0352076 211 202 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_040.v common 2.75 vpr 64.60 MiB -1 -1 0.19 18752 13 0.23 -1 -1 32248 -1 -1 49 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 31 32 276 308 1 210 112 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3496 1506 9527 2110 6648 769 64.6 MiB 0.05 0.00 10.2681 8.49401 -167.474 -8.49401 8.49401 0.24 0.000435905 0.000399578 0.0187398 0.0171331 -1 -1 -1 -1 26 4222 41 6.55708e+06 590695 477104. 1650.88 1.06 0.116426 0.103875 21022 109990 -1 3390 31 1362 4459 292331 95208 7.1573 7.1573 -156.188 -7.1573 0 0 585099. 2024.56 0.02 0.09 0.06 -1 -1 0.02 0.0302454 0.0269603 204 185 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_041.v common 4.13 vpr 64.66 MiB -1 -1 0.18 18368 13 0.33 -1 -1 32428 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 31 32 269 301 1 187 99 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2993 1382 7623 1737 5150 736 64.7 MiB 0.05 0.00 9.77611 7.29977 -148.117 -7.29977 7.29977 0.23 0.000649272 0.000586185 0.0179255 0.0164024 -1 -1 -1 -1 26 3776 30 6.55708e+06 433980 477104. 1650.88 2.36 0.170021 0.150298 21022 109990 -1 2992 18 1097 3889 201560 47848 6.31084 6.31084 -138.606 -6.31084 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0209992 0.0190088 186 178 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_042.v common 2.52 vpr 64.57 MiB -1 -1 0.16 17980 12 0.16 -1 -1 32392 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 264 296 1 182 100 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2787 1178 16572 4143 9707 2722 64.6 MiB 0.08 0.00 8.67103 7.20861 -147.87 -7.20861 7.20861 0.24 0.000396717 0.000362317 0.031655 0.0287685 -1 -1 -1 -1 28 2903 30 6.55708e+06 433980 500653. 1732.36 0.92 0.146414 0.129198 21310 115450 -1 2418 14 944 2858 141962 35987 6.33838 6.33838 -138.315 -6.33838 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0198651 0.0180623 180 170 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_043.v common 3.48 vpr 65.00 MiB -1 -1 0.30 19516 14 0.36 -1 -1 32460 -1 -1 46 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 32 32 324 356 1 237 110 17 17 289 -1 unnamed_device 25.2 MiB 0.09 3588 1767 7474 1429 5523 522 65.0 MiB 0.05 0.00 10.0303 8.51709 -182.069 -8.51709 8.51709 0.23 0.000502932 0.000460485 0.017751 0.0163008 -1 -1 -1 -1 32 4223 21 6.55708e+06 554530 554710. 1919.41 1.49 0.228883 0.201565 22174 131602 -1 3712 19 1425 5225 247788 61833 7.3565 7.3565 -172.567 -7.3565 0 0 701300. 2426.64 0.03 0.07 0.07 -1 -1 0.03 0.0292167 0.0264599 241 230 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_044.v common 1.96 vpr 63.96 MiB -1 -1 0.14 17984 11 0.17 -1 -1 31924 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65500 31 32 249 281 1 175 96 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2703 1245 9951 2354 6419 1178 64.0 MiB 0.05 0.00 8.92495 6.69552 -142.327 -6.69552 6.69552 0.23 0.000400985 0.000367433 0.020751 0.0189973 -1 -1 -1 -1 26 3314 26 6.55708e+06 397815 477104. 1650.88 0.45 0.0794923 0.0704457 21022 109990 -1 2774 20 1213 4204 218942 54057 5.89112 5.89112 -137.993 -5.89112 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0204148 0.0184373 169 158 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_045.v common 2.79 vpr 64.76 MiB -1 -1 0.17 18368 13 0.24 -1 -1 32256 -1 -1 43 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 284 316 1 195 106 17 17 289 -1 unnamed_device 24.8 MiB 0.09 2880 1407 6106 991 4788 327 64.8 MiB 0.04 0.00 10.1669 8.04395 -157.61 -8.04395 8.04395 0.23 0.000456389 0.000417669 0.0140646 0.0128906 -1 -1 -1 -1 26 3416 21 6.55708e+06 518365 477104. 1650.88 1.13 0.14093 0.124106 21022 109990 -1 2935 19 1052 3846 213355 60751 7.1573 7.1573 -151.712 -7.1573 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.0259928 0.0232535 202 193 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_046.v common 4.22 vpr 64.81 MiB -1 -1 0.16 18364 12 0.23 -1 -1 32416 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 32 32 303 335 1 213 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3637 1510 9620 2142 6549 929 64.8 MiB 0.06 0.00 9.78237 6.97332 -152.142 -6.97332 6.97332 0.23 0.000502106 0.00042931 0.0261794 0.0239064 -1 -1 -1 -1 26 4325 34 6.55708e+06 482200 477104. 1650.88 2.53 0.197744 0.174299 21022 109990 -1 3559 22 2010 7594 396246 94358 6.30318 6.30318 -151.607 -6.30318 0 0 585099. 2024.56 0.02 0.09 0.06 -1 -1 0.02 0.029183 0.0262317 216 209 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_047.v common 2.16 vpr 64.32 MiB -1 -1 0.15 18364 13 0.24 -1 -1 32524 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 32 32 272 304 1 187 98 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2741 1323 5723 957 4337 429 64.3 MiB 0.04 0.00 10.5096 7.47895 -154.869 -7.47895 7.47895 0.24 0.000437137 0.000400272 0.0143062 0.0131723 -1 -1 -1 -1 26 3535 21 6.55708e+06 409870 477104. 1650.88 0.54 0.0847412 0.0755315 21022 109990 -1 2816 18 1335 4235 204307 50601 6.70864 6.70864 -152.349 -6.70864 0 0 585099. 2024.56 0.02 0.05 0.07 -1 -1 0.02 0.0206862 0.0187005 188 178 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_048.v common 2.55 vpr 64.30 MiB -1 -1 0.16 18368 13 0.19 -1 -1 32404 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 32 32 271 303 1 198 105 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2854 1297 7762 1580 5576 606 64.3 MiB 0.05 0.00 9.09457 7.36601 -155.837 -7.36601 7.36601 0.23 0.000415008 0.000379214 0.0185983 0.0171236 -1 -1 -1 -1 26 3146 23 6.55708e+06 494255 477104. 1650.88 1.01 0.139015 0.12237 21022 109990 -1 2730 15 1086 3278 165110 40936 6.44432 6.44432 -147.717 -6.44432 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0184486 0.0168059 189 177 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_049.v common 3.65 vpr 64.80 MiB -1 -1 0.25 18368 12 0.22 -1 -1 32044 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66352 32 32 288 320 1 205 102 17 17 289 -1 unnamed_device 25.0 MiB 0.09 3079 1440 8670 1767 6237 666 64.8 MiB 0.05 0.00 8.89602 7.32135 -155.214 -7.32135 7.32135 0.23 0.000445433 0.000406962 0.0195291 0.0179138 -1 -1 -1 -1 26 3667 27 6.55708e+06 458090 477104. 1650.88 1.92 0.217527 0.191661 21022 109990 -1 3235 22 1404 5425 270682 64761 6.53898 6.53898 -150.672 -6.53898 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.024792 0.0223819 201 194 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_050.v common 3.79 vpr 64.84 MiB -1 -1 0.25 18752 13 0.26 -1 -1 33056 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66400 32 32 306 338 1 222 108 17 17 289 -1 unnamed_device 25.2 MiB 0.09 3151 1541 9617 2019 6835 763 64.8 MiB 0.06 0.00 10.5209 8.10463 -168.591 -8.10463 8.10463 0.23 0.000483588 0.000442669 0.0214407 0.0196021 -1 -1 -1 -1 26 4372 38 6.55708e+06 530420 477104. 1650.88 1.97 0.193338 0.171644 21022 109990 -1 3411 15 1394 4439 211034 53368 7.2801 7.2801 -161.773 -7.2801 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0212496 0.019415 223 212 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_051.v common 2.37 vpr 64.64 MiB -1 -1 0.15 18368 14 0.24 -1 -1 32696 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66192 32 32 262 294 1 188 100 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2763 1363 11700 2683 7233 1784 64.6 MiB 0.06 0.00 11.1513 8.70517 -163.209 -8.70517 8.70517 0.24 0.000445018 0.000409166 0.0237738 0.0217999 -1 -1 -1 -1 26 3751 36 6.55708e+06 433980 477104. 1650.88 0.74 0.097964 0.0871314 21022 109990 -1 2963 18 1219 3929 208524 50182 7.98142 7.98142 -159.654 -7.98142 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0219043 0.0197382 181 168 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_052.v common 3.29 vpr 64.70 MiB -1 -1 0.18 18364 13 0.23 -1 -1 32404 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 32 32 291 323 1 211 107 17 17 289 -1 unnamed_device 24.8 MiB 0.10 3299 1433 10480 2285 7646 549 64.7 MiB 0.08 0.00 11.3728 8.2812 -162.484 -8.2812 8.2812 0.23 0.000456943 0.000419163 0.0319448 0.0295537 -1 -1 -1 -1 26 4249 38 6.55708e+06 518365 477104. 1650.88 1.59 0.201052 0.17736 21022 109990 -1 3257 22 1390 4748 258559 69429 7.1579 7.1579 -156.58 -7.1579 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.0241806 0.0217837 211 197 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_053.v common 3.45 vpr 64.82 MiB -1 -1 0.25 18752 13 0.24 -1 -1 32152 -1 -1 44 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 31 32 302 334 1 217 107 17 17 289 -1 unnamed_device 24.8 MiB 0.06 3175 1433 9974 2144 6983 847 64.8 MiB 0.06 0.00 10.7693 8.14207 -165.881 -8.14207 8.14207 0.23 0.000463083 0.000424081 0.0213645 0.019549 -1 -1 -1 -1 26 3885 44 6.55708e+06 530420 477104. 1650.88 1.62 0.186609 0.164822 21022 109990 -1 3210 16 1307 4049 198045 49445 7.04936 7.04936 -156.762 -7.04936 0 0 585099. 2024.56 0.02 0.06 0.10 -1 -1 0.02 0.0220925 0.0201608 219 211 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_054.v common 3.00 vpr 64.88 MiB -1 -1 0.25 18748 12 0.28 -1 -1 32588 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66432 32 32 308 340 1 227 107 17 17 289 -1 unnamed_device 25.2 MiB 0.10 3553 1588 8456 1657 6340 459 64.9 MiB 0.05 0.00 10.5054 7.81338 -162.105 -7.81338 7.81338 0.23 0.000467261 0.0004282 0.0190897 0.0174553 -1 -1 -1 -1 30 3533 18 6.55708e+06 518365 526063. 1820.29 1.20 0.175664 0.154749 21886 126133 -1 2975 18 1181 4009 172026 42611 6.9633 6.9633 -152.154 -6.9633 0 0 666494. 2306.21 0.03 0.06 0.07 -1 -1 0.03 0.0281559 0.0255785 222 214 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_055.v common 2.30 vpr 63.96 MiB -1 -1 0.14 17984 11 0.11 -1 -1 32256 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65492 32 32 216 248 1 150 93 17 17 289 -1 unnamed_device 24.0 MiB 0.05 2172 1114 6813 1476 4649 688 64.0 MiB 0.03 0.00 7.67149 6.45472 -142.708 -6.45472 6.45472 0.23 0.000329671 0.000300919 0.0124913 0.0114155 -1 -1 -1 -1 26 2542 22 6.55708e+06 349595 477104. 1650.88 0.90 0.111032 0.0966003 21022 109990 -1 2319 13 784 2335 118482 29614 5.83766 5.83766 -144.011 -5.83766 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0132596 0.0121081 134 122 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_056.v common 2.35 vpr 64.57 MiB -1 -1 0.16 18224 13 0.19 -1 -1 31976 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 254 286 1 184 102 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2723 1225 8432 1783 5976 673 64.6 MiB 0.04 0.00 9.64721 7.76601 -160.89 -7.76601 7.76601 0.23 0.000398125 0.000364366 0.0168136 0.0153621 -1 -1 -1 -1 26 3260 44 6.55708e+06 458090 477104. 1650.88 0.72 0.0960043 0.0851036 21022 109990 -1 2668 30 1325 4578 317119 107312 7.1573 7.1573 -159.968 -7.1573 0 0 585099. 2024.56 0.02 0.10 0.06 -1 -1 0.02 0.0292682 0.0261828 175 160 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_057.v common 3.52 vpr 65.05 MiB -1 -1 0.19 19136 14 0.39 -1 -1 32632 -1 -1 47 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 338 370 1 243 111 17 17 289 -1 unnamed_device 25.8 MiB 0.09 3926 1767 7559 1351 5612 596 65.1 MiB 0.05 0.00 11.6381 8.88614 -176.77 -8.88614 8.88614 0.23 0.000538484 0.000482436 0.0186713 0.0170975 -1 -1 -1 -1 28 4757 39 6.55708e+06 566585 500653. 1732.36 1.59 0.216624 0.192218 21310 115450 -1 3846 18 1679 5489 285754 69543 7.90101 7.90101 -169.258 -7.90101 0 0 612192. 2118.31 0.02 0.07 0.06 -1 -1 0.02 0.0266501 0.0243171 256 244 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_058.v common 3.29 vpr 64.53 MiB -1 -1 0.19 18220 13 0.25 -1 -1 32408 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 271 303 1 202 100 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2981 1449 7060 1377 5094 589 64.5 MiB 0.04 0.00 9.8853 7.81987 -168.799 -7.81987 7.81987 0.23 0.000432617 0.000395853 0.0160406 0.0146835 -1 -1 -1 -1 26 3590 23 6.55708e+06 433980 477104. 1650.88 1.51 0.144757 0.127716 21022 109990 -1 3059 15 1235 3945 193279 47785 6.8803 6.8803 -158.318 -6.8803 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0195175 0.0177688 186 177 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_059.v common 2.17 vpr 64.32 MiB -1 -1 0.17 17980 11 0.15 -1 -1 32468 -1 -1 32 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65868 30 32 224 256 1 152 94 17 17 289 -1 unnamed_device 24.8 MiB 0.09 1968 1020 7762 1726 5530 506 64.3 MiB 0.05 0.00 8.50338 6.74949 -138.67 -6.74949 6.74949 0.26 0.000356161 0.00032542 0.0222888 0.0205686 -1 -1 -1 -1 24 2406 20 6.55708e+06 385760 448715. 1552.65 0.55 0.0898862 0.0798319 20734 103517 -1 2133 14 787 2459 127346 32295 5.93998 5.93998 -132.575 -5.93998 0 0 554710. 1919.41 0.02 0.04 0.06 -1 -1 0.02 0.0148732 0.0136023 150 136 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_060.v common 5.66 vpr 65.20 MiB -1 -1 0.19 19508 15 0.47 -1 -1 32024 -1 -1 49 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66760 32 32 351 383 1 261 113 17 17 289 -1 unnamed_device 25.6 MiB 0.09 3995 2010 11852 2629 8141 1082 65.2 MiB 0.07 0.00 12.8102 9.45181 -192.305 -9.45181 9.45181 0.23 0.000559457 0.000504907 0.027816 0.0253997 -1 -1 -1 -1 28 5547 42 6.55708e+06 590695 500653. 1732.36 3.63 0.240926 0.214838 21310 115450 -1 4448 19 2153 7534 412419 96794 8.64975 8.64975 -185.929 -8.64975 0 0 612192. 2118.31 0.02 0.09 0.06 -1 -1 0.02 0.0302484 0.0276287 261 257 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_061.v common 3.60 vpr 64.78 MiB -1 -1 0.29 18368 13 0.28 -1 -1 32244 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 32 32 297 329 1 206 104 17 17 289 -1 unnamed_device 25.2 MiB 0.08 3275 1492 10352 2588 6648 1116 64.8 MiB 0.06 0.00 10.6893 8.11669 -167.863 -8.11669 8.11669 0.24 0.000535712 0.000495888 0.0247164 0.0227451 -1 -1 -1 -1 28 4178 42 6.55708e+06 482200 500653. 1732.36 1.62 0.210555 0.186384 21310 115450 -1 3202 18 1377 4381 237630 56889 6.81096 6.81096 -157.796 -6.81096 0 0 612192. 2118.31 0.04 0.13 0.08 -1 -1 0.04 0.0513009 0.0464052 211 203 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_062.v common 1.74 vpr 64.33 MiB -1 -1 0.13 17980 11 0.11 -1 -1 32248 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 231 263 1 168 96 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2404 1200 5352 1082 3950 320 64.3 MiB 0.03 0.00 7.81172 6.30809 -138.848 -6.30809 6.30809 0.23 0.000345025 0.000315149 0.010973 0.0100535 -1 -1 -1 -1 26 2781 16 6.55708e+06 385760 477104. 1650.88 0.35 0.0549483 0.0486739 21022 109990 -1 2413 18 931 2920 146323 36299 5.79586 5.79586 -136.986 -5.79586 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0199369 0.0179319 149 137 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_063.v common 3.06 vpr 64.87 MiB -1 -1 0.18 18756 12 0.26 -1 -1 32492 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66428 32 32 305 337 1 209 106 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3192 1509 8106 1613 5842 651 64.9 MiB 0.06 0.00 10.8824 7.43184 -153.804 -7.43184 7.43184 0.23 0.000627827 0.000546897 0.025293 0.0233741 -1 -1 -1 -1 30 3226 28 6.55708e+06 506310 526063. 1820.29 1.36 0.221708 0.195832 21886 126133 -1 2895 17 1214 4355 186157 46002 6.47224 6.47224 -143.336 -6.47224 0 0 666494. 2306.21 0.02 0.05 0.07 -1 -1 0.02 0.0218846 0.0199037 224 211 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_064.v common 2.63 vpr 64.36 MiB -1 -1 0.16 17984 12 0.17 -1 -1 32132 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 32 32 243 275 1 185 101 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2741 1320 8326 1851 5875 600 64.4 MiB 0.04 0.00 8.98498 7.57401 -157.5 -7.57401 7.57401 0.23 0.000391939 0.000359402 0.0160215 0.0146932 -1 -1 -1 -1 28 3291 20 6.55708e+06 446035 500653. 1732.36 0.96 0.120985 0.106511 21310 115450 -1 2704 18 1002 3193 154404 38429 6.70098 6.70098 -151.983 -6.70098 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0183839 0.0166494 160 149 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_065.v common 2.00 vpr 64.36 MiB -1 -1 0.15 17976 12 0.16 -1 -1 32424 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 30 32 228 260 1 158 96 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2463 1057 6009 1165 4395 449 64.4 MiB 0.03 0.00 9.70233 7.10808 -144.903 -7.10808 7.10808 0.23 0.000361721 0.000331358 0.0122651 0.0112354 -1 -1 -1 -1 20 2487 24 6.55708e+06 409870 394039. 1363.46 0.49 0.061774 0.0548534 19870 87366 -1 2323 17 852 2864 148607 36739 6.46058 6.46058 -142.134 -6.46058 0 0 477104. 1650.88 0.02 0.04 0.05 -1 -1 0.02 0.0165964 0.0150485 151 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_066.v common 2.62 vpr 64.75 MiB -1 -1 0.18 18364 12 0.25 -1 -1 32836 -1 -1 41 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 29 32 275 307 1 195 102 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2776 1290 7956 1517 5875 564 64.8 MiB 0.04 0.00 9.75944 6.89912 -129.506 -6.89912 6.89912 0.23 0.000439187 0.000401806 0.0176508 0.016155 -1 -1 -1 -1 26 3296 19 6.55708e+06 494255 477104. 1650.88 0.94 0.140672 0.123405 21022 109990 -1 2817 17 1189 4151 205219 50431 6.27364 6.27364 -125.715 -6.27364 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0217945 0.0198656 198 190 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_067.v common 4.15 vpr 64.46 MiB -1 -1 0.20 18364 13 0.35 -1 -1 32304 -1 -1 50 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 330 362 1 232 114 17 17 289 -1 unnamed_device 25.2 MiB 0.13 3249 1646 11706 2331 8577 798 64.5 MiB 0.07 0.00 10.166 8.087 -174.968 -8.087 8.087 0.23 0.000504128 0.00046231 0.0252032 0.0230892 -1 -1 -1 -1 26 4440 49 6.55708e+06 602750 477104. 1650.88 2.09 0.265695 0.235973 21022 109990 -1 3658 31 2107 6976 387104 114321 7.6773 7.6773 -175.999 -7.6773 0 0 585099. 2024.56 0.02 0.16 0.06 -1 -1 0.02 0.0585253 0.0524828 247 236 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_068.v common 3.05 vpr 64.17 MiB -1 -1 0.20 18364 12 0.21 -1 -1 32352 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 290 322 1 203 104 17 17 289 -1 unnamed_device 24.4 MiB 0.10 3300 1279 10352 2652 6577 1123 64.2 MiB 0.07 0.00 10.7679 7.73832 -150.742 -7.73832 7.73832 0.25 0.000467737 0.000428655 0.0302749 0.0280738 -1 -1 -1 -1 28 3491 20 6.55708e+06 482200 500653. 1732.36 1.23 0.162438 0.144317 21310 115450 -1 2895 16 1315 4243 219437 55418 6.8405 6.8405 -146.978 -6.8405 0 0 612192. 2118.31 0.04 0.09 0.07 -1 -1 0.04 0.035537 0.0323181 206 196 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_069.v common 2.48 vpr 64.25 MiB -1 -1 0.14 17984 12 0.13 -1 -1 32928 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 214 246 1 156 95 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2480 1130 5927 1103 4408 416 64.2 MiB 0.03 0.00 9.31584 7.04661 -144.877 -7.04661 7.04661 0.24 0.000339655 0.000310041 0.0115631 0.010563 -1 -1 -1 -1 26 2534 18 6.55708e+06 373705 477104. 1650.88 1.07 0.122005 0.106406 21022 109990 -1 2279 18 854 2634 133675 33889 5.97718 5.97718 -136.774 -5.97718 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0161625 0.0146372 135 120 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_070.v common 2.62 vpr 64.46 MiB -1 -1 0.16 18368 12 0.19 -1 -1 31944 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 31 32 244 276 1 170 98 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2617 1274 6398 1159 4710 529 64.5 MiB 0.03 0.00 9.56447 7.57061 -150.375 -7.57061 7.57061 0.24 0.00038161 0.000349434 0.0132809 0.0121488 -1 -1 -1 -1 28 3024 18 6.55708e+06 421925 500653. 1732.36 1.06 0.135071 0.118552 21310 115450 -1 2560 16 918 3190 159899 38980 6.2813 6.2813 -142.114 -6.2813 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0199613 0.0181369 161 153 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_071.v common 3.01 vpr 64.17 MiB -1 -1 0.26 18368 11 0.17 -1 -1 32488 -1 -1 40 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 30 32 276 308 1 199 102 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2727 1365 7242 1318 5567 357 64.2 MiB 0.05 0.00 8.59664 6.98252 -137.845 -6.98252 6.98252 0.24 0.000452447 0.000411507 0.0193183 0.0178012 -1 -1 -1 -1 26 3630 40 6.55708e+06 482200 477104. 1650.88 1.29 0.156421 0.137889 21022 109990 -1 3067 18 1183 4172 215666 51876 6.07244 6.07244 -134.218 -6.07244 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0227691 0.0204083 194 188 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_072.v common 2.85 vpr 64.55 MiB -1 -1 0.17 17980 11 0.18 -1 -1 32268 -1 -1 36 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 28 32 253 285 1 177 96 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2506 1211 8199 1748 5508 943 64.6 MiB 0.05 0.00 8.69997 6.71295 -129.325 -6.71295 6.71295 0.23 0.00042684 0.000393932 0.0228206 0.0211229 -1 -1 -1 -1 30 2524 16 6.55708e+06 433980 526063. 1820.29 1.18 0.162297 0.142794 21886 126133 -1 2281 16 880 3154 140107 34317 5.85898 5.85898 -123.314 -5.85898 0 0 666494. 2306.21 0.04 0.08 0.08 -1 -1 0.04 0.0371708 0.0335976 176 171 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_073.v common 2.11 vpr 64.43 MiB -1 -1 0.16 18364 13 0.18 -1 -1 31916 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 30 32 235 267 1 166 98 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2275 1124 7748 1646 5543 559 64.4 MiB 0.06 0.00 10.228 7.79233 -143.293 -7.79233 7.79233 0.24 0.000882547 0.000817551 0.0271881 0.0254 -1 -1 -1 -1 26 2682 22 6.55708e+06 433980 477104. 1650.88 0.39 0.0872149 0.0781979 21022 109990 -1 2310 16 922 3336 150513 38472 6.8039 6.8039 -136.548 -6.8039 0 0 585099. 2024.56 0.04 0.06 0.09 -1 -1 0.04 0.0265682 0.0241882 157 147 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_074.v common 2.88 vpr 64.63 MiB -1 -1 0.18 18364 12 0.25 -1 -1 32276 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66180 32 32 264 296 1 187 100 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2846 1273 10540 2582 6897 1061 64.6 MiB 0.05 0.00 9.32034 7.41947 -161.03 -7.41947 7.41947 0.24 0.000416783 0.000381574 0.0215499 0.0196879 -1 -1 -1 -1 28 3178 43 6.55708e+06 433980 500653. 1732.36 1.13 0.150714 0.132237 21310 115450 -1 2752 18 1030 3249 171987 42405 6.2003 6.2003 -148.62 -6.2003 0 0 612192. 2118.31 0.02 0.05 0.08 -1 -1 0.02 0.019547 0.0176734 180 170 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_075.v common 2.19 vpr 64.74 MiB -1 -1 0.16 18000 13 0.26 -1 -1 32444 -1 -1 41 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 31 32 278 310 1 197 104 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2948 1285 6204 1121 4455 628 64.7 MiB 0.04 0.00 10.4607 8.33266 -159.321 -8.33266 8.33266 0.23 0.000450174 0.000413364 0.0161966 0.0149247 -1 -1 -1 -1 26 3400 25 6.55708e+06 494255 477104. 1650.88 0.51 0.0828088 0.0735628 21022 109990 -1 2719 17 1068 3376 157383 40304 7.28976 7.28976 -154.47 -7.28976 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0220486 0.0201017 196 187 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_076.v common 2.83 vpr 64.76 MiB -1 -1 0.18 18368 14 0.23 -1 -1 32384 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 32 32 290 322 1 201 102 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2948 1449 9860 2172 6855 833 64.8 MiB 0.05 0.00 10.9465 8.71544 -176.837 -8.71544 8.71544 0.34 0.000453693 0.000415773 0.0221562 0.02036 -1 -1 -1 -1 26 3548 21 6.55708e+06 458090 477104. 1650.88 1.07 0.149225 0.13138 21022 109990 -1 2951 16 1100 3513 167818 41879 7.92796 7.92796 -172.589 -7.92796 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0203231 0.0184758 203 196 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_077.v common 2.31 vpr 64.68 MiB -1 -1 0.18 18748 14 0.23 -1 -1 32424 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 269 301 1 187 100 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2291 1303 7756 1442 5636 678 64.7 MiB 0.04 0.00 10.3699 8.36955 -159.159 -8.36955 8.36955 0.23 0.000433687 0.000393612 0.0182587 0.0167452 -1 -1 -1 -1 26 3430 22 6.55708e+06 433980 477104. 1650.88 0.64 0.0842795 0.0747516 21022 109990 -1 2830 19 1184 4577 262704 74075 7.20936 7.20936 -150.018 -7.20936 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.0285986 0.0255366 179 175 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_078.v common 3.05 vpr 64.75 MiB -1 -1 0.20 18752 13 0.30 -1 -1 32616 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 296 328 1 216 108 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3246 1544 7561 1452 5398 711 64.7 MiB 0.05 0.00 10.7252 8.52515 -170.673 -8.52515 8.52515 0.24 0.000599389 0.000558386 0.0190979 0.0176173 -1 -1 -1 -1 30 3404 28 6.55708e+06 530420 526063. 1820.29 1.22 0.159177 0.140846 21886 126133 -1 3028 17 1199 4291 182956 46284 7.56735 7.56735 -161.205 -7.56735 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0223292 0.0203908 212 202 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_079.v common 2.70 vpr 64.03 MiB -1 -1 0.16 17984 13 0.16 -1 -1 32448 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65568 30 32 234 266 1 169 96 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2265 1134 4695 742 3633 320 64.0 MiB 0.03 0.00 10.2529 7.95464 -161.944 -7.95464 7.95464 0.24 0.000503181 0.00047225 0.0126481 0.0117035 -1 -1 -1 -1 28 2792 17 6.55708e+06 409870 500653. 1732.36 1.03 0.115548 0.101979 21310 115450 -1 2338 16 791 2338 113501 28721 6.77538 6.77538 -150.108 -6.77538 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0215635 0.0196967 155 146 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_080.v common 3.66 vpr 64.75 MiB -1 -1 0.30 18748 13 0.40 -1 -1 32412 -1 -1 42 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66308 30 32 291 323 1 211 104 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2984 1412 9376 2164 6142 1070 64.8 MiB 0.05 0.00 10.8675 8.7665 -166.076 -8.7665 8.7665 0.25 0.00048301 0.000435282 0.0216956 0.0198322 -1 -1 -1 -1 28 4440 36 6.55708e+06 506310 500653. 1732.36 1.52 0.195156 0.172406 21310 115450 -1 3306 22 1808 6039 308441 75318 8.13116 8.13116 -164.886 -8.13116 0 0 612192. 2118.31 0.02 0.12 0.06 -1 -1 0.02 0.0480109 0.0432038 211 203 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_081.v common 3.33 vpr 64.71 MiB -1 -1 0.17 18364 14 0.36 -1 -1 32276 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 32 32 274 306 1 188 100 17 17 289 -1 unnamed_device 24.8 MiB 0.11 2874 1381 6828 1358 4978 492 64.7 MiB 0.04 0.00 10.16 8.0528 -168.058 -8.0528 8.0528 0.26 0.000433477 0.000396437 0.0159878 0.0146877 -1 -1 -1 -1 26 3440 29 6.55708e+06 433980 477104. 1650.88 1.31 0.163675 0.144893 21022 109990 -1 2924 17 1120 4094 202887 49196 7.29236 7.29236 -160.792 -7.29236 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.021869 0.0198747 188 180 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_082.v common 2.44 vpr 64.65 MiB -1 -1 0.17 18368 13 0.20 -1 -1 32416 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 31 32 266 298 1 188 103 17 17 289 -1 unnamed_device 25.2 MiB 0.05 2648 1278 6851 1303 5218 330 64.7 MiB 0.06 0.00 9.79664 7.73626 -147.024 -7.73626 7.73626 0.26 0.000753216 0.000687884 0.0256158 0.0234295 -1 -1 -1 -1 26 3475 22 6.55708e+06 482200 477104. 1650.88 0.78 0.106799 0.0961352 21022 109990 -1 2882 21 1188 3871 201792 49498 6.6419 6.6419 -139.849 -6.6419 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0230652 0.0209088 189 175 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_083.v common 2.84 vpr 64.66 MiB -1 -1 0.17 18368 13 0.19 -1 -1 32276 -1 -1 42 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 30 32 266 298 1 198 104 17 17 289 -1 unnamed_device 25.3 MiB 0.08 3212 1451 7180 1397 5391 392 64.7 MiB 0.04 0.00 9.98558 8.08209 -153.888 -8.08209 8.08209 0.24 0.00041428 0.000379794 0.0146925 0.0134878 -1 -1 -1 -1 30 3135 19 6.55708e+06 506310 526063. 1820.29 1.15 0.133595 0.117686 21886 126133 -1 2656 16 1001 3565 158345 38941 6.8803 6.8803 -143.947 -6.8803 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0190113 0.0173463 188 178 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_084.v common 3.35 vpr 64.14 MiB -1 -1 0.17 18748 14 0.32 -1 -1 32436 -1 -1 45 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 310 342 1 226 109 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3591 1582 8689 1758 6168 763 64.1 MiB 0.06 0.00 10.8164 8.74282 -175.793 -8.74282 8.74282 0.24 0.000619421 0.000577581 0.0244264 0.0226096 -1 -1 -1 -1 28 3859 21 6.55708e+06 542475 500653. 1732.36 1.59 0.224812 0.199302 21310 115450 -1 3320 22 1569 5205 250249 62085 7.80069 7.80069 -168.216 -7.80069 0 0 612192. 2118.31 0.02 0.07 0.06 -1 -1 0.02 0.0269125 0.0242969 225 216 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_085.v common 2.20 vpr 64.32 MiB -1 -1 0.18 18368 11 0.24 -1 -1 32232 -1 -1 44 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 262 294 1 199 105 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3052 1320 8997 1938 5901 1158 64.3 MiB 0.05 0.00 10.039 7.47594 -139.521 -7.47594 7.47594 0.25 0.000443441 0.000400928 0.0210946 0.019397 -1 -1 -1 -1 28 3433 19 6.55708e+06 530420 500653. 1732.36 0.49 0.0838839 0.0748833 21310 115450 -1 2860 19 1167 3779 180535 45529 6.59044 6.59044 -133.662 -6.59044 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0217172 0.0197123 187 177 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_086.v common 1.76 vpr 64.29 MiB -1 -1 0.15 17452 13 0.14 -1 -1 32192 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 222 254 1 166 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2365 1134 8198 1752 5856 590 64.3 MiB 0.04 0.00 9.5772 7.60931 -162.659 -7.60931 7.60931 0.23 0.000354996 0.000325193 0.0199103 0.018532 -1 -1 -1 -1 26 2640 18 6.55708e+06 409870 477104. 1650.88 0.33 0.0653865 0.0584309 21022 109990 -1 2286 15 824 2298 113671 28726 6.82684 6.82684 -156.225 -6.82684 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0146309 0.01333 138 128 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_087.v common 2.89 vpr 64.68 MiB -1 -1 0.16 18752 14 0.32 -1 -1 32396 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 267 299 1 189 101 17 17 289 -1 unnamed_device 24.8 MiB 0.10 2654 1253 5741 1095 4066 580 64.7 MiB 0.03 0.00 10.1014 8.22497 -162.245 -8.22497 8.22497 0.23 0.000420987 0.000385592 0.0129977 0.0119483 -1 -1 -1 -1 28 3525 29 6.55708e+06 446035 500653. 1732.36 1.12 0.138603 0.121855 21310 115450 -1 2791 16 995 3352 161293 40081 7.37336 7.37336 -157.789 -7.37336 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0199676 0.0181409 183 173 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_088.v common 4.09 vpr 65.06 MiB -1 -1 0.18 18740 15 0.41 -1 -1 32468 -1 -1 50 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66624 32 32 334 366 1 242 114 17 17 289 -1 unnamed_device 25.6 MiB 0.10 3845 1754 10878 2260 7829 789 65.1 MiB 0.07 0.00 12.4201 9.30007 -197.166 -9.30007 9.30007 0.25 0.00073948 0.000685983 0.0295529 0.0270958 -1 -1 -1 -1 26 4755 36 6.55708e+06 602750 477104. 1650.88 2.09 0.22201 0.19724 21022 109990 -1 3923 19 1866 5993 314116 76247 8.60335 8.60335 -194.026 -8.60335 0 0 585099. 2024.56 0.02 0.10 0.06 -1 -1 0.02 0.0383912 0.0348739 250 240 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_089.v common 2.17 vpr 64.28 MiB -1 -1 0.18 17984 11 0.14 -1 -1 32264 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65824 32 32 220 252 1 154 97 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2168 1074 8977 1935 6287 755 64.3 MiB 0.04 0.00 8.59479 6.66858 -139.589 -6.66858 6.66858 0.23 0.000338532 0.000309224 0.0167458 0.015295 -1 -1 -1 -1 26 2415 19 6.55708e+06 397815 477104. 1650.88 0.66 0.0991471 0.0868577 21022 109990 -1 2246 16 755 2442 124269 30281 5.94258 5.94258 -136.678 -5.94258 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0148758 0.0135052 142 126 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_090.v common 2.99 vpr 64.48 MiB -1 -1 0.15 17984 12 0.16 -1 -1 32296 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 31 32 244 276 1 183 99 17 17 289 -1 unnamed_device 24.7 MiB 0.06 2718 1278 7623 1628 5411 584 64.5 MiB 0.04 0.00 9.30618 7.4792 -158.92 -7.4792 7.4792 0.23 0.000382061 0.000343151 0.0153388 0.0139891 -1 -1 -1 -1 26 3486 19 6.55708e+06 433980 477104. 1650.88 1.45 0.150081 0.132485 21022 109990 -1 2982 15 1147 3679 189997 47278 6.26704 6.26704 -150.559 -6.26704 0 0 585099. 2024.56 0.03 0.05 0.07 -1 -1 0.03 0.0191888 0.0175386 165 153 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_091.v common 3.49 vpr 64.71 MiB -1 -1 0.18 18368 12 0.26 -1 -1 32432 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 32 32 300 332 1 217 108 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3275 1622 10645 2328 7422 895 64.7 MiB 0.08 0.00 10.2612 7.59364 -164.56 -7.59364 7.59364 0.24 0.000486686 0.000442889 0.0386317 0.0358231 -1 -1 -1 -1 34 3724 22 6.55708e+06 530420 585099. 2024.56 1.66 0.233929 0.207628 22462 138074 -1 3411 16 1421 4778 241051 58262 6.6811 6.6811 -156.408 -6.6811 0 0 742403. 2568.87 0.04 0.10 0.08 -1 -1 0.04 0.03612 0.0328032 217 206 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_092.v common 3.37 vpr 64.69 MiB -1 -1 0.18 18604 12 0.21 -1 -1 32768 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 32 32 271 303 1 200 105 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3003 1380 8750 1810 6138 802 64.7 MiB 0.05 0.00 9.79464 7.36891 -159.112 -7.36891 7.36891 0.23 0.000426637 0.000390945 0.017895 0.0164169 -1 -1 -1 -1 24 4116 29 6.55708e+06 494255 448715. 1552.65 1.71 0.160092 0.141723 20734 103517 -1 3365 25 1982 7225 408926 104160 6.75244 6.75244 -158.639 -6.75244 0 0 554710. 1919.41 0.02 0.09 0.06 -1 -1 0.02 0.025969 0.0232829 190 177 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_093.v common 4.60 vpr 64.64 MiB -1 -1 0.18 19136 14 0.42 -1 -1 32440 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 327 359 1 229 108 17 17 289 -1 unnamed_device 25.3 MiB 0.09 3556 1590 6276 1065 4786 425 64.6 MiB 0.05 0.00 11.4017 8.85831 -179.658 -8.85831 8.85831 0.23 0.00100888 0.000964631 0.0195122 0.0181514 -1 -1 -1 -1 26 4696 36 6.55708e+06 530420 477104. 1650.88 2.70 0.216563 0.19256 21022 109990 -1 3722 21 1876 6496 326439 79639 7.96009 7.96009 -172.069 -7.96009 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.0285679 0.0258669 239 233 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_094.v common 2.94 vpr 64.52 MiB -1 -1 0.16 18364 12 0.18 -1 -1 32224 -1 -1 35 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 30 32 246 278 1 176 97 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2728 1268 8755 2050 5708 997 64.5 MiB 0.05 0.00 10.0467 7.41486 -143.807 -7.41486 7.41486 0.24 0.00040521 0.000366057 0.0205555 0.0189281 -1 -1 -1 -1 28 3102 24 6.55708e+06 421925 500653. 1732.36 1.32 0.176868 0.155997 21310 115450 -1 2547 27 942 3467 228891 85010 6.50684 6.50684 -134.136 -6.50684 0 0 612192. 2118.31 0.02 0.08 0.06 -1 -1 0.02 0.0271277 0.0243958 166 158 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_095.v common 2.40 vpr 64.17 MiB -1 -1 0.15 17980 11 0.16 -1 -1 31856 -1 -1 31 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 27 32 219 251 1 153 90 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2075 890 11346 2674 7241 1431 64.2 MiB 0.05 0.00 8.56235 6.47229 -119.898 -6.47229 6.47229 0.23 0.000341003 0.000311104 0.0216579 0.0197916 -1 -1 -1 -1 28 2291 17 6.55708e+06 373705 500653. 1732.36 0.84 0.110181 0.0967621 21310 115450 -1 1920 17 832 2771 122094 32173 5.80812 5.80812 -117.51 -5.80812 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0160773 0.0145507 146 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_096.v common 3.17 vpr 65.43 MiB -1 -1 0.30 19132 13 0.39 -1 -1 32616 -1 -1 54 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67004 32 32 380 412 1 274 118 17 17 289 -1 unnamed_device 25.5 MiB 0.10 4655 2221 11100 2341 7945 814 65.4 MiB 0.09 0.00 10.8384 8.21927 -169.077 -8.21927 8.21927 0.23 0.000611341 0.000552744 0.0377977 0.0348813 -1 -1 -1 -1 30 5210 32 6.55708e+06 650970 526063. 1820.29 1.10 0.160347 0.144658 21886 126133 -1 4272 20 1942 7051 322540 77378 7.23124 7.23124 -159.615 -7.23124 0 0 666494. 2306.21 0.02 0.08 0.07 -1 -1 0.02 0.031786 0.028998 289 286 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_097.v common 2.30 vpr 64.73 MiB -1 -1 0.17 18368 14 0.22 -1 -1 32316 -1 -1 41 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 31 32 277 309 1 197 104 17 17 289 -1 unnamed_device 25.2 MiB 0.06 3097 1274 12304 3037 7768 1499 64.7 MiB 0.06 0.00 12.2136 8.62006 -170.085 -8.62006 8.62006 0.24 0.000432138 0.000396089 0.0252147 0.0231002 -1 -1 -1 -1 26 3603 32 6.55708e+06 494255 477104. 1650.88 0.68 0.106179 0.0939771 21022 109990 -1 2789 17 1209 3625 176693 45658 7.45942 7.45942 -162.283 -7.45942 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0202702 0.0183759 202 186 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_098.v common 1.86 vpr 64.37 MiB -1 -1 0.16 18360 12 0.15 -1 -1 32220 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 229 261 1 169 98 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2364 1167 6398 1184 4756 458 64.4 MiB 0.04 0.00 10.1826 7.64801 -160.064 -7.64801 7.64801 0.23 0.00048408 0.000452387 0.0138589 0.0127355 -1 -1 -1 -1 26 2856 21 6.55708e+06 409870 477104. 1650.88 0.37 0.0640324 0.0568082 21022 109990 -1 2410 15 851 2669 125206 31603 6.5589 6.5589 -149.274 -6.5589 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0155306 0.0141676 149 135 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_099.v common 3.16 vpr 64.67 MiB -1 -1 0.18 18364 13 0.25 -1 -1 31888 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 32 32 263 295 1 192 101 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2878 1329 9971 1977 6864 1130 64.7 MiB 0.05 0.00 10.3391 7.91544 -159.644 -7.91544 7.91544 0.23 0.000426804 0.0003908 0.0210623 0.0192623 -1 -1 -1 -1 28 3543 34 6.55708e+06 446035 500653. 1732.36 1.25 0.163021 0.144227 21310 115450 -1 2890 17 1266 4303 210367 52177 6.7993 6.7993 -152.562 -6.7993 0 0 612192. 2118.31 0.02 0.06 0.08 -1 -1 0.02 0.0235242 0.0211813 177 169 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_100.v common 3.61 vpr 64.95 MiB -1 -1 0.17 18748 13 0.29 -1 -1 32496 -1 -1 48 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66504 31 32 321 353 1 234 111 17 17 289 -1 unnamed_device 25.6 MiB 0.08 3400 1604 9953 2030 7063 860 64.9 MiB 0.06 0.00 9.6468 7.26834 -148.565 -7.26834 7.26834 0.23 0.000503324 0.000461623 0.0225716 0.0206576 -1 -1 -1 -1 26 4462 29 6.55708e+06 578640 477104. 1650.88 1.84 0.204323 0.180668 21022 109990 -1 3651 20 2029 6761 360098 85834 6.67706 6.67706 -150.677 -6.67706 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.0263633 0.0238787 242 230 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_101.v common 2.43 vpr 64.31 MiB -1 -1 0.21 17984 11 0.22 -1 -1 32456 -1 -1 43 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 30 32 287 319 1 198 105 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3001 1293 11220 2634 7278 1308 64.3 MiB 0.14 0.00 9.47524 7.25311 -136.619 -7.25311 7.25311 0.25 0.00121921 0.00112523 0.0612861 0.0568716 -1 -1 -1 -1 30 2864 16 6.55708e+06 518365 526063. 1820.29 0.60 0.154135 0.140337 21886 126133 -1 2537 18 972 3930 165233 40913 6.35004 6.35004 -128.389 -6.35004 0 0 666494. 2306.21 0.03 0.06 0.07 -1 -1 0.03 0.0273439 0.0245502 207 199 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_102.v common 2.56 vpr 64.80 MiB -1 -1 0.18 18752 15 0.33 -1 -1 32512 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66360 32 32 296 328 1 208 101 17 17 289 -1 unnamed_device 24.8 MiB 0.11 3400 1425 8326 1756 5851 719 64.8 MiB 0.05 0.00 12.6428 9.11323 -184.154 -9.11323 9.11323 0.23 0.00050701 0.000465418 0.0201741 0.0184292 -1 -1 -1 -1 26 3950 24 6.55708e+06 446035 477104. 1650.88 0.61 0.0902455 0.0803698 21022 109990 -1 3244 16 1338 4712 234668 58393 7.97942 7.97942 -176.46 -7.97942 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0212655 0.0193666 207 202 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_103.v common 3.78 vpr 64.78 MiB -1 -1 0.18 18752 13 0.31 -1 -1 32440 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 32 32 285 317 1 204 102 17 17 289 -1 unnamed_device 25.2 MiB 0.12 3131 1495 5338 899 4142 297 64.8 MiB 0.03 0.00 10.6725 8.26703 -174.041 -8.26703 8.26703 0.24 0.000462099 0.000423406 0.0133165 0.0122552 -1 -1 -1 -1 28 4046 41 6.55708e+06 458090 500653. 1732.36 1.93 0.213209 0.188425 21310 115450 -1 3146 16 1246 4278 217929 53207 7.2409 7.2409 -163.588 -7.2409 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0212515 0.0193558 202 191 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_104.v common 2.00 vpr 64.46 MiB -1 -1 0.18 17984 12 0.18 -1 -1 32132 -1 -1 41 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 29 32 239 271 1 178 102 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2844 1190 7956 1682 5619 655 64.5 MiB 0.04 0.00 10.6983 7.98398 -159.232 -7.98398 7.98398 0.24 0.000371108 0.000339729 0.0153222 0.014034 -1 -1 -1 -1 26 3200 29 6.55708e+06 494255 477104. 1650.88 0.45 0.0732874 0.0649933 21022 109990 -1 2709 20 1104 3239 159893 40584 7.1573 7.1573 -156.73 -7.1573 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0188511 0.0170473 168 154 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_105.v common 2.75 vpr 63.94 MiB -1 -1 0.16 18368 11 0.13 -1 -1 32292 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 32 32 235 267 1 176 98 17 17 289 -1 unnamed_device 24.1 MiB 0.05 2767 1260 7298 1447 5288 563 63.9 MiB 0.05 0.00 9.23769 6.98988 -143.739 -6.98988 6.98988 0.34 0.000348314 0.000318582 0.018582 0.0170113 -1 -1 -1 -1 26 3168 19 6.55708e+06 409870 477104. 1650.88 1.13 0.150939 0.133035 21022 109990 -1 2729 16 1008 3088 154235 38775 6.31284 6.31284 -144.7 -6.31284 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0156476 0.0142051 155 141 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_106.v common 2.74 vpr 64.85 MiB -1 -1 0.17 18368 13 0.29 -1 -1 32432 -1 -1 44 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66404 31 32 294 326 1 211 107 17 17 289 -1 unnamed_device 24.8 MiB 0.11 3439 1453 7444 1510 5262 672 64.8 MiB 0.06 0.00 10.2189 7.97431 -160.47 -7.97431 7.97431 0.36 0.000708924 0.000639099 0.0251625 0.0230048 -1 -1 -1 -1 28 3874 29 6.55708e+06 530420 500653. 1732.36 0.63 0.105132 0.0937956 21310 115450 -1 3104 16 1212 4206 205123 50684 7.4003 7.4003 -160.122 -7.4003 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0211131 0.0192249 211 203 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_107.v common 2.44 vpr 64.32 MiB -1 -1 0.20 17972 10 0.18 -1 -1 32220 -1 -1 35 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 219 251 1 150 96 17 17 289 -1 unnamed_device 24.8 MiB 0.06 1946 1061 5790 1112 4104 574 64.3 MiB 0.04 0.00 7.37011 6.00295 -119.764 -6.00295 6.00295 0.25 0.00035911 0.000329803 0.0191472 0.0177945 -1 -1 -1 -1 26 2502 24 6.55708e+06 421925 477104. 1650.88 0.86 0.117586 0.103676 21022 109990 -1 2062 17 806 2797 128453 31706 5.21312 5.21312 -114.473 -5.21312 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0158314 0.0142786 147 134 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_108.v common 2.22 vpr 64.45 MiB -1 -1 0.18 17980 14 0.17 -1 -1 32276 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 239 271 1 173 98 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2734 1213 7073 1458 5059 556 64.5 MiB 0.05 0.00 11.0242 8.4809 -168.731 -8.4809 8.4809 0.33 0.000366617 0.000335327 0.0184044 0.0169477 -1 -1 -1 -1 26 3090 29 6.55708e+06 409870 477104. 1650.88 0.58 0.101652 0.0904075 21022 109990 -1 2658 16 969 3018 149359 37853 7.24455 7.24455 -157.889 -7.24455 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0163044 0.0148298 156 145 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_109.v common 2.81 vpr 64.29 MiB -1 -1 0.18 18752 13 0.24 -1 -1 32408 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 31 32 266 298 1 193 103 17 17 289 -1 unnamed_device 24.8 MiB 0.09 3161 1363 8538 1729 6172 637 64.3 MiB 0.05 0.00 10.4036 7.97301 -166.024 -7.97301 7.97301 0.24 0.000424703 0.000382451 0.024452 0.0226427 -1 -1 -1 -1 26 3263 23 6.55708e+06 482200 477104. 1650.88 1.15 0.195819 0.172559 21022 109990 -1 2818 15 1049 3322 160900 40390 6.8803 6.8803 -152.18 -6.8803 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0178379 0.0162423 188 175 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_110.v common 2.58 vpr 64.30 MiB -1 -1 0.21 17984 12 0.13 -1 -1 32200 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 31 32 225 257 1 161 97 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2415 1133 6757 1438 4598 721 64.3 MiB 0.03 0.00 9.26878 7.00946 -143.372 -7.00946 7.00946 0.23 0.000349322 0.000319975 0.0126652 0.0116002 -1 -1 -1 -1 26 2691 23 6.55708e+06 409870 477104. 1650.88 0.96 0.107657 0.0948875 21022 109990 -1 2292 17 845 2615 133353 32686 6.23184 6.23184 -137.649 -6.23184 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0283693 0.0256193 145 134 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_111.v common 2.97 vpr 64.77 MiB -1 -1 0.22 17980 12 0.18 -1 -1 33052 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 288 320 1 205 105 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3231 1460 9244 1928 6414 902 64.8 MiB 0.07 0.00 9.79864 7.07814 -148.913 -7.07814 7.07814 0.27 0.000569668 0.000527241 0.0282744 0.0260291 -1 -1 -1 -1 28 3623 19 6.55708e+06 494255 500653. 1732.36 1.21 0.175311 0.154218 21310 115450 -1 3038 18 1249 4669 234810 56737 6.41878 6.41878 -147.502 -6.41878 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0237192 0.021482 206 194 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_112.v common 3.31 vpr 64.61 MiB -1 -1 0.19 18740 13 0.29 -1 -1 32356 -1 -1 38 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 31 32 282 314 1 202 101 17 17 289 -1 unnamed_device 24.8 MiB 0.10 3277 1590 6681 1310 4868 503 64.6 MiB 0.04 0.00 10.7471 8.73972 -167.897 -8.73972 8.73972 0.23 0.000460535 0.000422889 0.0162374 0.0149525 -1 -1 -1 -1 28 3932 24 6.55708e+06 458090 500653. 1732.36 1.51 0.16573 0.146424 21310 115450 -1 3256 15 1195 4023 206433 49925 7.28716 7.28716 -157.96 -7.28716 0 0 612192. 2118.31 0.02 0.06 0.07 -1 -1 0.02 0.0254841 0.02301 201 191 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_113.v common 1.99 vpr 64.38 MiB -1 -1 0.19 17984 11 0.16 -1 -1 32248 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 233 265 1 176 99 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2465 1216 7395 1434 5485 476 64.4 MiB 0.04 0.00 8.01481 6.6836 -143.167 -6.6836 6.6836 0.23 0.000354533 0.00032415 0.0139007 0.0127385 -1 -1 -1 -1 26 2889 24 6.55708e+06 421925 477104. 1650.88 0.40 0.0652603 0.0578256 21022 109990 -1 2427 20 1207 3730 171289 43329 5.71184 5.71184 -135.745 -5.71184 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0233234 0.0209333 152 139 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_114.v common 2.17 vpr 64.54 MiB -1 -1 0.22 17980 13 0.22 -1 -1 32172 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 32 32 254 286 1 183 102 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2879 1214 6528 1147 5041 340 64.5 MiB 0.04 0.00 10.6786 7.73627 -160.675 -7.73627 7.73627 0.25 0.000409177 0.000375614 0.0135402 0.0124612 -1 -1 -1 -1 26 2886 16 6.55708e+06 458090 477104. 1650.88 0.39 0.0686872 0.0611683 21022 109990 -1 2556 28 1471 5017 296309 110070 6.74524 6.74524 -153.355 -6.74524 0 0 585099. 2024.56 0.02 0.09 0.06 -1 -1 0.02 0.0258403 0.0231684 170 160 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_115.v common 3.18 vpr 64.73 MiB -1 -1 0.25 18368 13 0.32 -1 -1 32408 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 32 32 285 317 1 211 105 17 17 289 -1 unnamed_device 25.3 MiB 0.10 3339 1491 8503 1758 5902 843 64.7 MiB 0.05 0.00 10.8748 7.88135 -168.607 -7.88135 7.88135 0.37 0.000513341 0.000475271 0.0182779 0.0167377 -1 -1 -1 -1 28 3856 19 6.55708e+06 494255 500653. 1732.36 1.11 0.135527 0.119597 21310 115450 -1 3156 16 1241 3837 184163 45729 6.9979 6.9979 -160.864 -6.9979 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0198868 0.0181274 203 191 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_116.v common 2.49 vpr 64.50 MiB -1 -1 0.18 18368 11 0.26 -1 -1 32416 -1 -1 36 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 29 32 243 275 1 174 97 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2558 1138 10309 2535 6640 1134 64.5 MiB 0.06 0.00 9.92175 6.74749 -129.645 -6.74749 6.74749 0.30 0.000772465 0.000712951 0.0260806 0.0238587 -1 -1 -1 -1 26 3126 32 6.55708e+06 433980 477104. 1650.88 0.67 0.0939845 0.0839562 21022 109990 -1 2578 17 931 3325 169042 40480 6.05818 6.05818 -124.542 -6.05818 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0184457 0.0167471 161 158 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_117.v common 4.27 vpr 64.39 MiB -1 -1 0.29 19136 14 0.31 -1 -1 33084 -1 -1 49 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 318 350 1 238 113 17 17 289 -1 unnamed_device 25.0 MiB 0.10 3835 1720 13490 3177 9101 1212 64.4 MiB 0.09 0.00 11.3374 8.61726 -184.782 -8.61726 8.61726 0.38 0.000531117 0.000488117 0.0381217 0.0350571 -1 -1 -1 -1 26 4747 29 6.55708e+06 590695 477104. 1650.88 1.96 0.210063 0.187395 21022 109990 -1 3847 17 1619 5028 258599 64735 7.6387 7.6387 -177.864 -7.6387 0 0 585099. 2024.56 0.03 0.07 0.10 -1 -1 0.03 0.0264884 0.0241963 237 224 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_118.v common 3.07 vpr 64.34 MiB -1 -1 0.14 17596 12 0.16 -1 -1 32212 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 31 32 222 254 1 168 102 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2680 1201 9146 2230 5919 997 64.3 MiB 0.07 0.00 9.64207 6.86528 -149.041 -6.86528 6.86528 0.27 0.000812538 0.000756576 0.0281269 0.0260777 -1 -1 -1 -1 28 2882 21 6.55708e+06 470145 500653. 1732.36 1.53 0.151684 0.134655 21310 115450 -1 2472 16 858 2767 136347 34084 6.01898 6.01898 -141.29 -6.01898 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0163473 0.014792 148 131 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_119.v common 3.95 vpr 64.73 MiB -1 -1 0.18 18748 13 0.38 -1 -1 33024 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 282 314 1 207 106 17 17 289 -1 unnamed_device 24.8 MiB 0.11 3147 1501 6856 1348 5065 443 64.7 MiB 0.04 0.00 11.0904 8.08861 -162.494 -8.08861 8.08861 0.24 0.000487836 0.00044248 0.0151914 0.0139396 -1 -1 -1 -1 30 3270 24 6.55708e+06 506310 526063. 1820.29 1.81 0.202497 0.178708 21886 126133 -1 2801 17 1152 3849 170213 42169 6.9959 6.9959 -151.51 -6.9959 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0214516 0.0195268 197 188 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_120.v common 2.26 vpr 64.41 MiB -1 -1 0.16 18356 13 0.16 -1 -1 31960 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 32 32 238 270 1 177 100 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2839 1155 9612 2317 6234 1061 64.4 MiB 0.06 0.00 10.0742 7.73627 -166.258 -7.73627 7.73627 0.26 0.000577123 0.000544952 0.0229617 0.0211759 -1 -1 -1 -1 26 3028 23 6.55708e+06 433980 477104. 1650.88 0.64 0.0971387 0.0867266 21022 109990 -1 2456 17 990 2796 128129 34060 6.7183 6.7183 -154.301 -6.7183 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0259404 0.0234647 163 144 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_121.v common 2.36 vpr 64.06 MiB -1 -1 0.19 18364 12 0.19 -1 -1 32400 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65600 32 32 269 301 1 185 98 17 17 289 -1 unnamed_device 24.0 MiB 0.07 2537 1263 4823 745 3784 294 64.1 MiB 0.04 0.00 8.39043 7.2824 -152.393 -7.2824 7.2824 0.28 0.000905441 0.000848363 0.0153777 0.0142054 -1 -1 -1 -1 26 3179 19 6.55708e+06 409870 477104. 1650.88 0.52 0.0875654 0.0779802 21022 109990 -1 2833 16 1121 3843 195292 47160 6.33578 6.33578 -144.328 -6.33578 0 0 585099. 2024.56 0.04 0.12 0.08 -1 -1 0.04 0.0502091 0.0457004 181 175 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_122.v common 4.30 vpr 64.66 MiB -1 -1 0.21 19136 15 0.52 -1 -1 32728 -1 -1 53 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 350 382 1 251 117 17 17 289 -1 unnamed_device 25.5 MiB 0.10 4081 1828 11271 2288 8079 904 64.7 MiB 0.08 0.00 12.2654 9.04209 -187.694 -9.04209 9.04209 0.24 0.000564516 0.000516461 0.0316535 0.0292536 -1 -1 -1 -1 34 4381 20 6.55708e+06 638915 585099. 2024.56 1.93 0.266028 0.237356 22462 138074 -1 3819 17 1628 5914 283565 69847 7.93821 7.93821 -172.8 -7.93821 0 0 742403. 2568.87 0.04 0.11 0.13 -1 -1 0.04 0.0448869 0.0406004 267 256 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_123.v common 2.15 vpr 63.67 MiB -1 -1 0.17 17984 10 0.08 -1 -1 31896 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65200 30 32 174 206 1 130 87 17 17 289 -1 unnamed_device 24.1 MiB 0.06 1854 885 5271 1136 3651 484 63.7 MiB 0.03 0.00 6.3165 5.04697 -113.367 -5.04697 5.04697 0.27 0.000281181 0.000256712 0.0096779 0.00890741 -1 -1 -1 -1 22 2009 18 6.55708e+06 301375 420624. 1455.45 0.72 0.0769089 0.067373 20158 92377 -1 1822 15 647 1672 87673 22492 4.69874 4.69874 -113.69 -4.69874 0 0 500653. 1732.36 0.02 0.03 0.05 -1 -1 0.02 0.0113927 0.0102766 101 86 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_124.v common 2.17 vpr 64.31 MiB -1 -1 0.16 17984 13 0.16 -1 -1 32224 -1 -1 35 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65856 30 32 228 260 1 166 97 17 17 289 -1 unnamed_device 24.7 MiB 0.04 2503 1064 8533 2145 5652 736 64.3 MiB 0.05 0.00 9.22658 7.43294 -146.134 -7.43294 7.43294 0.25 0.000684186 0.00061813 0.0193226 0.0176829 -1 -1 -1 -1 26 2779 19 6.55708e+06 421925 477104. 1650.88 0.59 0.0941429 0.083978 21022 109990 -1 2338 20 900 2793 146444 39162 6.62764 6.62764 -141.958 -6.62764 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0212905 0.0192897 158 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_125.v common 2.93 vpr 64.61 MiB -1 -1 0.16 17984 12 0.22 -1 -1 32456 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66164 32 32 264 296 1 190 103 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2629 1279 6851 1204 5209 438 64.6 MiB 0.06 0.00 9.58679 7.67078 -160.044 -7.67078 7.67078 0.26 0.00074458 0.000678895 0.0262383 0.0240079 -1 -1 -1 -1 26 3107 22 6.55708e+06 470145 477104. 1650.88 1.18 0.160881 0.142423 21022 109990 -1 2653 17 1110 3493 165297 42443 6.9215 6.9215 -157.739 -6.9215 0 0 585099. 2024.56 0.02 0.05 0.07 -1 -1 0.02 0.0191677 0.017369 182 170 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_126.v common 1.94 vpr 63.14 MiB -1 -1 0.16 17984 9 0.14 -1 -1 32072 -1 -1 32 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64652 25 32 183 215 1 133 89 17 17 289 -1 unnamed_device 23.7 MiB 0.04 1645 871 9395 2229 5617 1549 63.1 MiB 0.04 0.00 7.61712 5.81412 -100.01 -5.81412 5.81412 0.24 0.000292282 0.000267119 0.0173114 0.0159233 -1 -1 -1 -1 20 2082 17 6.55708e+06 385760 394039. 1363.46 0.46 0.0530832 0.0471797 19870 87366 -1 1921 20 716 2165 117867 32355 5.29412 5.29412 -99.9076 -5.29412 0 0 477104. 1650.88 0.02 0.04 0.05 -1 -1 0.02 0.0149858 0.0134956 117 110 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_127.v common 2.38 vpr 64.78 MiB -1 -1 0.19 18368 12 0.24 -1 -1 32288 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66336 32 32 300 332 1 216 107 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3565 1492 7444 1324 5746 374 64.8 MiB 0.05 0.00 10.0075 7.59118 -168.041 -7.59118 7.59118 0.24 0.000891795 0.000812487 0.0203308 0.0187674 -1 -1 -1 -1 26 3908 24 6.55708e+06 518365 477104. 1650.88 0.63 0.101343 0.0903997 21022 109990 -1 3205 18 1335 4400 213388 52780 6.7621 6.7621 -161.57 -6.7621 0 0 585099. 2024.56 0.03 0.09 0.07 -1 -1 0.03 0.038608 0.0346733 214 206 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_128.v common 3.03 vpr 64.82 MiB -1 -1 0.34 18748 13 0.34 -1 -1 32352 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 31 32 290 322 1 209 103 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3076 1400 9020 1816 6496 708 64.8 MiB 0.06 0.00 10.9492 8.22447 -168.698 -8.22447 8.22447 0.24 0.000468237 0.000425889 0.0269885 0.0247947 -1 -1 -1 -1 26 4161 44 6.55708e+06 482200 477104. 1650.88 0.88 0.150718 0.134439 21022 109990 -1 3404 19 1491 5035 261566 64544 7.49096 7.49096 -169.674 -7.49096 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0380429 0.0345811 210 199 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 2.05 vpr 64.81 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30188 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 32 32 354 285 1 202 100 17 17 289 -1 unnamed_device 24.9 MiB 0.17 2678 1168 17500 5183 9317 3000 64.8 MiB 0.09 0.00 6.89032 5.76129 -168.782 -5.76129 5.76129 0.25 0.000333333 0.000305308 0.0299479 0.0274962 -1 -1 -1 -1 32 2438 20 6.64007e+06 452088 554710. 1919.41 0.45 0.0846256 0.0753861 22834 132086 -1 2056 19 1088 1723 102004 24911 4.49028 4.49028 -149.555 -4.49028 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0160781 0.0144875 152 50 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.00 vpr 64.81 MiB -1 -1 0.12 18436 1 0.03 -1 -1 29772 -1 -1 30 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2387 1153 13961 4091 8036 1834 64.8 MiB 0.11 0.00 6.11521 5.05541 -146.114 -5.05541 5.05541 0.25 0.000500957 0.000466786 0.0364324 0.0336624 -1 -1 -1 -1 32 2330 19 6.64007e+06 376740 554710. 1919.41 0.43 0.0998543 0.0896451 22834 132086 -1 2183 20 1448 2220 169416 37520 3.76628 3.76628 -132.238 -3.76628 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0177524 0.0158766 147 63 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.62 vpr 64.13 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29804 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 32 32 299 247 1 188 94 17 17 289 -1 unnamed_device 24.5 MiB 0.16 2525 988 13087 3736 7613 1738 64.1 MiB 0.07 0.00 5.74935 4.679 -119.362 -4.679 4.679 0.23 0.000294184 0.000268866 0.0198637 0.018188 -1 -1 -1 -1 28 2482 34 6.64007e+06 376740 500653. 1732.36 1.10 0.1219 0.106318 21970 115934 -1 1920 19 1114 1579 102339 24279 3.91102 3.91102 -116.938 -3.91102 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0155755 0.0139714 129 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.18 vpr 64.59 MiB -1 -1 0.19 17668 1 0.03 -1 -1 29756 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2219 999 11684 2867 7870 947 64.6 MiB 0.06 0.00 5.50467 4.50524 -120.656 -4.50524 4.50524 0.23 0.000301757 0.000276843 0.0194556 0.0177984 -1 -1 -1 -1 26 2353 21 6.64007e+06 389298 477104. 1650.88 0.78 0.102845 0.0897238 21682 110474 -1 1996 22 1376 2539 149716 35231 3.78483 3.78483 -117.773 -3.78483 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0206924 0.0183868 132 31 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 1.93 vpr 64.67 MiB -1 -1 0.11 18052 1 0.03 -1 -1 30212 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66224 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 25.2 MiB 0.05 2401 1044 13340 3641 8511 1188 64.7 MiB 0.10 0.00 5.52176 4.47681 -129.939 -4.47681 4.47681 0.27 0.000326175 0.000298389 0.0335294 0.031105 -1 -1 -1 -1 26 2714 23 6.64007e+06 351624 477104. 1650.88 0.52 0.0841857 0.0755446 21682 110474 -1 2319 20 1464 2737 194545 44782 3.91083 3.91083 -130.973 -3.91083 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0173489 0.015589 134 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.19 vpr 64.17 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29756 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 24.6 MiB 0.07 2589 1146 13840 3734 8768 1338 64.2 MiB 0.07 0.00 4.20679 3.37156 -118.042 -3.37156 3.37156 0.24 0.000343562 0.000314786 0.0216965 0.0198462 -1 -1 -1 -1 28 2430 24 6.64007e+06 489762 500653. 1732.36 0.79 0.125458 0.109537 21970 115934 -1 2113 20 1219 1980 106732 27236 3.00917 3.00917 -117.621 -3.00917 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0217329 0.0195006 145 58 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.30 vpr 63.78 MiB -1 -1 0.20 17288 1 0.02 -1 -1 30552 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65312 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1585 646 13324 5650 6908 766 63.8 MiB 0.06 0.00 4.47141 3.76738 -100.249 -3.76738 3.76738 0.24 0.000261076 0.000238807 0.0222262 0.0203919 -1 -1 -1 -1 30 1362 22 6.64007e+06 263718 526063. 1820.29 0.89 0.104457 0.0913085 22546 126617 -1 1268 22 886 1557 92007 22640 2.87397 2.87397 -91.7688 -2.87397 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0171266 0.015248 97 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.27 vpr 64.12 MiB -1 -1 0.11 17912 1 0.03 -1 -1 29800 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65656 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 24.5 MiB 0.03 2037 1027 15848 4746 8906 2196 64.1 MiB 0.08 0.00 4.0843 3.4441 -101.869 -3.4441 3.4441 0.23 0.000279498 0.000255601 0.0233277 0.0213053 -1 -1 -1 -1 26 2300 22 6.64007e+06 439530 477104. 1650.88 0.94 0.108532 0.0952919 21682 110474 -1 2007 20 1077 1995 121729 28059 2.93817 2.93817 -99.1235 -2.93817 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0142379 0.0126856 123 4 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.53 vpr 64.61 MiB -1 -1 0.13 17908 1 0.03 -1 -1 30172 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 31 32 317 271 1 168 88 17 17 289 -1 unnamed_device 24.9 MiB 0.11 2086 995 13543 3931 7670 1942 64.6 MiB 0.06 0.00 3.99239 3.60222 -119.143 -3.60222 3.60222 0.23 0.000300054 0.000274015 0.0225345 0.0206345 -1 -1 -1 -1 32 1822 20 6.64007e+06 313950 554710. 1919.41 0.92 0.11928 0.104086 22834 132086 -1 1636 20 877 1310 79180 19116 2.89043 2.89043 -109.637 -2.89043 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0150146 0.013392 117 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.63 vpr 64.51 MiB -1 -1 0.13 17664 1 0.03 -1 -1 30140 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 24.9 MiB 0.12 1795 817 8003 1790 5827 386 64.5 MiB 0.05 0.00 4.55761 3.87558 -124.983 -3.87558 3.87558 0.24 0.000293751 0.000267622 0.014943 0.0137302 -1 -1 -1 -1 28 1916 23 6.64007e+06 238602 500653. 1732.36 0.99 0.107138 0.0936028 21970 115934 -1 1743 21 1210 1968 117336 30369 2.80477 2.80477 -113.751 -2.80477 0 0 612192. 2118.31 0.02 0.04 0.08 -1 -1 0.02 0.0158551 0.0140681 115 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.40 vpr 64.53 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29796 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 24.5 MiB 0.07 1688 651 12156 4701 5752 1703 64.5 MiB 0.06 0.00 4.55761 3.85358 -107.527 -3.85358 3.85358 0.25 0.000290653 0.000265701 0.0218367 0.0200019 -1 -1 -1 -1 30 1469 20 6.64007e+06 238602 526063. 1820.29 0.83 0.0990725 0.0867591 22546 126617 -1 1254 17 604 926 54157 13941 2.77497 2.77497 -95.1733 -2.77497 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0130171 0.0117058 101 63 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.31 vpr 64.49 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29716 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 24.5 MiB 0.13 2346 951 8919 2111 6427 381 64.5 MiB 0.05 0.00 4.97492 3.76035 -118.411 -3.76035 3.76035 0.23 0.000287454 0.000258142 0.0148458 0.0135347 -1 -1 -1 -1 26 2233 26 6.64007e+06 288834 477104. 1650.88 0.90 0.106722 0.0926572 21682 110474 -1 1861 21 1041 1454 89116 22517 3.10837 3.10837 -114.215 -3.10837 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0137714 0.0122685 110 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 1.86 vpr 64.40 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29768 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 24.9 MiB 0.14 2572 1221 14583 4808 7640 2135 64.4 MiB 0.09 0.00 4.99767 4.51687 -145.067 -4.51687 4.51687 0.24 0.000323777 0.000296108 0.0247005 0.0224532 -1 -1 -1 -1 30 2687 23 6.64007e+06 364182 526063. 1820.29 0.39 0.0704651 0.0623808 22546 126617 -1 2135 17 1045 1588 103097 22969 3.25883 3.25883 -126.603 -3.25883 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0154776 0.0138331 148 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.07 vpr 64.78 MiB -1 -1 0.14 17696 1 0.03 -1 -1 29780 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2535 922 19223 5837 10520 2866 64.8 MiB 0.11 0.00 5.92827 4.77444 -136.955 -4.77444 4.77444 0.25 0.000376709 0.000347561 0.0371074 0.034053 -1 -1 -1 -1 28 2714 33 6.64007e+06 426972 500653. 1732.36 0.57 0.0952296 0.0848217 21970 115934 -1 2193 22 1709 2838 188317 48152 4.01303 4.01303 -131.661 -4.01303 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0173466 0.0155029 139 61 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.26 vpr 64.13 MiB -1 -1 0.12 17672 1 0.02 -1 -1 30240 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 24.9 MiB 0.05 1651 648 11064 3436 5196 2432 64.1 MiB 0.06 0.00 3.81299 3.12479 -88.8266 -3.12479 3.12479 0.26 0.00026897 0.00023978 0.0232876 0.0215518 -1 -1 -1 -1 32 1369 19 6.64007e+06 288834 554710. 1919.41 0.89 0.105223 0.0919344 22834 132086 -1 1104 15 627 1014 49151 13344 2.77777 2.77777 -84.3561 -2.77777 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.0103697 0.00930164 103 27 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 1.84 vpr 64.30 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29768 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2380 942 16819 5830 8106 2883 64.3 MiB 0.09 0.00 4.6791 4.09527 -122.173 -4.09527 4.09527 0.23 0.000346698 0.000316608 0.0307314 0.0280788 -1 -1 -1 -1 32 2367 28 6.64007e+06 339066 554710. 1919.41 0.39 0.0804661 0.0715237 22834 132086 -1 1983 22 1455 2736 169045 42069 3.21356 3.21356 -117.004 -3.21356 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0201019 0.0179187 138 58 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 1.78 vpr 64.36 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29828 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2606 1192 12305 3184 7882 1239 64.4 MiB 0.07 0.00 5.47847 4.60407 -146.257 -4.60407 4.60407 0.23 0.000330363 0.000302451 0.0218624 0.0200378 -1 -1 -1 -1 32 2209 18 6.64007e+06 351624 554710. 1919.41 0.34 0.0628724 0.0559061 22834 132086 -1 2050 16 1144 1644 92509 23959 3.27883 3.27883 -126.125 -3.27883 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0139599 0.012587 144 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.37 vpr 64.11 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29644 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65648 32 32 323 276 1 153 98 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2093 899 12248 2945 8519 784 64.1 MiB 0.06 0.00 3.59784 2.85064 -103.682 -2.85064 2.85064 0.23 0.00031002 0.000284204 0.0183735 0.0167743 -1 -1 -1 -1 26 2006 25 6.64007e+06 426972 477104. 1650.88 0.82 0.101691 0.0889344 21682 110474 -1 1742 21 1124 1885 120447 29317 2.14431 2.14431 -98.4532 -2.14431 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0152302 0.0135505 115 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 2.13 vpr 64.00 MiB -1 -1 0.11 17528 1 0.02 -1 -1 29752 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65532 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1535 603 7853 2116 5212 525 64.0 MiB 0.04 0.00 2.99233 2.39133 -77.851 -2.39133 2.39133 0.24 0.000231626 0.000212413 0.0147234 0.0135737 -1 -1 -1 -1 32 1129 17 6.64007e+06 213486 554710. 1919.41 0.86 0.0935232 0.0812611 22834 132086 -1 990 20 553 827 48112 12467 1.79471 1.79471 -72.575 -1.79471 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.0110231 0.00979166 85 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 1.76 vpr 64.60 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29800 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 31 32 291 243 1 171 87 17 17 289 -1 unnamed_device 24.5 MiB 0.15 2125 1026 10455 2663 6617 1175 64.6 MiB 0.06 0.00 6.02746 5.0168 -149.308 -5.0168 5.0168 0.23 0.000293444 0.000269173 0.0187775 0.0172066 -1 -1 -1 -1 30 2023 21 6.64007e+06 301392 526063. 1820.29 0.32 0.0582338 0.0515822 22546 126617 -1 1733 20 829 1237 65753 16555 3.62043 3.62043 -133.716 -3.62043 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0181583 0.0162736 127 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 2.76 vpr 64.73 MiB -1 -1 0.16 18436 1 0.03 -1 -1 29980 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 25.2 MiB 0.04 2331 1141 17961 5691 10386 1884 64.7 MiB 0.11 0.00 5.44296 4.13552 -132.934 -4.13552 4.13552 0.24 0.000351539 0.00032317 0.0368032 0.0340409 -1 -1 -1 -1 26 2527 22 6.64007e+06 464646 477104. 1650.88 1.27 0.152604 0.135082 21682 110474 -1 2212 22 1474 2442 179110 40191 3.73683 3.73683 -133.451 -3.73683 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0173672 0.0155182 140 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 2.89 vpr 64.85 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29712 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66404 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 24.9 MiB 0.25 2693 1197 9383 1945 6894 544 64.8 MiB 0.06 0.00 5.6841 4.62416 -139.043 -4.62416 4.62416 0.24 0.000343386 0.000314627 0.0172008 0.0157806 -1 -1 -1 -1 30 2804 24 6.64007e+06 389298 526063. 1820.29 1.14 0.12124 0.106579 22546 126617 -1 2221 19 1154 1858 115618 26985 3.82228 3.82228 -129.932 -3.82228 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0172664 0.0155995 151 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 1.96 vpr 63.86 MiB -1 -1 0.12 18056 1 0.02 -1 -1 30160 -1 -1 20 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65396 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1349 633 10868 3050 6437 1381 63.9 MiB 0.04 0.00 2.81093 2.39133 -70.7944 -2.39133 2.39133 0.23 0.000198641 0.000181079 0.0142663 0.0130218 -1 -1 -1 -1 26 1233 20 6.64007e+06 251160 477104. 1650.88 0.68 0.070323 0.0614049 21682 110474 -1 1121 19 523 781 49077 12394 1.95411 1.95411 -71.0211 -1.95411 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.0107949 0.00959479 81 30 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 1.78 vpr 64.57 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29764 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2052 991 13751 4633 6453 2665 64.6 MiB 0.07 0.00 4.97861 4.55404 -124.907 -4.55404 4.55404 0.25 0.000298608 0.000273835 0.0228545 0.0209681 -1 -1 -1 -1 32 2035 19 6.64007e+06 313950 554710. 1919.41 0.36 0.0657503 0.0584607 22834 132086 -1 1878 20 1138 2086 138403 31685 3.44803 3.44803 -114.756 -3.44803 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0144217 0.0128571 125 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.04 vpr 63.86 MiB -1 -1 0.11 17664 1 0.02 -1 -1 30076 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65388 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 24.7 MiB 0.03 1447 554 12331 4885 6406 1040 63.9 MiB 0.05 0.00 2.77793 2.35833 -70.3669 -2.35833 2.35833 0.24 0.000401366 0.000368701 0.0176975 0.0162144 -1 -1 -1 -1 28 1254 19 6.64007e+06 213486 500653. 1732.36 0.82 0.074078 0.0649612 21970 115934 -1 991 16 450 533 42691 11758 1.86191 1.86191 -70.1632 -1.86191 0 0 612192. 2118.31 0.02 0.02 0.06 -1 -1 0.02 0.00837099 0.00747193 82 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.55 vpr 64.57 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29764 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2081 918 9383 2172 5914 1297 64.6 MiB 0.05 0.00 5.31627 4.63183 -123.978 -4.63183 4.63183 0.24 0.000306745 0.000280355 0.0150318 0.0138059 -1 -1 -1 -1 30 2001 23 6.64007e+06 389298 526063. 1820.29 1.00 0.115117 0.10028 22546 126617 -1 1617 20 798 1425 79320 19609 3.37283 3.37283 -108.474 -3.37283 0 0 666494. 2306.21 0.04 0.05 0.12 -1 -1 0.04 0.0244901 0.0219357 126 24 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.28 vpr 64.39 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29948 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 24.6 MiB 0.03 2388 1070 19624 5823 11095 2706 64.4 MiB 0.10 0.00 4.70631 3.69341 -108.189 -3.69341 3.69341 0.23 0.000320509 0.00029285 0.0301434 0.0276299 -1 -1 -1 -1 28 2304 20 6.64007e+06 489762 500653. 1732.36 0.89 0.12607 0.111455 21970 115934 -1 2043 19 1110 2038 137544 38662 3.00917 3.00917 -107.4 -3.00917 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0143121 0.0128153 136 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.84 vpr 64.70 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30168 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 338 277 1 179 98 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2303 1088 17423 5246 9519 2658 64.7 MiB 0.09 0.00 5.78707 4.89043 -136.673 -4.89043 4.89043 0.24 0.000327236 0.000299569 0.0274047 0.0250913 -1 -1 -1 -1 26 2626 24 6.64007e+06 426972 477104. 1650.88 1.39 0.158323 0.139377 21682 110474 -1 2086 20 1058 1856 117209 27300 3.85983 3.85983 -129.261 -3.85983 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0157392 0.0140998 132 50 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.00 vpr 64.45 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29628 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 24.9 MiB 0.05 1848 932 9571 2445 6468 658 64.4 MiB 0.05 0.00 3.79099 3.02179 -103.859 -3.02179 3.02179 0.23 0.000290894 0.000267194 0.0165695 0.0152169 -1 -1 -1 -1 30 1784 18 6.64007e+06 263718 526063. 1820.29 0.65 0.0906451 0.0790376 22546 126617 -1 1601 19 736 1233 74070 17622 2.70797 2.70797 -101.892 -2.70797 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0137793 0.0123494 107 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.26 vpr 64.42 MiB -1 -1 0.12 17668 1 0.02 -1 -1 29852 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65964 30 32 262 227 1 135 86 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1630 675 10103 2270 6949 884 64.4 MiB 0.05 0.00 3.60179 3.24119 -95.5452 -3.24119 3.24119 0.23 0.00034986 0.000321242 0.0196118 0.0180662 -1 -1 -1 -1 30 1518 17 6.64007e+06 301392 526063. 1820.29 0.88 0.10414 0.0913886 22546 126617 -1 1212 20 661 1089 52330 13795 2.56257 2.56257 -89.8228 -2.56257 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0132004 0.0116361 100 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 1.76 vpr 64.43 MiB -1 -1 0.15 17668 1 0.03 -1 -1 29816 -1 -1 24 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 24.3 MiB 0.04 1853 868 11247 3492 5966 1789 64.4 MiB 0.07 0.00 4.1543 3.41886 -98.6687 -3.41886 3.41886 0.25 0.000328088 0.000304966 0.0270155 0.0250108 -1 -1 -1 -1 32 1674 22 6.64007e+06 301392 554710. 1919.41 0.34 0.0669298 0.0597058 22834 132086 -1 1544 22 868 1612 92339 21804 2.72157 2.72157 -97.0146 -2.72157 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0150226 0.0132339 104 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 2.35 vpr 64.43 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29816 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2077 943 13663 4291 7577 1795 64.4 MiB 0.06 0.00 4.55061 3.72021 -112.43 -3.72021 3.72021 0.24 0.00027512 0.000252672 0.0213097 0.0195023 -1 -1 -1 -1 26 2096 19 6.64007e+06 263718 477104. 1650.88 0.79 0.0898311 0.0787572 21682 110474 -1 1871 22 1227 1984 139135 31601 2.85597 2.85597 -110.575 -2.85597 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0139917 0.0124162 116 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.20 vpr 64.48 MiB -1 -1 0.13 17544 1 0.02 -1 -1 30152 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1915 918 11703 2893 8058 752 64.5 MiB 0.06 0.00 3.9659 3.50227 -105.619 -3.50227 3.50227 0.24 0.000276998 0.000253415 0.0163437 0.014946 -1 -1 -1 -1 32 1765 22 6.64007e+06 414414 554710. 1919.41 0.90 0.108379 0.0945088 22834 132086 -1 1550 19 732 1226 65350 16682 2.72157 2.72157 -100.584 -2.72157 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0126351 0.0112682 111 30 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.30 vpr 64.14 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29800 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65676 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2169 773 17273 5937 9206 2130 64.1 MiB 0.18 0.00 3.9379 3.3369 -101.534 -3.3369 3.3369 0.24 0.000761204 0.000704797 0.0671225 0.0623348 -1 -1 -1 -1 26 1968 20 6.64007e+06 389298 477104. 1650.88 0.86 0.144333 0.129123 21682 110474 -1 1572 20 922 1465 89723 22843 2.34097 2.34097 -89.7372 -2.34097 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0136178 0.012134 112 54 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 3.16 vpr 64.87 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29616 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66428 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2308 1232 18356 5288 9596 3472 64.9 MiB 0.09 0.00 4.83776 4.37413 -122.59 -4.37413 4.37413 0.25 0.000352344 0.000322425 0.0280539 0.025636 -1 -1 -1 -1 28 2975 26 6.64007e+06 527436 500653. 1732.36 1.76 0.14119 0.125231 21970 115934 -1 2412 18 1248 2439 162377 37472 3.48123 3.48123 -118.393 -3.48123 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.016007 0.0144134 158 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.55 vpr 64.89 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29744 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66448 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 25.5 MiB 0.07 2421 1023 18877 5825 10430 2622 64.9 MiB 0.11 0.00 4.51361 3.87558 -128.529 -3.87558 3.87558 0.23 0.000369261 0.000339114 0.0340034 0.0311586 -1 -1 -1 -1 32 2017 21 6.64007e+06 514878 554710. 1919.41 1.15 0.184919 0.162569 22834 132086 -1 1849 21 1444 2355 125874 31664 2.77177 2.77177 -110.96 -2.77177 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0176566 0.0158237 150 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.42 vpr 64.50 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29780 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 24.5 MiB 0.14 2417 918 9536 2320 6465 751 64.5 MiB 0.06 0.00 5.18307 4.35884 -128.706 -4.35884 4.35884 0.24 0.000284721 0.000261675 0.0198292 0.0182771 -1 -1 -1 -1 32 1849 20 6.64007e+06 288834 554710. 1919.41 0.90 0.111762 0.0974411 22834 132086 -1 1689 20 806 1172 74453 17829 3.22283 3.22283 -115.365 -3.22283 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0134962 0.0120415 114 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 1.89 vpr 64.34 MiB -1 -1 0.13 18052 1 0.04 -1 -1 29788 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65884 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2217 1122 16238 4882 9322 2034 64.3 MiB 0.09 0.00 4.8385 3.9971 -121.388 -3.9971 3.9971 0.23 0.000336917 0.000307579 0.0286334 0.0261744 -1 -1 -1 -1 32 2344 20 6.64007e+06 364182 554710. 1919.41 0.36 0.0728185 0.0646739 22834 132086 -1 2088 23 1449 2642 147498 35841 3.12137 3.12137 -116.821 -3.12137 0 0 701300. 2426.64 0.03 0.05 0.10 -1 -1 0.03 0.0194932 0.0173853 145 61 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.22 vpr 64.95 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29756 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66504 31 32 377 302 1 233 99 17 17 289 -1 unnamed_device 25.2 MiB 0.24 2995 1421 19707 5440 12139 2128 64.9 MiB 0.11 0.00 7.81519 5.67793 -171.305 -5.67793 5.67793 0.23 0.000346066 0.000316676 0.0325169 0.0297691 -1 -1 -1 -1 28 3277 23 6.64007e+06 452088 500653. 1732.36 0.61 0.104355 0.0932129 21970 115934 -1 2581 21 1555 2326 136329 33259 4.52274 4.52274 -159.537 -4.52274 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.018193 0.0163931 178 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.73 vpr 64.90 MiB -1 -1 0.24 18056 1 0.03 -1 -1 29784 -1 -1 32 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66456 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 25.2 MiB 0.20 2681 1319 14999 4569 8381 2049 64.9 MiB 0.09 0.00 6.40882 5.22399 -160.729 -5.22399 5.22399 0.25 0.000373524 0.000343579 0.0331096 0.0307403 -1 -1 -1 -1 32 2679 17 6.64007e+06 401856 554710. 1919.41 0.96 0.122984 0.109251 22834 132086 -1 2354 19 1056 1619 130226 28911 4.31108 4.31108 -149.075 -4.31108 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0237688 0.0214486 167 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.39 vpr 64.77 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30124 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2150 1128 15412 3921 9377 2114 64.8 MiB 0.08 0.00 5.33427 4.63507 -135.372 -4.63507 4.63507 0.23 0.000329383 0.000301672 0.0241206 0.0220879 -1 -1 -1 -1 30 2296 22 6.64007e+06 464646 526063. 1820.29 0.94 0.132554 0.115834 22546 126617 -1 2016 22 1100 1926 104277 24750 3.19762 3.19762 -115.815 -3.19762 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0177833 0.0158452 140 55 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.60 vpr 64.61 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30148 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 32 32 291 242 1 179 91 17 17 289 -1 unnamed_device 24.5 MiB 0.19 2447 1083 8863 2197 6096 570 64.6 MiB 0.05 0.00 5.56996 4.45012 -118.426 -4.45012 4.45012 0.25 0.000299359 0.000274949 0.0144886 0.0132926 -1 -1 -1 -1 32 2169 21 6.64007e+06 339066 554710. 1919.41 0.92 0.11342 0.0992661 22834 132086 -1 1944 22 951 1417 84928 20855 3.51243 3.51243 -111.872 -3.51243 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0149971 0.0133682 124 27 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 2.52 vpr 65.09 MiB -1 -1 0.13 17668 1 0.03 -1 -1 29868 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 25.2 MiB 0.10 3200 1325 22371 6342 13589 2440 65.1 MiB 0.14 0.00 6.26139 5.1195 -164.675 -5.1195 5.1195 0.23 0.0004489 0.000412219 0.0433974 0.0398984 -1 -1 -1 -1 28 3170 21 6.64007e+06 539994 500653. 1732.36 1.01 0.166744 0.147094 21970 115934 -1 2626 19 1703 2722 167391 39031 4.00549 4.00549 -146.496 -4.00549 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0228447 0.0204446 176 87 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 1.70 vpr 64.06 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29676 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65596 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2009 855 10481 2942 6568 971 64.1 MiB 0.06 0.00 4.5869 3.77367 -103.344 -3.77367 3.77367 0.24 0.000271845 0.000248737 0.0209896 0.0193119 -1 -1 -1 -1 32 1689 18 6.64007e+06 288834 554710. 1919.41 0.32 0.0563517 0.0499083 22834 132086 -1 1523 18 785 1365 80306 19202 2.76057 2.76057 -98.8257 -2.76057 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0123234 0.0110592 104 28 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 1.88 vpr 64.25 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30236 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 24.7 MiB 0.15 2890 1252 16081 4637 9397 2047 64.2 MiB 0.10 0.00 6.34307 5.14733 -154.615 -5.14733 5.14733 0.24 0.000368948 0.00034104 0.0275732 0.0253414 -1 -1 -1 -1 30 2475 23 6.64007e+06 426972 526063. 1820.29 0.39 0.0714749 0.0637398 22546 126617 -1 2096 16 1084 1657 88851 21305 3.68189 3.68189 -130.335 -3.68189 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0145065 0.0130876 149 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.98 vpr 64.76 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29612 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 349 284 1 182 102 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2675 1103 12240 2946 8556 738 64.8 MiB 0.07 0.00 4.99666 3.95307 -115.476 -3.95307 3.95307 0.24 0.000333577 0.000303121 0.0217054 0.0198476 -1 -1 -1 -1 26 2701 22 6.64007e+06 477204 477104. 1650.88 1.63 0.165153 0.14533 21682 110474 -1 2200 19 1260 2288 139167 34153 3.10737 3.10737 -113.433 -3.10737 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0155087 0.0138955 136 53 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 1.77 vpr 64.59 MiB -1 -1 0.12 17672 1 0.03 -1 -1 29776 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1813 1148 12127 3848 6621 1658 64.6 MiB 0.07 0.00 4.79356 4.19256 -126.138 -4.19256 4.19256 0.24 0.000295337 0.000269636 0.0215588 0.0198294 -1 -1 -1 -1 32 2151 21 6.64007e+06 339066 554710. 1919.41 0.43 0.0824346 0.0732441 22834 132086 -1 1914 22 904 1746 107845 24237 3.45223 3.45223 -118.392 -3.45223 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.015861 0.0141677 127 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.07 vpr 64.82 MiB -1 -1 0.14 18052 1 0.03 -1 -1 30168 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 32 32 353 287 1 198 95 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2414 1205 15647 4038 9814 1795 64.8 MiB 0.11 0.00 5.52647 4.90352 -143.647 -4.90352 4.90352 0.25 0.0008019 0.000745825 0.0364362 0.033814 -1 -1 -1 -1 28 2686 18 6.64007e+06 389298 500653. 1732.36 0.39 0.0847936 0.0764764 21970 115934 -1 2410 18 1295 1758 111267 27132 3.30283 3.30283 -125.331 -3.30283 0 0 612192. 2118.31 0.02 0.07 0.10 -1 -1 0.02 0.02999 0.026759 142 55 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 2.65 vpr 64.80 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29828 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2461 1024 18178 5514 9376 3288 64.8 MiB 0.09 0.00 4.3595 3.73184 -117.882 -3.73184 3.73184 0.23 0.000342503 0.000313459 0.0274297 0.0250706 -1 -1 -1 -1 28 2934 24 6.64007e+06 489762 500653. 1732.36 1.24 0.134412 0.118217 21970 115934 -1 2157 20 1301 2160 149192 38424 3.16237 3.16237 -119.152 -3.16237 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0170942 0.0152499 139 55 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.02 vpr 64.38 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30240 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 24.9 MiB 0.10 2721 1115 21088 6199 11891 2998 64.4 MiB 0.14 0.00 5.01327 4.29207 -130.428 -4.29207 4.29207 0.25 0.000354017 0.000323912 0.0461859 0.0427932 -1 -1 -1 -1 28 2739 18 6.64007e+06 502320 500653. 1732.36 0.52 0.101778 0.0916839 21970 115934 -1 2203 21 1389 2324 157732 36229 3.12137 3.12137 -119.153 -3.12137 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0176308 0.0157409 149 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 3.47 vpr 64.60 MiB -1 -1 0.18 17672 1 0.03 -1 -1 30132 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 25.2 MiB 0.06 1947 873 16108 4476 7806 3826 64.6 MiB 0.07 0.00 4.78256 4.34576 -121.313 -4.34576 4.34576 0.23 0.000306518 0.000280534 0.0227357 0.0207675 -1 -1 -1 -1 30 2090 25 6.64007e+06 452088 526063. 1820.29 1.86 0.113549 0.0993707 22546 126617 -1 1553 21 1051 1873 98927 27703 4.05503 4.05503 -119.589 -4.05503 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0151484 0.0135515 127 24 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 1.86 vpr 64.32 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29572 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 32 32 319 257 1 198 92 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2350 1149 11684 3237 7258 1189 64.3 MiB 0.07 0.00 6.11266 5.05904 -138.884 -5.05904 5.05904 0.23 0.000310168 0.000284344 0.0194827 0.0178456 -1 -1 -1 -1 32 2297 18 6.64007e+06 351624 554710. 1919.41 0.33 0.0597045 0.0529702 22834 132086 -1 2103 18 1068 1607 98345 23408 3.70662 3.70662 -126.282 -3.70662 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0145917 0.0131743 137 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 1.83 vpr 64.86 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30156 -1 -1 30 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66412 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 24.9 MiB 0.14 2921 1233 9543 2186 6591 766 64.9 MiB 0.07 0.00 6.45652 5.2717 -153.789 -5.2717 5.2717 0.23 0.000341115 0.000312552 0.0185871 0.0170812 -1 -1 -1 -1 28 2872 24 6.64007e+06 376740 500653. 1732.36 0.39 0.0660029 0.0583999 21970 115934 -1 2431 24 1612 2594 167132 39590 4.02948 4.02948 -138.297 -4.02948 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0191265 0.0170798 151 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.47 vpr 64.84 MiB -1 -1 0.13 18048 1 0.03 -1 -1 30132 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66396 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2687 1076 16523 6080 8261 2182 64.8 MiB 0.10 0.00 5.30485 4.45447 -137.456 -4.45447 4.45447 0.23 0.000353272 0.000322898 0.0342221 0.0314022 -1 -1 -1 -1 32 2442 17 6.64007e+06 313950 554710. 1919.41 0.97 0.128817 0.11348 22834 132086 -1 2010 18 1272 2259 134813 32070 3.47843 3.47843 -125.006 -3.47843 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0187106 0.0168733 141 77 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 1.60 vpr 64.16 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29792 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65696 32 32 251 219 1 140 91 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1818 889 8659 1974 6034 651 64.2 MiB 0.05 0.00 3.7947 3.57147 -104.095 -3.57147 3.57147 0.23 0.000261867 0.000239075 0.0134388 0.0123337 -1 -1 -1 -1 28 1905 21 6.64007e+06 339066 500653. 1732.36 0.33 0.0523148 0.0459728 21970 115934 -1 1631 21 853 1375 86391 21527 2.77477 2.77477 -97.2385 -2.77477 0 0 612192. 2118.31 0.02 0.03 0.07 -1 -1 0.02 0.0138134 0.0123514 101 23 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.59 vpr 64.23 MiB -1 -1 0.12 18436 1 0.03 -1 -1 29420 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 24.9 MiB 0.18 2440 999 7231 1434 5468 329 64.2 MiB 0.06 0.00 5.00545 4.0787 -137.534 -4.0787 4.0787 0.25 0.000462463 0.000411606 0.0167471 0.0154013 -1 -1 -1 -1 26 2717 42 6.64007e+06 339066 477104. 1650.88 1.09 0.111643 0.0977058 21682 110474 -1 2232 21 1443 2087 144175 36536 3.38903 3.38903 -135.561 -3.38903 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0161341 0.0143439 133 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 1.94 vpr 64.99 MiB -1 -1 0.12 18676 1 0.03 -1 -1 30196 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66548 32 32 387 293 1 234 98 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2841 1439 17873 5142 10318 2413 65.0 MiB 0.11 0.00 6.57692 5.56526 -164.086 -5.56526 5.56526 0.24 0.000362134 0.000331955 0.0320601 0.0294007 -1 -1 -1 -1 32 2821 20 6.64007e+06 426972 554710. 1919.41 0.38 0.0829831 0.0739859 22834 132086 -1 2555 20 1454 2329 127947 31765 4.32308 4.32308 -149.736 -4.32308 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0193231 0.0173864 174 31 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 2.28 vpr 64.72 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29928 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66276 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2567 1021 10336 2399 7366 571 64.7 MiB 0.06 0.00 5.11912 4.26806 -134.06 -4.26806 4.26806 0.23 0.000334349 0.000304198 0.0160871 0.0147197 -1 -1 -1 -1 30 2164 19 6.64007e+06 477204 526063. 1820.29 0.92 0.113507 0.0996864 22546 126617 -1 1765 18 985 1626 87746 21380 2.84497 2.84497 -113.29 -2.84497 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0148181 0.0133477 141 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 1.72 vpr 64.52 MiB -1 -1 0.18 17672 1 0.02 -1 -1 30240 -1 -1 33 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 24.5 MiB 0.03 2182 743 10679 2942 6832 905 64.5 MiB 0.05 0.00 4.2965 3.52427 -104.21 -3.52427 3.52427 0.25 0.000284469 0.000260517 0.0152668 0.0139714 -1 -1 -1 -1 32 1599 16 6.64007e+06 414414 554710. 1919.41 0.31 0.0492061 0.0433694 22834 132086 -1 1397 17 644 1197 65700 16378 2.71257 2.71257 -96.443 -2.71257 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0125154 0.0112655 111 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.00 vpr 65.11 MiB -1 -1 0.18 18440 1 0.03 -1 -1 29996 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66676 32 32 431 332 1 235 95 17 17 289 -1 unnamed_device 25.6 MiB 0.20 2995 1451 16943 5312 9314 2317 65.1 MiB 0.14 0.00 7.55549 6.37067 -184.872 -6.37067 6.37067 0.25 0.000439913 0.000406748 0.0454496 0.0419737 -1 -1 -1 -1 32 3012 21 6.64007e+06 389298 554710. 1919.41 1.27 0.189098 0.167098 22834 132086 -1 2523 19 1586 2324 142907 33660 5.14455 5.14455 -172.168 -5.14455 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0191733 0.0172741 177 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.58 vpr 64.71 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30356 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1956 1035 13668 3578 8233 1857 64.7 MiB 0.08 0.00 5.19907 4.58683 -138.182 -4.58683 4.58683 0.24 0.000338718 0.000311084 0.0250615 0.0230519 -1 -1 -1 -1 28 2405 23 6.64007e+06 477204 500653. 1732.36 1.17 0.125233 0.110063 21970 115934 -1 2035 19 1349 2237 141237 33242 3.66243 3.66243 -129.496 -3.66243 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0159444 0.0143778 136 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.01 vpr 64.10 MiB -1 -1 0.10 17672 1 0.02 -1 -1 29932 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65640 32 32 231 199 1 140 91 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1906 764 9067 2085 6178 804 64.1 MiB 0.05 0.00 4.2445 3.5653 -97.5026 -3.5653 3.5653 0.23 0.000250471 0.000229596 0.0128699 0.011824 -1 -1 -1 -1 26 1747 20 6.64007e+06 339066 477104. 1650.88 0.78 0.0916771 0.079558 21682 110474 -1 1553 18 736 1243 69356 18200 3.03517 3.03517 -99.0581 -3.03517 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0114051 0.0102012 103 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.25 vpr 64.42 MiB -1 -1 0.11 17912 1 0.03 -1 -1 29820 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2540 1175 11816 2954 8205 657 64.4 MiB 0.07 0.00 6.69892 5.65147 -139.258 -5.65147 5.65147 0.23 0.000343487 0.000315207 0.018729 0.0171086 -1 -1 -1 -1 28 2581 21 6.64007e+06 502320 500653. 1732.36 0.91 0.119022 0.104048 21970 115934 -1 2231 19 1018 2155 132770 30621 4.27588 4.27588 -130.562 -4.27588 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0157386 0.0141662 147 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.20 vpr 64.39 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29800 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 24.5 MiB 0.03 2164 893 10263 2683 6663 917 64.4 MiB 0.06 0.00 4.3277 3.5273 -108.396 -3.5273 3.5273 0.24 0.000311698 0.000287949 0.0177608 0.0162611 -1 -1 -1 -1 32 1749 18 6.64007e+06 288834 554710. 1919.41 0.91 0.101392 0.0881871 22834 132086 -1 1533 20 784 1238 71387 17120 2.77177 2.77177 -103.397 -2.77177 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0129162 0.0115158 107 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 1.81 vpr 64.39 MiB -1 -1 0.13 17908 1 0.03 -1 -1 29836 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2117 911 17732 5400 9784 2548 64.4 MiB 0.08 0.00 5.13641 4.09995 -112.419 -4.09995 4.09995 0.28 0.000286035 0.000255044 0.0231712 0.0210843 -1 -1 -1 -1 28 1992 21 6.64007e+06 477204 500653. 1732.36 0.38 0.0635272 0.0563098 21970 115934 -1 1710 18 975 1883 102536 25450 2.74837 2.74837 -101.654 -2.74837 0 0 612192. 2118.31 0.02 0.03 0.07 -1 -1 0.02 0.0128309 0.0114514 110 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 2.43 vpr 64.82 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29760 -1 -1 30 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 29 32 355 287 1 198 91 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2698 1076 9679 2548 6094 1037 64.8 MiB 0.06 0.00 5.53367 4.61203 -130.625 -4.61203 4.61203 0.23 0.000338658 0.000311571 0.0192196 0.0176251 -1 -1 -1 -1 32 2459 22 6.64007e+06 376740 554710. 1919.41 0.99 0.129037 0.112919 22834 132086 -1 2073 18 1299 1977 111378 28075 3.37503 3.37503 -116.489 -3.37503 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0154722 0.0139398 146 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 1.96 vpr 64.73 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29784 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1949 947 7639 1677 5525 437 64.7 MiB 0.05 0.00 5.24456 4.53352 -139.004 -4.53352 4.53352 0.25 0.000332698 0.00030496 0.0143265 0.0131711 -1 -1 -1 -1 32 2009 19 6.64007e+06 339066 554710. 1919.41 0.49 0.0942014 0.0834076 22834 132086 -1 1774 21 1241 1905 118138 28466 3.74782 3.74782 -129.815 -3.74782 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0215813 0.0193967 135 54 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 1.84 vpr 64.76 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29752 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 25.2 MiB 0.13 2440 1011 14498 3923 8676 1899 64.8 MiB 0.08 0.00 5.77607 4.82681 -139.307 -4.82681 4.82681 0.23 0.000370343 0.000327299 0.0234924 0.0214514 -1 -1 -1 -1 32 2255 19 6.64007e+06 426972 554710. 1919.41 0.34 0.0668056 0.0594183 22834 132086 -1 1902 18 994 1738 88852 22474 4.06723 4.06723 -132.101 -4.06723 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0149293 0.013428 136 51 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.78 vpr 64.15 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29784 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 24.5 MiB 0.22 1928 770 5189 970 3673 546 64.2 MiB 0.03 0.00 5.21395 4.75032 -127.226 -4.75032 4.75032 0.24 0.000282943 0.000258953 0.0093242 0.0085679 -1 -1 -1 -1 28 2312 21 6.64007e+06 276276 500653. 1732.36 1.22 0.102145 0.0888686 21970 115934 -1 1617 18 803 1095 74187 19482 3.17683 3.17683 -111.986 -3.17683 0 0 612192. 2118.31 0.02 0.03 0.07 -1 -1 0.02 0.0160528 0.0144005 107 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.48 vpr 64.59 MiB -1 -1 0.12 18292 1 0.03 -1 -1 30320 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 31 32 319 272 1 169 86 17 17 289 -1 unnamed_device 25.1 MiB 0.12 2149 981 13694 3750 8080 1864 64.6 MiB 0.07 0.00 4.95096 4.00653 -127.945 -4.00653 4.00653 0.23 0.000296843 0.000271587 0.0257813 0.023674 -1 -1 -1 -1 32 1939 22 6.64007e+06 288834 554710. 1919.41 0.92 0.12807 0.111978 22834 132086 -1 1753 19 1043 1582 90723 22601 3.22583 3.22583 -119.839 -3.22583 0 0 701300. 2426.64 0.03 0.03 0.13 -1 -1 0.03 0.0144012 0.0128713 116 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.22 vpr 64.55 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30116 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2322 929 9548 2022 6797 729 64.6 MiB 0.05 0.00 4.3867 3.5433 -97.7345 -3.5433 3.5433 0.23 0.000315462 0.000287317 0.0152887 0.0139914 -1 -1 -1 -1 32 1970 20 6.64007e+06 452088 554710. 1919.41 0.89 0.111736 0.0971106 22834 132086 -1 1630 17 815 1410 71619 17962 2.64857 2.64857 -94.6457 -2.64857 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0141874 0.0127433 128 57 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.61 vpr 64.55 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29804 -1 -1 39 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1932 905 16515 4803 9135 2577 64.5 MiB 0.12 0.00 5.16736 4.19576 -104.869 -4.19576 4.19576 0.25 0.000632614 0.000587453 0.0403436 0.0370875 -1 -1 -1 -1 26 2022 22 6.64007e+06 489762 477104. 1650.88 1.09 0.130341 0.115208 21682 110474 -1 1822 20 1097 2083 117673 28230 3.55243 3.55243 -105.89 -3.55243 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0187176 0.0166672 122 27 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 1.68 vpr 64.55 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29788 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 30 32 317 269 1 152 83 17 17 289 -1 unnamed_device 24.5 MiB 0.07 1992 820 8003 2033 5428 542 64.5 MiB 0.05 0.00 4.60481 3.90078 -115.378 -3.90078 3.90078 0.23 0.000302657 0.000277024 0.0153228 0.0140736 -1 -1 -1 -1 32 1752 22 6.64007e+06 263718 554710. 1919.41 0.34 0.0557821 0.0493271 22834 132086 -1 1562 19 1039 1837 109271 27109 2.78277 2.78277 -104.529 -2.78277 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0140966 0.0125822 115 63 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 2.41 vpr 64.68 MiB -1 -1 0.17 18052 1 0.03 -1 -1 29816 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2267 1041 7728 1594 5511 623 64.7 MiB 0.05 0.00 4.51839 3.97836 -130.923 -3.97836 3.97836 0.23 0.000320385 0.000287586 0.0151298 0.0139414 -1 -1 -1 -1 28 2450 20 6.64007e+06 326508 500653. 1732.36 0.96 0.121822 0.106713 21970 115934 -1 2048 20 1250 1844 127691 29643 3.29503 3.29503 -126.978 -3.29503 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0153238 0.0137008 127 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.43 vpr 64.59 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29920 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2060 1087 14716 3609 8495 2612 64.6 MiB 0.08 0.00 5.23607 4.60801 -131.451 -4.60801 4.60801 0.24 0.000305422 0.000279931 0.0231359 0.0211931 -1 -1 -1 -1 30 2215 19 6.64007e+06 464646 526063. 1820.29 1.06 0.136734 0.120549 22546 126617 -1 1958 23 1056 1969 119309 26451 3.47322 3.47322 -117.132 -3.47322 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0158791 0.0141618 134 4 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 1.92 vpr 64.80 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29936 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66360 32 32 350 275 1 209 93 17 17 289 -1 unnamed_device 25.0 MiB 0.15 2681 1037 9753 2581 5955 1217 64.8 MiB 0.07 0.00 6.01073 5.18024 -156.404 -5.18024 5.18024 0.24 0.000336837 0.000308978 0.0215031 0.0199073 -1 -1 -1 -1 32 2480 23 6.64007e+06 364182 554710. 1919.41 0.42 0.0729427 0.0649708 22834 132086 -1 2043 17 1212 1843 105388 26002 4.27189 4.27189 -143.17 -4.27189 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0155817 0.0140506 151 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 2.78 vpr 64.84 MiB -1 -1 0.16 18052 1 0.03 -1 -1 29820 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66396 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2633 929 18196 5476 8417 4303 64.8 MiB 0.08 0.00 5.68167 4.5876 -139.046 -4.5876 4.5876 0.23 0.000362423 0.000326394 0.0296245 0.0269269 -1 -1 -1 -1 34 2649 32 6.64007e+06 464646 585099. 2024.56 1.32 0.155351 0.136509 23122 138558 -1 1938 22 1357 2352 167798 52522 3.76663 3.76663 -127.254 -3.76663 0 0 742403. 2568.87 0.03 0.05 0.08 -1 -1 0.03 0.0180392 0.0161401 143 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 2.96 vpr 64.88 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30224 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66436 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2914 1203 17817 4991 10319 2507 64.9 MiB 0.09 0.00 5.86707 4.47484 -142.898 -4.47484 4.47484 0.23 0.000359612 0.000326009 0.0272184 0.0247497 -1 -1 -1 -1 26 2975 23 6.64007e+06 539994 477104. 1650.88 1.56 0.12861 0.113349 21682 110474 -1 2473 21 1636 3093 192512 45419 3.88183 3.88183 -138.131 -3.88183 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.017884 0.0159925 147 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 1.71 vpr 64.47 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29852 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66020 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 24.3 MiB 0.07 1992 827 11963 3673 6023 2267 64.5 MiB 0.06 0.00 4.80601 3.86158 -112.965 -3.86158 3.86158 0.23 0.000449703 0.000425374 0.0237691 0.022019 -1 -1 -1 -1 32 1758 20 6.64007e+06 263718 554710. 1919.41 0.33 0.060739 0.0541405 22834 132086 -1 1584 20 900 1546 91449 21952 2.74357 2.74357 -100.335 -2.74357 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.015396 0.0137804 109 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 2.41 vpr 64.81 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30148 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 24.9 MiB 0.11 2027 1031 14741 4291 8504 1946 64.8 MiB 0.09 0.00 5.46127 4.75724 -139.41 -4.75724 4.75724 0.25 0.00034081 0.000312004 0.0309057 0.0283983 -1 -1 -1 -1 28 2442 23 6.64007e+06 339066 500653. 1732.36 0.80 0.136583 0.120041 21970 115934 -1 2156 21 1668 2701 170774 41593 4.08103 4.08103 -135.525 -4.08103 0 0 612192. 2118.31 0.04 0.08 0.11 -1 -1 0.04 0.0328061 0.0292899 147 63 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 2.69 vpr 64.76 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30236 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2563 1179 8401 1845 5726 830 64.8 MiB 0.05 0.00 6.4762 5.43878 -158.127 -5.43878 5.43878 0.24 0.000339119 0.000311131 0.0150216 0.0138245 -1 -1 -1 -1 28 2965 25 6.64007e+06 376740 500653. 1732.36 1.19 0.120148 0.105622 21970 115934 -1 2377 19 1306 2106 150947 36744 4.09669 4.09669 -142.216 -4.09669 0 0 612192. 2118.31 0.04 0.07 0.09 -1 -1 0.04 0.0253964 0.0228129 145 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 2.49 vpr 64.77 MiB -1 -1 0.15 17852 1 0.03 -1 -1 30196 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 24.9 MiB 0.17 2657 1228 12698 3369 8227 1102 64.8 MiB 0.07 0.00 6.49901 5.45438 -153.019 -5.45438 5.45438 0.24 0.000328689 0.000301312 0.0205704 0.0188312 -1 -1 -1 -1 28 2672 21 6.64007e+06 439530 500653. 1732.36 0.93 0.119834 0.105177 21970 115934 -1 2273 20 1393 2173 133451 33025 4.68168 4.68168 -150.535 -4.68168 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.018244 0.0164405 152 47 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.04 vpr 64.82 MiB -1 -1 0.19 17908 1 0.03 -1 -1 30140 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2368 1088 19124 5773 11033 2318 64.8 MiB 0.10 0.00 5.27727 4.45304 -133.741 -4.45304 4.45304 0.33 0.000340028 0.000311762 0.0308833 0.0282403 -1 -1 -1 -1 32 2027 17 6.64007e+06 477204 554710. 1919.41 0.34 0.0763852 0.0678982 22834 132086 -1 1840 18 828 1458 87897 20192 2.99843 2.99843 -114.489 -2.99843 0 0 701300. 2426.64 0.03 0.03 0.09 -1 -1 0.03 0.0156678 0.0141019 144 83 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 2.56 vpr 64.62 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29764 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 25.2 MiB 0.12 2717 1084 11771 2992 7832 947 64.6 MiB 0.08 0.00 6.07747 5.03001 -142.129 -5.03001 5.03001 0.24 0.000341787 0.000313273 0.0256136 0.0235617 -1 -1 -1 -1 32 2400 18 6.64007e+06 313950 554710. 1919.41 1.03 0.132022 0.115711 22834 132086 -1 2204 17 1217 2211 124731 29809 3.86283 3.86283 -134.875 -3.86283 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152233 0.0137184 141 57 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 1.75 vpr 64.43 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29736 -1 -1 38 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 29 32 378 310 1 177 99 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2434 959 18567 5802 9719 3046 64.4 MiB 0.10 0.00 5.08141 4.25424 -118.37 -4.25424 4.25424 0.24 0.000348555 0.000319788 0.0336972 0.0310577 -1 -1 -1 -1 32 1868 18 6.64007e+06 477204 554710. 1919.41 0.35 0.0778854 0.0696741 22834 132086 -1 1742 19 1067 1824 102169 25222 2.96197 2.96197 -106.132 -2.96197 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0166391 0.0149238 137 85 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 1.62 vpr 64.12 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29928 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65656 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1776 737 8003 1763 5996 244 64.1 MiB 0.04 0.00 4.47141 3.88758 -112.726 -3.88758 3.88758 0.24 0.000260941 0.000238488 0.0130657 0.0119905 -1 -1 -1 -1 28 1687 18 6.64007e+06 238602 500653. 1732.36 0.33 0.0470139 0.0415744 21970 115934 -1 1415 17 749 1150 66721 17748 2.93797 2.93797 -105.31 -2.93797 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0114493 0.0102428 99 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 1.96 vpr 64.79 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29772 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 25.3 MiB 0.11 2455 1051 10131 2558 6985 588 64.8 MiB 0.06 0.00 5.67067 4.66023 -138.505 -4.66023 4.66023 0.23 0.000342724 0.000314219 0.0174902 0.0160199 -1 -1 -1 -1 32 2099 20 6.64007e+06 439530 554710. 1919.41 0.36 0.0663895 0.058967 22834 132086 -1 1859 21 1036 1822 107535 26414 3.73983 3.73983 -129.269 -3.73983 0 0 701300. 2426.64 0.04 0.07 0.12 -1 -1 0.04 0.0301792 0.0272055 135 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 1.84 vpr 64.88 MiB -1 -1 0.13 17444 1 0.03 -1 -1 30116 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66432 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2786 978 14939 5098 7315 2526 64.9 MiB 0.09 0.00 5.96407 4.77924 -147.588 -4.77924 4.77924 0.23 0.000358013 0.000327645 0.0296295 0.0271703 -1 -1 -1 -1 32 2301 21 6.64007e+06 313950 554710. 1919.41 0.36 0.0769698 0.0685732 22834 132086 -1 1890 22 1749 2967 165614 41703 3.75843 3.75843 -135.029 -3.75843 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0205468 0.0184283 155 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 1.73 vpr 64.52 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29784 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66068 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 24.5 MiB 0.14 2060 1019 8999 2097 6268 634 64.5 MiB 0.05 0.00 5.08536 4.17772 -116.047 -4.17772 4.17772 0.23 0.000432787 0.000408561 0.0145659 0.0133905 -1 -1 -1 -1 26 2304 22 6.64007e+06 313950 477104. 1650.88 0.31 0.0518409 0.0456961 21682 110474 -1 1979 15 909 1262 86214 21433 3.35623 3.35623 -114.421 -3.35623 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0116363 0.0104526 117 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 2.18 vpr 63.69 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30320 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65216 31 32 245 205 1 150 86 17 17 289 -1 unnamed_device 23.9 MiB 0.04 2077 870 15017 4767 7797 2453 63.7 MiB 0.07 0.00 4.82101 3.80732 -109.576 -3.80732 3.80732 0.25 0.000256941 0.000235154 0.022651 0.0207191 -1 -1 -1 -1 30 1774 18 6.64007e+06 288834 526063. 1820.29 0.87 0.101667 0.0884464 22546 126617 -1 1499 20 971 1627 84799 20654 2.75457 2.75457 -100.629 -2.75457 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0128585 0.011425 110 4 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 3.07 vpr 64.81 MiB -1 -1 0.13 17908 1 0.03 -1 -1 30380 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66364 32 32 348 274 1 211 94 17 17 289 -1 unnamed_device 24.9 MiB 0.14 2693 1116 13726 3780 8585 1361 64.8 MiB 0.09 0.00 6.31933 5.03147 -151.742 -5.03147 5.03147 0.26 0.000340195 0.000312031 0.0263611 0.0242555 -1 -1 -1 -1 26 3082 38 6.64007e+06 376740 477104. 1650.88 1.57 0.135113 0.119158 21682 110474 -1 2413 18 1436 1908 121395 30312 4.28008 4.28008 -150.977 -4.28008 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0157398 0.0141925 151 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 3.12 vpr 64.84 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29864 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66400 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 24.9 MiB 0.23 2455 1138 17726 5560 9419 2747 64.8 MiB 0.09 0.00 6.43337 5.25633 -153.723 -5.25633 5.25633 0.24 0.00033534 0.000306284 0.0271419 0.0248337 -1 -1 -1 -1 28 2970 26 6.64007e+06 464646 500653. 1732.36 1.21 0.137274 0.12092 21970 115934 -1 2282 20 1151 1899 136719 33457 4.29708 4.29708 -142.574 -4.29708 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0176497 0.0158217 157 56 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.77 vpr 64.82 MiB -1 -1 0.12 17908 1 0.03 -1 -1 30172 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2789 1287 17058 4718 10081 2259 64.8 MiB 0.11 0.00 6.50947 5.53806 -146.188 -5.53806 5.53806 0.34 0.000845223 0.000792687 0.0343809 0.0317838 -1 -1 -1 -1 30 2736 22 6.64007e+06 539994 526063. 1820.29 1.15 0.160837 0.141766 22546 126617 -1 2231 22 1148 2273 135275 29822 4.48228 4.48228 -138.994 -4.48228 0 0 666494. 2306.21 0.04 0.10 0.10 -1 -1 0.04 0.0419782 0.0376554 162 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 1.72 vpr 64.60 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30204 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 30 32 316 264 1 162 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2263 842 16298 4881 8912 2505 64.6 MiB 0.08 0.00 4.4797 3.59647 -102.523 -3.59647 3.59647 0.23 0.000307307 0.000280621 0.0251614 0.0229662 -1 -1 -1 -1 32 1785 20 6.64007e+06 452088 554710. 1919.41 0.34 0.0656727 0.0582729 22834 132086 -1 1466 19 1042 1950 89350 23678 2.76377 2.76377 -94.1745 -2.76377 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0187442 0.0167254 124 52 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.16 vpr 63.77 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30148 -1 -1 23 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 27 32 255 219 1 132 82 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1707 787 11296 3601 6010 1685 63.8 MiB 0.05 0.00 4.4859 3.4653 -97.6029 -3.4653 3.4653 0.23 0.000259889 0.000238275 0.0182365 0.0167452 -1 -1 -1 -1 32 1511 19 6.64007e+06 288834 554710. 1919.41 0.87 0.102496 0.0888358 22834 132086 -1 1326 21 866 1379 78231 19198 2.71397 2.71397 -92.9443 -2.71397 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0130114 0.0115292 100 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 2.68 vpr 65.09 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30116 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66648 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 25.2 MiB 0.14 3118 1444 14498 4090 9211 1197 65.1 MiB 0.10 0.00 5.55196 4.5101 -140.741 -4.5101 4.5101 0.23 0.000398638 0.000366161 0.0272928 0.0249945 -1 -1 -1 -1 30 3465 22 6.64007e+06 426972 526063. 1820.29 1.05 0.136378 0.119849 22546 126617 -1 2722 21 1607 2624 142172 32764 3.65863 3.65863 -130.646 -3.65863 0 0 666494. 2306.21 0.04 0.06 0.12 -1 -1 0.04 0.0258273 0.0233244 176 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 2.80 vpr 64.80 MiB -1 -1 0.13 18044 1 0.03 -1 -1 29768 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 25.2 MiB 0.23 2629 1132 9336 2424 6148 764 64.8 MiB 0.06 0.00 6.80513 5.51727 -161.811 -5.51727 5.51727 0.24 0.000362914 0.000323191 0.0180721 0.016584 -1 -1 -1 -1 28 2466 20 6.64007e+06 339066 500653. 1732.36 1.25 0.174434 0.153503 21970 115934 -1 2101 19 1237 2000 130018 29929 4.16568 4.16568 -143.37 -4.16568 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0161927 0.0145835 151 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 1.88 vpr 64.64 MiB -1 -1 0.16 18056 1 0.03 -1 -1 30324 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 331 280 1 174 87 17 17 289 -1 unnamed_device 24.9 MiB 0.20 2094 1015 14679 4364 8389 1926 64.6 MiB 0.08 0.00 5.09416 4.33009 -141.29 -4.33009 4.33009 0.24 0.000312539 0.000284692 0.0257348 0.0234754 -1 -1 -1 -1 32 1899 18 6.64007e+06 288834 554710. 1919.41 0.32 0.066431 0.0591023 22834 132086 -1 1719 19 831 1221 79113 18762 3.36323 3.36323 -128.856 -3.36323 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0147407 0.0132364 128 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.01 vpr 64.66 MiB -1 -1 0.12 18056 1 0.04 -1 -1 29908 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 24.7 MiB 0.07 2458 1067 12164 3189 8279 696 64.7 MiB 0.07 0.00 6.37057 5.24988 -134.918 -5.24988 5.24988 0.23 0.000320631 0.000287726 0.018401 0.0167501 -1 -1 -1 -1 26 2581 23 6.64007e+06 452088 477104. 1650.88 0.42 0.0642136 0.0567882 21682 110474 -1 2228 21 1099 1899 121927 29754 3.83082 3.83082 -126.562 -3.83082 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.02192 0.0194781 133 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 2.30 vpr 64.30 MiB -1 -1 0.14 17892 1 0.03 -1 -1 29868 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 31 32 373 294 1 196 102 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2316 1109 11050 2358 7802 890 64.3 MiB 0.06 0.00 5.64915 5.02635 -128.904 -5.02635 5.02635 0.24 0.00034588 0.00031657 0.0180672 0.0165722 -1 -1 -1 -1 30 2070 21 6.64007e+06 489762 526063. 1820.29 0.90 0.13078 0.114565 22546 126617 -1 1846 16 918 1501 68384 17532 4.07422 4.07422 -121.604 -4.07422 0 0 666494. 2306.21 0.03 0.03 0.08 -1 -1 0.03 0.0168693 0.0152914 151 50 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.26 vpr 64.05 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29844 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65584 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 24.6 MiB 0.07 2399 1037 15848 4616 8805 2427 64.0 MiB 0.08 0.00 4.4759 3.71089 -106.291 -3.71089 3.71089 0.24 0.000314293 0.000287759 0.0254439 0.0233391 -1 -1 -1 -1 32 2018 20 6.64007e+06 452088 554710. 1919.41 0.89 0.106875 0.0936934 22834 132086 -1 1894 20 997 1743 113167 25894 2.73777 2.73777 -99.0335 -2.73777 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0155864 0.013987 130 51 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 2.58 vpr 64.82 MiB -1 -1 0.16 18048 1 0.03 -1 -1 29816 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 32 32 350 275 1 215 95 17 17 289 -1 unnamed_device 25.2 MiB 0.17 2711 1355 17159 4707 10238 2214 64.8 MiB 0.11 0.00 6.39133 5.42973 -168.16 -5.42973 5.42973 0.24 0.000333297 0.000305473 0.0305336 0.027931 -1 -1 -1 -1 32 2899 17 6.64007e+06 389298 554710. 1919.41 0.97 0.119619 0.104995 22834 132086 -1 2528 21 1636 2593 168950 38601 4.20469 4.20469 -151.273 -4.20469 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.017333 0.015535 155 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 3.02 vpr 64.88 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29784 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2637 1151 20606 6244 9655 4707 64.9 MiB 0.09 0.00 5.13347 4.30924 -132.442 -4.30924 4.30924 0.26 0.000366994 0.000335366 0.0367992 0.0340036 -1 -1 -1 -1 32 2462 42 6.64007e+06 527436 554710. 1919.41 1.55 0.189485 0.167465 22834 132086 -1 1986 17 1183 1864 116056 30310 3.22157 3.22157 -117.993 -3.22157 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0155732 0.014057 151 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.21 vpr 64.13 MiB -1 -1 0.12 18056 1 0.02 -1 -1 29828 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1582 689 11948 3112 7844 992 64.1 MiB 0.06 0.00 4.48041 4.01678 -109.438 -4.01678 4.01678 0.24 0.000455205 0.000431544 0.0247681 0.0228668 -1 -1 -1 -1 32 1385 20 6.64007e+06 238602 554710. 1919.41 0.86 0.10574 0.0924354 22834 132086 -1 1290 19 791 1195 77092 18865 2.88077 2.88077 -97.6008 -2.88077 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0128196 0.0114748 93 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.41 vpr 64.59 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29936 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 310 266 1 175 90 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2235 1059 15969 4938 9075 1956 64.6 MiB 0.07 0.00 5.20036 4.23876 -128.495 -4.23876 4.23876 0.24 0.000299718 0.000274504 0.0251125 0.0229545 -1 -1 -1 -1 32 2001 23 6.64007e+06 326508 554710. 1919.41 1.01 0.131817 0.114808 22834 132086 -1 1797 18 929 1290 89628 20456 3.08203 3.08203 -115.313 -3.08203 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0136287 0.0122168 123 58 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.97 vpr 64.70 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29924 -1 -1 43 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 31 32 326 261 1 177 106 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2343 905 18606 5361 10083 3162 64.7 MiB 0.09 0.00 5.80407 4.54858 -124.201 -4.54858 4.54858 0.24 0.000312841 0.000285299 0.0289889 0.0265187 -1 -1 -1 -1 28 2713 40 6.64007e+06 539994 500653. 1732.36 1.50 0.168338 0.147939 21970 115934 -1 2157 23 1491 2776 199878 49701 3.88503 3.88503 -124.264 -3.88503 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0168966 0.0150698 138 33 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 1.83 vpr 64.50 MiB -1 -1 0.16 17672 1 0.03 -1 -1 29820 -1 -1 26 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66044 29 32 262 224 1 168 87 17 17 289 -1 unnamed_device 24.5 MiB 0.14 1937 1016 11799 3172 7074 1553 64.5 MiB 0.06 0.00 4.85327 4.04852 -112.319 -4.04852 4.04852 0.23 0.000270092 0.000247629 0.0179409 0.0164448 -1 -1 -1 -1 26 2153 18 6.64007e+06 326508 477104. 1650.88 0.29 0.0517776 0.0458058 21682 110474 -1 1918 18 889 1186 72681 17751 3.29122 3.29122 -107.623 -3.29122 0 0 585099. 2024.56 0.04 0.06 0.09 -1 -1 0.04 0.0283681 0.0254054 116 31 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.23 vpr 64.48 MiB -1 -1 0.10 18052 1 0.02 -1 -1 29788 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1781 947 10883 2848 6498 1537 64.5 MiB 0.05 0.00 4.52641 4.02095 -125.546 -4.02095 4.02095 0.23 0.00027826 0.000254627 0.0185587 0.0170438 -1 -1 -1 -1 30 1980 22 6.64007e+06 238602 526063. 1820.29 0.93 0.111158 0.096955 22546 126617 -1 1771 19 1115 1979 106566 25643 2.79377 2.79377 -111.145 -2.79377 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0130158 0.0116049 111 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.54 vpr 64.81 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29768 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2560 1034 12876 3096 8656 1124 64.8 MiB 0.07 0.00 4.91801 4.20195 -124.421 -4.20195 4.20195 0.24 0.000360523 0.000329806 0.0257987 0.023957 -1 -1 -1 -1 32 2018 22 6.64007e+06 502320 554710. 1919.41 1.02 0.149989 0.131986 22834 132086 -1 1831 17 1180 1846 100223 25917 2.96877 2.96877 -113.134 -2.96877 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152364 0.0137279 141 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.41 vpr 64.49 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29848 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 24.9 MiB 0.10 1957 849 12568 3841 6272 2455 64.5 MiB 0.08 0.00 4.49165 3.90436 -116.108 -3.90436 3.90436 0.25 0.000270822 0.000247709 0.0271462 0.0251465 -1 -1 -1 -1 32 1843 22 6.64007e+06 313950 554710. 1919.41 0.99 0.126567 0.110341 22834 132086 -1 1628 20 997 1467 92295 22084 2.90603 2.90603 -105.107 -2.90603 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0130624 0.0116593 113 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.19 vpr 64.75 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29776 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2312 1072 14671 3700 9355 1616 64.8 MiB 0.07 0.00 4.37944 3.68167 -112.793 -3.68167 3.68167 0.23 0.000328231 0.000299444 0.0224555 0.0205477 -1 -1 -1 -1 26 2288 20 6.64007e+06 464646 477104. 1650.88 0.82 0.108143 0.0950909 21682 110474 -1 1944 21 1079 1949 120319 27849 2.90097 2.90097 -107.811 -2.90097 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0169673 0.0152162 131 57 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 1.81 vpr 64.74 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30212 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 24.7 MiB 0.13 2484 1002 10815 2483 7746 586 64.7 MiB 0.06 0.00 4.7433 4.0221 -125.424 -4.0221 4.0221 0.24 0.000397566 0.000334154 0.0194519 0.0177821 -1 -1 -1 -1 30 2069 23 6.64007e+06 452088 526063. 1820.29 0.35 0.0685942 0.0607519 22546 126617 -1 1876 21 1394 2192 129190 30545 3.12957 3.12957 -117.777 -3.12957 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0174038 0.015566 145 91 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 1.76 vpr 64.49 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29744 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1814 857 7770 1801 5584 385 64.5 MiB 0.10 0.00 3.8549 3.3869 -105.248 -3.3869 3.3869 0.26 0.000808908 0.000752472 0.036892 0.0342639 -1 -1 -1 -1 30 1717 23 6.64007e+06 251160 526063. 1820.29 0.36 0.0758761 0.0680954 22546 126617 -1 1505 18 707 1177 69640 16846 2.62037 2.62037 -101.98 -2.62037 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0131102 0.0117754 111 57 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 1.88 vpr 64.57 MiB -1 -1 0.11 18436 1 0.02 -1 -1 29784 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 290 244 1 177 89 17 17 289 -1 unnamed_device 24.5 MiB 0.13 2414 1035 16127 4715 9194 2218 64.6 MiB 0.08 0.00 5.19407 4.38701 -135.203 -4.38701 4.38701 0.30 0.000285817 0.00026167 0.0250029 0.0228938 -1 -1 -1 -1 28 2331 19 6.64007e+06 313950 500653. 1732.36 0.35 0.061641 0.0547906 21970 115934 -1 1998 18 1184 1766 112327 26702 3.18183 3.18183 -121.919 -3.18183 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0156723 0.0140089 123 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.90 vpr 64.68 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29532 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 318 257 1 194 92 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2494 951 15617 4720 8033 2864 64.7 MiB 0.08 0.00 5.8041 4.77338 -128.314 -4.77338 4.77338 0.24 0.000322955 0.000295402 0.0258152 0.0235919 -1 -1 -1 -1 30 2411 22 6.64007e+06 351624 526063. 1820.29 1.43 0.116548 0.102484 22546 126617 -1 1780 20 1025 1564 87363 22048 3.81583 3.81583 -122.51 -3.81583 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0154909 0.0139488 138 30 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.09 vpr 64.66 MiB -1 -1 0.14 18044 1 0.03 -1 -1 29808 -1 -1 36 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2020 1028 6757 1470 4618 669 64.7 MiB 0.04 0.00 4.83347 4.36984 -119.357 -4.36984 4.36984 0.24 0.000308469 0.000282152 0.0111219 0.0102283 -1 -1 -1 -1 26 2136 15 6.64007e+06 452088 477104. 1650.88 0.68 0.0886405 0.0772855 21682 110474 -1 1886 18 837 1482 89240 21546 3.02743 3.02743 -103.989 -3.02743 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0143245 0.0128477 129 55 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 2.68 vpr 64.55 MiB -1 -1 0.22 18440 1 0.03 -1 -1 30148 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66104 32 32 393 312 1 213 93 17 17 289 -1 unnamed_device 25.2 MiB 0.17 2426 1118 15843 4746 8389 2708 64.6 MiB 0.09 0.00 6.27101 5.72815 -176.849 -5.72815 5.72815 0.24 0.000376256 0.00034593 0.0315166 0.028967 -1 -1 -1 -1 32 2546 19 6.64007e+06 364182 554710. 1919.41 1.03 0.159075 0.140221 22834 132086 -1 2255 20 1391 2068 146331 34168 4.58628 4.58628 -155.397 -4.58628 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0179246 0.0161235 158 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.12 vpr 64.08 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29692 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 24.3 MiB 0.03 1660 747 7221 1683 5260 278 64.1 MiB 0.04 0.00 3.9861 3.49806 -100.112 -3.49806 3.49806 0.24 0.000247913 0.000227211 0.0112366 0.0103119 -1 -1 -1 -1 30 1664 18 6.64007e+06 263718 526063. 1820.29 0.90 0.0946062 0.0821045 22546 126617 -1 1301 16 550 893 50864 12892 2.64857 2.64857 -91.973 -2.64857 0 0 666494. 2306.21 0.03 0.02 0.07 -1 -1 0.03 0.0106208 0.00956507 100 4 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 1.94 vpr 64.96 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29708 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66516 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2451 1087 18431 5518 10395 2518 65.0 MiB 0.11 0.00 5.50696 4.44233 -144.688 -4.44233 4.44233 0.23 0.00038496 0.000353611 0.0389541 0.0358696 -1 -1 -1 -1 32 2221 20 6.64007e+06 464646 554710. 1919.41 0.39 0.0947235 0.0847517 22834 132086 -1 1905 18 1214 1798 108778 25534 3.75862 3.75862 -135.309 -3.75862 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0201159 0.0182483 146 90 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 1.77 vpr 64.17 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29824 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 376 318 1 155 82 17 17 289 -1 unnamed_device 24.4 MiB 0.12 1766 955 11830 3130 7536 1164 64.2 MiB 0.06 0.00 4.1133 3.5251 -125.052 -3.5251 3.5251 0.24 0.000330759 0.000302081 0.0243994 0.022357 -1 -1 -1 -1 32 1865 20 6.64007e+06 226044 554710. 1919.41 0.36 0.0677556 0.0602023 22834 132086 -1 1684 21 1128 1645 110610 25795 2.66437 2.66437 -115.654 -2.66437 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0168254 0.0150063 116 96 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.72 vpr 64.39 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29776 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2247 944 17427 4836 9376 3215 64.4 MiB 0.13 0.00 4.122 4.04884 -119.999 -4.04884 4.04884 0.23 0.000618313 0.000568585 0.0416241 0.038231 -1 -1 -1 -1 28 2356 26 6.64007e+06 439530 500653. 1732.36 1.26 0.157839 0.139557 21970 115934 -1 1861 17 982 1579 105965 27943 3.13537 3.13537 -108.58 -3.13537 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.015124 0.0136237 134 60 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 2.66 vpr 64.63 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29808 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66180 32 32 396 299 1 236 97 17 17 289 -1 unnamed_device 25.2 MiB 0.18 3069 1434 11863 3029 7657 1177 64.6 MiB 0.10 0.00 7.74409 6.65703 -196.862 -6.65703 6.65703 0.23 0.000392613 0.000361026 0.02616 0.0242474 -1 -1 -1 -1 30 2977 29 6.64007e+06 414414 526063. 1820.29 1.12 0.168442 0.148951 22546 126617 -1 2525 20 1541 2230 119707 29396 5.29994 5.29994 -175.636 -5.29994 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.019447 0.0175604 178 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 1.65 vpr 64.08 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30200 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 30 32 224 207 1 138 85 17 17 289 -1 unnamed_device 24.9 MiB 0.10 1779 825 13663 4108 8029 1526 64.1 MiB 0.05 0.00 3.77619 3.29107 -101.735 -3.29107 3.29107 0.23 0.000232903 0.000213388 0.0185332 0.0169707 -1 -1 -1 -1 26 1653 18 6.64007e+06 288834 477104. 1650.88 0.27 0.0489107 0.0432584 21682 110474 -1 1457 16 625 800 52338 13195 2.38617 2.38617 -94.87 -2.38617 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00980788 0.00878496 93 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.23 vpr 64.48 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30180 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1551 715 8831 2097 6321 413 64.5 MiB 0.04 0.00 4.64461 4.13192 -117.713 -4.13192 4.13192 0.23 0.000283608 0.000257957 0.0163788 0.0150423 -1 -1 -1 -1 32 1455 18 6.64007e+06 238602 554710. 1919.41 0.87 0.0917998 0.0799261 22834 132086 -1 1299 17 693 1155 74739 18315 2.98597 2.98597 -106.773 -2.98597 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0161838 0.0144625 95 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 1.80 vpr 64.14 MiB -1 -1 0.21 17672 1 0.03 -1 -1 29604 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65676 32 32 296 247 1 157 87 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2105 944 14103 4753 7503 1847 64.1 MiB 0.07 0.00 4.1763 3.40707 -111.974 -3.40707 3.40707 0.23 0.000441972 0.000415373 0.023287 0.0213172 -1 -1 -1 -1 32 1961 19 6.64007e+06 288834 554710. 1919.41 0.34 0.0611781 0.0542074 22834 132086 -1 1733 21 1059 1936 116096 28016 2.87177 2.87177 -111.073 -2.87177 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0147393 0.0131377 119 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 2.33 vpr 64.04 MiB -1 -1 0.10 18056 1 0.02 -1 -1 29888 -1 -1 31 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65572 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 24.9 MiB 0.03 1494 591 13153 4635 5984 2534 64.0 MiB 0.05 0.00 4.0913 3.45027 -80.5708 -3.45027 3.45027 0.25 0.000229 0.00020925 0.0176622 0.0161781 -1 -1 -1 -1 28 1498 20 6.64007e+06 389298 500653. 1732.36 1.02 0.117375 0.102145 21970 115934 -1 1204 20 767 1265 67303 18216 2.69777 2.69777 -76.5165 -2.69777 0 0 612192. 2118.31 0.03 0.03 0.08 -1 -1 0.03 0.0133537 0.0119732 93 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 2.42 vpr 64.81 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29772 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66364 32 32 376 307 1 185 88 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2264 1161 14323 4312 8018 1993 64.8 MiB 0.10 0.00 5.34776 4.34527 -135.212 -4.34527 4.34527 0.25 0.000775451 0.00072278 0.0348073 0.0320495 -1 -1 -1 -1 26 2998 22 6.64007e+06 301392 477104. 1650.88 0.83 0.118776 0.10489 21682 110474 -1 2499 16 1260 2258 137367 32949 3.70982 3.70982 -129.996 -3.70982 0 0 585099. 2024.56 0.04 0.07 0.07 -1 -1 0.04 0.0305887 0.02766 137 72 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 3.06 vpr 64.97 MiB -1 -1 0.14 18056 1 0.04 -1 -1 30020 -1 -1 42 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66532 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 25.6 MiB 0.11 2647 843 12949 3259 8450 1240 65.0 MiB 0.09 0.00 4.62461 4.03784 -124.693 -4.03784 4.03784 0.24 0.000379639 0.000344151 0.0272347 0.0251462 -1 -1 -1 -1 28 2404 29 6.64007e+06 527436 500653. 1732.36 1.36 0.169941 0.15025 21970 115934 -1 1842 19 1533 2462 139710 38054 3.40377 3.40377 -121.42 -3.40377 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0196062 0.0175902 148 90 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2387 1221 13961 4223 7808 1930 64.3 MiB 0.10 0.00 5.99396 4.81396 -139.964 -4.81396 4.81396 0.25 0.000338399 0.000310271 0.0346576 0.0320334 -1 -1 -1 -1 28 2736 20 6.65987e+06 380340 500653. 1732.36 1.05 0.148244 0.130948 21970 115934 -1 2265 22 1517 2342 156634 37698 4.01363 4.01363 -138.509 -4.01363 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0176982 0.015846 147 63 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 1.88 vpr 64.51 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30216 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 32 32 299 247 1 188 94 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2525 994 9892 2479 6892 521 64.5 MiB 0.06 0.00 5.48484 4.34823 -112.31 -4.34823 4.34823 0.24 0.000492363 0.000456063 0.0191802 0.0176607 -1 -1 -1 -1 26 2792 43 6.65987e+06 380340 477104. 1650.88 0.57 0.0721775 0.0637459 21682 110474 -1 2032 20 1364 1969 121340 31274 3.49631 3.49631 -112.125 -3.49631 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0150753 0.0135285 129 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.22 vpr 64.45 MiB -1 -1 0.15 18056 1 0.03 -1 -1 30124 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 24.7 MiB 0.04 2219 1039 14996 4248 8800 1948 64.4 MiB 0.08 0.00 5.26215 4.26714 -116.661 -4.26714 4.26714 0.24 0.000302092 0.000276833 0.0237687 0.02172 -1 -1 -1 -1 26 2187 23 6.65987e+06 393018 477104. 1650.88 0.82 0.105402 0.0923726 21682 110474 -1 1980 24 1460 2740 181180 44106 3.71485 3.71485 -115.237 -3.71485 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0193045 0.0170988 132 31 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.42 vpr 64.53 MiB -1 -1 0.11 18292 1 0.03 -1 -1 30208 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2401 1053 15203 4130 9477 1596 64.5 MiB 0.08 0.00 5.31844 4.32872 -126.669 -4.32872 4.32872 0.23 0.000320268 0.000292697 0.025632 0.0234395 -1 -1 -1 -1 32 2377 17 6.65987e+06 354984 554710. 1919.41 1.04 0.128557 0.112316 22834 132086 -1 2184 20 1318 2611 177400 41362 3.28085 3.28085 -117.499 -3.28085 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0162517 0.0145872 134 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.21 vpr 64.70 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29604 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 25.2 MiB 0.04 2589 1122 12876 3256 8561 1059 64.7 MiB 0.07 0.00 4.08553 3.2871 -114.846 -3.2871 3.2871 0.24 0.000367425 0.000337979 0.0203682 0.018632 -1 -1 -1 -1 26 2486 22 6.65987e+06 494442 477104. 1650.88 0.84 0.116554 0.102469 21682 110474 -1 2096 17 1159 1903 117864 29212 3.03931 3.03931 -115.398 -3.03931 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.016059 0.0145175 145 58 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.22 vpr 64.25 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30136 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1585 699 13324 5476 6895 953 64.2 MiB 0.06 0.00 4.35015 3.70388 -99.5965 -3.70388 3.70388 0.24 0.000265705 0.000243102 0.0220906 0.0202858 -1 -1 -1 -1 32 1384 19 6.65987e+06 266238 554710. 1919.41 0.86 0.104037 0.0904849 22834 132086 -1 1269 20 872 1519 90801 22733 2.68351 2.68351 -90.0723 -2.68351 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0133136 0.0118923 97 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.19 vpr 64.39 MiB -1 -1 0.12 17284 1 0.02 -1 -1 29624 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2037 1041 15848 4643 9032 2173 64.4 MiB 0.08 0.00 3.96304 3.28184 -98.7666 -3.28184 3.28184 0.23 0.000338791 0.000314774 0.0269531 0.0249084 -1 -1 -1 -1 26 2326 21 6.65987e+06 443730 477104. 1650.88 0.83 0.10049 0.0888051 21682 110474 -1 2048 20 1142 2144 140940 33098 2.61165 2.61165 -95.2482 -2.61165 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0141719 0.012715 123 4 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.35 vpr 64.45 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29784 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 31 32 317 271 1 168 88 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2086 993 10423 2723 6384 1316 64.5 MiB 0.07 0.00 3.77724 3.3699 -115.032 -3.3699 3.3699 0.25 0.000671767 0.000645824 0.0231996 0.0214673 -1 -1 -1 -1 32 1809 20 6.65987e+06 316950 554710. 1919.41 0.92 0.127375 0.111058 22834 132086 -1 1615 20 794 1199 70607 17725 2.71311 2.71311 -106.08 -2.71311 0 0 701300. 2426.64 0.03 0.07 0.07 -1 -1 0.03 0.0328717 0.0293078 117 64 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.60 vpr 64.36 MiB -1 -1 0.19 17660 1 0.03 -1 -1 29748 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 24.9 MiB 0.07 1795 844 9983 2313 7049 621 64.4 MiB 0.06 0.00 4.44435 3.77949 -122.028 -3.77949 3.77949 0.23 0.000293552 0.000268791 0.0198136 0.0182461 -1 -1 -1 -1 32 1846 16 6.65987e+06 240882 554710. 1919.41 0.94 0.121669 0.106343 22834 132086 -1 1731 18 979 1642 97359 24956 2.64251 2.64251 -108.37 -2.64251 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0139297 0.0125035 115 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 1.67 vpr 63.78 MiB -1 -1 0.12 18436 1 0.02 -1 -1 29804 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65308 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.9 MiB 0.06 1674 802 13206 4528 6671 2007 63.8 MiB 0.06 0.00 4.47555 3.77152 -109.712 -3.77152 3.77152 0.24 0.000293529 0.000268875 0.0245645 0.0225758 -1 -1 -1 -1 32 1549 21 6.65987e+06 240882 554710. 1919.41 0.31 0.0629295 0.0559363 22834 132086 -1 1379 21 624 931 58999 14595 2.67371 2.67371 -95.9888 -2.67371 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0197524 0.0176291 101 63 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.16 vpr 64.39 MiB -1 -1 0.12 17912 1 0.02 -1 -1 29688 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 24.8 MiB 0.05 2346 870 8343 1986 6056 301 64.4 MiB 0.05 0.00 4.65034 3.60712 -112.822 -3.60712 3.60712 0.23 0.00027589 0.000251814 0.013582 0.0124272 -1 -1 -1 -1 30 2025 25 6.65987e+06 291594 526063. 1820.29 0.87 0.0938097 0.0815367 22546 126617 -1 1544 16 760 1070 57907 15189 2.73385 2.73385 -101.25 -2.73385 0 0 666494. 2306.21 0.02 0.03 0.07 -1 -1 0.02 0.0118484 0.0106631 110 34 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2535 916 19223 6040 10330 2853 64.3 MiB 0.10 0.00 5.72495 4.44986 -128.732 -4.44986 4.44986 0.31 0.000335278 0.000306305 0.0326129 0.0298459 -1 -1 -1 -1 28 2781 28 6.65987e+06 431052 500653. 1732.36 1.60 0.164036 0.144127 21970 115934 -1 2095 22 1720 2855 211888 56822 3.64231 3.64231 -126.124 -3.64231 0 0 612192. 2118.31 0.02 0.07 0.07 -1 -1 0.02 0.0230006 0.0205473 139 61 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.35 vpr 63.86 MiB -1 -1 0.19 17672 1 0.03 -1 -1 29892 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65388 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 24.3 MiB 0.06 1651 644 11064 3432 5040 2592 63.9 MiB 0.05 0.00 3.69173 2.97053 -85.1657 -2.97053 2.97053 0.23 0.000259807 0.000238065 0.0167708 0.015379 -1 -1 -1 -1 32 1255 21 6.65987e+06 291594 554710. 1919.41 0.93 0.10113 0.0875946 22834 132086 -1 1067 19 701 1169 54274 15412 2.52431 2.52431 -81.3486 -2.52431 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0133753 0.0119419 103 27 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 1.85 vpr 64.63 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29772 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66184 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2380 968 16819 5706 8070 3043 64.6 MiB 0.11 0.00 4.6711 4.04346 -120.969 -4.04346 4.04346 0.24 0.000352021 0.000322419 0.0406105 0.0374978 -1 -1 -1 -1 32 2265 23 6.65987e+06 342306 554710. 1919.41 0.38 0.0901688 0.0809194 22834 132086 -1 1906 20 1277 2430 141211 36257 3.18037 3.18037 -113.866 -3.18037 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0169663 0.0152628 138 58 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 2.08 vpr 64.57 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29812 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2606 1180 9821 2681 6536 604 64.6 MiB 0.08 0.00 5.38841 4.32378 -139.417 -4.32378 4.32378 0.25 0.000791528 0.000740611 0.0268259 0.0249583 -1 -1 -1 -1 32 2326 24 6.65987e+06 354984 554710. 1919.41 0.36 0.0762524 0.0683985 22834 132086 -1 2119 19 1135 1613 108552 25602 2.99237 2.99237 -119.109 -2.99237 0 0 701300. 2426.64 0.04 0.06 0.13 -1 -1 0.04 0.0273834 0.0246954 144 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.62 vpr 64.43 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29744 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65980 32 32 323 276 1 153 98 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2090 920 16748 5345 9445 1958 64.4 MiB 0.08 0.00 3.59784 2.86781 -104.206 -2.86781 2.86781 0.24 0.000333852 0.000306347 0.0276424 0.0253042 -1 -1 -1 -1 26 2004 20 6.65987e+06 431052 477104. 1650.88 1.02 0.118539 0.104012 21682 110474 -1 1752 18 988 1648 111876 27246 2.22331 2.22331 -97.4468 -2.22331 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0138236 0.0124016 115 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 2.42 vpr 63.84 MiB -1 -1 0.19 17668 1 0.03 -1 -1 29836 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65372 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 24.6 MiB 0.04 1535 577 8022 1971 5649 402 63.8 MiB 0.04 0.00 2.83187 2.23087 -73.1637 -2.23087 2.23087 0.26 0.000238925 0.000219996 0.016597 0.0153503 -1 -1 -1 -1 32 1160 20 6.65987e+06 215526 554710. 1919.41 0.89 0.0914579 0.0795766 22834 132086 -1 1031 16 512 757 46741 12549 1.68145 1.68145 -71.9785 -1.68145 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.00974086 0.00870837 85 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 1.84 vpr 64.21 MiB -1 -1 0.14 17912 1 0.03 -1 -1 29612 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 31 32 291 243 1 171 87 17 17 289 -1 unnamed_device 24.5 MiB 0.13 2125 1025 13911 4279 7725 1907 64.2 MiB 0.09 0.00 5.78495 4.84052 -144.776 -4.84052 4.84052 0.24 0.000318651 0.000293292 0.0318166 0.0293921 -1 -1 -1 -1 32 1975 23 6.65987e+06 304272 554710. 1919.41 0.37 0.0796161 0.0710669 22834 132086 -1 1717 18 884 1286 76003 18888 3.38591 3.38591 -126.147 -3.38591 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0139715 0.012598 127 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 2.67 vpr 64.59 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29900 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2331 1127 17961 5306 10774 1881 64.6 MiB 0.09 0.00 5.44296 4.25196 -133.571 -4.25196 4.25196 0.24 0.000328108 0.000300221 0.0278798 0.0255437 -1 -1 -1 -1 32 2239 20 6.65987e+06 469086 554710. 1919.41 1.28 0.164041 0.144183 22834 132086 -1 2044 20 1134 1882 137464 30497 3.52443 3.52443 -125.531 -3.52443 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0164691 0.0147989 140 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 1.94 vpr 64.74 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29936 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2693 1105 8735 1790 6509 436 64.7 MiB 0.07 0.00 5.32033 4.24321 -129.182 -4.24321 4.24321 0.24 0.000355888 0.000326787 0.021586 0.0199751 -1 -1 -1 -1 32 2756 25 6.65987e+06 393018 554710. 1919.41 0.41 0.0732554 0.0652145 22834 132086 -1 2171 17 1204 1933 126107 29946 3.40551 3.40551 -121.526 -3.40551 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0163433 0.014756 151 62 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 1.60 vpr 63.71 MiB -1 -1 0.10 17672 1 0.02 -1 -1 29788 -1 -1 20 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65236 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 24.1 MiB 0.04 1349 468 11200 4643 5749 808 63.7 MiB 0.04 0.00 2.72887 2.30927 -65.1311 -2.30927 2.30927 0.23 0.000202817 0.000184723 0.0152371 0.0139236 -1 -1 -1 -1 28 1180 20 6.65987e+06 253560 500653. 1732.36 0.32 0.0421095 0.0370717 21970 115934 -1 973 22 671 1041 63401 16945 1.84505 1.84505 -64.3919 -1.84505 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0104773 0.00928288 81 30 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.48 vpr 64.38 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29792 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2052 1025 13751 4494 6800 2457 64.4 MiB 0.09 0.00 4.848 4.36895 -121.042 -4.36895 4.36895 0.24 0.000289177 0.000264542 0.0307812 0.0282922 -1 -1 -1 -1 30 2062 23 6.65987e+06 316950 526063. 1820.29 1.05 0.119757 0.105578 22546 126617 -1 1919 21 1129 2131 143866 32712 3.23591 3.23591 -111.109 -3.23591 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0153198 0.013733 125 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.21 vpr 63.69 MiB -1 -1 0.09 17676 1 0.03 -1 -1 29708 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65220 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 24.1 MiB 0.05 1447 545 12331 4341 5596 2394 63.7 MiB 0.04 0.00 2.73393 2.35833 -70.1665 -2.35833 2.35833 0.24 0.000200135 0.000182493 0.0152465 0.0138979 -1 -1 -1 -1 28 1272 22 6.65987e+06 215526 500653. 1732.36 0.84 0.0753932 0.0656314 21970 115934 -1 1023 19 461 533 38297 10550 1.69971 1.69971 -68.1319 -1.69971 0 0 612192. 2118.31 0.02 0.02 0.09 -1 -1 0.02 0.00930423 0.00823659 82 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.70 vpr 64.46 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30148 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2081 896 13487 3921 6875 2691 64.5 MiB 0.07 0.00 5.05175 4.41269 -119.651 -4.41269 4.41269 0.24 0.000297513 0.000271843 0.0207646 0.019033 -1 -1 -1 -1 30 2108 21 6.65987e+06 393018 526063. 1820.29 1.30 0.141092 0.123292 22546 126617 -1 1652 20 867 1525 86666 21900 3.26785 3.26785 -105.916 -3.26785 0 0 666494. 2306.21 0.03 0.04 0.08 -1 -1 0.03 0.0170098 0.0152863 126 24 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.92 vpr 63.70 MiB -1 -1 0.11 17664 1 0.03 -1 -1 29928 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65232 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 24.1 MiB 0.03 2388 1023 19624 6470 10444 2710 63.7 MiB 0.16 0.00 4.58506 3.64141 -104.769 -3.64141 3.64141 0.25 0.000560476 0.000510967 0.0484126 0.0441709 -1 -1 -1 -1 26 2542 46 6.65987e+06 494442 477104. 1650.88 1.29 0.168586 0.149805 21682 110474 -1 2045 18 1075 2003 124306 31296 3.00917 3.00917 -106.461 -3.00917 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0140512 0.0126467 136 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.79 vpr 64.55 MiB -1 -1 0.21 18044 1 0.04 -1 -1 30164 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 32 32 338 277 1 179 98 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2305 1091 18323 5790 9817 2716 64.6 MiB 0.09 0.00 5.46249 4.55003 -127.972 -4.55003 4.55003 0.24 0.000318033 0.000290194 0.0282284 0.0257753 -1 -1 -1 -1 30 2249 26 6.65987e+06 431052 526063. 1820.29 1.08 0.140788 0.122545 22546 126617 -1 1876 22 1106 1999 115126 27433 3.41605 3.41605 -116.12 -3.41605 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0170675 0.0152663 132 50 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.16 vpr 64.35 MiB -1 -1 0.11 18056 1 0.04 -1 -1 29776 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1848 913 13291 3770 7974 1547 64.3 MiB 0.06 0.00 3.57584 2.90053 -103.342 -2.90053 2.90053 0.24 0.000281589 0.000257719 0.0224208 0.0205218 -1 -1 -1 -1 28 1955 21 6.65987e+06 266238 500653. 1732.36 0.80 0.109728 0.0958161 21970 115934 -1 1804 21 1025 1722 112193 27509 2.68265 2.68265 -105.703 -2.68265 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0146769 0.0131164 107 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.40 vpr 64.27 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29776 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65808 30 32 262 227 1 135 86 17 17 289 -1 unnamed_device 24.3 MiB 0.04 1630 651 8969 1996 5970 1003 64.3 MiB 0.06 0.00 3.39847 3.05504 -90.9474 -3.05504 3.05504 0.25 0.000642942 0.000600414 0.0237623 0.0220744 -1 -1 -1 -1 28 1977 31 6.65987e+06 304272 500653. 1732.36 1.09 0.126607 0.110752 21970 115934 -1 1470 22 937 1443 90491 25132 2.67851 2.67851 -92.6094 -2.67851 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.01419 0.0126255 100 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 2.45 vpr 64.29 MiB -1 -1 0.12 18056 1 0.02 -1 -1 29432 -1 -1 24 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 24.9 MiB 0.03 1903 614 8319 1869 5547 903 64.3 MiB 0.04 0.00 4.15324 3.37407 -91.8212 -3.37407 3.37407 0.24 0.000265987 0.000243464 0.0137025 0.012562 -1 -1 -1 -1 28 1780 25 6.65987e+06 304272 500653. 1732.36 1.08 0.111413 0.0967491 21970 115934 -1 1400 26 1051 1933 126779 34231 2.79571 2.79571 -93.3762 -2.79571 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0181639 0.0161746 104 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 2.08 vpr 64.27 MiB -1 -1 0.10 17672 1 0.03 -1 -1 29812 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2077 937 13663 4386 7373 1904 64.3 MiB 0.07 0.00 4.42935 3.71432 -111.148 -3.71432 3.71432 0.24 0.000318555 0.000292319 0.0221483 0.0202869 -1 -1 -1 -1 30 1919 20 6.65987e+06 266238 526063. 1820.29 0.76 0.0917732 0.0801906 22546 126617 -1 1728 21 1075 1786 109331 25720 2.65051 2.65051 -104.501 -2.65051 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0142262 0.0127329 116 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 1.97 vpr 64.33 MiB -1 -1 0.12 17668 1 0.03 -1 -1 29800 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65876 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1915 835 10827 2687 7563 577 64.3 MiB 0.09 0.00 3.84464 3.33721 -100.19 -3.33721 3.33721 0.35 0.000522039 0.00047658 0.0275881 0.0251882 -1 -1 -1 -1 26 1992 24 6.65987e+06 418374 477104. 1650.88 0.54 0.0791696 0.0702585 21682 110474 -1 1818 16 954 1675 105836 27778 2.82585 2.82585 -102.328 -2.82585 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0117904 0.0105846 111 30 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 1.74 vpr 64.40 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30200 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2169 872 17273 5743 9135 2395 64.4 MiB 0.07 0.00 3.81664 3.21564 -100.08 -3.21564 3.21564 0.24 0.000287972 0.000263067 0.0258344 0.0235912 -1 -1 -1 -1 32 1641 19 6.65987e+06 393018 554710. 1919.41 0.35 0.0669967 0.0594516 22834 132086 -1 1488 14 765 1169 65775 17191 2.31791 2.31791 -88.1097 -2.31791 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0124866 0.0111334 112 54 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 2.12 vpr 64.70 MiB -1 -1 0.16 18436 1 0.03 -1 -1 29616 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2308 1244 18356 5163 9963 3230 64.7 MiB 0.10 0.00 4.39192 3.92829 -113.996 -3.92829 3.92829 0.25 0.000749949 0.000718237 0.0389664 0.0359702 -1 -1 -1 -1 32 2640 24 6.65987e+06 532476 554710. 1919.41 0.44 0.095081 0.0852499 22834 132086 -1 2262 21 1317 2612 179532 41270 3.25579 3.25579 -109.354 -3.25579 0 0 701300. 2426.64 0.03 0.08 0.13 -1 -1 0.03 0.0355269 0.0316882 158 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 1.87 vpr 64.75 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29764 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2421 1098 16654 4458 10225 1971 64.7 MiB 0.10 0.00 4.43155 3.83032 -129.396 -3.83032 3.83032 0.24 0.000365598 0.000334178 0.0332215 0.0304978 -1 -1 -1 -1 28 2395 21 6.65987e+06 519798 500653. 1732.36 0.37 0.0820495 0.0733414 21970 115934 -1 2087 22 1631 2798 163826 40220 2.88617 2.88617 -117.628 -2.88617 0 0 612192. 2118.31 0.03 0.05 0.06 -1 -1 0.03 0.0206196 0.0184833 150 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 1.74 vpr 64.39 MiB -1 -1 0.13 17912 1 0.03 -1 -1 29804 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 24.3 MiB 0.05 2417 954 13883 3379 9484 1020 64.4 MiB 0.07 0.00 4.94055 4.24332 -124.031 -4.24332 4.24332 0.24 0.000288508 0.000262756 0.0228909 0.0208676 -1 -1 -1 -1 32 1963 21 6.65987e+06 291594 554710. 1919.41 0.33 0.0612728 0.0542438 22834 132086 -1 1756 20 823 1155 77844 19870 2.98031 2.98031 -108.773 -2.98031 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0143922 0.0129215 114 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.26 vpr 64.67 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30520 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66224 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2217 1128 16238 4900 9111 2227 64.7 MiB 0.09 0.00 4.7803 3.9389 -118.342 -3.9389 3.9389 0.24 0.000337036 0.000307837 0.0287174 0.0262948 -1 -1 -1 -1 30 2357 17 6.65987e+06 367662 526063. 1820.29 0.85 0.125417 0.110734 22546 126617 -1 2060 20 1126 2079 105239 26274 2.83077 2.83077 -109.668 -2.83077 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0172833 0.0155108 145 61 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.99 vpr 64.78 MiB -1 -1 0.17 18440 1 0.03 -1 -1 29768 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 31 32 377 302 1 233 99 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2995 1450 19023 5551 11450 2022 64.8 MiB 0.12 0.00 7.69393 5.6677 -167.985 -5.6677 5.6677 0.32 0.000381638 0.000350701 0.0372226 0.0341246 -1 -1 -1 -1 28 3350 21 6.65987e+06 456408 500653. 1732.36 1.33 0.159215 0.140889 21970 115934 -1 2772 21 1856 2735 170569 41048 4.77703 4.77703 -165.781 -4.77703 0 0 612192. 2118.31 0.03 0.06 0.07 -1 -1 0.03 0.0228982 0.0206184 178 64 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.97 vpr 64.36 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30132 -1 -1 32 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 24.9 MiB 0.59 2681 1309 14999 4622 8322 2055 64.4 MiB 0.09 0.00 6.28756 5.10273 -157.72 -5.10273 5.10273 0.23 0.00068262 0.00062368 0.0291839 0.0267265 -1 -1 -1 -1 32 2682 21 6.65987e+06 405696 554710. 1919.41 1.01 0.131813 0.116038 22834 132086 -1 2351 17 1068 1598 128922 28801 3.94943 3.94943 -145.575 -3.94943 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0160375 0.0145622 167 64 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 1.94 vpr 64.62 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29740 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2150 1138 13788 3708 8180 1900 64.6 MiB 0.08 0.00 5.13095 4.43175 -130.78 -4.43175 4.43175 0.23 0.000330854 0.000303241 0.0226578 0.0208034 -1 -1 -1 -1 26 2684 23 6.65987e+06 469086 477104. 1650.88 0.48 0.0706622 0.0628663 21682 110474 -1 2241 22 1376 2290 147550 36455 3.10551 3.10551 -115.897 -3.10551 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0181755 0.0161496 140 55 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 1.78 vpr 64.46 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29580 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66008 32 32 291 242 1 179 91 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2447 1059 9883 2265 7085 533 64.5 MiB 0.06 0.00 5.12624 4.09841 -110.895 -4.09841 4.09841 0.25 0.000296132 0.000272346 0.0176985 0.0162418 -1 -1 -1 -1 26 2556 27 6.65987e+06 342306 477104. 1650.88 0.46 0.0606008 0.0535975 21682 110474 -1 2017 21 1095 1676 106066 26073 3.51731 3.51731 -113.349 -3.51731 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0152707 0.0135971 124 27 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 2.51 vpr 64.29 MiB -1 -1 0.12 18436 1 0.03 -1 -1 29856 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3074 1204 12757 3068 8413 1276 64.3 MiB 0.08 0.00 6.1774 4.89901 -154.002 -4.89901 4.89901 0.23 0.000414085 0.000380006 0.0237217 0.0217485 -1 -1 -1 -1 28 3067 37 6.65987e+06 545154 500653. 1732.36 1.06 0.158471 0.138717 21970 115934 -1 2549 21 1787 2650 155948 39478 4.09557 4.09557 -145.446 -4.09557 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.023765 0.0213011 176 87 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.10 vpr 64.28 MiB -1 -1 0.12 17668 1 0.02 -1 -1 29856 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65824 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2009 887 11048 2987 7063 998 64.3 MiB 0.06 0.00 4.26232 3.39378 -98.4132 -3.39378 3.39378 0.24 0.000267305 0.000244906 0.020054 0.018467 -1 -1 -1 -1 26 1891 30 6.65987e+06 291594 477104. 1650.88 0.77 0.105782 0.092071 21682 110474 -1 1662 20 1011 1739 107514 26503 2.82891 2.82891 -101.876 -2.82891 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0133012 0.0118709 104 28 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 2.54 vpr 64.61 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30240 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2890 1251 18301 5355 10266 2680 64.6 MiB 0.10 0.00 6.05769 4.76375 -144.29 -4.76375 4.76375 0.25 0.000325031 0.000298013 0.0320046 0.0294245 -1 -1 -1 -1 26 3189 24 6.65987e+06 431052 477104. 1650.88 1.13 0.140561 0.123821 21682 110474 -1 2546 22 1555 2328 159437 38754 4.09251 4.09251 -137.605 -4.09251 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0175959 0.015789 149 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.00 vpr 64.21 MiB -1 -1 0.12 18048 1 0.03 -1 -1 29732 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 32 32 349 284 1 182 102 17 17 289 -1 unnamed_device 24.2 MiB 0.05 2675 1157 12240 3182 8323 735 64.2 MiB 0.08 0.00 4.8754 3.93484 -114.185 -3.93484 3.93484 0.24 0.000330143 0.000300671 0.0222818 0.0204813 -1 -1 -1 -1 26 2757 32 6.65987e+06 481764 477104. 1650.88 0.60 0.0776811 0.0690096 21682 110474 -1 2363 19 1261 2360 164757 38552 3.36871 3.36871 -117.29 -3.36871 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.019165 0.0171186 136 53 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 1.88 vpr 64.40 MiB -1 -1 0.16 17528 1 0.03 -1 -1 30164 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1813 1098 12127 4092 6786 1249 64.4 MiB 0.09 0.00 4.58224 3.99224 -122.075 -3.99224 3.99224 0.25 0.000381717 0.000350442 0.0280412 0.0258922 -1 -1 -1 -1 32 2237 19 6.65987e+06 342306 554710. 1919.41 0.40 0.0682722 0.0610453 22834 132086 -1 2105 20 1119 2098 156985 35010 3.48525 3.48525 -121.639 -3.48525 0 0 701300. 2426.64 0.03 0.07 0.07 -1 -1 0.03 0.0257139 0.0230642 127 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.25 vpr 64.68 MiB -1 -1 0.16 18056 1 0.03 -1 -1 30152 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66232 32 32 353 287 1 198 95 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2414 1201 14783 3737 9111 1935 64.7 MiB 0.09 0.00 5.28395 4.64383 -136.782 -4.64383 4.64383 0.23 0.000330395 0.000300954 0.0254379 0.0232664 -1 -1 -1 -1 28 2543 26 6.65987e+06 393018 500653. 1732.36 0.80 0.120905 0.105969 21970 115934 -1 2251 21 1408 1875 123007 30781 3.10031 3.10031 -118.173 -3.10031 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0168622 0.0151259 142 55 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2721 1179 19868 6240 11195 2433 64.6 MiB 0.21 0.00 4.80995 4.10592 -126.681 -4.10592 4.10592 0.23 0.000537632 0.000496731 0.0705905 0.0653766 -1 -1 -1 -1 26 2816 24 6.65987e+06 507120 477104. 1650.88 0.60 0.128236 0.11589 21682 110474 -1 2357 21 1447 2439 171323 40624 2.93371 2.93371 -116.894 -2.93371 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0178623 0.0160256 149 62 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 3.71 vpr 64.45 MiB -1 -1 0.11 17904 1 0.03 -1 -1 29800 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 25.0 MiB 0.05 1946 873 16108 4349 7937 3822 64.5 MiB 0.07 0.00 4.57124 3.93324 -112.121 -3.93324 3.93324 0.23 0.000306658 0.000280335 0.0248876 0.0228463 -1 -1 -1 -1 30 2274 29 6.65987e+06 456408 526063. 1820.29 2.35 0.120616 0.105943 22546 126617 -1 1515 22 1093 1983 103839 27229 3.38699 3.38699 -106.02 -3.38699 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0177718 0.0157363 127 24 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.23 vpr 63.87 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29584 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 32 32 319 257 1 198 92 17 17 289 -1 unnamed_device 24.5 MiB 0.09 2350 1139 12719 3270 8148 1301 63.9 MiB 0.07 0.00 5.74889 4.74243 -133.951 -4.74243 4.74243 0.24 0.000312147 0.000284437 0.0214525 0.0196459 -1 -1 -1 -1 30 2287 21 6.65987e+06 354984 526063. 1820.29 0.68 0.102014 0.0894369 22546 126617 -1 1970 18 1171 1696 92785 22648 3.49131 3.49131 -121.376 -3.49131 0 0 666494. 2306.21 0.04 0.05 0.12 -1 -1 0.04 0.0187291 0.0169296 137 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 2.62 vpr 64.74 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29800 -1 -1 30 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2919 1229 8073 1790 5652 631 64.7 MiB 0.06 0.00 6.09275 4.90792 -144.963 -4.90792 4.90792 0.24 0.000354844 0.000325213 0.0163957 0.0150592 -1 -1 -1 -1 26 3109 38 6.65987e+06 380340 477104. 1650.88 1.20 0.150978 0.132741 21682 110474 -1 2584 23 1839 2855 189670 45582 4.00631 4.00631 -139.798 -4.00631 0 0 585099. 2024.56 0.02 0.05 0.07 -1 -1 0.02 0.019152 0.0170771 151 62 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.92 vpr 64.23 MiB -1 -1 0.17 18056 1 0.03 -1 -1 30108 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2687 1072 16523 5659 7829 3035 64.2 MiB 0.11 0.00 4.94107 4.09069 -129.92 -4.09069 4.09069 0.24 0.000857988 0.000801055 0.0416845 0.0386047 -1 -1 -1 -1 30 2468 19 6.65987e+06 316950 526063. 1820.29 1.40 0.171759 0.152727 22546 126617 -1 1929 19 1275 2194 126979 30184 3.36805 3.36805 -121.211 -3.36805 0 0 666494. 2306.21 0.03 0.05 0.08 -1 -1 0.03 0.0232353 0.0208535 141 77 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66120 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2440 992 6007 1156 4597 254 64.6 MiB 0.04 0.00 4.88419 3.97947 -135.407 -3.97947 3.97947 0.29 0.000328686 0.000301478 0.0111881 0.0102596 -1 -1 -1 -1 28 2655 20 6.65987e+06 342306 500653. 1732.36 0.40 0.0545205 0.04797 21970 115934 -1 2093 23 1541 2202 159522 39777 3.38797 3.38797 -131.381 -3.38797 0 0 612192. 2118.31 0.03 0.05 0.06 -1 -1 0.03 0.0182671 0.0163156 133 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 1.88 vpr 64.34 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29828 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 32 32 387 293 1 234 98 17 17 289 -1 unnamed_device 25.1 MiB 0.06 2841 1434 16523 4655 9834 2034 64.3 MiB 0.11 0.00 6.09189 5.18108 -152.063 -5.18108 5.18108 0.24 0.000363101 0.000332817 0.0361583 0.0334442 -1 -1 -1 -1 32 3145 19 6.65987e+06 431052 554710. 1919.41 0.38 0.0838214 0.0752932 22834 132086 -1 2602 22 1587 2577 157408 37857 4.25491 4.25491 -142.991 -4.25491 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0194226 0.0174853 174 31 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 3.65 vpr 64.57 MiB -1 -1 0.13 18020 1 0.03 -1 -1 29944 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 25.2 MiB 0.09 2565 908 17952 4964 9148 3840 64.6 MiB 0.09 0.00 5.03706 4.14283 -126.342 -4.14283 4.14283 0.23 0.000329597 0.000301333 0.0285814 0.0262011 -1 -1 -1 -1 30 2351 28 6.65987e+06 481764 526063. 1820.29 2.07 0.16465 0.145021 22546 126617 -1 1739 20 1039 1780 111645 29043 2.61551 2.61551 -104.065 -2.61551 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0164232 0.0147637 141 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.35 vpr 64.36 MiB -1 -1 0.12 17668 1 0.03 -1 -1 30328 -1 -1 33 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 24.9 MiB 0.03 2182 907 13703 3856 8397 1450 64.4 MiB 0.07 0.00 4.13824 3.55007 -108.481 -3.55007 3.55007 0.25 0.000293269 0.000263617 0.024289 0.0224368 -1 -1 -1 -1 32 1765 21 6.65987e+06 418374 554710. 1919.41 0.98 0.118204 0.103343 22834 132086 -1 1534 19 670 1228 76480 18288 2.48817 2.48817 -96.8001 -2.48817 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.013599 0.0121795 111 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 2.80 vpr 64.20 MiB -1 -1 0.15 18824 1 0.03 -1 -1 30124 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65744 32 32 431 332 1 235 95 17 17 289 -1 unnamed_device 24.9 MiB 0.16 2995 1435 16943 5441 8966 2536 64.2 MiB 0.11 0.00 7.19172 6.12709 -179.158 -6.12709 6.12709 0.24 0.000402579 0.000368127 0.0338431 0.0310673 -1 -1 -1 -1 32 2968 21 6.65987e+06 393018 554710. 1919.41 1.11 0.166916 0.146566 22834 132086 -1 2576 21 1778 2583 161656 39107 4.64457 4.64457 -161.765 -4.64457 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0204855 0.0183688 177 65 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 231 199 1 140 91 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1906 763 10291 2431 6883 977 64.2 MiB 0.05 0.00 4.00198 3.24072 -93.0898 -3.24072 3.24072 0.24 0.000252957 0.00023204 0.014133 0.0129556 -1 -1 -1 -1 26 1813 19 6.65987e+06 342306 477104. 1650.88 0.90 0.100565 0.0873611 21682 110474 -1 1587 17 924 1601 94219 24609 2.67551 2.67551 -95.133 -2.67551 0 0 585099. 2024.56 0.02 0.03 0.07 -1 -1 0.02 0.0144873 0.0129215 103 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.94 vpr 64.62 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30252 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2540 1184 12792 3130 8784 878 64.6 MiB 0.08 0.00 6.17103 5.12357 -128.342 -5.12357 5.12357 0.24 0.000405648 0.00035247 0.0251103 0.0232583 -1 -1 -1 -1 26 2736 22 6.65987e+06 507120 477104. 1650.88 1.38 0.129295 0.114292 21682 110474 -1 2329 19 1224 2599 181219 41024 3.77199 3.77199 -121.701 -3.77199 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0175625 0.0157507 147 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.20 vpr 64.25 MiB -1 -1 0.23 17912 1 0.02 -1 -1 29776 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 24.1 MiB 0.04 2164 862 9111 2261 6252 598 64.2 MiB 0.05 0.00 4.2295 3.4211 -103.943 -3.4211 3.4211 0.25 0.000272144 0.000249418 0.0165738 0.015236 -1 -1 -1 -1 26 1976 21 6.65987e+06 291594 477104. 1650.88 0.72 0.0817198 0.0712883 21682 110474 -1 1647 22 1171 2052 118500 29809 2.99817 2.99817 -107.951 -2.99817 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0148357 0.0132715 107 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.37 vpr 64.37 MiB -1 -1 0.15 17912 1 0.04 -1 -1 29824 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2117 919 17732 5394 9708 2630 64.4 MiB 0.09 0.00 5.05435 4.00072 -108.105 -4.00072 4.00072 0.25 0.000319002 0.000294923 0.0275487 0.0252902 -1 -1 -1 -1 28 1932 24 6.65987e+06 481764 500653. 1732.36 0.86 0.115273 0.101221 21970 115934 -1 1752 19 902 1787 109885 27332 2.74851 2.74851 -98.5026 -2.74851 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0132408 0.0118756 110 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 2.40 vpr 64.51 MiB -1 -1 0.18 18056 1 0.03 -1 -1 29996 -1 -1 30 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 29 32 355 287 1 198 91 17 17 289 -1 unnamed_device 25.2 MiB 0.09 2795 1157 13759 4262 7817 1680 64.5 MiB 0.08 0.00 5.46461 4.50718 -131.152 -4.50718 4.50718 0.31 0.000330091 0.000302586 0.0257511 0.0236546 -1 -1 -1 -1 26 2957 22 6.65987e+06 380340 477104. 1650.88 0.51 0.0783395 0.0700172 21682 110474 -1 2345 21 1460 2184 143176 34536 3.37397 3.37397 -119.24 -3.37397 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0287388 0.0256969 146 62 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66128 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2440 995 11573 3131 7196 1246 64.6 MiB 0.07 0.00 5.53355 4.52906 -132.157 -4.52906 4.52906 0.25 0.000337555 0.000309443 0.0200569 0.0183746 -1 -1 -1 -1 32 2149 21 6.65987e+06 431052 554710. 1919.41 0.34 0.0639729 0.0567577 22834 132086 -1 1930 21 1161 1924 112326 28305 3.56431 3.56431 -123.17 -3.56431 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0192602 0.017328 136 51 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.28 vpr 64.37 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29596 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1928 842 5756 1110 4290 356 64.4 MiB 0.04 0.00 5.01063 4.547 -125.133 -4.547 4.547 0.24 0.000281039 0.000257092 0.0108104 0.00993427 -1 -1 -1 -1 26 2746 42 6.65987e+06 278916 477104. 1650.88 0.81 0.0695017 0.0610828 21682 110474 -1 2009 23 1128 1545 124492 32025 3.20671 3.20671 -119.094 -3.20671 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0149363 0.0132929 107 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.31 vpr 64.45 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29780 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 31 32 319 272 1 169 86 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2087 999 8402 2135 5628 639 64.4 MiB 0.05 0.00 4.70844 3.76401 -122.041 -3.76401 3.76401 0.24 0.000297899 0.000272927 0.0150693 0.0138092 -1 -1 -1 -1 30 2009 19 6.65987e+06 291594 526063. 1820.29 0.77 0.139907 0.122491 22546 126617 -1 1802 22 1049 1597 92062 22220 3.08351 3.08351 -115.52 -3.08351 0 0 666494. 2306.21 0.05 0.05 0.11 -1 -1 0.05 0.023418 0.0209173 116 64 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.79 vpr 64.51 MiB -1 -1 0.14 18440 1 0.03 -1 -1 30120 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2322 911 10223 2206 7289 728 64.5 MiB 0.06 0.00 4.14418 3.34001 -95.1163 -3.34001 3.34001 0.24 0.000313524 0.000285877 0.0164285 0.0150486 -1 -1 -1 -1 26 2414 22 6.65987e+06 456408 477104. 1650.88 1.37 0.107607 0.0946655 21682 110474 -1 1927 22 1181 2235 140233 36386 2.57639 2.57639 -96.5212 -2.57639 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0200354 0.0178693 128 57 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.64 vpr 64.39 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30184 -1 -1 39 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1932 968 16515 5028 9029 2458 64.4 MiB 0.10 0.00 4.80358 3.82106 -98.9222 -3.82106 3.82106 0.27 0.000295246 0.000271701 0.0370857 0.0343414 -1 -1 -1 -1 30 1920 22 6.65987e+06 494442 526063. 1820.29 1.00 0.146017 0.128722 22546 126617 -1 1687 18 746 1556 78646 19064 3.06345 3.06345 -92.4917 -3.06345 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0156517 0.0140541 122 27 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65604 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2267 1081 11748 2737 7741 1270 64.1 MiB 0.12 0.00 4.27587 3.75301 -127.23 -3.75301 3.75301 0.24 0.000922484 0.000857673 0.046778 0.043576 -1 -1 -1 -1 32 2169 20 6.65987e+06 329628 554710. 1919.41 0.53 0.113914 0.10228 22834 132086 -1 1912 17 1021 1536 95655 22988 3.18891 3.18891 -117.522 -3.18891 0 0 701300. 2426.64 0.04 0.06 0.11 -1 -1 0.04 0.0257491 0.022733 127 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.59 vpr 64.44 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29548 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 25.0 MiB 0.04 2060 1066 14716 3823 8466 2427 64.4 MiB 0.07 0.00 4.86349 4.26143 -121.889 -4.26143 4.26143 0.27 0.000296603 0.000269714 0.0210521 0.0191673 -1 -1 -1 -1 32 2163 21 6.65987e+06 469086 554710. 1919.41 1.11 0.142451 0.124381 22834 132086 -1 1952 18 1051 1980 108284 26406 3.51125 3.51125 -111.09 -3.51125 0 0 701300. 2426.64 0.03 0.04 0.10 -1 -1 0.03 0.0165159 0.0149261 134 4 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 1.98 vpr 64.64 MiB -1 -1 0.12 18048 1 0.03 -1 -1 30360 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66192 32 32 350 275 1 209 93 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2681 1168 10383 2802 6577 1004 64.6 MiB 0.07 0.00 5.68615 4.86192 -151.547 -4.86192 4.86192 0.24 0.000334875 0.000306795 0.0187135 0.0171881 -1 -1 -1 -1 32 2556 25 6.65987e+06 367662 554710. 1919.41 0.49 0.0877671 0.0777807 22834 132086 -1 2143 20 1336 2094 119998 29832 3.72991 3.72991 -134.478 -3.72991 0 0 701300. 2426.64 0.04 0.06 0.08 -1 -1 0.04 0.0242861 0.021965 151 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 4.53 vpr 64.66 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29792 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2633 927 18196 5275 8727 4194 64.7 MiB 0.08 0.00 5.51755 4.47917 -136.038 -4.47917 4.47917 0.23 0.00035799 0.000327422 0.0311637 0.0285323 -1 -1 -1 -1 36 2460 39 6.65987e+06 469086 612192. 2118.31 3.09 0.183338 0.161522 23410 145293 -1 1908 19 1434 2459 149777 39483 3.72051 3.72051 -129.983 -3.72051 0 0 782063. 2706.10 0.03 0.04 0.09 -1 -1 0.03 0.0173432 0.0156109 143 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 3.52 vpr 64.05 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30240 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2914 1226 13516 3426 8918 1172 64.1 MiB 0.11 0.00 5.66375 4.30832 -138.449 -4.30832 4.30832 0.31 0.000364026 0.000327868 0.0352371 0.0324508 -1 -1 -1 -1 26 3133 37 6.65987e+06 545154 477104. 1650.88 2.01 0.204454 0.180913 21682 110474 -1 2585 21 1659 3001 194586 46671 3.27771 3.27771 -128.625 -3.27771 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0184663 0.0164533 147 65 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66176 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2028 1003 9395 2078 6561 756 64.6 MiB 0.06 0.00 5.34001 4.72954 -137.554 -4.72954 4.72954 0.23 0.000351356 0.000321724 0.0184561 0.0169463 -1 -1 -1 -1 28 2499 27 6.65987e+06 342306 500653. 1732.36 0.47 0.0711341 0.0630113 21970 115934 -1 2043 19 1375 2121 129278 33516 3.72637 3.72637 -132.273 -3.72637 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0175255 0.0158171 147 63 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 3.56 vpr 64.59 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29852 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2562 1172 8614 1885 5948 781 64.6 MiB 0.06 0.00 6.11242 5.075 -148.312 -5.075 5.075 0.24 0.000324053 0.000296578 0.0159447 0.0146839 -1 -1 -1 -1 28 3045 34 6.65987e+06 380340 500653. 1732.36 2.06 0.139928 0.123519 21970 115934 -1 2409 21 1636 2519 180150 43978 3.77211 3.77211 -133.398 -3.77211 0 0 612192. 2118.31 0.03 0.07 0.07 -1 -1 0.03 0.0233923 0.0209471 145 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 2.64 vpr 64.71 MiB -1 -1 0.16 17524 1 0.04 -1 -1 29784 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 31 32 340 275 1 195 98 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2655 1234 13373 3486 8666 1221 64.7 MiB 0.08 0.00 6.2565 5.20087 -146.632 -5.20087 5.20087 0.24 0.000337977 0.000309774 0.0232074 0.0213238 -1 -1 -1 -1 28 2603 23 6.65987e+06 443730 500653. 1732.36 0.95 0.148618 0.130153 21970 115934 -1 2276 21 1462 2381 143787 35641 4.28397 4.28397 -142.339 -4.28397 0 0 612192. 2118.31 0.04 0.07 0.11 -1 -1 0.04 0.0301272 0.0271323 152 47 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.11 vpr 64.64 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30124 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66188 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 24.9 MiB 0.37 2368 1078 19356 5734 11269 2353 64.6 MiB 0.11 0.00 5.15601 4.43481 -132.977 -4.43481 4.43481 0.24 0.000356646 0.000327786 0.0400155 0.0371255 -1 -1 -1 -1 32 2034 21 6.65987e+06 481764 554710. 1919.41 0.34 0.0872187 0.0784088 22834 132086 -1 1867 19 1042 1815 109969 26079 3.09757 3.09757 -117.861 -3.09757 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0270637 0.0241799 144 83 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 1.79 vpr 64.22 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29780 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65760 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2717 1028 9989 2368 7036 585 64.2 MiB 0.08 0.00 5.82395 4.80846 -135.83 -4.80846 4.80846 0.25 0.000785676 0.000756889 0.0268928 0.0250003 -1 -1 -1 -1 32 2279 22 6.65987e+06 316950 554710. 1919.41 0.40 0.0816934 0.072869 22834 132086 -1 1969 18 1045 1838 103539 25809 3.51511 3.51511 -124.567 -3.51511 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0162994 0.0147361 141 57 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65756 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 24.1 MiB 0.05 1776 913 13583 3827 8166 1590 64.2 MiB 0.06 0.00 4.36335 3.77952 -113.791 -3.77952 3.77952 0.23 0.000258733 0.000237246 0.0221535 0.0203246 -1 -1 -1 -1 32 1628 18 6.65987e+06 240882 554710. 1919.41 0.86 0.108382 0.0947406 22834 132086 -1 1492 15 568 862 53023 12847 2.73465 2.73465 -99.7426 -2.73465 0 0 701300. 2426.64 0.03 0.02 0.12 -1 -1 0.03 0.0110657 0.0100029 99 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 2.64 vpr 64.61 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29768 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2442 1018 18339 5915 9603 2821 64.6 MiB 0.09 0.00 5.53955 4.46392 -134.604 -4.46392 4.46392 0.24 0.000350581 0.000320376 0.030238 0.0276861 -1 -1 -1 -1 28 2559 33 6.65987e+06 443730 500653. 1732.36 1.23 0.157921 0.139255 21970 115934 -1 2034 22 1390 2379 155320 38127 3.72251 3.72251 -131.726 -3.72251 0 0 612192. 2118.31 0.03 0.06 0.06 -1 -1 0.03 0.0224972 0.0200975 135 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 1.88 vpr 64.36 MiB -1 -1 0.13 18044 1 0.03 -1 -1 29776 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2649 1042 7415 1478 5399 538 64.4 MiB 0.05 0.00 5.84281 4.69477 -144.735 -4.69477 4.69477 0.25 0.000363804 0.000333298 0.0164987 0.0151272 -1 -1 -1 -1 32 2467 22 6.65987e+06 316950 554710. 1919.41 0.43 0.0723381 0.0642314 22834 132086 -1 2120 20 1640 2746 168107 41989 3.74157 3.74157 -135.95 -3.74157 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0231033 0.0206951 155 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.15 vpr 64.37 MiB -1 -1 0.14 17660 1 0.03 -1 -1 29800 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2060 1041 9791 2284 6736 771 64.4 MiB 0.05 0.00 4.9641 4.13987 -114.14 -4.13987 4.13987 0.23 0.000285581 0.000261993 0.0167929 0.0154416 -1 -1 -1 -1 22 2510 30 6.65987e+06 316950 420624. 1455.45 0.84 0.0995754 0.0866549 20818 92861 -1 2270 19 1086 1462 115592 27496 3.61557 3.61557 -116.563 -3.61557 0 0 500653. 1732.36 0.02 0.04 0.05 -1 -1 0.02 0.0135916 0.0121488 117 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 1.77 vpr 64.24 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29940 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 31 32 245 205 1 150 86 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2068 883 14639 5191 7304 2144 64.2 MiB 0.07 0.00 4.81301 3.84841 -109.743 -3.84841 3.84841 0.25 0.000261358 0.000239166 0.0228225 0.0209759 -1 -1 -1 -1 32 1873 20 6.65987e+06 291594 554710. 1919.41 0.33 0.0586236 0.0521393 22834 132086 -1 1716 18 1042 1695 113744 27403 2.66951 2.66951 -100.595 -2.66951 0 0 701300. 2426.64 0.03 0.04 0.09 -1 -1 0.03 0.0131841 0.0117093 110 4 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 24.9 MiB 0.10 2455 1202 17726 5863 9448 2415 64.7 MiB 0.10 0.00 6.19085 4.98326 -147.838 -4.98326 4.98326 0.23 0.000337012 0.00030237 0.0286512 0.0261769 -1 -1 -1 -1 28 2992 31 6.65987e+06 469086 500653. 1732.36 1.28 0.150303 0.13201 21970 115934 -1 2209 22 1417 2227 163353 43256 4.07751 4.07751 -138.323 -4.07751 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0211012 0.0188692 157 56 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.12 vpr 64.40 MiB -1 -1 0.21 18056 1 0.04 -1 -1 29828 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 24.7 MiB 0.04 2789 1282 17058 4558 10111 2389 64.4 MiB 0.10 0.00 6.22775 5.25635 -138.9 -5.25635 5.25635 0.24 0.000847755 0.000792737 0.0270822 0.0248474 -1 -1 -1 -1 30 2744 22 6.65987e+06 545154 526063. 1820.29 0.51 0.0787829 0.0704927 22546 126617 -1 2279 19 1165 2296 144567 32446 4.20857 4.20857 -132.092 -4.20857 0 0 666494. 2306.21 0.04 0.09 0.08 -1 -1 0.04 0.0377591 0.0340845 162 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 2.48 vpr 64.46 MiB -1 -1 0.12 17908 1 0.03 -1 -1 29804 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 30 32 316 264 1 162 98 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2263 907 15623 4094 8873 2656 64.5 MiB 0.07 0.00 4.35844 3.46421 -101.49 -3.46421 3.46421 0.23 0.000302285 0.000277318 0.0237892 0.0218542 -1 -1 -1 -1 30 1887 20 6.65987e+06 456408 526063. 1820.29 0.93 0.125269 0.109434 22546 126617 -1 1617 20 923 1599 76990 19613 2.69151 2.69151 -96.3226 -2.69151 0 0 666494. 2306.21 0.04 0.07 0.08 -1 -1 0.04 0.035453 0.0317282 124 52 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.19 vpr 64.24 MiB -1 -1 0.14 17672 1 0.02 -1 -1 30144 -1 -1 23 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 27 32 255 219 1 132 82 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1707 762 11296 3316 6423 1557 64.2 MiB 0.05 0.00 4.35664 3.48247 -97.7908 -3.48247 3.48247 0.23 0.000254069 0.00023285 0.0176088 0.0161447 -1 -1 -1 -1 32 1498 19 6.65987e+06 291594 554710. 1919.41 0.88 0.0982668 0.0852425 22834 132086 -1 1390 21 750 1239 79737 19491 2.74977 2.74977 -93.2365 -2.74977 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0131444 0.0117322 100 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 3.10 vpr 64.94 MiB -1 -1 0.16 17672 1 0.03 -1 -1 30148 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66496 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 25.6 MiB 0.06 3118 1504 18998 5785 11135 2078 64.9 MiB 0.16 0.00 5.30144 4.15341 -134.659 -4.15341 4.15341 0.24 0.000723216 0.00066104 0.048028 0.0441656 -1 -1 -1 -1 32 3347 20 6.65987e+06 431052 554710. 1919.41 1.49 0.187082 0.165648 22834 132086 -1 2852 23 1753 2861 212134 47689 3.41911 3.41911 -128.837 -3.41911 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0239451 0.0214081 176 65 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65660 32 32 331 280 1 175 87 17 17 289 -1 unnamed_device 24.5 MiB 0.34 2093 1056 11223 2777 6565 1881 64.1 MiB 0.07 0.00 5.5891 4.44586 -136.991 -4.44586 4.44586 0.23 0.000310743 0.00028465 0.0245441 0.0226654 -1 -1 -1 -1 30 2098 21 6.65987e+06 291594 526063. 1820.29 0.83 0.115069 0.101493 22546 126617 -1 1713 17 744 1061 64700 15352 3.42717 3.42717 -125.557 -3.42717 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0188638 0.0169499 129 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 1.99 vpr 64.05 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30332 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2458 1023 12396 3002 8710 684 64.1 MiB 0.06 0.00 5.92474 4.91628 -125.981 -4.91628 4.91628 0.31 0.00031312 0.000285308 0.0186718 0.0170098 -1 -1 -1 -1 26 2519 25 6.65987e+06 456408 477104. 1650.88 0.49 0.0681747 0.0605424 21682 110474 -1 2143 19 1162 2005 137788 34909 3.45605 3.45605 -115.538 -3.45605 0 0 585099. 2024.56 0.04 0.04 0.08 -1 -1 0.04 0.0156747 0.0141323 133 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 2.49 vpr 64.38 MiB -1 -1 0.18 18052 1 0.03 -1 -1 29868 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 31 32 373 294 1 196 102 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2316 1116 9622 2124 6827 671 64.4 MiB 0.07 0.00 5.28538 4.66257 -122.009 -4.66257 4.66257 0.24 0.000500582 0.000470974 0.022367 0.0207019 -1 -1 -1 -1 32 2164 22 6.65987e+06 494442 554710. 1919.41 0.96 0.150679 0.132762 22834 132086 -1 1941 21 1024 1664 98113 24600 3.71045 3.71045 -118.186 -3.71045 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0217 0.0195245 151 50 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.43 vpr 64.50 MiB -1 -1 0.19 18056 1 0.03 -1 -1 30260 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2399 1001 15848 4524 8647 2677 64.5 MiB 0.10 0.00 4.35464 3.6178 -102.686 -3.6178 3.6178 0.25 0.000340058 0.000313523 0.032293 0.0300242 -1 -1 -1 -1 32 2093 22 6.65987e+06 456408 554710. 1919.41 0.91 0.115634 0.10181 22834 132086 -1 1735 20 927 1616 95276 23308 2.75671 2.75671 -93.3009 -2.75671 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152838 0.0137139 130 51 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 2.63 vpr 64.65 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30252 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 32 32 350 275 1 215 95 17 17 289 -1 unnamed_device 25.3 MiB 0.13 2711 1336 11327 3094 7340 893 64.7 MiB 0.08 0.00 6.10595 5.14435 -160.142 -5.14435 5.14435 0.23 0.00035727 0.000327964 0.0199369 0.0183003 -1 -1 -1 -1 32 2855 24 6.65987e+06 393018 554710. 1919.41 1.00 0.118695 0.104006 22834 132086 -1 2484 19 1479 2310 144508 33634 3.96111 3.96111 -144.603 -3.96111 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0177237 0.0159978 155 34 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65688 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1576 639 12464 3221 8431 812 64.1 MiB 0.09 0.00 4.48041 4.01678 -108.148 -4.01678 4.01678 0.28 0.000480442 0.000438543 0.0373201 0.0341971 -1 -1 -1 -1 30 1486 20 6.65987e+06 240882 526063. 1820.29 0.93 0.126396 0.111447 22546 126617 -1 1234 20 690 1018 70885 16894 2.71377 2.71377 -93.534 -2.71377 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0135202 0.0121234 93 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.28 vpr 63.98 MiB -1 -1 0.13 17908 1 0.03 -1 -1 29936 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65520 32 32 310 266 1 175 90 17 17 289 -1 unnamed_device 24.1 MiB 0.04 2095 940 8331 1938 5650 743 64.0 MiB 0.05 0.00 4.98039 4.1175 -122.325 -4.1175 4.1175 0.25 0.000294899 0.000270139 0.0142154 0.0130403 -1 -1 -1 -1 26 2117 18 6.65987e+06 329628 477104. 1650.88 0.95 0.114865 0.100577 21682 110474 -1 1793 22 1060 1496 105030 24470 3.22317 3.22317 -116.181 -3.22317 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0159831 0.014244 123 58 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.83 vpr 64.54 MiB -1 -1 0.14 18440 1 0.03 -1 -1 29876 -1 -1 43 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66088 31 32 326 261 1 177 106 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2343 916 18356 4978 9795 3583 64.5 MiB 0.09 0.00 5.52155 4.37352 -119.432 -4.37352 4.37352 0.25 0.000354148 0.000290662 0.0273844 0.0250176 -1 -1 -1 -1 30 2290 33 6.65987e+06 545154 526063. 1820.29 1.40 0.157058 0.137275 22546 126617 -1 1831 24 1339 2530 162695 40201 3.55325 3.55325 -112.175 -3.55325 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0183438 0.0163401 138 33 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 1.69 vpr 64.36 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29796 -1 -1 26 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 29 32 262 224 1 168 87 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1937 962 8151 2045 5043 1063 64.4 MiB 0.05 0.00 4.73201 3.89047 -108.453 -3.89047 3.89047 0.24 0.000334714 0.000292814 0.0167961 0.0155764 -1 -1 -1 -1 26 2222 19 6.65987e+06 329628 477104. 1650.88 0.37 0.0576277 0.0510664 21682 110474 -1 1935 15 790 1052 70400 17366 3.46957 3.46957 -109.369 -3.46957 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0117647 0.0106224 116 31 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.30 vpr 64.32 MiB -1 -1 0.12 17668 1 0.02 -1 -1 30196 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1781 952 11063 2996 6474 1593 64.3 MiB 0.06 0.00 4.35429 3.84883 -121.23 -3.84883 3.84883 0.23 0.000287209 0.000263087 0.0212423 0.0195714 -1 -1 -1 -1 32 2005 20 6.65987e+06 240882 554710. 1919.41 0.95 0.109571 0.0957045 22834 132086 -1 1812 17 1077 1863 113788 27875 2.76365 2.76365 -109.874 -2.76365 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0124444 0.0111877 111 34 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65780 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 24.2 MiB 0.05 1957 962 7888 1862 5402 624 64.2 MiB 0.04 0.00 4.37039 3.7831 -115.738 -3.7831 3.7831 0.24 0.000271273 0.000248449 0.0127145 0.0116877 -1 -1 -1 -1 32 1927 16 6.65987e+06 316950 554710. 1919.41 0.31 0.0483232 0.0426507 22834 132086 -1 1730 18 773 1167 76810 18412 2.99882 2.99882 -104.533 -2.99882 0 0 701300. 2426.64 0.03 0.03 0.12 -1 -1 0.03 0.0145656 0.0130899 113 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.22 vpr 64.57 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29800 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2312 1008 10206 2347 7231 628 64.6 MiB 0.06 0.00 4.25818 3.54324 -107.169 -3.54324 3.54324 0.23 0.000332085 0.000303616 0.0162243 0.0148741 -1 -1 -1 -1 26 2349 20 6.65987e+06 469086 477104. 1650.88 0.85 0.0996743 0.0869767 21682 110474 -1 2018 17 1073 1917 117571 28694 3.00811 3.00811 -108.65 -3.00811 0 0 585099. 2024.56 0.03 0.04 0.06 -1 -1 0.03 0.0161924 0.0146389 131 57 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.55 vpr 64.71 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30128 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 25.2 MiB 0.31 2511 865 8763 1886 5820 1057 64.7 MiB 0.04 0.00 4.68116 3.95996 -121.43 -3.95996 3.95996 0.23 0.000354374 0.00032327 0.0160355 0.0147464 -1 -1 -1 -1 30 2002 20 6.65987e+06 456408 526063. 1820.29 0.94 0.117387 0.102667 22546 126617 -1 1550 23 1220 1942 99122 25765 3.04517 3.04517 -111.679 -3.04517 0 0 666494. 2306.21 0.03 0.05 0.08 -1 -1 0.03 0.0217423 0.0193783 145 91 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.16 vpr 64.38 MiB -1 -1 0.13 17528 1 0.03 -1 -1 30128 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1814 855 8685 1965 6279 441 64.4 MiB 0.05 0.00 3.73364 3.26564 -102.346 -3.26564 3.26564 0.24 0.000288455 0.000264091 0.0153522 0.0140632 -1 -1 -1 -1 30 1748 23 6.65987e+06 253560 526063. 1820.29 0.85 0.110401 0.0963068 22546 126617 -1 1498 21 732 1205 70856 17065 2.63031 2.63031 -100.894 -2.63031 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.017499 0.0156765 111 57 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.55 vpr 64.08 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29772 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 32 32 290 244 1 177 89 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2414 1034 14345 4099 8382 1864 64.1 MiB 0.08 0.00 4.99075 4.16652 -128.649 -4.16652 4.16652 0.23 0.000836935 0.000781281 0.0238684 0.0218989 -1 -1 -1 -1 26 2468 26 6.65987e+06 316950 477104. 1650.88 1.23 0.120498 0.105531 21682 110474 -1 2134 24 1416 2156 157699 36703 3.04751 3.04751 -115.392 -3.04751 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0174596 0.0154964 123 34 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65960 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2020 1018 6757 1480 4594 683 64.4 MiB 0.04 0.00 4.63015 4.16652 -114.233 -4.16652 4.16652 0.24 0.000324166 0.00029741 0.0121531 0.0112268 -1 -1 -1 -1 26 2263 17 6.65987e+06 456408 477104. 1650.88 0.81 0.10672 0.0933432 21682 110474 -1 1930 17 916 1609 100571 24369 2.92431 2.92431 -101.278 -2.92431 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0152708 0.0135685 129 55 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 1.83 vpr 64.79 MiB -1 -1 0.17 18044 1 0.03 -1 -1 29804 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 32 32 393 312 1 213 93 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2445 1182 15843 4177 9740 1926 64.8 MiB 0.10 0.00 6.02849 5.60583 -175.338 -5.60583 5.60583 0.24 0.000364198 0.000333706 0.0327777 0.0301651 -1 -1 -1 -1 32 2463 22 6.65987e+06 367662 554710. 1919.41 0.36 0.0842253 0.075097 22834 132086 -1 2221 17 1304 1896 104576 26642 4.22277 4.22277 -152.701 -4.22277 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0167933 0.015254 158 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.23 vpr 63.93 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29940 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65468 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 24.1 MiB 0.04 1660 797 8502 1949 6085 468 63.9 MiB 0.04 0.00 3.86484 3.31781 -96.9676 -3.31781 3.31781 0.24 0.000251262 0.000230584 0.0130921 0.0120166 -1 -1 -1 -1 32 1566 18 6.65987e+06 266238 554710. 1919.41 0.87 0.0866868 0.0751474 22834 132086 -1 1391 19 657 1075 65111 16588 2.50751 2.50751 -91.4965 -2.50751 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0126917 0.0113845 100 4 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 1.89 vpr 64.77 MiB -1 -1 0.18 18052 1 0.03 -1 -1 29736 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2451 1117 18431 5270 10930 2231 64.8 MiB 0.10 0.00 5.26444 4.25378 -140.231 -4.25378 4.25378 0.23 0.000373417 0.000339939 0.0316981 0.0289474 -1 -1 -1 -1 32 2341 20 6.65987e+06 469086 554710. 1919.41 0.35 0.080619 0.0716735 22834 132086 -1 2008 21 1252 1842 124809 28919 3.67551 3.67551 -132.399 -3.67551 0 0 701300. 2426.64 0.05 0.10 0.07 -1 -1 0.05 0.0452931 0.0406668 146 90 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.82 vpr 64.54 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29804 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66092 32 32 376 318 1 156 82 17 17 289 -1 unnamed_device 24.5 MiB 0.09 1828 704 11118 4283 5586 1249 64.5 MiB 0.06 0.00 4.2335 3.6453 -123.384 -3.6453 3.6453 0.24 0.000342878 0.000313621 0.023058 0.0211148 -1 -1 -1 -1 28 2422 44 6.65987e+06 228204 500653. 1732.36 1.43 0.142219 0.124509 21970 115934 -1 1780 19 1300 1811 145425 37952 3.84337 3.84337 -134.566 -3.84337 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0162809 0.0146439 117 96 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 396 299 1 236 97 17 17 289 -1 unnamed_device 25.2 MiB 0.09 3069 1481 14971 3777 9344 1850 64.8 MiB 0.10 0.00 7.38831 6.08328 -185.229 -6.08328 6.08328 0.24 0.000411097 0.000378951 0.029417 0.0270377 -1 -1 -1 -1 28 3362 36 6.65987e+06 418374 500653. 1732.36 1.91 0.197809 0.176182 21970 115934 -1 2828 20 1964 2892 207521 47864 4.90737 4.90737 -169.574 -4.90737 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0197778 0.0179217 178 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.17 vpr 64.17 MiB -1 -1 0.14 17660 1 0.02 -1 -1 29808 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65708 30 32 224 207 1 138 85 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1779 770 11245 2856 7531 858 64.2 MiB 0.05 0.00 3.68981 3.20901 -98.3536 -3.20901 3.20901 0.25 0.000246513 0.000216211 0.0159507 0.0145994 -1 -1 -1 -1 28 1564 19 6.65987e+06 291594 500653. 1732.36 0.87 0.100704 0.088167 21970 115934 -1 1350 17 651 829 50023 12838 2.20351 2.20351 -87.8269 -2.20351 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0142654 0.0125989 93 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.33 vpr 64.30 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30056 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 24.9 MiB 0.07 1551 682 8831 2129 6271 431 64.3 MiB 0.04 0.00 4.40209 3.8416 -111.334 -3.8416 3.8416 0.23 0.000277254 0.000253555 0.0158328 0.0145297 -1 -1 -1 -1 30 1565 17 6.65987e+06 240882 526063. 1820.29 1.00 0.125437 0.109434 22546 126617 -1 1321 19 741 1248 76607 18509 2.86471 2.86471 -106.925 -2.86471 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0139883 0.0125804 95 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 1.67 vpr 64.40 MiB -1 -1 0.11 17672 1 0.04 -1 -1 29780 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 296 247 1 157 87 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2143 845 9303 1922 7070 311 64.4 MiB 0.05 0.00 4.04404 3.39881 -108.793 -3.39881 3.39881 0.23 0.000291844 0.000265742 0.0156435 0.0143167 -1 -1 -1 -1 30 2055 22 6.65987e+06 291594 526063. 1820.29 0.36 0.0577119 0.0509962 22546 126617 -1 1649 20 1059 1884 106086 26424 2.57731 2.57731 -102.381 -2.57731 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0142499 0.0127288 119 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 1.66 vpr 63.88 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29940 -1 -1 31 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1494 614 13153 4634 5792 2727 63.9 MiB 0.05 0.00 3.79264 3.36581 -78.5128 -3.36581 3.36581 0.24 0.000221928 0.000202489 0.0164571 0.0150544 -1 -1 -1 -1 32 1365 25 6.65987e+06 393018 554710. 1919.41 0.32 0.0489517 0.0432483 22834 132086 -1 1113 18 614 985 48919 13492 2.53525 2.53525 -71.42 -2.53525 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0126873 0.0114295 93 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 1.91 vpr 64.62 MiB -1 -1 0.14 18056 1 0.04 -1 -1 29764 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66176 32 32 376 307 1 185 88 17 17 289 -1 unnamed_device 24.7 MiB 0.06 2264 1147 14323 4224 8035 2064 64.6 MiB 0.10 0.00 5.10524 4.17275 -131.194 -4.17275 4.17275 0.25 0.000342368 0.000312581 0.0307727 0.0283674 -1 -1 -1 -1 32 2473 25 6.65987e+06 304272 554710. 1919.41 0.42 0.0914247 0.0815378 22834 132086 -1 2202 25 1395 2545 160708 39277 3.38805 3.38805 -119.812 -3.38805 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0241588 0.0215803 137 72 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 1.77 vpr 64.71 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29792 -1 -1 42 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2647 860 12702 3275 8213 1214 64.7 MiB 0.08 0.00 4.50335 3.91658 -121.607 -3.91658 3.91658 0.23 0.000366347 0.000329594 0.0216129 0.0197719 -1 -1 -1 -1 32 2045 24 6.65987e+06 532476 554710. 1919.41 0.38 0.0799359 0.0709708 22834 132086 -1 1761 21 1382 2184 119657 31714 2.82571 2.82571 -107.817 -2.82571 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0226136 0.02042 148 90 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_001.v common 4.08 vpr 65.26 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30128 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66828 32 32 354 285 1 191 80 17 17 289 -1 unnamed_device 25.6 MiB 0.85 2453 972 10228 4188 5749 291 65.3 MiB 0.06 0.00 6.53897 5.5107 -161.059 -5.5107 5.5107 0.25 0.000360483 0.000330651 0.0301468 0.0280027 -1 -1 -1 -1 48 2385 23 6.95648e+06 231611 865456. 2994.66 1.81 0.152519 0.134344 28354 207349 -1 1961 26 1704 2847 242432 77762 4.53791 4.53791 -149.014 -4.53791 0 0 1.05005e+06 3633.38 0.04 0.08 0.11 -1 -1 0.04 0.0207781 0.0185925 81 50 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 6.05 vpr 64.70 MiB -1 -1 0.13 18444 1 0.03 -1 -1 30380 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 30 32 363 293 1 187 80 17 17 289 -1 unnamed_device 25.5 MiB 1.26 2699 985 12980 3943 7957 1080 64.7 MiB 0.06 0.00 5.32638 4.21658 -134.56 -4.21658 4.21658 0.24 0.000338369 0.000310011 0.0273553 0.0251228 -1 -1 -1 -1 36 2667 32 6.95648e+06 260562 648988. 2245.63 3.39 0.180648 0.159451 26050 158493 -1 2213 23 2112 3019 267785 55858 4.35602 4.35602 -151.278 -4.35602 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0188925 0.0169542 79 63 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_003.v common 3.46 vpr 64.77 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29740 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 32 32 299 247 1 182 82 17 17 289 -1 unnamed_device 25.2 MiB 0.60 2358 1032 12186 3430 7248 1508 64.8 MiB 0.06 0.00 4.71675 3.78245 -119.015 -3.78245 3.78245 0.24 0.000295122 0.000269011 0.022121 0.0202745 -1 -1 -1 -1 40 2414 23 6.95648e+06 260562 706193. 2443.58 1.50 0.121574 0.106131 26914 176310 -1 2051 18 1192 1596 127749 28397 3.76412 3.76412 -125.019 -3.76412 0 0 926341. 3205.33 0.03 0.04 0.09 -1 -1 0.03 0.0170379 0.0152769 74 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_004.v common 3.41 vpr 64.20 MiB -1 -1 0.12 18048 1 0.04 -1 -1 29756 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 29 32 308 248 1 162 84 17 17 289 -1 unnamed_device 25.2 MiB 0.18 2112 720 13077 5176 5901 2000 64.2 MiB 0.06 0.00 4.84222 3.96328 -113.617 -3.96328 3.96328 0.25 0.000302052 0.000274458 0.0235956 0.0215408 -1 -1 -1 -1 40 2085 22 6.95648e+06 332941 706193. 2443.58 1.80 0.148459 0.129635 26914 176310 -1 1621 23 1506 2612 185027 44223 3.91416 3.91416 -121.795 -3.91416 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0165964 0.014824 73 31 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 2.47 vpr 64.86 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29800 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 32 32 336 268 1 167 85 17 17 289 -1 unnamed_device 25.2 MiB 0.20 1783 1032 10315 2877 5917 1521 64.9 MiB 0.05 0.00 4.51952 3.92812 -130.309 -3.92812 3.92812 0.25 0.000322632 0.000292025 0.0200178 0.0182508 -1 -1 -1 -1 38 2695 38 6.95648e+06 303989 678818. 2348.85 0.88 0.0962041 0.0849132 26626 170182 -1 2290 20 1586 2944 220343 47674 3.95326 3.95326 -137.892 -3.95326 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0177714 0.0159486 76 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_006.v common 2.99 vpr 65.46 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29784 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67028 32 32 366 295 1 182 89 17 17 289 -1 unnamed_device 25.6 MiB 0.25 1940 1017 15137 4323 9926 888 65.5 MiB 0.08 0.00 3.4886 3.1127 -116.972 -3.1127 3.1127 0.25 0.0003474 0.00031008 0.0306325 0.0281225 -1 -1 -1 -1 36 2556 21 6.95648e+06 361892 648988. 2245.63 1.35 0.148265 0.129937 26050 158493 -1 2163 22 1481 2233 179619 40338 3.25947 3.25947 -126.143 -3.25947 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0190004 0.0170065 81 58 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_007.v common 5.15 vpr 64.68 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30108 -1 -1 14 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 27 32 259 221 1 124 73 17 17 289 -1 unnamed_device 25.2 MiB 2.03 1479 544 11169 5105 5436 628 64.7 MiB 0.04 0.00 3.66833 3.46173 -93.1309 -3.46173 3.46173 0.25 0.000261857 0.000239568 0.0209747 0.0192546 -1 -1 -1 -1 38 1555 46 6.95648e+06 202660 678818. 2348.85 1.71 0.145141 0.126544 26626 170182 -1 1272 22 1128 1830 194540 63071 2.72212 2.72212 -92.3383 -2.72212 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0173633 0.0154463 52 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_008.v common 2.44 vpr 65.14 MiB -1 -1 0.11 17676 1 0.03 -1 -1 30192 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66704 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 25.2 MiB 0.13 1731 837 13758 3354 9842 562 65.1 MiB 0.06 0.00 3.236 3.0033 -96.4877 -3.0033 3.0033 0.25 0.000283257 0.000257476 0.0224466 0.0205166 -1 -1 -1 -1 38 2185 35 6.95648e+06 390843 678818. 2348.85 0.94 0.0935904 0.0819904 26626 170182 -1 1935 17 1016 1691 155726 37439 2.85232 2.85232 -101.969 -2.85232 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0128395 0.0115411 69 4 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_009.v common 6.46 vpr 65.11 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30160 -1 -1 13 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66672 31 32 317 271 1 163 76 17 17 289 -1 unnamed_device 25.4 MiB 1.02 2045 984 6476 1579 4344 553 65.1 MiB 0.04 0.00 4.38541 3.20949 -116.851 -3.20949 3.20949 0.25 0.000304035 0.000278359 0.0141149 0.0129919 -1 -1 -1 -1 38 2225 23 6.95648e+06 188184 678818. 2348.85 4.11 0.175878 0.153736 26626 170182 -1 1916 23 1238 1764 156025 32304 3.10437 3.10437 -120.049 -3.10437 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0167635 0.0150094 63 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_010.v common 2.47 vpr 64.80 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29756 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 298 248 1 150 75 17 17 289 -1 unnamed_device 25.2 MiB 0.52 1624 626 11135 4403 5579 1153 64.8 MiB 0.05 0.00 3.54488 3.30308 -115.111 -3.30308 3.30308 0.25 0.000294589 0.000269238 0.0240851 0.0221711 -1 -1 -1 -1 40 1722 35 6.95648e+06 159232 706193. 2443.58 0.62 0.0818033 0.0720409 26914 176310 -1 1420 24 1290 1850 123276 30882 3.09812 3.09812 -112.612 -3.09812 0 0 926341. 3205.33 0.03 0.04 0.10 -1 -1 0.03 0.0168038 0.0149627 60 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_011.v common 4.11 vpr 64.83 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29584 -1 -1 12 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 30 32 303 262 1 135 74 17 17 289 -1 unnamed_device 25.2 MiB 0.66 1495 729 9064 2569 5999 496 64.8 MiB 0.04 0.00 3.68438 3.28838 -103.976 -3.28838 3.28838 0.24 0.000292096 0.000267169 0.0187869 0.0172538 -1 -1 -1 -1 34 1814 26 6.95648e+06 173708 618332. 2139.56 2.16 0.138849 0.120791 25762 151098 -1 1490 24 1184 1664 130152 30363 3.42052 3.42052 -114.288 -3.42052 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0178223 0.0157866 54 63 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_012.v common 6.43 vpr 65.00 MiB -1 -1 0.13 17672 1 0.03 -1 -1 30076 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 32 32 276 237 1 161 77 17 17 289 -1 unnamed_device 25.2 MiB 0.89 1858 901 11324 2936 7996 392 65.0 MiB 0.05 0.00 4.14163 3.40773 -113.867 -3.40773 3.40773 0.25 0.000320972 0.000297119 0.0219671 0.0201439 -1 -1 -1 -1 38 2225 33 6.95648e+06 188184 678818. 2348.85 4.06 0.177221 0.15457 26626 170182 -1 1830 23 1206 1558 121613 27198 3.12917 3.12917 -117.675 -3.12917 0 0 902133. 3121.57 0.03 0.04 0.10 -1 -1 0.03 0.0181981 0.0163783 61 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_013.v common 7.28 vpr 64.84 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29752 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 344 272 1 194 81 17 17 289 -1 unnamed_device 25.2 MiB 1.00 2661 1052 13556 4454 6679 2423 64.8 MiB 0.07 0.00 4.95968 4.03143 -135.537 -4.03143 4.03143 0.24 0.000326325 0.000299541 0.0282066 0.0259143 -1 -1 -1 -1 38 2740 31 6.95648e+06 246087 678818. 2348.85 4.74 0.196684 0.172533 26626 170182 -1 2270 20 1490 2238 167680 36771 3.49922 3.49922 -132.659 -3.49922 0 0 902133. 3121.57 0.04 0.07 0.13 -1 -1 0.04 0.0232164 0.0208544 80 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_014.v common 3.32 vpr 65.40 MiB -1 -1 0.19 18056 1 0.04 -1 -1 30120 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66968 32 32 363 295 1 174 89 17 17 289 -1 unnamed_device 25.6 MiB 0.20 2639 1006 16721 5083 10286 1352 65.4 MiB 0.07 0.00 5.50502 4.26608 -134.261 -4.26608 4.26608 0.24 0.000347966 0.00031851 0.0304499 0.0278639 -1 -1 -1 -1 44 2225 22 6.95648e+06 361892 787024. 2723.27 1.60 0.154803 0.135854 27778 195446 -1 2034 24 1656 2393 186636 39712 3.87492 3.87492 -138.683 -3.87492 0 0 997811. 3452.63 0.04 0.05 0.11 -1 -1 0.04 0.0186054 0.0166199 78 61 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_015.v common 3.30 vpr 64.66 MiB -1 -1 0.19 18060 1 0.03 -1 -1 29916 -1 -1 18 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 29 32 248 215 1 132 79 17 17 289 -1 unnamed_device 25.6 MiB 0.37 1589 651 12078 4589 5218 2271 64.7 MiB 0.05 0.00 3.39735 2.90715 -89.179 -2.90715 2.90715 0.25 0.000252159 0.00023083 0.0201331 0.0184469 -1 -1 -1 -1 32 1836 31 6.95648e+06 260562 586450. 2029.24 1.34 0.118347 0.102735 25474 144626 -1 1503 20 997 1583 125466 28770 3.05702 3.05702 -99.4476 -3.05702 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0205365 0.0182302 55 27 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_016.v common 2.73 vpr 64.73 MiB -1 -1 0.12 18060 1 0.04 -1 -1 29784 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 370 297 1 178 81 17 17 289 -1 unnamed_device 25.6 MiB 0.39 2049 1029 11981 3954 6378 1649 64.7 MiB 0.06 0.00 3.37235 3.1427 -120.775 -3.1427 3.1427 0.25 0.00035851 0.000328148 0.0268688 0.0246765 -1 -1 -1 -1 36 2643 31 6.95648e+06 246087 648988. 2245.63 0.88 0.10544 0.0937733 26050 158493 -1 2255 24 1811 2949 246149 54989 3.28927 3.28927 -130.375 -3.28927 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0197367 0.0176201 77 58 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 4.33 vpr 65.27 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29808 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66840 32 32 338 269 1 190 81 17 17 289 -1 unnamed_device 26.0 MiB 1.14 2597 1132 10756 3252 6270 1234 65.3 MiB 0.09 0.00 4.76516 3.87916 -128.033 -3.87916 3.87916 0.27 0.000563673 0.000514764 0.0381079 0.0349105 -1 -1 -1 -1 42 2528 39 6.95648e+06 246087 744469. 2576.02 1.76 0.175647 0.154706 27202 183097 -1 2217 22 1720 2455 228601 47027 3.26597 3.26597 -129.76 -3.26597 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0178021 0.0160045 78 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_018.v common 2.86 vpr 64.37 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30132 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 32 32 323 276 1 148 80 17 17 289 -1 unnamed_device 25.1 MiB 0.47 1940 709 13324 5680 7328 316 64.4 MiB 0.06 0.00 2.8806 2.25046 -92.451 -2.25046 2.25046 0.24 0.000321601 0.000294567 0.0263952 0.0242186 -1 -1 -1 -1 38 2063 49 6.95648e+06 231611 678818. 2348.85 1.00 0.109513 0.096137 26626 170182 -1 1469 19 1138 1719 118571 27421 2.31168 2.31168 -99.7954 -2.31168 0 0 902133. 3121.57 0.04 0.04 0.11 -1 -1 0.04 0.0146975 0.0132061 61 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_019.v common 2.39 vpr 64.57 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29840 -1 -1 11 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 30 32 222 206 1 114 73 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1511 777 10865 4570 5988 307 64.6 MiB 0.04 0.00 2.51091 2.19546 -86.0348 -2.19546 2.19546 0.24 0.000228699 0.000208066 0.0176833 0.0161505 -1 -1 -1 -1 30 1680 41 6.95648e+06 159232 556674. 1926.21 1.04 0.0942002 0.0812793 25186 138497 -1 1470 25 872 1208 156123 52175 2.24868 2.24868 -93.6233 -2.24868 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0130512 0.0115238 44 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_020.v common 4.25 vpr 65.08 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29832 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66644 31 32 291 243 1 167 77 17 17 289 -1 unnamed_device 25.2 MiB 1.28 1942 915 11161 3690 6402 1069 65.1 MiB 0.05 0.00 5.06493 4.53133 -147.051 -4.53133 4.53133 0.25 0.000298558 0.000268472 0.0217239 0.0198683 -1 -1 -1 -1 36 2497 27 6.95648e+06 202660 648988. 2245.63 1.65 0.13307 0.116025 26050 158493 -1 2085 22 1516 2176 182935 41144 4.25897 4.25897 -152.532 -4.25897 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0156028 0.0139499 68 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_021.v common 4.09 vpr 65.23 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30352 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66792 32 32 342 271 1 172 91 17 17 289 -1 unnamed_device 26.0 MiB 0.15 2240 900 16819 7148 9182 489 65.2 MiB 0.09 0.00 4.59829 3.69419 -127.892 -3.69419 3.69419 0.25 0.000327843 0.000299751 0.0411088 0.0379383 -1 -1 -1 -1 36 2377 35 6.95648e+06 390843 648988. 2245.63 2.54 0.186161 0.164863 26050 158493 -1 1845 26 1702 2575 179217 41202 3.87196 3.87196 -134.248 -3.87196 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0217552 0.0194069 79 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_022.v common 7.73 vpr 65.38 MiB -1 -1 0.18 17676 1 0.03 -1 -1 30120 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66948 32 32 372 300 1 200 80 17 17 289 -1 unnamed_device 25.6 MiB 0.78 2415 1121 6444 1474 4751 219 65.4 MiB 0.04 0.00 5.37301 4.45576 -133.655 -4.45576 4.45576 0.26 0.00035798 0.00032954 0.0151061 0.0139068 -1 -1 -1 -1 38 2880 26 6.95648e+06 231611 678818. 2348.85 5.52 0.175453 0.15353 26626 170182 -1 2526 22 1727 2641 222774 46845 4.34031 4.34031 -139.36 -4.34031 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0185616 0.0166569 82 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_023.v common 2.66 vpr 64.47 MiB -1 -1 0.10 18060 1 0.02 -1 -1 30160 -1 -1 15 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66020 26 32 190 182 1 104 73 17 17 289 -1 unnamed_device 25.2 MiB 0.20 1222 421 8281 3372 4348 561 64.5 MiB 0.03 0.00 2.67211 2.19726 -65.4152 -2.19726 2.19726 0.26 0.000228356 0.00020948 0.0126875 0.0116165 -1 -1 -1 -1 34 1125 29 6.95648e+06 217135 618332. 2139.56 1.06 0.0810129 0.0700315 25762 151098 -1 896 17 520 688 56109 14316 2.11048 2.11048 -70.2765 -2.11048 0 0 787024. 2723.27 0.04 0.03 0.12 -1 -1 0.04 0.0133129 0.0119175 44 30 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_024.v common 6.89 vpr 64.69 MiB -1 -1 0.10 17676 1 0.03 -1 -1 29772 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 32 32 285 227 1 159 81 17 17 289 -1 unnamed_device 25.2 MiB 0.35 1875 1004 10231 3152 5666 1413 64.7 MiB 0.06 0.00 5.1927 4.35141 -124.49 -4.35141 4.35141 0.25 0.000474772 0.000449994 0.0235867 0.0218554 -1 -1 -1 -1 36 2522 34 6.95648e+06 246087 648988. 2245.63 5.19 0.179034 0.157958 26050 158493 -1 2149 24 1520 2509 215703 44929 4.03036 4.03036 -133.912 -4.03036 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0165415 0.0147724 66 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_025.v common 2.43 vpr 64.38 MiB -1 -1 0.09 17676 1 0.02 -1 -1 30096 -1 -1 10 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 25.1 MiB 0.07 1407 728 7049 2858 4069 122 64.4 MiB 0.02 0.00 2.65931 2.13126 -73.9387 -2.13126 2.13126 0.35 0.000195657 0.000177916 0.0099747 0.00911854 -1 -1 -1 -1 32 1341 22 6.95648e+06 144757 586450. 2029.24 1.01 0.0883843 0.0759555 25474 144626 -1 1180 22 633 749 76305 16284 2.09038 2.09038 -81.6951 -2.09038 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0107041 0.00951017 43 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_026.v common 5.27 vpr 65.07 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29532 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66636 32 32 300 245 1 159 83 17 17 289 -1 unnamed_device 25.2 MiB 0.32 1864 913 6383 1452 4629 302 65.1 MiB 0.04 0.00 5.25865 4.40051 -125.247 -4.40051 4.40051 0.26 0.000324656 0.000298873 0.0125488 0.0115213 -1 -1 -1 -1 34 2450 32 6.95648e+06 275038 618332. 2139.56 3.53 0.144068 0.12555 25762 151098 -1 1968 22 1275 2064 154484 34551 3.92096 3.92096 -128.528 -3.92096 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0158121 0.0141592 67 24 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_027.v common 3.01 vpr 64.59 MiB -1 -1 0.15 17912 1 0.04 -1 -1 29932 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 25.6 MiB 0.11 1827 924 6823 1513 4978 332 64.6 MiB 0.04 0.00 3.55265 2.9965 -104.682 -2.9965 2.9965 0.25 0.000516058 0.000468551 0.0159334 0.0147054 -1 -1 -1 -1 36 2414 49 6.95648e+06 390843 648988. 2245.63 1.42 0.124523 0.109913 26050 158493 -1 2132 24 1474 2395 199348 43414 3.61137 3.61137 -119.408 -3.61137 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0172033 0.015398 77 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_028.v common 8.45 vpr 64.66 MiB -1 -1 0.12 18036 1 0.04 -1 -1 30072 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 32 32 338 277 1 172 87 17 17 289 -1 unnamed_device 25.2 MiB 0.57 2669 874 15063 4561 8642 1860 64.7 MiB 0.07 0.00 5.40282 4.22168 -126.749 -4.22168 4.22168 0.24 0.000319671 0.000291658 0.02712 0.0248042 -1 -1 -1 -1 36 2848 47 6.95648e+06 332941 648988. 2245.63 6.44 0.185299 0.162867 26050 158493 -1 2116 21 1518 2498 224468 49562 4.10051 4.10051 -134.747 -4.10051 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0182949 0.0163777 74 50 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_029.v common 3.03 vpr 64.75 MiB -1 -1 0.19 17676 1 0.02 -1 -1 29812 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 284 241 1 139 79 17 17 289 -1 unnamed_device 25.6 MiB 0.33 1680 676 6670 1523 4966 181 64.7 MiB 0.04 0.00 3.27205 2.9051 -100.648 -2.9051 2.9051 0.24 0.000284299 0.000260273 0.0131353 0.012032 -1 -1 -1 -1 42 1765 28 6.95648e+06 217135 744469. 2576.02 1.26 0.115797 0.100284 27202 183097 -1 1497 22 1119 1800 140720 33242 2.86952 2.86952 -107.095 -2.86952 0 0 949917. 3286.91 0.03 0.04 0.10 -1 -1 0.03 0.0149791 0.0133634 57 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_030.v common 2.72 vpr 64.80 MiB -1 -1 0.14 18060 1 0.02 -1 -1 29852 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 30 32 262 227 1 134 81 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1538 820 8831 2040 6273 518 64.8 MiB 0.05 0.00 3.47888 3.21595 -101.099 -3.21595 3.21595 0.36 0.000386212 0.000355056 0.0224496 0.020607 -1 -1 -1 -1 32 1847 36 6.95648e+06 275038 586450. 2029.24 1.08 0.108432 0.0945639 25474 144626 -1 1689 22 1091 1749 148756 32107 3.02582 3.02582 -108.609 -3.02582 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0174901 0.0155263 59 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_031.v common 4.82 vpr 64.29 MiB -1 -1 0.14 16988 1 0.03 -1 -1 29608 -1 -1 21 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 28 32 260 223 1 135 81 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1490 680 8131 2137 5414 580 64.3 MiB 0.04 0.00 3.44925 2.9041 -94.451 -2.9041 2.9041 0.25 0.000306648 0.000271689 0.0168356 0.0155005 -1 -1 -1 -1 36 1823 27 6.95648e+06 303989 648988. 2245.63 3.31 0.15174 0.132313 26050 158493 -1 1652 18 950 1569 148138 33466 3.16212 3.16212 -107.018 -3.16212 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0121723 0.0109062 60 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_032.v common 3.39 vpr 64.12 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29812 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65664 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 24.9 MiB 0.12 1566 824 4152 861 3106 185 64.1 MiB 0.03 0.00 3.63718 3.35753 -114.051 -3.35753 3.35753 0.26 0.000266189 0.000243736 0.0126143 0.0117093 -1 -1 -1 -1 38 1997 21 6.95648e+06 188184 678818. 2348.85 1.83 0.153 0.132863 26626 170182 -1 1719 21 1284 1950 159352 33411 2.89152 2.89152 -114.478 -2.89152 0 0 902133. 3121.57 0.03 0.04 0.12 -1 -1 0.03 0.0157463 0.0139925 59 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_033.v common 3.90 vpr 64.73 MiB -1 -1 0.20 17676 1 0.02 -1 -1 29760 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 31 32 271 231 1 143 80 17 17 289 -1 unnamed_device 25.2 MiB 0.11 1688 869 8680 2729 4472 1479 64.7 MiB 0.04 0.00 3.72648 3.16398 -108.388 -3.16398 3.16398 0.25 0.00027281 0.000249896 0.0156627 0.0143815 -1 -1 -1 -1 34 2179 22 6.95648e+06 246087 618332. 2139.56 2.41 0.131565 0.114533 25762 151098 -1 2014 21 1110 1930 166652 35472 3.09012 3.09012 -116.571 -3.09012 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0141418 0.0126396 60 30 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_034.v common 4.04 vpr 65.15 MiB -1 -1 0.16 18056 1 0.02 -1 -1 29796 -1 -1 20 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66712 29 32 291 250 1 148 81 17 17 289 -1 unnamed_device 25.2 MiB 0.55 1854 689 13206 5558 7105 543 65.1 MiB 0.06 0.00 2.91366 2.41246 -87.9827 -2.41246 2.41246 0.25 0.000281282 0.000256616 0.0241148 0.0221193 -1 -1 -1 -1 36 2057 43 6.95648e+06 289514 648988. 2245.63 1.88 0.158976 0.138171 26050 158493 -1 1583 29 1369 1971 208107 67819 2.98053 2.98053 -102.288 -2.98053 0 0 828058. 2865.25 0.03 0.07 0.09 -1 -1 0.03 0.0181052 0.0160143 63 54 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_035.v common 7.24 vpr 64.71 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29616 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 32 32 367 282 1 193 97 17 17 289 -1 unnamed_device 25.6 MiB 0.21 2526 1025 17413 5779 8975 2659 64.7 MiB 0.08 0.00 5.03788 4.17868 -123.252 -4.17868 4.17868 0.25 0.000357228 0.000325244 0.030235 0.0275701 -1 -1 -1 -1 42 2595 19 6.95648e+06 477698 744469. 2576.02 5.55 0.206893 0.181707 27202 183097 -1 2211 31 1710 2988 296315 99088 3.69472 3.69472 -122.109 -3.69472 0 0 949917. 3286.91 0.03 0.09 0.11 -1 -1 0.03 0.0247971 0.0221375 91 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_036.v common 3.70 vpr 65.41 MiB -1 -1 0.12 18300 1 0.03 -1 -1 29748 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66984 32 32 391 311 1 184 96 17 17 289 -1 unnamed_device 25.6 MiB 0.38 2256 862 16740 6194 8330 2216 65.4 MiB 0.08 0.00 3.74582 3.41048 -122.287 -3.41048 3.41048 0.34 0.000358304 0.000326722 0.0296809 0.0270057 -1 -1 -1 -1 44 2238 38 6.95648e+06 463222 787024. 2723.27 1.75 0.167056 0.145504 27778 195446 -1 1850 25 2011 3068 224363 51977 3.35632 3.35632 -126.689 -3.35632 0 0 997811. 3452.63 0.04 0.06 0.12 -1 -1 0.04 0.0204384 0.0182152 88 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_037.v common 3.57 vpr 64.55 MiB -1 -1 0.12 18052 1 0.02 -1 -1 30172 -1 -1 13 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 31 32 279 237 1 159 76 17 17 289 -1 unnamed_device 25.5 MiB 0.74 1859 944 11436 4031 5937 1468 64.6 MiB 0.05 0.00 4.42062 3.66882 -116.881 -3.66882 3.66882 0.25 0.000536804 0.000511655 0.0225096 0.020716 -1 -1 -1 -1 40 2026 25 6.95648e+06 188184 706193. 2443.58 1.40 0.115557 0.10067 26914 176310 -1 1930 22 1362 1958 174593 39631 3.25737 3.25737 -121.471 -3.25737 0 0 926341. 3205.33 0.03 0.05 0.13 -1 -1 0.03 0.0175896 0.015843 65 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_038.v common 3.50 vpr 64.73 MiB -1 -1 0.13 18060 1 0.04 -1 -1 30156 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 31 32 370 297 1 179 82 17 17 289 -1 unnamed_device 26.0 MiB 0.37 2058 981 11474 4741 6449 284 64.7 MiB 0.06 0.00 4.15263 3.41873 -120.517 -3.41873 3.41873 0.25 0.000343553 0.000314072 0.0242446 0.0222411 -1 -1 -1 -1 36 2791 28 6.95648e+06 275038 648988. 2245.63 1.51 0.113157 0.100064 26050 158493 -1 2313 25 1860 2917 241256 52575 3.29867 3.29867 -128.902 -3.29867 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0199085 0.017774 78 61 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_039.v common 4.99 vpr 65.45 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29748 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67020 31 32 377 302 1 231 84 17 17 289 -1 unnamed_device 26.0 MiB 1.01 2986 1206 16188 5856 7795 2537 65.4 MiB 0.09 0.00 6.98421 5.23991 -167.77 -5.23991 5.23991 0.24 0.000345786 0.000316332 0.0397705 0.0366514 -1 -1 -1 -1 44 3341 26 6.95648e+06 303989 787024. 2723.27 2.49 0.212114 0.187739 27778 195446 -1 2677 24 2355 3504 330191 67709 4.75275 4.75275 -167.178 -4.75275 0 0 997811. 3452.63 0.04 0.07 0.11 -1 -1 0.04 0.0199259 0.0178701 99 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_040.v common 3.87 vpr 65.04 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30152 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66600 31 32 383 305 1 201 80 17 17 289 -1 unnamed_device 25.6 MiB 1.19 2460 938 14012 6050 7484 478 65.0 MiB 0.07 0.00 5.07595 4.39319 -147.97 -4.39319 4.39319 0.30 0.000353719 0.000323381 0.0319885 0.0293714 -1 -1 -1 -1 46 2574 33 6.95648e+06 246087 828058. 2865.25 1.19 0.122738 0.108773 28066 200906 -1 2087 21 1723 2601 166326 39721 4.33271 4.33271 -148.753 -4.33271 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0184975 0.0166052 88 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_041.v common 6.56 vpr 63.99 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29748 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65524 31 32 352 285 1 177 86 17 17 289 -1 unnamed_device 25.3 MiB 0.61 1905 1063 13505 4619 6904 1982 64.0 MiB 0.07 0.00 3.86153 3.50353 -122.837 -3.50353 3.50353 0.25 0.000334119 0.000306413 0.0260397 0.023895 -1 -1 -1 -1 38 2691 24 6.95648e+06 332941 678818. 2348.85 4.55 0.175979 0.154524 26626 170182 -1 2207 20 1543 2431 175549 38503 3.17607 3.17607 -124.233 -3.17607 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0179781 0.0161697 79 55 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_042.v common 2.72 vpr 65.22 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29772 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66788 32 32 291 242 1 173 82 17 17 289 -1 unnamed_device 25.4 MiB 0.58 2234 1084 10050 2925 5856 1269 65.2 MiB 0.05 0.00 5.02688 4.05268 -121.011 -4.05268 4.05268 0.24 0.000289648 0.000264781 0.018507 0.0170161 -1 -1 -1 -1 36 2592 25 6.95648e+06 260562 648988. 2245.63 0.78 0.0776036 0.068171 26050 158493 -1 2252 21 1397 2007 181674 36928 3.91432 3.91432 -125.021 -3.91432 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0149357 0.0133601 70 27 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_043.v common 8.70 vpr 65.39 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30288 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 32 32 457 356 1 214 92 17 17 289 -1 unnamed_device 26.0 MiB 0.61 3011 1199 9614 2248 6243 1123 65.4 MiB 0.06 0.00 5.60998 4.24958 -145.469 -4.24958 4.24958 0.25 0.000422765 0.000388597 0.0221656 0.0203896 -1 -1 -1 -1 36 3239 50 6.95648e+06 405319 648988. 2245.63 6.67 0.281134 0.247038 26050 158493 -1 2666 23 2075 3298 272107 58339 4.23492 4.23492 -151.925 -4.23492 0 0 828058. 2865.25 0.03 0.07 0.09 -1 -1 0.03 0.0229493 0.0205874 97 87 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_044.v common 1.98 vpr 64.71 MiB -1 -1 0.11 17912 1 0.02 -1 -1 30264 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 31 32 261 225 1 138 80 17 17 289 -1 unnamed_device 25.6 MiB 0.21 1501 818 9024 2908 5023 1093 64.7 MiB 0.04 0.00 3.4146 3.0387 -101.681 -3.0387 3.0387 0.25 0.000266387 0.000243369 0.0156035 0.0143094 -1 -1 -1 -1 32 2004 40 6.95648e+06 246087 586450. 2029.24 0.49 0.0599967 0.0526947 25474 144626 -1 1709 22 1202 1786 156398 34480 3.27367 3.27367 -111.108 -3.27367 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0143091 0.0127558 58 28 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_045.v common 4.00 vpr 64.32 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29872 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 31 32 337 267 1 199 81 17 17 289 -1 unnamed_device 25.6 MiB 0.71 2145 1112 10931 4151 5627 1153 64.3 MiB 0.06 0.00 4.85719 4.35599 -139.539 -4.35599 4.35599 0.25 0.000344925 0.000316949 0.0228979 0.021019 -1 -1 -1 -1 46 2578 27 6.95648e+06 260562 828058. 2865.25 1.80 0.152247 0.133516 28066 200906 -1 2222 20 1385 2128 175307 36107 4.35122 4.35122 -143.095 -4.35122 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0206612 0.0185831 82 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_046.v common 5.18 vpr 65.28 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29724 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66848 32 32 349 284 1 175 90 17 17 289 -1 unnamed_device 25.6 MiB 0.32 2157 965 10542 2851 6614 1077 65.3 MiB 0.06 0.00 3.52265 3.1127 -108.745 -3.1127 3.1127 0.24 0.000330891 0.000302135 0.0192964 0.0176786 -1 -1 -1 -1 36 2961 34 6.95648e+06 376368 648988. 2245.63 3.51 0.168227 0.14795 26050 158493 -1 2355 20 1415 2400 212790 47241 3.46317 3.46317 -122.988 -3.46317 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0163403 0.0146583 78 53 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_047.v common 4.70 vpr 65.20 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29816 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66768 32 32 291 230 1 161 83 17 17 289 -1 unnamed_device 25.6 MiB 0.22 1764 988 11603 4009 6122 1472 65.2 MiB 0.05 0.00 4.66672 3.99627 -123.227 -3.99627 3.99627 0.25 0.000450265 0.000422578 0.0219192 0.0201582 -1 -1 -1 -1 36 2563 29 6.95648e+06 275038 648988. 2245.63 2.93 0.158681 0.13936 26050 158493 -1 2183 22 1428 2520 202696 44123 3.83276 3.83276 -133.9 -3.83276 0 0 828058. 2865.25 0.04 0.08 0.14 -1 -1 0.04 0.0269728 0.0241938 70 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_048.v common 3.77 vpr 65.38 MiB -1 -1 0.17 18056 1 0.04 -1 -1 30056 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66952 32 32 353 287 1 190 80 17 17 289 -1 unnamed_device 25.6 MiB 1.14 2163 1097 11948 3658 6620 1670 65.4 MiB 0.06 0.00 4.63715 4.346 -136.985 -4.346 4.346 0.27 0.000328162 0.000300805 0.0253231 0.0232672 -1 -1 -1 -1 34 2975 47 6.95648e+06 231611 618332. 2139.56 0.96 0.10334 0.0912855 25762 151098 -1 2354 20 1518 2047 175086 38630 3.82676 3.82676 -139.13 -3.82676 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0164645 0.014809 76 55 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_049.v common 2.80 vpr 65.41 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30140 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66976 32 32 361 291 1 178 93 17 17 289 -1 unnamed_device 25.6 MiB 0.36 2190 1077 15423 4714 8722 1987 65.4 MiB 0.07 0.00 3.80407 3.1427 -117.276 -3.1427 3.1427 0.24 0.000335494 0.00030613 0.0268972 0.0246316 -1 -1 -1 -1 36 2642 22 6.95648e+06 419795 648988. 2245.63 1.07 0.115534 0.102164 26050 158493 -1 2227 23 1499 2470 188526 40710 3.00577 3.00577 -119.751 -3.00577 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0206086 0.0184721 81 55 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_050.v common 3.78 vpr 65.39 MiB -1 -1 0.21 18056 1 0.04 -1 -1 29324 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66960 32 32 382 305 1 184 92 17 17 289 -1 unnamed_device 26.0 MiB 0.26 1992 927 11891 3545 6012 2334 65.4 MiB 0.06 0.00 4.22719 3.72599 -122.298 -3.72599 3.72599 0.25 0.000354423 0.000324206 0.022889 0.0209982 -1 -1 -1 -1 38 2841 35 6.95648e+06 405319 678818. 2348.85 1.97 0.123296 0.108865 26626 170182 -1 2185 23 1596 2460 203199 45565 3.39842 3.39842 -128.958 -3.39842 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0194308 0.0173982 86 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_051.v common 3.43 vpr 64.74 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29772 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66292 32 32 306 248 1 160 86 17 17 289 -1 unnamed_device 25.2 MiB 0.41 1773 991 12182 3165 8076 941 64.7 MiB 0.06 0.00 4.66977 4.24147 -124.389 -4.24147 4.24147 0.25 0.000303542 0.000277176 0.0212523 0.0194711 -1 -1 -1 -1 44 2187 23 6.95648e+06 318465 787024. 2723.27 1.56 0.130789 0.114575 27778 195446 -1 1919 20 1150 1977 158945 33393 3.70736 3.70736 -126.727 -3.70736 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0150716 0.01354 70 24 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_052.v common 3.63 vpr 64.13 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29560 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 32 32 319 257 1 191 81 17 17 289 -1 unnamed_device 24.9 MiB 0.60 2389 1129 13556 4515 7064 1977 64.1 MiB 0.07 0.00 5.21638 4.27023 -132.909 -4.27023 4.27023 0.25 0.00032728 0.00029993 0.0285934 0.0263253 -1 -1 -1 -1 46 2261 24 6.95648e+06 246087 828058. 2865.25 1.56 0.139003 0.122239 28066 200906 -1 2053 19 1489 2067 148493 32149 3.91922 3.91922 -135.811 -3.91922 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0243854 0.0220312 78 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_053.v common 4.48 vpr 64.78 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29732 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 31 32 373 299 1 197 80 17 17 289 -1 unnamed_device 26.0 MiB 0.83 2531 897 9540 3871 5214 455 64.8 MiB 0.05 0.00 5.05188 4.17558 -131.538 -4.17558 4.17558 0.25 0.00034728 0.000317831 0.022077 0.0202609 -1 -1 -1 -1 52 2602 45 6.95648e+06 246087 926341. 3205.33 2.17 0.168751 0.148119 29218 227130 -1 1929 23 1708 2759 217252 49174 3.83221 3.83221 -127.134 -3.83221 0 0 1.14541e+06 3963.36 0.04 0.05 0.12 -1 -1 0.04 0.0187353 0.0168008 84 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_054.v common 8.14 vpr 65.36 MiB -1 -1 0.18 18296 1 0.03 -1 -1 30104 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66928 32 32 387 315 1 182 79 17 17 289 -1 unnamed_device 25.6 MiB 0.44 1967 1073 7177 2229 3943 1005 65.4 MiB 0.04 0.00 4.52855 3.87614 -130.615 -3.87614 3.87614 0.31 0.000389174 0.000358475 0.0179409 0.0165194 -1 -1 -1 -1 36 3074 47 6.95648e+06 217135 648988. 2245.63 6.15 0.265094 0.23242 26050 158493 -1 2610 24 1796 3077 296639 62485 4.18392 4.18392 -145.171 -4.18392 0 0 828058. 2865.25 0.03 0.07 0.08 -1 -1 0.03 0.020107 0.0180066 76 77 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_055.v common 2.83 vpr 64.64 MiB -1 -1 0.10 17912 1 0.02 -1 -1 29788 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66192 32 32 251 219 1 136 80 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1592 878 8852 2868 4758 1226 64.6 MiB 0.04 0.00 3.87998 3.17038 -103.769 -3.17038 3.17038 0.25 0.000264988 0.00024193 0.0149789 0.0137099 -1 -1 -1 -1 36 2026 24 6.95648e+06 231611 648988. 2245.63 1.46 0.117846 0.102121 26050 158493 -1 1799 19 1076 1732 149430 31991 3.22042 3.22042 -107.606 -3.22042 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0127789 0.0114464 56 23 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_056.v common 3.40 vpr 65.29 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29828 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66860 32 32 341 285 1 183 78 17 17 289 -1 unnamed_device 25.2 MiB 0.73 1846 1064 9706 3019 5412 1275 65.3 MiB 0.05 0.00 3.60009 3.47479 -130.861 -3.47479 3.47479 0.25 0.000773114 0.000715199 0.0212245 0.0194564 -1 -1 -1 -1 40 2587 46 6.95648e+06 202660 706193. 2443.58 1.27 0.118264 0.104074 26914 176310 -1 2232 22 1763 2514 248265 50335 3.32827 3.32827 -135.378 -3.32827 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0173627 0.0155392 72 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_057.v common 4.17 vpr 65.05 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30200 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 32 32 387 293 1 226 82 17 17 289 -1 unnamed_device 25.5 MiB 0.60 2660 1172 13076 5502 7259 315 65.0 MiB 0.07 0.00 5.95448 4.84692 -154.661 -4.84692 4.84692 0.25 0.000367204 0.000336088 0.0295512 0.0270804 -1 -1 -1 -1 46 3443 25 6.95648e+06 260562 828058. 2865.25 2.08 0.175334 0.154048 28066 200906 -1 2694 32 2085 3257 431955 154928 5.30886 5.30886 -163.334 -5.30886 0 0 1.01997e+06 3529.29 0.04 0.12 0.11 -1 -1 0.04 0.0268485 0.0240574 95 31 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_058.v common 3.02 vpr 65.37 MiB -1 -1 0.13 17916 1 0.03 -1 -1 30352 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66936 32 32 340 270 1 174 84 17 17 289 -1 unnamed_device 25.6 MiB 0.40 1785 1004 12162 4142 6583 1437 65.4 MiB 0.06 0.00 3.74951 3.62421 -127.524 -3.62421 3.62421 0.25 0.000328207 0.000300371 0.0237712 0.0218108 -1 -1 -1 -1 34 2614 24 6.95648e+06 289514 618332. 2139.56 1.06 0.099806 0.0878389 25762 151098 -1 2197 22 1673 2441 224418 54031 3.16082 3.16082 -132.565 -3.16082 0 0 787024. 2723.27 0.05 0.10 0.14 -1 -1 0.05 0.0315226 0.0283479 75 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_059.v common 3.39 vpr 64.27 MiB -1 -1 0.12 17532 1 0.02 -1 -1 29796 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 30 32 278 235 1 143 81 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1631 823 9181 2114 6505 562 64.3 MiB 0.05 0.00 3.34415 2.9573 -102.523 -2.9573 2.9573 0.26 0.00028315 0.000259772 0.0223587 0.0207038 -1 -1 -1 -1 36 1928 25 6.95648e+06 275038 648988. 2245.63 1.83 0.127391 0.111338 26050 158493 -1 1722 21 1126 1816 175406 51035 3.20612 3.20612 -118.395 -3.20612 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0163952 0.0145539 61 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_060.v common 9.47 vpr 65.29 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29820 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66856 32 32 431 332 1 227 82 17 17 289 -1 unnamed_device 25.6 MiB 0.98 2894 1372 10584 3239 6480 865 65.3 MiB 0.07 0.00 6.27232 5.48274 -168.026 -5.48274 5.48274 0.24 0.000400481 0.000366473 0.0260854 0.0239812 -1 -1 -1 -1 40 3261 24 6.95648e+06 260562 706193. 2443.58 7.07 0.217311 0.190731 26914 176310 -1 2808 20 2067 3042 240600 51699 5.01116 5.01116 -171.359 -5.01116 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0201692 0.0181833 94 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 3.66 vpr 64.59 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30340 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66140 32 32 336 268 1 169 89 17 17 289 -1 unnamed_device 25.2 MiB 0.69 1948 1025 14147 4356 8052 1739 64.6 MiB 0.06 0.00 5.21955 4.32235 -136.289 -4.32235 4.32235 0.26 0.000325361 0.00029643 0.025429 0.0232205 -1 -1 -1 -1 38 2361 27 6.95648e+06 361892 678818. 2348.85 1.59 0.152009 0.133043 26626 170182 -1 2059 21 1422 2085 156669 34906 4.01806 4.01806 -140.938 -4.01806 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0168919 0.0151418 75 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_062.v common 2.95 vpr 64.64 MiB -1 -1 0.10 17680 1 0.02 -1 -1 30328 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 231 199 1 136 80 17 17 289 -1 unnamed_device 25.6 MiB 0.15 1662 643 9368 2123 6903 342 64.6 MiB 0.05 0.00 3.47745 2.966 -95.4204 -2.966 2.966 0.26 0.000417153 0.00039395 0.0187903 0.0172787 -1 -1 -1 -1 36 2034 42 6.95648e+06 231611 648988. 2245.63 1.48 0.11454 0.0994636 26050 158493 -1 1518 21 1006 1688 188499 70294 3.07297 3.07297 -103.979 -3.07297 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0133088 0.0118814 54 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_063.v common 3.62 vpr 64.90 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29928 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66456 32 32 349 273 1 184 95 17 17 289 -1 unnamed_device 25.2 MiB 0.19 2110 1084 13919 4620 7096 2203 64.9 MiB 0.07 0.00 5.666 4.87452 -132.402 -4.87452 4.87452 0.27 0.000367143 0.000334943 0.0266391 0.0244722 -1 -1 -1 -1 36 3030 29 6.95648e+06 448746 648988. 2245.63 2.00 0.123915 0.110447 26050 158493 -1 2425 21 1662 3047 282448 59742 4.65731 4.65731 -144.362 -4.65731 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0173935 0.0156353 85 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_064.v common 2.65 vpr 64.11 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29776 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65652 32 32 247 207 1 142 80 17 17 289 -1 unnamed_device 25.2 MiB 0.16 1515 868 8852 2747 5050 1055 64.1 MiB 0.04 0.00 3.51345 2.9793 -108.005 -2.9793 2.9793 0.24 0.000259585 0.000237221 0.0150162 0.0137528 -1 -1 -1 -1 34 1886 24 6.95648e+06 231611 618332. 2139.56 1.18 0.0966165 0.0838043 25762 151098 -1 1797 19 1169 1788 142635 30918 3.15892 3.15892 -117.991 -3.15892 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0128545 0.0115147 58 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_065.v common 3.50 vpr 64.79 MiB -1 -1 0.16 18060 1 0.02 -1 -1 29840 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66340 30 32 278 235 1 141 87 17 17 289 -1 unnamed_device 25.6 MiB 0.33 1720 753 11223 4264 5738 1221 64.8 MiB 0.05 0.00 3.72028 3.23198 -104.978 -3.23198 3.23198 0.35 0.000279277 0.000254685 0.0198131 0.0182093 -1 -1 -1 -1 38 1855 21 6.95648e+06 361892 678818. 2348.85 1.56 0.133737 0.11684 26626 170182 -1 1614 22 1198 1946 139206 32254 3.38942 3.38942 -117.246 -3.38942 0 0 902133. 3121.57 0.05 0.06 0.14 -1 -1 0.05 0.0223008 0.0199494 64 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_066.v common 3.75 vpr 65.32 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29760 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66884 29 32 355 287 1 191 80 17 17 289 -1 unnamed_device 25.6 MiB 0.71 2234 978 11948 4957 6509 482 65.3 MiB 0.06 0.00 4.18549 3.52127 -111.57 -3.52127 3.52127 0.25 0.000328695 0.000300758 0.0250101 0.0229279 -1 -1 -1 -1 44 2569 26 6.95648e+06 275038 787024. 2723.27 1.60 0.138089 0.120443 27778 195446 -1 2149 23 1910 2895 251904 52894 3.24537 3.24537 -116.207 -3.24537 0 0 997811. 3452.63 0.04 0.08 0.11 -1 -1 0.04 0.0236407 0.0211535 81 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_067.v common 2.87 vpr 65.26 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29760 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66824 32 32 358 289 1 171 83 17 17 289 -1 unnamed_device 26.0 MiB 0.49 2085 843 13943 6117 7487 339 65.3 MiB 0.06 0.00 5.02682 4.14368 -134.376 -4.14368 4.14368 0.24 0.000339146 0.000310561 0.0280627 0.025702 -1 -1 -1 -1 36 2481 34 6.95648e+06 275038 648988. 2245.63 1.03 0.111834 0.0985597 26050 158493 -1 1947 23 1701 2459 192548 45377 4.30012 4.30012 -147.879 -4.30012 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0185936 0.0166696 74 54 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_068.v common 8.00 vpr 65.21 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29752 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66780 32 32 353 285 1 175 84 17 17 289 -1 unnamed_device 25.9 MiB 0.37 1817 988 13443 4741 6786 1916 65.2 MiB 0.06 0.00 4.64078 4.17648 -135.842 -4.17648 4.17648 0.24 0.000324448 0.000296469 0.0260462 0.0238591 -1 -1 -1 -1 36 3048 49 6.95648e+06 289514 648988. 2245.63 6.23 0.203406 0.178319 26050 158493 -1 2385 23 1677 2692 269744 58364 4.16382 4.16382 -145.367 -4.16382 0 0 828058. 2865.25 0.03 0.06 0.11 -1 -1 0.03 0.0195483 0.0175155 77 51 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_069.v common 6.19 vpr 65.02 MiB -1 -1 0.11 17916 1 0.03 -1 -1 29808 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 32 32 276 237 1 153 76 17 17 289 -1 unnamed_device 25.6 MiB 1.10 1886 837 9356 2240 6749 367 65.0 MiB 0.05 0.00 4.63212 3.81128 -119.489 -3.81128 3.81128 0.25 0.000277956 0.000254334 0.0212686 0.0195754 -1 -1 -1 -1 38 2203 37 6.95648e+06 173708 678818. 2348.85 3.64 0.151591 0.13123 26626 170182 -1 1790 20 1149 1580 134760 29661 3.38327 3.38327 -119.839 -3.38327 0 0 902133. 3121.57 0.05 0.08 0.10 -1 -1 0.05 0.0324819 0.0289059 59 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_070.v common 3.92 vpr 64.91 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29796 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 31 32 319 272 1 165 77 17 17 289 -1 unnamed_device 25.4 MiB 1.03 1833 985 10672 3667 5493 1512 64.9 MiB 0.05 0.00 4.19022 3.70692 -123.76 -3.70692 3.70692 0.24 0.000301967 0.00027545 0.0222779 0.020474 -1 -1 -1 -1 42 2256 26 6.95648e+06 202660 744469. 2576.02 1.53 0.125605 0.109064 27202 183097 -1 2010 22 1417 2054 188245 38923 3.30947 3.30947 -128.605 -3.30947 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0163974 0.0146881 65 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_071.v common 3.47 vpr 65.02 MiB -1 -1 0.14 17672 1 0.03 -1 -1 30516 -1 -1 29 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66576 30 32 329 273 1 160 91 17 17 289 -1 unnamed_device 25.2 MiB 0.19 1945 745 13351 4198 6604 2549 65.0 MiB 0.08 0.00 3.7091 3.01356 -93.2618 -3.01356 3.01356 0.25 0.000760732 0.000708834 0.035933 0.033495 -1 -1 -1 -1 38 2032 20 6.95648e+06 419795 678818. 2348.85 1.76 0.146264 0.12921 26626 170182 -1 1601 22 1121 1935 125895 29552 3.02112 3.02112 -95.7193 -3.02112 0 0 902133. 3121.57 0.03 0.04 0.18 -1 -1 0.03 0.0161828 0.0144409 75 57 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_072.v common 5.36 vpr 64.51 MiB -1 -1 0.16 17676 1 0.03 -1 -1 30208 -1 -1 30 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 28 32 277 229 1 150 90 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2011 872 12552 3452 7683 1417 64.5 MiB 0.06 0.00 4.66475 3.68024 -105.78 -3.68024 3.68024 0.24 0.000503075 0.000476972 0.0239511 0.0222033 -1 -1 -1 -1 32 2459 50 6.95648e+06 434271 586450. 2029.24 3.79 0.154412 0.135403 25474 144626 -1 2023 22 1254 2170 186743 41740 3.87011 3.87011 -115.393 -3.87011 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0154132 0.0137491 69 27 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_073.v common 2.40 vpr 65.05 MiB -1 -1 0.18 18060 1 0.04 -1 -1 30168 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 30 32 317 269 1 146 75 17 17 289 -1 unnamed_device 25.2 MiB 0.43 1690 920 7501 2498 3863 1140 65.1 MiB 0.04 0.00 3.88478 3.28908 -114.727 -3.28908 3.28908 0.24 0.000297594 0.000272455 0.0159031 0.0146019 -1 -1 -1 -1 32 2138 42 6.95648e+06 188184 586450. 2029.24 0.51 0.0667491 0.0588076 25474 144626 -1 1947 21 1371 2041 175235 41141 3.06372 3.06372 -123.129 -3.06372 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0152027 0.0135917 60 63 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_074.v common 10.45 vpr 64.18 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30184 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 32 32 335 282 1 178 78 17 17 289 -1 unnamed_device 25.2 MiB 0.98 1907 1068 11864 3789 6604 1471 64.2 MiB 0.06 0.00 3.98976 3.26039 -121.807 -3.26039 3.26039 0.25 0.000332258 0.000298989 0.0244042 0.0223413 -1 -1 -1 -1 40 2633 27 6.95648e+06 202660 706193. 2443.58 8.03 0.197614 0.173512 26914 176310 -1 2317 24 1532 2182 220982 44609 3.39857 3.39857 -132.889 -3.39857 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0197269 0.0177008 69 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_075.v common 6.33 vpr 65.14 MiB -1 -1 0.19 17676 1 0.03 -1 -1 29524 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66704 31 32 293 230 1 168 91 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1954 1022 8863 2079 6129 655 65.1 MiB 0.04 0.00 4.72172 4.01902 -124.512 -4.01902 4.01902 0.24 0.0003344 0.000307698 0.0152924 0.0139831 -1 -1 -1 -1 40 2382 38 6.95648e+06 405319 706193. 2443.58 4.77 0.171303 0.149447 26914 176310 -1 2176 25 1492 2546 211497 46101 3.93111 3.93111 -128.021 -3.93111 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0182985 0.016269 77 4 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_076.v common 8.52 vpr 65.37 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29952 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66940 32 32 350 275 1 201 81 17 17 289 -1 unnamed_device 25.8 MiB 0.86 2386 1198 10231 3183 5327 1721 65.4 MiB 0.06 0.00 5.01638 4.27059 -145.615 -4.27059 4.27059 0.25 0.000347323 0.000318969 0.0270089 0.0251911 -1 -1 -1 -1 38 3178 30 6.95648e+06 246087 678818. 2348.85 6.30 0.188955 0.166547 26626 170182 -1 2598 21 1833 2710 208293 44175 4.12906 4.12906 -152.157 -4.12906 0 0 902133. 3121.57 0.04 0.05 0.09 -1 -1 0.04 0.0179993 0.0161953 83 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_077.v common 4.33 vpr 64.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29768 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 385 308 1 176 91 17 17 289 -1 unnamed_device 25.6 MiB 0.76 2067 860 9067 2994 4608 1465 64.7 MiB 0.05 0.00 5.02252 4.13222 -135.728 -4.13222 4.13222 0.25 0.000357951 0.000322619 0.0220214 0.0203008 -1 -1 -1 -1 52 2139 29 6.95648e+06 390843 926341. 3205.33 2.07 0.163955 0.142438 29218 227130 -1 1758 23 1486 2566 195701 45640 3.61706 3.61706 -133.911 -3.61706 0 0 1.14541e+06 3963.36 0.04 0.05 0.14 -1 -1 0.04 0.0192195 0.0172358 81 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_078.v common 3.00 vpr 65.49 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29848 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67064 32 32 387 309 1 182 98 17 17 289 -1 unnamed_device 26.0 MiB 0.37 2383 1001 14723 3257 11066 400 65.5 MiB 0.07 0.00 4.65582 4.051 -135.3 -4.051 4.051 0.26 0.000364327 0.000329589 0.0259811 0.0236825 -1 -1 -1 -1 46 2674 49 6.95648e+06 492173 828058. 2865.25 1.18 0.131299 0.115986 28066 200906 -1 2258 24 1693 2916 231831 48343 3.79886 3.79886 -135.102 -3.79886 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0221089 0.0198942 88 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_079.v common 2.49 vpr 64.73 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29664 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 30 32 272 232 1 142 75 17 17 289 -1 unnamed_device 25.2 MiB 0.34 1640 871 10503 3905 4899 1699 64.7 MiB 0.05 0.00 4.04631 3.58091 -110.597 -3.58091 3.58091 0.25 0.000271226 0.000247969 0.0204865 0.0188574 -1 -1 -1 -1 40 1905 22 6.95648e+06 188184 706193. 2443.58 0.82 0.0881242 0.0774387 26914 176310 -1 1801 18 1073 1821 136370 29998 2.95232 2.95232 -113.094 -2.95232 0 0 926341. 3205.33 0.03 0.04 0.09 -1 -1 0.03 0.0127374 0.0114172 58 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_080.v common 3.12 vpr 64.73 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29792 -1 -1 16 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 30 32 375 299 1 179 78 17 17 289 -1 unnamed_device 25.6 MiB 0.20 2263 979 14022 6059 7515 448 64.7 MiB 0.07 0.00 4.96142 3.95902 -134.036 -3.95902 3.95902 0.24 0.000345961 0.000317658 0.0343629 0.0315794 -1 -1 -1 -1 40 2208 27 6.95648e+06 231611 706193. 2443.58 1.48 0.146559 0.128454 26914 176310 -1 1994 23 2050 2994 247756 52238 3.84676 3.84676 -136.997 -3.84676 0 0 926341. 3205.33 0.03 0.08 0.11 -1 -1 0.03 0.0293045 0.0261939 78 63 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_081.v common 4.32 vpr 65.41 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29852 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66984 32 32 340 270 1 193 82 17 17 289 -1 unnamed_device 25.3 MiB 0.83 2252 1135 5422 1105 3974 343 65.4 MiB 0.03 0.00 5.21041 4.51361 -142.408 -4.51361 4.51361 0.25 0.000326717 0.000299349 0.0118588 0.010928 -1 -1 -1 -1 48 2777 21 6.95648e+06 260562 865456. 2994.66 2.04 0.1506 0.131797 28354 207349 -1 2286 24 1653 2579 248336 48799 4.23062 4.23062 -147.459 -4.23062 0 0 1.05005e+06 3633.38 0.04 0.06 0.11 -1 -1 0.04 0.0184952 0.0165578 80 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_082.v common 7.39 vpr 65.29 MiB -1 -1 0.12 18444 1 0.04 -1 -1 29792 -1 -1 16 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66852 31 32 340 275 1 188 79 17 17 289 -1 unnamed_device 25.4 MiB 0.83 2310 992 9543 2486 6548 509 65.3 MiB 0.06 0.00 6.40554 5.4777 -155.957 -5.4777 5.4777 0.25 0.000327639 0.000300051 0.020285 0.0186377 -1 -1 -1 -1 38 2728 50 6.95648e+06 231611 678818. 2348.85 5.14 0.179636 0.157579 26626 170182 -1 2193 21 1591 2407 184090 43251 4.33266 4.33266 -145.385 -4.33266 0 0 902133. 3121.57 0.04 0.05 0.09 -1 -1 0.04 0.0169823 0.0152252 80 47 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_083.v common 3.68 vpr 64.68 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30372 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 30 32 377 310 1 169 87 17 17 289 -1 unnamed_device 25.6 MiB 1.28 1889 756 14871 5671 7163 2037 64.7 MiB 0.06 0.00 4.34198 4.07348 -128.883 -4.07348 4.07348 0.24 0.000338279 0.000309011 0.0286867 0.0262429 -1 -1 -1 -1 40 2318 30 6.95648e+06 361892 706193. 2443.58 1.01 0.100877 0.0892676 26914 176310 -1 1820 22 1439 2322 207641 51502 3.33982 3.33982 -122.459 -3.33982 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.018083 0.0162233 76 83 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_084.v common 3.78 vpr 65.30 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30156 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66864 32 32 365 294 1 177 79 17 17 289 -1 unnamed_device 26.0 MiB 0.31 1978 1030 12247 4070 6334 1843 65.3 MiB 0.06 0.00 4.70608 4.25858 -140.542 -4.25858 4.25858 0.25 0.000351506 0.000322633 0.0273447 0.0251296 -1 -1 -1 -1 46 2664 29 6.95648e+06 217135 828058. 2865.25 2.04 0.190442 0.16687 28066 200906 -1 2305 22 1743 3062 250592 49506 3.92702 3.92702 -139.174 -3.92702 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0181199 0.016217 74 57 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_085.v common 2.99 vpr 64.88 MiB -1 -1 0.13 18444 1 0.03 -1 -1 30004 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 29 32 378 310 1 170 86 17 17 289 -1 unnamed_device 25.5 MiB 0.38 1806 1002 10670 2920 6625 1125 64.9 MiB 0.05 0.00 3.96908 3.44163 -116.475 -3.44163 3.44163 0.25 0.000347162 0.000317562 0.0214865 0.0197233 -1 -1 -1 -1 36 2578 39 6.95648e+06 361892 648988. 2245.63 1.22 0.118359 0.104523 26050 158493 -1 2261 28 1817 2808 264581 56589 3.83567 3.83567 -128.927 -3.83567 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0211173 0.0187645 78 85 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_086.v common 2.57 vpr 64.28 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30124 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 243 205 1 140 76 17 17 289 -1 unnamed_device 25.2 MiB 0.62 1666 819 5676 1328 4145 203 64.3 MiB 0.04 0.00 3.96613 3.48283 -113.364 -3.48283 3.48283 0.25 0.000466901 0.000444113 0.0149633 0.0138973 -1 -1 -1 -1 34 1869 21 6.95648e+06 173708 618332. 2139.56 0.57 0.0703562 0.0621034 25762 151098 -1 1695 23 1032 1521 123987 26549 3.10097 3.10097 -115.483 -3.10097 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0146156 0.0130885 55 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_087.v common 5.53 vpr 64.86 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30140 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66416 32 32 373 302 1 170 91 17 17 289 -1 unnamed_device 25.0 MiB 2.25 2487 909 14983 5086 7268 2629 64.9 MiB 0.07 0.00 5.45342 4.07722 -130.088 -4.07722 4.07722 0.25 0.000344536 0.000314315 0.0289953 0.0265024 -1 -1 -1 -1 48 2299 22 6.95648e+06 390843 865456. 2994.66 1.80 0.164245 0.143738 28354 207349 -1 1991 19 1367 2167 187733 39323 4.06326 4.06326 -132.586 -4.06326 0 0 1.05005e+06 3633.38 0.04 0.05 0.11 -1 -1 0.04 0.0163677 0.0147465 77 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_088.v common 2.57 vpr 64.77 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29748 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 32 32 397 314 1 188 78 17 17 289 -1 unnamed_device 25.5 MiB 0.26 2454 1052 12860 4424 7590 846 64.8 MiB 0.07 0.00 4.96142 3.97692 -145.635 -3.97692 3.97692 0.24 0.000362887 0.000332149 0.0302037 0.0277082 -1 -1 -1 -1 40 2507 27 6.95648e+06 202660 706193. 2443.58 0.88 0.104123 0.0923463 26914 176310 -1 2263 21 2040 3064 258642 54364 3.94116 3.94116 -154.866 -3.94116 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0185875 0.0166838 80 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_089.v common 3.21 vpr 63.55 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30216 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65076 32 32 269 231 1 163 77 17 17 289 -1 unnamed_device 25.0 MiB 0.84 1853 775 10346 4263 5879 204 63.6 MiB 0.05 0.00 3.82363 3.41043 -106.561 -3.41043 3.41043 0.25 0.000274716 0.000250626 0.0190657 0.017461 -1 -1 -1 -1 40 2161 23 6.95648e+06 188184 706193. 2443.58 0.92 0.0905387 0.0795776 26914 176310 -1 1801 21 1327 1750 165546 38654 3.26227 3.26227 -113.791 -3.26227 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0146235 0.0130764 64 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_090.v common 2.68 vpr 64.38 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29944 -1 -1 16 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 31 32 245 205 1 144 79 17 17 289 -1 unnamed_device 25.2 MiB 0.15 1533 780 8529 3413 4923 193 64.4 MiB 0.04 0.00 3.74228 3.28943 -106.539 -3.28943 3.28943 0.26 0.000258839 0.000236409 0.0154785 0.0142302 -1 -1 -1 -1 34 1921 28 6.95648e+06 231611 618332. 2139.56 1.20 0.108495 0.0938914 25762 151098 -1 1669 23 1353 2052 154963 33971 3.10392 3.10392 -112.189 -3.10392 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0143899 0.0127996 59 4 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_091.v common 4.12 vpr 65.40 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29760 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66972 32 32 348 274 1 203 82 17 17 289 -1 unnamed_device 25.6 MiB 0.76 2467 1004 13432 4674 7054 1704 65.4 MiB 0.07 0.00 5.20718 4.12648 -139.222 -4.12648 4.12648 0.25 0.000332018 0.000303875 0.0273176 0.0250357 -1 -1 -1 -1 44 2510 23 6.95648e+06 260562 787024. 2723.27 1.70 0.141425 0.12424 27778 195446 -1 2086 22 1919 2600 212528 45424 4.00852 4.00852 -143.085 -4.00852 0 0 997811. 3452.63 0.04 0.05 0.11 -1 -1 0.04 0.0181433 0.0162844 82 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_092.v common 3.92 vpr 65.39 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29836 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 32 32 356 289 1 193 83 17 17 289 -1 unnamed_device 25.3 MiB 0.70 2587 1001 13943 3775 9769 399 65.4 MiB 0.07 0.00 5.38354 4.77262 -147.362 -4.77262 4.77262 0.25 0.00034617 0.000316777 0.0291289 0.0266296 -1 -1 -1 -1 46 2365 25 6.95648e+06 275038 828058. 2865.25 1.74 0.164581 0.144566 28066 200906 -1 2008 23 1426 2177 149929 33848 4.62936 4.62936 -148.354 -4.62936 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0184672 0.0165355 82 56 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_093.v common 2.94 vpr 65.11 MiB -1 -1 0.18 18060 1 0.03 -1 -1 29804 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66668 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 25.6 MiB 0.14 2197 1019 15213 5463 7727 2023 65.1 MiB 0.09 0.00 5.73982 4.68117 -141.736 -4.68117 4.68117 0.34 0.000368249 0.000317849 0.0353615 0.0325265 -1 -1 -1 -1 44 2766 38 6.95648e+06 419795 787024. 2723.27 1.13 0.119924 0.107142 27778 195446 -1 2279 21 1815 3185 288567 62270 4.55991 4.55991 -145.102 -4.55991 0 0 997811. 3452.63 0.04 0.07 0.11 -1 -1 0.04 0.0206305 0.0183858 90 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_094.v common 2.73 vpr 64.57 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29912 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 30 32 316 264 1 156 89 17 17 289 -1 unnamed_device 25.6 MiB 0.22 1994 761 12563 2870 9117 576 64.6 MiB 0.06 0.00 3.94408 3.31423 -98.4865 -3.31423 3.31423 0.39 0.000306285 0.000278227 0.0224075 0.0205549 -1 -1 -1 -1 36 2264 42 6.95648e+06 390843 648988. 2245.63 0.99 0.131193 0.116194 26050 158493 -1 1901 21 1431 2403 188292 43569 3.19992 3.19992 -108.587 -3.19992 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0162737 0.0145473 71 52 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_095.v common 2.55 vpr 64.66 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30556 -1 -1 19 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 27 32 255 219 1 128 78 17 17 289 -1 unnamed_device 25.4 MiB 0.16 1405 640 9872 2965 6271 636 64.7 MiB 0.04 0.00 3.54465 2.9243 -92.5518 -2.9243 2.9243 0.25 0.000264446 0.000241443 0.0170022 0.0155638 -1 -1 -1 -1 32 1668 25 6.95648e+06 275038 586450. 2029.24 1.07 0.0945713 0.0820646 25474 144626 -1 1378 22 1095 1565 118686 26784 2.92552 2.92552 -98.9985 -2.92552 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0136876 0.0121712 59 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_096.v common 3.68 vpr 65.58 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29744 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67152 32 32 421 327 1 224 82 17 17 289 -1 unnamed_device 26.0 MiB 0.61 2597 1273 12720 3612 7834 1274 65.6 MiB 0.08 0.00 4.73785 3.78655 -136.554 -3.78655 3.78655 0.24 0.000384672 0.000352581 0.0300313 0.0275734 -1 -1 -1 -1 42 3519 29 6.95648e+06 260562 744469. 2576.02 1.63 0.132697 0.117622 27202 183097 -1 3005 22 2080 3405 314185 64432 3.95532 3.95532 -149.527 -3.95532 0 0 949917. 3286.91 0.03 0.07 0.10 -1 -1 0.03 0.021025 0.0188977 93 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_097.v common 5.44 vpr 64.93 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29760 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66488 31 32 365 296 1 191 80 17 17 289 -1 unnamed_device 25.6 MiB 2.64 2283 1122 12292 4005 7130 1157 64.9 MiB 0.07 0.00 5.96575 5.12445 -155.529 -5.12445 5.12445 0.25 0.000337024 0.000308455 0.0295189 0.0270785 -1 -1 -1 -1 38 2762 45 6.95648e+06 246087 678818. 2348.85 1.37 0.131579 0.116282 26626 170182 -1 2224 21 1531 2248 178571 38503 4.67096 4.67096 -158.865 -4.67096 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0195671 0.0176194 81 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_098.v common 5.12 vpr 64.20 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30128 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65736 32 32 331 280 1 171 77 17 17 289 -1 unnamed_device 25.2 MiB 2.35 2263 831 10346 4372 5809 165 64.2 MiB 0.05 0.00 4.65874 3.66435 -131.027 -3.66435 3.66435 0.24 0.000310938 0.000283553 0.0216721 0.0198615 -1 -1 -1 -1 40 2127 20 6.95648e+06 188184 706193. 2443.58 1.44 0.137458 0.120294 26914 176310 -1 1839 21 1307 1913 170049 36740 3.63446 3.63446 -138.29 -3.63446 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0166748 0.0149375 69 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_099.v common 3.11 vpr 65.18 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30312 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66744 32 32 326 263 1 169 91 17 17 289 -1 unnamed_device 25.6 MiB 0.10 1919 1016 13147 4843 6404 1900 65.2 MiB 0.06 0.00 4.64482 4.16998 -130.262 -4.16998 4.16998 0.24 0.000346533 0.000316496 0.0224885 0.020484 -1 -1 -1 -1 40 2384 25 6.95648e+06 390843 706193. 2443.58 1.56 0.137469 0.119796 26914 176310 -1 2171 22 1287 2054 170952 36008 3.73576 3.73576 -130.81 -3.73576 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0168862 0.0151431 78 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_100.v common 5.22 vpr 64.75 MiB -1 -1 0.22 18060 1 0.03 -1 -1 29868 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66308 31 32 373 294 1 188 89 17 17 289 -1 unnamed_device 25.2 MiB 0.30 1978 1064 14147 4993 7358 1796 64.8 MiB 0.07 0.00 4.83868 4.13778 -125.088 -4.13778 4.13778 0.24 0.000347007 0.000317888 0.0269397 0.0247308 -1 -1 -1 -1 32 2893 42 6.95648e+06 376368 586450. 2029.24 3.43 0.174284 0.153096 25474 144626 -1 2450 24 1685 2597 193336 42653 3.90842 3.90842 -134.368 -3.90842 0 0 744469. 2576.02 0.03 0.06 0.09 -1 -1 0.03 0.0209366 0.0188136 86 50 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_101.v common 2.29 vpr 64.83 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29816 -1 -1 26 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66384 30 32 325 268 1 165 88 17 17 289 -1 unnamed_device 25.2 MiB 0.30 2005 1028 11788 3531 6603 1654 64.8 MiB 0.05 0.00 3.5368 3.13114 -104.094 -3.13114 3.13114 0.25 0.00031141 0.000284959 0.0207535 0.0190534 -1 -1 -1 -1 38 2346 24 6.95648e+06 376368 678818. 2348.85 0.66 0.0754822 0.0665845 26626 170182 -1 2032 19 1160 1908 135098 29773 3.16517 3.16517 -107.895 -3.16517 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0149197 0.013408 73 51 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_102.v common 7.44 vpr 64.93 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29764 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 350 275 1 208 82 17 17 289 -1 unnamed_device 25.6 MiB 0.70 2473 1225 12364 3185 8008 1171 64.9 MiB 0.08 0.00 4.77678 4.16128 -145.153 -4.16128 4.16128 0.26 0.000404071 0.000374789 0.0313753 0.0288088 -1 -1 -1 -1 44 3002 25 6.95648e+06 260562 787024. 2723.27 5.26 0.181151 0.159774 27778 195446 -1 2501 21 1929 2888 254181 52739 4.05232 4.05232 -152.306 -4.05232 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0178059 0.0160364 86 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_103.v common 3.78 vpr 65.50 MiB -1 -1 0.14 18444 1 0.03 -1 -1 29880 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67076 32 32 386 307 1 187 93 17 17 289 -1 unnamed_device 25.7 MiB 0.43 2024 1035 11643 3723 6128 1792 65.5 MiB 0.06 0.00 3.74723 3.51453 -126.992 -3.51453 3.51453 0.26 0.000359398 0.000328095 0.0219604 0.0201218 -1 -1 -1 -1 38 2497 41 6.95648e+06 419795 678818. 2348.85 1.61 0.171102 0.149711 26626 170182 -1 2126 21 1643 2340 175495 37297 3.06657 3.06657 -126.206 -3.06657 0 0 902133. 3121.57 0.04 0.07 0.13 -1 -1 0.04 0.0262995 0.0235558 89 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_104.v common 3.91 vpr 64.29 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29856 -1 -1 13 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 29 32 269 229 1 131 74 17 17 289 -1 unnamed_device 25.2 MiB 1.98 1409 525 11234 4704 6022 508 64.3 MiB 0.06 0.00 4.32326 3.73256 -100.612 -3.73256 3.73256 0.25 0.000454335 0.00043038 0.027869 0.0258546 -1 -1 -1 -1 36 1494 27 6.95648e+06 188184 648988. 2245.63 0.58 0.0907463 0.0799895 26050 158493 -1 1158 19 812 1114 77704 18636 2.78907 2.78907 -96.8024 -2.78907 0 0 828058. 2865.25 0.03 0.03 0.08 -1 -1 0.03 0.0132226 0.0118612 54 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_105.v common 3.50 vpr 65.11 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29916 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66668 32 32 310 266 1 169 78 17 17 289 -1 unnamed_device 25.2 MiB 0.56 1977 706 10038 3625 5105 1308 65.1 MiB 0.05 0.00 3.7422 3.1157 -108.673 -3.1157 3.1157 0.33 0.000294774 0.000269053 0.0197681 0.0181074 -1 -1 -1 -1 40 1746 31 6.95648e+06 202660 706193. 2443.58 1.49 0.12737 0.110608 26914 176310 -1 1498 22 1422 1863 141586 36360 3.37177 3.37177 -118.821 -3.37177 0 0 926341. 3205.33 0.03 0.04 0.10 -1 -1 0.03 0.015732 0.0140493 66 58 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_106.v common 3.58 vpr 65.12 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29912 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66684 31 32 326 261 1 170 94 17 17 289 -1 unnamed_device 25.2 MiB 0.17 2332 811 13087 3914 6088 3085 65.1 MiB 0.05 0.00 4.97742 3.97428 -119.674 -3.97428 3.97428 0.24 0.000315998 0.000287636 0.0230737 0.0211763 -1 -1 -1 -1 40 2279 46 6.95648e+06 448746 706193. 2443.58 2.01 0.173492 0.152007 26914 176310 -1 1762 28 1677 2723 255514 76442 3.96126 3.96126 -125.346 -3.96126 0 0 926341. 3205.33 0.04 0.08 0.10 -1 -1 0.04 0.0227733 0.0202212 80 33 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_107.v common 2.68 vpr 65.11 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29856 -1 -1 17 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66668 29 32 262 224 1 162 78 17 17 289 -1 unnamed_device 25.2 MiB 0.53 1704 832 10204 3476 5170 1558 65.1 MiB 0.04 0.00 4.25002 3.76672 -110.108 -3.76672 3.76672 0.24 0.000262567 0.000240474 0.0178239 0.0163649 -1 -1 -1 -1 34 2241 29 6.95648e+06 246087 618332. 2139.56 0.83 0.0787243 0.0694314 25762 151098 -1 1822 23 1401 1800 155915 34217 3.33297 3.33297 -112.31 -3.33297 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.01507 0.0132915 66 31 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_108.v common 4.86 vpr 64.69 MiB -1 -1 0.14 17676 1 0.02 -1 -1 30212 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66244 32 32 278 238 1 144 75 17 17 289 -1 unnamed_device 25.6 MiB 0.71 1586 629 9871 3760 4775 1336 64.7 MiB 0.05 0.00 4.25682 3.85356 -110.478 -3.85356 3.85356 0.25 0.000276118 0.000252385 0.0198227 0.0181798 -1 -1 -1 -1 36 2060 29 6.95648e+06 159232 648988. 2245.63 2.80 0.142247 0.123915 26050 158493 -1 1562 24 1364 2227 179795 40766 3.45952 3.45952 -119.804 -3.45952 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.015841 0.0140933 56 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_109.v common 3.44 vpr 64.82 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29784 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66376 31 32 373 300 1 174 94 17 17 289 -1 unnamed_device 25.5 MiB 0.39 1975 777 12235 3547 6422 2266 64.8 MiB 0.06 0.00 3.92078 3.36072 -113.014 -3.36072 3.36072 0.24 0.000343711 0.000312696 0.0218847 0.0199664 -1 -1 -1 -1 36 2383 29 6.95648e+06 448746 648988. 2245.63 1.69 0.174196 0.152739 26050 158493 -1 1890 23 1823 2630 192141 46427 3.32232 3.32232 -125.254 -3.32232 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0193631 0.0172866 83 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_110.v common 4.31 vpr 64.29 MiB -1 -1 0.12 17920 1 0.02 -1 -1 30204 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 31 32 265 230 1 159 77 17 17 289 -1 unnamed_device 24.6 MiB 1.08 1790 729 11813 4928 6553 332 64.3 MiB 0.05 0.00 3.77783 3.40453 -105.323 -3.40453 3.40453 0.25 0.000308872 0.000277629 0.0214596 0.0196707 -1 -1 -1 -1 40 2146 36 6.95648e+06 202660 706193. 2443.58 1.84 0.134082 0.117173 26914 176310 -1 1739 22 1464 2120 189319 43391 3.29247 3.29247 -120.401 -3.29247 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0143602 0.0128295 61 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_111.v common 3.26 vpr 64.05 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29460 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 349 286 1 165 90 17 17 289 -1 unnamed_device 25.4 MiB 0.60 2297 786 16371 5346 8562 2463 64.1 MiB 0.07 0.00 3.67454 3.219 -105.866 -3.219 3.219 0.25 0.000337391 0.000309016 0.0296005 0.0271143 -1 -1 -1 -1 36 2478 41 6.95648e+06 376368 648988. 2245.63 1.24 0.10822 0.0954031 26050 158493 -1 1746 19 1244 2022 141843 33916 3.28147 3.28147 -107.564 -3.28147 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0160826 0.0144954 73 57 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_112.v common 3.73 vpr 64.76 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29768 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 396 325 1 176 83 17 17 289 -1 unnamed_device 25.6 MiB 0.93 2367 760 13403 5641 7157 605 64.8 MiB 0.07 0.00 4.16215 3.42825 -117.829 -3.42825 3.42825 0.24 0.000472934 0.000415205 0.0310469 0.0284745 -1 -1 -1 -1 40 2441 42 6.95648e+06 289514 706193. 2443.58 1.28 0.128029 0.113433 26914 176310 -1 1940 25 1789 2570 188127 47601 3.62427 3.62427 -132.869 -3.62427 0 0 926341. 3205.33 0.03 0.06 0.12 -1 -1 0.03 0.0248133 0.0219353 79 91 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_113.v common 2.56 vpr 64.76 MiB -1 -1 0.12 18056 1 0.04 -1 -1 30116 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 303 262 1 145 75 17 17 289 -1 unnamed_device 25.6 MiB 0.21 1778 712 10977 4578 6228 171 64.8 MiB 0.05 0.00 3.29253 2.84005 -99.7836 -2.84005 2.84005 0.25 0.00042795 0.000388641 0.0239453 0.021948 -1 -1 -1 -1 36 2050 34 6.95648e+06 159232 648988. 2245.63 0.79 0.0853346 0.0750854 26050 158493 -1 1762 20 1194 1822 154899 35238 3.11192 3.11192 -113.612 -3.11192 0 0 828058. 2865.25 0.05 0.07 0.15 -1 -1 0.05 0.0238669 0.0213025 58 57 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_114.v common 3.40 vpr 64.19 MiB -1 -1 0.13 18296 1 0.03 -1 -1 29756 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 32 32 290 244 1 172 78 17 17 289 -1 unnamed_device 25.2 MiB 0.73 1995 861 8378 1972 6153 253 64.2 MiB 0.04 0.00 3.97583 3.49463 -115.332 -3.49463 3.49463 0.26 0.000286549 0.000262684 0.0160968 0.0147723 -1 -1 -1 -1 40 2267 25 6.95648e+06 202660 706193. 2443.58 1.28 0.0945591 0.0830124 26914 176310 -1 1967 21 1553 2292 189903 41785 3.35347 3.35347 -120.801 -3.35347 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0147377 0.0131938 68 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_115.v common 4.63 vpr 64.66 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29772 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 318 257 1 190 81 17 17 289 -1 unnamed_device 25.6 MiB 0.63 1985 868 6206 1328 4710 168 64.7 MiB 0.03 0.00 4.72618 4.25388 -127.376 -4.25388 4.25388 0.24 0.000319888 0.000293074 0.0132111 0.0121845 -1 -1 -1 -1 36 2808 32 6.95648e+06 246087 648988. 2245.63 2.57 0.158635 0.139331 26050 158493 -1 2074 22 1723 2285 180456 42709 4.25992 4.25992 -139.303 -4.25992 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0165456 0.0148185 76 30 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_116.v common 4.11 vpr 64.66 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29780 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 29 32 324 268 1 162 86 17 17 289 -1 unnamed_device 25.0 MiB 0.51 1715 960 12371 3218 7643 1510 64.7 MiB 0.06 0.00 4.12939 3.75349 -109.494 -3.75349 3.75349 0.25 0.000312325 0.000285891 0.0222995 0.0204763 -1 -1 -1 -1 36 2399 29 6.95648e+06 361892 648988. 2245.63 2.08 0.162881 0.143154 26050 158493 -1 2124 24 1309 2223 188987 40183 3.40282 3.40282 -112.56 -3.40282 0 0 828058. 2865.25 0.03 0.05 0.10 -1 -1 0.03 0.0178762 0.0159922 73 55 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_117.v common 10.74 vpr 64.86 MiB -1 -1 0.12 18296 1 0.03 -1 -1 29960 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66412 32 32 393 312 1 205 80 17 17 289 -1 unnamed_device 25.6 MiB 0.82 2498 877 13324 5609 7307 408 64.9 MiB 0.07 0.00 5.49221 4.58061 -145.903 -4.58061 4.58061 0.25 0.000374154 0.000342411 0.0337134 0.0310037 -1 -1 -1 -1 42 3205 39 6.95648e+06 231611 744469. 2576.02 8.24 0.240569 0.211499 27202 183097 -1 2393 26 2399 3408 288616 65006 4.30292 4.30292 -159.239 -4.30292 0 0 949917. 3286.91 0.05 0.10 0.14 -1 -1 0.05 0.0309125 0.0275603 86 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_118.v common 2.34 vpr 64.54 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29936 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 31 32 229 197 1 137 77 17 17 289 -1 unnamed_device 24.9 MiB 0.37 1573 789 7738 2349 3877 1512 64.5 MiB 0.03 0.00 3.62318 3.27643 -101.711 -3.27643 3.27643 0.24 0.000248976 0.000227423 0.0132757 0.0121928 -1 -1 -1 -1 34 1944 27 6.95648e+06 202660 618332. 2139.56 0.69 0.0826342 0.0725114 25762 151098 -1 1657 22 990 1577 151209 32013 3.17312 3.17312 -112.749 -3.17312 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0133466 0.0118792 54 4 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_119.v common 6.20 vpr 65.46 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29756 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67036 32 32 412 334 1 182 92 17 17 289 -1 unnamed_device 25.5 MiB 0.34 2584 779 15410 4873 7828 2709 65.5 MiB 0.07 0.00 4.99926 3.90964 -132.617 -3.90964 3.90964 0.35 0.000367291 0.000335681 0.0295207 0.0270144 -1 -1 -1 -1 54 2048 24 6.95648e+06 405319 949917. 3286.91 4.30 0.220353 0.193683 29506 232905 -1 1646 23 1577 2111 155055 38389 4.14962 4.14962 -142.145 -4.14962 0 0 1.17392e+06 4061.99 0.04 0.06 0.14 -1 -1 0.04 0.0246995 0.0221709 84 90 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_120.v common 4.94 vpr 64.66 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30212 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 32 32 376 318 1 154 75 17 17 289 -1 unnamed_device 25.6 MiB 1.68 1894 675 12083 5157 6591 335 64.7 MiB 0.06 0.00 3.54619 2.94085 -113.533 -2.94085 2.94085 0.25 0.000336191 0.000306852 0.0277439 0.0254059 -1 -1 -1 -1 48 1588 22 6.95648e+06 159232 865456. 2994.66 1.84 0.165957 0.145157 28354 207349 -1 1301 20 1327 1806 124593 28920 3.01532 3.01532 -115.899 -3.01532 0 0 1.05005e+06 3633.38 0.04 0.04 0.11 -1 -1 0.04 0.0165622 0.0148394 62 96 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_121.v common 3.44 vpr 64.68 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30156 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 360 293 1 172 90 17 17 289 -1 unnamed_device 25.3 MiB 0.48 1853 1069 14562 4604 8437 1521 64.7 MiB 0.07 0.00 3.91173 3.53583 -120.704 -3.53583 3.53583 0.25 0.000335501 0.000306033 0.0322582 0.0297118 -1 -1 -1 -1 40 2375 24 6.95648e+06 376368 706193. 2443.58 1.49 0.158921 0.139899 26914 176310 -1 2117 23 1326 2047 179309 38171 3.29717 3.29717 -119.13 -3.29717 0 0 926341. 3205.33 0.05 0.08 0.11 -1 -1 0.05 0.0312325 0.0278867 78 60 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_122.v common 3.18 vpr 65.48 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30192 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67056 32 32 396 299 1 227 83 17 17 289 -1 unnamed_device 25.6 MiB 0.86 2452 1278 10883 3044 6597 1242 65.5 MiB 0.07 0.00 6.40588 5.67799 -169.514 -5.67799 5.67799 0.26 0.000375871 0.000344229 0.0265442 0.0244031 -1 -1 -1 -1 42 3157 23 6.95648e+06 275038 744469. 2576.02 0.83 0.0987754 0.0878873 27202 183097 -1 2714 35 2694 3788 394527 125732 4.9392 4.9392 -169.567 -4.9392 0 0 949917. 3286.91 0.03 0.11 0.10 -1 -1 0.03 0.028617 0.0255556 95 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_123.v common 4.02 vpr 64.68 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29564 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 30 32 224 207 1 132 75 17 17 289 -1 unnamed_device 25.6 MiB 0.54 1627 598 12241 5372 6458 411 64.7 MiB 0.05 0.00 2.90706 2.40586 -87.9482 -2.40586 2.40586 0.25 0.000233649 0.000212956 0.0201236 0.0184129 -1 -1 -1 -1 40 1508 30 6.95648e+06 188184 706193. 2443.58 2.06 0.157661 0.137737 26914 176310 -1 1331 20 901 1144 111930 30811 2.88623 2.88623 -98.6954 -2.88623 0 0 926341. 3205.33 0.03 0.04 0.11 -1 -1 0.03 0.0123386 0.0110566 51 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_124.v common 4.72 vpr 64.19 MiB -1 -1 0.19 17676 1 0.03 -1 -1 30184 -1 -1 12 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 30 32 286 239 1 137 74 17 17 289 -1 unnamed_device 25.1 MiB 0.91 1634 584 10304 2805 7001 498 64.2 MiB 0.04 0.00 3.45258 3.27614 -105.411 -3.27614 3.27614 0.25 0.000284959 0.000261096 0.0205025 0.0187956 -1 -1 -1 -1 34 1944 38 6.95648e+06 173708 618332. 2139.56 2.32 0.143174 0.124606 25762 151098 -1 1413 22 1179 1705 141397 34783 3.09482 3.09482 -117.715 -3.09482 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0150785 0.0134656 56 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_125.v common 3.29 vpr 65.05 MiB -1 -1 0.11 18064 1 0.02 -1 -1 29768 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 296 247 1 152 83 17 17 289 -1 unnamed_device 25.2 MiB 0.11 1728 922 8723 2565 5365 793 65.1 MiB 0.04 0.00 3.55445 2.9873 -113.256 -2.9873 2.9873 0.25 0.000301223 0.00027349 0.0160763 0.0147241 -1 -1 -1 -1 40 2197 27 6.95648e+06 275038 706193. 2443.58 1.75 0.156743 0.136892 26914 176310 -1 2042 23 1349 2303 218886 48209 3.19827 3.19827 -121.7 -3.19827 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0160692 0.0143372 65 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_126.v common 2.84 vpr 64.26 MiB -1 -1 0.12 18060 1 0.02 -1 -1 29828 -1 -1 18 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 25 32 216 194 1 119 75 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1353 690 8449 3120 3872 1457 64.3 MiB 0.03 0.00 3.58218 3.24133 -80.823 -3.24133 3.24133 0.25 0.000224742 0.000205297 0.0131913 0.0120881 -1 -1 -1 -1 32 1648 24 6.95648e+06 260562 586450. 2029.24 1.34 0.123269 0.106366 25474 144626 -1 1400 20 849 1332 99865 22135 2.72602 2.72602 -85.395 -2.72602 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0111245 0.00989695 51 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_127.v common 6.84 vpr 64.71 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29796 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 32 32 376 307 1 179 78 17 17 289 -1 unnamed_device 26.0 MiB 0.46 1982 1168 8876 2502 5267 1107 64.7 MiB 0.05 0.00 4.59945 3.81054 -129.805 -3.81054 3.81054 0.25 0.000344787 0.000315324 0.0205257 0.0187772 -1 -1 -1 -1 40 2820 23 6.95648e+06 202660 706193. 2443.58 4.95 0.191278 0.167763 26914 176310 -1 2463 25 1559 2688 247418 60274 4.07062 4.07062 -139.096 -4.07062 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0204429 0.0182595 75 72 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_128.v common 3.87 vpr 65.58 MiB -1 -1 0.20 18440 1 0.03 -1 -1 29772 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67156 31 32 409 331 1 183 92 17 17 289 -1 unnamed_device 25.6 MiB 0.39 1880 934 14582 5336 7343 1903 65.6 MiB 0.07 0.00 3.75413 3.54189 -123.861 -3.54189 3.54189 0.25 0.000370518 0.000338041 0.0281666 0.0258067 -1 -1 -1 -1 40 2135 23 6.95648e+06 419795 706193. 2443.58 1.67 0.181804 0.159938 26914 176310 -1 1941 23 1958 2686 194478 42954 3.22012 3.22012 -126.025 -3.22012 0 0 926341. 3205.33 0.05 0.09 0.17 -1 -1 0.05 0.0361223 0.0324491 88 90 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_001.v common 3.61 vpr 65.28 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30180 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66844 32 32 354 285 1 206 82 17 17 289 -1 unnamed_device 25.2 MiB 0.57 2477 1104 5956 1234 4454 268 65.3 MiB 0.04 0.00 5.9831 5.0213 -150.404 -5.0213 5.0213 0.25 0.000339429 0.000311214 0.0135732 0.0124946 -1 -1 -1 -1 40 2746 30 6.99608e+06 264882 706193. 2443.58 1.64 0.140449 0.122546 26914 176310 -1 2503 21 1812 2826 219665 47612 4.45375 4.45375 -154.395 -4.45375 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0178176 0.0160479 89 50 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_002.v common 7.00 vpr 64.60 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29756 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 30 32 363 293 1 224 85 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2539 1213 13663 4903 6549 2211 64.6 MiB 0.08 0.00 5.97457 4.74455 -148.167 -4.74455 4.74455 0.25 0.000819983 0.00075946 0.0339081 0.0313222 -1 -1 -1 -1 38 2904 29 6.99608e+06 338461 678818. 2348.85 5.25 0.188274 0.165386 26626 170182 -1 2475 23 2204 3166 262316 53855 4.3292 4.3292 -149.244 -4.3292 0 0 902133. 3121.57 0.03 0.07 0.10 -1 -1 0.03 0.0216333 0.0194628 99 63 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_003.v common 6.20 vpr 64.43 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29800 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 32 32 299 247 1 182 82 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2357 1078 12186 3608 6974 1604 64.4 MiB 0.07 0.00 4.53839 3.58799 -116.676 -3.58799 3.58799 0.25 0.000295115 0.00027033 0.0302567 0.0279761 -1 -1 -1 -1 36 2482 30 6.99608e+06 264882 648988. 2245.63 4.46 0.190584 0.167465 26050 158493 -1 2238 23 1374 1912 157043 33421 4.08876 4.08876 -130.004 -4.08876 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0161449 0.0144234 75 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_004.v common 2.49 vpr 63.83 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29748 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65364 29 32 308 248 1 182 80 17 17 289 -1 unnamed_device 24.9 MiB 0.33 2573 764 13496 3536 9305 655 63.8 MiB 0.09 0.00 5.42531 4.05748 -115.939 -4.05748 4.05748 0.24 0.000828626 0.000781172 0.0376447 0.0347493 -1 -1 -1 -1 36 2604 27 6.99608e+06 279598 648988. 2245.63 0.77 0.0932788 0.0829728 26050 158493 -1 1796 20 1431 2220 152925 38511 3.99626 3.99626 -126.688 -3.99626 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.015111 0.0135488 79 31 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_005.v common 3.59 vpr 64.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29848 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 336 268 1 193 80 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2057 952 12464 3721 7118 1625 64.7 MiB 0.06 0.00 5.56057 4.88167 -146.243 -4.88167 4.88167 0.25 0.000331052 0.00030369 0.0256676 0.0235046 -1 -1 -1 -1 44 2790 26 6.99608e+06 235451 787024. 2723.27 1.89 0.151492 0.133144 27778 195446 -1 2240 23 1634 2747 222001 48807 4.40571 4.40571 -143.589 -4.40571 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0197017 0.0177011 86 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_006.v common 2.89 vpr 65.35 MiB -1 -1 0.12 18440 1 0.03 -1 -1 29780 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66916 32 32 366 295 1 222 88 17 17 289 -1 unnamed_device 25.6 MiB 0.24 2506 1118 13933 5613 7680 640 65.3 MiB 0.07 0.00 4.26916 3.42564 -123.507 -3.42564 3.42564 0.25 0.000345196 0.00031104 0.0287072 0.0263298 -1 -1 -1 -1 38 3421 45 6.99608e+06 353176 678818. 2348.85 1.26 0.112321 0.0993323 26626 170182 -1 2462 24 1784 3007 215704 50106 3.76796 3.76796 -132.934 -3.76796 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0195075 0.0174687 99 58 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_007.v common 2.41 vpr 64.68 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30136 -1 -1 18 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 27 32 259 221 1 152 77 17 17 289 -1 unnamed_device 25.2 MiB 0.25 1709 563 9857 3638 4045 2174 64.7 MiB 0.05 0.00 4.67622 3.83492 -100.928 -3.83492 3.83492 0.26 0.000310689 0.000287664 0.022248 0.0206329 -1 -1 -1 -1 38 1948 27 6.99608e+06 264882 678818. 2348.85 0.78 0.0780478 0.0687188 26626 170182 -1 1392 30 1579 2262 176346 42562 3.41652 3.41652 -110.525 -3.41652 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0218746 0.0192852 65 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_008.v common 2.40 vpr 64.66 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29804 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 24.9 MiB 0.11 1776 919 11547 2651 7976 920 64.7 MiB 0.05 0.00 3.1255 2.7565 -95.0074 -2.7565 2.7565 0.26 0.000293209 0.000264748 0.0180705 0.0165422 -1 -1 -1 -1 36 2309 50 6.99608e+06 397324 648988. 2245.63 0.94 0.103789 0.0914604 26050 158493 -1 1978 22 1218 2212 171223 38751 2.65381 2.65381 -102.167 -2.65381 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0148703 0.0132452 69 4 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_009.v common 3.28 vpr 65.09 MiB -1 -1 0.15 18064 1 0.03 -1 -1 29792 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66652 31 32 317 271 1 204 81 17 17 289 -1 unnamed_device 25.3 MiB 0.23 2338 1082 14256 5263 7162 1831 65.1 MiB 0.07 0.00 4.24759 3.13884 -116.913 -3.13884 3.13884 0.29 0.000304151 0.000278446 0.0274291 0.0251884 -1 -1 -1 -1 40 2502 31 6.99608e+06 264882 706193. 2443.58 1.59 0.13523 0.118366 26914 176310 -1 2233 22 1689 2280 192202 40085 3.05882 3.05882 -122.616 -3.05882 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0162855 0.014578 83 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_010.v common 4.75 vpr 64.41 MiB -1 -1 0.14 17676 1 0.03 -1 -1 29648 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65960 32 32 298 248 1 181 79 17 17 289 -1 unnamed_device 25.3 MiB 0.24 1862 1015 12247 3678 6923 1646 64.4 MiB 0.07 0.00 3.99837 3.64037 -128.737 -3.64037 3.64037 0.25 0.000447112 0.000420921 0.0321216 0.0299558 -1 -1 -1 -1 34 2533 32 6.99608e+06 220735 618332. 2139.56 3.11 0.172253 0.152194 25762 151098 -1 2146 19 1516 1997 164767 35720 3.09382 3.09382 -128.206 -3.09382 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0141017 0.0126303 72 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_011.v common 3.34 vpr 64.45 MiB -1 -1 0.16 18060 1 0.03 -1 -1 29772 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 30 32 303 262 1 186 79 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2266 960 13599 4745 6819 2035 64.4 MiB 0.09 0.00 4.98263 3.86818 -125.247 -3.86818 3.86818 0.28 0.000424381 0.00038739 0.0373622 0.0341447 -1 -1 -1 -1 36 2348 40 6.99608e+06 250167 648988. 2245.63 1.51 0.148585 0.130262 26050 158493 -1 2064 21 1422 1950 168607 36652 3.59731 3.59731 -129.651 -3.59731 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0172651 0.0154663 79 63 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_012.v common 2.79 vpr 64.71 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29692 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 32 32 276 237 1 165 78 17 17 289 -1 unnamed_device 24.9 MiB 0.24 1950 725 8212 1860 5677 675 64.7 MiB 0.05 0.00 4.10243 3.37048 -107.801 -3.37048 3.37048 0.25 0.000669283 0.000624933 0.0224593 0.0208535 -1 -1 -1 -1 38 2443 48 6.99608e+06 206020 678818. 2348.85 1.17 0.109588 0.0965962 26626 170182 -1 1781 21 1241 1639 121264 31618 3.06712 3.06712 -115.463 -3.06712 0 0 902133. 3121.57 0.03 0.04 0.10 -1 -1 0.03 0.0151789 0.0135417 65 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_013.v common 3.29 vpr 64.48 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29624 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 344 272 1 201 82 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2682 954 13076 5089 6303 1684 64.5 MiB 0.07 0.00 4.83632 3.86972 -128.357 -3.86972 3.86972 0.25 0.000326098 0.000297786 0.0290014 0.0266927 -1 -1 -1 -1 42 2795 25 6.99608e+06 264882 744469. 2576.02 1.57 0.143204 0.125742 27202 183097 -1 2199 24 1772 2664 231395 52184 3.34801 3.34801 -126.15 -3.34801 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0187747 0.0168077 85 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_014.v common 3.13 vpr 65.34 MiB -1 -1 0.20 18060 1 0.03 -1 -1 29688 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66908 32 32 363 295 1 228 85 17 17 289 -1 unnamed_device 25.2 MiB 0.32 2692 1244 14407 4661 7812 1934 65.3 MiB 0.08 0.00 5.90964 4.79277 -149.984 -4.79277 4.79277 0.27 0.000337196 0.000308944 0.0320247 0.0294721 -1 -1 -1 -1 40 2811 20 6.99608e+06 309029 706193. 2443.58 1.17 0.123832 0.110017 26914 176310 -1 2538 20 1946 2619 212273 44432 4.38451 4.38451 -153.65 -4.38451 0 0 926341. 3205.33 0.04 0.05 0.14 -1 -1 0.04 0.017113 0.0153806 96 61 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_015.v common 2.96 vpr 64.60 MiB -1 -1 0.11 18296 1 0.03 -1 -1 30276 -1 -1 17 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 29 32 248 215 1 150 78 17 17 289 -1 unnamed_device 24.9 MiB 0.31 1740 893 9706 2711 5534 1461 64.6 MiB 0.05 0.00 3.47743 2.91415 -94.4077 -2.91415 2.91415 0.25 0.000254157 0.000232628 0.020588 0.018958 -1 -1 -1 -1 32 2036 22 6.99608e+06 250167 586450. 2029.24 1.29 0.106588 0.0929905 25474 144626 -1 1646 20 1019 1427 101641 22220 2.71507 2.71507 -98.7671 -2.71507 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0128596 0.0114275 62 27 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_016.v common 2.63 vpr 65.34 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29784 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66912 32 32 370 297 1 219 83 17 17 289 -1 unnamed_device 25.7 MiB 0.35 2362 1073 15563 6532 7835 1196 65.3 MiB 0.08 0.00 4.16944 3.57294 -125.244 -3.57294 3.57294 0.24 0.000347667 0.000317742 0.0318598 0.0291397 -1 -1 -1 -1 38 2963 48 6.99608e+06 279598 678818. 2348.85 0.89 0.110101 0.0973561 26626 170182 -1 2204 21 1887 2913 199419 44516 3.57851 3.57851 -131.037 -3.57851 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0176817 0.0158624 98 58 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_017.v common 3.04 vpr 64.55 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29840 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 32 32 338 269 1 198 81 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2635 1084 14431 4177 8907 1347 64.5 MiB 0.08 0.00 4.64181 3.75386 -123.111 -3.75386 3.75386 0.25 0.000409682 0.000377196 0.036391 0.033598 -1 -1 -1 -1 36 2769 26 6.99608e+06 250167 648988. 2245.63 1.27 0.155204 0.138893 26050 158493 -1 2414 20 1701 2429 219821 56511 3.11862 3.11862 -126.555 -3.11862 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0208099 0.0188496 83 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_018.v common 3.89 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29584 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66612 32 32 323 276 1 210 81 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2734 1198 13031 4384 6941 1706 65.1 MiB 0.06 0.00 4.46501 3.1116 -120.136 -3.1116 3.1116 0.27 0.000301401 0.000276115 0.0248043 0.0226518 -1 -1 -1 -1 34 2850 47 6.99608e+06 250167 618332. 2139.56 2.24 0.158245 0.138253 25762 151098 -1 2471 21 1733 2316 195072 42876 3.22062 3.22062 -126.364 -3.22062 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0162061 0.0145209 84 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_019.v common 2.76 vpr 64.13 MiB -1 -1 0.13 18060 1 0.02 -1 -1 29784 -1 -1 14 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 30 32 222 206 1 135 76 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1543 727 10476 3465 5449 1562 64.1 MiB 0.04 0.00 2.68936 2.31346 -87.3083 -2.31346 2.31346 0.25 0.000244077 0.000223557 0.0172966 0.0158483 -1 -1 -1 -1 32 1548 26 6.99608e+06 206020 586450. 2029.24 1.21 0.103854 0.089959 25474 144626 -1 1415 22 733 828 76674 17191 2.18948 2.18948 -92.4069 -2.18948 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0121979 0.0108198 52 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_020.v common 3.85 vpr 63.91 MiB -1 -1 0.12 17712 1 0.03 -1 -1 29792 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65448 31 32 291 243 1 172 78 17 17 289 -1 unnamed_device 24.5 MiB 0.72 2133 838 8046 1881 5711 454 63.9 MiB 0.04 0.00 5.43629 4.06642 -132.88 -4.06642 4.06642 0.35 0.000286595 0.000262175 0.0155859 0.0143043 -1 -1 -1 -1 34 2585 50 6.99608e+06 220735 618332. 2139.56 1.53 0.13142 0.114418 25762 151098 -1 1987 22 1400 2056 153586 36992 3.64846 3.64846 -134.265 -3.64846 0 0 787024. 2723.27 0.04 0.07 0.13 -1 -1 0.04 0.0259421 0.0231603 70 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_021.v common 3.79 vpr 64.61 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30348 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 32 32 342 271 1 200 92 17 17 289 -1 unnamed_device 25.2 MiB 0.31 2545 898 17687 6355 8833 2499 64.6 MiB 0.08 0.00 5.23013 4.09659 -137.139 -4.09659 4.09659 0.24 0.000327188 0.000299437 0.0312595 0.0286912 -1 -1 -1 -1 38 2615 31 6.99608e+06 412039 678818. 2348.85 2.03 0.169548 0.152529 26626 170182 -1 1982 23 1854 2804 201893 47345 4.6472 4.6472 -149.149 -4.6472 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0179156 0.0160457 92 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_022.v common 3.69 vpr 64.76 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30104 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 32 32 372 300 1 225 84 17 17 289 -1 unnamed_device 25.2 MiB 0.37 2481 1280 13260 3957 7480 1823 64.8 MiB 0.08 0.00 5.12435 4.27615 -135.126 -4.27615 4.27615 0.26 0.000351019 0.000321597 0.0324092 0.0299401 -1 -1 -1 -1 44 3006 22 6.99608e+06 294314 787024. 2723.27 1.86 0.161059 0.14195 27778 195446 -1 2489 20 1768 2665 213136 44814 4.30622 4.30622 -143.652 -4.30622 0 0 997811. 3452.63 0.04 0.05 0.10 -1 -1 0.04 0.0175618 0.0158387 97 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_023.v common 2.37 vpr 64.02 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30140 -1 -1 17 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65556 26 32 190 182 1 123 75 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1496 591 9871 3440 4773 1658 64.0 MiB 0.03 0.00 3.5328 2.5304 -72.9745 -2.5304 2.5304 0.27 0.000201051 0.000183539 0.0137083 0.0125318 -1 -1 -1 -1 30 1434 20 6.99608e+06 250167 556674. 1926.21 0.88 0.0661549 0.0573686 25186 138497 -1 1178 19 742 883 70756 15921 2.30998 2.30998 -75.3621 -2.30998 0 0 706193. 2443.58 0.03 0.03 0.08 -1 -1 0.03 0.0122099 0.0107687 51 30 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_024.v common 6.67 vpr 64.61 MiB -1 -1 0.21 17672 1 0.03 -1 -1 30252 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 32 32 285 227 1 160 81 17 17 289 -1 unnamed_device 25.2 MiB 0.35 1881 1025 10231 3161 5849 1221 64.6 MiB 0.07 0.00 5.10855 4.37465 -123.584 -4.37465 4.37465 0.46 0.000291795 0.000266598 0.0320495 0.0296815 -1 -1 -1 -1 34 2652 24 6.99608e+06 250167 618332. 2139.56 4.51 0.160997 0.141917 25762 151098 -1 2217 22 1494 2515 241172 49180 3.78976 3.78976 -130.242 -3.78976 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0154296 0.0137911 66 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_025.v common 1.95 vpr 64.21 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29736 -1 -1 10 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65752 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1439 560 9374 3843 5323 208 64.2 MiB 0.07 0.00 2.54695 2.03911 -69.5392 -2.03911 2.03911 0.28 0.000517782 0.00047721 0.0311304 0.0286357 -1 -1 -1 -1 32 1253 27 6.99608e+06 147157 586450. 2029.24 0.57 0.0745683 0.0659302 25474 144626 -1 1084 17 554 676 57342 13979 1.94502 1.94502 -76.2104 -1.94502 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00875001 0.00782223 43 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_026.v common 3.04 vpr 64.42 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30180 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 32 32 300 245 1 176 79 17 17 289 -1 unnamed_device 24.9 MiB 0.75 2120 991 10050 3166 5397 1487 64.4 MiB 0.05 0.00 5.61451 4.50471 -128.436 -4.50471 4.50471 0.24 0.000301009 0.000274742 0.0212028 0.0195085 -1 -1 -1 -1 34 2653 41 6.99608e+06 220735 618332. 2139.56 0.94 0.100568 0.0883959 25762 151098 -1 2097 19 1258 1913 140387 31529 3.94702 3.94702 -130.561 -3.94702 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0143834 0.0129277 73 24 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_027.v common 3.06 vpr 64.92 MiB -1 -1 0.10 17672 1 0.03 -1 -1 29956 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 25.2 MiB 0.10 1823 770 8047 1794 5817 436 64.9 MiB 0.04 0.00 3.17834 2.84195 -96.8757 -2.84195 2.84195 0.25 0.000307522 0.000280239 0.0139893 0.0127846 -1 -1 -1 -1 38 2286 24 6.99608e+06 397324 678818. 2348.85 1.45 0.120098 0.104798 26626 170182 -1 1846 20 1304 2290 140400 35421 2.96851 2.96851 -105.541 -2.96851 0 0 902133. 3121.57 0.05 0.07 0.16 -1 -1 0.05 0.0249902 0.0224145 77 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_028.v common 7.89 vpr 65.12 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29768 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 32 32 338 277 1 204 84 17 17 289 -1 unnamed_device 25.2 MiB 0.46 2724 1022 8136 1841 6065 230 65.1 MiB 0.05 0.00 5.37647 4.14137 -127.473 -4.14137 4.14137 0.36 0.000375091 0.000347255 0.0168054 0.0153915 -1 -1 -1 -1 38 3057 31 6.99608e+06 294314 678818. 2348.85 5.89 0.19333 0.169565 26626 170182 -1 2256 20 1754 2596 181852 41367 3.87782 3.87782 -133.503 -3.87782 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0166011 0.0149371 88 50 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_029.v common 2.51 vpr 64.73 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29804 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 32 32 284 241 1 168 78 17 17 289 -1 unnamed_device 24.9 MiB 0.51 1906 924 9872 3709 5164 999 64.7 MiB 0.05 0.00 3.74453 3.11176 -114.352 -3.11176 3.11176 0.25 0.000287639 0.000263831 0.0210304 0.0193592 -1 -1 -1 -1 34 2359 22 6.99608e+06 206020 618332. 2139.56 0.67 0.0852771 0.0749924 25762 151098 -1 2040 23 1396 2031 159719 34924 3.14212 3.14212 -122.708 -3.14212 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0155618 0.0138549 68 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_030.v common 3.33 vpr 63.88 MiB -1 -1 0.18 17676 1 0.02 -1 -1 29840 -1 -1 16 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65416 30 32 262 227 1 160 78 17 17 289 -1 unnamed_device 24.9 MiB 0.18 1816 788 8212 1940 5916 356 63.9 MiB 0.04 0.00 4.36766 3.76823 -111.393 -3.76823 3.76823 0.24 0.000268796 0.000246457 0.014825 0.0136157 -1 -1 -1 -1 36 2251 27 6.99608e+06 235451 648988. 2245.63 1.49 0.114612 0.0991656 26050 158493 -1 1776 64 1632 2908 490429 252067 3.39226 3.39226 -111.31 -3.39226 0 0 828058. 2865.25 0.03 0.20 0.15 -1 -1 0.03 0.0388827 0.0341788 65 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_031.v common 2.37 vpr 64.65 MiB -1 -1 0.12 17472 1 0.02 -1 -1 29824 -1 -1 17 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 28 32 260 223 1 152 77 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1683 804 11650 4924 6170 556 64.7 MiB 0.05 0.00 4.26016 3.78259 -116.363 -3.78259 3.78259 0.25 0.000265538 0.000243257 0.0203419 0.0186211 -1 -1 -1 -1 40 1766 19 6.99608e+06 250167 706193. 2443.58 0.64 0.0678464 0.0597412 26914 176310 -1 1619 17 889 1497 109998 24855 3.37506 3.37506 -112.039 -3.37506 0 0 926341. 3205.33 0.05 0.05 0.17 -1 -1 0.05 0.0182635 0.0163129 69 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_032.v common 2.30 vpr 64.55 MiB -1 -1 0.13 17680 1 0.03 -1 -1 29808 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 24.9 MiB 0.10 1562 788 6108 1413 4387 308 64.5 MiB 0.03 0.00 3.55103 3.30043 -111.23 -3.30043 3.30043 0.25 0.00031688 0.00027615 0.0131315 0.0120434 -1 -1 -1 -1 36 2159 28 6.99608e+06 191304 648988. 2245.63 0.80 0.0795214 0.0697774 26050 158493 -1 1866 20 1176 1858 150356 33149 3.08997 3.08997 -117.255 -3.08997 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0133256 0.0119122 59 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_033.v common 2.91 vpr 64.66 MiB -1 -1 0.11 17676 1 0.03 -1 -1 30288 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 31 32 271 231 1 164 78 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1729 914 6552 1539 4793 220 64.7 MiB 0.03 0.00 3.64733 3.26948 -110.36 -3.26948 3.26948 0.24 0.000274842 0.000251498 0.0124484 0.0114395 -1 -1 -1 -1 38 2086 22 6.99608e+06 220735 678818. 2348.85 1.41 0.113843 0.0989225 26626 170182 -1 1766 19 1123 1539 113480 24974 2.95762 2.95762 -107.253 -2.95762 0 0 902133. 3121.57 0.03 0.03 0.09 -1 -1 0.03 0.0130744 0.0117173 65 30 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_034.v common 3.02 vpr 65.02 MiB -1 -1 0.23 18060 1 0.03 -1 -1 30260 -1 -1 18 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 29 32 291 250 1 177 79 17 17 289 -1 unnamed_device 25.1 MiB 0.30 1970 870 12923 5432 7041 450 65.0 MiB 0.06 0.00 3.19185 3.0305 -101.634 -3.0305 3.0305 0.25 0.0002811 0.000256228 0.026476 0.024338 -1 -1 -1 -1 34 2394 43 6.99608e+06 264882 618332. 2139.56 1.28 0.123062 0.107742 25762 151098 -1 1866 20 1335 1783 151180 34619 2.90282 2.90282 -102.948 -2.90282 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0142251 0.0127067 75 54 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_035.v common 5.13 vpr 65.27 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30252 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66840 32 32 367 282 1 214 85 17 17 289 -1 unnamed_device 25.2 MiB 0.22 2522 1172 14035 4232 7971 1832 65.3 MiB 0.17 0.00 4.99868 4.08568 -124.995 -4.08568 4.08568 0.27 0.000960124 0.000884277 0.076292 0.0708771 -1 -1 -1 -1 36 3145 22 6.99608e+06 309029 648988. 2245.63 3.32 0.224409 0.200545 26050 158493 -1 2479 23 1718 2753 202121 45212 3.89121 3.89121 -131.794 -3.89121 0 0 828058. 2865.25 0.03 0.06 0.14 -1 -1 0.03 0.020053 0.0180574 91 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_036.v common 2.64 vpr 65.45 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30308 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67016 32 32 391 311 1 244 85 17 17 289 -1 unnamed_device 25.6 MiB 0.27 3114 1259 14779 4738 7682 2359 65.4 MiB 0.18 0.00 5.22142 3.95648 -143.346 -3.95648 3.95648 0.25 0.000988432 0.000921433 0.0827453 0.0770468 -1 -1 -1 -1 38 3454 34 6.99608e+06 309029 678818. 2348.85 0.82 0.15522 0.140296 26626 170182 -1 2633 24 2431 3409 267181 56072 3.57966 3.57966 -146.352 -3.57966 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0199938 0.017896 103 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_037.v common 3.43 vpr 64.29 MiB -1 -1 0.12 18444 1 0.02 -1 -1 29780 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 31 32 279 237 1 161 77 17 17 289 -1 unnamed_device 24.9 MiB 0.30 1951 789 11976 3042 8492 442 64.3 MiB 0.06 0.00 4.50867 3.52417 -108.752 -3.52417 3.52417 0.26 0.000669405 0.0006251 0.0285923 0.0264143 -1 -1 -1 -1 36 2241 46 6.99608e+06 206020 648988. 2245.63 1.65 0.131689 0.116324 26050 158493 -1 1842 19 1371 2033 165078 39629 3.27322 3.27322 -114.522 -3.27322 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0134904 0.0120612 67 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_038.v common 2.81 vpr 65.36 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29968 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66932 31 32 370 297 1 227 85 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2471 1139 11059 3848 5463 1748 65.4 MiB 0.06 0.00 3.93715 3.60485 -125.992 -3.60485 3.60485 0.24 0.000340222 0.000310302 0.0228227 0.0209047 -1 -1 -1 -1 38 3226 39 6.99608e+06 323745 678818. 2348.85 1.11 0.101109 0.0890899 26626 170182 -1 2488 20 1747 2530 216446 46223 3.50736 3.50736 -133.253 -3.50736 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0172056 0.0154889 98 61 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_039.v common 7.93 vpr 65.27 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30176 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66836 31 32 377 302 1 235 85 17 17 289 -1 unnamed_device 25.6 MiB 0.26 3086 1318 10687 2982 7130 575 65.3 MiB 0.06 0.00 6.44118 5.00244 -160.349 -5.00244 5.00244 0.25 0.000364276 0.000335521 0.022151 0.0203222 -1 -1 -1 -1 38 3194 28 6.99608e+06 323745 678818. 2348.85 6.29 0.176922 0.15499 26626 170182 -1 2740 19 2162 3082 228411 49616 4.82274 4.82274 -169.003 -4.82274 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0170405 0.0153752 101 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_040.v common 3.46 vpr 65.41 MiB -1 -1 0.13 18048 1 0.03 -1 -1 29768 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66980 31 32 383 305 1 232 84 17 17 289 -1 unnamed_device 25.6 MiB 0.68 2998 1211 13809 5832 7618 359 65.4 MiB 0.09 0.00 6.73307 4.94768 -163.914 -4.94768 4.94768 0.26 0.000351527 0.000321331 0.040439 0.0373557 -1 -1 -1 -1 38 3344 24 6.99608e+06 309029 678818. 2348.85 1.31 0.133483 0.119387 26626 170182 -1 2611 24 2258 3370 271018 68504 4.84 4.84 -173.04 -4.84 0 0 902133. 3121.57 0.03 0.07 0.09 -1 -1 0.03 0.0207315 0.0186332 101 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_041.v common 2.96 vpr 64.58 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29740 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66132 31 32 352 285 1 214 82 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2321 1209 11118 3541 5840 1737 64.6 MiB 0.06 0.00 4.10443 3.47793 -120.035 -3.47793 3.47793 0.25 0.000339383 0.000311035 0.0228619 0.0209898 -1 -1 -1 -1 38 3104 43 6.99608e+06 279598 678818. 2348.85 1.16 0.105384 0.0934951 26626 170182 -1 2395 22 1987 2942 229567 48017 3.36022 3.36022 -127.979 -3.36022 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0181155 0.0162911 90 55 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_042.v common 2.91 vpr 64.39 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29748 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 291 242 1 173 82 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2257 1074 10584 2543 6589 1452 64.4 MiB 0.05 0.00 4.8427 4.02108 -120.371 -4.02108 4.02108 0.24 0.000295137 0.000271181 0.0192343 0.0176373 -1 -1 -1 -1 34 2686 27 6.99608e+06 264882 618332. 2139.56 1.31 0.0984721 0.0865377 25762 151098 -1 2408 21 1352 2027 180812 38694 3.83326 3.83326 -129.933 -3.83326 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0148508 0.0132692 73 27 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_043.v common 8.73 vpr 65.75 MiB -1 -1 0.13 18060 1 0.04 -1 -1 29816 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67328 32 32 457 356 1 282 90 17 17 289 -1 unnamed_device 26.4 MiB 0.34 3052 1509 12753 3455 8062 1236 65.8 MiB 0.08 0.00 6.26717 5.14656 -172.851 -5.14656 5.14656 0.24 0.000438438 0.000399665 0.0312348 0.0287359 -1 -1 -1 -1 40 3984 25 6.99608e+06 382608 706193. 2443.58 6.88 0.245438 0.215822 26914 176310 -1 3415 22 2474 3639 272449 59278 5.07634 5.07634 -175.218 -5.07634 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0225554 0.0203049 127 87 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_044.v common 2.27 vpr 64.58 MiB -1 -1 0.14 17672 1 0.03 -1 -1 29648 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66132 31 32 261 225 1 158 77 17 17 289 -1 unnamed_device 24.8 MiB 0.30 1593 899 7412 1777 4948 687 64.6 MiB 0.04 0.00 3.6621 3.0623 -104.163 -3.0623 3.0623 0.25 0.000597636 0.000555705 0.0176173 0.0163332 -1 -1 -1 -1 32 2111 32 6.99608e+06 206020 586450. 2029.24 0.60 0.0699195 0.0614205 25474 144626 -1 1852 20 1077 1450 120781 26826 3.31142 3.31142 -117.221 -3.31142 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0140206 0.0125371 65 28 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_045.v common 2.66 vpr 65.18 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30228 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66748 31 32 337 267 1 199 81 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2145 1115 11106 4094 5276 1736 65.2 MiB 0.06 0.00 4.77304 4.27184 -135.826 -4.27184 4.27184 0.25 0.000324833 0.000296411 0.0225737 0.0206979 -1 -1 -1 -1 44 2697 25 6.99608e+06 264882 787024. 2723.27 1.00 0.101064 0.0892623 27778 195446 -1 2120 21 1262 1981 149067 31664 4.02291 4.02291 -134.519 -4.02291 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0168417 0.0151147 82 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_046.v common 3.33 vpr 65.23 MiB -1 -1 0.12 18440 1 0.04 -1 -1 30020 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66800 32 32 349 284 1 213 84 17 17 289 -1 unnamed_device 25.2 MiB 0.34 2736 1076 15273 5235 7717 2321 65.2 MiB 0.08 0.00 4.55139 3.66953 -119.489 -3.66953 3.66953 0.24 0.000334283 0.000306338 0.0300208 0.0275113 -1 -1 -1 -1 42 2891 20 6.99608e+06 294314 744469. 2576.02 1.52 0.137871 0.120656 27202 183097 -1 2348 19 1511 2377 177851 40110 3.63266 3.63266 -126.058 -3.63266 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0163287 0.0147117 90 53 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_047.v common 7.22 vpr 64.62 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30168 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66176 32 32 291 230 1 160 83 17 17 289 -1 unnamed_device 24.9 MiB 0.20 1772 1011 10343 3054 6149 1140 64.6 MiB 0.09 0.00 4.52137 4.01417 -123.961 -4.01417 4.01417 0.29 0.000533086 0.000484878 0.0332193 0.0304525 -1 -1 -1 -1 36 2627 27 6.99608e+06 279598 648988. 2245.63 5.58 0.170154 0.149886 26050 158493 -1 2246 27 1497 2733 298227 86162 3.91606 3.91606 -131.254 -3.91606 0 0 828058. 2865.25 0.03 0.08 0.08 -1 -1 0.03 0.0183437 0.0162826 70 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_048.v common 3.80 vpr 65.15 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29736 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66716 32 32 353 287 1 210 83 17 17 289 -1 unnamed_device 25.8 MiB 0.48 2562 1041 14123 5669 6794 1660 65.2 MiB 0.09 0.00 4.62756 3.95722 -121.021 -3.95722 3.95722 0.25 0.000523358 0.000494676 0.0370832 0.0342115 -1 -1 -1 -1 38 3059 28 6.99608e+06 279598 678818. 2348.85 1.73 0.173229 0.152378 26626 170182 -1 2276 22 1550 2190 162466 35607 3.46336 3.46336 -123.742 -3.46336 0 0 902133. 3121.57 0.05 0.05 0.14 -1 -1 0.05 0.0177621 0.0159143 91 55 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_049.v common 4.27 vpr 65.19 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30164 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66756 32 32 361 291 1 214 85 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2404 1228 14407 4938 7065 2404 65.2 MiB 0.08 0.00 4.47599 3.61653 -127.814 -3.61653 3.61653 0.26 0.000342994 0.000313604 0.0323871 0.0296708 -1 -1 -1 -1 34 3482 45 6.99608e+06 309029 618332. 2139.56 2.58 0.169262 0.149247 25762 151098 -1 2670 20 1670 2442 197737 43022 3.59376 3.59376 -134.576 -3.59376 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0174682 0.0157616 94 55 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_050.v common 2.79 vpr 65.41 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29852 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66984 32 32 382 305 1 237 86 17 17 289 -1 unnamed_device 26.0 MiB 0.28 2390 1306 9725 3245 4874 1606 65.4 MiB 0.06 0.00 4.47137 3.65053 -130.846 -3.65053 3.65053 0.25 0.000352114 0.00032115 0.0220394 0.0202648 -1 -1 -1 -1 40 3093 27 6.99608e+06 323745 706193. 2443.58 1.04 0.110123 0.09724 26914 176310 -1 2643 22 2052 2804 233702 50043 3.29947 3.29947 -131.275 -3.29947 0 0 926341. 3205.33 0.03 0.07 0.11 -1 -1 0.03 0.0235983 0.0212753 101 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_051.v common 6.58 vpr 64.65 MiB -1 -1 0.12 17748 1 0.03 -1 -1 29776 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66200 32 32 306 248 1 175 80 17 17 289 -1 unnamed_device 25.2 MiB 0.41 2053 1074 11776 3968 6127 1681 64.6 MiB 0.07 0.00 5.26523 4.40603 -128.032 -4.40603 4.40603 0.26 0.000728279 0.000680288 0.0316996 0.0293502 -1 -1 -1 -1 34 2691 25 6.99608e+06 235451 618332. 2139.56 4.79 0.197275 0.172981 25762 151098 -1 2202 23 1453 2321 173808 37601 4.15667 4.15667 -136.845 -4.15667 0 0 787024. 2723.27 0.03 0.05 0.09 -1 -1 0.03 0.0195148 0.0174502 74 24 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_052.v common 3.39 vpr 64.48 MiB -1 -1 0.17 17676 1 0.03 -1 -1 29596 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 319 257 1 191 81 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2287 910 14606 5914 7002 1690 64.5 MiB 0.07 0.00 4.83128 4.09737 -124.66 -4.09737 4.09737 0.24 0.000310375 0.000283813 0.0282189 0.0258265 -1 -1 -1 -1 40 2417 38 6.99608e+06 250167 706193. 2443.58 1.69 0.153958 0.134164 26914 176310 -1 2039 22 1754 2409 172828 40103 4.13556 4.13556 -134.855 -4.13556 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0170663 0.0152923 79 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_053.v common 4.20 vpr 65.36 MiB -1 -1 0.22 18680 1 0.03 -1 -1 29812 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66928 31 32 373 299 1 222 83 17 17 289 -1 unnamed_device 25.3 MiB 0.29 3060 1061 14663 6195 7837 631 65.4 MiB 0.07 0.00 5.29948 4.04648 -128.43 -4.04648 4.04648 0.25 0.000346543 0.000316492 0.0300002 0.0274375 -1 -1 -1 -1 44 3255 35 6.99608e+06 294314 787024. 2723.27 2.28 0.202541 0.177628 27778 195446 -1 2207 24 1922 2925 205658 47391 4.38296 4.38296 -146.891 -4.38296 0 0 997811. 3452.63 0.04 0.05 0.12 -1 -1 0.04 0.0192397 0.0172114 96 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_054.v common 3.78 vpr 65.43 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29784 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67000 32 32 387 315 1 239 84 17 17 289 -1 unnamed_device 25.6 MiB 0.36 2489 1239 10515 4270 6030 215 65.4 MiB 0.08 0.00 4.49482 3.93712 -132.475 -3.93712 3.93712 0.26 0.00042534 0.0003946 0.0319843 0.0296844 -1 -1 -1 -1 42 3657 38 6.99608e+06 294314 744469. 2576.02 1.97 0.19167 0.168728 27202 183097 -1 2768 23 2154 3218 251393 54624 3.81701 3.81701 -136.091 -3.81701 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0194698 0.0174518 102 77 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_055.v common 2.78 vpr 64.02 MiB -1 -1 0.16 17916 1 0.03 -1 -1 29788 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65560 32 32 251 219 1 151 77 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1737 727 8879 3608 5056 215 64.0 MiB 0.04 0.00 3.88198 3.25548 -102.196 -3.25548 3.25548 0.28 0.00026341 0.0002409 0.0158008 0.0144687 -1 -1 -1 -1 38 1830 24 6.99608e+06 191304 678818. 2348.85 1.16 0.0983347 0.0862121 26626 170182 -1 1501 21 989 1400 93207 22725 2.96192 2.96192 -100.295 -2.96192 0 0 902133. 3121.57 0.03 0.03 0.09 -1 -1 0.03 0.013285 0.0118673 59 23 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_056.v common 7.37 vpr 65.13 MiB -1 -1 0.18 18056 1 0.03 -1 -1 30212 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66696 32 32 341 285 1 216 81 17 17 289 -1 unnamed_device 25.2 MiB 0.30 2337 1049 10756 3701 4965 2090 65.1 MiB 0.06 0.00 4.38205 3.60289 -133.031 -3.60289 3.60289 0.25 0.000415296 0.000387779 0.0239569 0.0220371 -1 -1 -1 -1 40 2703 23 6.99608e+06 250167 706193. 2443.58 5.55 0.167443 0.147046 26914 176310 -1 2352 23 2080 2820 262366 57085 3.88501 3.88501 -148.748 -3.88501 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0176703 0.015799 89 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_057.v common 4.03 vpr 64.22 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29984 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65764 32 32 387 293 1 225 82 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2656 1174 14144 6001 7737 406 64.2 MiB 0.08 0.00 5.84018 4.78152 -149.199 -4.78152 4.78152 0.32 0.00038237 0.00035059 0.0376424 0.0348163 -1 -1 -1 -1 50 2834 24 6.99608e+06 264882 902133. 3121.57 2.10 0.205741 0.181907 28642 213929 -1 2303 22 2041 3172 224362 48220 4.42076 4.42076 -146.875 -4.42076 0 0 1.08113e+06 3740.92 0.04 0.05 0.12 -1 -1 0.04 0.0197493 0.0177838 96 31 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_058.v common 2.62 vpr 65.04 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30412 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66596 32 32 340 270 1 205 82 17 17 289 -1 unnamed_device 25.3 MiB 0.24 2003 1157 10406 3036 5903 1467 65.0 MiB 0.05 0.00 4.01546 3.80886 -131.153 -3.80886 3.80886 0.25 0.000332988 0.00030492 0.0213291 0.0195744 -1 -1 -1 -1 36 2842 26 6.99608e+06 264882 648988. 2245.63 0.83 0.0904082 0.079963 26050 158493 -1 2400 20 1865 2578 211228 44537 3.22692 3.22692 -130.367 -3.22692 0 0 828058. 2865.25 0.05 0.08 0.15 -1 -1 0.05 0.0276081 0.0248415 83 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_059.v common 2.73 vpr 64.88 MiB -1 -1 0.19 17676 1 0.03 -1 -1 29812 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 30 32 278 235 1 166 86 17 17 289 -1 unnamed_device 25.6 MiB 0.17 1819 953 11237 3335 6152 1750 64.9 MiB 0.05 0.00 4.46953 3.72455 -123.086 -3.72455 3.72455 0.34 0.000295449 0.000271121 0.0207062 0.0190016 -1 -1 -1 -1 32 2493 41 6.99608e+06 353176 586450. 2029.24 0.99 0.0810683 0.0713788 25474 144626 -1 1945 20 1129 1868 155903 34266 3.66766 3.66766 -130.635 -3.66766 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0169198 0.0148726 75 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_060.v common 13.97 vpr 65.62 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29780 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67192 32 32 431 332 1 263 86 17 17 289 -1 unnamed_device 25.6 MiB 0.36 3530 1523 10859 3269 7015 575 65.6 MiB 0.07 0.00 8.11443 6.30909 -191.484 -6.30909 6.30909 0.25 0.000409098 0.000372795 0.0269271 0.024715 -1 -1 -1 -1 40 3812 24 6.99608e+06 323745 706193. 2443.58 12.07 0.275135 0.243556 26914 176310 -1 3230 22 2400 3619 307902 64475 5.46454 5.46454 -183.101 -5.46454 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0224372 0.0202166 113 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_061.v common 2.82 vpr 64.55 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30360 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 32 32 336 268 1 199 81 17 17 289 -1 unnamed_device 25.6 MiB 0.33 2220 1042 7256 1709 5288 259 64.5 MiB 0.10 0.00 5.22335 4.47706 -136.26 -4.47706 4.47706 0.26 0.000897643 0.000833199 0.040152 0.0374168 -1 -1 -1 -1 36 2668 31 6.99608e+06 250167 648988. 2245.63 1.01 0.123457 0.110111 26050 158493 -1 2169 22 1855 2587 213043 45510 4.09836 4.09836 -141.679 -4.09836 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0173523 0.015543 82 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_062.v common 3.31 vpr 64.49 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30328 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 32 32 231 199 1 136 80 17 17 289 -1 unnamed_device 25.0 MiB 0.14 1667 644 6788 1443 5150 195 64.5 MiB 0.04 0.00 3.3651 2.966 -94.919 -2.966 2.966 0.25 0.000257042 0.000236046 0.0117376 0.0108063 -1 -1 -1 -1 36 1886 27 6.99608e+06 235451 648988. 2245.63 1.77 0.127294 0.111299 26050 158493 -1 1559 19 950 1545 119567 29462 2.94467 2.94467 -105.198 -2.94467 0 0 828058. 2865.25 0.05 0.07 0.09 -1 -1 0.05 0.0278513 0.024845 54 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_063.v common 4.46 vpr 65.26 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30232 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66828 32 32 349 273 1 205 84 17 17 289 -1 unnamed_device 25.6 MiB 0.23 2149 1082 11430 4676 6413 341 65.3 MiB 0.06 0.00 5.75835 4.90682 -134.383 -4.90682 4.90682 0.25 0.000333152 0.000304183 0.0230581 0.0211123 -1 -1 -1 -1 50 2420 28 6.99608e+06 294314 902133. 3121.57 2.75 0.210124 0.185284 28642 213929 -1 2106 23 1498 2570 197970 44240 4.41151 4.41151 -133.222 -4.41151 0 0 1.08113e+06 3740.92 0.04 0.06 0.12 -1 -1 0.04 0.0201727 0.0180905 86 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_064.v common 2.35 vpr 64.20 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29800 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 247 207 1 142 80 17 17 289 -1 unnamed_device 24.9 MiB 0.14 1516 866 8852 2265 5550 1037 64.2 MiB 0.07 0.00 3.3589 2.9481 -106.495 -2.9481 2.9481 0.29 0.000477265 0.000433152 0.0294708 0.0271445 -1 -1 -1 -1 32 1986 23 6.99608e+06 235451 586450. 2029.24 0.76 0.0926109 0.0816633 25474 144626 -1 1818 21 1207 1848 144119 31724 2.97567 2.97567 -114.332 -2.97567 0 0 744469. 2576.02 0.04 0.04 0.14 -1 -1 0.04 0.0132219 0.0117761 58 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_065.v common 4.51 vpr 64.35 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29852 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 30 32 278 235 1 168 79 17 17 289 -1 unnamed_device 24.9 MiB 0.27 1881 846 11740 4899 6478 363 64.3 MiB 0.06 0.00 3.88477 3.61627 -115.385 -3.61627 3.61627 0.38 0.000277943 0.000253538 0.0253803 0.0232971 -1 -1 -1 -1 34 2626 42 6.99608e+06 250167 618332. 2139.56 2.59 0.149488 0.131234 25762 151098 -1 1930 22 1548 2150 173949 38779 3.36322 3.36322 -120.284 -3.36322 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0148292 0.0132602 69 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_066.v common 8.09 vpr 65.30 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29796 -1 -1 21 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66872 29 32 355 287 1 212 82 17 17 289 -1 unnamed_device 25.2 MiB 0.35 2487 1076 7024 1631 5053 340 65.3 MiB 0.04 0.00 4.65503 4.06423 -126.233 -4.06423 4.06423 0.24 0.0003279 0.00030095 0.0150345 0.0137987 -1 -1 -1 -1 40 2852 44 6.99608e+06 309029 706193. 2443.58 6.39 0.19367 0.169529 26914 176310 -1 2416 21 1657 2448 196716 42818 3.649 3.649 -124.232 -3.649 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0171414 0.0153764 94 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_067.v common 5.18 vpr 65.18 MiB -1 -1 0.12 18440 1 0.03 -1 -1 29760 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66744 32 32 358 289 1 214 83 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2512 1102 12323 3030 8331 962 65.2 MiB 0.06 0.00 5.76244 4.57197 -150.669 -4.57197 4.57197 0.25 0.000340918 0.00031236 0.0265798 0.0243785 -1 -1 -1 -1 40 2617 23 6.99608e+06 279598 706193. 2443.58 3.43 0.182268 0.159744 26914 176310 -1 2263 20 1664 2404 159920 36281 4.4118 4.4118 -149.852 -4.4118 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0170972 0.0153704 93 54 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_068.v common 6.18 vpr 65.29 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30264 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66856 32 32 353 285 1 210 82 17 17 289 -1 unnamed_device 25.2 MiB 0.35 2477 1259 12542 3693 7235 1614 65.3 MiB 0.07 0.00 5.61514 4.67867 -148.606 -4.67867 4.67867 0.26 0.000330558 0.000302788 0.0284666 0.0261654 -1 -1 -1 -1 36 3280 30 6.99608e+06 264882 648988. 2245.63 4.40 0.190601 0.1677 26050 158493 -1 2804 20 1753 2535 251826 52553 4.52301 4.52301 -153.738 -4.52301 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0175652 0.0158305 90 51 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_069.v common 2.87 vpr 64.66 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29796 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 32 32 276 237 1 160 77 17 17 289 -1 unnamed_device 25.2 MiB 0.39 2019 874 7412 2163 4944 305 64.7 MiB 0.04 0.00 4.43837 3.56127 -113.067 -3.56127 3.56127 0.25 0.000283865 0.000260375 0.0142326 0.0130747 -1 -1 -1 -1 38 2164 36 6.99608e+06 191304 678818. 2348.85 1.10 0.109947 0.0967195 26626 170182 -1 1847 21 1125 1512 114209 25335 3.29786 3.29786 -114.972 -3.29786 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.016037 0.0142694 65 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_070.v common 2.83 vpr 64.50 MiB -1 -1 0.15 17676 1 0.03 -1 -1 29640 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 31 32 319 272 1 200 80 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2059 1143 8680 2684 4726 1270 64.5 MiB 0.06 0.00 3.74443 3.36163 -119.008 -3.36163 3.36163 0.28 0.000348439 0.000322031 0.0245664 0.02271 -1 -1 -1 -1 36 2725 29 6.99608e+06 250167 648988. 2245.63 1.02 0.131981 0.116646 26050 158493 -1 2415 23 1788 2474 198378 43599 3.45072 3.45072 -132.987 -3.45072 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0175891 0.0157376 83 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_071.v common 3.31 vpr 64.93 MiB -1 -1 0.18 18060 1 0.04 -1 -1 30516 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 30 32 329 273 1 202 84 17 17 289 -1 unnamed_device 25.2 MiB 0.37 2292 985 10698 3333 5234 2131 64.9 MiB 0.05 0.00 3.96185 3.1635 -104.256 -3.1635 3.1635 0.25 0.000310397 0.000283766 0.0202326 0.0185443 -1 -1 -1 -1 38 2681 23 6.99608e+06 323745 678818. 2348.85 1.43 0.133462 0.116748 26626 170182 -1 2079 21 1525 2176 145997 33843 3.15117 3.15117 -108.403 -3.15117 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0163276 0.0146456 88 57 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_072.v common 2.62 vpr 64.30 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29820 -1 -1 20 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 28 32 277 229 1 167 80 17 17 289 -1 unnamed_device 24.6 MiB 0.18 2171 750 13324 5641 6785 898 64.3 MiB 0.06 0.00 4.60235 3.68935 -102.007 -3.68935 3.68935 0.26 0.000280311 0.000256331 0.0262871 0.0241405 -1 -1 -1 -1 38 2095 46 6.99608e+06 294314 678818. 2348.85 1.06 0.0999501 0.0881336 26626 170182 -1 1637 20 1275 2053 133456 31957 3.86712 3.86712 -107.152 -3.86712 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0139935 0.0125284 70 27 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_073.v common 4.06 vpr 64.07 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29780 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65612 30 32 317 269 1 200 80 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2064 1130 10400 3752 5071 1577 64.1 MiB 0.08 0.00 4.54182 3.92332 -130.777 -3.92332 3.92332 0.44 0.000299101 0.00027329 0.0360045 0.0331235 -1 -1 -1 -1 44 2351 40 6.99608e+06 264882 787024. 2723.27 1.79 0.167755 0.146837 27778 195446 -1 2079 50 2714 3757 509029 223795 3.54531 3.54531 -130.146 -3.54531 0 0 997811. 3452.63 0.04 0.17 0.11 -1 -1 0.04 0.0301622 0.0264103 84 63 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_074.v common 3.55 vpr 64.54 MiB -1 -1 0.20 17672 1 0.03 -1 -1 30204 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66088 32 32 335 282 1 216 82 17 17 289 -1 unnamed_device 25.2 MiB 0.38 2365 1114 12542 4673 5784 2085 64.5 MiB 0.08 0.00 3.99224 3.50894 -127.534 -3.50894 3.50894 0.25 0.000315106 0.000287859 0.034242 0.0315552 -1 -1 -1 -1 42 2677 24 6.99608e+06 264882 744469. 2576.02 1.61 0.152336 0.134508 27202 183097 -1 2084 22 1659 2257 159018 34861 3.14317 3.14317 -124.044 -3.14317 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0187501 0.0166729 87 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_075.v common 8.45 vpr 65.02 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29552 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 31 32 293 230 1 168 91 17 17 289 -1 unnamed_device 25.2 MiB 0.09 2000 982 10903 2684 7356 863 65.0 MiB 0.05 0.00 4.71072 4.12848 -125.314 -4.12848 4.12848 0.24 0.000299526 0.000273857 0.0177575 0.0162742 -1 -1 -1 -1 40 2473 20 6.99608e+06 412039 706193. 2443.58 6.98 0.188456 0.165444 26914 176310 -1 2209 24 1486 2666 236458 56195 4.03642 4.03642 -129.321 -4.03642 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0170776 0.0152593 77 4 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_076.v common 3.08 vpr 64.80 MiB -1 -1 0.15 17916 1 0.03 -1 -1 29968 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 350 275 1 206 83 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2490 1189 13403 4211 7234 1958 64.8 MiB 0.08 0.00 4.89302 4.14724 -142.136 -4.14724 4.14724 0.26 0.00033104 0.000302573 0.034491 0.0318021 -1 -1 -1 -1 36 3453 42 6.99608e+06 279598 648988. 2245.63 1.35 0.125825 0.111916 26050 158493 -1 2897 21 1884 2802 281160 57735 4.19956 4.19956 -157.838 -4.19956 0 0 828058. 2865.25 0.03 0.06 0.11 -1 -1 0.03 0.0184156 0.0165322 87 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_077.v common 4.17 vpr 64.71 MiB -1 -1 0.21 18060 1 0.04 -1 -1 29772 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 32 32 385 308 1 237 85 17 17 289 -1 unnamed_device 25.8 MiB 0.44 2652 1256 15151 5422 7831 1898 64.7 MiB 0.08 0.00 5.94478 5.006 -165.631 -5.006 5.006 0.25 0.000358141 0.000328231 0.0313961 0.0287286 -1 -1 -1 -1 40 3284 27 6.99608e+06 309029 706193. 2443.58 1.99 0.176264 0.156042 26914 176310 -1 2763 21 2194 3069 284504 58389 4.65534 4.65534 -165.239 -4.65534 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.020252 0.0182285 103 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_078.v common 3.00 vpr 65.43 MiB -1 -1 0.14 18296 1 0.03 -1 -1 29856 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67000 32 32 387 309 1 244 86 17 17 289 -1 unnamed_device 25.6 MiB 0.38 3090 1280 16529 5531 8719 2279 65.4 MiB 0.09 0.00 4.97976 4.22796 -143.885 -4.22796 4.22796 0.26 0.000359741 0.000330081 0.0345095 0.0317078 -1 -1 -1 -1 38 3429 46 6.99608e+06 323745 678818. 2348.85 1.11 0.118587 0.105226 26626 170182 -1 2650 21 2083 3065 220833 47744 4.0125 4.0125 -147.917 -4.0125 0 0 902133. 3121.57 0.03 0.06 0.10 -1 -1 0.03 0.0220048 0.0195822 102 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_079.v common 4.55 vpr 64.08 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29876 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65620 30 32 272 232 1 169 79 17 17 289 -1 unnamed_device 24.9 MiB 0.22 1873 976 10388 2655 6704 1029 64.1 MiB 0.05 0.00 4.35146 3.77996 -115.544 -3.77996 3.77996 0.25 0.000298857 0.000275244 0.019425 0.0178398 -1 -1 -1 -1 32 2668 46 6.99608e+06 250167 586450. 2029.24 2.81 0.171253 0.150186 25474 144626 -1 2156 23 1627 2295 190396 40496 3.16982 3.16982 -119.919 -3.16982 0 0 744469. 2576.02 0.04 0.08 0.14 -1 -1 0.04 0.0250296 0.0223372 68 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_080.v common 7.57 vpr 65.39 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29808 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 30 32 375 299 1 231 83 17 17 289 -1 unnamed_device 25.6 MiB 0.35 2543 1226 12863 4164 7357 1342 65.4 MiB 0.07 0.00 6.19097 4.8136 -157.664 -4.8136 4.8136 0.25 0.000343255 0.000314156 0.0271782 0.0248716 -1 -1 -1 -1 38 3234 41 6.99608e+06 309029 678818. 2348.85 5.75 0.208307 0.182755 26626 170182 -1 2608 23 2337 3366 264876 55857 4.57834 4.57834 -160.67 -4.57834 0 0 902133. 3121.57 0.03 0.06 0.11 -1 -1 0.03 0.0198221 0.0178488 101 63 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_081.v common 10.75 vpr 65.09 MiB -1 -1 0.21 18060 1 0.03 -1 -1 29580 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 32 32 340 270 1 197 82 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2353 1072 9338 2392 6620 326 65.1 MiB 0.05 0.00 5.08705 4.46071 -137.725 -4.46071 4.46071 0.25 0.000326806 0.000298657 0.0201311 0.018525 -1 -1 -1 -1 36 3037 36 6.99608e+06 264882 648988. 2245.63 8.96 0.198441 0.174241 26050 158493 -1 2579 20 1968 3193 317298 64436 4.05906 4.05906 -142.951 -4.05906 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0165587 0.014862 83 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_082.v common 5.09 vpr 65.23 MiB -1 -1 0.14 18444 1 0.03 -1 -1 29780 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66800 31 32 340 275 1 195 82 17 17 289 -1 unnamed_device 25.2 MiB 0.52 2485 1077 6846 1660 4720 466 65.2 MiB 0.04 0.00 5.99233 5.0824 -146.792 -5.0824 5.0824 0.25 0.000332049 0.000305039 0.0153348 0.0141025 -1 -1 -1 -1 36 2949 36 6.99608e+06 279598 648988. 2245.63 2.99 0.163543 0.14333 26050 158493 -1 2436 25 1611 2368 219315 58630 4.22141 4.22141 -143.659 -4.22141 0 0 828058. 2865.25 0.05 0.10 0.14 -1 -1 0.05 0.0345574 0.0311452 87 47 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_083.v common 4.20 vpr 64.68 MiB -1 -1 0.14 18296 1 0.03 -1 -1 30180 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 30 32 377 310 1 234 85 17 17 289 -1 unnamed_device 25.2 MiB 0.40 2527 1287 11803 3693 6222 1888 64.7 MiB 0.07 0.00 4.79242 3.97958 -130.547 -3.97958 3.97958 0.28 0.000341223 0.000312216 0.0298593 0.0275985 -1 -1 -1 -1 46 2907 27 6.99608e+06 338461 828058. 2865.25 2.30 0.188811 0.166861 28066 200906 -1 2352 20 1694 2546 209301 42710 3.4157 3.4157 -127.942 -3.4157 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0172781 0.0155465 105 83 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_084.v common 4.16 vpr 65.34 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29776 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66908 32 32 365 294 1 223 83 17 17 289 -1 unnamed_device 25.2 MiB 0.32 2642 1080 13043 4299 6062 2682 65.3 MiB 0.10 0.00 5.91884 4.65647 -145.605 -4.65647 4.65647 0.28 0.000616403 0.000561375 0.039827 0.0366499 -1 -1 -1 -1 58 2339 29 6.99608e+06 279598 997811. 3452.63 2.26 0.197471 0.173865 30370 251734 -1 1947 23 1549 2349 189783 40720 4.15385 4.15385 -138.843 -4.15385 0 0 1.25153e+06 4330.55 0.04 0.05 0.14 -1 -1 0.04 0.0191202 0.0171213 94 57 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_085.v common 3.96 vpr 65.42 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29244 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66988 29 32 378 310 1 232 84 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2249 1133 10332 4059 5536 737 65.4 MiB 0.06 0.00 4.37595 3.76735 -122.856 -3.76735 3.76735 0.25 0.000806941 0.000751406 0.0263063 0.0242243 -1 -1 -1 -1 40 2918 21 6.99608e+06 338461 706193. 2443.58 2.22 0.200676 0.177945 26914 176310 -1 2367 22 1494 2036 156146 35777 4.04156 4.04156 -134.374 -4.04156 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0229383 0.0205342 106 85 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_086.v common 3.20 vpr 64.49 MiB -1 -1 0.16 17676 1 0.03 -1 -1 30300 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 243 205 1 140 77 17 17 289 -1 unnamed_device 24.9 MiB 0.54 1620 885 6108 1414 4233 461 64.5 MiB 0.04 0.00 3.92693 3.42573 -113.797 -3.42573 3.42573 0.27 0.000262716 0.000240101 0.0155632 0.014418 -1 -1 -1 -1 32 2105 20 6.99608e+06 191304 586450. 2029.24 1.23 0.121706 0.106417 25474 144626 -1 1872 20 1044 1623 134418 28714 3.15892 3.15892 -116.975 -3.15892 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145525 0.0129752 56 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_087.v common 3.10 vpr 65.38 MiB -1 -1 0.13 17916 1 0.04 -1 -1 30272 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66952 32 32 373 302 1 234 85 17 17 289 -1 unnamed_device 25.3 MiB 0.25 2757 1184 15523 6072 7602 1849 65.4 MiB 0.08 0.00 6.55248 4.951 -158.167 -4.951 4.951 0.25 0.000359023 0.000329679 0.0314315 0.0288277 -1 -1 -1 -1 38 3214 39 6.99608e+06 309029 678818. 2348.85 1.29 0.120257 0.106819 26626 170182 -1 2557 23 2159 3151 273144 56610 4.50624 4.50624 -154.678 -4.50624 0 0 902133. 3121.57 0.05 0.10 0.11 -1 -1 0.05 0.0328808 0.0296767 98 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_088.v common 4.56 vpr 64.09 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29748 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 32 32 397 314 1 249 85 17 17 289 -1 unnamed_device 24.5 MiB 0.37 2726 1321 14965 5056 8532 1377 64.1 MiB 0.08 0.00 5.25319 4.65797 -164.783 -4.65797 4.65797 0.25 0.000368298 0.000331202 0.0316858 0.0290061 -1 -1 -1 -1 40 3636 25 6.99608e+06 309029 706193. 2443.58 2.70 0.227798 0.201867 26914 176310 -1 2903 21 2508 3573 301907 62282 4.82971 4.82971 -176.472 -4.82971 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0188725 0.0170092 105 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_089.v common 2.76 vpr 64.69 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29784 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 32 32 269 231 1 163 77 17 17 289 -1 unnamed_device 25.5 MiB 0.26 1853 737 10346 4283 5770 293 64.7 MiB 0.05 0.00 3.61613 3.25618 -100.635 -3.25618 3.25618 0.26 0.000294064 0.00026383 0.0250246 0.0231762 -1 -1 -1 -1 40 1864 45 6.99608e+06 191304 706193. 2443.58 1.05 0.104956 0.0924776 26914 176310 -1 1561 25 1244 1653 120205 30029 3.41867 3.41867 -112.985 -3.41867 0 0 926341. 3205.33 0.05 0.04 0.17 -1 -1 0.05 0.0158374 0.0140831 66 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_090.v common 2.08 vpr 64.09 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30324 -1 -1 16 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 31 32 245 205 1 144 79 17 17 289 -1 unnamed_device 24.9 MiB 0.11 1536 858 8360 2256 5168 936 64.1 MiB 0.04 0.00 3.61893 3.28943 -106.361 -3.28943 3.28943 0.35 0.000256667 0.000234795 0.014228 0.0130658 -1 -1 -1 -1 32 2072 26 6.99608e+06 235451 586450. 2029.24 0.56 0.0580191 0.0509893 25474 144626 -1 1856 19 1171 1959 154991 34293 3.14792 3.14792 -114.535 -3.14792 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0130327 0.0116131 59 4 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_091.v common 3.42 vpr 65.25 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29996 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66820 32 32 348 274 1 209 82 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2619 1051 8270 2110 5627 533 65.3 MiB 0.05 0.00 4.98867 4.02312 -135.346 -4.02312 4.02312 0.24 0.000356126 0.000327305 0.0175964 0.0161306 -1 -1 -1 -1 40 2752 48 6.99608e+06 264882 706193. 2443.58 1.62 0.131444 0.115935 26914 176310 -1 2412 21 1981 2778 221710 49503 4.01046 4.01046 -144.849 -4.01046 0 0 926341. 3205.33 0.05 0.09 0.16 -1 -1 0.05 0.0312576 0.0282401 85 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_092.v common 3.75 vpr 65.31 MiB -1 -1 0.12 17696 1 0.03 -1 -1 30196 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66876 32 32 356 289 1 215 85 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2661 1142 10687 2890 6795 1002 65.3 MiB 0.06 0.00 5.42227 4.69222 -141.619 -4.69222 4.69222 0.24 0.000331438 0.000303919 0.0213103 0.0195584 -1 -1 -1 -1 36 3081 25 6.99608e+06 309029 648988. 2245.63 1.92 0.196571 0.172762 26050 158493 -1 2497 20 1667 2322 178458 40445 4.59211 4.59211 -151.626 -4.59211 0 0 828058. 2865.25 0.03 0.09 0.12 -1 -1 0.03 0.032519 0.0294266 93 56 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_093.v common 4.75 vpr 64.54 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29808 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66092 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 25.3 MiB 0.13 2109 1015 8913 2758 4385 1770 64.5 MiB 0.04 0.00 5.39397 4.48151 -135.956 -4.48151 4.48151 0.25 0.000344854 0.000313183 0.0166858 0.0152261 -1 -1 -1 -1 46 2960 42 6.99608e+06 426755 828058. 2865.25 3.17 0.188439 0.16599 28066 200906 -1 2212 21 1697 3063 248423 56450 4.31935 4.31935 -140.411 -4.31935 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0181888 0.0163971 90 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_094.v common 2.90 vpr 65.11 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29988 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66672 30 32 316 264 1 191 83 17 17 289 -1 unnamed_device 25.6 MiB 0.38 2606 1009 7823 1822 5457 544 65.1 MiB 0.04 0.00 4.76312 3.58427 -106.995 -3.58427 3.58427 0.25 0.000308712 0.000283316 0.015233 0.0140358 -1 -1 -1 -1 36 2586 30 6.99608e+06 309029 648988. 2245.63 1.08 0.106457 0.0937082 26050 158493 -1 2283 24 1925 2911 230611 48960 3.34252 3.34252 -113.894 -3.34252 0 0 828058. 2865.25 0.03 0.06 0.11 -1 -1 0.03 0.0217187 0.0192677 86 52 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_095.v common 3.04 vpr 64.51 MiB -1 -1 0.11 17916 1 0.03 -1 -1 30168 -1 -1 17 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 27 32 255 219 1 145 76 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1732 742 10956 3486 6732 738 64.5 MiB 0.04 0.00 4.92129 3.75245 -110.833 -3.75245 3.75245 0.24 0.000254695 0.00023279 0.0189859 0.0174081 -1 -1 -1 -1 30 1917 29 6.99608e+06 250167 556674. 1926.21 1.56 0.0982599 0.0857575 25186 138497 -1 1600 18 968 1431 102703 23011 3.61546 3.61546 -115.129 -3.61546 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0121467 0.0108756 67 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_096.v common 10.72 vpr 65.53 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29736 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67100 32 32 421 327 1 263 87 17 17 289 -1 unnamed_device 25.6 MiB 0.32 3139 1454 14487 3900 9094 1493 65.5 MiB 0.13 0.00 5.82494 4.22974 -144.161 -4.22974 4.22974 0.30 0.00039563 0.000362842 0.0564457 0.052421 -1 -1 -1 -1 42 3877 49 6.99608e+06 338461 744469. 2576.02 8.82 0.261665 0.23186 27202 183097 -1 3220 21 2143 3398 291996 60989 4.20031 4.20031 -152.043 -4.20031 0 0 949917. 3286.91 0.04 0.06 0.10 -1 -1 0.04 0.0201234 0.0181126 110 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_097.v common 3.24 vpr 64.75 MiB -1 -1 0.15 18060 1 0.03 -1 -1 29756 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 31 32 365 296 1 229 84 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2811 1262 12894 3886 6900 2108 64.7 MiB 0.07 0.00 6.59169 5.46783 -160.186 -5.46783 5.46783 0.25 0.000339653 0.000311033 0.0258576 0.0236764 -1 -1 -1 -1 40 2874 28 6.99608e+06 309029 706193. 2443.58 1.49 0.140763 0.124371 26914 176310 -1 2401 22 2013 2891 213884 45949 4.54281 4.54281 -157.549 -4.54281 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.018057 0.0162127 97 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_098.v common 3.44 vpr 65.15 MiB -1 -1 0.15 18444 1 0.02 -1 -1 29880 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66712 32 32 331 280 1 215 82 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2580 1220 8448 2298 5647 503 65.1 MiB 0.05 0.00 4.4353 3.55199 -133.806 -3.55199 3.55199 0.26 0.000319361 0.000292362 0.0213717 0.0197884 -1 -1 -1 -1 36 2753 24 6.99608e+06 264882 648988. 2245.63 1.68 0.158365 0.138772 26050 158493 -1 2346 21 1724 2226 174140 38058 3.49956 3.49956 -137.622 -3.49956 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0165778 0.0149044 86 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_099.v common 3.91 vpr 64.49 MiB -1 -1 0.12 17916 1 0.03 -1 -1 30300 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 326 263 1 198 81 17 17 289 -1 unnamed_device 25.2 MiB 0.24 2007 915 11806 4558 6015 1233 64.5 MiB 0.06 0.00 4.69498 4.19833 -126.153 -4.19833 4.19833 0.35 0.000331511 0.000303973 0.027978 0.0258442 -1 -1 -1 -1 44 2540 49 6.99608e+06 250167 787024. 2723.27 2.16 0.194089 0.170363 27778 195446 -1 1804 19 1192 1636 115903 27473 3.77352 3.77352 -123.719 -3.77352 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0177594 0.0161027 80 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_100.v common 2.91 vpr 65.25 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29868 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66816 31 32 373 294 1 216 84 17 17 289 -1 unnamed_device 25.8 MiB 0.36 2762 1151 14907 5290 7728 1889 65.2 MiB 0.09 0.00 5.40098 4.12378 -127.257 -4.12378 4.12378 0.24 0.000371977 0.000340791 0.0370602 0.0340631 -1 -1 -1 -1 40 2607 25 6.99608e+06 309029 706193. 2443.58 1.10 0.12845 0.114036 26914 176310 -1 2325 22 1845 2733 198743 43453 3.81082 3.81082 -130.703 -3.81082 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.019102 0.0171685 97 50 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_101.v common 3.97 vpr 65.03 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29816 -1 -1 20 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66592 30 32 325 268 1 197 82 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2275 931 9694 3916 5291 487 65.0 MiB 0.05 0.00 4.37729 3.52894 -109.796 -3.52894 3.52894 0.24 0.000319843 0.00028404 0.0189408 0.017331 -1 -1 -1 -1 46 2439 26 6.99608e+06 294314 828058. 2865.25 2.25 0.144389 0.126734 28066 200906 -1 1870 19 1331 2123 160757 36535 3.48697 3.48697 -114.338 -3.48697 0 0 1.01997e+06 3529.29 0.04 0.04 0.11 -1 -1 0.04 0.0153406 0.0138183 85 51 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_102.v common 3.77 vpr 65.11 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29792 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66672 32 32 350 275 1 209 82 17 17 289 -1 unnamed_device 25.6 MiB 0.29 2452 1191 11118 2720 7663 735 65.1 MiB 0.06 0.00 4.76098 4.21963 -145.335 -4.21963 4.21963 0.25 0.000357095 0.000307568 0.0240345 0.0221081 -1 -1 -1 -1 42 3059 30 6.99608e+06 264882 744469. 2576.02 1.99 0.183276 0.160905 27202 183097 -1 2646 22 2111 3171 339117 78140 4.30592 4.30592 -150.736 -4.30592 0 0 949917. 3286.91 0.03 0.07 0.10 -1 -1 0.03 0.0180706 0.0162177 87 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_103.v common 3.22 vpr 65.43 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29804 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67000 32 32 386 307 1 240 85 17 17 289 -1 unnamed_device 25.5 MiB 0.28 2544 1330 10687 2581 6972 1134 65.4 MiB 0.06 0.00 4.10857 3.66363 -131.207 -3.66363 3.66363 0.24 0.000358631 0.000328675 0.0233891 0.0214854 -1 -1 -1 -1 40 2913 20 6.99608e+06 309029 706193. 2443.58 1.54 0.146169 0.128078 26914 176310 -1 2609 26 2198 3089 256591 54227 3.46877 3.46877 -133.609 -3.46877 0 0 926341. 3205.33 0.03 0.07 0.09 -1 -1 0.03 0.0247133 0.0222095 102 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 3.89 vpr 64.69 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29992 -1 -1 18 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 29 32 269 229 1 166 79 17 17 289 -1 unnamed_device 24.9 MiB 0.22 1756 750 8867 3422 4589 856 64.7 MiB 0.04 0.00 4.44376 3.81986 -111.589 -3.81986 3.81986 0.25 0.000268678 0.000245483 0.0157691 0.0144682 -1 -1 -1 -1 32 2228 31 6.99608e+06 264882 586450. 2029.24 2.28 0.125635 0.109629 25474 144626 -1 1667 22 1606 2144 164445 35623 3.43772 3.43772 -115.848 -3.43772 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0143813 0.012807 68 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_105.v common 4.92 vpr 65.08 MiB -1 -1 0.12 17916 1 0.02 -1 -1 29928 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66640 32 32 310 266 1 186 79 17 17 289 -1 unnamed_device 25.6 MiB 0.25 2114 1072 10388 2745 6664 979 65.1 MiB 0.05 0.00 4.23779 3.56989 -126.273 -3.56989 3.56989 0.25 0.000302879 0.000276572 0.0200515 0.018352 -1 -1 -1 -1 40 2251 27 6.99608e+06 220735 706193. 2443.58 3.29 0.150356 0.131318 26914 176310 -1 2129 19 1386 1859 153495 33604 3.78796 3.78796 -134.796 -3.78796 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0256499 0.0230263 78 58 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_106.v common 3.40 vpr 64.12 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30268 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65664 31 32 326 261 1 197 83 17 17 289 -1 unnamed_device 25.2 MiB 0.22 2462 1162 13763 5234 6995 1534 64.1 MiB 0.07 0.00 5.08188 4.09932 -130.497 -4.09932 4.09932 0.24 0.000314789 0.000287897 0.02625 0.0240865 -1 -1 -1 -1 46 2358 22 6.99608e+06 294314 828058. 2865.25 1.74 0.147828 0.129695 28066 200906 -1 2124 17 1370 2011 124268 27371 3.74866 3.74866 -129.695 -3.74866 0 0 1.01997e+06 3529.29 0.04 0.04 0.11 -1 -1 0.04 0.0146133 0.0132243 82 33 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_107.v common 4.76 vpr 64.61 MiB -1 -1 0.12 17676 1 0.02 -1 -1 30212 -1 -1 17 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 29 32 262 224 1 162 78 17 17 289 -1 unnamed_device 24.9 MiB 0.25 1704 837 10204 3081 5451 1672 64.6 MiB 0.05 0.00 4.00332 3.52002 -104.505 -3.52002 3.52002 0.24 0.000266925 0.000244771 0.0181439 0.016651 -1 -1 -1 -1 34 2235 27 6.99608e+06 250167 618332. 2139.56 3.12 0.149414 0.130029 25762 151098 -1 1839 33 1724 2185 236919 81430 3.10977 3.10977 -108.554 -3.10977 0 0 787024. 2723.27 0.03 0.10 0.08 -1 -1 0.03 0.029701 0.0266071 67 31 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_108.v common 5.46 vpr 63.99 MiB -1 -1 0.13 17676 1 0.02 -1 -1 30164 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65524 32 32 278 238 1 178 79 17 17 289 -1 unnamed_device 24.9 MiB 0.27 2344 802 11233 4665 6317 251 64.0 MiB 0.05 0.00 4.87466 3.81986 -117.727 -3.81986 3.81986 0.25 0.000293201 0.000268469 0.0227949 0.020989 -1 -1 -1 -1 36 2662 38 6.99608e+06 220735 648988. 2245.63 3.82 0.16388 0.143411 26050 158493 -1 1945 22 1737 2335 205163 46980 3.35647 3.35647 -125.635 -3.35647 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0146639 0.0130972 70 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_109.v common 3.50 vpr 64.76 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29776 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 373 300 1 230 85 17 17 289 -1 unnamed_device 25.2 MiB 0.35 2524 1290 13291 4296 7426 1569 64.8 MiB 0.07 0.00 5.14528 3.96644 -137.42 -3.96644 3.96644 0.25 0.000387044 0.000354926 0.0287595 0.0262542 -1 -1 -1 -1 44 2878 34 6.99608e+06 323745 787024. 2723.27 1.73 0.151986 0.133028 27778 195446 -1 2429 20 1825 2644 204826 43184 3.64925 3.64925 -135.828 -3.64925 0 0 997811. 3452.63 0.04 0.05 0.11 -1 -1 0.04 0.0179987 0.0161854 100 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_110.v common 2.92 vpr 64.68 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29828 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 31 32 265 230 1 170 78 17 17 289 -1 unnamed_device 25.2 MiB 0.22 1901 926 8378 2454 4499 1425 64.7 MiB 0.05 0.00 3.62338 3.26538 -103.352 -3.26538 3.26538 0.26 0.000272319 0.000249627 0.0194942 0.0180456 -1 -1 -1 -1 38 2049 20 6.99608e+06 220735 678818. 2348.85 1.28 0.102417 0.0892263 26626 170182 -1 1809 21 1209 1714 135631 28455 2.80117 2.80117 -107.376 -2.80117 0 0 902133. 3121.57 0.03 0.04 0.17 -1 -1 0.03 0.0141216 0.0125816 67 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_111.v common 2.51 vpr 65.15 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29804 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66712 32 32 349 286 1 207 82 17 17 289 -1 unnamed_device 25.6 MiB 0.27 2683 1135 10584 3164 6747 673 65.1 MiB 0.06 0.00 4.36937 3.54449 -120.669 -3.54449 3.54449 0.25 0.000338843 0.000311513 0.0217633 0.0199616 -1 -1 -1 -1 38 2762 21 6.99608e+06 264882 678818. 2348.85 0.89 0.0998171 0.0884553 26626 170182 -1 2311 19 1299 1882 133571 29409 3.16766 3.16766 -121.59 -3.16766 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0163812 0.0147286 89 57 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_112.v common 3.05 vpr 65.50 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29576 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67072 31 32 396 325 1 257 88 17 17 289 -1 unnamed_device 26.0 MiB 0.29 2720 1315 14128 4475 8272 1381 65.5 MiB 0.08 0.00 6.02652 4.44482 -155.897 -4.44482 4.44482 0.26 0.000742385 0.000711038 0.0330194 0.0304111 -1 -1 -1 -1 36 3582 39 6.99608e+06 367892 648988. 2245.63 1.27 0.133571 0.118438 26050 158493 -1 2929 30 2912 4166 446962 115122 4.4407 4.4407 -163.878 -4.4407 0 0 828058. 2865.25 0.03 0.10 0.08 -1 -1 0.03 0.0236603 0.0210998 111 91 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_113.v common 2.45 vpr 65.07 MiB -1 -1 0.11 18052 1 0.02 -1 -1 29604 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66636 32 32 303 262 1 189 80 17 17 289 -1 unnamed_device 25.0 MiB 0.32 1997 1013 12808 5361 7263 184 65.1 MiB 0.06 0.00 4.02834 3.18879 -114.113 -3.18879 3.18879 0.24 0.00029145 0.000266248 0.0237704 0.0217697 -1 -1 -1 -1 40 2271 23 6.99608e+06 235451 706193. 2443.58 0.77 0.0897322 0.0787789 26914 176310 -1 1978 19 1566 2160 160897 35900 2.92196 2.92196 -113.469 -2.92196 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0177855 0.0158654 80 57 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_114.v common 2.89 vpr 64.03 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29764 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65568 32 32 290 244 1 174 79 17 17 289 -1 unnamed_device 25.2 MiB 0.25 2070 991 12078 3761 7335 982 64.0 MiB 0.07 0.00 3.92883 3.42763 -115.198 -3.42763 3.42763 0.25 0.000352015 0.00032687 0.0293293 0.0270993 -1 -1 -1 -1 44 2260 49 6.99608e+06 220735 787024. 2723.27 1.27 0.11646 0.102895 27778 195446 -1 1939 20 1462 2114 176026 37248 3.13262 3.13262 -118.27 -3.13262 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0141357 0.0126608 70 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_115.v common 3.03 vpr 64.48 MiB -1 -1 0.14 17976 1 0.03 -1 -1 29776 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 318 257 1 190 81 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2008 1061 12156 3939 6984 1233 64.5 MiB 0.06 0.00 4.55868 4.12158 -127.831 -4.12158 4.12158 0.34 0.000319482 0.00029223 0.0286941 0.0265897 -1 -1 -1 -1 36 2636 26 6.99608e+06 250167 648988. 2245.63 1.09 0.120052 0.106785 26050 158493 -1 2264 21 1654 2305 182456 39548 3.99926 3.99926 -138.156 -3.99926 0 0 828058. 2865.25 0.05 0.08 0.14 -1 -1 0.05 0.0252004 0.0226623 79 30 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_116.v common 3.84 vpr 64.70 MiB -1 -1 0.21 18060 1 0.04 -1 -1 30232 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 29 32 324 268 1 193 80 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2038 850 7992 3080 4019 893 64.7 MiB 0.04 0.00 4.14059 3.42459 -102.439 -3.42459 3.42459 0.24 0.000309691 0.000283343 0.0167648 0.0154227 -1 -1 -1 -1 38 2478 27 6.99608e+06 279598 678818. 2348.85 1.97 0.15036 0.131366 26626 170182 -1 1937 19 1363 2005 132397 30881 3.27106 3.27106 -107.497 -3.27106 0 0 902133. 3121.57 0.03 0.04 0.15 -1 -1 0.03 0.0152913 0.0137551 85 55 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_117.v common 4.11 vpr 65.06 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29792 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66624 32 32 393 312 1 234 83 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2763 1341 14303 4864 7770 1669 65.1 MiB 0.08 0.00 6.04713 5.29533 -174.708 -5.29533 5.29533 0.25 0.000363933 0.000332944 0.0312788 0.0287185 -1 -1 -1 -1 48 3515 28 6.99608e+06 279598 865456. 2994.66 2.34 0.196802 0.172935 28354 207349 -1 2907 22 1926 2921 248278 49536 4.46704 4.46704 -168.361 -4.46704 0 0 1.05005e+06 3633.38 0.04 0.07 0.11 -1 -1 0.04 0.0224785 0.02012 102 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_118.v common 3.22 vpr 64.43 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29936 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65980 31 32 229 197 1 138 78 17 17 289 -1 unnamed_device 24.9 MiB 0.38 1665 866 10038 3879 5332 827 64.4 MiB 0.04 0.00 3.45398 3.07808 -95.6005 -3.07808 3.07808 0.25 0.00025341 0.000231039 0.0176736 0.0161604 -1 -1 -1 -1 34 1957 19 6.99608e+06 220735 618332. 2139.56 1.45 0.11107 0.0962653 25762 151098 -1 1727 19 948 1543 115724 25796 2.76232 2.76232 -99.9411 -2.76232 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0119476 0.0106754 55 4 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_119.v common 3.17 vpr 65.16 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30156 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66724 32 32 412 334 1 258 87 17 17 289 -1 unnamed_device 25.6 MiB 0.30 3136 1376 11799 3682 6020 2097 65.2 MiB 0.06 0.00 6.25193 4.95808 -168.612 -4.95808 4.95808 0.35 0.000374179 0.000341467 0.0250565 0.0229553 -1 -1 -1 -1 36 3619 37 6.99608e+06 338461 648988. 2245.63 1.34 0.128163 0.113155 26050 158493 -1 2910 20 2239 2839 225407 51024 5.3834 5.3834 -185.015 -5.3834 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0193173 0.017444 114 90 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_120.v common 8.25 vpr 65.29 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30212 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66852 32 32 376 318 1 253 85 17 17 289 -1 unnamed_device 25.6 MiB 0.30 2503 1284 12919 4933 5948 2038 65.3 MiB 0.07 0.00 5.63182 4.45298 -163.199 -4.45298 4.45298 0.25 0.000344204 0.000305634 0.0255725 0.0233133 -1 -1 -1 -1 36 3534 41 6.99608e+06 309029 648988. 2245.63 6.45 0.227881 0.19988 26050 158493 -1 2786 22 2693 3443 310767 66326 4.37485 4.37485 -164.891 -4.37485 0 0 828058. 2865.25 0.03 0.07 0.17 -1 -1 0.03 0.0187806 0.0168388 105 96 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_121.v common 3.52 vpr 65.28 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30160 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66848 32 32 360 293 1 219 84 17 17 289 -1 unnamed_device 25.2 MiB 0.25 2367 1051 11247 3952 5722 1573 65.3 MiB 0.05 0.00 4.26889 3.47593 -117.199 -3.47593 3.47593 0.26 0.000336143 0.000306239 0.022991 0.021056 -1 -1 -1 -1 44 2721 42 6.99608e+06 294314 787024. 2723.27 1.71 0.152173 0.133648 27778 195446 -1 1977 21 1581 2145 160989 36030 3.25147 3.25147 -116.771 -3.25147 0 0 997811. 3452.63 0.05 0.07 0.16 -1 -1 0.05 0.0257259 0.0230873 93 60 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_122.v common 9.91 vpr 65.45 MiB -1 -1 0.13 17840 1 0.03 -1 -1 29812 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67020 32 32 396 299 1 231 85 17 17 289 -1 unnamed_device 26.0 MiB 0.30 2469 1280 14965 4476 8929 1560 65.4 MiB 0.08 0.00 6.28253 5.57594 -163.801 -5.57594 5.57594 0.25 0.000370225 0.000338122 0.0321979 0.0295165 -1 -1 -1 -1 38 3513 25 6.99608e+06 309029 678818. 2348.85 8.19 0.201075 0.176852 26626 170182 -1 2951 22 2194 3313 270278 56814 5.12565 5.12565 -169.601 -5.12565 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0204029 0.0183752 99 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_123.v common 2.18 vpr 64.52 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29792 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 30 32 224 207 1 134 75 17 17 289 -1 unnamed_device 24.9 MiB 0.24 1623 599 8449 2065 6066 318 64.5 MiB 0.04 0.00 2.83666 2.33546 -84.6639 -2.33546 2.33546 0.25 0.000555342 0.00051864 0.0194883 0.0180519 -1 -1 -1 -1 34 1695 48 6.99608e+06 191304 618332. 2139.56 0.65 0.0682305 0.0598421 25762 151098 -1 1398 20 868 1102 100646 25554 2.33678 2.33678 -94.189 -2.33678 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0115737 0.0102789 52 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_124.v common 2.81 vpr 64.67 MiB -1 -1 0.13 17676 1 0.02 -1 -1 29812 -1 -1 15 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 30 32 286 239 1 159 77 17 17 289 -1 unnamed_device 24.9 MiB 0.91 1725 902 8879 3004 4356 1519 64.7 MiB 0.04 0.00 4.10447 3.92803 -130.612 -3.92803 3.92803 0.24 0.000281139 0.000257365 0.0174054 0.0159733 -1 -1 -1 -1 34 2176 27 6.99608e+06 220735 618332. 2139.56 0.56 0.068423 0.0600819 25762 151098 -1 1899 22 1246 1955 169232 36091 3.59731 3.59731 -136.68 -3.59731 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0152632 0.0136748 70 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_125.v common 3.35 vpr 64.34 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29168 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 296 247 1 182 79 17 17 289 -1 unnamed_device 25.2 MiB 0.20 1971 882 13261 5570 7431 260 64.3 MiB 0.09 0.00 4.19149 3.78235 -133.321 -3.78235 3.78235 0.29 0.000445199 0.000403688 0.0373451 0.0341953 -1 -1 -1 -1 38 2651 49 6.99608e+06 220735 678818. 2348.85 1.75 0.126489 0.111927 26626 170182 -1 2020 20 1450 2457 219315 48983 3.62081 3.62081 -134.809 -3.62081 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0146507 0.0131502 74 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_126.v common 2.16 vpr 64.50 MiB -1 -1 0.14 18056 1 0.02 -1 -1 29884 -1 -1 19 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 25 32 216 194 1 134 76 17 17 289 -1 unnamed_device 25.0 MiB 0.25 1590 696 11596 3751 6795 1050 64.5 MiB 0.04 0.00 4.10053 3.35753 -84.3952 -3.35753 3.35753 0.25 0.000220573 0.000201876 0.0175116 0.016058 -1 -1 -1 -1 36 1574 20 6.99608e+06 279598 648988. 2245.63 0.51 0.054351 0.0477519 26050 158493 -1 1398 21 929 1335 101544 22940 3.09097 3.09097 -90.8946 -3.09097 0 0 828058. 2865.25 0.04 0.04 0.08 -1 -1 0.04 0.0146461 0.0129751 57 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_127.v common 2.88 vpr 65.38 MiB -1 -1 0.13 17528 1 0.04 -1 -1 30176 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66952 32 32 376 307 1 230 83 17 17 289 -1 unnamed_device 25.6 MiB 0.45 2657 1316 7463 1720 5150 593 65.4 MiB 0.05 0.00 4.40039 3.97548 -133.176 -3.97548 3.97548 0.25 0.000350248 0.000315913 0.016928 0.0155579 -1 -1 -1 -1 38 3462 44 6.99608e+06 279598 678818. 2348.85 1.00 0.108019 0.0954574 26626 170182 -1 2797 24 2179 3377 250295 53465 4.20392 4.20392 -145.444 -4.20392 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0211822 0.0189813 99 72 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_128.v common 4.42 vpr 65.54 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29820 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67112 31 32 409 331 1 257 86 17 17 289 -1 unnamed_device 25.6 MiB 0.29 3057 1328 14639 4861 7943 1835 65.5 MiB 0.08 0.00 5.90204 4.55497 -151.39 -4.55497 4.55497 0.25 0.00036635 0.000334698 0.0308268 0.0282486 -1 -1 -1 -1 42 3264 47 6.99608e+06 338461 744469. 2576.02 2.69 0.236746 0.209256 27202 183097 -1 2636 21 2145 2960 233871 50459 3.92175 3.92175 -144.746 -3.92175 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0203923 0.0184184 114 90 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_001.v common 4.41 vpr 64.49 MiB -1 -1 0.19 18436 14 0.23 -1 -1 32268 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 32 32 277 309 1 196 84 17 17 289 -1 unnamed_device 24.9 MiB 0.78 3031 1205 13626 4599 7190 1837 64.5 MiB 0.16 0.00 11.4241 8.56631 -174.636 -8.56631 8.56631 0.24 0.00119097 0.00110789 0.0820653 0.0761529 -1 -1 -1 -1 40 2941 23 6.79088e+06 269440 706193. 2443.58 1.87 0.27365 0.243248 26254 175826 -1 2711 18 1428 4274 219784 51179 7.12477 7.12477 -158.977 -7.12477 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0219342 0.0199651 135 183 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_002.v common 3.93 vpr 64.29 MiB -1 -1 0.18 18440 14 0.33 -1 -1 32040 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 30 32 272 304 1 199 83 17 17 289 -1 unnamed_device 25.1 MiB 0.45 2323 1121 7283 1658 4725 900 64.3 MiB 0.06 0.00 9.21432 7.55348 -154.172 -7.55348 7.55348 0.25 0.000649361 0.00061241 0.0264904 0.0245894 -1 -1 -1 -1 38 2991 20 6.79088e+06 282912 678818. 2348.85 1.69 0.220787 0.195563 25966 169698 -1 2398 20 1400 3922 178800 44179 6.62003 6.62003 -146.847 -6.62003 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0235963 0.0214056 130 184 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_003.v common 3.30 vpr 64.28 MiB -1 -1 0.15 18052 11 0.20 -1 -1 32452 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65824 32 32 280 312 1 194 83 17 17 289 -1 unnamed_device 24.9 MiB 0.67 2611 1308 5483 1021 4219 243 64.3 MiB 0.05 0.00 9.0712 6.64585 -143.643 -6.64585 6.64585 0.27 0.000440044 0.000403629 0.0264756 0.0247267 -1 -1 -1 -1 32 4014 47 6.79088e+06 255968 586450. 2029.24 0.98 0.126559 0.113318 24814 144142 -1 2998 23 1611 5320 356143 96112 6.11518 6.11518 -146.285 -6.11518 0 0 744469. 2576.02 0.03 0.10 0.08 -1 -1 0.03 0.0310327 0.0279645 132 186 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_004.v common 5.13 vpr 64.30 MiB -1 -1 0.16 18284 12 0.37 -1 -1 32692 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 29 32 275 307 1 194 86 17 17 289 -1 unnamed_device 25.2 MiB 0.49 2342 1180 5189 1017 3857 315 64.3 MiB 0.04 0.00 9.35225 7.37182 -142.972 -7.37182 7.37182 0.26 0.00044831 0.00041197 0.0190445 0.0176998 -1 -1 -1 -1 32 3270 50 6.79088e+06 336800 586450. 2029.24 2.83 0.273476 0.241544 24814 144142 -1 2476 22 1379 3781 200348 47482 6.53383 6.53383 -138.939 -6.53383 0 0 744469. 2576.02 0.03 0.07 0.09 -1 -1 0.03 0.0330859 0.0298846 141 190 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_005.v common 6.99 vpr 63.98 MiB -1 -1 0.18 18436 13 0.24 -1 -1 32424 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65512 32 32 302 334 1 227 87 17 17 289 -1 unnamed_device 25.2 MiB 0.34 2826 1422 5847 1175 4382 290 64.0 MiB 0.05 0.00 10.4933 7.73127 -164.781 -7.73127 7.73127 0.24 0.000482411 0.000442208 0.0217472 0.0201042 -1 -1 -1 -1 36 3783 23 6.79088e+06 309856 648988. 2245.63 5.01 0.257872 0.227573 25390 158009 -1 3208 19 1670 4461 243005 57993 6.89412 6.89412 -162.383 -6.89412 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0245951 0.0223687 155 208 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_006.v common 3.67 vpr 64.34 MiB -1 -1 0.19 18436 13 0.23 -1 -1 32428 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 292 324 1 217 86 17 17 289 -1 unnamed_device 25.2 MiB 0.66 3136 1331 12560 3423 7370 1767 64.3 MiB 0.07 0.00 9.76013 7.28237 -154.711 -7.28237 7.28237 0.24 0.00046408 0.000424198 0.0337388 0.0309128 -1 -1 -1 -1 32 4210 42 6.79088e+06 296384 586450. 2029.24 1.27 0.132124 0.118043 24814 144142 -1 3323 21 1903 5560 319427 73380 6.75647 6.75647 -158.319 -6.75647 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0269225 0.024456 141 198 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_007.v common 2.75 vpr 64.39 MiB -1 -1 0.15 18052 12 0.17 -1 -1 32268 -1 -1 25 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 27 32 229 261 1 165 84 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1861 902 5757 1286 4119 352 64.4 MiB 0.03 0.00 8.53024 6.95672 -126.14 -6.95672 6.95672 0.25 0.000354372 0.000324783 0.013746 0.0126635 -1 -1 -1 -1 28 2519 27 6.79088e+06 336800 531479. 1839.03 1.09 0.120253 0.106175 23950 126010 -1 2066 18 1046 2497 128398 31899 5.82898 5.82898 -118.677 -5.82898 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0178246 0.0161843 109 150 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_008.v common 6.07 vpr 63.68 MiB -1 -1 0.16 17908 12 0.17 -1 -1 32412 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65212 31 32 229 261 1 181 82 17 17 289 -1 unnamed_device 24.1 MiB 0.28 2040 1181 5956 1284 4146 526 63.7 MiB 0.04 0.00 6.73834 6.21924 -138.39 -6.21924 6.21924 0.24 0.000362618 0.00032571 0.0141613 0.0129176 -1 -1 -1 -1 30 3719 48 6.79088e+06 255968 556674. 1926.21 4.29 0.201748 0.178617 24526 138013 -1 2630 18 1198 3419 188591 45425 5.43491 5.43491 -136.039 -5.43491 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0184844 0.0167371 110 138 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_009.v common 3.21 vpr 64.70 MiB -1 -1 0.15 17668 12 0.19 -1 -1 32372 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 31 32 235 267 1 189 83 17 17 289 -1 unnamed_device 24.9 MiB 0.25 2543 1227 8543 2270 5212 1061 64.7 MiB 0.05 0.00 8.6557 7.27148 -152.778 -7.27148 7.27148 0.24 0.000361802 0.000331237 0.0195722 0.0179241 -1 -1 -1 -1 40 2618 15 6.79088e+06 269440 706193. 2443.58 1.38 0.119766 0.105239 26254 175826 -1 2483 16 1033 2770 145853 34562 6.49468 6.49468 -148.795 -6.49468 0 0 926341. 3205.33 0.03 0.04 0.10 -1 -1 0.03 0.0170104 0.0154989 110 144 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_010.v common 2.55 vpr 64.77 MiB -1 -1 0.15 17668 13 0.17 -1 -1 32296 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 250 282 1 179 81 17 17 289 -1 unnamed_device 24.9 MiB 0.40 2565 1165 6206 1220 4462 524 64.8 MiB 0.04 0.00 10.5547 7.36881 -166.317 -7.36881 7.36881 0.24 0.000391536 0.000359231 0.016511 0.0152106 -1 -1 -1 -1 28 3160 27 6.79088e+06 229024 531479. 1839.03 0.64 0.0799198 0.0709347 23950 126010 -1 2659 17 1153 2882 165722 40410 6.36594 6.36594 -163.044 -6.36594 0 0 648988. 2245.63 0.03 0.06 0.07 -1 -1 0.03 0.0254959 0.022977 110 156 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_011.v common 3.94 vpr 64.14 MiB -1 -1 0.15 18060 12 0.16 -1 -1 32264 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65684 30 32 216 248 1 163 81 17 17 289 -1 unnamed_device 24.5 MiB 0.58 2068 857 10756 4429 6016 311 64.1 MiB 0.05 0.00 8.56921 6.97458 -139.004 -6.97458 6.97458 0.24 0.000343467 0.000307099 0.0234334 0.0214136 -1 -1 -1 -1 38 2181 21 6.79088e+06 255968 678818. 2348.85 1.84 0.135883 0.119614 25966 169698 -1 1757 15 890 2413 117726 29155 5.82898 5.82898 -125.97 -5.82898 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0154421 0.0141457 101 128 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_012.v common 3.54 vpr 64.31 MiB -1 -1 0.26 18056 12 0.13 -1 -1 32112 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 236 268 1 168 82 17 17 289 -1 unnamed_device 24.5 MiB 0.35 2572 1214 8982 2331 5744 907 64.3 MiB 0.05 0.00 8.22306 6.49083 -156.629 -6.49083 6.49083 0.24 0.000363246 0.000331103 0.0206227 0.0189085 -1 -1 -1 -1 36 2644 29 6.79088e+06 242496 648988. 2245.63 1.41 0.132842 0.116763 25390 158009 -1 2417 16 966 2757 155170 36040 6.09296 6.09296 -155.583 -6.09296 0 0 828058. 2865.25 0.05 0.07 0.15 -1 -1 0.05 0.0296218 0.0271121 104 142 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_013.v common 4.32 vpr 64.31 MiB -1 -1 0.17 18440 13 0.25 -1 -1 32384 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 283 315 1 215 84 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2835 1334 6489 1499 4360 630 64.3 MiB 0.04 0.00 11.6534 8.17439 -174.342 -8.17439 8.17439 0.25 0.000438675 0.000401184 0.0187568 0.0172093 -1 -1 -1 -1 32 3619 35 6.79088e+06 269440 586450. 2029.24 2.19 0.200192 0.177548 24814 144142 -1 3033 18 1340 3636 199882 46955 7.21431 7.21431 -168.629 -7.21431 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0230824 0.0210502 133 189 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_014.v common 5.12 vpr 65.04 MiB -1 -1 0.18 18440 14 0.28 -1 -1 32424 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66600 32 32 303 335 1 227 86 17 17 289 -1 unnamed_device 25.2 MiB 0.69 3489 1455 10292 2847 6856 589 65.0 MiB 0.07 0.00 11.4534 8.74059 -185.972 -8.74059 8.74059 0.25 0.000488456 0.000447227 0.0303164 0.0277935 -1 -1 -1 -1 40 3374 27 6.79088e+06 296384 706193. 2443.58 2.50 0.277905 0.246685 26254 175826 -1 3075 32 1530 4441 421130 190943 7.41807 7.41807 -171.541 -7.41807 0 0 926341. 3205.33 0.03 0.17 0.10 -1 -1 0.03 0.0436618 0.0390518 156 209 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_015.v common 3.18 vpr 64.39 MiB -1 -1 0.25 18056 11 0.15 -1 -1 32288 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 29 32 225 257 1 169 84 17 17 289 -1 unnamed_device 24.7 MiB 0.34 2298 1064 6855 1570 4646 639 64.4 MiB 0.04 0.00 8.40469 6.70263 -132.295 -6.70263 6.70263 0.25 0.000348348 0.000318449 0.0154087 0.0141195 -1 -1 -1 -1 30 2425 21 6.79088e+06 309856 556674. 1926.21 1.15 0.119115 0.105149 24526 138013 -1 2231 17 985 2602 130423 31578 5.86469 5.86469 -127.664 -5.86469 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0175344 0.0160361 108 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_016.v common 5.96 vpr 65.10 MiB -1 -1 0.19 18436 12 0.24 -1 -1 32692 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 32 32 301 333 1 219 91 17 17 289 -1 unnamed_device 25.2 MiB 0.74 2958 1459 10087 2738 6560 789 65.1 MiB 0.06 0.00 9.40585 7.27585 -159.598 -7.27585 7.27585 0.24 0.000475027 0.000434934 0.0268074 0.0244932 -1 -1 -1 -1 32 4260 32 6.79088e+06 363744 586450. 2029.24 3.49 0.246475 0.218856 24814 144142 -1 3465 23 1720 5638 455130 145122 6.73753 6.73753 -163.315 -6.73753 0 0 744469. 2576.02 0.03 0.12 0.08 -1 -1 0.03 0.0287396 0.026003 152 207 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_017.v common 3.79 vpr 64.29 MiB -1 -1 0.17 18440 14 0.22 -1 -1 32384 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 277 309 1 212 86 17 17 289 -1 unnamed_device 24.9 MiB 0.60 2850 1312 6890 1429 5359 102 64.3 MiB 0.05 0.00 10.5304 7.97872 -168.371 -7.97872 7.97872 0.25 0.000606839 0.000536353 0.0197275 0.018177 -1 -1 -1 -1 36 3500 42 6.79088e+06 296384 648988. 2245.63 1.53 0.148978 0.131812 25390 158009 -1 2790 18 1406 4143 221995 51462 7.21088 7.21088 -159.551 -7.21088 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0218356 0.0197917 131 183 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_018.v common 3.27 vpr 64.32 MiB -1 -1 0.15 18052 12 0.14 -1 -1 31972 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 32 32 227 259 1 171 82 17 17 289 -1 unnamed_device 24.5 MiB 0.54 2494 1086 7736 1808 5543 385 64.3 MiB 0.04 0.00 8.77612 6.78318 -155.712 -6.78318 6.78318 0.25 0.000354223 0.000323322 0.018174 0.0166131 -1 -1 -1 -1 30 2715 18 6.79088e+06 242496 556674. 1926.21 1.25 0.12632 0.111156 24526 138013 -1 2226 14 889 2523 130718 31522 5.88818 5.88818 -146.658 -5.88818 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0162673 0.0148851 108 133 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_019.v common 2.55 vpr 64.02 MiB -1 -1 0.14 17908 10 0.10 -1 -1 32064 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65556 30 32 175 207 1 131 75 17 17 289 -1 unnamed_device 24.9 MiB 0.22 1668 806 10503 2849 6815 839 64.0 MiB 0.05 0.00 6.26916 4.98721 -124.709 -4.98721 4.98721 0.26 0.000478461 0.000454715 0.023872 0.02204 -1 -1 -1 -1 32 1826 25 6.79088e+06 175136 586450. 2029.24 0.94 0.0901868 0.0792017 24814 144142 -1 1616 13 591 1361 77271 18739 4.34281 4.34281 -119.196 -4.34281 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0113524 0.0103305 65 87 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_020.v common 3.03 vpr 63.89 MiB -1 -1 0.16 18052 13 0.16 -1 -1 32244 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65428 31 32 231 263 1 178 83 17 17 289 -1 unnamed_device 24.5 MiB 0.50 2365 1084 11783 3551 6465 1767 63.9 MiB 0.06 0.00 8.87866 7.49722 -158.804 -7.49722 7.49722 0.25 0.000362742 0.000331666 0.0270047 0.0247456 -1 -1 -1 -1 28 3316 28 6.79088e+06 269440 531479. 1839.03 0.98 0.0892173 0.0800554 23950 126010 -1 2618 16 1153 2704 167677 39802 6.33372 6.33372 -153.752 -6.33372 0 0 648988. 2245.63 0.03 0.05 0.07 -1 -1 0.03 0.0199065 0.0183664 109 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_021.v common 3.60 vpr 64.00 MiB -1 -1 0.21 18440 13 0.32 -1 -1 33084 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65536 32 32 304 336 1 215 87 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2586 1376 10839 2728 7031 1080 64.0 MiB 0.09 0.00 8.96492 7.91997 -166.691 -7.91997 7.91997 0.25 0.000464279 0.000424653 0.0425461 0.0392674 -1 -1 -1 -1 34 3753 44 6.79088e+06 309856 618332. 2139.56 1.41 0.199259 0.177438 25102 150614 -1 3173 21 1808 5062 277517 63992 7.25767 7.25767 -167.443 -7.25767 0 0 787024. 2723.27 0.03 0.08 0.08 -1 -1 0.03 0.029666 0.0271387 145 210 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_022.v common 5.06 vpr 64.92 MiB -1 -1 0.24 18440 13 0.26 -1 -1 32316 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66480 32 32 288 320 1 216 86 17 17 289 -1 unnamed_device 25.0 MiB 0.54 3098 1371 8969 2158 5992 819 64.9 MiB 0.06 0.00 10.2409 8.00961 -172.114 -8.00961 8.00961 0.25 0.000455242 0.000416838 0.0273004 0.025115 -1 -1 -1 -1 48 3044 22 6.79088e+06 296384 865456. 2994.66 2.49 0.280748 0.25145 27694 206865 -1 2693 35 1210 3789 333870 151059 6.84611 6.84611 -157.334 -6.84611 0 0 1.05005e+06 3633.38 0.05 0.14 0.20 -1 -1 0.05 0.0416726 0.0377162 144 194 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_023.v common 2.67 vpr 63.91 MiB -1 -1 0.15 17672 9 0.07 -1 -1 32016 -1 -1 19 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65448 26 32 152 184 1 121 77 17 17 289 -1 unnamed_device 24.5 MiB 0.19 1488 617 5782 1436 3916 430 63.9 MiB 0.03 0.00 6.09263 4.97145 -92.9358 -4.97145 4.97145 0.24 0.000244262 0.000223535 0.0101216 0.00930478 -1 -1 -1 -1 26 1806 27 6.79088e+06 255968 503264. 1741.40 1.15 0.100936 0.0879412 23662 119890 -1 1410 16 621 1418 72154 18823 4.40201 4.40201 -92.9496 -4.40201 0 0 618332. 2139.56 0.02 0.03 0.06 -1 -1 0.02 0.01089 0.00983063 70 76 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_024.v common 10.31 vpr 64.41 MiB -1 -1 0.16 18052 13 0.31 -1 -1 32380 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 32 32 287 319 1 211 88 17 17 289 -1 unnamed_device 24.9 MiB 0.53 2866 1367 5353 1032 4119 202 64.4 MiB 0.04 0.00 10.0962 7.88173 -161.78 -7.88173 7.88173 0.25 0.000449381 0.000411785 0.015309 0.0141099 -1 -1 -1 -1 38 3405 34 6.79088e+06 323328 678818. 2348.85 8.08 0.267815 0.236873 25966 169698 -1 2807 21 1639 4697 237671 55346 7.00707 7.00707 -156.558 -7.00707 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0252728 0.0228831 137 193 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_025.v common 3.06 vpr 63.40 MiB -1 -1 0.11 17668 8 0.07 -1 -1 32008 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64924 32 32 154 186 1 122 81 17 17 289 -1 unnamed_device 24.1 MiB 0.21 1801 751 10056 3801 5079 1176 63.4 MiB 0.04 0.00 5.37538 4.0417 -97.2106 -4.0417 4.0417 0.25 0.000246317 0.000224443 0.0162963 0.0149155 -1 -1 -1 -1 28 2037 20 6.79088e+06 229024 531479. 1839.03 1.53 0.0849702 0.074266 23950 126010 -1 1607 16 643 1316 83382 21230 3.71266 3.71266 -99.3645 -3.71266 0 0 648988. 2245.63 0.02 0.03 0.07 -1 -1 0.02 0.0106624 0.00961875 64 60 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_026.v common 5.45 vpr 64.21 MiB -1 -1 0.30 18056 15 0.21 -1 -1 32388 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65752 32 32 254 286 1 199 85 17 17 289 -1 unnamed_device 24.9 MiB 0.57 2483 1240 9943 2138 6866 939 64.2 MiB 0.06 0.00 9.80857 8.30542 -172.111 -8.30542 8.30542 0.24 0.000413589 0.000379237 0.0245435 0.0225401 -1 -1 -1 -1 30 3906 37 6.79088e+06 282912 556674. 1926.21 3.13 0.211236 0.18686 24526 138013 -1 2898 17 1285 3527 205171 47925 7.42577 7.42577 -170.534 -7.42577 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0194069 0.0176652 125 160 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_027.v common 5.76 vpr 64.77 MiB -1 -1 0.24 18436 13 0.26 -1 -1 32408 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 32 32 260 292 1 195 85 17 17 289 -1 unnamed_device 24.9 MiB 0.59 2809 1235 6223 1362 4311 550 64.8 MiB 0.04 0.00 9.72987 7.14037 -153.834 -7.14037 7.14037 0.25 0.000409309 0.00037536 0.0166027 0.015261 -1 -1 -1 -1 28 3847 37 6.79088e+06 282912 531479. 1839.03 3.35 0.189471 0.167684 23950 126010 -1 3140 18 1510 4391 259846 62056 6.54163 6.54163 -159.303 -6.54163 0 0 648988. 2245.63 0.02 0.07 0.10 -1 -1 0.02 0.0221816 0.0201556 121 166 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_028.v common 3.24 vpr 64.31 MiB -1 -1 0.16 18440 13 0.24 -1 -1 32460 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 279 311 1 197 86 17 17 289 -1 unnamed_device 25.3 MiB 0.42 3092 1312 10670 2502 6881 1287 64.3 MiB 0.06 0.00 10.7137 7.55772 -167.165 -7.55772 7.55772 0.25 0.000496424 0.000437606 0.0278823 0.0255608 -1 -1 -1 -1 34 3511 26 6.79088e+06 296384 618332. 2139.56 1.12 0.149524 0.132934 25102 150614 -1 3012 26 1394 4168 319805 117147 6.53742 6.53742 -161.936 -6.53742 0 0 787024. 2723.27 0.03 0.11 0.08 -1 -1 0.03 0.0306397 0.0275996 137 185 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_029.v common 4.78 vpr 64.34 MiB -1 -1 0.21 18048 12 0.14 -1 -1 32216 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65884 32 32 238 270 1 179 83 17 17 289 -1 unnamed_device 24.9 MiB 0.53 2215 1077 7463 1926 5127 410 64.3 MiB 0.04 0.00 8.90447 7.16817 -157.085 -7.16817 7.16817 0.24 0.000360981 0.000329659 0.0183015 0.016781 -1 -1 -1 -1 30 2953 38 6.79088e+06 255968 556674. 1926.21 2.72 0.213179 0.189075 24526 138013 -1 2363 15 977 2427 125582 30236 6.04043 6.04043 -146.514 -6.04043 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0233315 0.0211966 106 144 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_030.v common 2.66 vpr 63.57 MiB -1 -1 0.15 18056 11 0.13 -1 -1 32052 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65092 30 32 213 245 1 164 83 17 17 289 -1 unnamed_device 24.2 MiB 0.54 2157 906 8903 2145 5507 1251 63.6 MiB 0.05 0.00 8.36704 6.05468 -133.402 -6.05468 6.05468 0.26 0.000335989 0.00030755 0.0246192 0.02286 -1 -1 -1 -1 30 2680 33 6.79088e+06 282912 556674. 1926.21 0.66 0.0826156 0.0734008 24526 138013 -1 2099 20 1066 2662 146556 35824 5.18426 5.18426 -128.437 -5.18426 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0169118 0.0152834 98 125 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_031.v common 2.87 vpr 64.38 MiB -1 -1 0.15 18056 11 0.15 -1 -1 32252 -1 -1 22 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 28 32 227 259 1 169 82 17 17 289 -1 unnamed_device 24.9 MiB 0.19 2381 1026 10050 2724 5924 1402 64.4 MiB 0.05 0.00 8.60731 6.75879 -129.565 -6.75879 6.75879 0.24 0.000355493 0.000325819 0.0222164 0.0203714 -1 -1 -1 -1 32 2423 27 6.79088e+06 296384 586450. 2029.24 1.21 0.137782 0.121045 24814 144142 -1 2131 17 976 2549 133309 32630 5.82893 5.82893 -125.134 -5.82893 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0170262 0.0153374 110 145 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_032.v common 3.22 vpr 64.91 MiB -1 -1 0.14 18052 12 0.23 -1 -1 32352 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 274 306 1 205 88 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2875 1212 13153 3436 7680 2037 64.9 MiB 0.07 0.00 9.54873 6.775 -163.89 -6.775 6.775 0.25 0.000426219 0.000390708 0.0317792 0.0291933 -1 -1 -1 -1 38 3105 28 6.79088e+06 323328 678818. 2348.85 1.00 0.14567 0.129269 25966 169698 -1 2513 19 1288 3419 170230 41113 6.11529 6.11529 -157.306 -6.11529 0 0 902133. 3121.57 0.03 0.05 0.13 -1 -1 0.03 0.0220122 0.0199881 127 180 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_033.v common 2.77 vpr 64.30 MiB -1 -1 0.17 18056 12 0.14 -1 -1 32240 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 31 32 237 269 1 170 84 17 17 289 -1 unnamed_device 24.9 MiB 0.57 2060 1002 6672 1433 5012 227 64.3 MiB 0.04 0.00 7.92332 6.92092 -140.498 -6.92092 6.92092 0.24 0.000365858 0.000335237 0.0155583 0.0142796 -1 -1 -1 -1 34 2714 22 6.79088e+06 282912 618332. 2139.56 0.66 0.0804347 0.070896 25102 150614 -1 2212 17 1038 2779 151082 36854 5.83236 5.83236 -136.839 -5.83236 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0169749 0.0153974 103 146 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_034.v common 4.42 vpr 64.34 MiB -1 -1 0.15 18056 10 0.18 -1 -1 32228 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 29 32 220 252 1 166 80 17 17 289 -1 unnamed_device 24.5 MiB 0.38 2498 1114 12464 4239 6338 1887 64.3 MiB 0.08 0.00 8.45663 5.89864 -127.83 -5.89864 5.89864 0.27 0.000350178 0.000319832 0.0386761 0.0358483 -1 -1 -1 -1 30 2868 39 6.79088e+06 255968 556674. 1926.21 2.44 0.157288 0.139573 24526 138013 -1 2191 15 1009 2745 133799 31948 5.07353 5.07353 -121.877 -5.07353 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0187168 0.0170958 106 135 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_035.v common 4.31 vpr 65.09 MiB -1 -1 0.17 18824 13 0.37 -1 -1 32496 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 32 32 315 347 1 231 87 17 17 289 -1 unnamed_device 25.6 MiB 0.82 3406 1501 8151 1916 5443 792 65.1 MiB 0.06 0.00 10.5847 8.3634 -174.549 -8.3634 8.3634 0.25 0.000512226 0.000469738 0.0256547 0.0235679 -1 -1 -1 -1 34 4177 45 6.79088e+06 309856 618332. 2139.56 1.60 0.155047 0.138288 25102 150614 -1 3221 19 1668 4722 270668 63068 7.30036 7.30036 -169.537 -7.30036 0 0 787024. 2723.27 0.03 0.07 0.09 -1 -1 0.03 0.0268631 0.0244829 155 221 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_036.v common 6.21 vpr 64.89 MiB -1 -1 0.17 18680 14 0.29 -1 -1 32488 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66444 32 32 282 314 1 220 85 17 17 289 -1 unnamed_device 25.2 MiB 0.69 2943 1394 7711 1611 5817 283 64.9 MiB 0.05 0.00 10.4967 7.87598 -171.941 -7.87598 7.87598 0.26 0.000454747 0.000412271 0.021847 0.0200618 -1 -1 -1 -1 32 4122 48 6.79088e+06 282912 586450. 2029.24 3.80 0.264087 0.233687 24814 144142 -1 3384 26 1590 4354 315532 91570 6.90989 6.90989 -166.802 -6.90989 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0278672 0.0250781 141 188 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_037.v common 3.47 vpr 64.29 MiB -1 -1 0.27 18048 12 0.18 -1 -1 31904 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 31 32 241 273 1 167 85 17 17 289 -1 unnamed_device 24.9 MiB 0.81 2245 1124 11617 2830 7151 1636 64.3 MiB 0.06 0.00 9.13651 7.16673 -154.158 -7.16673 7.16673 0.24 0.000402222 0.000371053 0.0298095 0.027394 -1 -1 -1 -1 32 2540 25 6.79088e+06 296384 586450. 2029.24 0.75 0.104561 0.0929539 24814 144142 -1 2194 38 912 2526 247643 119222 6.40858 6.40858 -147.26 -6.40858 0 0 744469. 2576.02 0.03 0.11 0.08 -1 -1 0.03 0.0307068 0.027383 109 150 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_038.v common 4.79 vpr 64.44 MiB -1 -1 0.21 18440 12 0.24 -1 -1 32412 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 31 32 307 339 1 224 88 17 17 289 -1 unnamed_device 25.2 MiB 1.02 2945 1333 7108 1597 4418 1093 64.4 MiB 0.06 0.00 9.92626 7.46598 -153.742 -7.46598 7.46598 0.26 0.000482238 0.000434978 0.0278272 0.0257809 -1 -1 -1 -1 44 3306 50 6.79088e+06 336800 787024. 2723.27 2.00 0.23826 0.210092 27118 194962 -1 2867 17 1292 4003 228351 52035 6.84601 6.84601 -149.478 -6.84601 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0229471 0.0209391 149 216 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_039.v common 3.38 vpr 65.07 MiB -1 -1 0.21 18820 14 0.30 -1 -1 33008 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66632 31 32 293 325 1 210 87 17 17 289 -1 unnamed_device 25.2 MiB 0.62 2863 1260 7191 1526 5185 480 65.1 MiB 0.05 0.00 10.7622 8.34339 -164.83 -8.34339 8.34339 0.25 0.000461007 0.000422205 0.0206457 0.0189982 -1 -1 -1 -1 32 4175 47 6.79088e+06 323328 586450. 2029.24 0.99 0.128067 0.114334 24814 144142 -1 2958 17 1420 4068 211841 50823 7.27357 7.27357 -157.701 -7.27357 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0330715 0.026157 145 202 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_040.v common 3.88 vpr 64.86 MiB -1 -1 0.18 18824 13 0.23 -1 -1 32404 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 31 32 276 308 1 215 92 17 17 289 -1 unnamed_device 25.2 MiB 0.64 2522 1348 10856 2834 7113 909 64.9 MiB 0.06 0.00 9.47173 8.62453 -173.004 -8.62453 8.62453 0.29 0.000440966 0.000404379 0.0276626 0.025418 -1 -1 -1 -1 40 2987 28 6.79088e+06 390688 706193. 2443.58 1.54 0.191963 0.16863 26254 175826 -1 2731 15 1325 3511 178012 43029 7.1786 7.1786 -159.768 -7.1786 0 0 926341. 3205.33 0.03 0.05 0.11 -1 -1 0.03 0.0194924 0.0177471 141 185 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_041.v common 8.44 vpr 64.92 MiB -1 -1 0.18 18440 13 0.23 -1 -1 32424 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 31 32 269 301 1 202 87 17 17 289 -1 unnamed_device 25.2 MiB 0.42 2556 1153 5463 969 4379 115 64.9 MiB 0.04 0.00 9.98527 7.53333 -150.109 -7.53333 7.53333 0.24 0.000423469 0.000387405 0.0151339 0.0139092 -1 -1 -1 -1 38 3092 22 6.79088e+06 323328 678818. 2348.85 6.41 0.234781 0.206989 25966 169698 -1 2670 17 1343 3980 206829 49786 6.58427 6.58427 -142.162 -6.58427 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0206137 0.0188038 132 178 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_042.v common 3.53 vpr 64.59 MiB -1 -1 0.15 18056 12 0.16 -1 -1 32384 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 264 296 1 184 83 17 17 289 -1 unnamed_device 24.6 MiB 0.54 2002 1172 9083 2391 5419 1273 64.6 MiB 0.05 0.00 8.49442 7.30279 -160.079 -7.30279 7.30279 0.25 0.000425324 0.000390776 0.0256692 0.0237463 -1 -1 -1 -1 32 3059 44 6.79088e+06 255968 586450. 2029.24 1.35 0.163263 0.143696 24814 144142 -1 2506 18 1001 2650 149679 35783 6.24413 6.24413 -151.681 -6.24413 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0197901 0.0179497 117 170 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_043.v common 4.74 vpr 64.55 MiB -1 -1 0.35 19212 14 0.36 -1 -1 32704 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 32 32 324 356 1 233 89 17 17 289 -1 unnamed_device 25.2 MiB 0.53 2721 1387 9593 2160 6158 1275 64.6 MiB 0.06 0.00 10.2498 8.60377 -176.638 -8.60377 8.60377 0.36 0.000519234 0.000475246 0.0287265 0.0263298 -1 -1 -1 -1 42 3697 28 6.79088e+06 336800 744469. 2576.02 2.10 0.220451 0.19538 26542 182613 -1 3213 16 1508 4554 251372 60167 7.8443 7.8443 -173.087 -7.8443 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0253925 0.0232663 166 230 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_044.v common 3.17 vpr 64.68 MiB -1 -1 0.16 18052 11 0.17 -1 -1 32184 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 31 32 249 281 1 182 81 17 17 289 -1 unnamed_device 24.9 MiB 0.36 2383 1234 8831 2136 5283 1412 64.7 MiB 0.06 0.00 9.03977 6.55167 -143.832 -6.55167 6.55167 0.26 0.000390614 0.000357326 0.0306504 0.0284119 -1 -1 -1 -1 34 3424 26 6.79088e+06 242496 618332. 2139.56 1.28 0.149155 0.132617 25102 150614 -1 2799 17 1286 3775 224926 52311 5.53137 5.53137 -138.061 -5.53137 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0185385 0.0168386 116 158 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_045.v common 4.04 vpr 64.32 MiB -1 -1 0.18 18436 13 0.24 -1 -1 32404 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 31 32 284 316 1 189 83 17 17 289 -1 unnamed_device 25.2 MiB 0.59 2583 1227 7823 1987 5336 500 64.3 MiB 0.06 0.00 10.3304 8.2347 -167.362 -8.2347 8.2347 0.25 0.00107463 0.00100212 0.0242496 0.0222372 -1 -1 -1 -1 38 3089 31 6.79088e+06 269440 678818. 2348.85 1.79 0.182563 0.160756 25966 169698 -1 2457 17 1102 3538 183777 43994 6.928 6.928 -151.92 -6.928 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0229341 0.020939 137 193 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_046.v common 5.85 vpr 64.33 MiB -1 -1 0.20 18440 12 0.23 -1 -1 32476 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 303 335 1 211 88 17 17 289 -1 unnamed_device 25.2 MiB 0.72 3276 1368 7303 1652 5036 615 64.3 MiB 0.05 0.00 9.50649 7.04019 -156.99 -7.04019 7.04019 0.28 0.000485597 0.000444829 0.0239096 0.0220685 -1 -1 -1 -1 32 4045 46 6.79088e+06 323328 586450. 2029.24 3.39 0.250211 0.22096 24814 144142 -1 3137 20 1473 4574 259310 60569 6.07958 6.07958 -153.718 -6.07958 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0247197 0.0224238 149 209 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_047.v common 4.57 vpr 64.27 MiB -1 -1 0.19 18432 13 0.33 -1 -1 32428 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65812 32 32 272 304 1 193 84 17 17 289 -1 unnamed_device 25.2 MiB 1.10 2365 1209 7587 1894 5178 515 64.3 MiB 0.05 0.00 9.74801 7.69207 -163.114 -7.69207 7.69207 0.26 0.000440032 0.000395698 0.0215181 0.0197213 -1 -1 -1 -1 30 3206 26 6.79088e+06 269440 556674. 1926.21 1.49 0.177988 0.157193 24526 138013 -1 2685 19 1329 3576 180486 43057 6.58083 6.58083 -156.048 -6.58083 0 0 706193. 2443.58 0.03 0.06 0.07 -1 -1 0.03 0.0268247 0.0243982 129 178 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_048.v common 4.15 vpr 64.91 MiB -1 -1 0.17 18436 13 0.29 -1 -1 32272 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 32 32 271 303 1 208 84 17 17 289 -1 unnamed_device 24.9 MiB 0.36 3179 1230 9417 2549 6214 654 64.9 MiB 0.06 0.00 12.3503 7.56546 -162.927 -7.56546 7.56546 0.24 0.000419777 0.000383264 0.0245488 0.0224769 -1 -1 -1 -1 34 3342 25 6.79088e+06 269440 618332. 2139.56 1.96 0.222507 0.197685 25102 150614 -1 2749 20 1287 3531 194100 46258 6.63461 6.63461 -153.875 -6.63461 0 0 787024. 2723.27 0.03 0.06 0.09 -1 -1 0.03 0.0229001 0.0207611 126 177 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_049.v common 4.41 vpr 64.33 MiB -1 -1 0.29 18440 12 0.22 -1 -1 32072 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 288 320 1 213 85 17 17 289 -1 unnamed_device 25.2 MiB 0.73 3237 1350 6781 1616 4569 596 64.3 MiB 0.05 0.00 9.79309 7.26885 -157.003 -7.26885 7.26885 0.29 0.000453889 0.000415087 0.0228808 0.0209913 -1 -1 -1 -1 36 3641 25 6.79088e+06 282912 648988. 2245.63 1.83 0.204078 0.18037 25390 158009 -1 3026 21 1415 4844 275624 62278 6.33013 6.33013 -152.464 -6.33013 0 0 828058. 2865.25 0.03 0.07 0.08 -1 -1 0.03 0.0264261 0.0237997 143 194 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_050.v common 3.94 vpr 65.12 MiB -1 -1 0.18 18824 13 0.26 -1 -1 33052 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 306 338 1 225 90 17 17 289 -1 unnamed_device 25.2 MiB 0.43 2993 1412 5718 1172 4154 392 65.1 MiB 0.05 0.00 9.84216 7.93745 -169.253 -7.93745 7.93745 0.26 0.000506572 0.000441632 0.0199996 0.0184984 -1 -1 -1 -1 34 3731 24 6.79088e+06 350272 618332. 2139.56 1.65 0.183595 0.164168 25102 150614 -1 3234 20 1610 4700 250750 58995 6.64794 6.64794 -157.372 -6.64794 0 0 787024. 2723.27 0.03 0.07 0.09 -1 -1 0.03 0.0260849 0.023678 154 212 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_051.v common 4.60 vpr 64.25 MiB -1 -1 0.15 18296 14 0.25 -1 -1 32688 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 262 294 1 194 83 17 17 289 -1 unnamed_device 24.9 MiB 0.48 2657 1180 4583 839 3547 197 64.2 MiB 0.03 0.00 10.6221 8.57741 -169.869 -8.57741 8.57741 0.25 0.000429716 0.000393141 0.0139303 0.012808 -1 -1 -1 -1 28 3338 31 6.79088e+06 255968 531479. 1839.03 2.48 0.181889 0.160377 23950 126010 -1 2914 20 1463 4240 240521 57665 7.62947 7.62947 -166.279 -7.62947 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.022302 0.0202324 126 168 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_052.v common 3.72 vpr 65.03 MiB -1 -1 0.28 18440 13 0.29 -1 -1 32388 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66592 32 32 291 323 1 211 86 17 17 289 -1 unnamed_device 25.6 MiB 0.57 2869 1258 10481 2943 5987 1551 65.0 MiB 0.07 0.00 10.9668 8.37706 -166.957 -8.37706 8.37706 0.26 0.000452579 0.00041402 0.0351629 0.0326495 -1 -1 -1 -1 32 3983 34 6.79088e+06 296384 586450. 2029.24 1.24 0.15596 0.139386 24814 144142 -1 3104 18 1493 4014 248833 58652 7.1394 7.1394 -164.599 -7.1394 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0277841 0.0252849 141 197 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_053.v common 5.22 vpr 63.88 MiB -1 -1 0.22 18436 13 0.32 -1 -1 32356 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 31 32 302 334 1 219 90 17 17 289 -1 unnamed_device 25.2 MiB 0.71 2984 1375 7929 1755 5579 595 63.9 MiB 0.05 0.00 10.6879 7.80965 -168.49 -7.80965 7.80965 0.26 0.000508235 0.000468038 0.0234246 0.0216387 -1 -1 -1 -1 44 3117 28 6.79088e+06 363744 787024. 2723.27 2.60 0.247217 0.219943 27118 194962 -1 2818 25 1372 3980 318440 129638 6.99593 6.99593 -160.634 -6.99593 0 0 997811. 3452.63 0.04 0.11 0.10 -1 -1 0.04 0.0310593 0.0280909 152 211 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_054.v common 4.83 vpr 65.00 MiB -1 -1 0.31 18824 12 0.27 -1 -1 32268 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 32 32 308 340 1 222 92 17 17 289 -1 unnamed_device 25.6 MiB 0.41 3144 1337 10649 2743 7103 803 65.0 MiB 0.07 0.00 10.1967 7.58252 -163.027 -7.58252 7.58252 0.25 0.000490837 0.000443114 0.0319269 0.0295168 -1 -1 -1 -1 40 3178 19 6.79088e+06 377216 706193. 2443.58 2.41 0.251239 0.223458 26254 175826 -1 3008 22 1701 4827 258713 61668 6.50587 6.50587 -155.351 -6.50587 0 0 926341. 3205.33 0.05 0.11 0.09 -1 -1 0.05 0.0451514 0.0407572 156 214 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_055.v common 2.48 vpr 63.77 MiB -1 -1 0.22 18052 11 0.11 -1 -1 32232 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 32 32 216 248 1 163 81 17 17 289 -1 unnamed_device 24.5 MiB 0.16 2444 1016 13381 3505 8370 1506 63.8 MiB 0.06 0.00 8.71077 6.38377 -127.37 -6.38377 6.38377 0.25 0.000324322 0.000295525 0.0272651 0.0249364 -1 -1 -1 -1 30 2471 48 6.79088e+06 229024 556674. 1926.21 0.77 0.111758 0.0991533 24526 138013 -1 2018 16 855 2033 108403 26277 5.53907 5.53907 -126.438 -5.53907 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0151176 0.0137736 96 122 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_056.v common 3.03 vpr 64.83 MiB -1 -1 0.17 18440 13 0.19 -1 -1 31976 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66384 32 32 254 286 1 192 84 17 17 289 -1 unnamed_device 25.0 MiB 0.79 2200 1130 7953 1961 5244 748 64.8 MiB 0.06 0.00 9.12952 7.64382 -162.069 -7.64382 7.64382 0.26 0.000404932 0.00037113 0.0266925 0.0246854 -1 -1 -1 -1 32 3343 36 6.79088e+06 269440 586450. 2029.24 0.62 0.103698 0.0924632 24814 144142 -1 2509 20 1303 3343 181626 44818 6.83492 6.83492 -156.203 -6.83492 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0210802 0.0190009 117 160 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_057.v common 4.16 vpr 64.23 MiB -1 -1 0.19 19208 14 0.50 -1 -1 32596 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 32 32 338 370 1 249 88 17 17 289 -1 unnamed_device 25.6 MiB 0.55 3289 1631 6133 1207 4481 445 64.2 MiB 0.05 0.00 12.1157 8.85191 -183.37 -8.85191 8.85191 0.25 0.00052977 0.00048526 0.0246398 0.0227741 -1 -1 -1 -1 36 4433 25 6.79088e+06 323328 648988. 2245.63 1.60 0.198607 0.176942 25390 158009 -1 3727 23 2320 7287 414178 93236 7.92691 7.92691 -180.612 -7.92691 0 0 828058. 2865.25 0.03 0.09 0.08 -1 -1 0.03 0.0315216 0.0285437 178 244 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_058.v common 4.45 vpr 64.82 MiB -1 -1 0.16 18436 13 0.25 -1 -1 32520 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 32 32 271 303 1 213 87 17 17 289 -1 unnamed_device 25.2 MiB 0.41 2695 1357 7767 1632 5687 448 64.8 MiB 0.05 0.00 9.55819 7.43065 -172.005 -7.43065 7.43065 0.26 0.000453633 0.000416022 0.0206436 0.0188543 -1 -1 -1 -1 44 3224 37 6.79088e+06 309856 787024. 2723.27 2.25 0.249436 0.219598 27118 194962 -1 2850 17 1234 3473 205079 46010 6.76533 6.76533 -164.687 -6.76533 0 0 997811. 3452.63 0.06 0.09 0.14 -1 -1 0.06 0.0356138 0.032349 139 177 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_059.v common 5.16 vpr 63.62 MiB -1 -1 0.15 18056 11 0.15 -1 -1 32220 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65144 30 32 224 256 1 165 81 17 17 289 -1 unnamed_device 24.5 MiB 0.28 2111 998 6031 1372 4208 451 63.6 MiB 0.04 0.00 8.95732 6.57733 -140.708 -6.57733 6.57733 0.25 0.000361391 0.000331213 0.0187657 0.0173949 -1 -1 -1 -1 30 2897 39 6.79088e+06 255968 556674. 1926.21 3.36 0.147671 0.130734 24526 138013 -1 2204 19 1182 3397 176175 42450 5.70014 5.70014 -134.673 -5.70014 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0198801 0.0179249 103 136 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_060.v common 5.46 vpr 64.95 MiB -1 -1 0.22 19208 15 0.48 -1 -1 32792 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66504 32 32 351 383 1 253 89 17 17 289 -1 unnamed_device 25.2 MiB 0.71 3433 1562 7613 1907 5097 609 64.9 MiB 0.10 0.00 11.6801 9.39421 -191.348 -9.39421 9.39421 0.36 0.00106071 0.000968475 0.046627 0.0426776 -1 -1 -1 -1 42 3751 25 6.79088e+06 336800 744469. 2576.02 2.52 0.366544 0.326961 26542 182613 -1 3337 18 1749 5222 274844 63949 8.01666 8.01666 -177.783 -8.01666 0 0 949917. 3286.91 0.04 0.07 0.10 -1 -1 0.04 0.0297378 0.0272194 185 257 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_061.v common 4.20 vpr 64.39 MiB -1 -1 0.17 18440 13 0.28 -1 -1 32436 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 297 329 1 219 84 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2331 1313 3744 580 3016 148 64.4 MiB 0.03 0.00 9.31665 8.10068 -171.378 -8.10068 8.10068 0.25 0.00048237 0.000443634 0.0128747 0.0119037 -1 -1 -1 -1 30 3374 30 6.79088e+06 269440 556674. 1926.21 1.97 0.161087 0.142735 24526 138013 -1 2738 19 1436 3802 177108 45178 7.26121 7.26121 -166.861 -7.26121 0 0 706193. 2443.58 0.03 0.05 0.13 -1 -1 0.03 0.0260456 0.0238074 143 203 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_062.v common 4.84 vpr 64.27 MiB -1 -1 0.14 18056 11 0.17 -1 -1 32236 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 231 263 1 167 82 17 17 289 -1 unnamed_device 24.9 MiB 0.44 2270 1023 7736 2019 5297 420 64.3 MiB 0.04 0.00 8.47541 6.67703 -137.267 -6.67703 6.67703 0.25 0.000362463 0.000328679 0.018534 0.0169718 -1 -1 -1 -1 32 2657 23 6.79088e+06 242496 586450. 2029.24 2.81 0.168016 0.148222 24814 144142 -1 2290 22 939 2390 174462 52299 5.65673 5.65673 -133.532 -5.65673 0 0 744469. 2576.02 0.03 0.05 0.09 -1 -1 0.03 0.0191776 0.0172547 102 137 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_063.v common 4.62 vpr 65.11 MiB -1 -1 0.29 18444 12 0.27 -1 -1 32348 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66676 32 32 305 337 1 213 84 17 17 289 -1 unnamed_device 25.6 MiB 0.45 2891 1443 5757 1168 4018 571 65.1 MiB 0.04 0.00 9.11861 7.63944 -167.73 -7.63944 7.63944 0.25 0.000465144 0.000424934 0.0193417 0.0177798 -1 -1 -1 -1 34 3932 44 6.79088e+06 269440 618332. 2139.56 2.35 0.227299 0.200836 25102 150614 -1 3251 21 1580 4929 276598 63194 6.67032 6.67032 -159.862 -6.67032 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0265715 0.0240576 150 211 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_064.v common 3.39 vpr 64.76 MiB -1 -1 0.14 18052 12 0.17 -1 -1 32236 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 32 32 243 275 1 185 85 17 17 289 -1 unnamed_device 24.9 MiB 0.31 2761 1193 9013 2310 6187 516 64.8 MiB 0.06 0.00 9.53525 7.06923 -152.736 -7.06923 7.06923 0.25 0.000831744 0.000771026 0.0259706 0.0239944 -1 -1 -1 -1 32 3476 32 6.79088e+06 282912 586450. 2029.24 1.53 0.163362 0.144355 24814 144142 -1 2663 17 1226 3225 178849 42340 6.24403 6.24403 -150.803 -6.24403 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0181705 0.0165401 116 149 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_065.v common 2.59 vpr 64.29 MiB -1 -1 0.15 18056 12 0.16 -1 -1 32240 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 30 32 228 260 1 164 81 17 17 289 -1 unnamed_device 24.5 MiB 0.38 2420 1052 9006 2359 5756 891 64.3 MiB 0.06 0.00 9.79978 7.51114 -149.061 -7.51114 7.51114 0.26 0.000582199 0.00055125 0.0274052 0.0252224 -1 -1 -1 -1 28 2581 46 6.79088e+06 255968 531479. 1839.03 0.62 0.10047 0.0893174 23950 126010 -1 2268 17 883 2304 127041 31144 6.50931 6.50931 -142.821 -6.50931 0 0 648988. 2245.63 0.02 0.04 0.14 -1 -1 0.02 0.0175122 0.0159131 106 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_066.v common 4.27 vpr 65.00 MiB -1 -1 0.18 18440 12 0.24 -1 -1 33000 -1 -1 27 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 29 32 275 307 1 201 88 17 17 289 -1 unnamed_device 25.2 MiB 0.86 2477 1194 11983 2982 7056 1945 65.0 MiB 0.07 0.00 9.28703 7.29287 -140.54 -7.29287 7.29287 0.25 0.000596237 0.000555455 0.0308238 0.0281961 -1 -1 -1 -1 34 3229 49 6.79088e+06 363744 618332. 2139.56 1.61 0.208 0.183725 25102 150614 -1 2663 18 1246 3691 195920 47061 6.49468 6.49468 -135.021 -6.49468 0 0 787024. 2723.27 0.04 0.08 0.12 -1 -1 0.04 0.031244 0.0281388 141 190 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_067.v common 3.17 vpr 64.52 MiB -1 -1 0.19 18436 13 0.30 -1 -1 32424 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 32 32 330 362 1 243 89 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2791 1433 6425 1352 4743 330 64.5 MiB 0.05 0.00 10.3234 8.72856 -182.327 -8.72856 8.72856 0.24 0.000795659 0.000728071 0.0232994 0.0214039 -1 -1 -1 -1 38 3464 26 6.79088e+06 336800 678818. 2348.85 1.14 0.157746 0.140616 25966 169698 -1 2843 20 1580 4086 185601 47097 7.50416 7.50416 -166.392 -7.50416 0 0 902133. 3121.57 0.03 0.07 0.09 -1 -1 0.03 0.0309614 0.0279604 164 236 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_068.v common 4.63 vpr 63.84 MiB -1 -1 0.30 18440 12 0.30 -1 -1 32376 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65376 32 32 290 322 1 218 87 17 17 289 -1 unnamed_device 24.9 MiB 0.35 2738 1381 6039 1246 4273 520 63.8 MiB 0.04 0.00 10.6331 7.88426 -165.865 -7.88426 7.88426 0.25 0.000465683 0.000427551 0.0179957 0.016611 -1 -1 -1 -1 44 3100 19 6.79088e+06 309856 787024. 2723.27 2.38 0.252406 0.224359 27118 194962 -1 2732 20 1293 3687 194765 45364 7.04976 7.04976 -158.257 -7.04976 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0242765 0.022065 145 196 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_069.v common 3.11 vpr 64.28 MiB -1 -1 0.19 18056 12 0.13 -1 -1 32964 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 214 246 1 158 81 17 17 289 -1 unnamed_device 24.5 MiB 0.65 2402 966 11631 3699 5844 2088 64.3 MiB 0.06 0.00 10.2046 7.4716 -147.486 -7.4716 7.4716 0.31 0.000337689 0.000308377 0.0259086 0.0237764 -1 -1 -1 -1 30 2786 28 6.79088e+06 229024 556674. 1926.21 0.63 0.0863746 0.076974 24526 138013 -1 2052 27 873 2476 167777 62750 6.58427 6.58427 -143.078 -6.58427 0 0 706193. 2443.58 0.03 0.07 0.08 -1 -1 0.03 0.027424 0.0243636 94 120 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_070.v common 3.07 vpr 64.72 MiB -1 -1 0.17 18052 12 0.19 -1 -1 32040 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66276 31 32 244 276 1 178 85 17 17 289 -1 unnamed_device 25.2 MiB 0.54 2184 1042 4921 903 3842 176 64.7 MiB 0.05 0.00 8.68884 7.00394 -143.566 -7.00394 7.00394 0.35 0.000580339 0.000532143 0.0195529 0.0179552 -1 -1 -1 -1 30 3034 24 6.79088e+06 296384 556674. 1926.21 0.78 0.0893686 0.0802788 24526 138013 -1 2491 21 1275 3564 186778 44710 6.22488 6.22488 -141.943 -6.22488 0 0 706193. 2443.58 0.03 0.05 0.12 -1 -1 0.03 0.0205045 0.0184847 113 153 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_071.v common 3.99 vpr 64.89 MiB -1 -1 0.26 18436 11 0.17 -1 -1 32464 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66448 30 32 276 308 1 187 83 17 17 289 -1 unnamed_device 24.9 MiB 0.88 2327 1150 11783 3905 5750 2128 64.9 MiB 0.07 0.00 8.87527 6.95498 -139.11 -6.95498 6.95498 0.25 0.000420157 0.000383828 0.0308821 0.0282508 -1 -1 -1 -1 36 2957 25 6.79088e+06 282912 648988. 2245.63 1.42 0.17502 0.154264 25390 158009 -1 2591 18 1136 3349 191755 44399 5.75396 5.75396 -131.866 -5.75396 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0209723 0.0190357 129 188 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_072.v common 2.83 vpr 64.16 MiB -1 -1 0.15 18292 11 0.18 -1 -1 32256 -1 -1 22 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65704 28 32 253 285 1 172 82 17 17 289 -1 unnamed_device 24.9 MiB 0.41 2569 974 5778 1226 4251 301 64.2 MiB 0.05 0.00 9.47421 6.55419 -124.806 -6.55419 6.55419 0.25 0.000396379 0.000362887 0.0227797 0.0211258 -1 -1 -1 -1 30 2829 21 6.79088e+06 296384 556674. 1926.21 0.90 0.0960849 0.0857142 24526 138013 -1 2180 16 1052 3156 159340 38063 5.81774 5.81774 -121.9 -5.81774 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0180222 0.0164005 120 171 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_073.v common 4.56 vpr 64.36 MiB -1 -1 0.15 18052 13 0.24 -1 -1 32168 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 30 32 235 267 1 170 80 17 17 289 -1 unnamed_device 25.2 MiB 0.73 2387 982 10056 3040 5967 1049 64.4 MiB 0.08 0.00 9.81312 7.63272 -149.917 -7.63272 7.63272 0.26 0.000365681 0.000334243 0.0425039 0.0393652 -1 -1 -1 -1 28 3041 35 6.79088e+06 242496 531479. 1839.03 2.19 0.170005 0.151582 23950 126010 -1 2375 17 1061 2784 162889 39902 6.66693 6.66693 -147.788 -6.66693 0 0 648988. 2245.63 0.03 0.05 0.07 -1 -1 0.03 0.0189454 0.0172721 108 147 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_074.v common 3.17 vpr 64.23 MiB -1 -1 0.22 18436 12 0.17 -1 -1 31628 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 264 296 1 197 84 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2415 1100 7770 2015 4653 1102 64.2 MiB 0.05 0.00 8.61815 6.91588 -153.666 -6.91588 6.91588 0.25 0.000579984 0.000543002 0.0212815 0.0195477 -1 -1 -1 -1 34 3490 32 6.79088e+06 269440 618332. 2139.56 1.09 0.135237 0.119678 25102 150614 -1 2558 21 1284 3364 172397 44534 5.95079 5.95079 -148.444 -5.95079 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0229694 0.020794 123 170 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_075.v common 4.84 vpr 64.97 MiB -1 -1 0.23 18440 13 0.26 -1 -1 32440 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66528 31 32 278 310 1 200 88 17 17 289 -1 unnamed_device 24.9 MiB 0.60 2897 1114 11788 3097 6456 2235 65.0 MiB 0.07 0.00 11.7353 8.38278 -163.21 -8.38278 8.38278 0.25 0.000448414 0.000410921 0.031208 0.0287226 -1 -1 -1 -1 32 3812 34 6.79088e+06 336800 586450. 2029.24 2.47 0.211753 0.186949 24814 144142 -1 2673 22 1312 3766 200576 50238 7.37881 7.37881 -158.541 -7.37881 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0245143 0.0221544 139 187 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_076.v common 4.12 vpr 65.02 MiB -1 -1 0.17 18056 14 0.23 -1 -1 32256 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 290 322 1 211 86 17 17 289 -1 unnamed_device 25.6 MiB 0.40 2838 1263 6323 1281 4818 224 65.0 MiB 0.05 0.00 9.79877 8.51252 -171.88 -8.51252 8.51252 0.30 0.000558009 0.000518729 0.0243299 0.022691 -1 -1 -1 -1 36 3441 45 6.79088e+06 296384 648988. 2245.63 1.72 0.189446 0.168875 25390 158009 -1 2883 25 1619 4804 303117 88801 7.57564 7.57564 -165.101 -7.57564 0 0 828058. 2865.25 0.03 0.09 0.08 -1 -1 0.03 0.0285655 0.0257961 142 196 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_077.v common 5.32 vpr 64.20 MiB -1 -1 0.18 18824 14 0.21 -1 -1 31756 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 269 301 1 198 83 17 17 289 -1 unnamed_device 24.9 MiB 0.76 2866 1248 7823 1994 5588 241 64.2 MiB 0.08 0.00 10.6835 8.05628 -162.217 -8.05628 8.05628 0.44 0.000778824 0.000710335 0.0372945 0.0341344 -1 -1 -1 -1 36 3198 50 6.79088e+06 255968 648988. 2245.63 2.26 0.244666 0.217046 25390 158009 -1 2775 21 1430 4356 266832 59760 7.46142 7.46142 -158.825 -7.46142 0 0 828058. 2865.25 0.05 0.11 0.14 -1 -1 0.05 0.0415661 0.0375795 124 175 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_078.v common 4.92 vpr 64.81 MiB -1 -1 0.17 18820 13 0.29 -1 -1 32464 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66364 32 32 296 328 1 220 88 17 17 289 -1 unnamed_device 24.9 MiB 0.79 3301 1354 9838 2791 5943 1104 64.8 MiB 0.11 0.00 11.6561 8.50014 -174.144 -8.50014 8.50014 0.44 0.000953862 0.000846986 0.050354 0.0460695 -1 -1 -1 -1 40 3071 19 6.79088e+06 323328 706193. 2443.58 1.90 0.242904 0.215911 26254 175826 -1 2921 18 1386 4092 217498 50671 7.4292 7.4292 -164.596 -7.4292 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0236931 0.0216261 148 202 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_079.v common 3.73 vpr 64.04 MiB -1 -1 0.15 18056 13 0.16 -1 -1 32240 -1 -1 20 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65572 30 32 234 266 1 174 82 17 17 289 -1 unnamed_device 24.9 MiB 0.71 2093 1110 11118 3343 5904 1871 64.0 MiB 0.07 0.00 8.34292 7.03168 -146.297 -7.03168 7.03168 0.37 0.000407522 0.000370634 0.0354939 0.0326379 -1 -1 -1 -1 32 3046 36 6.79088e+06 269440 586450. 2029.24 1.25 0.163242 0.144621 24814 144142 -1 2365 20 1188 3012 173307 40703 6.14335 6.14335 -141.075 -6.14335 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0190443 0.0172279 105 146 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_080.v common 4.29 vpr 64.45 MiB -1 -1 0.21 18824 13 0.40 -1 -1 32420 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 30 32 291 323 1 221 84 17 17 289 -1 unnamed_device 24.9 MiB 0.49 2701 1328 5940 1337 4353 250 64.5 MiB 0.08 0.00 9.92372 8.27725 -167.59 -8.27725 8.27725 0.32 0.000471761 0.000432104 0.0419352 0.0390168 -1 -1 -1 -1 40 2990 21 6.79088e+06 296384 706193. 2443.58 1.77 0.216138 0.191906 26254 175826 -1 2793 21 1499 3987 204361 48668 7.05325 7.05325 -158.984 -7.05325 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0270017 0.0245199 148 203 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_081.v common 4.21 vpr 64.30 MiB -1 -1 0.17 18444 14 0.37 -1 -1 32456 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 32 32 274 306 1 198 83 17 17 289 -1 unnamed_device 24.9 MiB 0.42 2766 1310 6203 1436 4242 525 64.3 MiB 0.06 0.00 10.68 7.90813 -170.809 -7.90813 7.90813 0.26 0.000437767 0.000400069 0.0261332 0.0241232 -1 -1 -1 -1 38 3375 23 6.79088e+06 255968 678818. 2348.85 1.97 0.190854 0.168878 25966 169698 -1 2731 20 1307 4212 215589 49236 6.96028 6.96028 -163.001 -6.96028 0 0 902133. 3121.57 0.03 0.06 0.10 -1 -1 0.03 0.0239148 0.021685 132 180 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_082.v common 6.03 vpr 63.70 MiB -1 -1 0.17 18420 13 0.21 -1 -1 32388 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65224 31 32 266 298 1 197 82 17 17 289 -1 unnamed_device 24.9 MiB 0.50 2670 1263 9516 2495 6168 853 63.7 MiB 0.08 0.00 9.28969 7.78026 -159.259 -7.78026 7.78026 0.24 0.000427306 0.000391277 0.0374739 0.0347377 -1 -1 -1 -1 40 3248 40 6.79088e+06 255968 706193. 2443.58 3.11 0.247052 0.219892 26254 175826 -1 2973 78 1765 5797 1115118 678019 6.70192 6.70192 -151.991 -6.70192 0 0 926341. 3205.33 0.05 0.62 0.18 -1 -1 0.05 0.0991482 0.088454 126 175 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_083.v common 6.00 vpr 64.51 MiB -1 -1 0.25 18048 13 0.19 -1 -1 32400 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 30 32 266 298 1 199 87 17 17 289 -1 unnamed_device 24.9 MiB 0.58 3172 1233 7767 1881 5232 654 64.5 MiB 0.05 0.00 10.3598 7.59138 -150.075 -7.59138 7.59138 0.25 0.000417312 0.000382562 0.0197533 0.0181414 -1 -1 -1 -1 30 3483 48 6.79088e+06 336800 556674. 1926.21 3.75 0.181702 0.160413 24526 138013 -1 2860 17 1326 3637 193421 45729 6.80459 6.80459 -149.735 -6.80459 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0204113 0.0184966 131 178 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_084.v common 10.01 vpr 64.36 MiB -1 -1 0.19 18680 14 0.32 -1 -1 32292 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 32 32 310 342 1 223 90 17 17 289 -1 unnamed_device 24.9 MiB 0.53 2887 1381 9336 2138 6356 842 64.4 MiB 0.06 0.00 11.5139 8.70357 -178.124 -8.70357 8.70357 0.25 0.00049894 0.000457278 0.02631 0.0241948 -1 -1 -1 -1 32 4103 38 6.79088e+06 350272 586450. 2029.24 7.66 0.268987 0.239194 24814 144142 -1 3266 21 1495 4302 258673 61020 8.00547 8.00547 -175.323 -8.00547 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.026999 0.0245295 158 216 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_085.v common 4.72 vpr 64.77 MiB -1 -1 0.19 18440 11 0.25 -1 -1 32332 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 29 32 262 294 1 200 84 17 17 289 -1 unnamed_device 25.2 MiB 0.67 2793 1203 9966 2546 6206 1214 64.8 MiB 0.06 0.00 9.38772 7.1445 -141.662 -7.1445 7.1445 0.24 0.000419357 0.000383247 0.0259456 0.0238008 -1 -1 -1 -1 28 3470 28 6.79088e+06 309856 531479. 1839.03 2.12 0.187136 0.166118 23950 126010 -1 2930 22 1722 4992 281067 65184 6.54502 6.54502 -143.562 -6.54502 0 0 648988. 2245.63 0.04 0.12 0.12 -1 -1 0.04 0.0430561 0.0387822 138 177 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_086.v common 3.15 vpr 64.34 MiB -1 -1 0.15 18052 13 0.21 -1 -1 31724 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 32 32 222 254 1 179 83 17 17 289 -1 unnamed_device 24.9 MiB 0.55 2069 1200 7283 1764 4531 988 64.3 MiB 0.04 0.00 8.60203 7.14167 -162.348 -7.14167 7.14167 0.25 0.000344035 0.000314977 0.0190755 0.0175703 -1 -1 -1 -1 30 2976 21 6.79088e+06 255968 556674. 1926.21 0.84 0.0752712 0.0674518 24526 138013 -1 2322 18 1104 2731 132385 32111 6.15798 6.15798 -152.89 -6.15798 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0171264 0.0155641 100 128 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_087.v common 4.03 vpr 63.72 MiB -1 -1 0.19 18440 14 0.30 -1 -1 32404 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65252 32 32 267 299 1 192 83 17 17 289 -1 unnamed_device 24.9 MiB 0.66 2378 1170 9443 2925 4513 2005 63.7 MiB 0.06 0.00 10.4435 8.52224 -173.995 -8.52224 8.52224 0.25 0.000566754 0.000498933 0.0287922 0.0265342 -1 -1 -1 -1 34 3483 37 6.79088e+06 255968 618332. 2139.56 1.62 0.18205 0.160753 25102 150614 -1 2712 18 1256 3540 198662 47419 7.38302 7.38302 -165.88 -7.38302 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0210165 0.0191077 127 173 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_088.v common 3.79 vpr 63.94 MiB -1 -1 0.18 18824 15 0.39 -1 -1 32460 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 32 32 334 366 1 249 94 17 17 289 -1 unnamed_device 25.1 MiB 0.67 2997 1457 6271 1114 4893 264 63.9 MiB 0.05 0.00 11.8769 9.02668 -192.137 -9.02668 9.02668 0.24 0.000537557 0.000493455 0.0195073 0.0180239 -1 -1 -1 -1 36 4225 32 6.79088e+06 404160 648988. 2245.63 1.21 0.163429 0.145622 25390 158009 -1 3413 20 1762 4569 244133 58653 8.26721 8.26721 -187.065 -8.26721 0 0 828058. 2865.25 0.03 0.08 0.09 -1 -1 0.03 0.0324314 0.0294256 173 240 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_089.v common 4.34 vpr 64.31 MiB -1 -1 0.14 18052 11 0.14 -1 -1 32388 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 220 252 1 162 82 17 17 289 -1 unnamed_device 24.5 MiB 0.43 1851 1048 4710 962 3444 304 64.3 MiB 0.03 0.00 7.41857 6.65913 -141.007 -6.65913 6.65913 0.25 0.000338577 0.000308878 0.011031 0.0101382 -1 -1 -1 -1 30 2490 34 6.79088e+06 242496 556674. 1926.21 2.37 0.132925 0.116936 24526 138013 -1 2104 20 918 2474 125119 29697 5.77089 5.77089 -135.604 -5.77089 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0227745 0.020516 99 126 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_090.v common 3.59 vpr 64.79 MiB -1 -1 0.14 18056 12 0.16 -1 -1 31716 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 31 32 244 276 1 190 91 17 17 289 -1 unnamed_device 25.2 MiB 0.38 2514 1243 8251 2100 5415 736 64.8 MiB 0.07 0.00 8.41327 6.64151 -151.522 -6.64151 6.64151 0.36 0.000384324 0.000351749 0.030995 0.0286946 -1 -1 -1 -1 36 3288 38 6.79088e+06 377216 648988. 2245.63 1.31 0.171017 0.151396 25390 158009 -1 2786 19 1310 3450 219229 55840 5.77084 5.77084 -147.31 -5.77084 0 0 828058. 2865.25 0.04 0.09 0.15 -1 -1 0.04 0.0326963 0.0295814 120 153 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_091.v common 4.25 vpr 64.96 MiB -1 -1 0.17 18440 12 0.26 -1 -1 32432 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 32 32 300 332 1 219 84 17 17 289 -1 unnamed_device 25.2 MiB 0.58 3008 1362 5208 1021 3853 334 65.0 MiB 0.04 0.00 9.33179 7.30279 -161.797 -7.30279 7.30279 0.24 0.000490485 0.000449616 0.0170101 0.0156458 -1 -1 -1 -1 32 4017 47 6.79088e+06 269440 586450. 2029.24 1.72 0.181491 0.159594 24814 144142 -1 3222 25 1827 5666 393170 111302 6.49473 6.49473 -154.751 -6.49473 0 0 744469. 2576.02 0.05 0.17 0.14 -1 -1 0.05 0.0525904 0.0474923 147 206 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_092.v common 4.94 vpr 64.30 MiB -1 -1 0.17 18440 12 0.21 -1 -1 32704 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 32 32 271 303 1 207 87 17 17 289 -1 unnamed_device 24.9 MiB 0.35 2518 1359 4887 914 3740 233 64.3 MiB 0.04 0.00 9.30843 7.32413 -157.509 -7.32413 7.32413 0.24 0.000422354 0.000385538 0.0141421 0.0129613 -1 -1 -1 -1 42 3546 34 6.79088e+06 309856 744469. 2576.02 2.98 0.184685 0.162721 26542 182613 -1 3075 20 1631 5150 317078 68780 6.32248 6.32248 -151.947 -6.32248 0 0 949917. 3286.91 0.03 0.07 0.10 -1 -1 0.03 0.0225575 0.0203783 135 177 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_093.v common 4.66 vpr 65.20 MiB -1 -1 0.18 18820 14 0.41 -1 -1 32516 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66760 32 32 327 359 1 232 89 17 17 289 -1 unnamed_device 25.2 MiB 0.91 2902 1486 9197 2044 6238 915 65.2 MiB 0.07 0.00 11.0044 9.05824 -184.444 -9.05824 9.05824 0.24 0.000531234 0.000486752 0.0317284 0.0292755 -1 -1 -1 -1 36 4352 44 6.79088e+06 336800 648988. 2245.63 1.82 0.192183 0.171116 25390 158009 -1 3470 21 2095 6448 340912 77405 7.89475 7.89475 -180.096 -7.89475 0 0 828058. 2865.25 0.03 0.09 0.09 -1 -1 0.03 0.0368876 0.0334178 170 233 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_094.v common 5.07 vpr 64.79 MiB -1 -1 0.16 18052 12 0.18 -1 -1 32312 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 30 32 246 278 1 190 83 17 17 289 -1 unnamed_device 25.2 MiB 0.38 2872 1225 9443 2668 5974 801 64.8 MiB 0.07 0.00 11.0773 8.04235 -151.9 -8.04235 8.04235 0.26 0.000906454 0.000843157 0.0312125 0.0289054 -1 -1 -1 -1 30 3247 21 6.79088e+06 282912 556674. 1926.21 3.09 0.153647 0.13626 24526 138013 -1 2617 19 1174 3385 171181 40726 7.03513 7.03513 -147.434 -7.03513 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0208927 0.0189654 123 158 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_095.v common 3.30 vpr 64.29 MiB -1 -1 0.14 17924 11 0.16 -1 -1 32200 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 27 32 219 251 1 158 80 17 17 289 -1 unnamed_device 24.5 MiB 0.66 2254 914 10228 3057 5550 1621 64.3 MiB 0.06 0.00 9.28609 7.11012 -129.104 -7.11012 7.11012 0.26 0.000834625 0.000778535 0.0290409 0.0268197 -1 -1 -1 -1 32 2363 20 6.79088e+06 282912 586450. 2029.24 1.10 0.132738 0.117693 24814 144142 -1 2014 16 860 2297 118764 28995 6.41202 6.41202 -124.201 -6.41202 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.018655 0.0167893 106 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_096.v common 12.15 vpr 64.09 MiB -1 -1 0.34 19208 13 0.38 -1 -1 32612 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65628 32 32 380 412 1 267 93 17 17 289 -1 unnamed_device 25.2 MiB 0.96 3799 1688 9333 2238 6298 797 64.1 MiB 0.07 0.00 9.85648 8.03891 -164.154 -8.03891 8.03891 0.24 0.000570832 0.000522627 0.0301749 0.0276234 -1 -1 -1 -1 36 4720 50 6.79088e+06 390688 648988. 2245.63 9.12 0.333255 0.295789 25390 158009 -1 4022 18 1939 5882 349528 81642 7.24643 7.24643 -163.259 -7.24643 0 0 828058. 2865.25 0.03 0.09 0.09 -1 -1 0.03 0.0332537 0.0305258 194 286 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_097.v common 5.05 vpr 64.26 MiB -1 -1 0.18 18440 14 0.23 -1 -1 32352 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 31 32 277 309 1 194 84 17 17 289 -1 unnamed_device 25.2 MiB 0.43 2825 1259 8502 2170 5586 746 64.3 MiB 0.05 0.00 10.5434 8.40299 -170.106 -8.40299 8.40299 0.26 0.000438649 0.000401614 0.0240127 0.0220456 -1 -1 -1 -1 28 3607 48 6.79088e+06 282912 531479. 1839.03 2.70 0.212266 0.187267 23950 126010 -1 2799 19 1355 3498 182428 44663 7.5622 7.5622 -166.161 -7.5622 0 0 648988. 2245.63 0.03 0.08 0.07 -1 -1 0.03 0.0331487 0.0300722 135 186 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_098.v common 4.33 vpr 64.66 MiB -1 -1 0.27 18044 12 0.14 -1 -1 32196 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 32 32 229 261 1 173 88 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2146 1148 7498 1703 4699 1096 64.7 MiB 0.04 0.00 9.61147 7.37908 -161.709 -7.37908 7.37908 0.25 0.000363041 0.000331373 0.0171253 0.015721 -1 -1 -1 -1 30 2639 20 6.79088e+06 323328 556674. 1926.21 2.24 0.140925 0.124252 24526 138013 -1 2241 16 933 2468 118642 29008 6.35367 6.35367 -152.496 -6.35367 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0215127 0.019597 114 135 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_099.v common 4.34 vpr 64.91 MiB -1 -1 0.18 18056 13 0.26 -1 -1 32468 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 32 32 263 295 1 189 86 17 17 289 -1 unnamed_device 24.9 MiB 0.87 2477 1198 6323 1455 4634 234 64.9 MiB 0.04 0.00 9.94771 7.95285 -163.297 -7.95285 7.95285 0.25 0.000419039 0.000383418 0.0192272 0.0177068 -1 -1 -1 -1 30 3038 31 6.79088e+06 296384 556674. 1926.21 1.80 0.189632 0.166804 24526 138013 -1 2547 17 1163 3392 164677 39638 6.92451 6.92451 -155.538 -6.92451 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0206129 0.0187785 132 169 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_100.v common 5.11 vpr 64.46 MiB -1 -1 0.18 18824 13 0.30 -1 -1 32440 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 321 353 1 243 89 17 17 289 -1 unnamed_device 25.5 MiB 0.47 2996 1555 6425 1253 4749 423 64.5 MiB 0.08 0.00 9.44492 8.03594 -170.227 -8.03594 8.03594 0.46 0.00109351 0.000985855 0.037958 0.0348172 -1 -1 -1 -1 36 4372 49 6.79088e+06 350272 648988. 2245.63 2.33 0.288027 0.256154 25390 158009 -1 3542 17 1701 4822 272035 63597 6.79572 6.79572 -158.919 -6.79572 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0243842 0.0223031 162 230 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_101.v common 4.27 vpr 64.99 MiB -1 -1 0.16 18440 11 0.22 -1 -1 32436 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66552 30 32 287 319 1 199 87 17 17 289 -1 unnamed_device 25.2 MiB 0.86 2711 1222 7191 1645 4976 570 65.0 MiB 0.05 0.00 9.60741 7.06412 -137.725 -7.06412 7.06412 0.24 0.000443175 0.000405281 0.0197344 0.0181089 -1 -1 -1 -1 40 2876 29 6.79088e+06 336800 706193. 2443.58 1.75 0.202725 0.178825 26254 175826 -1 2606 19 1353 4351 224230 52925 5.91852 5.91852 -128.55 -5.91852 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.022852 0.0207243 143 199 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_102.v common 4.55 vpr 64.41 MiB -1 -1 0.27 18440 15 0.33 -1 -1 32440 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 32 32 296 328 1 214 86 17 17 289 -1 unnamed_device 25.2 MiB 0.59 3096 1319 6134 1277 4632 225 64.4 MiB 0.04 0.00 11.1915 8.22013 -174.204 -8.22013 8.22013 0.24 0.000481606 0.000431524 0.0187261 0.0171522 -1 -1 -1 -1 34 4119 45 6.79088e+06 296384 618332. 2139.56 2.03 0.178009 0.157929 25102 150614 -1 3072 18 1428 4203 233689 55761 7.32848 7.32848 -170.707 -7.32848 0 0 787024. 2723.27 0.05 0.08 0.14 -1 -1 0.05 0.0306779 0.0281631 148 202 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_103.v common 4.64 vpr 64.37 MiB -1 -1 0.25 18820 13 0.37 -1 -1 32476 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 285 317 1 219 85 17 17 289 -1 unnamed_device 25.2 MiB 0.46 2930 1425 7525 1768 5171 586 64.4 MiB 0.05 0.00 10.4559 8.30966 -180.808 -8.30966 8.30966 0.25 0.000502423 0.000463715 0.0224499 0.0206809 -1 -1 -1 -1 36 3708 27 6.79088e+06 282912 648988. 2245.63 2.23 0.211147 0.187347 25390 158009 -1 3210 17 1367 3795 216510 50749 7.33966 7.33966 -172.69 -7.33966 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0240039 0.0219196 145 191 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_104.v common 3.64 vpr 64.62 MiB -1 -1 0.14 18052 12 0.17 -1 -1 32272 -1 -1 24 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 29 32 239 271 1 185 85 17 17 289 -1 unnamed_device 25.2 MiB 0.48 2084 1062 6595 1474 4636 485 64.6 MiB 0.04 0.00 10.0683 7.87572 -156.471 -7.87572 7.87572 0.40 0.000377318 0.000346308 0.0159074 0.0146289 -1 -1 -1 -1 30 2731 21 6.79088e+06 323328 556674. 1926.21 1.31 0.146981 0.129805 24526 138013 -1 2294 18 1137 2909 136931 33931 6.58776 6.58776 -145.673 -6.58776 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0182257 0.0165595 115 154 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_105.v common 2.40 vpr 64.36 MiB -1 -1 0.14 18056 11 0.13 -1 -1 32284 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 32 32 235 267 1 172 82 17 17 289 -1 unnamed_device 24.5 MiB 0.32 2050 1060 6668 1430 4144 1094 64.4 MiB 0.04 0.00 7.79354 6.47149 -144.071 -6.47149 6.47149 0.24 0.000355213 0.000324341 0.0157647 0.0144757 -1 -1 -1 -1 30 2916 41 6.79088e+06 242496 556674. 1926.21 0.65 0.0815988 0.0723604 24526 138013 -1 2303 20 1233 3012 153485 37395 5.85694 5.85694 -146.237 -5.85694 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.018489 0.0167165 105 141 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_106.v common 5.00 vpr 64.54 MiB -1 -1 0.23 18440 13 0.37 -1 -1 32424 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 31 32 294 326 1 211 85 17 17 289 -1 unnamed_device 24.9 MiB 0.70 2712 1384 8455 2000 5617 838 64.5 MiB 0.06 0.00 10.7696 8.27424 -162.337 -8.27424 8.27424 0.24 0.000474087 0.00042731 0.0248337 0.0227038 -1 -1 -1 -1 44 3185 20 6.79088e+06 296384 787024. 2723.27 2.15 0.239145 0.211054 27118 194962 -1 2809 17 1208 3870 211069 47834 7.26465 7.26465 -155.018 -7.26465 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0260052 0.0238743 146 203 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_107.v common 4.01 vpr 64.32 MiB -1 -1 0.15 18056 10 0.23 -1 -1 32416 -1 -1 20 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 219 251 1 164 81 17 17 289 -1 unnamed_device 24.9 MiB 0.41 2040 1050 9181 2635 5082 1464 64.3 MiB 0.05 0.00 8.60248 6.23968 -127.611 -6.23968 6.23968 0.25 0.000341543 0.000311725 0.020299 0.0185793 -1 -1 -1 -1 30 2491 49 6.79088e+06 269440 556674. 1926.21 1.98 0.183649 0.161612 24526 138013 -1 2107 16 952 2430 121433 29267 5.32762 5.32762 -123.296 -5.32762 0 0 706193. 2443.58 0.03 0.04 0.10 -1 -1 0.03 0.0157135 0.0142992 102 134 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_108.v common 3.06 vpr 64.46 MiB -1 -1 0.27 18052 14 0.21 -1 -1 32268 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66008 32 32 239 271 1 181 84 17 17 289 -1 unnamed_device 24.9 MiB 0.73 2315 1098 11430 3365 6228 1837 64.5 MiB 0.06 0.00 10.7127 7.63704 -166.154 -7.63704 7.63704 0.24 0.000386695 0.000354045 0.0270002 0.0247053 -1 -1 -1 -1 30 3052 25 6.79088e+06 269440 556674. 1926.21 0.65 0.0895294 0.0802576 24526 138013 -1 2455 17 1129 3039 153350 36717 6.70624 6.70624 -158.346 -6.70624 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0180472 0.0163852 109 145 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_109.v common 3.80 vpr 64.23 MiB -1 -1 0.19 18440 13 0.30 -1 -1 31856 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 31 32 266 298 1 201 86 17 17 289 -1 unnamed_device 24.9 MiB 0.22 2581 1245 12938 3565 7972 1401 64.2 MiB 0.07 0.00 9.50492 7.70092 -164.904 -7.70092 7.70092 0.25 0.000426903 0.000390675 0.0317082 0.0290071 -1 -1 -1 -1 40 2648 20 6.79088e+06 309856 706193. 2443.58 1.70 0.179053 0.1576 26254 175826 -1 2643 32 1411 4011 312466 112192 6.87412 6.87412 -157.009 -6.87412 0 0 926341. 3205.33 0.03 0.10 0.09 -1 -1 0.03 0.0302607 0.0270951 131 175 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_110.v common 4.15 vpr 64.27 MiB -1 -1 0.15 18056 12 0.13 -1 -1 32216 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 31 32 225 257 1 170 83 17 17 289 -1 unnamed_device 24.9 MiB 0.49 2115 1069 8363 2595 4472 1296 64.3 MiB 0.04 0.00 7.74408 6.38969 -140.212 -6.38969 6.38969 0.35 0.000345596 0.000315547 0.018183 0.0166542 -1 -1 -1 -1 34 2730 27 6.79088e+06 269440 618332. 2139.56 1.95 0.172862 0.151998 25102 150614 -1 2386 18 1076 2987 160528 38621 5.77854 5.77854 -138.465 -5.77854 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0168124 0.0152225 103 134 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_111.v common 7.51 vpr 64.32 MiB -1 -1 0.17 18296 12 0.18 -1 -1 33036 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65868 32 32 288 320 1 203 88 17 17 289 -1 unnamed_device 25.5 MiB 0.51 3004 1280 11788 3296 6900 1592 64.3 MiB 0.07 0.00 10.2613 7.00869 -152.842 -7.00869 7.00869 0.27 0.000438351 0.000399908 0.031924 0.029294 -1 -1 -1 -1 28 3899 44 6.79088e+06 323328 531479. 1839.03 5.38 0.219573 0.193871 23950 126010 -1 2955 20 1664 4630 280626 64993 6.12648 6.12648 -151.532 -6.12648 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0235006 0.0210914 135 194 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_112.v common 6.17 vpr 64.38 MiB -1 -1 0.19 18828 13 0.26 -1 -1 32432 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 31 32 282 314 1 210 85 17 17 289 -1 unnamed_device 25.2 MiB 0.59 2791 1262 11989 3047 7402 1540 64.4 MiB 0.09 0.00 9.30843 7.42893 -161.431 -7.42893 7.42893 0.28 0.000974651 0.000901685 0.043486 0.040061 -1 -1 -1 -1 30 3449 32 6.79088e+06 296384 556674. 1926.21 3.72 0.235374 0.209057 24526 138013 -1 2705 19 1433 4023 185362 45909 6.48354 6.48354 -153.414 -6.48354 0 0 706193. 2443.58 0.04 0.09 0.09 -1 -1 0.04 0.0421007 0.0381483 146 191 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_113.v common 3.75 vpr 64.15 MiB -1 -1 0.16 18048 11 0.15 -1 -1 32388 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 32 32 233 265 1 180 86 17 17 289 -1 unnamed_device 24.5 MiB 0.41 2072 1111 7835 1720 5449 666 64.2 MiB 0.05 0.00 7.45434 6.20134 -144.716 -6.20134 6.20134 0.32 0.000830303 0.000790451 0.0195382 0.0179662 -1 -1 -1 -1 36 2970 27 6.79088e+06 296384 648988. 2245.63 1.69 0.172648 0.151291 25390 158009 -1 2502 29 1264 3459 234056 74739 5.52096 5.52096 -139.628 -5.52096 0 0 828058. 2865.25 0.03 0.07 0.08 -1 -1 0.03 0.0240282 0.0214863 110 139 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_114.v common 5.62 vpr 64.79 MiB -1 -1 0.17 18056 13 0.24 -1 -1 32176 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66348 32 32 254 286 1 184 81 17 17 289 -1 unnamed_device 24.9 MiB 1.26 2540 1123 6906 1729 4876 301 64.8 MiB 0.04 0.00 10.5313 7.62596 -162.162 -7.62596 7.62596 0.40 0.000407825 0.000374245 0.018867 0.0173648 -1 -1 -1 -1 38 2722 40 6.79088e+06 229024 678818. 2348.85 2.19 0.276797 0.244307 25966 169698 -1 2249 15 995 2896 146488 34789 6.54512 6.54512 -154.218 -6.54512 0 0 902133. 3121.57 0.05 0.07 0.16 -1 -1 0.05 0.0297021 0.0269232 116 160 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_115.v common 3.89 vpr 63.58 MiB -1 -1 0.16 18436 13 0.24 -1 -1 32396 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65108 32 32 285 317 1 212 85 17 17 289 -1 unnamed_device 24.9 MiB 0.63 2626 1379 8083 1955 5557 571 63.6 MiB 0.07 0.00 9.80963 7.47873 -167.813 -7.47873 7.47873 0.25 0.000461112 0.000414019 0.0308002 0.0282531 -1 -1 -1 -1 34 3779 35 6.79088e+06 282912 618332. 2139.56 1.52 0.160694 0.142529 25102 150614 -1 3127 35 2346 6906 463431 130783 6.64799 6.64799 -160.553 -6.64799 0 0 787024. 2723.27 0.03 0.13 0.08 -1 -1 0.03 0.0366382 0.0328335 141 191 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_116.v common 3.53 vpr 64.07 MiB -1 -1 0.16 18436 11 0.17 -1 -1 32420 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65612 29 32 243 275 1 183 84 17 17 289 -1 unnamed_device 25.0 MiB 0.49 2499 1173 5208 1126 3631 451 64.1 MiB 0.03 0.00 8.34934 6.48043 -132.63 -6.48043 6.48043 0.25 0.000388058 0.000355693 0.0135592 0.0124786 -1 -1 -1 -1 36 2852 31 6.79088e+06 309856 648988. 2245.63 1.48 0.140205 0.122902 25390 158009 -1 2465 15 967 2919 169443 38934 5.75934 5.75934 -130.721 -5.75934 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0215183 0.0194205 118 158 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_117.v common 7.21 vpr 64.50 MiB -1 -1 0.24 18824 14 0.29 -1 -1 33064 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 318 350 1 238 89 17 17 289 -1 unnamed_device 25.6 MiB 0.50 3185 1427 9989 2338 6256 1395 64.5 MiB 0.07 0.00 11.6109 8.7465 -186.455 -8.7465 8.7465 0.33 0.000521333 0.000476424 0.0308609 0.0283334 -1 -1 -1 -1 30 4195 34 6.79088e+06 336800 556674. 1926.21 4.77 0.280847 0.2493 24526 138013 -1 3114 19 1654 4325 208709 51804 7.58672 7.58672 -175.163 -7.58672 0 0 706193. 2443.58 0.03 0.06 0.08 -1 -1 0.03 0.0266528 0.0243323 164 224 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_118.v common 3.55 vpr 64.24 MiB -1 -1 0.14 18052 12 0.13 -1 -1 32232 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65780 31 32 222 254 1 182 84 17 17 289 -1 unnamed_device 24.9 MiB 0.32 2515 1195 7953 1918 5225 810 64.2 MiB 0.10 0.00 9.02976 6.57733 -149.186 -6.57733 6.57733 0.27 0.00096 0.00088875 0.0449597 0.0417068 -1 -1 -1 -1 40 2450 19 6.79088e+06 282912 706193. 2443.58 1.51 0.16322 0.144706 26254 175826 -1 2277 19 1016 2613 138232 32332 5.70014 5.70014 -139.839 -5.70014 0 0 926341. 3205.33 0.03 0.04 0.15 -1 -1 0.03 0.0177558 0.0160847 105 131 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_119.v common 4.23 vpr 64.32 MiB -1 -1 0.31 18824 13 0.26 -1 -1 33012 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 282 314 1 202 87 17 17 289 -1 unnamed_device 25.2 MiB 0.57 2586 1294 11223 2709 7284 1230 64.3 MiB 0.07 0.00 9.80636 7.81522 -163.002 -7.81522 7.81522 0.24 0.000459996 0.000421553 0.0298052 0.027397 -1 -1 -1 -1 32 3772 44 6.79088e+06 309856 586450. 2029.24 1.80 0.216101 0.190564 24814 144142 -1 3139 27 1415 4088 291600 96304 6.80686 6.80686 -159.585 -6.80686 0 0 744469. 2576.02 0.03 0.10 0.08 -1 -1 0.03 0.0326913 0.0294747 141 188 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_120.v common 3.43 vpr 64.70 MiB -1 -1 0.16 18428 13 0.16 -1 -1 32224 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 238 270 1 179 87 17 17 289 -1 unnamed_device 24.9 MiB 0.33 2213 1145 7959 1748 5469 742 64.7 MiB 0.06 0.00 9.57282 7.74786 -170.737 -7.74786 7.74786 0.30 0.000551588 0.000502718 0.0268101 0.0244864 -1 -1 -1 -1 32 2899 40 6.79088e+06 309856 586450. 2029.24 1.46 0.179622 0.159166 24814 144142 -1 2346 15 990 2455 133104 32316 6.67386 6.67386 -160.516 -6.67386 0 0 744469. 2576.02 0.04 0.05 0.10 -1 -1 0.04 0.0230009 0.0211562 112 144 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_121.v common 3.57 vpr 64.93 MiB -1 -1 0.17 18052 12 0.23 -1 -1 32288 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66488 32 32 269 301 1 193 85 17 17 289 -1 unnamed_device 24.9 MiB 0.83 2838 1258 5665 1169 4247 249 64.9 MiB 0.04 0.00 10.2294 7.48857 -162.185 -7.48857 7.48857 0.27 0.000426859 0.00038986 0.0193522 0.0178721 -1 -1 -1 -1 32 3332 43 6.79088e+06 282912 586450. 2029.24 0.72 0.118284 0.105925 24814 144142 -1 2752 17 1274 3805 210568 50438 6.37282 6.37282 -153.729 -6.37282 0 0 744469. 2576.02 0.04 0.12 0.08 -1 -1 0.04 0.0501828 0.0454932 132 175 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_122.v common 6.84 vpr 64.75 MiB -1 -1 0.20 19208 15 0.56 -1 -1 32720 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 350 382 1 251 89 17 17 289 -1 unnamed_device 25.6 MiB 1.00 3569 1573 10583 2766 6384 1433 64.7 MiB 0.09 0.00 11.6887 9.43481 -197.257 -9.43481 9.43481 0.24 0.000575225 0.00052701 0.0405772 0.0372963 -1 -1 -1 -1 48 3820 22 6.79088e+06 336800 865456. 2994.66 3.48 0.393652 0.351941 27694 206865 -1 3410 19 1843 6055 331838 74371 8.18111 8.18111 -182.275 -8.18111 0 0 1.05005e+06 3633.38 0.04 0.08 0.11 -1 -1 0.04 0.0308149 0.0280731 184 256 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_123.v common 2.87 vpr 64.00 MiB -1 -1 0.15 17668 10 0.10 -1 -1 32064 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65540 30 32 174 206 1 132 75 17 17 289 -1 unnamed_device 24.3 MiB 0.27 1704 689 6079 1358 4541 180 64.0 MiB 0.03 0.00 5.85167 5.06685 -115.513 -5.06685 5.06685 0.25 0.000272135 0.000249038 0.0120598 0.0110675 -1 -1 -1 -1 34 1844 23 6.79088e+06 175136 618332. 2139.56 1.13 0.0922076 0.0806298 25102 150614 -1 1531 16 723 1671 81394 21367 4.46811 4.46811 -112.797 -4.46811 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0119656 0.0108259 66 86 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_124.v common 4.10 vpr 64.34 MiB -1 -1 0.15 18056 13 0.16 -1 -1 32248 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 30 32 228 260 1 170 83 17 17 289 -1 unnamed_device 24.6 MiB 0.72 2214 1013 9083 2607 5166 1310 64.3 MiB 0.05 0.00 9.66643 7.93028 -158.567 -7.93028 7.93028 0.35 0.000357607 0.000326665 0.0206406 0.0189224 -1 -1 -1 -1 34 2709 33 6.79088e+06 282912 618332. 2139.56 1.47 0.155242 0.1373 25102 150614 -1 2341 27 1048 2773 214239 76852 6.87418 6.87418 -150.154 -6.87418 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0227765 0.0204907 108 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_125.v common 4.29 vpr 64.83 MiB -1 -1 0.17 18292 12 0.18 -1 -1 32276 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 32 32 264 296 1 193 87 17 17 289 -1 unnamed_device 25.2 MiB 0.53 2664 1204 6039 1295 4393 351 64.8 MiB 0.06 0.00 9.33663 7.42897 -167.088 -7.42897 7.42897 0.45 0.000748074 0.000682446 0.0272169 0.0249518 -1 -1 -1 -1 32 3186 39 6.79088e+06 309856 586450. 2029.24 1.61 0.19246 0.169113 24814 144142 -1 2600 14 1082 2781 153438 36660 6.37287 6.37287 -156.925 -6.37287 0 0 744469. 2576.02 0.05 0.07 0.14 -1 -1 0.05 0.032197 0.0295269 122 170 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_126.v common 2.53 vpr 64.12 MiB -1 -1 0.15 17672 9 0.11 -1 -1 31992 -1 -1 21 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65660 25 32 183 215 1 134 78 17 17 289 -1 unnamed_device 24.5 MiB 0.35 1513 648 7216 2007 4704 505 64.1 MiB 0.05 0.00 5.889 5.1159 -95.0834 -5.1159 5.1159 0.26 0.000290205 0.000265211 0.026009 0.0242288 -1 -1 -1 -1 30 1972 23 6.79088e+06 282912 556674. 1926.21 0.76 0.077457 0.0696231 24526 138013 -1 1532 18 764 2122 115511 30012 4.5968 4.5968 -95.8798 -4.5968 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0140883 0.0127257 88 110 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_127.v common 4.22 vpr 63.79 MiB -1 -1 0.18 18436 12 0.24 -1 -1 32436 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65324 32 32 300 332 1 224 87 17 17 289 -1 unnamed_device 24.8 MiB 0.34 3045 1374 8343 1969 5805 569 63.8 MiB 0.06 0.00 9.97086 7.70352 -168.911 -7.70352 7.70352 0.25 0.000460963 0.000421707 0.0249877 0.0229274 -1 -1 -1 -1 38 3802 30 6.79088e+06 309856 678818. 2348.85 2.16 0.213639 0.188965 25966 169698 -1 3001 21 1702 4852 241275 56642 6.49817 6.49817 -159.124 -6.49817 0 0 902133. 3121.57 0.03 0.07 0.09 -1 -1 0.03 0.029603 0.0270055 149 206 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_128.v common 8.43 vpr 64.56 MiB -1 -1 0.18 18676 13 0.28 -1 -1 31596 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66108 31 32 290 322 1 214 89 17 17 289 -1 unnamed_device 24.9 MiB 0.67 2884 1321 10979 2886 6026 2067 64.6 MiB 0.06 0.00 10.7249 8.28064 -170.23 -8.28064 8.28064 0.24 0.000458984 0.000419435 0.0290037 0.0265888 -1 -1 -1 -1 30 4442 39 6.79088e+06 350272 556674. 1926.21 5.83 0.209846 0.18645 24526 138013 -1 3137 25 1751 5411 317221 91806 6.76345 6.76345 -158.739 -6.76345 0 0 706193. 2443.58 0.04 0.14 0.11 -1 -1 0.04 0.0497607 0.0449491 152 199 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_001.v common 5.80 vpr 65.13 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29804 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66692 32 32 354 285 1 207 93 17 17 289 -1 unnamed_device 25.6 MiB 2.12 2779 1278 16893 5344 9435 2114 65.1 MiB 0.10 0.00 6.98757 5.68891 -164.239 -5.68891 5.68891 0.25 0.000338691 0.000310099 0.0300408 0.0274606 -1 -1 -1 -1 28 3219 28 6.87369e+06 405241 531479. 1839.03 2.22 0.157807 0.138497 24610 126494 -1 2606 22 1750 2807 239588 55064 4.64695 4.64695 -157.22 -4.64695 0 0 648988. 2245.63 0.04 0.10 0.07 -1 -1 0.04 0.0310265 0.0277948 140 50 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_002.v common 4.10 vpr 65.14 MiB -1 -1 0.15 18060 1 0.04 -1 -1 29588 -1 -1 26 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66700 30 32 363 293 1 200 88 17 17 289 -1 unnamed_device 25.2 MiB 2.26 2339 1135 13153 3755 7866 1532 65.1 MiB 0.07 0.00 5.6483 4.6679 -138.364 -4.6679 4.6679 0.25 0.000376387 0.000339735 0.0260552 0.0238597 -1 -1 -1 -1 32 2500 24 6.87369e+06 363320 586450. 2029.24 0.40 0.0720625 0.0638607 25474 144626 -1 2037 21 1653 2504 161353 39229 3.72316 3.72316 -133.558 -3.72316 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.018555 0.0164825 138 63 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_003.v common 4.52 vpr 64.16 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29804 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65700 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 24.8 MiB 1.92 2478 1094 14965 5159 7778 2028 64.2 MiB 0.08 0.00 5.41115 4.32745 -123.858 -4.32745 4.32745 0.26 0.00029771 0.000272503 0.0284356 0.0260371 -1 -1 -1 -1 32 2462 24 6.87369e+06 293451 586450. 2029.24 1.20 0.158071 0.138595 25474 144626 -1 1923 20 1108 1542 96591 24435 3.88596 3.88596 -121.789 -3.88596 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0144447 0.012843 118 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_004.v common 3.08 vpr 64.42 MiB -1 -1 0.12 18064 1 0.04 -1 -1 29732 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 29 32 308 248 1 172 90 17 17 289 -1 unnamed_device 24.9 MiB 0.98 2239 851 8532 2063 5786 683 64.4 MiB 0.06 0.00 5.55862 4.64138 -122.547 -4.64138 4.64138 0.26 0.000307462 0.000282124 0.0164768 0.0151923 -1 -1 -1 -1 32 2081 20 6.87369e+06 405241 586450. 2029.24 0.62 0.0640387 0.056848 25474 144626 -1 1662 22 1299 2371 141246 35332 3.7854 3.7854 -114.536 -3.7854 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0152355 0.0135343 124 31 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_005.v common 3.79 vpr 65.01 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29848 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66568 32 32 336 268 1 181 91 17 17 289 -1 unnamed_device 25.2 MiB 1.26 2579 1028 12331 3533 8153 645 65.0 MiB 0.07 0.00 5.58731 4.58138 -133.975 -4.58138 4.58138 0.25 0.00032842 0.00029842 0.0222301 0.0202265 -1 -1 -1 -1 34 2450 23 6.87369e+06 377294 618332. 2139.56 1.15 0.13371 0.116761 25762 151098 -1 2095 20 1351 2747 172345 43095 3.7624 3.7624 -131.476 -3.7624 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.015162 0.0134923 132 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_006.v common 4.58 vpr 65.02 MiB -1 -1 0.14 18448 1 0.03 -1 -1 29780 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 32 32 366 295 1 189 96 17 17 289 -1 unnamed_device 25.6 MiB 1.47 2521 1045 10389 2533 6980 876 65.0 MiB 0.11 0.00 4.09707 3.40153 -116.732 -3.40153 3.40153 0.44 0.000632207 0.000578463 0.0332248 0.0304864 -1 -1 -1 -1 30 2392 22 6.87369e+06 447163 556674. 1926.21 1.17 0.156714 0.137506 25186 138497 -1 1903 19 1087 1810 94547 23615 2.90721 2.90721 -116.443 -2.90721 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0210304 0.0187682 138 58 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_007.v common 4.53 vpr 64.02 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30528 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 27 32 259 221 1 141 80 17 17 289 -1 unnamed_device 24.9 MiB 2.14 1624 653 12120 3521 6665 1934 64.0 MiB 0.09 0.00 4.57488 3.84098 -103.196 -3.84098 3.84098 0.44 0.000480389 0.000439216 0.0357836 0.0328233 -1 -1 -1 -1 30 1522 20 6.87369e+06 293451 556674. 1926.21 0.59 0.0942957 0.0835691 25186 138497 -1 1227 20 894 1556 82299 20516 2.81866 2.81866 -96.2951 -2.81866 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0122356 0.0108607 97 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_008.v common 2.67 vpr 64.45 MiB -1 -1 0.19 17672 1 0.02 -1 -1 29744 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 31 32 271 219 1 164 96 17 17 289 -1 unnamed_device 24.9 MiB 0.68 2063 1017 12798 3323 7724 1751 64.4 MiB 0.06 0.00 4.11555 3.57969 -107.766 -3.57969 3.57969 0.31 0.000280987 0.000257318 0.0179421 0.0164247 -1 -1 -1 -1 32 2056 21 6.87369e+06 461137 586450. 2029.24 0.37 0.0598981 0.0528727 25474 144626 -1 1863 18 869 1628 98904 24067 2.70166 2.70166 -100.41 -2.70166 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0134961 0.0120734 119 4 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_009.v common 3.65 vpr 64.42 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29768 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 31 32 317 271 1 175 83 17 17 289 -1 unnamed_device 24.9 MiB 1.75 2074 1069 13943 3853 8284 1806 64.4 MiB 0.08 0.00 4.71896 3.59126 -121.314 -3.59126 3.59126 0.26 0.000300172 0.000275204 0.0327664 0.030306 -1 -1 -1 -1 32 2340 23 6.87369e+06 279477 586450. 2029.24 0.41 0.0792721 0.0707055 25474 144626 -1 1994 22 1117 1624 122047 28163 2.96331 2.96331 -117.189 -2.96331 0 0 744469. 2576.02 0.05 0.07 0.11 -1 -1 0.05 0.0269692 0.0240161 110 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_010.v common 5.50 vpr 64.53 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29756 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 298 248 1 162 81 17 17 289 -1 unnamed_device 25.1 MiB 2.97 1876 975 12681 3745 6747 2189 64.5 MiB 0.07 0.00 4.66108 3.90928 -131.51 -3.90928 3.90928 0.25 0.00030816 0.000282988 0.0298978 0.0278187 -1 -1 -1 -1 32 2119 22 6.87369e+06 237555 586450. 2029.24 1.04 0.113415 0.0997871 25474 144626 -1 1840 18 1127 1808 118643 28174 3.01796 3.01796 -123.051 -3.01796 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0243406 0.0217732 107 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_011.v common 4.92 vpr 64.09 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29796 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65624 30 32 303 262 1 148 80 17 17 289 -1 unnamed_device 24.9 MiB 2.42 1634 783 11948 4947 6106 895 64.1 MiB 0.05 0.00 4.23198 3.85608 -112.834 -3.85608 3.85608 0.25 0.000296286 0.000271011 0.0217417 0.0199276 -1 -1 -1 -1 28 2153 36 6.87369e+06 251529 531479. 1839.03 1.18 0.116888 0.101806 24610 126494 -1 1655 22 1103 1769 168234 43143 3.01626 3.01626 -112.104 -3.01626 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0149998 0.0130769 99 63 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_012.v common 4.20 vpr 64.57 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29732 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 24.8 MiB 1.84 2449 1027 12898 3673 7248 1977 64.6 MiB 0.07 0.00 4.7813 3.6715 -118.222 -3.6715 3.6715 0.25 0.000276217 0.00025305 0.0233421 0.0213867 -1 -1 -1 -1 32 2217 20 6.87369e+06 251529 586450. 2029.24 0.99 0.121125 0.105513 25474 144626 -1 1865 18 1024 1435 104148 24249 2.77201 2.77201 -111.424 -2.77201 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0124142 0.0110837 102 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_013.v common 6.02 vpr 64.56 MiB -1 -1 0.21 18060 1 0.04 -1 -1 29956 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66108 32 32 344 272 1 209 89 17 17 289 -1 unnamed_device 24.9 MiB 2.77 2479 1044 14147 4566 6974 2607 64.6 MiB 0.08 0.00 4.50463 4.21693 -134.575 -4.21693 4.21693 0.30 0.000329492 0.000301485 0.0259677 0.0238215 -1 -1 -1 -1 30 2730 27 6.87369e+06 349346 556674. 1926.21 1.60 0.132473 0.116447 25186 138497 -1 1999 23 1665 2538 150407 37762 3.15591 3.15591 -119.224 -3.15591 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0170917 0.0151913 139 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_014.v common 4.56 vpr 64.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29804 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66292 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 25.4 MiB 2.01 2505 986 14999 4213 8032 2754 64.7 MiB 0.08 0.00 5.95652 4.79778 -139.915 -4.79778 4.79778 0.25 0.000334016 0.000305104 0.0255084 0.0233651 -1 -1 -1 -1 32 2454 25 6.87369e+06 433189 586450. 2029.24 1.07 0.12617 0.110398 25474 144626 -1 1945 22 1516 2402 150206 37108 3.67906 3.67906 -131.28 -3.67906 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0168173 0.0149209 133 61 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_015.v common 3.07 vpr 64.52 MiB -1 -1 0.15 17676 1 0.02 -1 -1 29868 -1 -1 21 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66068 29 32 248 215 1 142 82 17 17 289 -1 unnamed_device 24.9 MiB 1.40 1696 858 12008 3401 6739 1868 64.5 MiB 0.05 0.00 3.78522 3.15872 -98.3476 -3.15872 3.15872 0.24 0.00026521 0.000242593 0.018962 0.017341 -1 -1 -1 -1 30 1702 24 6.87369e+06 293451 556674. 1926.21 0.33 0.0533522 0.046956 25186 138497 -1 1492 19 693 1109 62576 15355 2.83796 2.83796 -99.8638 -2.83796 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0116954 0.0103542 94 27 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 4.40 vpr 64.64 MiB -1 -1 0.19 18440 1 0.03 -1 -1 30168 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 370 297 1 191 88 17 17 289 -1 unnamed_device 25.2 MiB 1.60 2351 1142 14908 4316 8497 2095 64.6 MiB 0.09 0.00 4.2467 3.7455 -126.819 -3.7455 3.7455 0.30 0.000339557 0.000310568 0.0292364 0.026805 -1 -1 -1 -1 32 2773 22 6.87369e+06 335372 586450. 2029.24 1.07 0.140584 0.122861 25474 144626 -1 2188 19 1521 2634 169491 39910 2.97426 2.97426 -122.17 -2.97426 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0158553 0.0142194 135 58 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 4.43 vpr 65.07 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29816 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66636 32 32 338 269 1 204 87 17 17 289 -1 unnamed_device 25.2 MiB 2.59 2594 1106 15639 5153 7404 3082 65.1 MiB 0.09 0.00 5.08229 4.18625 -135.173 -4.18625 4.18625 0.24 0.00034271 0.000315029 0.0333882 0.030975 -1 -1 -1 -1 30 2654 25 6.87369e+06 321398 556674. 1926.21 0.39 0.0779122 0.0697554 25186 138497 -1 2046 22 1375 2028 125721 30050 3.0509 3.0509 -118.831 -3.0509 0 0 706193. 2443.58 0.03 0.04 0.10 -1 -1 0.03 0.0182401 0.0161792 136 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_018.v common 4.70 vpr 64.24 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30116 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 32 32 323 276 1 156 93 17 17 289 -1 unnamed_device 24.7 MiB 2.05 2257 926 17103 5432 9461 2210 64.2 MiB 0.13 0.00 3.68501 2.85191 -105.908 -2.85191 2.85191 0.25 0.000847649 0.000787011 0.0450084 0.0415445 -1 -1 -1 -1 32 2002 22 6.87369e+06 405241 586450. 2029.24 1.10 0.152835 0.134719 25474 144626 -1 1661 17 1142 1944 120028 29235 2.07352 2.07352 -97.0447 -2.07352 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0127224 0.0113475 110 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_019.v common 2.78 vpr 63.89 MiB -1 -1 0.10 17528 1 0.02 -1 -1 29868 -1 -1 15 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65420 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 24.9 MiB 0.53 1506 681 11976 4667 6344 965 63.9 MiB 0.05 0.00 2.88898 2.40568 -84.2035 -2.40568 2.40568 0.35 0.000230573 0.000210344 0.0181275 0.0165527 -1 -1 -1 -1 34 1276 19 6.87369e+06 209608 618332. 2139.56 0.88 0.0736418 0.0640869 25762 151098 -1 1140 17 567 794 53109 12483 1.81522 1.81522 -81.3143 -1.81522 0 0 787024. 2723.27 0.03 0.02 0.08 -1 -1 0.03 0.00970028 0.00862224 71 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 4.51 vpr 64.20 MiB -1 -1 0.12 18060 1 0.02 -1 -1 29796 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65744 31 32 291 243 1 178 84 17 17 289 -1 unnamed_device 24.9 MiB 2.19 2220 961 14358 5263 6619 2476 64.2 MiB 0.08 0.00 6.07113 5.06873 -151.735 -5.06873 5.06873 0.25 0.000358414 0.000333638 0.0281325 0.0259646 -1 -1 -1 -1 30 2126 21 6.87369e+06 293451 556674. 1926.21 0.97 0.119718 0.104846 25186 138497 -1 1726 21 1006 1462 90107 22146 3.69941 3.69941 -133.261 -3.69941 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0147264 0.013189 114 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 3.28 vpr 64.35 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29956 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 342 271 1 181 99 17 17 289 -1 unnamed_device 24.9 MiB 0.78 2270 1098 17427 5042 9940 2445 64.3 MiB 0.10 0.00 5.48809 4.18395 -137.714 -4.18395 4.18395 0.25 0.000328306 0.000300353 0.0313602 0.0288796 -1 -1 -1 -1 28 2563 20 6.87369e+06 489084 531479. 1839.03 1.15 0.149045 0.131128 24610 126494 -1 2239 21 1371 2094 147615 35637 4.016 4.016 -141.152 -4.016 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0159409 0.014208 137 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_022.v common 4.53 vpr 64.32 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29916 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65868 32 32 372 300 1 206 87 17 17 289 -1 unnamed_device 24.9 MiB 1.91 2678 1260 15255 4028 9506 1721 64.3 MiB 0.10 0.00 5.24603 4.32815 -136.261 -4.32815 4.32815 0.25 0.000453897 0.000414665 0.0367843 0.0339982 -1 -1 -1 -1 30 2840 29 6.87369e+06 321398 556674. 1926.21 1.17 0.148596 0.131521 25186 138497 -1 2225 19 1315 2150 129279 30551 3.85476 3.85476 -132.586 -3.85476 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0156418 0.0140089 138 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_023.v common 3.40 vpr 64.21 MiB -1 -1 0.10 18060 1 0.02 -1 -1 29792 -1 -1 18 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 26 32 190 182 1 108 76 17 17 289 -1 unnamed_device 25.2 MiB 1.35 1317 566 8396 2777 4117 1502 64.2 MiB 0.04 0.00 3.13338 2.41583 -71.9717 -2.41583 2.41583 0.25 0.000203836 0.000182325 0.0145818 0.0134291 -1 -1 -1 -1 26 1284 21 6.87369e+06 251529 503264. 1741.40 0.75 0.0793038 0.0686608 24322 120374 -1 1126 22 717 1085 75720 19389 2.17212 2.17212 -75.7209 -2.17212 0 0 618332. 2139.56 0.02 0.03 0.06 -1 -1 0.02 0.0101223 0.00893365 67 30 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 3.30 vpr 64.92 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30152 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 32 32 285 227 1 169 88 17 17 289 -1 unnamed_device 24.9 MiB 0.94 2097 1049 14908 4450 8551 1907 64.9 MiB 0.08 0.00 5.2197 4.59222 -130.8 -4.59222 4.59222 0.24 0.000295354 0.0002705 0.0241002 0.0220402 -1 -1 -1 -1 32 2268 21 6.87369e+06 335372 586450. 2029.24 1.03 0.112059 0.0980207 25474 144626 -1 1966 21 1268 2283 143914 34546 3.7121 3.7121 -127.472 -3.7121 0 0 744469. 2576.02 0.03 0.04 0.09 -1 -1 0.03 0.014224 0.0126546 120 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 2.03 vpr 64.13 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29712 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 25.2 MiB 0.51 1340 735 9836 2832 5893 1111 64.1 MiB 0.03 0.00 2.66305 2.35478 -79.4936 -2.35478 2.35478 0.25 0.000195429 0.000177475 0.0131108 0.011945 -1 -1 -1 -1 28 1349 20 6.87369e+06 167686 531479. 1839.03 0.31 0.0383427 0.0336698 24610 126494 -1 1279 18 595 720 57806 14512 1.93882 1.93882 -81.3285 -1.93882 0 0 648988. 2245.63 0.02 0.03 0.07 -1 -1 0.02 0.011158 0.00985811 64 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 2.88 vpr 63.77 MiB -1 -1 0.12 18056 1 0.02 -1 -1 30152 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 24.9 MiB 0.98 2085 932 9892 2528 6924 440 63.8 MiB 0.11 0.00 5.60262 4.76542 -131.149 -4.76542 4.76542 0.30 0.000296832 0.000272087 0.035253 0.0326811 -1 -1 -1 -1 26 2518 22 6.87369e+06 419215 503264. 1741.40 0.49 0.0786368 0.0705901 24322 120374 -1 2096 32 1737 2939 210434 50691 3.872 3.872 -127.362 -3.872 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0198711 0.0174655 120 24 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 3.39 vpr 64.89 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29944 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66452 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 24.9 MiB 0.79 2474 1054 16727 4817 9341 2569 64.9 MiB 0.09 0.00 4.54391 3.51795 -111.316 -3.51795 3.51795 0.29 0.000303592 0.000276236 0.0266519 0.0242859 -1 -1 -1 -1 28 2471 24 6.87369e+06 433189 531479. 1839.03 1.06 0.125733 0.110248 24610 126494 -1 2110 19 1290 2308 150392 36562 2.98246 2.98246 -112.166 -2.98246 0 0 648988. 2245.63 0.02 0.04 0.14 -1 -1 0.02 0.014283 0.0127629 130 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_028.v common 3.50 vpr 65.02 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29752 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 338 277 1 183 93 17 17 289 -1 unnamed_device 25.0 MiB 1.17 2236 1093 11433 2910 6842 1681 65.0 MiB 0.06 0.00 5.66492 4.81048 -136.943 -4.81048 4.81048 0.25 0.000325641 0.000298897 0.0192171 0.0176088 -1 -1 -1 -1 30 2323 24 6.87369e+06 405241 556674. 1926.21 0.99 0.124524 0.108552 25186 138497 -1 1955 23 1075 1929 108605 26660 3.99996 3.99996 -133.755 -3.99996 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0163959 0.0145775 128 50 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_029.v common 2.55 vpr 64.41 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29808 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65960 32 32 284 241 1 148 82 17 17 289 -1 unnamed_device 24.9 MiB 0.78 1785 959 11118 3077 6379 1662 64.4 MiB 0.06 0.00 3.63792 3.01142 -107.753 -3.01142 3.01142 0.35 0.000279667 0.000255769 0.0214261 0.019741 -1 -1 -1 -1 32 1994 19 6.87369e+06 251529 586450. 2029.24 0.35 0.0582033 0.0516193 25474 144626 -1 1714 18 879 1436 101674 23709 2.60666 2.60666 -105.374 -2.60666 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.012868 0.011506 101 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_030.v common 3.41 vpr 64.49 MiB -1 -1 0.11 17912 1 0.02 -1 -1 29832 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 30 32 262 227 1 138 84 17 17 289 -1 unnamed_device 24.9 MiB 0.91 1644 645 11979 4232 5199 2548 64.5 MiB 0.06 0.00 3.71922 3.04032 -95.3449 -3.04032 3.04032 0.24 0.000643706 0.000601065 0.0220199 0.0202565 -1 -1 -1 -1 34 1737 24 6.87369e+06 307425 618332. 2139.56 1.12 0.115953 0.101499 25762 151098 -1 1305 21 903 1431 87262 23733 2.94926 2.94926 -95.9302 -2.94926 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0131376 0.0116079 95 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_031.v common 3.63 vpr 63.98 MiB -1 -1 0.18 17676 1 0.03 -1 -1 29688 -1 -1 19 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65516 28 32 260 223 1 140 79 17 17 289 -1 unnamed_device 24.9 MiB 1.12 2176 705 11233 3031 6920 1282 64.0 MiB 0.05 0.00 4.53245 3.58631 -100.001 -3.58631 3.58631 0.24 0.000258351 0.000236282 0.018592 0.0170282 -1 -1 -1 -1 34 1817 24 6.87369e+06 265503 618332. 2139.56 1.09 0.101843 0.0884679 25762 151098 -1 1498 21 1087 2028 123464 32422 2.82496 2.82496 -100.192 -2.82496 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0132302 0.0117007 96 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_032.v common 3.29 vpr 64.43 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30216 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65972 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 24.7 MiB 1.03 2154 721 8092 1745 5645 702 64.4 MiB 0.04 0.00 4.63718 3.86314 -115.034 -3.86314 3.86314 0.26 0.000269999 0.000245848 0.0141003 0.0128609 -1 -1 -1 -1 32 1894 22 6.87369e+06 251529 586450. 2029.24 1.00 0.0989113 0.085688 25474 144626 -1 1497 16 987 1649 88162 23720 2.96326 2.96326 -109.749 -2.96326 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0110703 0.00990835 101 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_033.v common 2.78 vpr 64.53 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29760 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 31 32 271 231 1 149 89 17 17 289 -1 unnamed_device 24.9 MiB 0.78 1850 927 12563 3215 8032 1316 64.5 MiB 0.06 0.00 4.00125 3.42265 -107.908 -3.42265 3.42265 0.27 0.000276398 0.000253509 0.0189718 0.0173754 -1 -1 -1 -1 32 1906 22 6.87369e+06 363320 586450. 2029.24 0.42 0.0676784 0.0597762 25474 144626 -1 1629 20 901 1604 91239 22844 2.75166 2.75166 -105.307 -2.75166 0 0 744469. 2576.02 0.04 0.05 0.14 -1 -1 0.04 0.0210922 0.018721 102 30 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_034.v common 4.49 vpr 64.58 MiB -1 -1 0.18 18060 1 0.03 -1 -1 30212 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66128 29 32 291 250 1 154 86 17 17 289 -1 unnamed_device 24.9 MiB 2.38 2244 863 12938 3817 7914 1207 64.6 MiB 0.06 0.00 3.77556 3.08002 -100.294 -3.08002 3.08002 0.25 0.000282356 0.000258955 0.0207796 0.0190526 -1 -1 -1 -1 30 1838 22 6.87369e+06 349346 556674. 1926.21 0.69 0.093284 0.0814168 25186 138497 -1 1561 17 902 1386 82031 19933 2.25347 2.25347 -93.7602 -2.25347 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0118709 0.010591 105 54 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_035.v common 5.18 vpr 65.22 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29612 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 32 32 367 282 1 201 104 17 17 289 -1 unnamed_device 25.2 MiB 2.42 2344 1146 10352 2228 7273 851 65.2 MiB 0.07 0.00 4.92569 4.24719 -123.08 -4.24719 4.24719 0.27 0.000368919 0.000338189 0.0189776 0.0174183 -1 -1 -1 -1 28 2900 23 6.87369e+06 558954 531479. 1839.03 1.33 0.141629 0.123881 24610 126494 -1 2537 22 1665 3171 206581 51344 4.0723 4.0723 -130.143 -4.0723 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0174867 0.0155615 156 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_036.v common 4.25 vpr 64.88 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30132 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 391 311 1 194 104 17 17 289 -1 unnamed_device 24.8 MiB 2.37 2402 1081 18892 5390 10690 2812 64.9 MiB 0.10 0.00 4.68095 4.00848 -135.306 -4.00848 4.00848 0.24 0.000357663 0.00032748 0.0300492 0.0273707 -1 -1 -1 -1 32 2374 22 6.87369e+06 558954 586450. 2029.24 0.39 0.0788336 0.06992 25474 144626 -1 2026 19 1508 2475 143567 35245 3.17446 3.17446 -127.465 -3.17446 0 0 744469. 2576.02 0.03 0.04 0.16 -1 -1 0.03 0.0159635 0.0142608 149 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 3.90 vpr 64.01 MiB -1 -1 0.18 18060 1 0.03 -1 -1 29492 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65544 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 24.9 MiB 1.82 2434 993 8831 2488 5523 820 64.0 MiB 0.05 0.00 4.95083 4.14789 -126.829 -4.14789 4.14789 0.25 0.000284845 0.000261619 0.0156499 0.0143835 -1 -1 -1 -1 32 2206 21 6.87369e+06 251529 586450. 2029.24 0.39 0.0531276 0.0469574 25474 144626 -1 1881 19 958 1525 103993 24504 3.15461 3.15461 -119.875 -3.15461 0 0 744469. 2576.02 0.04 0.05 0.14 -1 -1 0.04 0.0169656 0.0150243 106 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_038.v common 4.62 vpr 65.14 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29212 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66704 31 32 370 297 1 187 89 17 17 289 -1 unnamed_device 25.6 MiB 1.93 2217 1129 14147 4459 7560 2128 65.1 MiB 0.14 0.00 4.3461 3.7686 -123.743 -3.7686 3.7686 0.28 0.000620839 0.000567351 0.0472881 0.0432612 -1 -1 -1 -1 32 2620 20 6.87369e+06 363320 586450. 2029.24 1.22 0.166856 0.146757 25474 144626 -1 2210 20 1429 2447 155773 36552 3.00426 3.00426 -116.646 -3.00426 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0161313 0.0143767 136 61 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_039.v common 6.59 vpr 65.16 MiB -1 -1 0.17 18292 1 0.03 -1 -1 30164 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66720 31 32 377 302 1 237 92 17 17 289 -1 unnamed_device 25.3 MiB 2.75 2915 1335 13547 3729 7970 1848 65.2 MiB 0.09 0.00 6.76692 5.53978 -169.274 -5.53978 5.53978 0.26 0.000351561 0.000322679 0.025746 0.0236688 -1 -1 -1 -1 28 3654 23 6.87369e+06 405241 531479. 1839.03 2.34 0.14442 0.126946 24610 126494 -1 2988 22 2444 3552 326119 72975 5.20869 5.20869 -174.053 -5.20869 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0175115 0.0155948 155 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_040.v common 5.04 vpr 65.22 MiB -1 -1 0.18 18056 1 0.03 -1 -1 29792 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 31 32 383 305 1 212 91 17 17 289 -1 unnamed_device 25.2 MiB 3.04 2741 1334 14575 4470 8160 1945 65.2 MiB 0.09 0.00 6.34854 5.22459 -163.482 -5.22459 5.22459 0.25 0.000351439 0.000321335 0.0270274 0.0247642 -1 -1 -1 -1 32 3169 36 6.87369e+06 391268 586450. 2029.24 0.53 0.0967574 0.0859341 25474 144626 -1 2624 20 1587 2410 208304 44942 4.5599 4.5599 -158.949 -4.5599 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164815 0.0147252 151 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_041.v common 4.03 vpr 64.61 MiB -1 -1 0.18 18060 1 0.04 -1 -1 29768 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 31 32 352 285 1 186 92 17 17 289 -1 unnamed_device 24.9 MiB 2.19 2134 1048 14996 4681 7704 2611 64.6 MiB 0.08 0.00 4.61893 4.13563 -128.575 -4.13563 4.13563 0.24 0.000335656 0.000307486 0.025684 0.0235144 -1 -1 -1 -1 32 2650 22 6.87369e+06 405241 586450. 2029.24 0.39 0.0700836 0.0620377 25474 144626 -1 2076 22 1454 2414 153424 36772 3.09131 3.09131 -118.471 -3.09131 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0166059 0.0147621 133 55 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 4.06 vpr 64.91 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29768 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 291 242 1 183 86 17 17 289 -1 unnamed_device 24.9 MiB 1.85 2477 1095 15206 4442 8662 2102 64.9 MiB 0.08 0.00 5.51278 4.43075 -121.679 -4.43075 4.43075 0.25 0.000292028 0.0002669 0.0253669 0.0232324 -1 -1 -1 -1 28 2503 21 6.87369e+06 307425 531479. 1839.03 0.90 0.105951 0.0925844 24610 126494 -1 2252 18 1382 2015 133917 32844 4.15256 4.15256 -127.257 -4.15256 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0130387 0.0116467 114 27 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_043.v common 5.91 vpr 65.00 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29896 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 32 32 457 356 1 225 104 17 17 289 -1 unnamed_device 25.6 MiB 2.42 3065 1148 12304 2744 8146 1414 65.0 MiB 0.07 0.00 6.15708 4.89003 -155.75 -4.89003 4.89003 0.35 0.000421745 0.000385657 0.023456 0.0215124 -1 -1 -1 -1 30 3162 34 6.87369e+06 558954 556674. 1926.21 1.94 0.208648 0.182713 25186 138497 -1 2244 22 1501 2532 144540 36667 4.07996 4.07996 -146.784 -4.07996 0 0 706193. 2443.58 0.03 0.06 0.08 -1 -1 0.03 0.0238413 0.0212161 173 87 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_044.v common 3.27 vpr 64.49 MiB -1 -1 0.11 16980 1 0.03 -1 -1 29852 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 31 32 261 225 1 148 83 17 17 289 -1 unnamed_device 24.9 MiB 1.60 1997 648 8723 1892 5777 1054 64.5 MiB 0.04 0.00 4.27085 3.54105 -101.242 -3.54105 3.54105 0.24 0.000273941 0.000251112 0.0141802 0.0129943 -1 -1 -1 -1 30 1800 23 6.87369e+06 279477 556674. 1926.21 0.38 0.0500756 0.0439754 25186 138497 -1 1451 23 1102 1888 103072 27957 2.98326 2.98326 -102.512 -2.98326 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0136731 0.0120739 95 28 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_045.v common 5.40 vpr 65.09 MiB -1 -1 0.12 18064 1 0.03 -1 -1 29856 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 25.2 MiB 2.38 2833 1039 9058 2162 5891 1005 65.1 MiB 0.05 0.00 5.78298 4.80948 -141.445 -4.80948 4.80948 0.24 0.000334797 0.000307237 0.0177481 0.0163442 -1 -1 -1 -1 32 3153 40 6.87369e+06 349346 586450. 2029.24 1.70 0.143091 0.124424 25474 144626 -1 2143 18 1358 2000 125184 32958 3.90446 3.90446 -133.851 -3.90446 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0142968 0.0128029 139 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_046.v common 3.83 vpr 64.51 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29712 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 32 32 349 284 1 183 96 17 17 289 -1 unnamed_device 24.8 MiB 1.34 2291 1135 16740 4742 9662 2336 64.5 MiB 0.09 0.00 4.4574 3.7235 -119.349 -3.7235 3.7235 0.24 0.000325745 0.0002983 0.0287406 0.0263737 -1 -1 -1 -1 32 2604 22 6.87369e+06 447163 586450. 2029.24 1.09 0.136222 0.119082 25474 144626 -1 2160 22 1397 2353 160693 37464 2.99951 2.99951 -114.657 -2.99951 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164752 0.014613 133 53 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_047.v common 3.46 vpr 64.45 MiB -1 -1 0.14 17676 1 0.03 -1 -1 29764 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 291 230 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 1.06 1933 1125 13963 5217 7708 1038 64.5 MiB 0.08 0.00 4.86339 4.12259 -128.092 -4.12259 4.12259 0.34 0.000311483 0.000285719 0.023139 0.021179 -1 -1 -1 -1 30 2522 22 6.87369e+06 377294 556674. 1926.21 0.94 0.103938 0.0910827 25186 138497 -1 2070 22 1119 2125 158916 33999 3.6151 3.6151 -123.407 -3.6151 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0149392 0.0132718 123 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_048.v common 4.70 vpr 64.43 MiB -1 -1 0.12 18436 1 0.03 -1 -1 30156 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 32 32 353 287 1 203 88 17 17 289 -1 unnamed_device 25.1 MiB 2.35 2449 1198 10033 2856 6133 1044 64.4 MiB 0.08 0.00 5.38385 4.51686 -135.093 -4.51686 4.51686 0.24 0.000807747 0.000754987 0.0265271 0.0244839 -1 -1 -1 -1 28 2785 20 6.87369e+06 335372 531479. 1839.03 1.01 0.122769 0.108079 24610 126494 -1 2415 23 1599 2149 149891 36230 3.45411 3.45411 -130.575 -3.45411 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0173931 0.0154887 133 55 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_049.v common 4.46 vpr 64.64 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29752 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 361 291 1 189 97 17 17 289 -1 unnamed_device 25.2 MiB 2.43 2368 918 12307 3182 8052 1073 64.6 MiB 0.07 0.00 4.4072 3.86034 -120.004 -3.86034 3.86034 0.35 0.00033864 0.000309864 0.0204635 0.0187149 -1 -1 -1 -1 32 2307 29 6.87369e+06 461137 586450. 2029.24 0.44 0.0695487 0.0614194 25474 144626 -1 1780 19 1175 2009 111141 30153 3.17181 3.17181 -113.554 -3.17181 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0255044 0.0228037 137 55 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_050.v common 4.27 vpr 65.20 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30244 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66768 32 32 382 305 1 193 99 17 17 289 -1 unnamed_device 25.2 MiB 2.29 2780 1180 19251 5845 10953 2453 65.2 MiB 0.11 0.00 4.88053 4.12873 -137.656 -4.12873 4.12873 0.25 0.000352547 0.000322509 0.0316187 0.0288943 -1 -1 -1 -1 30 2658 24 6.87369e+06 489084 556674. 1926.21 0.42 0.0788497 0.0700438 25186 138497 -1 2203 22 1272 2103 125088 30094 3.13881 3.13881 -123.39 -3.13881 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0173831 0.0154972 145 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_051.v common 3.73 vpr 64.93 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29780 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 306 248 1 170 97 17 17 289 -1 unnamed_device 24.9 MiB 0.73 2039 950 16747 5537 7489 3721 64.9 MiB 0.09 0.00 4.87439 4.39109 -126.937 -4.39109 4.39109 0.24 0.000739823 0.00069028 0.0312699 0.0286694 -1 -1 -1 -1 32 2421 33 6.87369e+06 461137 586450. 2029.24 1.56 0.147368 0.129021 25474 144626 -1 1887 19 1239 2208 161661 39936 3.8374 3.8374 -122.561 -3.8374 0 0 744469. 2576.02 0.04 0.07 0.11 -1 -1 0.04 0.0221875 0.0198695 124 24 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_052.v common 3.98 vpr 63.73 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29584 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65256 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 24.7 MiB 1.52 2220 1156 13527 3541 8079 1907 63.7 MiB 0.08 0.00 5.73418 4.82931 -141.931 -4.82931 4.82931 0.25 0.00030882 0.000282743 0.0239023 0.0219138 -1 -1 -1 -1 32 2802 25 6.87369e+06 321398 586450. 2029.24 1.00 0.110833 0.096714 25474 144626 -1 2292 20 1462 2137 136001 32714 3.76576 3.76576 -131.742 -3.76576 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0146108 0.0130258 129 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 3.68 vpr 64.53 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30160 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 31 32 373 299 1 204 87 17 17 289 -1 unnamed_device 25.0 MiB 1.72 3065 1027 11415 2970 7272 1173 64.5 MiB 0.14 0.00 6.22918 4.75448 -142.391 -4.75448 4.75448 0.28 0.000987483 0.000915055 0.0501293 0.0464441 -1 -1 -1 -1 32 2875 29 6.87369e+06 335372 586450. 2029.24 0.48 0.0988957 0.0888001 25474 144626 -1 2254 24 1603 2664 177040 43531 3.86846 3.86846 -138.859 -3.86846 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0184397 0.0164021 140 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_054.v common 5.11 vpr 64.59 MiB -1 -1 0.13 18056 1 0.04 -1 -1 30260 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66140 32 32 387 315 1 194 86 17 17 289 -1 unnamed_device 25.2 MiB 2.03 2512 933 14072 5096 6356 2620 64.6 MiB 0.08 0.00 5.37753 4.33435 -129.429 -4.33435 4.33435 0.26 0.00035546 0.000324775 0.0324406 0.0297238 -1 -1 -1 -1 36 2716 47 6.87369e+06 307425 648988. 2245.63 1.52 0.178156 0.156102 26050 158493 -1 1916 20 1476 2587 164969 42265 3.74066 3.74066 -126.184 -3.74066 0 0 828058. 2865.25 0.03 0.05 0.16 -1 -1 0.03 0.016656 0.0148392 134 77 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_055.v common 2.54 vpr 64.50 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29788 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 251 219 1 141 87 17 17 289 -1 unnamed_device 24.7 MiB 0.72 1844 681 8727 1897 6216 614 64.5 MiB 0.04 0.00 4.11555 3.50043 -101.627 -3.50043 3.50043 0.24 0.000263113 0.000240025 0.0133071 0.0121657 -1 -1 -1 -1 28 2084 39 6.87369e+06 321398 531479. 1839.03 0.52 0.0574569 0.050311 24610 126494 -1 1578 21 1147 1792 117952 31406 2.70196 2.70196 -100.629 -2.70196 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0127218 0.0112708 93 23 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_056.v common 3.75 vpr 64.36 MiB -1 -1 0.12 18060 1 0.04 -1 -1 30204 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 32 32 341 285 1 188 84 17 17 289 -1 unnamed_device 25.2 MiB 1.54 2256 885 8868 2113 6056 699 64.4 MiB 0.05 0.00 4.91669 4.05749 -134.722 -4.05749 4.05749 0.25 0.000319097 0.00029131 0.0168116 0.0154068 -1 -1 -1 -1 32 2587 38 6.87369e+06 279477 586450. 2029.24 0.66 0.0980793 0.0867185 25474 144626 -1 1878 20 1605 2345 172300 41500 3.30791 3.30791 -127.081 -3.30791 0 0 744469. 2576.02 0.03 0.10 0.08 -1 -1 0.03 0.0359951 0.0321136 120 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_057.v common 4.72 vpr 65.30 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29816 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66864 32 32 387 293 1 236 93 17 17 289 -1 unnamed_device 25.6 MiB 2.03 2858 1452 14373 4135 8862 1376 65.3 MiB 0.09 0.00 6.54252 5.67053 -168.179 -5.67053 5.67053 0.26 0.000367846 0.000336898 0.0279177 0.0256551 -1 -1 -1 -1 32 3361 38 6.87369e+06 405241 586450. 2029.24 1.27 0.174645 0.153213 25474 144626 -1 2769 22 1643 2597 165910 40569 4.6651 4.6651 -156.548 -4.6651 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0186054 0.0166428 164 31 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_058.v common 3.95 vpr 64.71 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29944 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 32 32 340 270 1 185 98 17 17 289 -1 unnamed_device 25.2 MiB 2.19 2646 1109 17198 4503 10702 1993 64.7 MiB 0.09 0.00 5.22181 4.34585 -138.752 -4.34585 4.34585 0.24 0.000328609 0.000299932 0.0269673 0.0246622 -1 -1 -1 -1 32 2400 41 6.87369e+06 475111 586450. 2029.24 0.39 0.0787899 0.0696865 25474 144626 -1 1955 21 1277 2204 125556 30508 2.86466 2.86466 -118.79 -2.86466 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.01591 0.0142043 137 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_059.v common 2.33 vpr 64.59 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29824 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66140 30 32 278 235 1 150 87 17 17 289 -1 unnamed_device 25.2 MiB 0.61 2187 808 9879 2531 6399 949 64.6 MiB 0.05 0.00 4.30385 3.42675 -104.9 -3.42675 3.42675 0.24 0.000283569 0.000258971 0.0157083 0.0143422 -1 -1 -1 -1 26 2066 25 6.87369e+06 349346 503264. 1741.40 0.40 0.0537143 0.0471404 24322 120374 -1 1867 26 1418 2313 162293 41447 3.43946 3.43946 -116.403 -3.43946 0 0 618332. 2139.56 0.02 0.06 0.07 -1 -1 0.02 0.0217145 0.0191615 104 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_060.v common 5.58 vpr 65.42 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29800 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66992 32 32 431 332 1 239 91 17 17 289 -1 unnamed_device 25.6 MiB 3.74 2820 1401 12535 3692 7672 1171 65.4 MiB 0.08 0.00 6.88686 5.84665 -173.286 -5.84665 5.84665 0.24 0.000419434 0.000387317 0.0280962 0.0259362 -1 -1 -1 -1 32 3289 23 6.87369e+06 377294 586450. 2029.24 0.45 0.0856957 0.0766235 25474 144626 -1 2597 22 1840 2810 199075 44926 4.4923 4.4923 -155.353 -4.4923 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0201657 0.0180183 166 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_061.v common 4.33 vpr 64.54 MiB -1 -1 0.19 18448 1 0.03 -1 -1 29960 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 32 32 336 268 1 182 99 17 17 289 -1 unnamed_device 24.9 MiB 2.38 2019 1059 12867 3257 7846 1764 64.5 MiB 0.08 0.00 5.26892 4.63938 -140.042 -4.63938 4.63938 0.33 0.000319991 0.000293027 0.0261935 0.0241675 -1 -1 -1 -1 32 2403 25 6.87369e+06 489084 586450. 2029.24 0.40 0.0756114 0.0675688 25474 144626 -1 1978 19 1375 2255 145823 36321 3.5567 3.5567 -129.487 -3.5567 0 0 744469. 2576.02 0.03 0.05 0.09 -1 -1 0.03 0.0171303 0.0153048 135 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_062.v common 2.49 vpr 64.31 MiB -1 -1 0.11 17148 1 0.02 -1 -1 30328 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 25.2 MiB 0.63 1762 855 12512 3348 8365 799 64.3 MiB 0.05 0.00 3.96025 3.6312 -105.59 -3.6312 3.6312 0.24 0.000255426 0.000233116 0.0167194 0.015257 -1 -1 -1 -1 28 1989 22 6.87369e+06 391268 531479. 1839.03 0.34 0.0495916 0.0435939 24610 126494 -1 1736 22 999 1747 115875 28970 2.92726 2.92726 -105.066 -2.92726 0 0 648988. 2245.63 0.04 0.06 0.12 -1 -1 0.04 0.0205974 0.0181628 96 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_063.v common 4.97 vpr 65.02 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29572 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 349 273 1 191 101 17 17 289 -1 unnamed_device 25.6 MiB 1.72 2736 1219 17491 4613 10519 2359 65.0 MiB 0.10 0.00 6.69567 5.1464 -138.872 -5.1464 5.1464 0.31 0.000341259 0.000311913 0.0305984 0.0281463 -1 -1 -1 -1 26 2928 24 6.87369e+06 517032 503264. 1741.40 1.78 0.151555 0.13355 24322 120374 -1 2550 23 1721 3309 237917 56001 4.68785 4.68785 -144.023 -4.68785 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.017333 0.0153937 145 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_064.v common 2.60 vpr 64.46 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30196 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 25.2 MiB 0.94 2118 750 9385 2715 5945 725 64.5 MiB 0.05 0.00 4.52145 3.49353 -105.466 -3.49353 3.49353 0.24 0.000265033 0.000242603 0.0146375 0.0133717 -1 -1 -1 -1 32 1967 23 6.87369e+06 293451 586450. 2029.24 0.35 0.0505078 0.0444585 25474 144626 -1 1595 20 1184 2094 130220 31374 2.83596 2.83596 -104.337 -2.83596 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0123439 0.0109405 99 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_065.v common 4.46 vpr 64.53 MiB -1 -1 0.16 17676 1 0.03 -1 -1 29828 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 30 32 278 235 1 151 96 17 17 289 -1 unnamed_device 25.4 MiB 1.69 2241 719 10608 2312 6839 1457 64.5 MiB 0.07 0.00 4.84748 3.98828 -113.215 -3.98828 3.98828 0.25 0.000391645 0.000367026 0.0289935 0.0271019 -1 -1 -1 -1 28 2331 36 6.87369e+06 475111 531479. 1839.03 1.39 0.12692 0.111488 24610 126494 -1 1678 21 1245 2215 142434 39295 3.33286 3.33286 -116.77 -3.33286 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0160478 0.0141015 109 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_066.v common 4.89 vpr 65.07 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29768 -1 -1 26 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66632 29 32 355 287 1 200 87 17 17 289 -1 unnamed_device 25.2 MiB 2.10 2696 974 15831 5641 7207 2983 65.1 MiB 0.09 0.00 5.17922 4.15337 -121.297 -4.15337 4.15337 0.24 0.000328376 0.000300502 0.0322937 0.0296945 -1 -1 -1 -1 34 2718 23 6.87369e+06 363320 618332. 2139.56 1.42 0.164397 0.143584 25762 151098 -1 2026 21 1484 2291 146376 37672 3.47616 3.47616 -116.825 -3.47616 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0161593 0.0144132 136 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_067.v common 3.68 vpr 64.94 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29776 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66496 32 32 358 289 1 183 90 17 17 289 -1 unnamed_device 25.0 MiB 1.76 2016 1105 14160 4101 8351 1708 64.9 MiB 0.08 0.00 5.27855 4.41935 -143.334 -4.41935 4.41935 0.24 0.000346002 0.000316456 0.0278664 0.0255617 -1 -1 -1 -1 32 2363 23 6.87369e+06 363320 586450. 2029.24 0.46 0.08495 0.0752392 25474 144626 -1 2046 21 1489 2340 158892 36945 3.6681 3.6681 -134.244 -3.6681 0 0 744469. 2576.02 0.03 0.05 0.16 -1 -1 0.03 0.016676 0.0148494 132 54 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_068.v common 3.76 vpr 65.11 MiB -1 -1 0.16 18056 1 0.03 -1 -1 30160 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66676 32 32 353 285 1 188 93 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2553 1054 11433 3167 7604 662 65.1 MiB 0.07 0.00 5.94852 4.77748 -139.018 -4.77748 4.77748 0.24 0.000334015 0.000305667 0.0198564 0.0181388 -1 -1 -1 -1 32 2558 25 6.87369e+06 405241 586450. 2029.24 0.40 0.0648189 0.0572644 25474 144626 -1 2013 22 1396 2524 151194 37389 3.71836 3.71836 -131.742 -3.71836 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.02815 0.0249344 134 51 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_069.v common 4.73 vpr 64.56 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30160 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66112 32 32 276 237 1 165 82 17 17 289 -1 unnamed_device 24.9 MiB 2.17 1940 852 6668 1493 4863 312 64.6 MiB 0.04 0.00 5.16415 4.88031 -136.568 -4.88031 4.88031 0.33 0.000282263 0.00025852 0.0119638 0.0109757 -1 -1 -1 -1 26 2532 37 6.87369e+06 251529 503264. 1741.40 1.14 0.0984009 0.0854727 24322 120374 -1 1898 19 1074 1463 105865 29212 3.47621 3.47621 -124.999 -3.47621 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.0128064 0.0114271 102 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_070.v common 4.05 vpr 64.92 MiB -1 -1 0.18 18048 1 0.03 -1 -1 30180 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66480 31 32 319 272 1 176 83 17 17 289 -1 unnamed_device 25.2 MiB 2.04 2174 1028 12503 3213 7830 1460 64.9 MiB 0.07 0.00 4.4732 3.7214 -122.26 -3.7214 3.7214 0.25 0.00040486 0.000356531 0.029162 0.0270087 -1 -1 -1 -1 32 2289 30 6.87369e+06 279477 586450. 2029.24 0.38 0.0734498 0.0653217 25474 144626 -1 1934 22 1164 1724 125099 29725 3.28891 3.28891 -122.449 -3.28891 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0151763 0.0134859 110 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_071.v common 4.41 vpr 64.98 MiB -1 -1 0.18 18436 1 0.03 -1 -1 30304 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66544 30 32 329 273 1 167 96 17 17 289 -1 unnamed_device 25.2 MiB 1.97 2361 965 13236 3751 8252 1233 65.0 MiB 0.07 0.00 4.47245 3.48795 -100.051 -3.48795 3.48795 0.25 0.00036336 0.000336979 0.0214233 0.0195433 -1 -1 -1 -1 30 1999 23 6.87369e+06 475111 556674. 1926.21 1.02 0.112542 0.0980759 25186 138497 -1 1729 16 946 1790 90841 23393 2.93826 2.93826 -100.371 -2.93826 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.0155344 0.0138624 124 57 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_072.v common 3.05 vpr 64.84 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29812 -1 -1 35 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66396 28 32 277 229 1 156 95 17 17 289 -1 unnamed_device 25.2 MiB 1.29 1945 924 16079 4874 9529 1676 64.8 MiB 0.07 0.00 5.23859 4.10437 -105.39 -4.10437 4.10437 0.25 0.000282598 0.000259458 0.0221159 0.02018 -1 -1 -1 -1 26 2118 21 6.87369e+06 489084 503264. 1741.40 0.47 0.0647093 0.0572097 24322 120374 -1 1838 21 1280 2507 173302 41037 3.6161 3.6161 -108.097 -3.6161 0 0 618332. 2139.56 0.03 0.05 0.06 -1 -1 0.03 0.0148899 0.0133326 117 27 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 5.59 vpr 64.57 MiB -1 -1 0.18 18060 1 0.03 -1 -1 29836 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 30 32 317 269 1 155 80 17 17 289 -1 unnamed_device 24.9 MiB 2.37 2041 784 11088 4549 5689 850 64.6 MiB 0.09 0.00 4.60788 3.85608 -116.241 -3.85608 3.85608 0.26 0.000373926 0.000343506 0.0399959 0.0370619 -1 -1 -1 -1 28 2449 50 6.87369e+06 251529 531479. 1839.03 1.69 0.171036 0.150399 24610 126494 -1 1896 24 1646 2865 221151 58757 3.15776 3.15776 -117.819 -3.15776 0 0 648988. 2245.63 0.02 0.06 0.09 -1 -1 0.02 0.015881 0.0140268 105 63 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 4.14 vpr 65.02 MiB -1 -1 0.15 17916 1 0.03 -1 -1 29628 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 32 32 335 282 1 189 84 17 17 289 -1 unnamed_device 25.6 MiB 1.66 2218 967 9966 2748 6633 585 65.0 MiB 0.06 0.00 5.10429 3.99449 -129.503 -3.99449 3.99449 0.25 0.000328462 0.000301649 0.020079 0.0184308 -1 -1 -1 -1 32 2511 25 6.87369e+06 279477 586450. 2029.24 1.09 0.117666 0.102422 25474 144626 -1 2008 18 1211 1757 119685 28936 3.4488 3.4488 -126.894 -3.4488 0 0 744469. 2576.02 0.04 0.06 0.08 -1 -1 0.04 0.023357 0.0207862 118 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_075.v common 3.32 vpr 64.91 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29900 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66468 31 32 293 230 1 175 96 17 17 289 -1 unnamed_device 24.9 MiB 0.79 2036 1158 10170 2450 6680 1040 64.9 MiB 0.06 0.00 5.31102 4.59912 -134.752 -4.59912 4.59912 0.27 0.000342506 0.000316632 0.0162185 0.0148702 -1 -1 -1 -1 32 2499 23 6.87369e+06 461137 586450. 2029.24 1.11 0.129327 0.112575 25474 144626 -1 2100 22 1224 2150 133245 32520 3.6524 3.6524 -124.426 -3.6524 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0168294 0.014975 130 4 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_076.v common 4.44 vpr 65.12 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29968 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 25.2 MiB 2.45 2819 1040 12178 3350 7228 1600 65.1 MiB 0.09 0.00 5.70484 4.82048 -149.342 -4.82048 4.82048 0.26 0.000400944 0.000372604 0.0283893 0.026235 -1 -1 -1 -1 32 3002 29 6.87369e+06 335372 586450. 2029.24 0.60 0.0908346 0.081116 25474 144626 -1 2195 18 1476 2286 156593 38820 3.90405 3.90405 -139.251 -3.90405 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0148102 0.0132845 141 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 5.94 vpr 65.12 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30176 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 32 32 385 308 1 195 101 17 17 289 -1 unnamed_device 25.6 MiB 3.09 2653 1152 16316 4343 10844 1129 65.1 MiB 0.08 0.00 6.91417 5.25048 -151.042 -5.25048 5.25048 0.24 0.000352849 0.000323511 0.0264732 0.0241542 -1 -1 -1 -1 28 2872 20 6.87369e+06 517032 531479. 1839.03 1.50 0.125407 0.110692 24610 126494 -1 2428 23 1830 3262 241216 56854 3.93035 3.93035 -146.382 -3.93035 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0181598 0.0161266 147 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_078.v common 5.07 vpr 65.23 MiB -1 -1 0.18 18048 1 0.03 -1 -1 30240 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66796 32 32 387 309 1 192 105 17 17 289 -1 unnamed_device 25.2 MiB 2.38 2943 1241 19618 5694 11739 2185 65.2 MiB 0.24 0.00 5.98952 4.52582 -145.898 -4.52582 4.52582 0.24 0.000822808 0.000763121 0.0762442 0.0705218 -1 -1 -1 -1 30 2850 25 6.87369e+06 572927 556674. 1926.21 1.09 0.176382 0.157475 25186 138497 -1 2346 21 1345 2673 179539 40524 3.5128 3.5128 -133.556 -3.5128 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0169879 0.0151336 148 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_079.v common 3.71 vpr 64.45 MiB -1 -1 0.12 17672 1 0.03 -1 -1 29504 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 30 32 272 232 1 151 80 17 17 289 -1 unnamed_device 24.7 MiB 1.97 2072 788 12808 4627 5785 2396 64.4 MiB 0.06 0.00 4.73318 3.87398 -115.445 -3.87398 3.87398 0.24 0.000270734 0.000246942 0.0216325 0.0197871 -1 -1 -1 -1 32 2109 26 6.87369e+06 251529 586450. 2029.24 0.39 0.0619366 0.0547203 25474 144626 -1 1731 21 1247 2177 152375 36953 2.94096 2.94096 -109.117 -2.94096 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.013509 0.0119628 99 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_080.v common 5.31 vpr 64.71 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30528 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 30 32 375 299 1 188 85 17 17 289 -1 unnamed_device 25.4 MiB 2.75 2081 1069 9943 2328 6646 969 64.7 MiB 0.07 0.00 5.31292 4.64076 -144.318 -4.64076 4.64076 0.24 0.000345453 0.000316854 0.0247669 0.0228435 -1 -1 -1 -1 26 2497 31 6.87369e+06 321398 503264. 1741.40 1.21 0.124009 0.109075 24322 120374 -1 2213 21 1786 2855 199315 47103 3.8714 3.8714 -142.891 -3.8714 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0221423 0.0198078 137 63 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_081.v common 4.20 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29864 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 25.7 MiB 1.66 2664 1115 14741 4886 7454 2401 65.1 MiB 0.09 0.00 5.92334 5.22106 -152.202 -5.22106 5.22106 0.25 0.000334817 0.000306968 0.0281764 0.0259055 -1 -1 -1 -1 30 2721 24 6.87369e+06 349346 556674. 1926.21 1.15 0.126827 0.11113 25186 138497 -1 2014 20 1447 2533 138886 35336 3.89246 3.89246 -136.446 -3.89246 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0169656 0.0152085 136 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_082.v common 4.71 vpr 65.10 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30172 -1 -1 30 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 31 32 340 275 1 201 93 17 17 289 -1 unnamed_device 25.2 MiB 2.09 2886 1189 10173 2898 6614 661 65.1 MiB 0.06 0.00 6.73744 5.23384 -148.634 -5.23384 5.23384 0.24 0.000333069 0.000305994 0.0175158 0.0160644 -1 -1 -1 -1 26 2895 35 6.87369e+06 419215 503264. 1741.40 1.31 0.132751 0.11687 24322 120374 -1 2483 26 1948 3189 213646 52192 4.5628 4.5628 -152.603 -4.5628 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0183985 0.0163074 139 47 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_083.v common 4.67 vpr 64.75 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30524 -1 -1 31 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 30 32 377 310 1 181 93 17 17 289 -1 unnamed_device 25.3 MiB 2.60 2449 1224 16893 5635 9042 2216 64.7 MiB 0.12 0.00 5.39266 4.94818 -149.82 -4.94818 4.94818 0.25 0.000344756 0.000315816 0.0388335 0.0359078 -1 -1 -1 -1 28 2735 20 6.87369e+06 433189 531479. 1839.03 0.59 0.0915719 0.0819831 24610 126494 -1 2284 25 1446 2485 237805 83948 3.50651 3.50651 -131.776 -3.50651 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0187101 0.0165963 136 83 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 4.69 vpr 64.62 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30168 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 32 32 365 294 1 187 86 17 17 289 -1 unnamed_device 24.9 MiB 2.10 2716 990 11993 3472 6935 1586 64.6 MiB 0.08 0.00 5.90348 4.77578 -139.992 -4.77578 4.77578 0.24 0.000817076 0.000762471 0.0254697 0.0234016 -1 -1 -1 -1 32 2722 28 6.87369e+06 307425 586450. 2029.24 1.25 0.143023 0.125248 25474 144626 -1 2150 18 1396 2412 167928 39620 4.02096 4.02096 -141.443 -4.02096 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0148475 0.0133072 131 57 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_085.v common 4.17 vpr 64.65 MiB -1 -1 0.20 18056 1 0.03 -1 -1 30008 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 29 32 378 310 1 179 90 17 17 289 -1 unnamed_device 25.2 MiB 1.85 2351 942 10944 2964 7013 967 64.7 MiB 0.08 0.00 5.07613 4.09163 -121.097 -4.09163 4.09163 0.24 0.000344576 0.000316288 0.0268546 0.0247877 -1 -1 -1 -1 30 2041 24 6.87369e+06 405241 556674. 1926.21 0.83 0.118594 0.104208 25186 138497 -1 1616 20 1131 1865 97938 24518 2.87521 2.87521 -106.946 -2.87521 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0165374 0.0147987 132 85 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 3.34 vpr 64.44 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29956 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 24.9 MiB 0.87 1905 855 8448 2270 5828 350 64.4 MiB 0.07 0.00 4.48878 3.94428 -118.381 -3.94428 3.94428 0.35 0.000389992 0.000357049 0.0201422 0.0184089 -1 -1 -1 -1 30 1821 20 6.87369e+06 251529 556674. 1926.21 1.08 0.110404 0.0961912 25186 138497 -1 1536 18 722 1020 59686 14633 2.76086 2.76086 -104.224 -2.76086 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0114509 0.0102269 96 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_087.v common 5.58 vpr 64.67 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29576 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 32 32 373 302 1 184 98 17 17 289 -1 unnamed_device 25.2 MiB 3.81 2454 1140 11348 2927 7443 978 64.7 MiB 0.06 0.00 5.90822 4.62608 -141.402 -4.62608 4.62608 0.24 0.000359269 0.000329782 0.0201378 0.0184997 -1 -1 -1 -1 32 2643 23 6.87369e+06 475111 586450. 2029.24 0.39 0.0672069 0.0596834 25474 144626 -1 2128 20 1410 2389 151377 37388 3.7954 3.7954 -133.896 -3.7954 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0158466 0.0141663 138 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_088.v common 5.61 vpr 65.12 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30108 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66684 32 32 397 314 1 197 86 17 17 289 -1 unnamed_device 25.2 MiB 3.49 2187 1055 13694 4095 7104 2495 65.1 MiB 0.10 0.00 5.30372 4.6886 -155.532 -4.6886 4.6886 0.25 0.000362587 0.000331007 0.0357278 0.0329807 -1 -1 -1 -1 32 2864 30 6.87369e+06 307425 586450. 2029.24 0.68 0.12507 0.112141 25474 144626 -1 2190 22 1874 3084 201524 49363 3.9064 3.9064 -149.446 -3.9064 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0279863 0.0250155 142 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_089.v common 4.77 vpr 64.04 MiB -1 -1 0.18 17912 1 0.03 -1 -1 30160 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65576 32 32 269 231 1 170 81 17 17 289 -1 unnamed_device 24.9 MiB 2.01 2026 911 13031 5411 7150 470 64.0 MiB 0.06 0.00 4.68123 4.08363 -117.144 -4.08363 4.08363 0.25 0.000275146 0.000251503 0.021986 0.0201273 -1 -1 -1 -1 32 2111 22 6.87369e+06 237555 586450. 2029.24 1.33 0.11397 0.0992625 25474 144626 -1 1780 20 1174 1591 109623 27308 2.93201 2.93201 -108.593 -2.93201 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0129851 0.0115452 102 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_090.v common 3.15 vpr 64.46 MiB -1 -1 0.12 17676 1 0.02 -1 -1 30324 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 31 32 245 205 1 153 85 17 17 289 -1 unnamed_device 25.2 MiB 0.92 2028 920 14407 4467 8027 1913 64.5 MiB 0.09 0.00 4.79248 4.04068 -118.574 -4.04068 4.04068 0.26 0.000267498 0.000244558 0.0312119 0.0289087 -1 -1 -1 -1 28 2103 24 6.87369e+06 307425 531479. 1839.03 0.89 0.116531 0.102508 24610 126494 -1 1895 20 1292 2098 141548 34713 3.03526 3.03526 -115.93 -3.03526 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.012172 0.0107774 100 4 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_091.v common 4.52 vpr 65.07 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30384 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 25.2 MiB 2.04 2676 1170 8083 1952 5562 569 65.1 MiB 0.06 0.00 5.61368 4.75448 -152.304 -4.75448 4.75448 0.24 0.000340485 0.000312452 0.0175897 0.0162244 -1 -1 -1 -1 28 3115 23 6.87369e+06 335372 531479. 1839.03 1.17 0.121612 0.106252 24610 126494 -1 2580 22 2029 2754 244375 55049 4.10006 4.10006 -153.878 -4.10006 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0170113 0.0151164 141 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_092.v common 4.74 vpr 64.53 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29860 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 356 289 1 201 92 17 17 289 -1 unnamed_device 25.2 MiB 2.09 2208 1201 15203 4959 7948 2296 64.5 MiB 0.09 0.00 6.10904 5.2802 -157.375 -5.2802 5.2802 0.26 0.000329459 0.000300811 0.0303446 0.0279453 -1 -1 -1 -1 32 2749 23 6.87369e+06 391268 586450. 2029.24 1.11 0.143611 0.125949 25474 144626 -1 2240 21 1434 2171 140842 33587 4.39535 4.39535 -145.45 -4.39535 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0163683 0.0146225 137 56 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_093.v common 3.58 vpr 65.16 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30184 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66724 32 32 349 260 1 204 101 17 17 289 -1 unnamed_device 25.1 MiB 0.59 2787 1264 13966 4175 8662 1129 65.2 MiB 0.09 0.00 6.34944 5.29707 -150.39 -5.29707 5.29707 0.25 0.000641819 0.000586368 0.0256625 0.023543 -1 -1 -1 -1 26 3191 27 6.87369e+06 517032 503264. 1741.40 1.55 0.15078 0.133588 24322 120374 -1 2699 24 1873 3447 292705 65551 4.85515 4.85515 -153.959 -4.85515 0 0 618332. 2139.56 0.02 0.07 0.06 -1 -1 0.02 0.018655 0.0166398 158 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_094.v common 4.68 vpr 64.82 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29784 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 30 32 316 264 1 165 96 17 17 289 -1 unnamed_device 25.2 MiB 1.81 2174 784 9732 2367 5855 1510 64.8 MiB 0.06 0.00 4.46215 3.60295 -103.566 -3.60295 3.60295 0.24 0.000311867 0.000285473 0.019448 0.0179445 -1 -1 -1 -1 28 2361 29 6.87369e+06 475111 531479. 1839.03 1.46 0.120329 0.105955 24610 126494 -1 1792 22 1436 2513 178226 45465 3.17456 3.17456 -108.253 -3.17456 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0176424 0.0156828 119 52 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_095.v common 3.21 vpr 64.41 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30544 -1 -1 23 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65956 27 32 255 219 1 139 82 17 17 289 -1 unnamed_device 25.2 MiB 0.82 1612 787 10050 2715 6635 700 64.4 MiB 0.12 0.00 4.33505 3.47585 -98.4683 -3.47585 3.47585 0.24 0.000838006 0.000776448 0.0486502 0.0453067 -1 -1 -1 -1 32 1635 26 6.87369e+06 321398 586450. 2029.24 1.00 0.129214 0.114695 25474 144626 -1 1333 20 839 1234 78424 18728 2.61836 2.61836 -92.7343 -2.61836 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0122542 0.0108438 97 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_096.v common 6.04 vpr 64.92 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30156 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 32 32 421 327 1 233 90 17 17 289 -1 unnamed_device 25.2 MiB 2.48 2919 1374 16371 4730 9445 2196 64.9 MiB 0.15 0.00 5.11591 4.4536 -142.768 -4.4536 4.4536 0.25 0.000385467 0.000353596 0.0502962 0.0461038 -1 -1 -1 -1 28 3929 41 6.87369e+06 363320 531479. 1839.03 2.06 0.199677 0.176685 24610 126494 -1 3169 20 2039 3316 292745 68186 4.14656 4.14656 -145.254 -4.14656 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0200713 0.0178199 162 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_097.v common 7.52 vpr 63.80 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29888 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65336 31 32 365 296 1 202 86 17 17 289 -1 unnamed_device 24.5 MiB 4.65 2567 1117 15395 4375 9100 1920 63.8 MiB 0.14 0.00 6.54132 5.50252 -165.378 -5.50252 5.50252 0.35 0.00094304 0.000877411 0.0550549 0.0509965 -1 -1 -1 -1 32 2527 22 6.87369e+06 321398 586450. 2029.24 1.17 0.172222 0.152753 25474 144626 -1 2171 20 1502 2393 131573 34068 4.315 4.315 -149.599 -4.315 0 0 744469. 2576.02 0.03 0.05 0.16 -1 -1 0.03 0.0215759 0.0193293 137 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_098.v common 6.32 vpr 64.46 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29900 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 331 280 1 185 84 17 17 289 -1 unnamed_device 24.9 MiB 3.54 2356 848 11247 3613 5403 2231 64.5 MiB 0.06 0.00 6.05365 4.34735 -140.957 -4.34735 4.34735 0.25 0.000314113 0.000285916 0.0209042 0.0191109 -1 -1 -1 -1 36 2307 30 6.87369e+06 279477 648988. 2245.63 1.38 0.125955 0.109635 26050 158493 -1 1710 21 1244 1786 130702 34809 3.71381 3.71381 -135.737 -3.71381 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0151241 0.0134502 115 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_099.v common 3.64 vpr 64.93 MiB -1 -1 0.13 18300 1 0.03 -1 -1 29928 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 326 263 1 176 97 17 17 289 -1 unnamed_device 25.2 MiB 1.05 2500 991 17191 5469 8763 2959 64.9 MiB 0.09 0.00 6.23855 4.94131 -133.771 -4.94131 4.94131 0.25 0.000319217 0.000287453 0.0282491 0.0257815 -1 -1 -1 -1 32 2541 23 6.87369e+06 461137 586450. 2029.24 1.16 0.135339 0.118369 25474 144626 -1 1967 20 1134 1814 128657 30637 3.5348 3.5348 -122.778 -3.5348 0 0 744469. 2576.02 0.03 0.04 0.11 -1 -1 0.03 0.0146995 0.0130737 129 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_100.v common 4.05 vpr 65.20 MiB -1 -1 0.19 18444 1 0.03 -1 -1 29872 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66764 31 32 373 294 1 197 97 17 17 289 -1 unnamed_device 25.2 MiB 1.63 2375 1162 12529 3039 8249 1241 65.2 MiB 0.07 0.00 5.24822 4.52085 -131.628 -4.52085 4.52085 0.24 0.000358061 0.000328139 0.0216078 0.0197952 -1 -1 -1 -1 32 2575 27 6.87369e+06 475111 586450. 2029.24 0.97 0.118535 0.103282 25474 144626 -1 2191 21 1428 2414 145484 35797 3.60116 3.60116 -127.313 -3.60116 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.016991 0.0151674 149 50 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_101.v common 3.92 vpr 64.44 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29836 -1 -1 31 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 30 32 325 268 1 172 93 17 17 289 -1 unnamed_device 24.8 MiB 2.07 2526 942 15843 4746 8425 2672 64.4 MiB 0.09 0.00 4.42088 3.6935 -105.372 -3.6935 3.6935 0.24 0.000305767 0.000279253 0.0263327 0.0240824 -1 -1 -1 -1 32 2304 24 6.87369e+06 433189 586450. 2029.24 0.37 0.0677758 0.060063 25474 144626 -1 1855 23 1310 2247 143307 35215 3.26111 3.26111 -104.441 -3.26111 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0191546 0.0170659 124 51 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_102.v common 5.92 vpr 65.10 MiB -1 -1 0.11 18440 1 0.03 -1 -1 29800 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 25.2 MiB 2.99 2913 1092 15883 6638 8299 946 65.1 MiB 0.09 0.00 5.80498 4.83838 -151.498 -4.83838 4.83838 0.24 0.00033385 0.00030469 0.0295813 0.0270307 -1 -1 -1 -1 36 3177 26 6.87369e+06 335372 648988. 2245.63 1.54 0.148107 0.129932 26050 158493 -1 2412 24 2420 3761 269815 66337 4.18536 4.18536 -142.06 -4.18536 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0188696 0.0167907 143 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_103.v common 4.43 vpr 65.22 MiB -1 -1 0.20 18056 1 0.03 -1 -1 29788 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 32 32 386 307 1 196 100 17 17 289 -1 unnamed_device 25.2 MiB 2.49 2629 1181 18660 5371 11070 2219 65.2 MiB 0.11 0.00 5.00583 4.14663 -139.408 -4.14663 4.14663 0.26 0.000357344 0.000326842 0.0340144 0.0312299 -1 -1 -1 -1 28 2725 24 6.87369e+06 503058 531479. 1839.03 0.46 0.0869383 0.0774914 24610 126494 -1 2433 22 1625 2600 177794 43230 3.30791 3.30791 -131.404 -3.30791 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0177087 0.0157872 148 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 3.83 vpr 64.40 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29796 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 29 32 269 229 1 150 80 17 17 289 -1 unnamed_device 24.9 MiB 1.50 1800 855 13152 3903 8012 1237 64.4 MiB 0.06 0.00 4.51078 3.96392 -119.802 -3.96392 3.96392 0.26 0.000278562 0.000250763 0.0228269 0.0208948 -1 -1 -1 -1 28 1573 21 6.87369e+06 265503 531479. 1839.03 0.84 0.102535 0.089372 24610 126494 -1 1449 18 1081 1538 90664 22450 2.84596 2.84596 -105.452 -2.84596 0 0 648988. 2245.63 0.04 0.05 0.12 -1 -1 0.04 0.0194379 0.0172703 101 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 3.61 vpr 64.89 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29720 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66452 32 32 310 266 1 175 84 17 17 289 -1 unnamed_device 24.9 MiB 1.23 1945 989 10881 3547 5830 1504 64.9 MiB 0.06 0.00 4.46846 3.96726 -124.286 -3.96726 3.96726 0.26 0.000539246 0.000491191 0.0218895 0.020114 -1 -1 -1 -1 32 2199 21 6.87369e+06 279477 586450. 2029.24 1.07 0.120443 0.104867 25474 144626 -1 1917 19 1282 1770 134180 30773 3.22347 3.22347 -121.937 -3.22347 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0136307 0.0121427 109 58 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 3.23 vpr 64.45 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30288 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 24.8 MiB 1.16 2369 985 12716 3543 8146 1027 64.4 MiB 0.07 0.00 5.82022 4.63448 -129.081 -4.63448 4.63448 0.25 0.000313758 0.00028752 0.0185202 0.0168858 -1 -1 -1 -1 26 2817 33 6.87369e+06 544980 503264. 1741.40 0.75 0.0722394 0.063921 24322 120374 -1 2199 25 1679 3103 232332 55175 4.5252 4.5252 -139.616 -4.5252 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0171975 0.0152355 135 33 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 3.73 vpr 64.02 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30200 -1 -1 22 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65560 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 24.9 MiB 1.93 2013 868 12143 3086 7739 1318 64.0 MiB 0.07 0.00 5.50062 4.39082 -119.863 -4.39082 4.39082 0.26 0.000638417 0.000596436 0.0244094 0.0224743 -1 -1 -1 -1 26 2317 25 6.87369e+06 307425 503264. 1741.40 0.40 0.0704772 0.0627406 24322 120374 -1 1903 21 1304 1681 120177 29907 3.4928 3.4928 -115.033 -3.4928 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.0130638 0.0115815 104 31 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_108.v common 4.93 vpr 64.00 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30192 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65532 32 32 278 238 1 158 80 17 17 289 -1 unnamed_device 24.9 MiB 2.65 2071 908 11604 3546 6151 1907 64.0 MiB 0.06 0.00 4.62988 3.89598 -123.598 -3.89598 3.89598 0.24 0.00027488 0.00025107 0.0199843 0.0182973 -1 -1 -1 -1 32 2061 26 6.87369e+06 223581 586450. 2029.24 0.99 0.101454 0.0882131 25474 144626 -1 1820 19 1201 2020 146655 33744 2.79301 2.79301 -110.871 -2.79301 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0126783 0.0112607 101 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 4.03 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29784 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 31 32 373 300 1 185 100 17 17 289 -1 unnamed_device 25.2 MiB 2.20 2655 991 12396 3296 8295 805 65.0 MiB 0.12 0.00 4.74418 3.88072 -123.81 -3.88072 3.88072 0.24 0.00100784 0.000938791 0.0351059 0.0323701 -1 -1 -1 -1 30 2157 23 6.87369e+06 517032 556674. 1926.21 0.44 0.0812104 0.0724896 25186 138497 -1 1772 22 1406 2370 128493 31312 2.87096 2.87096 -113.357 -2.87096 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.0170484 0.0151613 141 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 4.53 vpr 64.52 MiB -1 -1 0.11 17676 1 0.03 -1 -1 30204 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 31 32 265 230 1 169 82 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2006 938 8270 2331 5442 497 64.5 MiB 0.04 0.00 4.2629 3.6763 -117.183 -3.6763 3.6763 0.25 0.00027393 0.000251177 0.0138467 0.0127085 -1 -1 -1 -1 26 2515 27 6.87369e+06 265503 503264. 1741.40 1.38 0.113204 0.0989182 24322 120374 -1 2077 22 1426 2063 144088 35253 3.24491 3.24491 -120.554 -3.24491 0 0 618332. 2139.56 0.02 0.05 0.07 -1 -1 0.02 0.017819 0.0156637 100 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 4.78 vpr 65.08 MiB -1 -1 0.16 18440 1 0.03 -1 -1 29780 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66640 32 32 349 286 1 177 96 17 17 289 -1 unnamed_device 25.0 MiB 2.22 2443 1058 16740 5363 9029 2348 65.1 MiB 0.09 0.00 4.43988 3.7125 -116.005 -3.7125 3.7125 0.26 0.000330638 0.000302394 0.0297324 0.0273204 -1 -1 -1 -1 32 2537 48 6.87369e+06 447163 586450. 2029.24 1.13 0.162075 0.142002 25474 144626 -1 1979 19 985 1660 107053 25693 3.14681 3.14681 -112.185 -3.14681 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0153245 0.0136416 130 57 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_112.v common 4.16 vpr 64.70 MiB -1 -1 0.15 18060 1 0.03 -1 -1 29768 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 31 32 396 325 1 183 94 17 17 289 -1 unnamed_device 25.2 MiB 2.39 2295 980 16282 5415 8151 2716 64.7 MiB 0.09 0.00 4.1365 3.7606 -126.341 -3.7606 3.7606 0.24 0.000372826 0.000341745 0.0318259 0.0293245 -1 -1 -1 -1 32 2275 22 6.87369e+06 433189 586450. 2029.24 0.38 0.0785981 0.0701866 25474 144626 -1 1857 22 1574 2432 136184 34381 3.09951 3.09951 -122.264 -3.09951 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.017615 0.0156661 136 91 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 4.02 vpr 64.45 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29760 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 303 262 1 154 82 17 17 289 -1 unnamed_device 24.9 MiB 1.70 1892 948 13610 3927 7739 1944 64.5 MiB 0.06 0.00 4.21775 3.46595 -110.85 -3.46595 3.46595 0.25 0.000291981 0.000266784 0.023879 0.0218333 -1 -1 -1 -1 28 2163 25 6.87369e+06 251529 531479. 1839.03 0.99 0.110338 0.0961183 24610 126494 -1 1875 22 1244 1995 152174 36647 2.85796 2.85796 -109.463 -2.85796 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0145337 0.0128796 100 57 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 4.14 vpr 64.85 MiB -1 -1 0.15 18060 1 0.03 -1 -1 30164 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66408 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 24.9 MiB 1.43 2269 846 15023 5112 7105 2806 64.9 MiB 0.07 0.00 5.53062 4.43872 -133.042 -4.43872 4.43872 0.24 0.000284962 0.000260591 0.0256698 0.023447 -1 -1 -1 -1 34 2491 31 6.87369e+06 265503 618332. 2139.56 1.18 0.131504 0.114323 25762 151098 -1 1812 20 1302 1953 138182 35210 3.43421 3.43421 -119.565 -3.43421 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0182939 0.0160101 110 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 4.58 vpr 64.35 MiB -1 -1 0.11 18300 1 0.03 -1 -1 30164 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 318 257 1 196 86 17 17 289 -1 unnamed_device 25.2 MiB 1.82 2163 1060 11048 3713 5060 2275 64.3 MiB 0.06 0.00 5.70718 4.76478 -133.796 -4.76478 4.76478 0.24 0.000307552 0.000280889 0.0197149 0.0180596 -1 -1 -1 -1 30 2427 22 6.87369e+06 307425 556674. 1926.21 1.43 0.157271 0.137375 25186 138497 -1 2020 20 1254 1731 101663 25086 3.76346 3.76346 -131.36 -3.76346 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0152417 0.0136094 128 30 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 3.95 vpr 64.96 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29816 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 24.9 MiB 2.06 2255 990 10140 2558 6775 807 65.0 MiB 0.07 0.00 4.47163 4.11363 -115.607 -4.11363 4.11363 0.40 0.000313842 0.00028706 0.0212981 0.0195614 -1 -1 -1 -1 30 2125 26 6.87369e+06 405241 556674. 1926.21 0.38 0.0666518 0.0590345 25186 138497 -1 1706 22 856 1609 88635 21834 3.01151 3.01151 -103.493 -3.01151 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0154263 0.0137196 123 55 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 5.65 vpr 65.12 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29772 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 393 312 1 215 88 17 17 289 -1 unnamed_device 25.6 MiB 2.55 2550 1006 14713 4986 7296 2431 65.1 MiB 0.09 0.00 5.75531 5.22906 -161.966 -5.22906 5.22906 0.24 0.000362547 0.00033201 0.0299732 0.0274495 -1 -1 -1 -1 34 2714 38 6.87369e+06 335372 618332. 2139.56 1.66 0.174151 0.152107 25762 151098 -1 2202 24 1965 3055 205816 51673 4.28506 4.28506 -150.228 -4.28506 0 0 787024. 2723.27 0.03 0.06 0.08 -1 -1 0.03 0.0195635 0.0173908 148 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 3.35 vpr 64.40 MiB -1 -1 0.21 17676 1 0.02 -1 -1 30044 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 24.9 MiB 1.02 1779 625 4631 866 3215 550 64.4 MiB 0.02 0.00 4.01225 3.52895 -101.476 -3.52895 3.52895 0.26 0.000250149 0.000229138 0.00776917 0.00714495 -1 -1 -1 -1 30 1639 23 6.87369e+06 251529 556674. 1926.21 0.93 0.0804275 0.069412 25186 138497 -1 1219 21 737 1159 53687 15362 3.04656 3.04656 -101.409 -3.04656 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0147543 0.0131178 93 4 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 5.06 vpr 65.28 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30124 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66848 32 32 412 334 1 194 99 17 17 289 -1 unnamed_device 25.2 MiB 1.54 2354 1015 18111 5950 8835 3326 65.3 MiB 0.09 0.00 5.55115 4.44135 -143.231 -4.44135 4.44135 0.24 0.00037324 0.000341662 0.0311831 0.0284679 -1 -1 -1 -1 36 2533 50 6.87369e+06 489084 648988. 2245.63 2.14 0.218208 0.192077 26050 158493 -1 2040 21 1539 2249 177726 45330 3.99296 3.99296 -143.127 -3.99296 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0185306 0.0165275 145 90 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 5.27 vpr 64.52 MiB -1 -1 0.12 18300 1 0.03 -1 -1 30220 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 32 32 376 318 1 168 82 17 17 289 -1 unnamed_device 25.2 MiB 3.41 2123 865 10762 4115 4722 1925 64.5 MiB 0.07 0.00 4.47325 3.59615 -127.488 -3.59615 3.59615 0.25 0.000337104 0.000308034 0.0274738 0.0253226 -1 -1 -1 -1 32 2183 25 6.87369e+06 251529 586450. 2029.24 0.40 0.0761496 0.0673204 25474 144626 -1 1767 22 1484 2215 152133 36159 3.15446 3.15446 -127.944 -3.15446 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0171901 0.0152467 114 96 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 4.62 vpr 64.23 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29776 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 360 293 1 182 97 17 17 289 -1 unnamed_device 24.9 MiB 2.31 2242 1134 8533 1953 5707 873 64.2 MiB 0.09 0.00 4.26762 4.14663 -128.445 -4.14663 4.14663 0.30 0.000656918 0.000603764 0.0275667 0.025307 -1 -1 -1 -1 28 2384 22 6.87369e+06 461137 531479. 1839.03 0.80 0.104875 0.092177 24610 126494 -1 2150 21 1079 1675 108833 27521 3.38591 3.38591 -122.541 -3.38591 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0280771 0.0250376 134 60 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_122.v common 5.89 vpr 65.18 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29804 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66748 32 32 396 299 1 240 91 17 17 289 -1 unnamed_device 25.6 MiB 3.34 2861 1325 10699 2829 6710 1160 65.2 MiB 0.08 0.00 6.83115 5.96543 -180.924 -5.96543 5.96543 0.25 0.000377616 0.000346769 0.0221869 0.020377 -1 -1 -1 -1 30 3159 21 6.87369e+06 377294 556674. 1926.21 1.15 0.128384 0.113301 25186 138497 -1 2486 20 1783 2650 160621 38650 4.9295 4.9295 -162.971 -4.9295 0 0 706193. 2443.58 0.03 0.05 0.09 -1 -1 0.03 0.0179893 0.0161715 166 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_123.v common 3.42 vpr 64.37 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29608 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 30 32 224 207 1 137 79 17 17 289 -1 unnamed_device 25.2 MiB 1.16 1796 583 12754 5340 6497 917 64.4 MiB 0.05 0.00 3.69857 3.16961 -92.7187 -3.16961 3.16961 0.24 0.000234624 0.000214291 0.0192412 0.0176121 -1 -1 -1 -1 30 1782 28 6.87369e+06 237555 556674. 1926.21 1.00 0.0855611 0.0741408 25186 138497 -1 1269 16 770 993 68728 19715 2.63001 2.63001 -90.3813 -2.63001 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0115953 0.0103417 78 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_124.v common 2.65 vpr 64.55 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29832 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66104 30 32 286 239 1 151 83 17 17 289 -1 unnamed_device 24.9 MiB 0.84 1770 758 12863 4724 6383 1756 64.6 MiB 0.06 0.00 4.46678 3.90824 -117.819 -3.90824 3.90824 0.24 0.000282976 0.000258279 0.0218206 0.0199412 -1 -1 -1 -1 32 1677 18 6.87369e+06 293451 586450. 2029.24 0.39 0.0704146 0.0621642 25474 144626 -1 1359 23 1013 1508 94997 23267 2.89296 2.89296 -107.7 -2.89296 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0242749 0.0214518 106 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 2.82 vpr 64.59 MiB -1 -1 0.15 18056 1 0.02 -1 -1 30148 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 296 247 1 158 81 17 17 289 -1 unnamed_device 25.4 MiB 1.05 2174 940 13381 4853 6305 2223 64.6 MiB 0.07 0.00 4.05625 3.42975 -116.374 -3.42975 3.42975 0.24 0.000299088 0.000273989 0.024265 0.0222129 -1 -1 -1 -1 30 2272 22 6.87369e+06 237555 556674. 1926.21 0.41 0.0633576 0.0560039 25186 138497 -1 1909 22 1221 2293 143256 34040 2.85696 2.85696 -116.827 -2.85696 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0147316 0.0130541 106 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_126.v common 3.03 vpr 64.39 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29888 -1 -1 29 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 25 32 216 194 1 123 86 17 17 289 -1 unnamed_device 24.9 MiB 0.63 1478 521 12938 4434 5564 2940 64.4 MiB 0.05 0.00 4.10455 3.48943 -81.0717 -3.48943 3.48943 0.24 0.000223717 0.000203889 0.0164858 0.015004 -1 -1 -1 -1 30 1629 41 6.87369e+06 405241 556674. 1926.21 1.12 0.0952124 0.0819646 25186 138497 -1 1166 19 766 1360 77787 20476 2.73796 2.73796 -77.5522 -2.73796 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0101821 0.0089722 87 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_127.v common 3.81 vpr 65.07 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30176 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 32 32 376 307 1 192 86 17 17 289 -1 unnamed_device 25.2 MiB 1.93 2245 1110 15017 5165 7384 2468 65.1 MiB 0.09 0.00 5.02315 4.32635 -130.464 -4.32635 4.32635 0.25 0.000345488 0.000315825 0.0292868 0.026788 -1 -1 -1 -1 32 2752 22 6.87369e+06 307425 586450. 2029.24 0.39 0.0749442 0.0663177 25474 144626 -1 2132 20 1326 2357 146716 35875 3.49806 3.49806 -125.919 -3.49806 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0162152 0.0144597 131 72 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_128.v common 4.21 vpr 64.78 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29828 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 31 32 409 331 1 193 97 17 17 289 -1 unnamed_device 25.2 MiB 2.25 2417 956 9199 2038 6732 429 64.8 MiB 0.06 0.00 4.74423 4.19189 -134.468 -4.19189 4.19189 0.25 0.000365815 0.000335309 0.016995 0.0155775 -1 -1 -1 -1 32 2555 23 6.87369e+06 475111 586450. 2029.24 0.40 0.0696073 0.0613481 25474 144626 -1 1959 21 1593 2492 151905 37256 3.18561 3.18561 -123.559 -3.18561 0 0 744469. 2576.02 0.04 0.08 0.13 -1 -1 0.04 0.0315952 0.0282545 145 90 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_001.v common 4.16 vpr 64.96 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29412 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66516 32 32 354 285 1 223 90 17 17 289 -1 unnamed_device 24.9 MiB 1.36 2668 1268 14562 3744 8579 2239 65.0 MiB 0.09 0.00 6.46147 5.42478 -161.939 -5.42478 5.42478 0.27 0.000354138 0.000325872 0.0286551 0.0264431 -1 -1 -1 -1 28 3093 28 6.89349e+06 366440 531479. 1839.03 1.39 0.149217 0.131137 24610 126494 -1 2624 19 1777 2523 168314 41073 4.42749 4.42749 -154.329 -4.42749 0 0 648988. 2245.63 0.03 0.05 0.07 -1 -1 0.03 0.0180098 0.0159135 146 50 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_002.v common 3.13 vpr 64.73 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29756 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 30 32 363 293 1 229 89 17 17 289 -1 unnamed_device 25.0 MiB 1.18 2791 1263 14939 4998 7127 2814 64.7 MiB 0.08 0.00 6.19428 4.98048 -150.88 -4.98048 4.98048 0.25 0.000332168 0.000303056 0.0271095 0.0247833 -1 -1 -1 -1 32 3445 31 6.89349e+06 380534 586450. 2029.24 0.56 0.0865076 0.0767831 25474 144626 -1 2439 21 1808 2625 186782 45091 4.32429 4.32429 -146.227 -4.32429 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164687 0.014674 152 63 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_003.v common 3.92 vpr 63.83 MiB -1 -1 0.16 18060 1 0.03 -1 -1 29808 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65360 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 24.6 MiB 1.12 2478 1102 14965 5131 8043 1791 63.8 MiB 0.10 0.00 5.35819 4.28675 -123.145 -4.28675 4.28675 0.26 0.000327491 0.000280328 0.0326438 0.0301867 -1 -1 -1 -1 38 2116 21 6.89349e+06 295971 678818. 2348.85 1.23 0.129476 0.113859 26626 170182 -1 1908 22 1051 1471 95425 22642 3.6203 3.6203 -116.676 -3.6203 0 0 902133. 3121.57 0.05 0.05 0.14 -1 -1 0.05 0.0196229 0.0174739 119 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_004.v common 3.21 vpr 64.77 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29748 -1 -1 27 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 29 32 308 248 1 195 88 17 17 289 -1 unnamed_device 24.9 MiB 0.81 2689 1112 15493 4685 9183 1625 64.8 MiB 0.08 0.00 6.19768 4.85518 -132.85 -4.85518 4.85518 0.24 0.000305043 0.000279294 0.0254061 0.0232564 -1 -1 -1 -1 32 2525 37 6.89349e+06 380534 586450. 2029.24 1.02 0.125355 0.10906 25474 144626 -1 2095 21 1267 2022 127854 30529 3.81286 3.81286 -122.541 -3.81286 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145113 0.0128994 130 31 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_005.v common 3.38 vpr 64.86 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29824 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66416 32 32 336 268 1 211 89 17 17 289 -1 unnamed_device 24.8 MiB 1.44 2799 1150 14741 4806 7062 2873 64.9 MiB 0.09 0.00 6.91451 5.19194 -150.686 -5.19194 5.19194 0.24 0.000325479 0.000297988 0.0258125 0.023632 -1 -1 -1 -1 32 3393 21 6.89349e+06 352346 586450. 2029.24 0.46 0.0685243 0.0608933 25474 144626 -1 2453 20 1763 3114 214478 51266 4.54675 4.54675 -150.299 -4.54675 0 0 744469. 2576.02 0.04 0.08 0.11 -1 -1 0.04 0.0249649 0.022335 141 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_006.v common 3.78 vpr 64.55 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29780 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 32 32 366 295 1 231 99 17 17 289 -1 unnamed_device 25.2 MiB 1.70 2831 1275 17883 5747 9425 2711 64.6 MiB 0.12 0.00 4.85631 3.97606 -129.432 -3.97606 3.97606 0.26 0.000347219 0.000318231 0.0368098 0.0340006 -1 -1 -1 -1 32 3207 27 6.89349e+06 493284 586450. 2029.24 0.65 0.101339 0.0899346 25474 144626 -1 2564 21 1683 2745 172590 41903 3.49866 3.49866 -125.251 -3.49866 0 0 744469. 2576.02 0.03 0.06 0.09 -1 -1 0.03 0.0203705 0.0179603 156 58 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_007.v common 2.73 vpr 63.64 MiB -1 -1 0.17 17672 1 0.03 -1 -1 30152 -1 -1 22 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65168 27 32 259 221 1 159 81 17 17 289 -1 unnamed_device 24.1 MiB 0.88 1787 834 12681 4344 6184 2153 63.6 MiB 0.06 0.00 4.91933 4.22379 -114.63 -4.22379 4.22379 0.25 0.000258176 0.000236283 0.020121 0.018441 -1 -1 -1 -1 32 1839 34 6.89349e+06 310065 586450. 2029.24 0.42 0.0705179 0.0621317 25474 144626 -1 1480 21 1046 1586 115082 27270 3.11381 3.11381 -103.863 -3.11381 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.013738 0.0122335 104 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_008.v common 2.98 vpr 64.40 MiB -1 -1 0.16 17672 1 0.03 -1 -1 29836 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 31 32 271 219 1 164 96 17 17 289 -1 unnamed_device 24.8 MiB 0.58 2064 1021 15426 4233 9006 2187 64.4 MiB 0.08 0.00 4.0124 3.39815 -103.342 -3.39815 3.39815 0.25 0.000304464 0.000279784 0.0290524 0.0266819 -1 -1 -1 -1 32 2265 19 6.89349e+06 465097 586450. 2029.24 0.99 0.12256 0.107042 25474 144626 -1 1863 19 982 1779 108256 26071 2.49221 2.49221 -95.7819 -2.49221 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0130806 0.0116211 119 4 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_009.v common 3.56 vpr 64.82 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29764 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 31 32 317 271 1 207 86 17 17 289 -1 unnamed_device 24.9 MiB 1.03 2257 970 6512 1373 4783 356 64.8 MiB 0.04 0.00 4.58785 3.71075 -120.491 -3.71075 3.71075 0.26 0.000307831 0.000282316 0.0119944 0.0109864 -1 -1 -1 -1 30 2557 25 6.89349e+06 324158 556674. 1926.21 1.21 0.11422 0.0990295 25186 138497 -1 1893 22 1510 2075 128297 33350 3.17321 3.17321 -122.163 -3.17321 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0153599 0.013634 125 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_010.v common 3.21 vpr 64.44 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29780 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 32 32 298 248 1 185 83 17 17 289 -1 unnamed_device 24.9 MiB 1.12 1986 1014 8003 1763 5681 559 64.4 MiB 0.06 0.00 4.79638 4.06248 -133.531 -4.06248 4.06248 0.25 0.000293762 0.000269576 0.0208869 0.019182 -1 -1 -1 -1 30 2247 30 6.89349e+06 267783 556674. 1926.21 0.79 0.0985272 0.0859376 25186 138497 -1 1845 21 1118 1550 104372 24397 2.79711 2.79711 -117.654 -2.79711 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0142957 0.0127128 115 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_011.v common 3.56 vpr 64.48 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29804 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66024 30 32 303 262 1 191 84 17 17 289 -1 unnamed_device 25.2 MiB 1.11 2045 1034 13992 5226 7098 1668 64.5 MiB 0.07 0.00 5.30417 4.58817 -134.271 -4.58817 4.58817 0.25 0.000285823 0.000261664 0.0234962 0.0215034 -1 -1 -1 -1 32 2570 23 6.89349e+06 310065 586450. 2029.24 1.08 0.117321 0.102048 25474 144626 -1 1928 20 1166 1543 112527 25961 3.52775 3.52775 -121.933 -3.52775 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0137984 0.0122887 121 63 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_012.v common 2.79 vpr 64.41 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29740 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65956 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 24.9 MiB 1.00 2463 976 13432 3930 7414 2088 64.4 MiB 0.07 0.00 4.7073 3.6928 -114.983 -3.6928 3.6928 0.25 0.000275071 0.000252008 0.0223127 0.0204555 -1 -1 -1 -1 32 2213 22 6.89349e+06 253689 586450. 2029.24 0.39 0.0611593 0.0541867 25474 144626 -1 1780 22 1007 1381 100176 22972 2.74911 2.74911 -106.8 -2.74911 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0141439 0.0125142 103 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_013.v common 3.51 vpr 64.23 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29796 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65776 32 32 344 272 1 209 89 17 17 289 -1 unnamed_device 25.2 MiB 1.38 2413 1094 15335 5171 7707 2457 64.2 MiB 0.10 0.00 4.45968 4.21034 -134.417 -4.21034 4.21034 0.25 0.000329997 0.000301932 0.0308546 0.0282959 -1 -1 -1 -1 32 2902 28 6.89349e+06 352346 586450. 2029.24 0.75 0.12445 0.110508 25474 144626 -1 2293 23 1740 2630 196717 47360 3.47746 3.47746 -126.462 -3.47746 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0169096 0.0150531 140 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_014.v common 4.58 vpr 65.01 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29772 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66568 32 32 363 295 1 232 90 17 17 289 -1 unnamed_device 24.9 MiB 1.45 2789 1385 9939 2779 6391 769 65.0 MiB 0.06 0.00 6.97451 5.52182 -162.398 -5.52182 5.52182 0.25 0.000335248 0.000306745 0.0184652 0.016897 -1 -1 -1 -1 28 3357 31 6.89349e+06 366440 531479. 1839.03 1.79 0.124115 0.10906 24610 126494 -1 2785 22 1872 2537 229756 59541 4.40835 4.40835 -155.309 -4.40835 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0181619 0.0162326 151 61 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_015.v common 3.42 vpr 64.33 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30272 -1 -1 21 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 29 32 248 215 1 160 82 17 17 289 -1 unnamed_device 24.9 MiB 0.98 1849 777 10762 2615 7615 532 64.3 MiB 0.05 0.00 4.18032 3.23418 -96.7477 -3.23418 3.23418 0.24 0.000255908 0.00023477 0.0168335 0.0154381 -1 -1 -1 -1 30 1844 21 6.89349e+06 295971 556674. 1926.21 1.12 0.122352 0.106443 25186 138497 -1 1498 22 967 1375 83682 21630 2.89731 2.89731 -98.7482 -2.89731 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.014901 0.0131379 98 27 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_016.v common 5.13 vpr 65.03 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29760 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66592 32 32 370 297 1 234 91 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2606 1335 15187 5552 7119 2516 65.0 MiB 0.11 0.00 5.16764 4.22024 -136.349 -4.22024 4.22024 0.26 0.000412992 0.000382645 0.0361098 0.0332974 -1 -1 -1 -1 30 3279 35 6.89349e+06 380534 556674. 1926.21 1.79 0.162898 0.143544 25186 138497 -1 2450 20 1777 2835 162669 40771 3.68045 3.68045 -133.182 -3.68045 0 0 706193. 2443.58 0.04 0.07 0.11 -1 -1 0.04 0.02568 0.022915 156 58 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_017.v common 3.90 vpr 64.87 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30200 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66424 32 32 338 269 1 204 87 17 17 289 -1 unnamed_device 25.2 MiB 1.28 2621 1087 13911 3796 7786 2329 64.9 MiB 0.08 0.00 4.95288 4.09494 -130.17 -4.09494 4.09494 0.24 0.000327812 0.000300274 0.0254079 0.0232692 -1 -1 -1 -1 36 2373 21 6.89349e+06 324158 648988. 2245.63 1.25 0.13221 0.115644 26050 158493 -1 1986 20 1185 1718 122618 29684 3.19801 3.19801 -114.684 -3.19801 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0152461 0.013601 137 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 3.28 vpr 64.84 MiB -1 -1 0.12 17916 1 0.03 -1 -1 30116 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 323 276 1 215 89 17 17 289 -1 unnamed_device 24.8 MiB 1.33 2509 1207 11573 2908 7136 1529 64.8 MiB 0.07 0.00 4.33725 3.64971 -129.543 -3.64971 3.64971 0.25 0.000446323 0.000418476 0.0206661 0.0189407 -1 -1 -1 -1 30 2877 36 6.89349e+06 352346 556674. 1926.21 0.61 0.0867738 0.0767415 25186 138497 -1 2229 18 1150 1585 105826 24515 3.03215 3.03215 -122.568 -3.03215 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0147283 0.0131892 130 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_019.v common 2.68 vpr 64.25 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29816 -1 -1 16 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 30 32 222 206 1 141 78 17 17 289 -1 unnamed_device 25.2 MiB 0.61 1681 755 9872 2574 6614 684 64.2 MiB 0.04 0.00 3.29613 2.66963 -90.6547 -2.66963 2.66963 0.24 0.000244818 0.000217441 0.016279 0.0149582 -1 -1 -1 -1 28 1581 17 6.89349e+06 225501 531479. 1839.03 0.81 0.0691751 0.060157 24610 126494 -1 1395 17 749 863 62232 15664 2.11002 2.11002 -91.215 -2.11002 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00977148 0.00866811 79 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_020.v common 3.99 vpr 64.46 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30172 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 31 32 291 243 1 179 84 17 17 289 -1 unnamed_device 24.7 MiB 1.29 2232 990 14358 5433 7130 1795 64.5 MiB 0.07 0.00 5.72212 4.79672 -142.478 -4.79672 4.79672 0.24 0.00047536 0.000450156 0.0250063 0.0229537 -1 -1 -1 -1 28 2553 26 6.89349e+06 295971 531479. 1839.03 1.37 0.109881 0.0966787 24610 126494 -1 2028 19 1246 1876 131016 32194 3.77545 3.77545 -139.775 -3.77545 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0130579 0.0116135 115 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_021.v common 3.83 vpr 64.80 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29940 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66360 32 32 342 271 1 207 99 17 17 289 -1 unnamed_device 24.8 MiB 1.07 2415 1186 18795 6653 9829 2313 64.8 MiB 0.09 0.00 6.0155 4.63443 -148.243 -4.63443 4.63443 0.25 0.000331482 0.000297849 0.0288279 0.0263868 -1 -1 -1 -1 36 2535 22 6.89349e+06 493284 648988. 2245.63 1.37 0.133607 0.116992 26050 158493 -1 2136 21 1575 2368 182986 42853 4.01424 4.01424 -140.469 -4.01424 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0195265 0.0174675 150 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_022.v common 3.80 vpr 65.02 MiB -1 -1 0.13 18064 1 0.04 -1 -1 29728 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 372 300 1 229 89 17 17 289 -1 unnamed_device 25.2 MiB 1.07 2872 1408 14741 4188 8680 1873 65.0 MiB 0.09 0.00 5.95345 4.79088 -146.55 -4.79088 4.79088 0.24 0.000345743 0.000316106 0.0275037 0.0252196 -1 -1 -1 -1 30 3072 30 6.89349e+06 352346 556674. 1926.21 1.31 0.14375 0.125667 25186 138497 -1 2494 21 1700 2463 172223 38111 3.67269 3.67269 -133.602 -3.67269 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0167697 0.0149365 152 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_023.v common 2.82 vpr 64.13 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30148 -1 -1 19 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 26 32 190 182 1 126 77 17 17 289 -1 unnamed_device 25.2 MiB 0.59 1378 528 11324 4722 5741 861 64.1 MiB 0.04 0.00 2.92131 2.67071 -73.9405 -2.67071 2.67071 0.25 0.000200742 0.000182777 0.0149184 0.0136176 -1 -1 -1 -1 30 1223 26 6.89349e+06 267783 556674. 1926.21 0.88 0.0684971 0.0593734 25186 138497 -1 921 17 565 672 37400 10275 1.85675 1.85675 -65.726 -1.85675 0 0 706193. 2443.58 0.03 0.02 0.13 -1 -1 0.03 0.00849785 0.00758487 72 30 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_024.v common 2.50 vpr 64.45 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29756 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 285 227 1 169 88 17 17 289 -1 unnamed_device 24.9 MiB 0.80 2097 1093 14908 4191 8870 1847 64.4 MiB 0.07 0.00 5.19194 4.58773 -130.119 -4.58773 4.58773 0.24 0.000291779 0.000266841 0.0240118 0.0219813 -1 -1 -1 -1 32 2488 23 6.89349e+06 338252 586450. 2029.24 0.38 0.0638837 0.0566624 25474 144626 -1 2145 20 1144 2016 159814 37055 3.49805 3.49805 -121.157 -3.49805 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0137382 0.0122388 120 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_025.v common 2.49 vpr 64.04 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30104 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65576 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 25.2 MiB 0.50 1343 738 9516 2733 5641 1142 64.0 MiB 0.03 0.00 2.53969 2.22522 -77.1622 -2.22522 2.22522 0.24 0.000194566 0.000176679 0.0126767 0.0115566 -1 -1 -1 -1 26 1456 18 6.89349e+06 169126 503264. 1741.40 0.55 0.0594687 0.0515478 24322 120374 -1 1353 21 670 881 68720 16870 1.77811 1.77811 -79.1079 -1.77811 0 0 618332. 2139.56 0.02 0.03 0.13 -1 -1 0.02 0.00971171 0.00855551 64 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_026.v common 3.48 vpr 64.49 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29588 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 32 32 300 245 1 187 86 17 17 289 -1 unnamed_device 24.9 MiB 1.13 2120 1085 9536 2559 6078 899 64.5 MiB 0.05 0.00 5.62618 4.92048 -138.071 -4.92048 4.92048 0.25 0.00030219 0.000276959 0.0167141 0.015329 -1 -1 -1 -1 32 2428 20 6.89349e+06 310065 586450. 2029.24 1.01 0.131882 0.115016 25474 144626 -1 1966 16 1004 1478 88603 22258 3.7112 3.7112 -125.676 -3.7112 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.012272 0.0110367 121 24 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 3.11 vpr 64.46 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29936 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 24.6 MiB 0.69 2474 1043 16727 4808 9374 2545 64.5 MiB 0.08 0.00 4.41543 3.451 -108.699 -3.451 3.451 0.25 0.000307109 0.000276632 0.0248743 0.022735 -1 -1 -1 -1 32 2399 21 6.89349e+06 436909 586450. 2029.24 1.10 0.124692 0.108971 25474 144626 -1 2003 21 1136 2050 128645 30983 2.66571 2.66571 -101.838 -2.66571 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145269 0.0129327 130 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 3.35 vpr 63.82 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29780 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65348 32 32 338 277 1 215 89 17 17 289 -1 unnamed_device 24.9 MiB 1.36 2459 1294 14741 4922 7916 1903 63.8 MiB 0.09 0.00 5.82658 4.85308 -136.949 -4.85308 4.85308 0.24 0.000317563 0.000290569 0.025462 0.0232995 -1 -1 -1 -1 32 2850 43 6.89349e+06 352346 586450. 2029.24 0.61 0.0964175 0.0847986 25474 144626 -1 2288 20 1262 1877 121444 29241 3.65326 3.65326 -130.716 -3.65326 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0153091 0.0136806 139 50 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_029.v common 3.54 vpr 64.44 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29808 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 32 32 284 241 1 177 84 17 17 289 -1 unnamed_device 24.9 MiB 1.26 1936 1067 12894 4344 6614 1936 64.4 MiB 0.07 0.00 4.31105 3.7646 -126.911 -3.7646 3.7646 0.24 0.000281184 0.000257399 0.0213517 0.0195486 -1 -1 -1 -1 32 2226 20 6.89349e+06 281877 586450. 2029.24 0.96 0.0987942 0.0861715 25474 144626 -1 1958 21 1103 1593 110334 26241 2.69186 2.69186 -115.097 -2.69186 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0143842 0.0127846 110 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_030.v common 2.58 vpr 64.37 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30264 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 30 32 262 227 1 161 83 17 17 289 -1 unnamed_device 24.9 MiB 0.86 2301 943 13043 4183 6793 2067 64.4 MiB 0.06 0.00 5.05544 4.00962 -116.333 -4.00962 4.00962 0.25 0.000274696 0.000251996 0.0211122 0.0193502 -1 -1 -1 -1 32 2109 18 6.89349e+06 295971 586450. 2029.24 0.37 0.0588309 0.0520159 25474 144626 -1 1793 21 971 1595 128041 29328 3.30785 3.30785 -109.419 -3.30785 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0162331 0.0145062 103 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_031.v common 3.34 vpr 64.19 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29604 -1 -1 20 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65732 28 32 260 223 1 163 80 17 17 289 -1 unnamed_device 24.7 MiB 1.04 1953 1013 13324 4541 7089 1694 64.2 MiB 0.08 0.00 5.13107 4.43603 -124.612 -4.43603 4.43603 0.26 0.000270744 0.000248135 0.0269024 0.0247709 -1 -1 -1 -1 30 2187 21 6.89349e+06 281877 556674. 1926.21 0.98 0.110529 0.0969537 25186 138497 -1 1819 17 903 1571 100336 23266 3.3055 3.3055 -115.801 -3.3055 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0112853 0.0100418 104 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_032.v common 3.17 vpr 64.25 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29720 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 24.8 MiB 0.85 2155 955 10228 2872 6411 945 64.2 MiB 0.05 0.00 4.55303 3.92502 -120.982 -3.92502 3.92502 0.24 0.000264604 0.000242521 0.0173918 0.015918 -1 -1 -1 -1 32 2080 26 6.89349e+06 253689 586450. 2029.24 1.01 0.103009 0.0892271 25474 144626 -1 1800 19 1015 1740 120492 28474 2.78381 2.78381 -113.151 -2.78381 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0120413 0.0106721 101 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 3.00 vpr 64.44 MiB -1 -1 0.20 18056 1 0.02 -1 -1 29764 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 31 32 271 231 1 172 84 17 17 289 -1 unnamed_device 24.6 MiB 1.05 2571 955 9966 2827 6447 692 64.4 MiB 0.05 0.00 4.5958 3.73465 -114.886 -3.73465 3.73465 0.25 0.000280398 0.000257313 0.0163776 0.0149922 -1 -1 -1 -1 26 2565 37 6.89349e+06 295971 503264. 1741.40 0.50 0.0627421 0.0550562 24322 120374 -1 2108 18 1121 1641 117820 29274 3.19091 3.19091 -118.654 -3.19091 0 0 618332. 2139.56 0.02 0.03 0.11 -1 -1 0.02 0.0119732 0.0106622 105 30 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 3.97 vpr 63.87 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29848 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 29 32 291 250 1 185 84 17 17 289 -1 unnamed_device 24.7 MiB 1.46 2485 957 12894 3059 8335 1500 63.9 MiB 0.06 0.00 4.26057 3.6185 -104.685 -3.6185 3.6185 0.25 0.000308233 0.000278605 0.0227674 0.0209684 -1 -1 -1 -1 34 2000 20 6.89349e+06 324158 618332. 2139.56 1.16 0.133759 0.116522 25762 151098 -1 1717 18 913 1287 86496 21872 2.65071 2.65071 -97.5528 -2.65071 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0126343 0.0112802 117 54 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_035.v common 4.08 vpr 64.57 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29612 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 367 282 1 224 91 17 17 289 -1 unnamed_device 24.9 MiB 1.04 2453 1261 14371 4620 7204 2547 64.6 MiB 0.09 0.00 5.05875 4.57545 -133.583 -4.57545 4.57545 0.25 0.000352767 0.000323289 0.0269709 0.0247561 -1 -1 -1 -1 36 2825 23 6.89349e+06 380534 648988. 2245.63 1.58 0.178928 0.157203 26050 158493 -1 2396 20 1295 2069 145934 34231 3.97056 3.97056 -127.691 -3.97056 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0167835 0.0150141 154 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_036.v common 4.42 vpr 64.68 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30128 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 391 311 1 250 92 17 17 289 -1 unnamed_device 25.2 MiB 1.60 2644 1340 16238 5326 8855 2057 64.7 MiB 0.10 0.00 4.96607 4.60807 -154.992 -4.60807 4.60807 0.25 0.000361877 0.000331603 0.0308029 0.028253 -1 -1 -1 -1 32 3395 36 6.89349e+06 394628 586450. 2029.24 1.34 0.162449 0.143043 25474 144626 -1 2714 23 2107 3054 238419 53335 3.72925 3.72925 -145.858 -3.72925 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.019568 0.017421 163 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_037.v common 2.66 vpr 64.02 MiB -1 -1 0.12 18052 1 0.02 -1 -1 29812 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 24.9 MiB 0.84 2434 989 8306 2314 5441 551 64.0 MiB 0.05 0.00 4.86668 4.04584 -122.858 -4.04584 4.04584 0.25 0.000282431 0.000258833 0.0169493 0.0155912 -1 -1 -1 -1 32 2127 23 6.89349e+06 253689 586450. 2029.24 0.40 0.0554529 0.0490594 25474 144626 -1 1912 23 1092 1705 138575 32111 3.38461 3.38461 -118.083 -3.38461 0 0 744469. 2576.02 0.04 0.06 0.12 -1 -1 0.04 0.0225944 0.0201313 107 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 4.05 vpr 64.24 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30160 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65780 31 32 370 297 1 235 90 17 17 289 -1 unnamed_device 24.9 MiB 1.59 2670 1289 13155 3308 7952 1895 64.2 MiB 0.08 0.00 5.12349 4.31155 -137.727 -4.31155 4.31155 0.24 0.00034025 0.000311385 0.0239065 0.0219058 -1 -1 -1 -1 30 2812 22 6.89349e+06 380534 556674. 1926.21 1.10 0.121591 0.106877 25186 138497 -1 2328 20 1532 2286 129522 32467 3.41065 3.41065 -129.329 -3.41065 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0161074 0.0143427 154 61 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 3.89 vpr 65.05 MiB -1 -1 0.14 17676 1 0.03 -1 -1 30160 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 31 32 377 302 1 241 91 17 17 289 -1 unnamed_device 25.2 MiB 1.61 2869 1286 10291 2730 6649 912 65.0 MiB 0.07 0.00 6.59857 5.48687 -163.025 -5.48687 5.48687 0.25 0.000347488 0.000319042 0.0195108 0.0178794 -1 -1 -1 -1 32 3330 22 6.89349e+06 394628 586450. 2029.24 0.79 0.0829449 0.0732081 25474 144626 -1 2600 21 1764 2590 214962 46783 4.41735 4.41735 -155.28 -4.41735 0 0 744469. 2576.02 0.04 0.08 0.13 -1 -1 0.04 0.0280281 0.0249912 158 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_040.v common 3.79 vpr 64.29 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30140 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 31 32 383 305 1 240 92 17 17 289 -1 unnamed_device 24.9 MiB 1.77 2971 1288 18308 5162 11169 1977 64.3 MiB 0.11 0.00 7.06021 5.82563 -172.459 -5.82563 5.82563 0.24 0.000352762 0.000318106 0.0338824 0.0310012 -1 -1 -1 -1 32 3079 30 6.89349e+06 408721 586450. 2029.24 0.50 0.0862449 0.076668 25474 144626 -1 2614 23 1873 2828 219295 50747 5.21269 5.21269 -171.607 -5.21269 0 0 744469. 2576.02 0.03 0.06 0.16 -1 -1 0.03 0.0202925 0.0181011 160 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_041.v common 3.23 vpr 64.96 MiB -1 -1 0.13 18056 1 0.04 -1 -1 29764 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 31 32 352 285 1 223 90 17 17 289 -1 unnamed_device 25.2 MiB 1.25 2244 1364 13356 3907 7417 2032 65.0 MiB 0.08 0.00 4.56598 4.06478 -129.084 -4.06478 4.06478 0.24 0.000332109 0.000304119 0.0239262 0.0219187 -1 -1 -1 -1 30 3087 26 6.89349e+06 380534 556674. 1926.21 0.48 0.0737516 0.0650058 25186 138497 -1 2499 20 1518 2227 158913 35691 3.44916 3.44916 -121.559 -3.44916 0 0 706193. 2443.58 0.03 0.04 0.13 -1 -1 0.03 0.0158182 0.0140933 147 55 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_042.v common 3.82 vpr 64.50 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30156 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 32 32 291 242 1 188 86 17 17 289 -1 unnamed_device 25.2 MiB 1.22 2505 1019 15017 5391 6893 2733 64.5 MiB 0.07 0.00 5.50703 4.42605 -118.578 -4.42605 4.42605 0.24 0.000290947 0.000266089 0.024837 0.022735 -1 -1 -1 -1 30 2553 47 6.89349e+06 310065 556674. 1926.21 1.26 0.131474 0.114382 25186 138497 -1 1963 19 1069 1508 97270 23623 3.8018 3.8018 -115.623 -3.8018 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0134814 0.012024 114 27 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_043.v common 4.96 vpr 65.33 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29828 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66896 32 32 457 356 1 296 101 17 17 289 -1 unnamed_device 25.6 MiB 2.07 3202 1707 11616 2831 7740 1045 65.3 MiB 0.10 0.00 6.63 5.71166 -180.923 -5.71166 5.71166 0.24 0.000421051 0.000387062 0.029106 0.0268523 -1 -1 -1 -1 32 4457 33 6.89349e+06 521472 586450. 2029.24 1.36 0.174611 0.153493 25474 144626 -1 3340 23 2283 3484 283406 73527 4.54378 4.54378 -163.759 -4.54378 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0244152 0.0218808 199 87 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_044.v common 2.47 vpr 64.36 MiB -1 -1 0.14 17676 1 0.03 -1 -1 30212 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 31 32 261 225 1 171 83 17 17 289 -1 unnamed_device 24.9 MiB 0.78 2305 761 9803 2301 6865 637 64.4 MiB 0.05 0.00 4.9117 3.8019 -108.91 -3.8019 3.8019 0.25 0.000282573 0.000259542 0.0176186 0.0162018 -1 -1 -1 -1 32 2072 23 6.89349e+06 281877 586450. 2029.24 0.35 0.0559811 0.0492287 25474 144626 -1 1627 20 1015 1385 86539 22892 3.18906 3.18906 -107.56 -3.18906 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0125017 0.0110861 101 28 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_045.v common 4.29 vpr 64.86 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29856 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66412 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 24.9 MiB 1.31 2787 1139 8473 1978 5944 551 64.9 MiB 0.06 0.00 5.76922 4.83408 -143.835 -4.83408 4.83408 0.25 0.000323 0.000295931 0.0164862 0.0151597 -1 -1 -1 -1 28 3258 24 6.89349e+06 352346 531479. 1839.03 1.61 0.11073 0.0969671 24610 126494 -1 2479 21 1692 2507 182798 44288 4.1091 4.1091 -145.402 -4.1091 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0160239 0.0143004 139 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_046.v common 3.42 vpr 64.40 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29704 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 349 284 1 222 91 17 17 289 -1 unnamed_device 24.8 MiB 1.38 2669 1235 9475 2196 6793 486 64.4 MiB 0.07 0.00 5.26295 4.39795 -133.209 -4.39795 4.39795 0.26 0.000355222 0.000316909 0.0220287 0.0202872 -1 -1 -1 -1 30 3163 30 6.89349e+06 380534 556674. 1926.21 0.62 0.0861179 0.0762636 25186 138497 -1 2521 38 1868 3138 263695 85979 3.45195 3.45195 -128.059 -3.45195 0 0 706193. 2443.58 0.03 0.08 0.07 -1 -1 0.03 0.0244879 0.0215511 146 53 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_047.v common 3.30 vpr 64.44 MiB -1 -1 0.22 17676 1 0.02 -1 -1 29788 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 32 32 291 230 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 0.71 1933 1092 14575 4579 7786 2210 64.4 MiB 0.08 0.00 4.84964 4.24939 -129.722 -4.24939 4.24939 0.24 0.00086745 0.000802011 0.0241679 0.0221141 -1 -1 -1 -1 32 2496 21 6.89349e+06 380534 586450. 2029.24 1.14 0.111521 0.0978012 25474 144626 -1 2102 21 1130 2260 167469 38040 3.607 3.607 -125.377 -3.607 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0144232 0.0128114 123 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_048.v common 4.01 vpr 64.57 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29752 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 353 287 1 220 90 17 17 289 -1 unnamed_device 24.9 MiB 1.31 2606 1137 13959 4872 6200 2887 64.6 MiB 0.08 0.00 4.99599 4.43611 -128.994 -4.43611 4.43611 0.24 0.000337654 0.000308984 0.0250131 0.0228926 -1 -1 -1 -1 36 2583 24 6.89349e+06 366440 648988. 2245.63 1.32 0.134965 0.117841 26050 158493 -1 2080 19 1418 1940 131258 33952 3.32661 3.32661 -114.202 -3.32661 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0151167 0.0135052 143 55 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_049.v common 4.06 vpr 64.57 MiB -1 -1 0.11 17908 1 0.03 -1 -1 29788 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 361 291 1 231 90 17 17 289 -1 unnamed_device 24.9 MiB 1.46 2568 1471 16773 5286 9456 2031 64.6 MiB 0.11 0.00 5.07339 4.21419 -136.215 -4.21419 4.21419 0.25 0.000340656 0.000312322 0.0401428 0.0371406 -1 -1 -1 -1 26 3247 37 6.89349e+06 366440 503264. 1741.40 1.17 0.154223 0.136036 24322 120374 -1 2794 20 1750 2576 179633 42531 3.67355 3.67355 -137.947 -3.67355 0 0 618332. 2139.56 0.02 0.05 0.06 -1 -1 0.02 0.0159892 0.0142241 149 55 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_050.v common 5.10 vpr 65.05 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29844 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 382 305 1 243 92 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2705 1368 16031 4740 8553 2738 65.1 MiB 0.09 0.00 5.02847 4.40197 -141.012 -4.40197 4.40197 0.36 0.00035782 0.000328643 0.0292191 0.0267664 -1 -1 -1 -1 36 3034 44 6.89349e+06 394628 648988. 2245.63 1.76 0.173531 0.152219 26050 158493 -1 2623 21 1990 2843 215002 49630 3.41336 3.41336 -127.927 -3.41336 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0213513 0.0191552 160 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_051.v common 3.39 vpr 63.93 MiB -1 -1 0.11 18300 1 0.03 -1 -1 29748 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65464 32 32 306 248 1 188 87 17 17 289 -1 unnamed_device 24.7 MiB 0.98 2196 1143 14295 3709 9126 1460 63.9 MiB 0.08 0.00 5.64975 4.52825 -134.553 -4.52825 4.52825 0.25 0.000307577 0.000281552 0.0241934 0.0221636 -1 -1 -1 -1 26 2654 43 6.89349e+06 324158 503264. 1741.40 1.10 0.126441 0.110874 24322 120374 -1 2299 20 1441 2205 153221 36540 4.2106 4.2106 -141.768 -4.2106 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.014174 0.012622 123 24 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_052.v common 2.59 vpr 64.79 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29952 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66348 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 24.9 MiB 0.92 2220 1132 9303 2287 5956 1060 64.8 MiB 0.06 0.00 5.85178 4.86728 -141.077 -4.86728 4.86728 0.24 0.00031178 0.000285633 0.0165258 0.0151309 -1 -1 -1 -1 30 2732 27 6.89349e+06 324158 556674. 1926.21 0.37 0.0623473 0.0549675 25186 138497 -1 2302 22 1328 1944 126115 30047 3.82166 3.82166 -132.023 -3.82166 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.015552 0.0138663 129 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_053.v common 3.46 vpr 64.98 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29768 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66536 31 32 373 299 1 227 90 17 17 289 -1 unnamed_device 25.2 MiB 1.38 2459 1142 10944 2981 6313 1650 65.0 MiB 0.07 0.00 5.42896 4.77798 -141.248 -4.77798 4.77798 0.35 0.000351179 0.000321756 0.0206113 0.0188859 -1 -1 -1 -1 32 3654 30 6.89349e+06 380534 586450. 2029.24 0.54 0.0724628 0.0639195 25474 144626 -1 2569 21 1631 2555 180112 43962 4.02469 4.02469 -136.645 -4.02469 0 0 744469. 2576.02 0.03 0.05 0.13 -1 -1 0.03 0.0166904 0.0148941 154 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_054.v common 4.29 vpr 65.09 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29528 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66652 32 32 387 315 1 247 91 17 17 289 -1 unnamed_device 25.2 MiB 1.78 2851 1347 7231 1595 5190 446 65.1 MiB 0.05 0.00 5.65933 4.38345 -134.94 -4.38345 4.38345 0.24 0.000357978 0.000328523 0.0146477 0.0134302 -1 -1 -1 -1 32 3284 25 6.89349e+06 380534 586450. 2029.24 1.09 0.112964 0.0982118 25474 144626 -1 2634 20 2010 2965 184477 44253 3.54626 3.54626 -130.981 -3.54626 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0169355 0.0150937 160 77 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_055.v common 4.33 vpr 64.33 MiB -1 -1 0.15 17676 1 0.02 -1 -1 29816 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 251 219 1 156 81 17 17 289 -1 unnamed_device 24.9 MiB 0.98 1772 720 12681 4996 6149 1536 64.3 MiB 0.05 0.00 4.27105 3.55383 -105.248 -3.55383 3.55383 0.35 0.000260874 0.00023824 0.0202907 0.0185529 -1 -1 -1 -1 32 2262 44 6.89349e+06 239595 586450. 2029.24 1.89 0.130372 0.113046 25474 144626 -1 1579 19 952 1380 99711 28807 2.81411 2.81411 -102.252 -2.81411 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0119485 0.0106421 93 23 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_056.v common 3.03 vpr 64.53 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30208 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 341 285 1 219 88 17 17 289 -1 unnamed_device 24.9 MiB 1.23 2681 1141 15103 4277 8627 2199 64.5 MiB 0.09 0.00 5.91853 4.58813 -154.793 -4.58813 4.58813 0.25 0.000320476 0.000293647 0.0265283 0.0242834 -1 -1 -1 -1 32 2780 22 6.89349e+06 338252 586450. 2029.24 0.40 0.0714864 0.0634616 25474 144626 -1 2260 21 1752 2418 177496 42479 3.78384 3.78384 -143.369 -3.78384 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0157346 0.0140365 137 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_057.v common 3.73 vpr 65.04 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29980 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66600 32 32 387 293 1 237 93 17 17 289 -1 unnamed_device 25.6 MiB 1.16 2868 1359 7443 1583 5363 497 65.0 MiB 0.06 0.00 6.45037 5.51607 -162.931 -5.51607 5.51607 0.24 0.000366596 0.000336094 0.0148177 0.0136169 -1 -1 -1 -1 32 3548 27 6.89349e+06 408721 586450. 2029.24 1.21 0.122099 0.106722 25474 144626 -1 2719 24 1840 2982 202888 48705 4.85635 4.85635 -159.726 -4.85635 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0194438 0.0173392 166 31 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_058.v common 2.75 vpr 64.23 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29948 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 32 32 340 270 1 212 88 17 17 289 -1 unnamed_device 25.2 MiB 1.00 2505 1217 15493 4661 8456 2376 64.2 MiB 0.09 0.00 5.54276 4.5126 -143.919 -4.5126 4.5126 0.24 0.000326565 0.000298191 0.0283386 0.0259713 -1 -1 -1 -1 32 2665 26 6.89349e+06 338252 586450. 2029.24 0.38 0.0732243 0.065078 25474 144626 -1 2106 18 1333 1923 122925 29624 2.94921 2.94921 -122.833 -2.94921 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145007 0.0129746 137 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_059.v common 2.83 vpr 64.14 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29820 -1 -1 32 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65684 30 32 278 235 1 175 94 17 17 289 -1 unnamed_device 25.1 MiB 1.03 2250 1061 16282 4606 9784 1892 64.1 MiB 0.08 0.00 5.16569 4.37039 -131.236 -4.37039 4.37039 0.24 0.000283376 0.000255448 0.0231331 0.021189 -1 -1 -1 -1 30 2166 21 6.89349e+06 451003 556674. 1926.21 0.35 0.0595493 0.0527931 25186 138497 -1 1802 21 1102 1807 103448 25235 3.19625 3.19625 -118.702 -3.19625 0 0 706193. 2443.58 0.04 0.05 0.11 -1 -1 0.04 0.0200294 0.0177972 118 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_060.v common 5.65 vpr 64.85 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29820 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66408 32 32 431 332 1 270 94 17 17 289 -1 unnamed_device 25.2 MiB 1.90 3075 1543 15004 4609 8067 2328 64.9 MiB 0.11 0.00 7.91759 6.34645 -186.607 -6.34645 6.34645 0.34 0.000416403 0.000382506 0.0312082 0.0287208 -1 -1 -1 -1 34 3953 24 6.89349e+06 422815 618332. 2139.56 2.22 0.207421 0.183112 25762 151098 -1 3259 22 2492 3991 303577 69677 5.59473 5.59473 -185.938 -5.59473 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0201136 0.017945 182 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_061.v common 3.31 vpr 64.80 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29956 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 336 268 1 205 88 17 17 289 -1 unnamed_device 24.9 MiB 0.88 2530 936 7303 1455 5167 681 64.8 MiB 0.04 0.00 5.66882 4.76668 -140.932 -4.76668 4.76668 0.24 0.000324361 0.00029737 0.013727 0.0125967 -1 -1 -1 -1 34 2331 26 6.89349e+06 338252 618332. 2139.56 1.13 0.102032 0.089028 25762 151098 -1 1928 21 1515 2171 157974 39480 3.73286 3.73286 -126.515 -3.73286 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0156274 0.0139155 136 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_062.v common 2.77 vpr 63.61 MiB -1 -1 0.13 17676 1 0.02 -1 -1 29944 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65132 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 23.9 MiB 0.53 1762 895 10649 2847 7198 604 63.6 MiB 0.05 0.00 3.9244 3.74796 -105.814 -3.74796 3.74796 0.24 0.000268278 0.000244282 0.0179661 0.0166428 -1 -1 -1 -1 32 1907 18 6.89349e+06 394628 586450. 2029.24 0.90 0.0935599 0.0813927 25474 144626 -1 1683 19 741 1322 94047 22538 2.77811 2.77811 -100.732 -2.77811 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0110016 0.00974569 96 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_063.v common 4.11 vpr 64.88 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29820 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 349 273 1 214 91 17 17 289 -1 unnamed_device 24.8 MiB 1.25 3131 1378 18043 5544 10561 1938 64.9 MiB 0.11 0.00 6.94676 5.55938 -147.432 -5.55938 5.55938 0.25 0.000339508 0.000310993 0.0322799 0.0295947 -1 -1 -1 -1 30 2968 27 6.89349e+06 380534 556674. 1926.21 1.36 0.143251 0.126546 25186 138497 -1 2443 20 1275 2357 162480 37915 4.27535 4.27535 -136.057 -4.27535 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0192963 0.0171527 146 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_064.v common 3.12 vpr 64.30 MiB -1 -1 0.10 17668 1 0.03 -1 -1 29808 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 24.9 MiB 0.71 2118 762 14407 5564 6574 2269 64.3 MiB 0.06 0.00 4.4685 3.6244 -108.803 -3.6244 3.6244 0.24 0.000261105 0.000238587 0.0216374 0.0197903 -1 -1 -1 -1 34 1873 19 6.89349e+06 295971 618332. 2139.56 1.12 0.118262 0.102525 25762 151098 -1 1576 20 1144 2018 129507 32747 2.93836 2.93836 -105.161 -2.93836 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0122186 0.0108317 99 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_065.v common 3.40 vpr 64.37 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29832 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 30 32 278 235 1 175 86 17 17 289 -1 unnamed_device 24.7 MiB 1.03 2617 994 11426 3379 7154 893 64.4 MiB 0.06 0.00 5.48567 4.35797 -127.583 -4.35797 4.35797 0.25 0.000284282 0.000261237 0.0182379 0.0167215 -1 -1 -1 -1 30 2087 21 6.89349e+06 338252 556674. 1926.21 1.02 0.105116 0.0921757 25186 138497 -1 1740 21 1006 1535 104945 23844 3.05475 3.05475 -111.469 -3.05475 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0135113 0.011984 110 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_066.v common 4.35 vpr 64.92 MiB -1 -1 0.15 18064 1 0.03 -1 -1 30120 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66480 29 32 355 287 1 223 90 17 17 289 -1 unnamed_device 25.2 MiB 1.68 3036 1235 16170 4166 10388 1616 64.9 MiB 0.12 0.00 6.20943 4.65473 -135.021 -4.65473 4.65473 0.26 0.000340499 0.000312371 0.0380566 0.0352096 -1 -1 -1 -1 30 2943 33 6.89349e+06 408721 556674. 1926.21 1.24 0.150728 0.132472 25186 138497 -1 2341 19 1282 1890 114886 27835 3.41865 3.41865 -124.026 -3.41865 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0150858 0.0134617 150 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_067.v common 4.30 vpr 64.95 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29764 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 32 32 358 289 1 230 91 17 17 289 -1 unnamed_device 24.9 MiB 1.53 2704 1306 16819 4681 10419 1719 64.9 MiB 0.09 0.00 6.50098 4.98955 -155.576 -4.98955 4.98955 0.32 0.000334926 0.000306435 0.0292019 0.0266694 -1 -1 -1 -1 30 2937 26 6.89349e+06 380534 556674. 1926.21 1.17 0.135449 0.118337 25186 138497 -1 2245 22 1603 2359 152417 37029 4.30739 4.30739 -148.653 -4.30739 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0166872 0.0148652 149 54 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_068.v common 4.36 vpr 64.91 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30160 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 353 285 1 227 89 17 17 289 -1 unnamed_device 24.9 MiB 1.57 2686 1321 12959 3747 7875 1337 64.9 MiB 0.08 0.00 6.75127 5.45967 -157.239 -5.45967 5.45967 0.34 0.000333505 0.000305472 0.0233836 0.0214198 -1 -1 -1 -1 30 3232 23 6.89349e+06 352346 556674. 1926.21 1.24 0.13275 0.115861 25186 138497 -1 2671 21 1571 2337 162253 37482 4.45865 4.45865 -150.907 -4.45865 0 0 706193. 2443.58 0.03 0.05 0.12 -1 -1 0.03 0.016106 0.0143412 144 51 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_069.v common 3.50 vpr 64.39 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29756 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 276 237 1 165 82 17 17 289 -1 unnamed_device 24.9 MiB 1.13 1895 1005 11652 3070 6952 1630 64.4 MiB 0.07 0.00 5.1192 4.9044 -138.677 -4.9044 4.9044 0.26 0.000278309 0.000254748 0.0235075 0.0216386 -1 -1 -1 -1 32 2185 33 6.89349e+06 253689 586450. 2029.24 1.01 0.115145 0.100551 25474 144626 -1 1883 14 742 1011 79811 18262 3.27225 3.27225 -119.982 -3.27225 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0114505 0.0102782 103 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_070.v common 3.91 vpr 64.19 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30176 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 31 32 319 272 1 203 85 17 17 289 -1 unnamed_device 25.2 MiB 1.37 2292 1146 15523 5307 8105 2111 64.2 MiB 0.10 0.00 4.5444 3.67535 -123.05 -3.67535 3.67535 0.25 0.000307579 0.000282148 0.0348281 0.0320625 -1 -1 -1 -1 34 2599 23 6.89349e+06 310065 618332. 2139.56 1.15 0.134759 0.118755 25762 151098 -1 2270 20 1476 2059 153853 36261 3.29286 3.29286 -123.024 -3.29286 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0143522 0.0127744 125 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_071.v common 4.12 vpr 64.14 MiB -1 -1 0.12 18064 1 0.03 -1 -1 29804 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65684 30 32 329 273 1 213 89 17 17 289 -1 unnamed_device 24.6 MiB 1.51 2646 1203 12761 3384 8201 1176 64.1 MiB 0.07 0.00 4.5069 3.773 -110.836 -3.773 3.773 0.24 0.000311783 0.000285761 0.02181 0.0200015 -1 -1 -1 -1 28 2719 25 6.89349e+06 380534 531479. 1839.03 1.20 0.137278 0.120489 24610 126494 -1 2355 23 1698 2575 179984 42945 3.00476 3.00476 -111.209 -3.00476 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0163353 0.0144894 139 57 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_072.v common 3.37 vpr 64.45 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29840 -1 -1 26 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 28 32 277 229 1 171 86 17 17 289 -1 unnamed_device 25.2 MiB 0.89 2290 995 14639 5073 7461 2105 64.5 MiB 0.07 0.00 5.43839 4.41095 -114.576 -4.41095 4.41095 0.24 0.000281419 0.000258556 0.0248781 0.0228497 -1 -1 -1 -1 30 2148 20 6.89349e+06 366440 556674. 1926.21 1.07 0.103487 0.0905008 25186 138497 -1 1844 17 968 1744 111480 25633 3.44096 3.44096 -108.289 -3.44096 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.011729 0.0104772 116 27 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_073.v common 3.60 vpr 64.80 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29776 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66352 30 32 317 269 1 202 85 17 17 289 -1 unnamed_device 24.9 MiB 1.62 2526 1178 15151 5407 7948 1796 64.8 MiB 0.08 0.00 6.03926 4.84252 -145.079 -4.84252 4.84252 0.36 0.000308102 0.00028241 0.0259855 0.0238032 -1 -1 -1 -1 32 2638 26 6.89349e+06 324158 586450. 2029.24 0.54 0.0727006 0.0644386 25474 144626 -1 2199 17 1333 1877 129448 30773 3.77919 3.77919 -132.955 -3.77919 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0129051 0.0115612 127 63 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_074.v common 3.30 vpr 64.90 MiB -1 -1 0.18 18060 1 0.04 -1 -1 29804 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66460 32 32 335 282 1 222 88 17 17 289 -1 unnamed_device 24.9 MiB 1.19 2501 1336 13543 3628 8253 1662 64.9 MiB 0.08 0.00 4.4454 3.9442 -135.714 -3.9442 3.9442 0.24 0.000315843 0.000288919 0.0231779 0.0211775 -1 -1 -1 -1 32 3103 40 6.89349e+06 338252 586450. 2029.24 0.56 0.0750108 0.066122 25474 144626 -1 2494 23 1598 2140 158708 36808 3.28651 3.28651 -129.749 -3.28651 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0160547 0.0142476 131 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_075.v common 2.57 vpr 64.46 MiB -1 -1 0.13 17676 1 0.03 -1 -1 29532 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 293 230 1 175 96 17 17 289 -1 unnamed_device 24.7 MiB 0.63 2002 1084 14769 4409 8006 2354 64.5 MiB 0.07 0.00 5.30012 4.68052 -134.297 -4.68052 4.68052 0.24 0.000295535 0.000269833 0.0214319 0.0196168 -1 -1 -1 -1 28 2586 32 6.89349e+06 465097 531479. 1839.03 0.54 0.0663218 0.0585427 24610 126494 -1 2233 21 1356 2590 184684 43970 3.7486 3.7486 -127.386 -3.7486 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.01425 0.0126423 130 4 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_076.v common 3.30 vpr 64.94 MiB -1 -1 0.11 17744 1 0.03 -1 -1 30352 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66496 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 24.9 MiB 1.40 2769 1083 6718 1366 4439 913 64.9 MiB 0.05 0.00 5.69108 4.83188 -148.303 -4.83188 4.83188 0.35 0.000338842 0.000310699 0.0130856 0.0120274 -1 -1 -1 -1 32 2917 37 6.89349e+06 338252 586450. 2029.24 0.48 0.0657926 0.0578615 25474 144626 -1 2309 21 1509 2317 154492 38324 3.91029 3.91029 -139.835 -3.91029 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.016088 0.0143116 142 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_077.v common 5.21 vpr 65.04 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29796 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66596 32 32 385 308 1 244 92 17 17 289 -1 unnamed_device 25.7 MiB 1.48 2790 1274 17273 5734 8473 3066 65.0 MiB 0.12 0.00 6.85201 5.78412 -176.84 -5.78412 5.78412 0.26 0.000597265 0.000566774 0.0414682 0.0383639 -1 -1 -1 -1 34 3863 36 6.89349e+06 394628 618332. 2139.56 2.28 0.215964 0.190586 25762 151098 -1 2559 23 1887 2646 185724 45717 4.97334 4.97334 -162.157 -4.97334 0 0 787024. 2723.27 0.03 0.06 0.08 -1 -1 0.03 0.0215156 0.0190645 162 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_078.v common 3.67 vpr 64.65 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29836 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66200 32 32 387 309 1 248 93 17 17 289 -1 unnamed_device 25.2 MiB 1.66 3405 1313 11223 3015 7022 1186 64.6 MiB 0.07 0.00 6.15614 4.85896 -154.704 -4.85896 4.85896 0.24 0.000355317 0.000325773 0.0210931 0.0192759 -1 -1 -1 -1 32 3310 32 6.89349e+06 408721 586450. 2029.24 0.54 0.0745848 0.0659313 25474 144626 -1 2572 19 1527 2333 153538 35602 3.68845 3.68845 -137.066 -3.68845 0 0 744469. 2576.02 0.03 0.04 0.13 -1 -1 0.03 0.0166105 0.0147769 163 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_079.v common 3.71 vpr 64.38 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29856 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 30 32 272 232 1 175 84 17 17 289 -1 unnamed_device 25.2 MiB 1.31 2272 918 14724 4804 7694 2226 64.4 MiB 0.07 0.00 5.36037 4.39377 -130.219 -4.39377 4.39377 0.24 0.000287341 0.000264486 0.0234956 0.0215251 -1 -1 -1 -1 30 2227 25 6.89349e+06 310065 556674. 1926.21 1.10 0.108014 0.0941904 25186 138497 -1 1897 16 970 1436 106281 24291 3.2479 3.2479 -115.807 -3.2479 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0114634 0.010241 108 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_080.v common 4.51 vpr 64.62 MiB -1 -1 0.12 18060 1 0.04 -1 -1 30192 -1 -1 29 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 30 32 375 299 1 236 91 17 17 289 -1 unnamed_device 25.2 MiB 1.55 3003 1114 16819 5989 7667 3163 64.6 MiB 0.09 0.00 6.38211 5.54961 -163.139 -5.54961 5.54961 0.25 0.000340617 0.000311648 0.0301202 0.0275803 -1 -1 -1 -1 34 2922 32 6.89349e+06 408721 618332. 2139.56 1.39 0.156699 0.137371 25762 151098 -1 2293 19 1618 2268 162682 39870 4.68838 4.68838 -154.58 -4.68838 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.015856 0.0141856 159 63 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_081.v common 3.54 vpr 64.86 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29880 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 24.9 MiB 0.94 2652 1098 15731 5114 8768 1849 64.9 MiB 0.09 0.00 5.91759 5.21145 -150.283 -5.21145 5.21145 0.24 0.000328416 0.000300997 0.028151 0.0258108 -1 -1 -1 -1 32 2768 22 6.89349e+06 352346 586450. 2029.24 1.20 0.135819 0.119475 25474 144626 -1 2250 20 1419 2440 185945 44358 4.03336 4.03336 -132.792 -4.03336 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0152433 0.0136056 137 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_082.v common 4.27 vpr 64.33 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29652 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 31 32 340 275 1 211 88 17 17 289 -1 unnamed_device 24.7 MiB 1.65 2743 1182 11788 3318 7484 986 64.3 MiB 0.07 0.00 6.23744 5.09779 -147.137 -5.09779 5.09779 0.24 0.000321184 0.000294656 0.021254 0.0194531 -1 -1 -1 -1 32 2731 26 6.89349e+06 352346 586450. 2029.24 1.07 0.113692 0.0993541 25474 144626 -1 2290 19 1442 2154 142174 34243 4.42139 4.42139 -145.725 -4.42139 0 0 744469. 2576.02 0.03 0.04 0.09 -1 -1 0.03 0.0147709 0.0132276 139 47 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_083.v common 4.19 vpr 64.57 MiB -1 -1 0.15 18060 1 0.03 -1 -1 30520 -1 -1 30 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66120 30 32 377 310 1 239 92 17 17 289 -1 unnamed_device 24.9 MiB 1.58 3065 1308 17480 5851 9201 2428 64.6 MiB 0.11 0.00 6.31486 5.04907 -145.771 -5.04907 5.04907 0.25 0.000363407 0.000333582 0.034511 0.0317521 -1 -1 -1 -1 34 2995 23 6.89349e+06 422815 618332. 2139.56 1.11 0.131067 0.115037 25762 151098 -1 2440 29 2151 3033 223442 62433 3.98754 3.98754 -132.06 -3.98754 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0212267 0.0187147 160 83 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_084.v common 4.21 vpr 64.60 MiB -1 -1 0.14 18444 1 0.03 -1 -1 30172 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 32 32 365 294 1 230 89 17 17 289 -1 unnamed_device 25.1 MiB 1.54 2903 1193 13553 4146 6698 2709 64.6 MiB 0.09 0.00 6.82527 5.54847 -159.396 -5.54847 5.54847 0.24 0.000340769 0.000311467 0.0254812 0.0233158 -1 -1 -1 -1 36 2667 24 6.89349e+06 352346 648988. 2245.63 1.27 0.129417 0.113035 26050 158493 -1 2183 22 1623 2400 146356 36675 4.41775 4.41775 -145.775 -4.41775 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0172307 0.0153579 150 57 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_085.v common 4.61 vpr 64.64 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30156 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66188 29 32 378 310 1 246 92 17 17 289 -1 unnamed_device 25.2 MiB 1.49 2857 1221 11684 3249 7028 1407 64.6 MiB 0.07 0.00 5.69689 4.40161 -128.825 -4.40161 4.40161 0.24 0.000347187 0.000318839 0.0212948 0.0195102 -1 -1 -1 -1 30 3093 22 6.89349e+06 436909 556674. 1926.21 1.62 0.150322 0.131694 25186 138497 -1 2297 20 1507 2044 138797 32504 3.501 3.501 -118.443 -3.501 0 0 706193. 2443.58 0.04 0.07 0.12 -1 -1 0.04 0.027885 0.0249954 162 85 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_086.v common 3.09 vpr 64.28 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30312 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 24.9 MiB 0.72 1910 928 13788 4105 7638 2045 64.3 MiB 0.06 0.00 4.56098 4.02268 -121.319 -4.02268 4.02268 0.25 0.000259422 0.000237335 0.0213947 0.0196035 -1 -1 -1 -1 32 1927 19 6.89349e+06 253689 586450. 2029.24 0.99 0.101249 0.0880851 25474 144626 -1 1681 21 920 1495 107983 25474 2.89716 2.89716 -108.882 -2.89716 0 0 744469. 2576.02 0.04 0.07 0.08 -1 -1 0.04 0.0266531 0.0236216 96 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_087.v common 4.16 vpr 64.99 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29764 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66552 32 32 373 302 1 241 92 17 17 289 -1 unnamed_device 25.2 MiB 1.26 3226 1286 16652 5101 8812 2739 65.0 MiB 0.10 0.00 7.53678 5.6817 -168.121 -5.6817 5.6817 0.25 0.000349472 0.000320694 0.0296423 0.0271629 -1 -1 -1 -1 34 3248 37 6.89349e+06 394628 618332. 2139.56 1.48 0.155596 0.136385 25762 151098 -1 2485 23 1928 2763 231875 54095 4.63118 4.63118 -153.969 -4.63118 0 0 787024. 2723.27 0.03 0.06 0.08 -1 -1 0.03 0.0185313 0.0165548 156 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_088.v common 3.82 vpr 64.70 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29736 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 397 314 1 256 92 17 17 289 -1 unnamed_device 25.2 MiB 1.82 3241 1349 17066 5543 8987 2536 64.7 MiB 0.11 0.00 6.47017 5.4924 -173.425 -5.4924 5.4924 0.25 0.000365552 0.000330091 0.0320572 0.0293256 -1 -1 -1 -1 32 3371 24 6.89349e+06 394628 586450. 2029.24 0.49 0.0824342 0.0732588 25474 144626 -1 2591 21 1981 2792 182661 43773 4.46865 4.46865 -163.826 -4.46865 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.017704 0.0158097 166 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_089.v common 3.55 vpr 64.38 MiB -1 -1 0.13 17676 1 0.02 -1 -1 30172 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 269 231 1 172 82 17 17 289 -1 unnamed_device 24.9 MiB 1.01 1994 1069 14144 5297 7505 1342 64.4 MiB 0.07 0.00 4.47373 3.85823 -113.356 -3.85823 3.85823 0.25 0.000269263 0.000246111 0.0229361 0.0209552 -1 -1 -1 -1 26 2405 34 6.89349e+06 253689 503264. 1741.40 1.22 0.104104 0.090382 24322 120374 -1 2118 19 1267 1650 143777 33707 3.05266 3.05266 -112.136 -3.05266 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.012389 0.0110027 104 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_090.v common 3.15 vpr 64.09 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30312 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 31 32 245 205 1 153 85 17 17 289 -1 unnamed_device 24.6 MiB 0.82 2028 838 14407 3892 9360 1155 64.1 MiB 0.07 0.00 4.70033 3.85018 -114.048 -3.85018 3.85018 0.24 0.000258947 0.000237202 0.0224492 0.0205414 -1 -1 -1 -1 32 1902 23 6.89349e+06 310065 586450. 2029.24 1.05 0.117197 0.101976 25474 144626 -1 1656 20 933 1613 114014 26385 2.82486 2.82486 -106.443 -2.82486 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.01196 0.0105886 100 4 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_091.v common 3.10 vpr 64.52 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30000 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 24.9 MiB 1.32 2676 1136 9448 2110 6726 612 64.5 MiB 0.06 0.00 5.50572 4.64652 -147.013 -4.64652 4.64652 0.25 0.000337089 0.000309156 0.0178547 0.0163613 -1 -1 -1 -1 32 2903 23 6.89349e+06 338252 586450. 2029.24 0.41 0.0621535 0.0549096 25474 144626 -1 2275 18 1479 2130 167790 37316 3.63095 3.63095 -136.052 -3.63095 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145128 0.0129763 142 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_092.v common 4.39 vpr 64.57 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29816 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 356 289 1 223 90 17 17 289 -1 unnamed_device 24.9 MiB 1.43 2323 1112 13758 4906 6702 2150 64.6 MiB 0.08 0.00 5.68208 4.94624 -146.779 -4.94624 4.94624 0.25 0.000331787 0.000302979 0.0262302 0.0240273 -1 -1 -1 -1 38 2572 49 6.89349e+06 366440 678818. 2348.85 1.52 0.168236 0.146876 26626 170182 -1 2205 27 1686 2316 190689 61677 4.12995 4.12995 -139.314 -4.12995 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0196348 0.0174401 145 56 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_093.v common 2.83 vpr 64.91 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29788 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 32 32 349 260 1 204 101 17 17 289 -1 unnamed_device 24.9 MiB 0.51 2788 1276 12556 3435 8230 891 64.9 MiB 0.09 0.00 6.16499 5.16501 -145.808 -5.16501 5.16501 0.38 0.000394125 0.000363253 0.0265423 0.0244872 -1 -1 -1 -1 32 3172 25 6.89349e+06 521472 586450. 2029.24 0.72 0.0967584 0.0855786 25474 144626 -1 2570 21 1634 3205 242418 55454 4.33309 4.33309 -144.215 -4.33309 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0179264 0.0159944 158 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_094.v common 4.27 vpr 64.20 MiB -1 -1 0.17 18440 1 0.03 -1 -1 29780 -1 -1 28 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65736 30 32 316 264 1 208 90 17 17 289 -1 unnamed_device 25.2 MiB 1.21 2512 1137 8934 2329 5933 672 64.2 MiB 0.06 0.00 4.62558 3.87324 -113.147 -3.87324 3.87324 0.26 0.000430676 0.000404412 0.0194294 0.0180078 -1 -1 -1 -1 26 2997 43 6.89349e+06 394628 503264. 1741.40 1.64 0.141375 0.123852 24322 120374 -1 2387 26 1622 2422 199717 53667 3.36211 3.36211 -112.626 -3.36211 0 0 618332. 2139.56 0.02 0.06 0.07 -1 -1 0.02 0.0171514 0.0151399 133 52 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_095.v common 2.50 vpr 64.38 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30560 -1 -1 24 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 27 32 255 219 1 162 83 17 17 289 -1 unnamed_device 24.9 MiB 0.89 1709 895 11423 3598 6289 1536 64.4 MiB 0.06 0.00 5.37186 4.45989 -120.873 -4.45989 4.45989 0.25 0.000258494 0.000236562 0.0197284 0.0181083 -1 -1 -1 -1 32 1885 21 6.89349e+06 338252 586450. 2029.24 0.33 0.0533561 0.0470861 25474 144626 -1 1605 17 829 1207 77343 18883 3.505 3.505 -112.859 -3.505 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0110978 0.00988432 104 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_096.v common 5.27 vpr 65.19 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29756 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66756 32 32 421 327 1 271 95 17 17 289 -1 unnamed_device 25.2 MiB 1.78 3336 1650 16943 4550 10611 1782 65.2 MiB 0.17 0.00 5.75687 4.66636 -149.532 -4.66636 4.66636 0.28 0.000384059 0.000352114 0.0541153 0.0500458 -1 -1 -1 -1 32 4257 48 6.89349e+06 436909 586450. 2029.24 1.95 0.218959 0.193276 25474 144626 -1 3241 25 2181 3435 276689 69635 4.34439 4.34439 -149.479 -4.34439 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0212911 0.0189332 181 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_097.v common 3.79 vpr 64.60 MiB -1 -1 0.15 18060 1 0.03 -1 -1 30148 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 31 32 365 296 1 233 89 17 17 289 -1 unnamed_device 24.9 MiB 1.40 2877 1253 10781 3020 6724 1037 64.6 MiB 0.07 0.00 6.6941 5.817 -167.929 -5.817 5.817 0.25 0.000354766 0.00032589 0.0218487 0.0201788 -1 -1 -1 -1 30 2956 23 6.89349e+06 366440 556674. 1926.21 1.02 0.112557 0.0989778 25186 138497 -1 2341 19 1649 2421 144006 35330 4.38675 4.38675 -149.789 -4.38675 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0154389 0.0138086 151 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_098.v common 3.96 vpr 63.84 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29908 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65376 32 32 331 280 1 221 87 17 17 289 -1 unnamed_device 24.9 MiB 1.25 2547 1197 9303 2202 6355 746 63.8 MiB 0.06 0.00 5.09387 4.28945 -141.157 -4.28945 4.28945 0.25 0.00042315 0.000395805 0.019167 0.0177577 -1 -1 -1 -1 28 3036 35 6.89349e+06 324158 531479. 1839.03 1.34 0.126513 0.110677 24610 126494 -1 2512 25 1803 2385 195350 47064 4.2519 4.2519 -146.428 -4.2519 0 0 648988. 2245.63 0.03 0.07 0.07 -1 -1 0.03 0.0238407 0.021067 132 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_099.v common 3.83 vpr 64.82 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29904 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 32 32 326 263 1 203 88 17 17 289 -1 unnamed_device 25.0 MiB 1.30 2319 1186 11593 3417 7038 1138 64.8 MiB 0.07 0.00 6.11951 5.26542 -147.058 -5.26542 5.26542 0.24 0.000321945 0.000295215 0.0228394 0.0210531 -1 -1 -1 -1 30 2530 20 6.89349e+06 338252 556674. 1926.21 1.15 0.135844 0.118798 25186 138497 -1 2079 20 1172 1728 106041 25591 3.68526 3.68526 -129.365 -3.68526 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0173921 0.0156473 131 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_100.v common 3.69 vpr 65.00 MiB -1 -1 0.13 18064 1 0.03 -1 -1 30232 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 31 32 373 294 1 231 91 17 17 289 -1 unnamed_device 25.1 MiB 1.27 2701 1254 13759 3627 8626 1506 65.0 MiB 0.08 0.00 5.36757 4.57215 -129.401 -4.57215 4.57215 0.24 0.000371097 0.000341499 0.0274086 0.0252012 -1 -1 -1 -1 32 2893 23 6.89349e+06 394628 586450. 2029.24 1.04 0.127297 0.11159 25474 144626 -1 2390 20 1697 2539 165581 39636 3.8238 3.8238 -127.582 -3.8238 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0171484 0.0153377 158 50 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_101.v common 3.88 vpr 64.89 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29868 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66444 30 32 325 268 1 210 89 17 17 289 -1 unnamed_device 24.9 MiB 1.36 2500 1222 15731 4428 8998 2305 64.9 MiB 0.09 0.00 5.01568 4.37438 -123.571 -4.37438 4.37438 0.24 0.000307761 0.000281755 0.0263716 0.0241537 -1 -1 -1 -1 34 2819 30 6.89349e+06 380534 618332. 2139.56 1.15 0.118553 0.103653 25762 151098 -1 2471 19 1223 1977 156412 35023 3.48615 3.48615 -117.196 -3.48615 0 0 787024. 2723.27 0.03 0.05 0.09 -1 -1 0.03 0.0169984 0.0150589 134 51 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_102.v common 4.61 vpr 64.93 MiB -1 -1 0.20 18056 1 0.03 -1 -1 29764 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 25.5 MiB 1.70 2913 1236 16468 4324 10879 1265 64.9 MiB 0.10 0.00 5.92998 4.92758 -154.078 -4.92758 4.92758 0.24 0.000375636 0.000345494 0.0296261 0.0271151 -1 -1 -1 -1 32 3235 49 6.89349e+06 338252 586450. 2029.24 1.34 0.160502 0.140912 25474 144626 -1 2641 21 1807 2827 217818 50476 3.81776 3.81776 -142.241 -3.81776 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0167762 0.0149719 143 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_103.v common 4.98 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29592 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 32 32 386 307 1 246 93 17 17 289 -1 unnamed_device 25.2 MiB 1.63 2578 1265 14583 4645 6831 3107 65.0 MiB 0.08 0.00 4.8916 4.45823 -142.35 -4.45823 4.45823 0.24 0.000360905 0.000330749 0.0267126 0.0244643 -1 -1 -1 -1 36 3322 50 6.89349e+06 408721 648988. 2245.63 1.94 0.173141 0.15178 26050 158493 -1 2430 26 2202 3086 217671 55907 3.43671 3.43671 -127.871 -3.43671 0 0 828058. 2865.25 0.03 0.08 0.08 -1 -1 0.03 0.0275492 0.0245357 160 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_104.v common 2.65 vpr 64.39 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29828 -1 -1 22 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 29 32 269 229 1 173 83 17 17 289 -1 unnamed_device 24.9 MiB 0.87 1941 905 12863 3695 7288 1880 64.4 MiB 0.06 0.00 4.94313 4.20923 -126.338 -4.20923 4.20923 0.28 0.000269427 0.000245811 0.0208088 0.0190655 -1 -1 -1 -1 32 1947 26 6.89349e+06 310065 586450. 2029.24 0.38 0.0634184 0.0559623 25474 144626 -1 1640 18 1223 1625 105232 25124 3.02451 3.02451 -110.783 -3.02451 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0116555 0.0103855 108 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_105.v common 3.55 vpr 64.53 MiB -1 -1 0.11 18440 1 0.02 -1 -1 30308 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 310 266 1 198 85 17 17 289 -1 unnamed_device 24.9 MiB 1.00 2331 1018 14593 5365 7180 2048 64.5 MiB 0.07 0.00 5.35099 4.29493 -129.187 -4.29493 4.29493 0.24 0.000296307 0.000271021 0.0248078 0.0226923 -1 -1 -1 -1 34 2466 24 6.89349e+06 295971 618332. 2139.56 1.15 0.108741 0.0947769 25762 151098 -1 1986 19 1370 1939 133873 32096 3.832 3.832 -129.652 -3.832 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0135162 0.0120723 121 58 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_106.v common 3.39 vpr 64.43 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30268 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65980 31 32 326 261 1 204 89 17 17 289 -1 unnamed_device 24.9 MiB 0.97 2471 1196 14741 4167 8661 1913 64.4 MiB 0.08 0.00 5.98928 4.87948 -139.23 -4.87948 4.87948 0.24 0.000320063 0.000293836 0.024991 0.0228928 -1 -1 -1 -1 26 2979 26 6.89349e+06 366440 503264. 1741.40 1.07 0.104685 0.0918426 24322 120374 -1 2528 23 1727 2832 223076 51486 3.8639 3.8639 -135.445 -3.8639 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0164645 0.0146522 134 33 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_107.v common 3.77 vpr 63.91 MiB -1 -1 0.12 17672 1 0.03 -1 -1 29900 -1 -1 22 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65440 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 24.8 MiB 1.12 2013 926 8543 2203 5453 887 63.9 MiB 0.04 0.00 5.29312 4.18332 -115.535 -4.18332 4.18332 0.26 0.000268815 0.00024715 0.0138272 0.0126803 -1 -1 -1 -1 26 2277 48 6.89349e+06 310065 503264. 1741.40 1.30 0.100987 0.0875584 24322 120374 -1 2031 27 1546 2031 172833 51950 3.3714 3.3714 -109.468 -3.3714 0 0 618332. 2139.56 0.02 0.05 0.06 -1 -1 0.02 0.0154285 0.0135584 105 31 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_108.v common 3.52 vpr 63.93 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29880 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65460 32 32 278 238 1 182 84 17 17 289 -1 unnamed_device 24.7 MiB 1.16 2123 1039 14358 3958 8394 2006 63.9 MiB 0.07 0.00 5.08457 4.36857 -137.465 -4.36857 4.36857 0.24 0.000278263 0.000254499 0.0233188 0.021363 -1 -1 -1 -1 30 2385 23 6.89349e+06 281877 556674. 1926.21 1.07 0.109577 0.0957306 25186 138497 -1 2017 21 1374 2007 134054 31869 3.07751 3.07751 -120.896 -3.07751 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0134373 0.0119178 109 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_109.v common 3.60 vpr 65.00 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29840 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 31 32 373 300 1 237 92 17 17 289 -1 unnamed_device 25.6 MiB 1.50 2847 1321 9407 2126 6476 805 65.0 MiB 0.06 0.00 5.94996 4.99396 -156.415 -4.99396 4.99396 0.24 0.000346762 0.00031781 0.0173071 0.0158311 -1 -1 -1 -1 28 3256 26 6.89349e+06 408721 531479. 1839.03 0.66 0.0811964 0.0718657 24610 126494 -1 2728 22 2029 2815 203521 48201 3.81684 3.81684 -144.87 -3.81684 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0174056 0.0154965 157 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_110.v common 3.81 vpr 63.98 MiB -1 -1 0.18 18056 1 0.03 -1 -1 29852 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65512 31 32 265 230 1 175 83 17 17 289 -1 unnamed_device 24.9 MiB 1.23 1998 822 6203 1282 4444 477 64.0 MiB 0.04 0.00 4.0554 3.59765 -110.566 -3.59765 3.59765 0.26 0.000325594 0.000302519 0.0132653 0.0122948 -1 -1 -1 -1 34 2076 24 6.89349e+06 281877 618332. 2139.56 1.12 0.115819 0.100786 25762 151098 -1 1723 20 1130 1580 102110 25750 2.82336 2.82336 -104.389 -2.82336 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0126467 0.0112452 103 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_111.v common 3.63 vpr 64.95 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30136 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 32 32 349 286 1 221 88 17 17 289 -1 unnamed_device 24.9 MiB 1.25 2652 1326 9253 2409 6050 794 64.9 MiB 0.07 0.00 4.83964 4.21314 -126.908 -4.21314 4.21314 0.26 0.000335167 0.000307637 0.02296 0.0211984 -1 -1 -1 -1 32 2832 23 6.89349e+06 338252 586450. 2029.24 1.03 0.113834 0.099746 25474 144626 -1 2356 20 1336 1987 129392 30987 3.4009 3.4009 -123.821 -3.4009 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0155457 0.0138799 141 57 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_112.v common 4.76 vpr 64.70 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29572 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 31 32 396 325 1 259 94 17 17 289 -1 unnamed_device 25.2 MiB 1.76 2853 1403 14578 4264 8207 2107 64.7 MiB 0.10 0.00 5.59288 4.8279 -156.525 -4.8279 4.8279 0.26 0.000369837 0.000335668 0.0333882 0.0308902 -1 -1 -1 -1 30 3242 26 6.89349e+06 436909 556674. 1926.21 1.56 0.142469 0.12585 25186 138497 -1 2649 19 1916 2730 173100 41045 4.05069 4.05069 -152.083 -4.05069 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0168232 0.0150458 168 91 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_113.v common 3.26 vpr 64.76 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29756 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 303 262 1 200 86 17 17 289 -1 unnamed_device 24.9 MiB 1.33 2386 1003 8213 1905 5885 423 64.8 MiB 0.07 0.00 5.08019 3.80489 -115.807 -3.80489 3.80489 0.25 0.000384058 0.000353865 0.0240162 0.0223341 -1 -1 -1 -1 26 2751 41 6.89349e+06 310065 503264. 1741.40 0.56 0.0757766 0.067046 24322 120374 -1 2325 35 2024 2740 201705 49859 3.37141 3.37141 -124.682 -3.37141 0 0 618332. 2139.56 0.03 0.07 0.07 -1 -1 0.03 0.0273323 0.0239382 121 57 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 3.46 vpr 63.79 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30148 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65324 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 24.6 MiB 0.81 2269 837 15023 5167 6942 2914 63.8 MiB 0.08 0.00 5.43847 4.34657 -130.295 -4.34657 4.34657 0.24 0.000423514 0.000388067 0.0296063 0.0270771 -1 -1 -1 -1 36 2125 20 6.89349e+06 267783 648988. 2245.63 1.29 0.13798 0.120975 26050 158493 -1 1708 21 1250 1889 158472 38821 3.16246 3.16246 -117.696 -3.16246 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0138878 0.0123302 111 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_115.v common 3.92 vpr 64.39 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29808 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 318 257 1 197 87 17 17 289 -1 unnamed_device 24.9 MiB 1.51 2206 1061 15255 5362 7838 2055 64.4 MiB 0.12 0.00 5.66222 4.93863 -135.261 -4.93863 4.93863 0.38 0.000465778 0.000424965 0.0394743 0.0360442 -1 -1 -1 -1 32 2576 20 6.89349e+06 324158 586450. 2029.24 0.55 0.10291 0.0916188 25474 144626 -1 2067 20 1241 1762 109322 26595 3.75376 3.75376 -127.245 -3.75376 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.014591 0.0129818 130 30 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_116.v common 2.99 vpr 64.83 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30232 -1 -1 28 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 29 32 324 268 1 205 89 17 17 289 -1 unnamed_device 25.2 MiB 1.21 2470 1190 15335 4895 8484 1956 64.8 MiB 0.12 0.00 4.7462 4.04278 -114.91 -4.04278 4.04278 0.25 0.000470059 0.000430443 0.0387134 0.0355344 -1 -1 -1 -1 32 2572 19 6.89349e+06 394628 586450. 2029.24 0.37 0.0791568 0.070506 25474 144626 -1 2079 21 1060 1535 114324 26106 3.1022 3.1022 -107.005 -3.1022 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0151094 0.0134471 136 55 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_117.v common 3.77 vpr 65.06 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29764 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66620 32 32 393 312 1 243 90 17 17 289 -1 unnamed_device 25.2 MiB 1.77 2982 1296 15567 4292 8859 2416 65.1 MiB 0.11 0.00 6.82244 5.69986 -179.713 -5.69986 5.69986 0.26 0.000519859 0.000488808 0.0338423 0.0310508 -1 -1 -1 -1 32 3149 23 6.89349e+06 366440 586450. 2029.24 0.50 0.0977618 0.086857 25474 144626 -1 2680 23 2091 3202 214974 51581 4.45265 4.45265 -163.975 -4.45265 0 0 744469. 2576.02 0.03 0.06 0.11 -1 -1 0.03 0.0183996 0.016371 162 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_118.v common 3.84 vpr 64.24 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29940 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 24.9 MiB 1.21 1779 858 10231 2722 6503 1006 64.2 MiB 0.07 0.00 3.8889 3.28224 -101.713 -3.28224 3.28224 0.45 0.000385879 0.000354379 0.0241506 0.0220973 -1 -1 -1 -1 30 1861 20 6.89349e+06 253689 556674. 1926.21 0.74 0.0892488 0.0792797 25186 138497 -1 1517 18 846 1343 70273 18201 2.62851 2.62851 -97.2865 -2.62851 0 0 706193. 2443.58 0.04 0.04 0.11 -1 -1 0.04 0.0159301 0.0141792 93 4 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 7.04 vpr 65.12 MiB -1 -1 0.16 18680 1 0.03 -1 -1 30100 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66684 32 32 412 334 1 269 95 17 17 289 -1 unnamed_device 25.6 MiB 2.35 3112 1429 7871 1651 5611 609 65.1 MiB 0.06 0.00 7.06988 5.66654 -175.904 -5.66654 5.66654 0.34 0.000375537 0.000339759 0.0156753 0.0143834 -1 -1 -1 -1 24 4306 40 6.89349e+06 436909 470940. 1629.55 3.01 0.164231 0.144271 24034 113901 -1 3379 35 3463 4537 442158 133615 5.55244 5.55244 -193.596 -5.55244 0 0 586450. 2029.24 0.02 0.11 0.06 -1 -1 0.02 0.0262324 0.0232024 172 90 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 3.77 vpr 65.05 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30196 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 376 318 1 259 91 17 17 289 -1 unnamed_device 25.2 MiB 1.60 2995 1457 17227 5058 10064 2105 65.1 MiB 0.20 0.00 6.59283 5.06664 -170.928 -5.06664 5.06664 0.28 0.00033737 0.000308852 0.0723416 0.0671243 -1 -1 -1 -1 32 3389 24 6.89349e+06 380534 586450. 2029.24 0.53 0.118774 0.107591 25474 144626 -1 2826 20 2173 2713 238525 51366 4.42408 4.42408 -166.095 -4.42408 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0158806 0.0141647 154 96 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 4.46 vpr 64.99 MiB -1 -1 0.16 18056 1 0.04 -1 -1 30148 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66548 32 32 360 293 1 226 90 17 17 289 -1 unnamed_device 24.9 MiB 1.76 2575 1188 14361 4167 7345 2849 65.0 MiB 0.14 0.00 4.49365 4.14004 -127.133 -4.14004 4.14004 0.44 0.000619044 0.000567785 0.0472235 0.0432217 -1 -1 -1 -1 32 2842 27 6.89349e+06 366440 586450. 2029.24 0.75 0.140806 0.125491 25474 144626 -1 2167 18 1381 1988 128583 31532 3.26765 3.26765 -116.85 -3.26765 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0154305 0.0137976 147 60 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 4.23 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29792 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 396 299 1 240 91 17 17 289 -1 unnamed_device 25.2 MiB 1.61 2868 1421 16615 5234 8988 2393 65.1 MiB 0.10 0.00 6.7782 5.7937 -174.554 -5.7937 5.7937 0.24 0.000377195 0.000345698 0.0328161 0.0301431 -1 -1 -1 -1 32 3522 22 6.89349e+06 380534 586450. 2029.24 1.21 0.139004 0.122484 25474 144626 -1 2816 20 1940 3057 243941 59443 4.77005 4.77005 -160.085 -4.77005 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0206995 0.0185208 167 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 2.39 vpr 63.83 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30220 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65364 30 32 224 207 1 138 79 17 17 289 -1 unnamed_device 24.9 MiB 0.67 1877 553 12416 4327 6159 1930 63.8 MiB 0.05 0.00 3.67846 3.05196 -89.5454 -3.05196 3.05196 0.24 0.000240967 0.000220771 0.0184976 0.0169233 -1 -1 -1 -1 32 1600 50 6.89349e+06 239595 586450. 2029.24 0.41 0.0589787 0.0516028 25474 144626 -1 1097 15 520 670 46236 12957 2.13076 2.13076 -83.1557 -2.13076 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00913946 0.00819187 79 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 2.61 vpr 64.39 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29772 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 30 32 286 239 1 176 85 17 17 289 -1 unnamed_device 25.0 MiB 0.95 1847 961 11617 2788 7841 988 64.4 MiB 0.06 0.00 5.09505 4.48403 -138.191 -4.48403 4.48403 0.24 0.000279345 0.000255614 0.018968 0.0173529 -1 -1 -1 -1 32 1983 22 6.89349e+06 324158 586450. 2029.24 0.36 0.0566188 0.0499704 25474 144626 -1 1730 24 1374 2089 138709 33546 3.26135 3.26135 -120.882 -3.26135 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0151238 0.0133003 120 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 3.15 vpr 64.11 MiB -1 -1 0.12 18064 1 0.02 -1 -1 30120 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65644 32 32 296 247 1 187 86 17 17 289 -1 unnamed_device 24.9 MiB 1.47 2379 1099 6512 1400 4709 403 64.1 MiB 0.04 0.00 5.39489 4.40387 -142.112 -4.40387 4.40387 0.24 0.000297099 0.000272253 0.0116876 0.0106979 -1 -1 -1 -1 32 2461 22 6.89349e+06 310065 586450. 2029.24 0.38 0.049722 0.04369 25474 144626 -1 2000 16 1036 1938 114017 27700 3.4032 3.4032 -130.786 -3.4032 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0118866 0.0106258 117 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 2.54 vpr 64.23 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29744 -1 -1 22 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65776 25 32 216 194 1 138 79 17 17 289 -1 unnamed_device 24.9 MiB 0.81 1444 623 8698 3045 3646 2007 64.2 MiB 0.04 0.00 4.2673 3.669 -85.1281 -3.669 3.669 0.24 0.000223849 0.000204642 0.0128618 0.011782 -1 -1 -1 -1 34 1477 40 6.89349e+06 310065 618332. 2139.56 0.48 0.0554996 0.0482709 25762 151098 -1 1167 17 675 1007 65080 17606 2.74431 2.74431 -76.9396 -2.74431 0 0 787024. 2723.27 0.03 0.02 0.08 -1 -1 0.03 0.00963225 0.00859939 88 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 4.70 vpr 64.68 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30176 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66232 32 32 376 307 1 242 90 17 17 289 -1 unnamed_device 25.2 MiB 1.91 3246 1394 13155 3589 8227 1339 64.7 MiB 0.10 0.00 5.69179 4.38685 -135.96 -4.38685 4.38685 0.27 0.00035587 0.000326364 0.0317988 0.0292838 -1 -1 -1 -1 28 3647 48 6.89349e+06 366440 531479. 1839.03 1.37 0.175343 0.154197 24610 126494 -1 2835 24 2070 3115 222959 51695 3.94436 3.94436 -138.765 -3.94436 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0182264 0.0161589 155 72 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 3.95 vpr 64.75 MiB -1 -1 0.21 18056 1 0.03 -1 -1 29792 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 31 32 409 331 1 264 96 17 17 289 -1 unnamed_device 25.2 MiB 1.66 3421 1405 9951 2248 6876 827 64.8 MiB 0.07 0.00 6.59166 4.95446 -159.482 -4.95446 4.95446 0.26 0.000368094 0.000337513 0.0186641 0.0170676 -1 -1 -1 -1 26 4013 41 6.89349e+06 465097 503264. 1741.40 0.83 0.0913258 0.0808566 24322 120374 -1 3056 21 2358 3239 221980 53983 4.35939 4.35939 -160.133 -4.35939 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0179468 0.0160232 174 90 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt index 2aa73474bd1..d3a8f8c6f9c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 346.85 vpr 1.15 GiB -1 -1 34.22 328308 27 15.05 -1 -1 138296 -1 -1 6514 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1202304 641 128 52026 52154 1 22211 7283 96 96 9216 clb auto 299.9 MiB 22.55 298865 9039475 3705368 5259409 74698 1174.1 MiB 99.58 0.80 15.6652 -38327.4 -15.6652 15.6652 30.26 0.094057 0.0773765 12.1503 10.1571 -1 -1 -1 -1 52 436843 31 2.87242e+08 7.85314e+07 3.22264e+07 3496.79 84.03 34.4054 28.6501 876764 7891077 -1 405234 17 92350 208771 15162225 3092956 14.5295 14.5295 -35310.2 -14.5295 0 0 3.95636e+07 4292.92 2.28 8.25 6.87 -1 -1 2.28 3.81485 3.27893 44137 14777 -1 -1 -1 -1 - k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 4.27 vpr 64.04 MiB -1 -1 0.87 26712 11 0.25 -1 -1 33516 -1 -1 51 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65580 54 51 461 512 1 281 156 11 11 121 clb auto 24.7 MiB 0.16 2356 11469 1919 8714 836 64.0 MiB 0.12 0.00 5.64506 -244.834 -5.64506 5.64506 0.13 0.00146196 0.00133342 0.0458162 0.0422569 -1 -1 -1 -1 48 5066 26 2.09946e+06 614805 317060. 2620.33 1.31 0.36651 0.319953 10252 71876 -1 4625 16 1697 8023 407060 95904 5.13857 5.13857 -230.591 -5.13857 0 0 382250. 3159.09 0.01 0.15 0.06 -1 -1 0.01 0.0499744 0.0448408 351 351 -1 -1 -1 -1 - k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 399.84 vpr 1.07 GiB -1 -1 21.81 218380 1 3.70 -1 -1 145176 -1 -1 5511 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1117152 641 128 55563 47815 1 19087 6280 89 89 7921 clb auto 300.2 MiB 18.05 230047 8461724 3459022 4875110 127592 1091.0 MiB 204.82 1.70 7.09259 -24894.9 -7.09259 7.09259 27.46 0.0722137 0.0620773 11.1205 9.22983 -1 -1 -1 -1 66 309563 40 2.46893e+08 6.92128e+07 3.31523e+07 4185.37 68.55 29.6499 24.5503 846610 8512169 -1 289933 30 70505 114345 10785585 2091912 4.98188 4.98188 -21717.1 -4.98188 0 0 4.13768e+07 5223.69 2.61 7.93 7.55 -1 -1 2.61 4.60052 3.86111 40340 2050 -1 -1 -1 -1 - k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.46 vpr 64.67 MiB -1 -1 0.88 25784 4 0.13 -1 -1 33088 -1 -1 47 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66224 54 51 503 502 1 293 152 10 10 100 clb auto 25.4 MiB 1.53 2207 8657 1268 6725 664 64.7 MiB 0.12 0.00 4.72142 -243.243 -4.72142 4.72142 0.10 0.00138683 0.00126889 0.0371909 0.0344533 -1 -1 -1 -1 44 4688 46 1.94278e+06 590226 231289. 2312.89 1.36 0.376354 0.326721 8470 54129 -1 4028 17 1662 7146 368098 92041 3.78868 3.78868 -208.146 -3.78868 0 0 291571. 2915.71 0.01 0.14 0.05 -1 -1 0.01 0.0559049 0.0498459 310 281 -1 -1 -1 -1 - k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 415.20 vpr 1.04 GiB -1 -1 21.75 218308 1 4.05 -1 -1 145180 -1 -1 5620 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1088640 641 128 55563 47815 1 19638 6389 89 89 7921 clb auto 308.1 MiB 52.99 226704 9072863 3788850 5116203 167810 1063.1 MiB 189.74 1.45 7.32093 -25503.3 -7.32093 7.32093 27.00 0.0695794 0.0596563 11.1854 9.32085 -1 -1 -1 -1 62 301435 41 2.47551e+08 7.12563e+07 3.13221e+07 3954.32 64.63 30.1669 25.0298 822850 7925305 -1 280695 33 74632 110486 9460418 1906659 4.74051 4.74051 -21753 -4.74051 0 0 3.86383e+07 4877.96 2.36 8.35 6.62 -1 -1 2.36 5.11529 4.30965 40780 2050 -1 -1 -1 -1 - k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.14 vpr 64.61 MiB -1 -1 0.49 25988 4 0.16 -1 -1 33144 -1 -1 50 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66164 54 51 503 502 1 302 155 11 11 121 clb auto 25.5 MiB 0.55 2264 11803 2091 8793 919 64.6 MiB 0.15 0.01 4.6074 -231.734 -4.6074 4.6074 0.13 0.00143538 0.00131584 0.0463156 0.0428406 -1 -1 -1 -1 46 4761 36 2.13871e+06 633900 304223. 2514.24 1.58 0.37716 0.328993 10384 69934 -1 4032 15 1433 6356 300467 73316 3.80829 3.80829 -202.73 -3.80829 0 0 371547. 3070.64 0.01 0.12 0.06 -1 -1 0.01 0.0507242 0.0453634 307 281 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 285.87 vpr 1.07 GiB -1 -1 21.15 328044 27 17.19 -1 -1 136772 -1 -1 6530 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1127196 641 128 52026 52154 1 22146 7299 96 96 9216 clb auto 332.2 MiB 15.82 1 293360 9065987 3711370 5281819 72798 1100.8 MiB 87.32 0.64 63.9835 15.6932 -38098.7 -15.6932 15.6932 27.45 0.0673124 0.0602963 10.1706 8.43326 -1 -1 -1 -1 52 432440 35 2.87242e+08 7.87243e+07 3.22264e+07 3496.79 70.10 28.8986 24.6513 876764 7891077 -1 399137 17 95401 216864 15038479 3106649 13.6903 13.6903 -35069.4 -13.6903 0 0 3.95636e+07 4292.92 2.24 7.32 5.18 -1 -1 2.24 3.2763 2.91469 44106 14777 -1 -1 -1 -1 +k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 2.47 vpr 65.25 MiB -1 -1 0.45 26432 11 0.21 -1 -1 33212 -1 -1 50 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66820 54 51 461 512 1 279 155 11 11 121 clb auto 26.2 MiB 0.08 3521 2357 11387 1976 8700 711 65.3 MiB 0.07 0.00 6.1966 5.68811 -245.341 -5.68811 5.68811 0.09 0.000716615 0.0006463 0.0243569 0.0221714 -1 -1 -1 -1 46 5194 30 2.09946e+06 602750 304223. 2514.24 0.73 0.182335 0.162552 10132 69752 -1 4547 19 1747 8058 386967 94105 5.17977 5.17977 -229.771 -5.17977 0 0 371547. 3070.64 0.01 0.10 0.04 -1 -1 0.01 0.0385667 0.0352693 351 351 -1 -1 -1 -1 +k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 339.81 vpr 953.70 MiB -1 -1 13.28 218372 1 3.24 -1 -1 144528 -1 -1 5506 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 976588 641 128 55563 47815 1 19075 6275 89 89 7921 clb auto 330.3 MiB 10.44 1 214102 8568519 3563555 4885647 119317 953.7 MiB 169.32 1.12 17.4207 6.98821 -24570.4 -6.98821 6.98821 25.47 0.0471077 0.041108 9.13248 7.51499 -1 -1 -1 -1 64 294624 49 2.46893e+08 6.915e+07 3.22737e+07 4074.44 78.53 27.676 23.1791 838690 8307980 -1 274225 28 72425 118832 10979794 2166804 4.60329 4.60329 -21219.4 -4.60329 0 0 4.04365e+07 5104.97 2.30 5.71 5.61 -1 -1 2.30 2.97998 2.59225 40344 2050 -1 -1 -1 -1 +k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 4.44 vpr 65.57 MiB -1 -1 0.41 25348 4 0.13 -1 -1 32876 -1 -1 48 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67144 54 51 503 502 1 293 153 10 10 100 clb auto 26.7 MiB 1.29 3063 2216 11196 1953 8114 1129 65.6 MiB 0.14 0.01 5.24197 4.75513 -244.6 -4.75513 4.75513 0.09 0.00169788 0.00158536 0.0530931 0.0496201 -1 -1 -1 -1 50 4239 34 1.94278e+06 602784 264954. 2649.54 1.48 0.359688 0.32242 8770 59529 -1 3822 16 1455 6320 297317 74232 3.99954 3.99954 -212.879 -3.99954 0 0 317040. 3170.40 0.01 0.18 0.04 -1 -1 0.01 0.0756285 0.0693569 310 281 -1 -1 -1 -1 +k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 357.91 vpr 981.56 MiB -1 -1 12.96 218396 1 4.88 -1 -1 144524 -1 -1 5615 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1005120 641 128 55563 47815 1 19621 6384 89 89 7921 clb auto 336.8 MiB 44.88 1 218506 8826737 3646134 5035828 144775 981.6 MiB 155.92 1.22 19.4565 7.31966 -25233.7 -7.31966 7.31966 24.82 0.0474495 0.0415552 8.20397 6.77827 -1 -1 -1 -1 60 294604 45 2.47551e+08 7.11929e+07 3.04132e+07 3839.56 73.27 27.1474 22.801 814930 7734163 -1 276739 33 78983 115921 10759440 2250313 4.51897 4.51897 -21514.2 -4.51897 0 0 3.78426e+07 4777.50 2.27 6.83 4.86 -1 -1 2.27 3.77776 3.25281 40785 2050 -1 -1 -1 -1 +k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 3.71 vpr 65.89 MiB -1 -1 0.41 25352 4 0.13 -1 -1 32860 -1 -1 49 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67476 54 51 503 502 1 301 154 11 11 121 clb auto 26.8 MiB 0.37 3371 2219 12102 2212 9004 886 65.9 MiB 0.08 0.00 5.48793 4.4172 -224.447 -4.4172 4.4172 0.09 0.000674884 0.000607414 0.0249059 0.0227895 -1 -1 -1 -1 46 4716 45 2.13871e+06 621222 304223. 2514.24 1.64 0.233573 0.207329 10384 69934 -1 3942 18 1779 7182 348702 84785 3.54243 3.54243 -193.203 -3.54243 0 0 371547. 3070.64 0.01 0.09 0.04 -1 -1 0.01 0.0361351 0.0331666 307 281 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt index e0e23492818..10684a36519 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt @@ -1,11 +1,11 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_2ripple_N8_22nm.xml Md5Core.v common 541.33 vpr 770.48 MiB -1 -1 21.57 219052 1 3.94 -1 -1 145160 -1 -1 2904 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 788976 641 128 55563 47815 1 17837 3673 65 65 4225 clb auto 278.4 MiB 280.64 186842 4139415 1628153 2426823 84439 770.5 MiB 80.11 0.65 6.85172 -24425.5 -6.85172 6.85172 17.37 0.0707807 0.0606116 10.8556 9.00171 -1 -1 -1 -1 86 266896 42 1.34217e+08 4.20381e+07 2.31978e+07 5490.61 95.85 37.0767 30.5473 551762 6310377 -1 239670 19 85960 107325 12022295 2121435 5.37037 5.37037 -22498.9 -5.37037 0 0 2.90884e+07 6884.83 1.53 5.92 5.28 -1 -1 1.53 3.24584 2.77988 21038 2050 -1 -1 -1 -1 - k6_frac_2ripple_N8_22nm.xml cordic.v common 7.58 vpr 65.10 MiB -1 -1 0.88 26100 4 0.16 -1 -1 33024 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66664 54 51 503 502 1 316 138 9 9 81 clb auto 26.1 MiB 3.78 1956 11174 2060 8307 807 65.1 MiB 0.13 0.00 4.40854 -233.833 -4.40854 4.40854 0.09 0.00139097 0.00128641 0.0504025 0.0467374 -1 -1 -1 -1 56 4041 27 1.45065e+06 477698 231774. 2861.41 1.17 0.353028 0.308187 7704 54090 -1 3517 18 1771 6187 313268 82102 4.02896 4.02896 -216.237 -4.02896 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0573414 0.0511544 225 281 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml Md5Core.v common 445.49 vpr 768.55 MiB -1 -1 21.93 218372 1 4.17 -1 -1 145216 -1 -1 2904 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 787000 641 128 55563 47815 1 17906 3673 65 65 4225 clb auto 273.5 MiB 187.96 185308 3941126 1565098 2300167 75861 768.6 MiB 89.53 0.80 6.8947 -23916.3 -6.8947 6.8947 17.72 0.0715102 0.0611769 10.6329 8.87437 -1 -1 -1 -1 86 262207 37 1.34928e+08 4.2735e+07 2.31978e+07 5490.61 81.66 34.9922 28.9773 551762 6310377 -1 236506 17 80887 101963 10950479 1939027 5.59715 5.59715 -21989.7 -5.59715 0 0 2.90884e+07 6884.83 1.64 5.62 5.31 -1 -1 1.64 3.04009 2.59505 20989 2050 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml cordic.v common 5.96 vpr 64.87 MiB -1 -1 0.87 26208 4 0.16 -1 -1 33076 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66424 54 51 503 502 1 318 138 9 9 81 clb auto 25.9 MiB 0.40 1964 10462 1843 7559 1060 64.9 MiB 0.13 0.00 4.28518 -225.617 -4.28518 4.28518 0.09 0.00139646 0.00129195 0.0476616 0.0441834 -1 -1 -1 -1 56 4128 31 1.45905e+06 485618 231774. 2861.41 2.57 0.547183 0.474234 7704 54090 -1 3583 18 1731 6262 331465 85566 3.8968 3.8968 -212.026 -3.8968 0 0 286113. 3532.26 0.01 0.14 0.05 -1 -1 0.01 0.058103 0.0518196 225 281 -1 -1 -1 -1 - k6_frac_N8_22nm.xml Md5Core.v common 523.72 vpr 809.32 MiB -1 -1 35.88 328152 27 14.52 -1 -1 138636 -1 -1 3446 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 828744 641 128 52026 52154 1 22420 4215 70 70 4900 clb auto 269.8 MiB 211.66 265423 4326406 1648229 2614689 63488 809.3 MiB 79.80 0.65 14.952 -39387.3 -14.952 14.952 20.28 0.0925834 0.0810563 12.6496 10.7217 -1 -1 -1 -1 84 394620 43 1.54829e+08 4.64245e+07 2.64571e+07 5399.40 108.95 44.8309 37.5465 624050 7235563 -1 356794 20 108067 230531 16879775 3154299 13.0725 13.0725 -36269.1 -13.0725 0 0 3.34846e+07 6833.59 1.94 9.36 5.72 -1 -1 1.94 4.65498 4.01829 24663 14777 -1 -1 -1 -1 - k6_frac_N8_22nm.xml cordic.v common 4.95 vpr 64.28 MiB -1 -1 0.95 26424 11 0.25 -1 -1 33660 -1 -1 34 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65824 54 51 461 512 1 317 139 9 9 81 clb auto 25.0 MiB 0.23 2204 9473 1828 7093 552 64.3 MiB 0.12 0.00 6.42199 -256.014 -6.42199 6.42199 0.09 0.00144714 0.00133734 0.0443724 0.0410787 -1 -1 -1 -1 62 4693 48 1.41552e+06 458048 249781. 3083.72 1.55 0.41392 0.360399 7884 59488 -1 3923 19 2092 8192 403186 97926 5.39904 5.39904 -231.32 -5.39904 0 0 310465. 3832.90 0.01 0.10 0.04 -1 -1 0.01 0.0365187 0.0331706 252 351 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml Md5Core.v common 968.02 vpr 871.61 MiB -1 -1 22.34 218328 1 3.90 -1 -1 145312 -1 -1 3580 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 892524 641 128 55563 47815 1 19465 4349 71 71 5041 clb auto 262.5 MiB 670.29 210279 5114045 1917429 3043210 153406 871.6 MiB 143.83 0.80 7.61884 -24559.3 -7.61884 7.61884 21.38 0.0719772 0.0594682 10.7407 8.89088 -1 -1 -1 -1 72 286581 46 1.58244e+08 5.00245e+07 2.39867e+07 4758.32 62.14 31.0052 25.5746 615390 6416121 -1 266321 24 92304 125385 12396060 2405052 4.93927 4.93927 -21502.9 -4.93927 0 0 3.00078e+07 5952.75 1.71 7.10 5.50 -1 -1 1.71 3.83741 3.21004 25723 2050 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml cordic.v common 5.83 vpr 64.57 MiB -1 -1 0.88 26136 4 0.16 -1 -1 33044 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66124 54 51 503 502 1 304 138 9 9 81 clb auto 25.3 MiB 2.08 2002 12954 2480 9062 1412 64.6 MiB 0.20 0.01 4.43013 -227.708 -4.43013 4.43013 0.09 0.001451 0.0013363 0.0685664 0.0632597 -1 -1 -1 -1 56 4228 32 1.43308e+06 461137 231774. 2861.41 1.26 0.391145 0.341818 7704 54090 -1 3725 17 1917 7166 373067 93632 3.65072 3.65072 -196.427 -3.65072 0 0 286113. 3532.26 0.01 0.09 0.03 -1 -1 0.01 0.0324143 0.0294926 234 281 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml Md5Core.v common 472.40 vpr 866.96 MiB -1 -1 22.33 218376 1 4.13 -1 -1 145204 -1 -1 3485 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 887772 641 128 55563 47815 1 18425 4254 71 71 5041 clb auto 256.6 MiB 191.79 205408 4896722 1844424 2914068 138230 867.0 MiB 129.30 1.04 8.03131 -25587.9 -8.03131 8.03131 21.08 0.0733517 0.0590529 10.6832 8.73949 -1 -1 -1 -1 64 273108 50 1.5868e+08 4.91153e+07 2.16513e+07 4295.04 61.30 30.7872 25.3336 590190 5755241 -1 250871 18 71120 89065 8566793 1619750 5.5524 5.5524 -21928.1 -5.5524 0 0 2.72404e+07 5403.77 1.82 6.19 4.71 -1 -1 1.82 3.42355 2.88442 25749 2050 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml cordic.v common 4.49 vpr 64.21 MiB -1 -1 0.92 26136 4 0.16 -1 -1 33152 -1 -1 35 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65752 54 51 503 502 1 303 140 9 9 81 clb auto 25.4 MiB 0.68 1940 13934 2921 9841 1172 64.2 MiB 0.17 0.00 4.47128 -234.847 -4.47128 4.47128 0.09 0.00140285 0.00129011 0.0597002 0.0551005 -1 -1 -1 -1 56 3999 30 1.43728e+06 493284 231774. 2861.41 1.11 0.375638 0.327858 7704 54090 -1 3545 17 1758 6326 315468 81095 3.68106 3.68106 -203.624 -3.68106 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0539124 0.0479125 251 281 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_2ripple_N8_22nm.xml Md5Core.v common 477.93 vpr 699.03 MiB -1 -1 15.73 218396 1 3.59 -1 -1 144908 -1 -1 2893 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 715804 641 128 55563 47815 1 17875 3662 65 65 4225 clb auto 307.3 MiB 229.77 653595 188180 4010050 1589381 2339755 80914 698.8 MiB 74.46 0.60 15.2096 7.56088 -24817.3 -7.56088 7.56088 15.68 0.0492048 0.042965 7.99151 6.70431 -1 -1 -1 -1 92 259836 45 1.34217e+08 4.18788e+07 2.45933e+07 5820.91 106.38 34.176 28.8777 568658 6739433 -1 238307 25 84571 105591 11115783 1991214 6.27776 6.27776 -22967 -6.27776 0 0 3.06352e+07 7250.94 1.72 5.76 4.59 -1 -1 1.72 3.18855 2.77683 20993 2050 -1 -1 -1 -1 +k6_frac_2ripple_N8_22nm.xml cordic.v common 5.88 vpr 66.43 MiB -1 -1 0.42 25312 4 0.13 -1 -1 32620 -1 -1 34 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68024 54 51 503 502 1 316 139 9 9 81 clb auto 27.1 MiB 2.92 2831 1984 7678 1282 5509 887 66.4 MiB 0.06 0.00 4.51901 4.18969 -226.44 -4.18969 4.18969 0.06 0.000666802 0.000609419 0.0195881 0.0180803 -1 -1 -1 -1 58 4540 50 1.45065e+06 492173 237595. 2933.27 1.32 0.289584 0.254751 7864 57025 -1 3555 20 1939 7105 362500 91101 3.89871 3.89871 -212.35 -3.89871 0 0 298762. 3688.42 0.01 0.10 0.03 -1 -1 0.01 0.0438049 0.0398469 226 281 -1 -1 -1 -1 +k6_frac_2uripple_N8_22nm.xml Md5Core.v common 370.63 vpr 696.85 MiB -1 -1 13.58 217508 1 3.90 -1 -1 144528 -1 -1 2897 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 713572 641 128 55563 47815 1 17888 3666 65 65 4225 clb auto 301.8 MiB 158.38 643219 185056 4072386 1563668 2435367 73351 696.8 MiB 66.14 0.59 16.3713 7.04442 -24207.9 -7.04442 7.04442 16.43 0.055064 0.0485492 7.86424 6.61941 -1 -1 -1 -1 86 262236 34 1.34928e+08 4.2632e+07 2.31978e+07 5490.61 81.10 27.3467 23.1128 551762 6310377 -1 236085 23 81064 102545 11776128 2047879 6.1643 6.1643 -22374.2 -6.1643 0 0 2.90884e+07 6884.83 1.62 5.64 4.36 -1 -1 1.62 3.20849 2.80174 20965 2050 -1 -1 -1 -1 +k6_frac_2uripple_N8_22nm.xml cordic.v common 3.07 vpr 66.24 MiB -1 -1 0.43 25360 4 0.20 -1 -1 32860 -1 -1 33 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67832 54 51 503 502 1 318 138 9 9 81 clb auto 27.1 MiB 0.36 2931 2050 13310 2770 9570 970 66.2 MiB 0.09 0.00 4.3236 4.15816 -225.982 -4.15816 4.15816 0.06 0.000742946 0.000682425 0.0328962 0.0301738 -1 -1 -1 -1 56 4421 38 1.45905e+06 485618 231774. 2861.41 0.93 0.244522 0.218208 7704 54090 -1 3718 18 1920 6861 352217 88853 3.68306 3.68306 -206.395 -3.68306 0 0 286113. 3532.26 0.01 0.09 0.05 -1 -1 0.01 0.03847 0.0354053 227 281 -1 -1 -1 -1 +k6_frac_N8_22nm.xml Md5Core.v common 451.99 vpr 788.38 MiB -1 -1 21.29 328008 27 14.03 -1 -1 137544 -1 -1 3471 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 807304 641 128 52026 52154 1 22539 4240 71 71 5041 clb auto 302.9 MiB 198.91 971668 249965 4292115 1627870 2599391 64854 788.4 MiB 59.25 0.47 52.2374 15.4038 -39114.5 -15.4038 15.4038 28.59 0.0690838 0.0616158 10.1516 8.54447 -1 -1 -1 -1 82 376055 32 1.56446e+08 4.67613e+07 2.66411e+07 5284.89 89.69 34.2976 29.2554 631278 7194181 -1 345823 16 104618 223290 16671777 3186307 13.7481 13.7481 -36094 -13.7481 0 0 3.32761e+07 6601.10 1.86 7.39 4.64 -1 -1 1.86 3.26381 2.92376 24649 14777 -1 -1 -1 -1 +k6_frac_N8_22nm.xml cordic.v common 3.05 vpr 65.40 MiB -1 -1 0.46 26504 11 0.21 -1 -1 33124 -1 -1 33 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66972 54 51 461 512 1 307 138 9 9 81 clb auto 26.1 MiB 0.13 3103 2218 10462 2076 7758 628 65.4 MiB 0.07 0.00 6.80674 6.00424 -251.72 -6.00424 6.00424 0.06 0.000725644 0.000663618 0.0277173 0.0254463 -1 -1 -1 -1 60 4772 48 1.41552e+06 444576 242836. 2997.97 1.31 0.311025 0.277224 7804 58296 -1 4045 19 1952 7820 394587 97023 5.48514 5.48514 -233.228 -5.48514 0 0 304930. 3764.57 0.01 0.10 0.04 -1 -1 0.01 0.0390285 0.035773 250 351 -1 -1 -1 -1 +k6_frac_ripple_N8_22nm.xml Md5Core.v common 880.65 vpr 786.22 MiB -1 -1 12.64 217632 1 3.52 -1 -1 144524 -1 -1 3573 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 805092 641 128 55563 47815 1 19435 4342 71 71 5041 clb auto 289.0 MiB 580.57 819752 209041 5067686 1879984 3018557 169145 786.2 MiB 123.00 0.77 15.3089 8.61024 -24476.7 -8.61024 8.61024 19.39 0.0540455 0.0439781 8.09228 6.53093 -1 -1 -1 -1 74 282704 34 1.58244e+08 4.99267e+07 2.44980e+07 4859.74 108.08 34.8268 29.2592 620430 6551051 -1 266640 25 86742 116693 12206521 2336167 5.88317 5.88317 -21677.4 -5.88317 0 0 3.04825e+07 6046.92 1.75 5.63 4.53 -1 -1 1.75 2.84807 2.46262 25727 2050 -1 -1 -1 -1 +k6_frac_ripple_N8_22nm.xml cordic.v common 4.85 vpr 65.68 MiB -1 -1 0.75 25352 4 0.19 -1 -1 32876 -1 -1 33 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67252 54 51 503 502 1 305 138 9 9 81 clb auto 26.7 MiB 1.90 2824 1925 10818 2107 7677 1034 65.7 MiB 0.09 0.00 4.87184 4.35815 -225.348 -4.35815 4.35815 0.06 0.000770335 0.000672667 0.0289517 0.0267081 -1 -1 -1 -1 54 4063 43 1.43308e+06 461137 226270. 2793.45 0.99 0.2461 0.216024 7624 52756 -1 3291 17 1788 6579 287632 74898 3.83626 3.83626 -198.879 -3.83626 0 0 280165. 3458.82 0.01 0.09 0.03 -1 -1 0.01 0.0383915 0.0351202 234 281 -1 -1 -1 -1 +k6_frac_uripple_N8_22nm.xml Md5Core.v common 388.87 vpr 781.73 MiB -1 -1 13.78 217608 1 3.59 -1 -1 144908 -1 -1 3472 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 800492 641 128 55563 47815 1 18248 4241 71 71 5041 clb auto 285.5 MiB 160.70 748459 205594 4842515 1817314 2868610 156591 781.7 MiB 103.27 0.79 17.6617 8.00284 -25797.5 -8.00284 8.00284 22.43 0.0525316 0.041828 7.49622 6.1714 -1 -1 -1 -1 60 281470 45 1.5868e+08 4.89321e+07 2.04516e+07 4057.04 56.14 22.8967 19.2291 575070 5378021 -1 255823 17 76566 95763 9476991 1821430 5.31054 5.31054 -22200.8 -5.31054 0 0 2.55408e+07 5066.62 1.34 4.26 3.31 -1 -1 1.34 2.0631 1.81096 25722 2050 -1 -1 -1 -1 +k6_frac_uripple_N8_22nm.xml cordic.v common 3.50 vpr 65.62 MiB -1 -1 0.45 25356 4 0.14 -1 -1 32508 -1 -1 35 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67200 54 51 503 502 1 301 140 9 9 81 clb auto 26.4 MiB 0.52 2717 2105 7763 1290 5799 674 65.6 MiB 0.06 0.00 4.88573 4.50668 -234.843 -4.50668 4.50668 0.06 0.000670214 0.000611502 0.01904 0.0174694 -1 -1 -1 -1 60 4031 25 1.43728e+06 493284 242836. 2997.97 1.34 0.287424 0.253314 7944 58396 -1 3718 20 1983 8095 422416 104597 3.58761 3.58761 -202.534 -3.58761 0 0 304930. 3764.57 0.01 0.14 0.05 -1 -1 0.01 0.0558313 0.0505463 250 281 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt index bc4a9702b59..9e219b5070f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt @@ -1,31 +1,31 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.41 vpr 66.85 MiB -1 -1 0.34 22268 3 0.10 -1 -1 37000 -1 54240 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68452 99 130 344 474 1 226 298 12 12 144 clb auto 27.2 MiB 0.07 661 69948 21317 34488 14143 66.8 MiB 0.19 0.00 1.84343 -120.716 -1.84343 1.84343 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Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 435424 114 102 21994 21904 1 11199 1467 50 50 2500 memory auto 173.7 MiB 160.18 498306 142361 884659 311124 554810 18725 425.2 MiB 18.63 0.17 175.7 78.9128 -49795.1 -78.9128 78.9128 9.86 0.0494021 0.0446317 6.20357 4.97966 -1 -1 -1 -1 86 212684 30 1.47946e+08 9.23952e+07 1.49824e+07 5992.98 257.20 25.7378 21.2495 340872 3235144 -1 192023 18 37543 153253 8529801 1673802 79.8203 79.8203 -61388.2 -79.8203 -28.4501 -0.29436 1.89069e+07 7562.76 0.79 4.41 2.28 -1 -1 0.79 2.59244 2.28805 0.08429 0.3846 0.01159 0.6038 +k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.13 vpr 66.50 MiB -1 -1 0.23 18748 3 0.07 -1 -1 32700 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68096 99 130 344 474 1 224 298 12 12 144 clb auto 26.7 MiB 0.10 1602 677 71938 23237 33899 14802 66.5 MiB 0.15 0.00 2.12998 1.84564 -120.965 -1.84564 1.84564 0.11 0.000760103 0.000723485 0.0543791 0.0512037 -1 -1 -1 -1 32 1650 13 5.66058e+06 4.21279e+06 307825. 2137.67 0.36 0.184989 0.171256 12860 59602 -1 1400 11 452 691 34201 11876 1.88346 1.88346 -144.078 -1.88346 -0.484813 -0.296573 375846. 2610.04 0.01 0.03 0.04 -1 -1 0.01 0.0208013 0.0193133 0.01053 0.2499 0.06921 0.6809 +k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 8.05 vpr 69.89 MiB -1 -1 0.49 23352 15 0.30 -1 -1 33476 -1 53996 38 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71568 162 96 1009 950 1 704 301 16 16 256 mult_36 auto 30.4 MiB 0.40 9299 5715 87997 27573 53784 6640 69.9 MiB 0.38 0.01 22.6764 20.6663 -1473.39 -20.6663 20.6663 0.22 0.00359067 0.00347295 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release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 479372 114 102 21994 21904 1 10803 1458 50 50 2500 memory auto 173.6 MiB 205.93 506208 141993 860914 287837 555087 17990 468.1 MiB 19.97 0.18 173.854 77.809 -53343.1 -77.809 77.809 11.37 0.058387 0.052435 6.55994 5.25064 -1 -1 -1 -1 86 210901 20 1.47946e+08 9.19101e+07 1.55613e+07 6224.53 95.11 21.2605 17.5729 351240 3418312 -1 189357 19 34668 146207 8378386 1660456 79.4888 79.4888 -63710.1 -79.4888 -20.6468 -0.292146 1.95825e+07 7833.01 0.82 4.66 2.29 -1 -1 0.82 2.8036 2.44094 0.08776 0.3779 0.01182 0.6103 +k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.92 vpr 66.19 MiB -1 -1 0.31 18744 3 0.10 -1 -1 32740 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67776 99 130 344 474 1 225 298 12 12 144 clb auto 26.3 MiB 0.10 1615 746 67958 18270 34570 15118 66.2 MiB 0.11 0.00 2.01486 1.59858 -123.171 -1.59858 1.59858 0.10 0.000556701 0.000520594 0.0409336 0.0382267 -1 -1 -1 -1 38 1453 18 5.66058e+06 4.21279e+06 319130. 2216.18 0.84 0.240772 0.219266 12522 62564 -1 1256 9 390 597 28390 9347 1.91586 1.91586 -139.414 -1.91586 -0.519581 -0.320482 406292. 2821.48 0.02 0.04 0.07 -1 -1 0.02 0.0249994 0.0232439 0.01048 0.2589 0.07296 0.6681 +k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 7.44 vpr 69.52 MiB -1 -1 0.35 23352 15 0.30 -1 -1 33448 -1 54344 38 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71192 162 96 1009 950 1 700 301 16 16 256 mult_36 auto 29.7 MiB 0.45 9328 5492 86989 27657 51981 7351 69.5 MiB 0.37 0.01 24.0124 21.2051 -1567.83 -21.2051 21.2051 0.19 0.00168462 0.001571 0.159436 0.148658 -1 -1 -1 -1 48 12122 34 1.21132e+07 4.02797e+06 756778. 2956.16 2.79 0.668469 0.620661 25228 149258 -1 9821 21 3409 7006 953600 270168 22.4255 22.4255 -1694.34 -22.4255 0 0 968034. 3781.38 0.03 0.24 0.09 -1 -1 0.03 0.0968556 0.0912177 0.007714 0.3551 0.01683 0.628 +k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 617.65 vpr 395.10 MiB -1 -1 59.81 339204 123 70.26 -1 -1 77108 -1 116408 1325 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 404580 114 102 21994 21904 1 11955 1594 50 50 2500 memory auto 175.0 MiB 120.88 545909 151828 1053285 379121 652784 21380 393.1 MiB 22.00 0.18 211.344 80.3034 -52037 -80.3034 80.3034 8.39 0.0493259 0.0426176 6.56156 5.30077 -1 -1 -1 -1 88 232639 46 1.47946e+08 9.924e+07 1.46563e+07 5862.50 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8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 417356 114 102 21994 21904 1 11319 1506 50 50 2500 memory auto 174.6 MiB 117.47 510273 146262 916180 316752 580447 18981 392.9 MiB 29.07 0.18 165.87 79.0039 -52422.3 -79.0039 79.0039 8.86 0.06359 0.0575998 10.4538 8.54795 -1 -1 -1 -1 88 228519 39 1.47946e+08 9.44971e+07 1.46563e+07 5862.50 80.09 30.4837 25.1306 331272 3068748 -1 202165 20 43563 170190 10468459 1963493 80.5091 80.5091 -64425 -80.5091 -28.7444 -0.217304 1.83775e+07 7351.00 0.78 5.22 2.53 -1 -1 0.78 2.88415 2.48287 0.08172 0.3986 0.01152 0.5898 +k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.51 vpr 66.29 MiB -1 -1 0.35 18748 3 0.07 -1 -1 32164 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67884 99 130 344 474 1 224 298 12 12 144 clb auto 26.3 MiB 0.16 1602 666 71938 23977 33264 14697 66.3 MiB 0.18 0.00 2.12112 1.84343 -121.24 -1.84343 1.84343 0.11 0.000569735 0.000533646 0.0633907 0.0590458 -1 -1 -1 -1 48 1355 18 5.66058e+06 4.21279e+06 394078. 2736.65 0.37 0.185219 0.170081 13382 75762 -1 1110 12 455 720 27368 8107 1.92497 1.92497 -135.097 -1.92497 -1.55249 -0.320482 503207. 3494.49 0.01 0.03 0.05 -1 -1 0.01 0.0195482 0.0182461 0.01038 0.2431 0.0817 0.6752 +k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 9.87 vpr 69.59 MiB -1 -1 0.43 23360 15 0.45 -1 -1 33444 -1 54344 37 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71260 162 96 1009 950 1 700 300 16 16 256 mult_36 auto 30.0 MiB 0.37 9485 5610 94582 32807 54533 7242 69.6 MiB 0.52 0.01 23.4051 20.8518 -1522.69 -20.8518 20.8518 0.19 0.0017459 0.00162984 0.238561 0.22249 -1 -1 -1 -1 56 11497 31 1.21132e+07 3.97408e+06 870502. 3400.40 4.78 1.06486 0.985301 26504 172068 -1 9372 19 3152 6553 767916 254054 22.0135 22.0135 -1616.86 -22.0135 0 0 1.11200e+06 4343.75 0.03 0.26 0.11 -1 -1 0.03 0.121125 0.114779 0.008056 0.36 0.0171 0.6229 +k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 431.79 vpr 403.17 MiB -1 -1 57.52 340456 123 73.46 -1 -1 77196 -1 116412 1313 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 412844 114 102 21994 21904 1 11874 1582 50 50 2500 memory auto 175.5 MiB 127.72 524305 149710 996694 350454 623863 22377 393.6 MiB 26.24 0.20 203.639 80.9643 -51545.9 -80.9643 80.9643 8.39 0.0657084 0.0526311 8.69857 7.16568 -1 -1 -1 -1 94 223929 33 1.47946e+08 9.85932e+07 1.55181e+07 6207.23 67.00 26.1341 21.847 341268 3271592 -1 206441 20 44988 173109 9748126 1854113 82.7058 82.7058 -65880.3 -82.7058 -20.8209 -0.193384 1.95446e+07 7817.85 1.28 7.30 4.37 -1 -1 1.28 4.23242 3.61957 0.08268 0.4153 0.01156 0.5731 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 2.50 vpr 66.00 MiB -1 -1 0.22 17984 3 0.07 -1 -1 32052 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67588 99 130 344 474 1 223 298 12 12 144 clb auto 26.7 MiB 0.09 1533 708 65968 20934 31709 13325 66.0 MiB 0.11 0.00 1.94397 1.59858 -119.385 -1.59858 1.59858 0.10 0.000559731 0.000523779 0.0400831 0.0375076 -1 -1 -1 -1 46 1248 19 5.66058e+06 4.21279e+06 378970. 2631.74 0.79 0.311108 0.284597 13238 73581 -1 1204 9 412 659 29582 9323 1.90944 1.90944 -132.99 -1.90944 -1.05698 -0.322548 486261. 3376.82 0.01 0.03 0.05 -1 -1 0.01 0.0177437 0.0167297 0.01201 0.2303 0.07038 0.6994 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 10.58 vpr 69.70 MiB -1 -1 0.58 22696 15 0.47 -1 -1 33808 -1 54340 37 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71368 162 96 1009 950 1 700 300 16 16 256 mult_36 auto 30.0 MiB 0.55 9485 5610 94582 32808 54547 7227 69.7 MiB 0.39 0.01 23.4051 20.8518 -1522.66 -20.8518 20.8518 0.19 0.00166218 0.00154141 0.169989 0.158279 -1 -1 -1 -1 56 11809 46 1.21132e+07 3.97408e+06 870502. 3400.40 5.43 1.03813 0.961056 26504 172068 -1 9483 23 3566 7596 912328 301551 22.4383 22.4383 -1675.76 -22.4383 0 0 1.11200e+06 4343.75 0.03 0.25 0.11 -1 -1 0.03 0.104618 0.0981207 0.008278 0.3493 0.01636 0.6344 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 567.43 vpr 394.45 MiB -1 -1 51.45 339968 123 70.70 -1 -1 76424 -1 116412 1207 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 403920 114 102 21994 21904 1 11085 1476 50 50 2500 memory auto 173.7 MiB 130.64 491408 141971 866676 294452 552810 19414 391.9 MiB 17.82 0.15 158.585 79.1521 -48519.8 -79.1521 79.1521 8.23 0.0453742 0.0406504 5.90749 4.79132 -1 -1 -1 -1 86 219171 50 1.47946e+08 9.28803e+07 1.43148e+07 5725.91 226.89 25.5151 20.9431 328776 3019144 -1 195661 23 42037 165667 9419021 1798243 80.1516 80.1516 -60422.3 -80.1516 -31.1111 -0.295467 1.81111e+07 7244.46 0.94 6.49 2.12 -1 -1 0.94 3.85264 3.3137 0.08223 0.3879 0.01173 0.6003 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt index 8d6884970eb..276468e2908 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt @@ -1,15 +1,15 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 98.48 parmys 238.48 MiB -1 -1 62.65 244200 13 8.25 -1 -1 47788 -1 49624 326 257 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 95576 257 32 5008 5040 1 2954 615 23 23 529 clb auto 50.5 MiB 2.76 20267 220191 65143 146065 8983 93.3 MiB 2.97 0.04 8.82032 -3904.7 -8.82032 8.82032 0.54 0.0109643 0.0098333 1.02884 0.902188 -1 -1 -1 -1 56 33645 24 2.70004e+07 1.75694e+07 1.92373e+06 3636.54 6.22 3.27588 2.85668 56706 387443 -1 30010 16 11550 36095 972511 199422 9.40635 9.40635 -3964.62 -9.40635 0 0 2.45466e+06 4640.18 0.09 0.82 0.33 -1 -1 0.09 0.508209 0.459137 0.01648 0.4272 0.03377 0.5391 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 94.21 parmys 306.69 MiB -1 -1 21.16 314052 7 13.24 -1 -1 60844 -1 50612 549 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 136868 36 100 6778 6878 1 3144 685 30 30 900 clb auto 67.3 MiB 3.50 42466 287395 83633 184471 19291 113.8 MiB 5.19 0.06 5.74861 -2247.23 -5.74861 5.74861 1.03 0.0222208 0.0200972 1.955 1.66503 -1 -1 -1 -1 66 68658 45 4.8774e+07 2.95878e+07 3.99156e+06 4435.07 27.65 7.52931 6.32406 104036 803752 -1 60922 16 14883 67597 2789200 373708 5.76735 5.76735 -2377.78 -5.76735 0 0 4.95347e+06 5503.86 0.20 1.71 0.69 -1 -1 0.20 0.908064 0.803825 0.02605 0.351 0.06511 0.5839 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 24.14 vpr 68.57 MiB -1 -1 17.73 31664 4 0.24 -1 -1 34328 -1 55248 53 195 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70220 195 193 1087 1280 1 610 442 15 15 225 io auto 28.4 MiB 0.31 3111 131716 33861 86359 11496 68.6 MiB 0.67 0.01 2.49928 -1087.72 -2.49928 2.49928 0.23 0.00362287 0.00338275 0.298018 0.277768 -1 -1 -1 -1 40 5849 18 1.03862e+07 3.40438e+06 568276. 2525.67 1.78 1.09849 1.00863 21262 112936 -1 5416 11 1616 2529 155491 45590 2.72859 2.72859 -1209.59 -2.72859 -0.959406 -0.246 712852. 3168.23 0.02 0.09 0.07 -1 -1 0.02 0.0607763 0.057325 0.01365 0.3769 0.05606 0.567 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.23 vpr 63.89 MiB -1 -1 0.49 18176 3 0.10 -1 -1 33044 -1 53092 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65428 99 130 344 474 1 226 298 12 12 144 clb auto 24.1 MiB 0.08 678 66963 19395 33485 14083 63.9 MiB 0.23 0.00 1.86362 -122.41 -1.86362 1.86362 0.14 0.00130445 0.00123497 0.0907109 0.085881 -1 -1 -1 -1 52 1254 11 5.66058e+06 4.21279e+06 419432. 2912.72 0.65 0.338628 0.310581 13810 82561 -1 1175 7 368 599 29659 8862 1.9806 1.9806 -135.825 -1.9806 -0.309826 -0.0782318 551878. 3832.49 0.02 0.04 0.08 -1 -1 0.02 0.0250196 0.0231993 0.01031 0.263 0.08354 0.6535 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 10.16 vpr 68.16 MiB -1 -1 0.74 23332 15 0.35 -1 -1 34092 -1 54824 39 162 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69796 162 96 1009 950 1 709 302 16 16 256 mult_36 auto 28.2 MiB 0.19 5587 92394 30880 53838 7676 68.2 MiB 0.69 0.01 21.0975 -1536.06 -21.0975 21.0975 0.26 0.00337966 0.00317219 0.323022 0.303359 -1 -1 -1 -1 56 11812 30 1.21132e+07 4.08187e+06 870502. 3400.40 4.17 1.16452 1.07293 26504 172068 -1 9609 16 2935 5927 775463 239759 22.3005 22.3005 -1636.88 -22.3005 0 0 1.11200e+06 4343.75 0.04 0.29 0.15 -1 -1 0.04 0.13141 0.122082 0.007854 0.3765 0.01734 0.6061 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 7.88 vpr 65.00 MiB -1 -1 0.61 21868 16 0.27 -1 -1 33428 -1 53744 25 66 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66560 66 96 616 557 1 415 192 16 16 256 mult_36 auto 25.5 MiB 0.17 3625 36690 9459 22826 4405 65.0 MiB 0.32 0.01 17.203 -935.064 -17.203 17.203 0.26 0.00236496 0.0022302 0.166486 0.157037 -1 -1 -1 -1 40 8373 37 1.21132e+07 3.32735e+06 642278. 2508.90 3.53 0.766237 0.703647 23952 127161 -1 7217 17 2534 5167 951988 292757 18.0101 18.0101 -1019.64 -18.0101 0 0 805949. 3148.24 0.02 0.19 0.08 -1 -1 0.02 0.05209 0.0486566 0.007411 0.3353 0.01978 0.6449 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 440.60 vpr 461.59 MiB -1 -1 84.00 349248 123 64.46 -1 -1 78572 -1 117272 1375 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 472672 114 102 21994 21904 1 11802 1644 50 50 2500 memory auto 155.4 MiB 20.55 160790 1049136 374899 655277 18960 461.6 MiB 26.29 0.22 78.4871 -53143.2 -78.4871 78.4871 9.75 0.0621978 0.0545143 7.35439 6.13837 -1 -1 -1 -1 94 240662 29 1.47946e+08 1.01935e+08 1.55181e+07 6207.23 162.29 28.9908 23.8912 341268 3271592 -1 217509 21 44132 167614 9994098 1867129 81.2261 81.2261 -64082.4 -81.2261 -12.841 -0.29436 1.95446e+07 7817.85 0.86 6.13 3.06 -1 -1 0.86 3.42933 2.93557 0.08134 0.4302 0.01139 0.5585 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 70.13 vpr 332.00 MiB -1 -1 18.29 128412 5 3.25 -1 -1 56812 -1 73340 470 506 47 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 339964 506 553 3055 3608 1 2790 1576 50 50 2500 memory auto 45.7 MiB 4.81 15429 1147451 561958 401565 183928 332.0 MiB 5.51 0.07 7.14518 -1819.3 -7.14518 7.14518 9.87 0.0227758 0.020582 2.93349 2.63053 -1 -1 -1 -1 38 22365 17 1.47946e+08 5.10868e+07 6.86584e+06 2746.33 11.85 8.32526 7.54939 251304 1421084 -1 21433 18 3916 5150 995348 263030 7.69019 7.69019 -2049.85 -7.69019 -5.04137 -0.293253 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28.03 vpr 76.09 MiB -1 -1 9.24 55960 7 2.30 -1 -1 37416 -1 59040 157 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77920 193 205 2234 2439 1 1179 560 20 20 400 memory auto 35.6 MiB 1.10 9842 228953 80249 124571 24133 76.1 MiB 1.72 0.02 5.08439 -2926.08 -5.08439 5.08439 0.43 0.00685575 0.00620383 0.738776 0.665656 -1 -1 -1 -1 48 17744 33 2.07112e+07 1.12014e+07 1.23055e+06 3076.38 6.37 2.5483 2.26983 40448 245963 -1 15329 16 4566 11562 627458 139494 5.47739 5.47739 -3135.16 -5.47739 -11.584 -0.360359 1.57502e+06 3937.55 0.06 0.44 0.22 -1 -1 0.06 0.280677 0.254763 0.02856 0.2221 0.02552 0.7523 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 63.07 vpr 106.00 MiB -1 -1 7.93 68908 27 4.13 -1 -1 38580 -1 61144 234 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 108548 385 394 3906 4237 1 2373 1016 27 27 729 io auto 46.0 MiB 2.92 31525 572776 227317 322407 23052 88.3 MiB 5.07 0.06 14.4133 -13461.7 -14.4133 14.4133 0.83 0.0160926 0.0150256 1.89286 1.74364 -1 -1 -1 -1 78 51645 44 3.93038e+07 1.41032e+07 3.65949e+06 5019.88 29.17 7.69214 7.06424 90401 760319 -1 44396 14 10279 35511 1944665 349659 14.8103 14.8103 -13960.4 -14.8103 0 0 4.63207e+06 6354.00 0.16 1.07 0.66 -1 -1 0.16 0.591618 0.549921 0.02224 0.4637 0.02666 0.5097 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 25.27 vpr 77.84 MiB -1 -1 6.25 46808 8 0.90 -1 -1 37872 -1 60796 133 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79708 235 305 2600 2761 1 1501 680 19 19 361 io auto 36.8 MiB 2.09 12500 263712 91208 158948 13556 77.8 MiB 1.99 0.03 5.38636 -2731.89 -5.38636 5.38636 0.39 0.00825643 0.00765916 0.774605 0.712384 -1 -1 -1 -1 56 23995 47 1.72706e+07 1.00919e+07 1.27879e+06 3542.35 6.04 2.65451 2.42437 38159 255829 -1 20300 15 5879 16147 1393547 361528 5.87661 5.87661 -3009.11 -5.87661 -1.26427 -0.201639 1.63234e+06 4521.70 0.07 0.66 0.22 -1 -1 0.07 0.333764 0.30935 0.02386 0.4083 0.02598 0.5657 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 19.44 vpr 78.34 MiB -1 -1 4.20 47476 21 2.24 -1 -1 40644 -1 45784 147 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80220 38 36 2570 2606 1 1050 221 17 17 289 clb auto 37.3 MiB 1.10 9478 36239 7889 25786 2564 78.3 MiB 0.76 0.01 14.6977 -2591.44 -14.6977 14.6977 0.30 0.00627054 0.00560905 0.378906 0.335347 -1 -1 -1 -1 46 16543 25 1.34605e+07 7.92242e+06 830882. 2875.03 3.43 1.51759 1.31374 28231 166010 -1 13884 15 4024 11917 367875 68444 15.3347 15.3347 -2866.69 -15.3347 0 0 1.06831e+06 3696.59 0.04 0.39 0.14 -1 -1 0.04 0.261218 0.233045 0.006476 0.3635 0.02972 0.6068 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 5304.23 vpr 1.66 GiB -1 -1 692.05 1442556 64 3350.31 -1 -1 347144 -1 317188 6851 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1741944 36 356 125423 124208 1 34881 7429 98 98 9604 clb auto 660.2 MiB 73.61 461903 10223866 4318975 5823833 81058 1701.1 MiB 186.47 1.32 63.3139 -299631 -63.3139 63.3139 39.62 0.235404 0.202231 35.8753 30.2278 -1 -1 -1 -1 80 612389 32 5.9175e+08 4.67016e+08 5.28775e+07 5505.77 350.18 119.658 98.779 1236252 11146124 -1 575490 18 116226 373166 21552241 4233065 64.9427 64.9427 -370561 -64.9427 0 0 6.66202e+07 6936.71 3.07 14.93 8.56 -1 -1 3.07 9.99565 8.64031 0.27 0.3629 0.01392 0.6231 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 73.91 parmys 233.23 MiB -1 -1 39.47 238824 13 7.95 -1 -1 46764 -1 48996 327 257 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 96536 257 32 5008 5040 1 2943 616 23 23 529 clb auto 54.8 MiB 2.79 65213 20720 212836 62576 141404 8856 94.3 MiB 2.16 0.03 15.6864 8.68111 -3946.45 -8.68111 8.68111 0.47 0.00900431 0.00825416 0.809596 0.685169 -1 -1 -1 -1 54 36711 43 2.70004e+07 1.76233e+07 1.84580e+06 3489.22 7.98 3.562 3.08331 56178 377761 -1 31514 18 12398 38406 1049777 214372 9.02421 9.02421 -4006.96 -9.02421 0 0 2.39736e+06 4531.87 0.08 0.66 0.23 -1 -1 0.08 0.416736 0.377988 0.01687 0.4307 0.035 0.5343 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 84.17 parmys 301.52 MiB -1 -1 12.62 308752 7 12.18 -1 -1 60036 -1 50488 549 36 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 150732 36 100 6778 6878 1 3174 685 30 30 900 clb auto 74.4 MiB 2.46 100415 43091 287395 84241 184732 18422 122.8 MiB 4.40 0.04 10.787 5.93521 -2226.9 -5.93521 5.93521 0.88 0.0156921 0.0138472 1.85917 1.49809 -1 -1 -1 -1 68 69536 47 4.8774e+07 2.95878e+07 4.08678e+06 4540.87 32.68 11.9422 9.93511 104936 820930 -1 62040 16 15562 69635 2878029 387059 5.92616 5.92616 -2305.97 -5.92616 0 0 5.07014e+06 5633.48 0.28 1.64 0.84 -1 -1 0.28 0.904982 0.807567 0.02624 0.3631 0.0623 0.5746 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 15.19 vpr 70.11 MiB -1 -1 10.61 30332 4 0.19 -1 -1 34124 -1 54840 52 195 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71796 195 193 1087 1280 1 610 441 15 15 225 io auto 30.0 MiB 0.19 7614 3059 146427 37859 95262 13306 70.1 MiB 0.42 0.01 3.20593 2.49928 -1069.9 -2.49928 2.49928 0.17 0.00182089 0.00169146 0.184374 0.171367 -1 -1 -1 -1 38 6113 40 1.03862e+07 3.35049e+06 544128. 2418.35 1.13 0.604765 0.560239 21038 109288 -1 5298 14 1719 2545 149969 42488 2.49938 2.49938 -1173.25 -2.49938 -0.366048 -0.154403 690492. 3068.85 0.02 0.12 0.06 -1 -1 0.02 0.0807398 0.0762167 0.01471 0.3796 0.05512 0.5653 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.53 vpr 65.32 MiB -1 -1 0.23 18360 3 0.08 -1 -1 32348 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66884 99 130 344 474 1 225 298 12 12 144 clb auto 25.9 MiB 0.05 1615 746 67958 18270 34570 15118 65.3 MiB 0.13 0.00 2.01486 1.59858 -123.171 -1.59858 1.59858 0.11 0.000556191 0.000520549 0.0495332 0.0464577 -1 -1 -1 -1 38 1499 18 5.66058e+06 4.21279e+06 319130. 2216.18 0.69 0.227149 0.207861 12522 62564 -1 1252 9 384 592 28238 9313 1.91586 1.91586 -140.767 -1.91586 -0.519581 -0.320482 406292. 2821.48 0.02 0.05 0.08 -1 -1 0.02 0.0293074 0.0273435 0.0104 0.2593 0.07351 0.6672 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 8.38 vpr 69.14 MiB -1 -1 0.36 22972 15 0.30 -1 -1 33488 -1 54344 39 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70796 162 96 1009 950 1 708 302 16 16 256 mult_36 auto 30.0 MiB 0.17 9283 5447 78226 20759 50449 7018 69.1 MiB 0.55 0.01 23.1618 21.0975 -1526.6 -21.0975 21.0975 0.21 0.00330278 0.00307022 0.260633 0.24323 -1 -1 -1 -1 46 12326 45 1.21132e+07 4.08187e+06 727248. 2840.81 4.06 0.987618 0.914723 24972 144857 -1 9837 18 3344 6799 857275 248767 22.0372 22.0372 -1631.88 -22.0372 0 0 934704. 3651.19 0.03 0.25 0.09 -1 -1 0.03 0.105117 0.0992267 0.007635 0.3555 0.01709 0.6274 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 6.01 vpr 66.57 MiB -1 -1 0.28 21820 16 0.30 -1 -1 33456 -1 53260 25 66 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68172 66 96 616 557 1 413 192 16 16 256 mult_36 auto 27.8 MiB 0.16 5839 3600 33925 8855 22033 3037 66.6 MiB 0.16 0.00 18.5797 17.3962 -922.324 -17.3962 17.3962 0.19 0.00117398 0.00109916 0.0799091 0.0749224 -1 -1 -1 -1 42 8401 30 1.21132e+07 3.32735e+06 666210. 2602.38 2.88 0.529946 0.4903 24208 131534 -1 7297 20 2245 4601 911103 273230 18.2437 18.2437 -1021.13 -18.2437 0 0 835850. 3265.04 0.03 0.19 0.08 -1 -1 0.03 0.0644744 0.0606047 0.007431 0.3429 0.01978 0.6373 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 522.10 vpr 405.85 MiB -1 -1 51.98 340472 123 64.80 -1 -1 76780 -1 116408 1382 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 415592 114 102 21994 21904 1 11821 1651 50 50 2500 memory auto 174.6 MiB 14.96 552678 151396 1064837 378372 663631 22834 395.6 MiB 24.91 0.20 205.795 79.0262 -52621 -79.0262 79.0262 11.89 0.0788831 0.0646447 8.71447 7.02325 -1 -1 -1 -1 84 236453 45 1.47946e+08 1.02312e+08 1.39795e+07 5591.78 288.11 29.1843 24.0513 326276 2968264 -1 209371 19 45363 173487 10455005 1964601 80.3198 80.3198 -64807.2 -80.3198 -16.7054 -0.295467 1.77686e+07 7107.43 0.90 5.81 2.30 -1 -1 0.90 3.12869 2.68349 0.07831 0.407 0.01163 0.5813 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 52.70 vpr 304.03 MiB -1 -1 11.10 123576 5 4.06 -1 -1 56180 -1 72900 463 506 45 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 311328 506 553 3055 3608 1 2790 1567 50 50 2500 memory auto 51.4 MiB 2.49 38121 16032 1138817 560483 396028 182306 304.0 MiB 4.30 0.05 10.0192 8.1793 -1876.61 -8.1793 8.1793 8.82 0.0151622 0.014182 2.36885 2.18985 -1 -1 -1 -1 38 23425 15 1.47946e+08 4.96135e+07 6.86584e+06 2746.33 9.51 6.26379 5.86537 251304 1421084 -1 22431 19 3940 5274 1035253 269611 8.62851 8.62851 -2150.71 -8.62851 -2.64826 -0.292146 8.69095e+06 3476.38 0.52 0.87 1.07 -1 -1 0.52 0.67084 0.634949 0.1419 0.1545 0.03969 0.8058 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 11.14 vpr 71.76 MiB -1 -1 0.89 25268 2 0.13 -1 -1 33312 -1 59472 29 311 15 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73484 311 156 972 1128 1 953 511 28 28 784 memory auto 31.5 MiB 0.32 19380 8779 212879 80847 122346 9686 70.8 MiB 0.75 0.01 4.64689 4.01099 -4636.11 -4.01099 4.01099 0.72 0.00267918 0.00237848 0.370373 0.330948 -1 -1 -1 -1 46 13615 18 4.25198e+07 9.78293e+06 2.40571e+06 3068.51 4.48 1.46611 1.31834 79818 491339 -1 13091 12 2437 2782 609856 172667 4.39426 4.39426 -4975.9 -4.39426 -18.8574 -0.359474 3.09729e+06 3950.62 0.11 0.22 0.30 -1 -1 0.11 0.114983 0.106778 0.08453 0.1621 0.01936 0.8185 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 20.19 vpr 77.92 MiB -1 -1 5.94 52388 7 2.11 -1 -1 38364 -1 58368 156 193 5 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79792 193 205 2234 2439 1 1179 559 20 20 400 memory auto 38.3 MiB 0.70 19798 9243 232960 80121 128094 24745 77.9 MiB 1.37 0.01 6.68534 4.93811 -2978.4 -4.93811 4.93811 0.33 0.003984 0.00362373 0.591618 0.530389 -1 -1 -1 -1 48 17116 41 2.07112e+07 1.11475e+07 1.23055e+06 3076.38 4.08 1.8516 1.65979 40448 245963 -1 15026 17 4638 11384 567227 126883 5.14369 5.14369 -3220.63 -5.14369 -9.04127 -0.360359 1.57502e+06 3937.55 0.05 0.37 0.15 -1 -1 0.05 0.268917 0.249398 0.02986 0.2145 0.02596 0.7596 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 44.90 vpr 97.20 MiB -1 -1 4.85 67128 27 4.33 -1 -1 41292 -1 60432 239 385 2 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 99528 385 394 3906 4237 1 2372 1021 27 27 729 io auto 50.3 MiB 1.86 62812 31588 571450 225577 322746 23127 89.5 MiB 3.55 0.04 20.8327 14.4872 -13369.2 -14.4872 14.4872 0.67 0.0121619 0.0113765 1.35407 1.22514 -1 -1 -1 -1 74 52438 48 3.93038e+07 1.43727e+07 3.51708e+06 4824.52 18.39 4.96637 4.54914 88217 717307 -1 45207 16 10797 38297 2240291 399545 15.587 15.587 -13991.8 -15.587 0 0 4.41327e+06 6053.86 0.17 0.96 0.47 -1 -1 0.17 0.489497 0.455404 0.02143 0.4567 0.02564 0.5177 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 21.43 vpr 79.10 MiB -1 -1 3.27 45264 8 1.18 -1 -1 38148 -1 60352 133 235 1 6 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 80996 235 305 2600 2761 1 1486 680 19 19 361 io auto 39.4 MiB 2.00 26051 12689 254745 87597 153775 13373 79.1 MiB 1.38 0.04 7.908 5.29959 -2839.7 -5.29959 5.29959 0.29 0.012127 0.011067 0.525997 0.479113 -1 -1 -1 -1 58 24404 36 1.72706e+07 1.00919e+07 1.32783e+06 3678.19 7.31 2.15982 1.97301 38879 268173 -1 20459 16 5974 16694 1375263 341705 5.25495 5.25495 -3023.54 -5.25495 0 0 1.69263e+06 4688.74 0.05 0.45 0.16 -1 -1 0.05 0.221912 0.208508 0.02626 0.4113 0.02791 0.5608 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 15.61 vpr 80.29 MiB -1 -1 2.33 46604 21 2.08 -1 -1 40588 -1 44928 147 38 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 82220 38 36 2570 2606 1 1047 221 17 17 289 clb auto 40.5 MiB 0.69 18019 8908 39574 9690 26848 3036 80.3 MiB 0.53 0.01 21.1511 14.3355 -2466.66 -14.3355 14.3355 0.22 0.00360612 0.00322534 0.263315 0.232003 -1 -1 -1 -1 48 15040 24 1.34605e+07 7.92242e+06 864508. 2991.38 3.70 1.49854 1.31021 28519 171069 -1 12978 12 3830 11571 346206 65034 15.2896 15.2896 -2704.54 -15.2896 0 0 1.10659e+06 3829.03 0.05 0.37 0.16 -1 -1 0.05 0.271424 0.248723 0.006497 0.3637 0.03004 0.6063 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 5092.02 vpr 1.53 GiB -1 -1 463.82 1402996 65 3505.00 -1 -1 351932 -1 316376 6857 36 159 27 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1606748 36 356 125571 124356 1 35021 7435 98 98 9604 clb auto 758.6 MiB 44.19 2 441443 10017265 4132627 5827470 57168 1569.1 MiB 178.80 1.37 172.807 64.2278 -293929 -64.2278 64.2278 33.55 0.203257 0.163777 30.6282 24.8932 -1 -1 -1 -1 78 591086 48 5.9175e+08 4.6734e+08 5.17038e+07 5383.57 240.84 97.3599 80.2169 1226648 10944044 -1 553448 19 118693 385257 20226886 3989619 65.0797 65.0797 -378350 -65.0797 -0.256508 -0.0326169 6.54025e+07 6809.92 3.27 14.83 7.78 -1 -1 3.27 9.82532 8.5296 0.2679 0.3573 0.01398 0.6288 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt index afc7702ee1c..15ab4719c9e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 4.59 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65868 14 8 926 934 0 490 100 11 11 121 clb auto 24.6 MiB 0.91 4639 5668 847 4419 402 64.3 MiB 0.16 0.01 4.54815 -31.8355 -4.54815 nan 0.11 0.00249412 0.00221472 0.083083 0.0754962 -1 -1 -1 -1 48 7214 49 4.36541e+06 4.20373e+06 357017. 2950.55 2.04 0.729015 0.623693 12171 71069 -1 6577 19 3324 15359 408061 81134 4.87162 nan -34.7178 -4.87162 0 0 455885. 3767.64 0.01 0.26 0.06 -1 -1 0.01 0.140142 0.125126 - k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 6.95 vpr 65.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 103 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67448 38 3 1113 1116 0 662 144 13 13 169 clb auto 26.3 MiB 1.53 7442 11831 1926 8689 1216 65.9 MiB 0.29 0.01 5.59822 -16.3249 -5.59822 nan 0.16 0.00306728 0.00270237 0.126883 0.113876 -1 -1 -1 -1 64 12841 39 6.52117e+06 5.55108e+06 687872. 4070.25 3.20 0.976549 0.840439 19211 138678 -1 11425 17 4712 23613 728373 121323 5.82519 nan -16.8677 -5.82519 0 0 856291. 5066.81 0.03 0.36 0.11 -1 -1 0.03 0.160453 0.144609 - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.91 vpr 64.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65892 9 19 897 916 0 556 110 12 12 144 clb auto 24.8 MiB 1.46 6252 7474 1266 5720 488 64.3 MiB 0.20 0.01 4.74237 -77.8307 -4.74237 nan 0.14 0.00271417 0.00242922 0.0925149 0.0843887 -1 -1 -1 -1 62 10739 47 5.3894e+06 4.41931e+06 554770. 3852.57 2.59 0.760237 0.654515 15940 110000 -1 9728 17 4391 21118 675575 120995 5.20821 nan -84.4166 -5.20821 0 0 687181. 4772.09 0.02 0.31 0.09 -1 -1 0.02 0.1315 0.118528 - k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 6.12 vpr 65.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67388 229 197 1364 1561 1 539 497 16 16 256 io auto 26.1 MiB 0.83 4504 148022 42306 97632 8084 65.8 MiB 0.82 0.01 2.97254 -656.061 -2.97254 2.97254 0.27 0.00439332 0.00408702 0.35847 0.333653 -1 -1 -1 -1 36 7822 26 1.05632e+07 3.82647e+06 638738. 2495.07 2.60 1.40665 1.28851 24820 128426 -1 7098 11 1611 3987 187232 44731 3.15649 3.15649 -738.429 -3.15649 0 0 786978. 3074.13 0.03 0.19 0.08 -1 -1 0.03 0.132772 0.123936 - k6_frac_N10_40nm.xml clma.pre-vpr.blif common 28.51 vpr 89.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 316 62 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91500 62 82 3672 3754 1 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2.93 1.43298 1.34768 31748 166456 -1 8164 13 2250 4803 238712 56339 4.07339 nan -791.038 -4.07339 0 0 1.01518e+06 3133.28 0.04 0.21 0.14 -1 -1 0.04 0.139599 0.132291 - k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 3.71 vpr 64.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66072 64 39 1371 1410 1 541 167 10 10 100 clb auto 25.0 MiB 0.50 3623 18986 4100 13819 1067 64.5 MiB 0.29 0.01 5.32461 -1004.72 -5.32461 5.32461 0.09 0.00297013 0.00265425 0.142744 0.129291 -1 -1 -1 -1 50 5495 30 3.44922e+06 3.44922e+06 295697. 2956.97 1.53 0.822979 0.71402 10016 58256 -1 4877 17 1881 5375 141590 30815 5.49357 5.49357 -1059.83 -5.49357 0 0 379824. 3798.24 0.01 0.18 0.05 -1 -1 0.01 0.130986 0.117787 - k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 6.57 vpr 65.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66956 229 197 1362 1559 1 570 496 16 16 256 io auto 25.8 MiB 0.92 5066 137836 36889 92766 8181 65.4 MiB 0.78 0.01 2.91431 -671.379 -2.91431 2.91431 0.27 0.00438808 0.00409538 0.327876 0.305574 -1 -1 -1 -1 36 8862 27 1.05632e+07 3.77258e+06 638738. 2495.07 2.96 1.41434 1.29776 24820 128426 -1 7675 13 1986 5211 265646 63312 3.18697 3.18697 -739.19 -3.18697 0 0 786978. 3074.13 0.03 0.23 0.10 -1 -1 0.03 0.155656 0.14507 - k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 12.40 vpr 77.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 171 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79424 131 114 3421 3535 1 1164 416 16 16 256 clb auto 36.2 MiB 3.40 10474 95088 26501 63930 4657 77.6 MiB 1.19 0.02 7.51043 -4391.12 -7.51043 7.51043 0.26 0.00746347 0.00670247 0.527413 0.462699 -1 -1 -1 -1 56 18313 31 1.05632e+07 9.21587e+06 942187. 3680.42 4.59 2.05209 1.78067 28136 192436 -1 15484 16 5183 22017 710369 128360 7.51944 7.51944 -4543.65 -7.51944 0 0 1.20185e+06 4694.72 0.04 0.55 0.15 -1 -1 0.04 0.349204 0.315387 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 24.75 vpr 82.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 285 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83992 10 10 2659 2669 0 1401 305 19 19 361 clb auto 39.3 MiB 4.57 26220 51605 13492 36245 1868 82.0 MiB 1.25 0.02 6.59302 -61.9652 -6.59302 nan 0.39 0.00827542 0.00731978 0.484089 0.41329 -1 -1 -1 -1 90 42829 31 1.55754e+07 1.53598e+07 2.09179e+06 5794.43 14.00 3.32602 2.79995 48131 439069 -1 39158 17 9518 58062 2365838 328796 6.83753 nan -64.8858 -6.83753 0 0 2.60973e+06 7229.16 0.08 1.03 0.29 -1 -1 0.08 0.41705 0.373851 - k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 3.76 vpr 63.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 8 63 761 824 0 435 134 10 10 100 clb auto 23.7 MiB 0.68 3999 11420 2063 8488 869 63.1 MiB 0.20 0.01 3.77984 -169.82 -3.77984 nan 0.09 0.00233479 0.00210219 0.0905659 0.0824737 -1 -1 -1 -1 58 6565 28 3.44922e+06 3.39532e+06 342720. 3427.20 1.56 0.557203 0.48462 10608 68480 -1 5918 16 2541 10577 323005 63220 4.22288 nan -188.35 -4.22288 0 0 435638. 4356.38 0.01 0.19 0.05 -1 -1 0.01 0.102623 0.0927145 - k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 13.58 vpr 77.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 167 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79220 20 116 3175 3291 1 1338 303 15 15 225 clb auto 36.1 MiB 3.06 14602 62340 15718 42273 4349 77.4 MiB 1.17 0.02 8.56273 -4519.63 -8.56273 8.56273 0.22 0.00757247 0.0068348 0.522644 0.463063 -1 -1 -1 -1 80 24018 43 9.10809e+06 9.0003e+06 1.12687e+06 5008.33 6.06 2.41987 2.10801 28171 234221 -1 21050 15 6703 26493 1041429 176822 9.09101 9.09101 -4756.62 -9.09101 0 0 1.41774e+06 6301.08 0.04 0.63 0.19 -1 -1 0.04 0.342199 0.310175 - k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 4.84 vpr 63.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 14 14 828 842 0 475 99 11 11 121 clb auto 24.1 MiB 0.91 4532 5343 748 4219 376 63.7 MiB 0.15 0.01 4.39029 -57.6027 -4.39029 nan 0.11 0.00227799 0.00202987 0.0718845 0.0655562 -1 -1 -1 -1 52 7728 41 4.36541e+06 3.82647e+06 379421. 3135.71 2.05 0.703343 0.603899 12531 77429 -1 6634 16 3040 13763 383785 71279 4.69105 nan -60.7462 -4.69105 0 0 499620. 4129.09 0.01 0.15 0.04 -1 -1 0.01 0.0814211 0.0751261 - k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 26.16 vpr 82.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 272 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84416 16 40 2839 2879 0 1511 328 19 19 361 clb auto 39.8 MiB 3.52 23598 55698 13292 40268 2138 82.4 MiB 1.28 0.02 6.48626 -238.484 -6.48626 nan 0.44 0.00886302 0.00735171 0.491212 0.417579 -1 -1 -1 -1 82 38584 40 1.55754e+07 1.46592e+07 1.91630e+06 5308.30 16.27 3.50905 2.95866 46331 403357 -1 35281 17 9680 52085 1891572 294823 6.8403 nan -243.508 -6.8403 0 0 2.40187e+06 6653.38 0.08 1.01 0.33 -1 -1 0.08 0.437668 0.392311 - k6_frac_N10_40nm.xml s298.pre-vpr.blif common 3.15 vpr 62.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 4 6 726 732 1 395 74 10 10 100 clb auto 23.4 MiB 0.73 3639 2709 340 2252 117 62.8 MiB 0.10 0.00 6.02711 -48.0055 -6.02711 6.02711 0.09 0.00207648 0.0018638 0.0538424 0.0494959 -1 -1 -1 -1 50 5470 24 3.44922e+06 3.44922e+06 295697. 2956.97 1.28 0.507359 0.443613 10016 58256 -1 4992 17 2195 9283 271197 50082 6.42868 6.42868 -51.2874 -6.42868 0 0 379824. 3798.24 0.01 0.12 0.03 -1 -1 0.01 0.0746748 0.0694149 - k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 13.59 vpr 87.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 250 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89136 29 106 4782 4888 1 1993 385 18 18 324 clb auto 44.4 MiB 2.46 13385 89985 21640 60579 7766 87.0 MiB 1.52 0.02 5.22969 -3570.14 -5.22969 5.22969 0.34 0.00938818 0.00831247 0.681949 0.588191 -1 -1 -1 -1 50 21612 42 1.37969e+07 1.34735e+07 1.08879e+06 3360.46 5.45 2.95573 2.52337 34656 222912 -1 19075 14 7130 20879 621675 127526 5.31212 5.31212 -3691.5 -5.31212 0 0 1.40279e+06 4329.61 0.05 0.59 0.17 -1 -1 0.05 0.416139 0.374046 - k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 13.45 vpr 85.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 228 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87964 38 304 4422 4726 1 1994 570 18 18 324 clb auto 43.2 MiB 2.50 13819 172996 49998 111442 11556 85.9 MiB 2.01 0.03 4.76683 -2916.88 -4.76683 4.76683 0.35 0.00939228 0.00841165 0.819185 0.712738 -1 -1 -1 -1 58 23055 36 1.37969e+07 1.22878e+07 1.26150e+06 3893.53 4.75 2.90623 2.51915 36592 261672 -1 20398 14 6469 17425 591858 126037 4.97859 4.97859 -3048.53 -4.97859 0 0 1.60510e+06 4954.00 0.05 0.63 0.21 -1 -1 0.05 0.450883 0.410575 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.73 vpr 65.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66644 41 35 1006 1041 0 604 160 12 12 144 clb auto 25.4 MiB 1.22 6515 13180 2173 9685 1322 65.1 MiB 0.26 0.01 4.58553 -134.055 -4.58553 nan 0.14 0.00299227 0.00267516 0.112623 0.102342 -1 -1 -1 -1 64 10841 30 5.3894e+06 4.5271e+06 575115. 3993.85 2.53 0.863068 0.745904 16224 115365 -1 9534 17 3641 17204 511035 92223 4.88481 nan -140.076 -4.88481 0 0 716128. 4973.11 0.02 0.28 0.09 -1 -1 0.02 0.142307 0.128311 - k6_frac_N10_40nm.xml spla.pre-vpr.blif common 15.03 vpr 76.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78680 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.0 MiB 2.88 16089 42000 9359 30203 2438 76.8 MiB 0.95 0.02 5.95204 -207.143 -5.95204 nan 0.30 0.00775355 0.00661099 0.401796 0.349405 -1 -1 -1 -1 68 27700 45 1.21262e+07 1.16411e+07 1.30851e+06 4527.71 7.55 2.17634 1.8524 34227 265321 -1 23554 19 8023 43603 1540936 228530 6.17174 nan -217.21 -6.17174 0 0 1.61843e+06 5600.10 0.05 0.82 0.21 -1 -1 0.05 0.356964 0.321301 - k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 3.30 vpr 65.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66732 52 122 1461 1583 1 472 237 10 10 100 clb auto 25.8 MiB 0.55 2690 30290 6635 22073 1582 65.2 MiB 0.30 0.01 4.95966 -1122.48 -4.95966 4.95966 0.09 0.00309899 0.0028239 0.143089 0.130468 -1 -1 -1 -1 46 4786 25 3.44922e+06 3.39532e+06 276332. 2763.32 1.07 0.637438 0.562157 9816 55112 -1 4250 13 1489 3922 122560 29939 5.00101 5.00101 -1209.26 -5.00101 0 0 354105. 3541.05 0.01 0.16 0.04 -1 -1 0.01 0.119116 0.108599 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 4.22 vpr 65.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66736 14 8 926 934 0 489 102 11 11 121 clb auto 25.9 MiB 0.87 5716 4667 5814 773 4648 393 65.2 MiB 0.12 0.00 5.1758 4.39004 -31.3924 -4.39004 nan 0.08 0.00178088 0.00159339 0.0633619 0.0585507 -1 -1 -1 -1 52 7329 33 4.36541e+06 4.31152e+06 379421. 3135.71 2.20 0.764911 0.665568 12531 77429 -1 6513 17 2865 12552 316734 63876 5.07045 nan -34.2643 -5.07045 0 0 499620. 4129.09 0.01 0.16 0.04 -1 -1 0.01 0.100679 0.092897 +k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 6.36 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68812 38 3 1113 1116 0 665 142 13 13 169 clb auto 28.1 MiB 1.08 10548 7468 13832 2493 9914 1425 67.2 MiB 0.23 0.01 7.37702 5.32001 -15.73 -5.32001 nan 0.12 0.00232644 0.00203595 0.107932 0.0969942 -1 -1 -1 -1 62 13388 40 6.52117e+06 5.44329e+06 663442. 3925.69 3.52 1.00129 0.877983 18875 132257 -1 11741 18 5422 26877 882518 148818 5.56885 nan -16.3181 -5.56885 0 0 821735. 4862.34 0.02 0.36 0.07 -1 -1 0.02 0.164374 0.151826 +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 6.24 vpr 65.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66700 9 19 897 916 0 559 109 11 11 121 clb auto 26.4 MiB 1.02 7140 6126 6609 990 5282 337 65.1 MiB 0.20 0.00 5.35916 4.63303 -75.5716 -4.63303 nan 0.10 0.00138137 0.00119951 0.0992015 0.0904761 -1 -1 -1 -1 70 9981 48 4.36541e+06 4.36541e+06 511363. 4226.14 3.71 1.03481 0.903319 13971 102581 -1 9236 20 4663 24137 775856 134967 5.15777 nan -81.91 -5.15777 0 0 640906. 5296.74 0.02 0.37 0.06 -1 -1 0.02 0.155463 0.140494 +k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 4.08 vpr 67.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68648 229 197 1364 1561 1 545 498 16 16 256 io auto 27.7 MiB 0.54 8834 4538 160311 47174 104392 8745 67.0 MiB 0.49 0.01 4.09828 3.00075 -655.912 -3.00075 3.00075 0.20 0.00228394 0.00210599 0.199935 0.183794 -1 -1 -1 -1 36 7805 27 1.05632e+07 3.88037e+06 638738. 2495.07 1.70 0.763949 0.703546 24820 128426 -1 7103 12 1701 4682 221888 53122 3.35736 3.35736 -731.549 -3.35736 0 0 786978. 3074.13 0.03 0.13 0.07 -1 -1 0.03 0.0913876 0.0861942 +k6_frac_N10_40nm.xml clma.pre-vpr.blif common 19.63 vpr 90.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 319 62 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 92520 62 82 3672 3754 1 2348 463 20 20 400 clb auto 49.5 MiB 2.88 53167 28547 136503 37288 90480 8735 90.4 MiB 2.11 0.03 11.2331 7.97399 -326.521 -7.97399 7.97399 0.34 0.00875297 0.00797138 0.847567 0.688107 -1 -1 -1 -1 88 44571 35 1.74617e+07 1.71922e+07 2.29517e+06 5737.92 10.39 3.83688 3.1762 53088 483428 -1 41011 17 14832 64712 2253455 355288 8.38548 8.38548 -344.884 -8.38548 0 0 2.86840e+06 7171.00 0.10 1.04 0.30 -1 -1 0.10 0.521148 0.466219 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.69 vpr 64.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 54 256 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66552 256 245 954 1199 0 584 555 18 18 324 io auto 25.1 MiB 0.19 10217 5340 128235 34840 87101 6294 65.0 MiB 0.34 0.01 4.93688 3.71329 -708.053 -3.71329 nan 0.26 0.00199948 0.00187995 0.119693 0.112603 -1 -1 -1 -1 36 8812 39 1.37969e+07 2.91028e+06 824466. 2544.65 1.82 0.672729 0.63177 31748 166456 -1 7817 13 2215 4847 223176 52694 4.15133 nan -780.347 -4.15133 0 0 1.01518e+06 3133.28 0.03 0.12 0.09 -1 -1 0.03 0.0775895 0.0741275 +k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 2.72 vpr 66.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 65 64 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67680 64 39 1371 1410 1 539 168 11 11 121 clb auto 26.8 MiB 0.33 5584 3554 15910 3123 11816 971 66.1 MiB 0.15 0.00 6.03227 5.37507 -1038.07 -5.37507 5.37507 0.08 0.00156771 0.00139193 0.0747596 0.0677057 -1 -1 -1 -1 44 6185 38 4.36541e+06 3.50311e+06 327165. 2703.84 1.27 0.53243 0.470835 11931 67129 -1 5007 15 2028 5618 150141 32799 5.22952 5.22952 -1076.2 -5.22952 0 0 426099. 3521.48 0.01 0.11 0.04 -1 -1 0.01 0.0857885 0.0796425 +k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 4.92 vpr 68.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69680 229 197 1362 1559 1 570 498 16 16 256 io auto 28.1 MiB 0.74 9108 4889 148473 42778 97578 8117 68.0 MiB 0.47 0.01 4.8348 3.14736 -669.02 -3.14736 3.14736 0.30 0.00226729 0.00207241 0.17999 0.165413 -1 -1 -1 -1 36 8500 42 1.05632e+07 3.88037e+06 638738. 2495.07 2.30 0.957058 0.879549 24820 128426 -1 7656 13 1979 5245 274588 68226 3.45161 3.45161 -741.384 -3.45161 0 0 786978. 3074.13 0.03 0.14 0.07 -1 -1 0.03 0.0922548 0.0865961 +k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 10.27 vpr 80.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 166 131 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 81932 131 114 3421 3535 1 1168 411 15 15 225 clb auto 39.7 MiB 2.11 17765 10281 92031 24314 63237 4480 80.0 MiB 0.79 0.01 8.75467 7.10514 -4204.38 -7.10514 7.10514 0.17 0.00510006 0.00460859 0.376436 0.322116 -1 -1 -1 -1 58 16799 43 9.10809e+06 8.9464e+06 849382. 3775.03 5.12 2.28086 1.94401 25035 174617 -1 14821 15 4952 19579 622719 112047 7.25821 7.25821 -4441.31 -7.25821 0 0 1.08042e+06 4801.85 0.03 0.47 0.10 -1 -1 0.03 0.312728 0.287837 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 19.60 vpr 83.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 285 10 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85448 10 10 2659 2669 0 1441 305 19 19 361 clb auto 42.5 MiB 2.94 32579 26449 48527 11753 35255 1519 83.4 MiB 0.90 0.02 8.51351 6.36561 -61.7098 -6.36561 nan 0.29 0.00762048 0.00590277 0.393677 0.31916 -1 -1 -1 -1 90 44070 44 1.55754e+07 1.53598e+07 2.09179e+06 5794.43 12.11 2.73293 2.25343 48131 439069 -1 39495 18 9987 58249 2505846 334449 6.84682 nan -65.1715 -6.84682 0 0 2.60973e+06 7229.16 0.08 0.99 0.28 -1 -1 0.08 0.39675 0.358216 +k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 3.52 vpr 64.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 61 8 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 8 63 761 824 0 464 132 10 10 100 clb auto 25.1 MiB 0.64 5202 4219 8172 1346 6226 600 64.3 MiB 0.09 0.00 4.68322 3.95136 -171.257 -3.95136 nan 0.06 0.00117832 0.00103729 0.0411713 0.0375951 -1 -1 -1 -1 62 6890 29 3.44922e+06 3.28753e+06 366588. 3665.88 1.84 0.563741 0.499247 10808 71624 -1 6383 18 3263 13910 450723 84886 4.2104 nan -190.423 -4.2104 0 0 454102. 4541.02 0.01 0.16 0.04 -1 -1 0.01 0.0848892 0.0789772 +k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 10.71 vpr 79.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 167 20 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 81228 20 116 3175 3291 1 1354 303 15 15 225 clb auto 39.0 MiB 2.04 21678 14434 62340 15479 42636 4225 79.3 MiB 0.81 0.01 11.5497 8.67217 -4535.6 -8.67217 8.67217 0.17 0.00598961 0.00491716 0.389418 0.339327 -1 -1 -1 -1 78 23275 41 9.10809e+06 9.0003e+06 1.10266e+06 4900.72 5.62 2.16304 1.89205 27947 230153 -1 20596 15 6319 24844 985205 167745 9.14545 9.14545 -4810.82 -9.14545 0 0 1.39226e+06 6187.84 0.04 0.44 0.14 -1 -1 0.04 0.265519 0.24418 +k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 3.65 vpr 64.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 14 14 828 842 0 484 98 11 11 121 clb auto 25.3 MiB 0.70 5838 4589 4598 577 3714 307 64.4 MiB 0.11 0.00 5.13552 4.41862 -57.2342 -4.41862 nan 0.08 0.00216019 0.00187605 0.0527162 0.0474817 -1 -1 -1 -1 54 7371 29 4.36541e+06 3.77258e+06 393282. 3250.26 1.86 0.551705 0.483513 12651 80029 -1 6708 16 2958 13782 384033 69922 4.93716 nan -62.34 -4.93716 0 0 511363. 4226.14 0.01 0.15 0.04 -1 -1 0.01 0.0854717 0.079196 +k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 23.21 vpr 83.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 276 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85224 16 40 2839 2879 0 1524 332 19 19 361 clb auto 43.1 MiB 2.38 33170 23812 55484 13930 38908 2646 83.2 MiB 0.98 0.02 8.45123 6.4916 -240.609 -6.4916 nan 0.30 0.00735271 0.00577674 0.43013 0.346976 -1 -1 -1 -1 82 38872 48 1.55754e+07 1.48747e+07 1.91630e+06 5308.30 15.94 3.73157 3.06855 46331 403357 -1 35345 20 9890 54530 2023172 305290 6.9919 nan -256.124 -6.9919 0 0 2.40187e+06 6653.38 0.07 0.96 0.35 -1 -1 0.07 0.455144 0.414767 +k6_frac_N10_40nm.xml s298.pre-vpr.blif common 2.45 vpr 63.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 4 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65500 4 6 726 732 1 394 72 10 10 100 clb auto 24.7 MiB 0.61 4227 3644 2903 384 2413 106 64.0 MiB 0.07 0.00 6.29092 5.97061 -49.6933 -5.97061 5.97061 0.06 0.0011726 0.00103084 0.0377402 0.0347094 -1 -1 -1 -1 50 5462 25 3.44922e+06 3.34143e+06 295697. 2956.97 0.92 0.356034 0.31648 10016 58256 -1 5052 19 2244 8824 249008 48074 6.12473 6.12473 -52.0854 -6.12473 0 0 379824. 3798.24 0.01 0.12 0.03 -1 -1 0.01 0.080217 0.0746323 +k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 10.95 vpr 87.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 246 29 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 89912 29 106 4782 4888 1 1971 381 18 18 324 clb auto 48.7 MiB 2.66 31912 12914 91461 22158 61224 8079 87.8 MiB 1.14 0.01 9.34045 5.08538 -3515.89 -5.08538 5.08538 0.26 0.00638819 0.00575669 0.565699 0.465182 -1 -1 -1 -1 50 20649 31 1.37969e+07 1.32579e+07 1.08879e+06 3360.46 4.26 2.39167 2.01576 34656 222912 -1 18390 14 6502 17795 514521 108732 5.44467 5.44467 -3642.89 -5.44467 0 0 1.40279e+06 4329.61 0.04 0.42 0.12 -1 -1 0.04 0.333311 0.305973 +k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 12.77 vpr 87.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 229 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 89956 38 304 4422 4726 1 2011 571 18 18 324 clb auto 46.9 MiB 2.05 33483 13735 180539 53183 115745 11611 87.8 MiB 1.66 0.02 7.36291 4.83236 -2990.06 -4.83236 4.83236 0.26 0.00680899 0.00622388 0.730543 0.637641 -1 -1 -1 -1 60 23373 35 1.37969e+07 1.23417e+07 1.30451e+06 4026.26 6.11 3.12581 2.73129 36916 268072 -1 20457 17 6818 18608 617442 129769 5.15119 5.15119 -3122.73 -5.15119 0 0 1.63833e+06 5056.57 0.05 0.48 0.15 -1 -1 0.05 0.367799 0.338547 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.48 vpr 65.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67480 41 35 1006 1041 0 592 161 12 12 144 clb auto 27.0 MiB 0.83 8414 6369 15019 2656 10738 1625 65.9 MiB 0.21 0.00 5.81314 4.61808 -132.961 -4.61808 nan 0.10 0.00201435 0.00179366 0.0926978 0.0839262 -1 -1 -1 -1 64 10589 23 5.3894e+06 4.58099e+06 575115. 3993.85 2.87 0.892311 0.78471 16224 115365 -1 9640 17 3842 18426 545262 97961 4.99365 nan -142.217 -4.99365 0 0 716128. 4973.11 0.03 0.35 0.10 -1 -1 0.03 0.188284 0.172824 +k6_frac_N10_40nm.xml spla.pre-vpr.blif common 13.16 vpr 77.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 215 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79808 16 46 2232 2278 0 1144 277 17 17 289 clb auto 38.2 MiB 1.83 22379 15624 39965 9015 28403 2547 77.9 MiB 0.68 0.01 8.06632 5.82643 -200.335 -5.82643 nan 0.23 0.00653831 0.00547397 0.306995 0.255726 -1 -1 -1 -1 70 24462 32 1.21262e+07 1.15872e+07 1.33894e+06 4633.02 8.07 2.37386 2.02136 34803 275938 -1 23042 19 7242 39793 1366468 212085 6.30161 nan -215.252 -6.30161 0 0 1.67721e+06 5803.51 0.05 0.63 0.16 -1 -1 0.05 0.303222 0.274342 +k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 2.59 vpr 66.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 52 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68136 52 122 1461 1583 1 474 236 10 10 100 clb auto 27.4 MiB 0.37 4398 2714 31583 7033 22612 1938 66.5 MiB 0.18 0.00 5.30829 4.88854 -1118.91 -4.88854 4.88854 0.06 0.00173145 0.00158417 0.0816441 0.0741193 -1 -1 -1 -1 48 4763 22 3.44922e+06 3.34143e+06 287248. 2872.48 1.12 0.524806 0.467815 9916 56712 -1 4187 14 1409 3627 116662 29178 5.05451 5.05451 -1201.54 -5.05451 0 0 366588. 3665.88 0.01 0.10 0.03 -1 -1 0.01 0.0817235 0.0765267 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt index cc7b62c6a7e..06a4bcb6915 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt @@ -1,20 +1,20 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml alu4.pre-vpr.blif common 5.15 vpr 63.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 106 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 14 8 926 934 0 505 128 13 13 169 clb auto 23.7 MiB 0.39 5320 9466 1544 7430 492 63.5 MiB 0.20 0.01 4.98964 -35.546 -4.98964 nan 0.16 0.00251625 0.00223401 0.0945898 0.085379 -1 -1 -1 -1 40 8155 39 2.178e+06 1.908e+06 430798. 2549.10 2.23 0.762692 0.650665 13014 85586 -1 7291 24 4695 18699 612030 108244 5.31783 nan -35.626 -5.31783 0 0 541003. 3201.20 0.02 0.33 0.07 -1 -1 0.02 0.150814 0.13295 - k6_N10_40nm.xml apex2.pre-vpr.blif common 6.81 vpr 64.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 126 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66296 39 3 1113 1117 0 649 168 14 14 196 clb auto 25.0 MiB 0.51 8161 14521 2331 10832 1358 64.7 MiB 0.30 0.01 5.83152 -17.3307 -5.83152 nan 0.19 0.00327303 0.00291207 0.125054 0.112287 -1 -1 -1 -1 56 14649 45 2.592e+06 2.268e+06 683928. 3489.43 3.11 0.783946 0.67859 17100 137604 -1 12055 22 6319 31081 1191742 177825 5.79636 nan -17.0558 -5.79636 0 0 875557. 4467.13 0.03 0.48 0.11 -1 -1 0.03 0.176297 0.156434 - k6_N10_40nm.xml apex4.pre-vpr.blif common 6.12 vpr 63.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 105 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 9 19 897 916 0 543 133 13 13 169 clb auto 23.6 MiB 0.47 6734 11998 2247 9058 693 63.2 MiB 0.26 0.01 5.30224 -88.3937 -5.30224 nan 0.16 0.00277568 0.00248416 0.111245 0.10094 -1 -1 -1 -1 56 11936 45 2.178e+06 1.89e+06 580647. 3435.78 2.98 0.824097 0.708448 14694 116443 -1 10212 27 5690 29063 1167825 181866 5.38635 nan -89.1109 -5.38635 0 0 743711. 4400.66 0.02 0.48 0.09 -1 -1 0.02 0.171957 0.151906 - k6_N10_40nm.xml bigkey.pre-vpr.blif common 6.47 vpr 64.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 93 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 263 197 1372 1603 1 490 553 17 17 289 io auto 24.6 MiB 0.28 4778 170728 50681 109298 10749 64.2 MiB 0.88 0.01 3.19105 -732.6 -3.19105 3.19105 0.29 0.00444133 0.00414189 0.352128 0.327314 -1 -1 -1 -1 34 7398 17 4.05e+06 1.674e+06 688919. 2383.80 2.76 1.3271 1.215 21366 134962 -1 6995 17 2392 10610 509085 104346 3.17804 3.17804 -782.762 -3.17804 0 0 845950. 2927.16 0.03 0.32 0.10 -1 -1 0.03 0.181779 0.167898 - k6_N10_40nm.xml clma.pre-vpr.blif common 30.50 vpr 89.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 436 62 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91460 383 82 3674 4077 1 2255 901 23 23 529 clb auto 43.8 MiB 1.76 30959 435901 143273 235791 56837 87.8 MiB 4.57 0.05 8.55335 -395.949 -8.55335 8.55335 0.57 0.011521 0.00974146 1.22739 1.05507 -1 -1 -1 -1 70 48766 40 7.938e+06 7.848e+06 2.49953e+06 4725.00 12.64 4.21839 3.57666 52134 511241 -1 43952 24 19574 92605 3927944 550062 8.47101 8.47101 -397.531 -8.47101 0 0 3.12202e+06 5901.73 0.11 1.74 0.41 -1 -1 0.11 0.663416 0.57888 - k6_N10_40nm.xml des.pre-vpr.blif common 5.88 vpr 62.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 102 256 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63636 256 245 954 1199 0 608 603 18 18 324 io auto 23.0 MiB 0.22 5227 148271 39552 101169 7550 62.1 MiB 0.69 0.01 4.37046 -770.45 -4.37046 nan 0.33 0.00429362 0.00409542 0.263968 0.251414 -1 -1 -1 -1 34 7404 17 4.608e+06 1.836e+06 779010. 2404.35 2.41 1.22781 1.15626 24000 152888 -1 6744 14 2452 5473 272585 59901 4.46945 nan -782.102 -4.46945 0 0 956463. 2952.05 0.03 0.22 0.12 -1 -1 0.03 0.141821 0.134018 - k6_N10_40nm.xml diffeq.pre-vpr.blif common 4.62 vpr 63.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 102 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65388 64 39 1371 1410 1 525 205 13 13 169 clb auto 24.1 MiB 0.32 3921 26177 5932 18684 1561 63.9 MiB 0.32 0.01 6.43054 -1169.36 -6.43054 6.43054 0.16 0.00298713 0.00270217 0.145753 0.131572 -1 -1 -1 -1 30 6223 39 2.178e+06 1.836e+06 350324. 2072.92 1.18 0.626373 0.545912 12006 67531 -1 5218 22 3090 9783 337940 60993 6.09481 6.09481 -1163.91 -6.09481 0 0 430798. 2549.10 0.01 0.26 0.05 -1 -1 0.01 0.150744 0.133108 - k6_N10_40nm.xml dsip.pre-vpr.blif common 7.16 vpr 64.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 97 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65576 229 197 1370 1567 1 538 523 16 16 256 io auto 24.5 MiB 0.29 5055 147943 44035 96679 7229 64.0 MiB 0.84 0.01 3.2095 -723.52 -3.2095 3.2095 0.25 0.00439778 0.00410483 0.327457 0.304273 -1 -1 -1 -1 34 8590 45 3.528e+06 1.746e+06 604079. 2359.69 3.67 1.47788 1.35056 18880 118149 -1 7508 16 2871 10488 535186 116741 3.28619 3.28619 -773.959 -3.28619 0 0 742044. 2898.61 0.03 0.31 0.09 -1 -1 0.03 0.167166 0.154045 - k6_N10_40nm.xml elliptic.pre-vpr.blif common 17.77 vpr 75.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 242 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77400 131 114 3421 3535 1 1197 487 18 18 324 clb auto 34.5 MiB 0.89 12132 123047 34177 83673 5197 75.6 MiB 1.37 0.02 7.4606 -4613.61 -7.4606 7.4606 0.33 0.00810581 0.00695927 0.560378 0.487409 -1 -1 -1 -1 52 19935 35 4.608e+06 4.356e+06 1.09957e+06 3393.73 5.31 2.48742 2.1439 27876 225772 -1 16865 24 7619 33177 1410533 212600 7.58148 7.58148 -4794.49 -7.58148 0 0 1.44575e+06 4462.18 0.05 0.82 0.17 -1 -1 0.05 0.442646 0.391497 - k6_N10_40nm.xml ex1010.pre-vpr.blif common 25.84 vpr 79.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 322 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81016 10 10 2659 2669 0 1386 342 20 20 400 clb auto 36.7 MiB 1.37 27552 61287 15872 43555 1860 79.1 MiB 1.33 0.02 7.05556 -66.589 -7.05556 nan 0.42 0.00818042 0.00678636 0.481651 0.408035 -1 -1 -1 -1 86 46648 32 5.832e+06 5.796e+06 2.18757e+06 5468.92 16.22 3.3084 2.77524 43296 457864 -1 40817 23 12321 76660 3960652 471991 6.89706 nan -66.7022 -6.89706 0 0 2.74971e+06 6874.27 0.09 1.55 0.38 -1 -1 0.09 0.488654 0.431177 - k6_N10_40nm.xml ex5p.pre-vpr.blif common 4.10 vpr 61.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 98 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 8 63 761 824 0 446 169 12 12 144 clb auto 22.7 MiB 0.28 4942 12778 2101 9758 919 62.0 MiB 0.13 0.01 4.47718 -204.583 -4.47718 nan 0.10 0.00216344 0.00193361 0.0452269 0.0410824 -1 -1 -1 -1 44 8061 45 1.8e+06 1.764e+06 394711. 2741.05 2.19 0.64483 0.556552 11464 79652 -1 6964 19 3697 15748 572693 99319 4.62135 nan -207.386 -4.62135 0 0 511253. 3550.37 0.01 0.17 0.04 -1 -1 0.01 0.0737609 0.0675818 - k6_N10_40nm.xml frisc.pre-vpr.blif common 18.44 vpr 75.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 251 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77320 20 116 3175 3291 1 1188 387 18 18 324 clb auto 34.6 MiB 0.98 15146 84927 21530 58089 5308 75.5 MiB 1.28 0.02 10.0229 -5171.77 -10.0229 10.0229 0.33 0.00873977 0.00797476 0.530643 0.47162 -1 -1 -1 -1 58 25204 50 4.608e+06 4.518e+06 1.23881e+06 3823.48 6.40 2.34822 2.02881 29168 251432 -1 21617 25 8510 38924 1908034 279685 10.0072 10.0072 -5231.56 -10.0072 0 0 1.57021e+06 4846.34 0.05 0.98 0.20 -1 -1 0.05 0.493797 0.440091 - k6_N10_40nm.xml misex3.pre-vpr.blif common 4.74 vpr 63.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 100 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 14 14 828 842 0 489 128 12 12 144 clb auto 23.4 MiB 0.39 5175 7856 1075 6307 474 63.2 MiB 0.17 0.01 4.84801 -64.1454 -4.84801 nan 0.13 0.00237316 0.00211186 0.0763038 0.069521 -1 -1 -1 -1 46 7690 36 1.8e+06 1.8e+06 409728. 2845.33 1.90 0.68048 0.582561 11608 81817 -1 6920 20 4140 18396 605767 102501 4.82071 nan -63.1482 -4.82071 0 0 527971. 3666.47 0.02 0.29 0.06 -1 -1 0.02 0.12603 0.112062 - k6_N10_40nm.xml pdc.pre-vpr.blif common 21.86 vpr 80.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 332 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82088 16 40 2839 2879 0 1508 388 21 21 441 clb auto 37.7 MiB 1.17 25399 76744 19217 54467 3060 80.2 MiB 1.51 0.03 6.92036 -251.161 -6.92036 nan 0.47 0.00885769 0.00740089 0.531173 0.448728 -1 -1 -1 -1 72 40612 31 6.498e+06 5.976e+06 2.09950e+06 4760.78 11.04 2.90977 2.44288 43822 429389 -1 36688 22 12583 72460 3185853 429873 7.06044 nan -257.312 -7.06044 0 0 2.62494e+06 5952.24 0.09 1.30 0.27 -1 -1 0.09 0.47556 0.41731 - k6_N10_40nm.xml s298.pre-vpr.blif common 3.96 vpr 61.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62952 4 6 726 732 1 389 94 12 12 144 clb auto 22.2 MiB 0.25 4089 5206 723 4335 148 61.5 MiB 0.09 0.00 7.44269 -59.1085 -7.44269 7.44269 0.10 0.00104361 0.000914441 0.0377587 0.0345446 -1 -1 -1 -1 40 6786 29 1.8e+06 1.512e+06 360446. 2503.10 1.34 0.413858 0.360142 11036 71301 -1 5886 21 3075 15208 517485 86492 7.26292 7.26292 -60.1433 -7.26292 0 0 452692. 3143.70 0.01 0.25 0.06 -1 -1 0.01 0.116222 0.103786 - k6_N10_40nm.xml s38584.1.pre-vpr.blif common 25.20 vpr 84.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 404 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86316 39 304 4677 4982 1 2030 747 23 23 529 clb auto 42.7 MiB 1.01 14904 261623 79531 168959 13133 84.3 MiB 2.43 0.03 5.31651 -3386.99 -5.31651 5.31651 0.57 0.010079 0.00906179 0.841925 0.734315 -1 -1 -1 -1 38 21753 42 7.938e+06 7.272e+06 1.42597e+06 2695.60 6.41 3.52156 3.02715 41046 290405 -1 19677 23 11025 32342 1182586 226448 5.01574 5.01574 -3392.1 -5.01574 0 0 1.79789e+06 3398.65 0.07 0.91 0.22 -1 -1 0.07 0.560332 0.490747 - k6_N10_40nm.xml seq.pre-vpr.blif common 6.68 vpr 63.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 112 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65376 41 35 1006 1041 0 592 188 13 13 169 clb auto 24.2 MiB 0.53 7217 15790 2751 11594 1445 63.8 MiB 0.29 0.01 4.98507 -144.608 -4.98507 nan 0.16 0.00308253 0.00273928 0.120489 0.109161 -1 -1 -1 -1 54 11911 44 2.178e+06 2.016e+06 560467. 3316.37 3.24 0.979146 0.844173 14526 113769 -1 10428 30 5280 24638 903866 142828 4.87201 nan -144.017 -4.87201 0 0 730287. 4321.22 0.02 0.46 0.10 -1 -1 0.02 0.199563 0.175824 - k6_N10_40nm.xml spla.pre-vpr.blif common 17.67 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 265 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76688 16 46 2232 2278 0 1137 327 19 19 361 clb auto 33.2 MiB 0.92 17307 56627 13789 39736 3102 74.9 MiB 1.05 0.02 6.63208 -224.84 -6.63208 nan 0.37 0.00697821 0.0058582 0.391341 0.336325 -1 -1 -1 -1 60 30174 42 5.202e+06 4.77e+06 1.43744e+06 3981.82 8.84 2.3335 1.98111 32910 290117 -1 25425 24 9835 57132 2445755 336723 6.52939 nan -226.972 -6.52939 0 0 1.79849e+06 4981.96 0.06 1.13 0.23 -1 -1 0.06 0.404897 0.357661 - k6_N10_40nm.xml tseng.pre-vpr.blif common 3.61 vpr 64.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 112 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65656 52 122 1461 1583 1 500 286 13 13 169 clb auto 24.5 MiB 0.22 3158 39808 8713 28658 2437 64.1 MiB 0.20 0.00 6.15771 -1276.75 -6.15771 6.15771 0.12 0.00151949 0.00138677 0.0725931 0.0655934 -1 -1 -1 -1 26 4848 34 2.178e+06 2.016e+06 310759. 1838.81 0.73 0.389324 0.342948 11502 59218 -1 4210 17 2436 6640 243507 54081 5.71256 5.71256 -1266.26 -5.71256 0 0 383419. 2268.75 0.01 0.20 0.05 -1 -1 0.01 0.123184 0.110004 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml alu4.pre-vpr.blif common 4.91 vpr 64.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 106 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 14 8 926 934 0 514 128 13 13 169 clb auto 25.5 MiB 0.26 7083 5448 9788 1646 7588 554 64.7 MiB 0.15 0.00 5.97999 5.05611 -36.7617 -5.05611 nan 0.12 0.00148321 0.00129161 0.0679953 0.0617759 -1 -1 -1 -1 44 7669 23 2.178e+06 1.908e+06 471456. 2789.68 2.75 0.831893 0.720002 13518 95550 -1 7054 22 4067 16637 523317 87764 5.0058 nan -36.2952 -5.0058 0 0 610661. 3613.38 0.02 0.22 0.05 -1 -1 0.02 0.107729 0.0979149 +k6_N10_40nm.xml apex2.pre-vpr.blif common 5.45 vpr 66.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 128 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67684 39 3 1113 1117 0 649 170 14 14 196 clb auto 26.6 MiB 0.33 11306 8269 11920 1732 9182 1006 66.1 MiB 0.22 0.01 7.69377 5.66253 -16.5951 -5.66253 nan 0.14 0.0022649 0.00196723 0.0992103 0.0892723 -1 -1 -1 -1 56 13927 44 2.592e+06 2.304e+06 683928. 3489.43 2.89 0.787426 0.691094 17100 137604 -1 12377 22 5754 26605 1002340 150693 5.6078 nan -16.6372 -5.6078 0 0 875557. 4467.13 0.02 0.32 0.07 -1 -1 0.02 0.136693 0.125427 +k6_N10_40nm.xml apex4.pre-vpr.blif common 4.23 vpr 64.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 105 9 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 9 19 897 916 0 542 133 13 13 169 clb auto 25.3 MiB 0.30 8391 6735 11320 1952 8674 694 64.4 MiB 0.18 0.01 6.17724 5.31226 -86.9474 -5.31226 nan 0.12 0.00238491 0.00209788 0.0788687 0.0719373 -1 -1 -1 -1 56 11713 33 2.178e+06 1.89e+06 580647. 3435.78 2.11 0.543082 0.475032 14694 116443 -1 9840 25 5479 27940 1052585 163171 5.34721 nan -87.0992 -5.34721 0 0 743711. 4400.66 0.02 0.32 0.06 -1 -1 0.02 0.122642 0.110483 +k6_N10_40nm.xml bigkey.pre-vpr.blif common 4.46 vpr 65.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 93 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67288 263 197 1372 1603 1 497 553 17 17 289 io auto 26.4 MiB 0.18 9146 4610 166190 47472 107803 10915 65.7 MiB 0.53 0.01 4.32883 3.19205 -751.534 -3.19205 3.19205 0.22 0.00219749 0.00194794 0.192948 0.175966 -1 -1 -1 -1 34 7284 17 4.05e+06 1.674e+06 688919. 2383.80 1.91 0.747795 0.681917 21366 134962 -1 6861 14 2305 8738 471382 100298 3.29238 3.29238 -791.887 -3.29238 0 0 845950. 2927.16 0.03 0.18 0.07 -1 -1 0.03 0.0886663 0.08254 +k6_N10_40nm.xml clma.pre-vpr.blif common 22.99 vpr 88.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 436 62 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 90652 383 82 3674 4077 1 2242 901 23 23 529 clb auto 47.8 MiB 1.18 60546 31685 440251 147763 235759 56729 88.1 MiB 3.47 0.04 12.5735 9.22505 -390.083 -9.22505 9.22505 0.45 0.00877321 0.00803484 1.08071 0.909904 -1 -1 -1 -1 70 48763 36 7.938e+06 7.848e+06 2.49953e+06 4725.00 10.11 3.40178 2.84763 52134 511241 -1 43533 21 17430 80185 3323118 476163 9.07936 9.07936 -387.93 -9.07936 0 0 3.12202e+06 5901.73 0.10 1.21 0.29 -1 -1 0.10 0.508039 0.448686 +k6_N10_40nm.xml des.pre-vpr.blif common 3.90 vpr 63.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 100 256 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 256 245 954 1199 0 602 601 18 18 324 io auto 24.3 MiB 0.15 10721 5420 140026 39341 93980 6705 63.9 MiB 0.42 0.01 5.97631 4.13264 -765.653 -4.13264 nan 0.25 0.0020053 0.00187678 0.147575 0.139546 -1 -1 -1 -1 34 7666 22 4.608e+06 1.8e+06 779010. 2404.35 1.54 0.633075 0.594925 24000 152888 -1 6972 15 2528 6105 319538 68984 4.28747 nan -801.598 -4.28747 0 0 956463. 2952.05 0.03 0.15 0.08 -1 -1 0.03 0.0834864 0.079197 +k6_N10_40nm.xml diffeq.pre-vpr.blif common 4.46 vpr 65.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 64 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67180 64 39 1371 1410 1 525 204 13 13 169 clb auto 25.8 MiB 0.31 6520 3916 21204 4010 16081 1113 65.6 MiB 0.27 0.01 7.55482 6.06737 -1159.7 -6.06737 6.06737 0.18 0.003443 0.00316736 0.139109 0.12543 -1 -1 -1 -1 30 6125 43 2.178e+06 1.818e+06 350324. 2072.92 1.46 0.788466 0.702487 12006 67531 -1 5178 22 3019 9742 337555 60954 5.95152 5.95152 -1177.43 -5.95152 0 0 430798. 2549.10 0.01 0.19 0.04 -1 -1 0.01 0.11622 0.105207 +k6_N10_40nm.xml dsip.pre-vpr.blif common 4.48 vpr 65.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 95 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67132 229 197 1370 1567 1 534 521 16 16 256 io auto 26.2 MiB 0.19 9562 4735 149266 43445 98316 7505 65.6 MiB 0.48 0.01 4.18888 3.1959 -736.239 -3.1959 3.1959 0.19 0.00226564 0.00209541 0.172523 0.158247 -1 -1 -1 -1 34 7794 33 3.528e+06 1.71e+06 604079. 2359.69 2.19 0.758038 0.690657 18880 118149 -1 7160 19 2717 9216 471971 103095 3.3317 3.3317 -798.533 -3.3317 0 0 742044. 2898.61 0.02 0.21 0.06 -1 -1 0.02 0.111339 0.10326 +k6_N10_40nm.xml elliptic.pre-vpr.blif common 13.58 vpr 77.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 241 131 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78864 131 114 3421 3535 1 1197 486 18 18 324 clb auto 37.1 MiB 0.54 22607 11749 126546 34749 85241 6556 77.0 MiB 0.92 0.01 10.1196 7.35398 -4585.48 -7.35398 7.35398 0.25 0.00500688 0.00453694 0.403499 0.341049 -1 -1 -1 -1 50 18922 32 4.608e+06 4.338e+06 1.06618e+06 3290.67 3.44 1.55452 1.32535 27232 214208 -1 16253 19 7367 30536 1267689 193203 7.26105 7.26105 -4670.93 -7.26105 0 0 1.36711e+06 4219.48 0.04 0.61 0.11 -1 -1 0.04 0.339667 0.306043 +k6_N10_40nm.xml ex1010.pre-vpr.blif common 23.28 vpr 81.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 316 10 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 82956 10 10 2659 2669 0 1391 336 20 20 400 clb auto 40.8 MiB 0.87 34173 27378 59853 15980 41901 1972 81.0 MiB 1.02 0.02 9.34252 6.78888 -65.5484 -6.78888 nan 0.31 0.00780115 0.00619201 0.432572 0.349828 -1 -1 -1 -1 88 47872 43 5.832e+06 5.688e+06 2.22978e+06 5574.46 16.41 3.76498 3.11287 43692 465500 -1 40197 24 12700 79693 4033407 473272 6.80998 nan -65.6831 -6.80998 0 0 2.79850e+06 6996.25 0.09 1.26 0.29 -1 -1 0.09 0.421009 0.3711 +k6_N10_40nm.xml ex5p.pre-vpr.blif common 4.03 vpr 63.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 95 8 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 8 63 761 824 0 447 166 12 12 144 clb auto 24.0 MiB 0.23 6388 4881 13846 2417 10426 1003 63.9 MiB 0.15 0.01 5.38222 4.4446 -201.57 -4.4446 nan 0.10 0.0021612 0.00201166 0.0602991 0.0553309 -1 -1 -1 -1 46 7969 39 1.8e+06 1.71e+06 409728. 2845.33 2.33 0.640527 0.567984 11608 81817 -1 6969 27 3861 16117 591553 100720 4.44193 nan -200.716 -4.44193 0 0 527971. 3666.47 0.01 0.20 0.04 -1 -1 0.01 0.0930208 0.0850464 +k6_N10_40nm.xml frisc.pre-vpr.blif common 15.36 vpr 77.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 249 20 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79300 20 116 3175 3291 1 1155 385 18 18 324 clb auto 37.5 MiB 0.57 23449 14674 85785 22555 57970 5260 77.4 MiB 0.86 0.01 13.9915 9.85955 -5064.76 -9.85955 9.85955 0.36 0.00518812 0.00473015 0.375569 0.324925 -1 -1 -1 -1 54 24717 46 4.608e+06 4.482e+06 1.13978e+06 3517.85 5.34 2.00436 1.71283 28200 234220 -1 20929 29 7959 35697 1712456 256751 9.75974 9.75974 -5111.13 -9.75974 0 0 1.48298e+06 4577.10 0.05 0.71 0.13 -1 -1 0.05 0.381404 0.339549 +k6_N10_40nm.xml misex3.pre-vpr.blif common 3.47 vpr 63.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 99 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65484 14 14 828 842 0 495 127 12 12 144 clb auto 25.1 MiB 0.26 6785 5201 6826 774 5709 343 63.9 MiB 0.10 0.00 6.08887 4.91247 -64.3251 -4.91247 nan 0.10 0.00150222 0.00134616 0.0447251 0.0409107 -1 -1 -1 -1 44 7811 41 1.8e+06 1.782e+06 394711. 2741.05 1.40 0.492209 0.435312 11464 79652 -1 6924 20 4019 17263 551288 95278 5.04493 nan -64.2968 -5.04493 0 0 511253. 3550.37 0.01 0.24 0.05 -1 -1 0.01 0.106579 0.0965979 +k6_N10_40nm.xml pdc.pre-vpr.blif common 17.45 vpr 81.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 330 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 83676 16 40 2839 2879 0 1467 386 21 21 441 clb auto 41.2 MiB 0.78 36890 24945 71990 18391 50424 3175 81.7 MiB 1.09 0.02 10.1773 7.09431 -258.357 -7.09431 nan 0.35 0.00651541 0.00583051 0.445898 0.359931 -1 -1 -1 -1 72 42025 42 6.498e+06 5.94e+06 2.09950e+06 4760.78 9.01 2.40714 1.97615 43822 429389 -1 35463 21 12440 72372 3086341 420076 7.18526 nan -260.461 -7.18526 0 0 2.62494e+06 5952.24 0.09 1.13 0.25 -1 -1 0.09 0.428209 0.378195 +k6_N10_40nm.xml s298.pre-vpr.blif common 3.58 vpr 63.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 86 4 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64908 4 6 726 732 1 396 96 12 12 144 clb auto 23.6 MiB 0.20 5047 4214 4476 509 3811 156 63.4 MiB 0.09 0.00 8.22999 7.1626 -56.5861 -7.1626 7.1626 0.10 0.00127359 0.0011384 0.0456131 0.0421391 -1 -1 -1 -1 38 7004 50 1.8e+06 1.548e+06 347776. 2415.11 1.56 0.480843 0.430228 10892 69136 -1 6169 23 3648 19435 701468 113085 7.00833 7.00833 -56.0805 -7.00833 0 0 439064. 3049.06 0.01 0.21 0.03 -1 -1 0.01 0.09092 0.0829136 +k6_N10_40nm.xml s38584.1.pre-vpr.blif common 47.18 vpr 86.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 404 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88680 39 304 4677 4982 1 2045 747 23 23 529 clb auto 46.5 MiB 0.75 45108 15162 254847 76917 164647 13283 86.6 MiB 1.64 0.02 9.61199 5.3655 -3362.15 -5.3655 5.3655 0.44 0.00679555 0.00619652 0.605609 0.521814 -1 -1 -1 -1 36 23003 46 7.938e+06 7.272e+06 1.36659e+06 2583.35 4.11 2.33544 2.00342 39990 270289 -1 20202 25 11198 32005 1222912 235642 5.42021 5.42021 -3467.48 -5.42021 0 0 1.67430e+06 3165.03 0.06 0.75 0.19 -1 -1 0.06 0.46165 0.407176 +k6_N10_40nm.xml seq.pre-vpr.blif common 6.02 vpr 65.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 113 41 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66840 41 35 1006 1041 0 592 189 13 13 169 clb auto 25.8 MiB 0.29 9486 7332 19159 3405 13914 1840 65.3 MiB 0.33 0.01 6.24344 5.08166 -147.244 -5.08166 nan 0.18 0.00313515 0.00279961 0.136721 0.121582 -1 -1 -1 -1 56 11939 50 2.178e+06 2.034e+06 580647. 3435.78 3.52 0.997007 0.871403 14694 116443 -1 10324 20 5127 24770 910918 144801 5.20387 nan -145.39 -5.20387 0 0 743711. 4400.66 0.02 0.29 0.06 -1 -1 0.02 0.117813 0.107036 +k6_N10_40nm.xml spla.pre-vpr.blif common 15.49 vpr 75.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 255 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77688 16 46 2232 2278 0 1142 317 18 18 324 clb auto 36.3 MiB 0.61 24484 16948 51077 11678 36839 2560 75.9 MiB 0.74 0.01 8.85685 6.23263 -214.486 -6.23263 nan 0.25 0.0056626 0.00447365 0.316066 0.258337 -1 -1 -1 -1 62 27299 43 4.608e+06 4.59e+06 1.32550e+06 4091.04 9.17 2.50414 2.08209 29816 263480 -1 24298 20 9391 53871 2167776 305985 6.52956 nan -216.506 -6.52956 0 0 1.62910e+06 5028.10 0.05 0.76 0.15 -1 -1 0.05 0.297609 0.265752 +k6_N10_40nm.xml tseng.pre-vpr.blif common 3.14 vpr 65.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 113 52 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66992 52 122 1461 1583 1 500 287 13 13 169 clb auto 26.4 MiB 0.19 6165 3259 40019 8603 29010 2406 65.4 MiB 0.20 0.00 7.76697 6.20124 -1275.15 -6.20124 6.20124 0.12 0.00156781 0.0014181 0.0808621 0.0730003 -1 -1 -1 -1 26 5124 30 2.178e+06 2.034e+06 310759. 1838.81 0.81 0.447445 0.401543 11502 59218 -1 4548 25 2647 7841 292976 65953 5.87644 5.87644 -1276.67 -5.87644 0 0 383419. 2268.75 0.01 0.18 0.03 -1 -1 0.01 0.116471 0.105499 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt index 9c78b87cb9f..a74307e5813 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu - hard_fpu_arch_timing.xml bfly.v common 10.66 vpr 62.66 MiB -1 -1 0.29 18880 1 0.04 -1 -1 31060 -1 -1 14 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64160 193 64 833 649 1 555 275 30 30 900 block_FPU auto 22.9 MiB 9.06 7227 73501 28110 42559 2832 62.7 MiB 0.24 0.00 2.985 -1449.57 -2.985 2.985 0.00 0.00129076 0.0012041 0.111382 0.10419 -1 -1 -1 -1 10011 18.0704 2627 4.74188 921 1045 352645 96816 1.6779e+06 169623 2.03108e+06 2256.75 6 48532 406344 -1 2.985 2.985 -1492.92 -2.985 -24.3711 -0.0851 0.33 -1 -1 62.7 MiB 0.08 0.141917 0.133178 62.7 MiB -1 0.09 4 - hard_fpu_arch_timing.xml bgm.v common 4.38 vpr 66.29 MiB -1 -1 0.37 19684 1 0.06 -1 -1 31568 -1 -1 0 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67880 257 32 1281 693 1 1048 299 38 38 1444 block_FPU auto 27.1 MiB 1.15 17732 96203 37615 55516 3072 66.3 MiB 0.97 0.01 2.985 -3196.19 -2.985 2.985 0.00 0.0058053 0.00549326 0.572424 0.541944 -1 -1 -1 -1 24861 23.7450 6446 6.15664 1897 2343 998279 268232 2.90196e+06 343832 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3400.32 -2.985 -32.9279 -0.0851 0.72 -1 -1 66.3 MiB 0.27 0.668829 0.633922 66.3 MiB -1 0.18 10 - hard_fpu_arch_timing.xml dscg.v common 11.83 vpr 63.13 MiB -1 -1 0.27 18916 1 0.05 -1 -1 30476 -1 -1 0 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 129 64 769 585 1 513 197 30 30 900 block_FPU auto 23.0 MiB 9.85 7095 47183 20094 26781 308 63.1 MiB 0.42 0.00 2.985 -1443.24 -2.985 2.985 0.00 0.00302745 0.00284785 0.254581 0.239617 -1 -1 -1 -1 9979 19.4902 2627 5.13086 790 910 348267 96422 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1537.32 -2.985 -21.8648 -0.0851 0.44 -1 -1 63.1 MiB 0.11 0.304162 0.286319 63.1 MiB -1 0.10 4 - hard_fpu_arch_timing.xml fir.v common 19.03 vpr 63.21 MiB -1 -1 0.34 19016 1 0.05 -1 -1 32588 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64724 161 32 993 808 1 587 198 32 32 1024 block_FPU auto 23.3 MiB 16.72 9692 44550 18401 25778 371 63.2 MiB 0.41 0.00 2.985 -1407.96 -2.985 2.985 0.00 0.00297922 0.00277214 0.239029 0.222609 -1 -1 -1 -1 12905 22.0222 3330 5.68259 990 1086 448603 120061 2.063e+06 171916 2.37490e+06 2319.23 5 57140 479124 -1 2.985 2.985 -1491.67 -2.985 -38.4653 -0.0851 0.53 -1 -1 63.2 MiB 0.13 0.291694 0.271864 63.2 MiB -1 0.12 5 - hard_fpu_arch_timing.xml mm3.v common 6.50 vpr 61.19 MiB -1 -1 0.23 18328 1 0.04 -1 -1 30736 -1 -1 0 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62656 193 32 545 422 1 386 228 22 22 484 block_FPU auto 21.8 MiB 4.95 4984 53124 22938 29850 336 61.2 MiB 0.32 0.00 2.985 -851.626 -2.985 2.985 0.00 0.00217515 0.00206622 0.171111 0.1626 -1 -1 -1 -1 6454 16.7636 1714 4.45195 565 565 194103 53991 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -877.472 -2.985 -13.5705 -0.0851 0.24 -1 -1 61.2 MiB 0.07 0.203477 0.193246 61.2 MiB -1 0.05 3 - hard_fpu_arch_timing.xml ode.v common 53.14 vpr 64.66 MiB -1 -1 0.41 19816 1 0.10 -1 -1 34200 -1 -1 141 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66208 130 72 1194 1103 1 571 345 19 19 361 io auto 24.6 MiB 50.95 5001 98274 32566 61072 4636 64.7 MiB 0.54 0.01 2.985 -1384.17 -2.985 2.985 0.00 0.00308436 0.00282904 0.260751 0.239819 -1 -1 -1 -1 6737 11.8193 1762 3.09123 1249 1362 304558 77526 653279 391968 795482. 2203.55 8 19802 160939 -1 2.985 2.985 -1385.47 -2.985 -52.8417 -0.0851 0.18 -1 -1 64.7 MiB 0.13 0.330036 0.303434 64.7 MiB -1 0.04 2 - hard_fpu_arch_timing.xml syn2.v common 3.85 vpr 62.39 MiB -1 -1 0.16 18524 1 0.04 -1 -1 30832 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63892 161 128 641 490 1 475 293 30 30 900 block_FPU auto 23.1 MiB 1.75 8105 81941 35762 45750 429 62.4 MiB 0.54 0.01 2.985 -1571.9 -2.985 2.985 0.00 0.00342016 0.0032503 0.298242 0.283689 -1 -1 -1 -1 10335 21.8038 2743 5.78692 780 976 327494 85675 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1595.62 -2.985 -16.3392 -0.0851 0.44 -1 -1 62.4 MiB 0.11 0.355509 0.338332 62.4 MiB -1 0.10 4 - hard_fpu_arch_timing.xml syn7.v common 7.45 vpr 112.47 MiB -1 -1 0.45 21564 1 0.08 -1 -1 32500 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 115168 161 128 1921 499 1 1760 309 54 54 2916 block_FPU auto 37.0 MiB 0.62 44624 112017 52264 59181 572 112.5 MiB 2.20 0.02 2.985 -8100.96 -2.985 2.985 0.00 0.0120269 0.0114133 1.31427 1.24716 -1 -1 -1 -1 60108 34.1717 15324 8.71177 4214 6760 3339753 839694 6.08571e+06 687663 6.89978e+06 2366.18 9 161598 1383069 -1 2.985 2.985 -8533.86 -2.985 -46.3798 -0.0851 1.55 -1 -1 112.5 MiB 0.90 1.61708 1.53715 112.5 MiB -1 0.39 20 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu +hard_fpu_arch_timing.xml bfly.v common 1.69 vpr 63.78 MiB -1 -1 0.13 18684 1 0.04 -1 -1 30412 -1 -1 0 193 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65312 193 64 833 649 1 513 261 30 30 900 block_FPU auto 24.2 MiB 0.32 11091 7034 74398 32654 41106 638 63.8 MiB 0.28 0.00 2.985 2.985 -1424.43 -2.985 2.985 0.00 0.00159102 0.00149083 0.154903 0.145699 -1 -1 -1 -1 9364 18.2891 2492 4.86719 779 887 316097 86405 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1464.04 -2.985 -27.2716 -0.0851 0.33 -1 -1 63.8 MiB 0.08 0.186823 0.176339 63.8 MiB -1 0.11 4 +hard_fpu_arch_timing.xml bgm.v common 2.89 vpr 66.42 MiB -1 -1 0.21 19836 1 0.05 -1 -1 31084 -1 -1 0 257 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68012 257 32 1281 693 1 999 299 38 38 1444 block_FPU auto 28.3 MiB 0.56 24417 20354 90209 37667 52028 514 66.4 MiB 0.59 0.01 2.985 2.985 -3279.31 -2.985 2.985 0.00 0.00306286 0.00289708 0.339134 0.321404 -1 -1 -1 -1 26869 26.9228 6935 6.94890 1862 2375 1114441 288875 2.90196e+06 343832 3.35777e+06 2325.33 7 79768 674274 -1 2.985 2.985 -3485.89 -2.985 -32.7577 -0.0851 0.55 -1 -1 66.4 MiB 0.24 0.412563 0.392015 66.4 MiB -1 0.17 10 +hard_fpu_arch_timing.xml dscg.v common 2.15 vpr 63.84 MiB -1 -1 0.16 18684 1 0.04 -1 -1 30748 -1 -1 0 129 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65368 129 64 769 585 1 513 198 32 32 1024 block_FPU auto 24.2 MiB 0.74 11272 7736 52614 22764 29600 250 63.8 MiB 0.24 0.00 2.985 2.985 -1450.41 -2.985 2.985 0.00 0.00146576 0.00137209 0.141162 0.132297 -1 -1 -1 -1 11188 21.8516 2890 5.64453 838 1049 418805 112428 2.063e+06 171916 2.37490e+06 2319.23 5 57140 479124 -1 2.985 2.985 -1553.53 -2.985 -21.7856 -0.0851 0.36 -1 -1 63.8 MiB 0.09 0.172509 0.162281 63.8 MiB -1 0.12 5 +hard_fpu_arch_timing.xml fir.v common 8.36 vpr 63.77 MiB -1 -1 0.21 18684 1 0.04 -1 -1 31156 -1 -1 0 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65300 161 32 993 808 1 562 198 32 32 1024 block_FPU auto 24.2 MiB 6.82 11288 7405 51462 21510 29704 248 63.8 MiB 0.24 0.00 2.985 2.985 -1332.96 -2.985 2.985 0.00 0.00145997 0.00135492 0.138155 0.128337 -1 -1 -1 -1 10782 19.2193 2771 4.93939 899 992 433591 120812 2.063e+06 171916 2.37490e+06 2319.23 5 57140 479124 -1 2.985 2.985 -1428.14 -2.985 -40.5929 -0.0851 0.44 -1 -1 63.8 MiB 0.09 0.17082 0.159463 63.8 MiB -1 0.11 5 +hard_fpu_arch_timing.xml mm3.v common 1.38 vpr 62.52 MiB -1 -1 0.12 18296 1 0.03 -1 -1 30628 -1 -1 0 193 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64024 193 32 545 422 1 385 229 30 30 900 block_FPU auto 22.7 MiB 0.18 8272 4968 58329 25699 32293 337 62.5 MiB 0.22 0.00 2.985 2.985 -855.954 -2.985 2.985 0.00 0.00103363 0.000972137 0.116063 0.109526 -1 -1 -1 -1 6670 17.3698 1756 4.57292 533 533 185005 50756 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -882.014 -2.985 -13.6953 -0.0851 0.31 -1 -1 62.5 MiB 0.05 0.136779 0.129322 62.5 MiB -1 0.09 4 +hard_fpu_arch_timing.xml ode.v common 2.88 vpr 64.91 MiB -1 -1 0.19 19452 1 0.07 -1 -1 33584 -1 -1 128 130 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66468 130 72 1194 1103 1 591 333 22 22 484 block_FPU auto 25.4 MiB 1.51 8920 6104 92573 27080 59763 5730 64.9 MiB 0.33 0.00 2.985 2.985 -1423.15 -2.985 2.985 0.00 0.00148876 0.00135475 0.152232 0.139158 -1 -1 -1 -1 8458 14.3356 2267 3.84237 1308 1755 428944 116306 882498 396552 1.07647e+06 2224.11 9 26490 217099 -1 2.985 2.985 -1454.47 -2.985 -48.7964 -0.0851 0.16 -1 -1 64.9 MiB 0.10 0.196644 0.180827 64.9 MiB -1 0.05 3 +hard_fpu_arch_timing.xml syn2.v common 2.86 vpr 62.56 MiB -1 -1 0.12 18680 1 0.03 -1 -1 30532 -1 -1 0 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64060 161 128 641 490 1 479 293 30 30 900 block_FPU auto 23.9 MiB 1.43 10930 8213 81941 35740 45812 389 62.6 MiB 0.29 0.00 2.985 2.985 -1573.71 -2.985 2.985 0.00 0.00170674 0.00161454 0.150112 0.142271 -1 -1 -1 -1 10469 21.9017 2773 5.80126 795 1003 347207 90839 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1600.15 -2.985 -16.078 -0.0851 0.41 -1 -1 62.6 MiB 0.10 0.187774 0.17827 62.6 MiB -1 0.10 4 +hard_fpu_arch_timing.xml syn7.v common 5.27 vpr 111.22 MiB -1 -1 0.24 21372 1 0.07 -1 -1 31944 -1 -1 0 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 113888 161 128 1921 499 1 1761 309 54 54 2916 block_FPU auto 38.1 MiB 0.38 74672 45797 118281 55728 61956 597 111.2 MiB 1.82 0.01 2.985 2.985 -8183.2 -2.985 2.985 0.00 0.00708224 0.00672565 1.09152 1.03992 -1 -1 -1 -1 61720 35.0682 15701 8.92102 4096 6553 3150232 794260 6.08571e+06 687663 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8633.26 -2.985 -40.8482 -0.0851 1.09 -1 -1 111.2 MiB 0.61 1.24899 1.19225 111.2 MiB -1 0.37 20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt index 985745ce71c..f279e94b037 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt @@ -1,8 +1,8 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - soft_fpu_arch_timing.xml bfly.v common 41.34 parmys 121.35 MiB -1 -1 28.71 124260 23 3.25 -1 -1 39816 -1 -1 1065 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84540 193 64 3908 3972 1 2590 1322 35 35 1225 clb auto 40.9 MiB 0.92 23821 566978 183866 374301 8811 82.6 MiB 3.62 0.05 15.2252 -3632.45 -15.2252 15.2252 0.00 0.00893832 0.00809078 0.765101 0.674928 -1 -1 -1 -1 41554 16.0502 10620 4.10197 16398 55146 3818752 563046 2.49624e+06 2.44122e+06 2.83731e+06 2316.17 20 66042 566079 -1 14.3186 14.3186 -3387.7 -14.3186 -31.8712 -0.0851 0.59 -1 -1 82.6 MiB 1.30 1.1781 1.04452 82.6 MiB -1 0.14 - soft_fpu_arch_timing.xml bgm.v common 91.63 parmys 261.79 MiB -1 -1 68.05 268076 18 8.02 -1 -1 47316 -1 -1 1490 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 98376 257 32 6040 6072 1 3862 1779 41 41 1681 clb auto 52.4 MiB 1.35 32284 896104 308252 576620 11232 96.1 MiB 5.96 0.07 12.7604 -5544.74 -12.7604 12.7604 0.00 0.0121239 0.0108644 1.11649 0.963883 -1 -1 -1 -1 53705 13.9132 13764 3.56580 24580 81256 5307364 800086 3.48649e+06 3.41543e+06 3.92715e+06 2336.20 24 90666 782499 -1 12.0246 12.0246 -5156.11 -12.0246 -31.3502 -0.0851 0.78 -1 -1 96.1 MiB 1.91 1.78217 1.54405 96.1 MiB -1 0.19 - soft_fpu_arch_timing.xml dscg.v common 37.96 parmys 121.48 MiB -1 -1 31.02 124396 24 1.46 -1 -1 38668 -1 -1 602 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72036 129 64 2192 2256 1 1525 795 27 27 729 clb auto 30.2 MiB 0.54 13360 240060 66463 162314 11283 70.3 MiB 1.50 0.02 16.4736 -1891.5 -16.4736 16.4736 0.00 0.00522672 0.00478088 0.373681 0.337968 -1 -1 -1 -1 23389 15.7821 5992 4.04318 10665 36046 2530253 367157 1.43263e+06 1.37991e+06 1.65895e+06 2275.65 21 39258 331839 -1 14.938 14.938 -1781.33 -14.938 -9.29425 -0.0851 0.32 -1 -1 70.3 MiB 0.86 0.642834 0.579879 70.3 MiB -1 0.07 - soft_fpu_arch_timing.xml fir.v common 30.01 parmys 107.04 MiB -1 -1 25.31 109604 16 0.75 -1 -1 35824 -1 -1 480 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69144 161 32 2044 2076 1 1154 673 24 24 576 clb auto 27.8 MiB 0.33 7067 186397 50839 130117 5441 67.5 MiB 1.00 0.02 10.7496 -1623.35 -10.7496 10.7496 0.00 0.00400883 0.00360476 0.266889 0.238205 -1 -1 -1 -1 11039 9.58247 2844 2.46875 5647 15675 1030099 156890 1.10943e+06 1.10026e+06 1.29802e+06 2253.51 23 30996 260004 -1 10.1243 10.1243 -1523.31 -10.1243 -41.6788 -0.0851 0.25 -1 -1 67.5 MiB 0.42 0.454829 0.403412 67.5 MiB -1 0.06 - soft_fpu_arch_timing.xml mm3.v common 19.71 parmys 76.30 MiB -1 -1 17.40 78128 11 0.25 -1 -1 34080 -1 -1 188 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62248 193 32 892 924 1 553 413 21 21 441 io auto 21.0 MiB 0.15 2944 81874 21125 56255 4494 60.8 MiB 0.37 0.01 7.4944 -557.676 -7.4944 7.4944 0.00 0.00203025 0.00187301 0.114304 0.105094 -1 -1 -1 -1 4300 7.78986 1136 2.05797 2073 4078 247328 39648 827486 430936 981244. 2225.04 17 23706 196899 -1 6.6809 6.6809 -514.232 -6.6809 -6.91814 -0.0851 0.19 -1 -1 60.8 MiB 0.13 0.187463 0.170377 60.8 MiB -1 0.04 - soft_fpu_arch_timing.xml ode.v common 40.64 parmys 125.57 MiB -1 -1 23.10 128584 24 4.17 -1 -1 44228 -1 -1 1412 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 94024 130 72 5151 5223 1 3426 1614 40 40 1600 clb auto 48.4 MiB 1.33 35991 777580 261625 505362 10593 91.8 MiB 5.34 0.06 15.9431 -5264.37 -15.9431 15.9431 0.00 0.0117408 0.0100826 1.01252 0.875255 -1 -1 -1 -1 60460 17.6732 15462 4.51973 24242 84687 5987586 871715 3.30999e+06 3.23663e+06 3.73324e+06 2333.28 21 86292 744004 -1 14.8488 14.8488 -4929.15 -14.8488 -50.5031 -0.0851 0.74 -1 -1 91.8 MiB 1.94 1.5713 1.36676 91.8 MiB -1 0.19 - soft_fpu_arch_timing.xml syn2.v common 62.84 parmys 154.08 MiB -1 -1 29.55 157776 24 7.67 -1 -1 48164 -1 -1 2381 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 146376 161 128 8330 8458 1 5909 2670 51 51 2601 clb auto 69.8 MiB 2.37 66146 1576445 571349 976282 28814 142.9 MiB 12.22 0.13 17.1016 -8352.63 -17.1016 17.1016 0.00 0.0199685 0.0180821 1.87397 1.60664 -1 -1 -1 -1 113775 19.4487 28920 4.94359 45588 170928 12281742 1779631 5.50353e+06 5.45769e+06 6.13592e+06 2359.06 21 140346 1220799 -1 15.9299 15.9299 -7817.18 -15.9299 -29.0971 -0.0851 1.30 -1 -1 142.9 MiB 4.07 2.89569 2.48638 142.9 MiB -1 0.35 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +soft_fpu_arch_timing.xml bfly.v common 25.70 parmys 119.72 MiB -1 -1 16.23 122596 23 3.17 -1 -1 39160 -1 -1 1061 193 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85484 193 64 3908 3972 1 2576 1318 35 35 1225 clb auto 43.7 MiB 0.48 79910 23275 535820 162842 363780 9198 83.5 MiB 2.37 0.03 26.2008 15.2827 -3619.83 -15.2827 15.2827 0.00 0.00583731 0.00532945 0.539265 0.456016 -1 -1 -1 -1 41486 16.1111 10615 4.12233 21157 75339 5284993 776800 2.49624e+06 2.43205e+06 2.83731e+06 2316.17 22 66042 566079 -1 13.7882 13.7882 -3355.71 -13.7882 -32.1044 -0.0851 0.41 -1 -1 83.5 MiB 1.36 0.900525 0.772298 83.5 MiB -1 0.14 +soft_fpu_arch_timing.xml bgm.v common 60.02 parmys 257.67 MiB -1 -1 43.09 263856 18 7.15 -1 -1 47244 -1 -1 1479 257 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 98424 257 32 6040 6072 1 3846 1768 41 41 1681 clb auto 55.7 MiB 0.67 136608 31559 920764 325700 583886 11178 96.1 MiB 4.28 0.05 28.1556 12.6901 -5506.58 -12.6901 12.6901 0.00 0.00823797 0.00745153 0.848573 0.704986 -1 -1 -1 -1 53037 13.7973 13649 3.55073 23421 74765 4846056 742834 3.48649e+06 3.39022e+06 3.92715e+06 2336.20 20 90666 782499 -1 12.1348 12.1348 -5104.31 -12.1348 -30.6427 -0.0851 0.55 -1 -1 96.1 MiB 1.45 1.31763 1.11876 96.1 MiB -1 0.18 +soft_fpu_arch_timing.xml dscg.v common 21.73 parmys 118.54 MiB -1 -1 17.10 121384 24 1.26 -1 -1 37208 -1 -1 606 129 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73408 129 64 2192 2256 1 1520 799 27 27 729 clb auto 32.0 MiB 0.25 37820 13615 252807 71072 169981 11754 71.7 MiB 1.02 0.01 24.7174 16.2048 -1915.25 -16.2048 16.2048 0.00 0.00319424 0.00292766 0.253046 0.226671 -1 -1 -1 -1 23619 15.9912 6076 4.11374 10729 37676 2562082 383443 1.43263e+06 1.38908e+06 1.65895e+06 2275.65 22 39258 331839 -1 14.4972 14.4972 -1770.59 -14.4972 -8.16584 -0.0851 0.23 -1 -1 71.7 MiB 0.66 0.44222 0.396859 71.7 MiB -1 0.07 +soft_fpu_arch_timing.xml fir.v common 18.98 parmys 104.27 MiB -1 -1 16.05 106772 16 0.65 -1 -1 35424 -1 -1 473 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71212 161 32 2044 2076 1 1153 666 24 24 576 clb auto 29.5 MiB 0.16 22592 6905 180900 49669 126169 5062 69.5 MiB 0.57 0.01 16.2554 10.8177 -1611.57 -10.8177 10.8177 0.00 0.00217865 0.00192073 0.148828 0.132433 -1 -1 -1 -1 10858 9.43354 2814 2.44483 5861 16059 1047087 162683 1.10943e+06 1.08421e+06 1.29802e+06 2253.51 24 30996 260004 -1 10.1035 10.1035 -1503.91 -10.1035 -41.9575 -0.0851 0.18 -1 -1 69.5 MiB 0.27 0.263872 0.235975 69.5 MiB -1 0.05 +soft_fpu_arch_timing.xml mm3.v common 12.80 parmys 74.96 MiB -1 -1 11.19 76756 11 0.24 -1 -1 33096 -1 -1 188 193 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63472 193 32 892 924 1 551 413 21 21 441 io auto 22.3 MiB 0.07 8826 2864 88022 23644 59473 4905 62.0 MiB 0.32 0.00 9.16995 7.25696 -552.465 -7.25696 7.25696 0.00 0.000933453 0.000846072 0.098381 0.0901077 -1 -1 -1 -1 4134 7.53005 1108 2.01821 2160 4743 285352 45613 827486 430936 981244. 2225.04 23 23706 196899 -1 6.70177 6.70177 -514.125 -6.70177 -7.31444 -0.0851 0.13 -1 -1 62.0 MiB 0.10 0.148211 0.135458 62.0 MiB -1 0.05 +soft_fpu_arch_timing.xml ode.v common 26.43 parmys 123.43 MiB -1 -1 13.73 126388 24 3.93 -1 -1 45256 -1 -1 1403 130 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 100336 130 72 5151 5223 1 3359 1605 40 40 1600 clb auto 52.6 MiB 0.64 118795 35523 743652 244138 490210 9304 98.0 MiB 3.58 0.04 28.0949 16.0769 -5246.14 -16.0769 16.0769 0.00 0.00769968 0.00700229 0.751948 0.617028 -1 -1 -1 -1 59826 17.8372 15257 4.54890 23759 85913 6076912 889657 3.30999e+06 3.216e+06 3.73324e+06 2333.28 20 86292 744004 -1 15.2896 15.2896 -4910.83 -15.2896 -56.4251 -0.0851 0.53 -1 -1 98.0 MiB 1.60 1.19686 1.00822 98.0 MiB -1 0.18 +soft_fpu_arch_timing.xml syn2.v common 41.96 parmys 149.56 MiB -1 -1 17.16 153148 24 7.18 -1 -1 43992 -1 -1 2370 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 140116 161 128 8330 8458 1 5899 2659 51 51 2601 clb auto 76.2 MiB 1.15 274570 64420 1567764 565755 975262 26747 136.8 MiB 9.02 0.09 39.1135 16.9598 -8268.93 -16.9598 16.9598 0.00 0.0148804 0.0136535 1.56721 1.24827 -1 -1 -1 -1 111825 19.1481 28457 4.87277 45367 166434 11972783 1740291 5.50353e+06 5.43247e+06 6.13592e+06 2359.06 21 140346 1220799 -1 15.9299 15.9299 -7700.02 -15.9299 -28.1506 -0.0851 0.93 -1 -1 136.8 MiB 3.15 2.40226 1.95187 136.8 MiB -1 0.32 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt index 2054d1011a1..c2c54f3903c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt @@ -1,24 +1,24 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 240.41 vpr 1.80 GiB 274 1048 36 59 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1886012 22 252 53001 29054 7 22984 1419 89 66 5874 DSP auto 1200.1 MiB 62.75 248316 1021579 298715 629192 93672 1841.8 MiB 68.63 0.51 7.79847 -44076.4 -6.79847 3.16357 0.04 0.165964 0.147061 22.0804 19.3916 348037 15.1637 76678 3.34080 64297 133419 118695520 34142571 0 0 1.08074e+08 18398.6 17 1714760 18504579 -1 8.25872 3.11653 -42832.7 -7.25872 0 0 39.08 -1 -1 1841.8 MiB 30.91 29.1651 25.7894 1841.8 MiB -1 9.35 - stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 221.39 vpr 1.47 GiB 36 1585 10 10 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1538160 3 33 48977 39238 1 26095 1641 54 40 2160 LAB auto 1221.8 MiB 84.83 286068 978816 295772 657268 25776 1394.2 MiB 66.20 0.76 87.9237 -89444.7 -86.9237 87.9237 0.01 0.146793 0.123189 13.268 11.0829 379754 14.5550 90020 3.45023 82718 219511 74496266 16257762 0 0 3.96436e+07 18353.5 24 632584 6763270 -1 71.937 71.937 -113847 -70.937 0 0 15.28 -1 -1 1448.2 MiB 25.20 20.4884 17.2546 1394.2 MiB -1 3.21 - stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 444.61 vpr 1.93 GiB 211 2277 3 210 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2019520 38 173 62892 59064 3 35370 2701 86 64 5504 M9K auto 1405.6 MiB 170.24 614048 2033317 732647 1250104 50566 1914.9 MiB 137.20 1.11 13.4281 -360550 -12.4281 8.02047 0.05 0.23718 0.189938 28.8989 23.0941 838072 23.6991 190423 5.38481 138127 489921 156343017 30753609 0 0 1.01286e+08 18402.3 18 1602300 17340426 -1 13.7513 7.61228 -381806 -12.7513 0 0 36.15 -1 -1 1914.9 MiB 51.84 41.0998 33.5135 1914.9 MiB -1 8.59 - stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 501.58 vpr 2.01 GiB 574 2786 16 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2102528 4 570 66175 54803 2 39221 3376 91 67 6097 io auto 1442.3 MiB 161.57 637050 2737396 996225 1655508 85663 2024.4 MiB 158.02 1.26 31.0835 -120493 -30.0835 7.14678 0.05 0.240469 0.215113 28.7629 24.2021 899667 22.9413 200386 5.10980 182427 712388 314287781 64497091 0 0 1.12154e+08 18394.9 22 1777086 19206576 -1 31.4681 7.0455 -124410 -30.4681 0 0 40.06 -1 -1 2024.4 MiB 90.83 43.0922 36.5972 2024.4 MiB -1 9.96 - stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 613.83 vpr 4.71 GiB 40 3697 172 1 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 4942100 19 21 171111 96274 1 69059 3910 194 144 27936 DSP auto 1879.7 MiB 115.33 765653 3945030 1609251 2318045 17734 4826.3 MiB 167.87 1.46 6.56186 -137549 -5.56186 3.59168 0.15 0.576478 0.517383 74.0936 66.3885 885829 12.8277 186548 2.70140 135284 168559 115764486 31200317 0 0 5.18916e+08 18575.2 10 8071764 88644687 -1 6.86266 4.08192 -171393 -5.86266 0 0 170.99 -1 -1 4826.3 MiB 38.25 90.8697 81.8728 4826.3 MiB -1 57.03 - stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 331.14 vpr 1.78 GiB 536 1955 7 4 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1867752 227 309 49176 40422 1 28301 2502 85 63 5355 io auto 1275.0 MiB 118.12 297917 2005906 751440 1231297 23169 1824.0 MiB 109.86 1.00 221.816 -136664 -220.816 221.816 0.03 0.177495 0.149764 22.2953 18.9612 392043 13.8546 93134 3.29130 81629 256552 61785790 11540590 0 0 9.84380e+07 18382.4 20 1549486 16842765 -1 194.877 194.877 -143592 -193.877 0 0 35.33 -1 -1 1824.0 MiB 25.15 30.8256 26.312 1824.0 MiB -1 8.89 - stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 254.24 vpr 1.60 GiB 36 1393 8 149 2 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1675928 3 33 52402 39411 1 26961 1588 73 54 3942 M9K auto 1241.5 MiB 98.93 308817 862861 247827 593176 21858 1636.6 MiB 62.77 0.68 18.2872 -344515 -17.2872 18.2872 0.02 0.157897 0.128343 14.8112 12.1152 431314 16.0024 99151 3.67866 81236 209217 91482078 19724978 0 0 7.26311e+07 18424.9 20 1148308 12423798 -1 18.3421 18.3421 -345738 -17.3421 0 0 26.16 -1 -1 1636.6 MiB 29.12 22.8904 19.0386 1636.6 MiB -1 6.51 - stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 112.25 vpr 1.21 GiB 251 955 1 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1271072 55 196 20131 19956 1 8273 1224 44 33 1452 io auto 1086.4 MiB 51.28 121891 590184 190135 382049 18000 1219.0 MiB 16.74 0.19 8.00991 -79285.3 -7.00991 8.00991 0.01 0.0547434 0.0433722 5.31094 4.24309 175526 21.2244 41043 4.96288 27288 110050 30231721 5468094 0 0 2.65070e+07 18255.5 16 423692 4510959 -1 8.24194 8.24194 -78833.9 -7.24194 0 0 10.69 -1 -1 1219.0 MiB 10.21 7.91932 6.48482 1219.0 MiB -1 2.12 - stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 255.51 vpr 1.50 GiB 255 2122 1 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1577872 84 171 36458 36247 3 20327 2406 62 46 2852 LAB auto 1227.6 MiB 129.85 282856 1613906 577988 956437 79481 1496.3 MiB 54.24 0.51 12.7635 -89890.6 -11.7635 4.81564 0.02 0.13392 0.10812 13.9969 11.3761 395367 19.4637 87910 4.32777 59014 216498 49458484 8714433 0 0 5.24492e+07 18390.3 15 836198 8956163 -1 12.8132 4.74014 -89522.7 -11.8132 0 0 19.60 -1 -1 1496.3 MiB 18.50 19.7465 16.2691 1496.3 MiB -1 4.60 - stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 314.95 vpr 2.14 GiB 69 2192 10 295 16 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2241312 36 33 57796 49182 1 19758 2582 105 78 8190 M9K auto 1352.5 MiB 98.71 254549 2375186 921212 1420848 33126 2188.8 MiB 78.05 0.73 9.75634 -115117 -8.75634 9.75634 0.04 0.165792 0.132975 21.7204 17.5791 406833 20.5960 91948 4.65489 55491 166503 116017937 30967034 0 0 1.50983e+08 18435.1 16 2375962 25880196 -1 8.76007 8.76007 -153174 -7.76007 0 0 52.19 -1 -1 2188.8 MiB 36.04 29.2444 24.0731 2188.8 MiB -1 14.84 - stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 253.58 vpr 2.06 GiB 478 1233 1 300 4 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2160324 202 276 35125 30509 3 21219 2016 106 79 8374 M9K auto 1184.1 MiB 78.17 275268 1593266 551386 986614 55266 2109.7 MiB 49.61 0.39 9.2665 -49067 -8.2665 3.57275 0.07 0.132325 0.103283 17.1511 13.6719 420825 19.8381 90110 4.24787 51659 142658 103986450 24159841 0 0 1.54357e+08 18432.8 12 2427254 26454832 -1 9.68883 3.86627 -55338.2 -8.68883 0 0 53.22 -1 -1 2109.7 MiB 28.24 22.2919 18.1524 2109.7 MiB -1 14.60 - stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 138.75 vpr 1.69 GiB 5 333 31 105 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1766856 3 2 14862 10304 26 7583 476 89 66 5874 DSP auto 1033.6 MiB 52.72 124138 182462 49732 129080 3650 1725.4 MiB 10.74 0.10 5.88079 -31819.8 -4.88079 4.5134 0.03 0.0620074 0.052736 6.45505 5.4875 179249 23.7196 37106 4.91015 18387 40581 28916864 7312373 0 0 1.08074e+08 18398.6 14 1714760 18504579 -1 6.28555 4.43959 -39032.4 -5.28555 0 0 38.39 -1 -1 1725.4 MiB 8.42 8.94725 7.69206 1725.4 MiB -1 9.13 - stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 306.68 vpr 2.16 GiB 693 1797 25 16 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2263960 35 658 51416 37539 1 27427 2531 108 80 8640 io auto 1279.4 MiB 81.16 241934 2243861 754419 1344439 145003 2210.9 MiB 89.43 0.73 41.8615 -66574.8 -40.8615 41.8615 0.05 0.188177 0.163426 25.8422 22.4375 341602 13.1806 80002 3.08685 77035 236832 91449571 21610430 0 0 1.59375e+08 18446.1 27 2505018 27321913 -1 38.4065 38.4065 -64812.4 -37.4065 0 0 54.97 -1 -1 2210.9 MiB 32.24 37.3082 32.5377 2210.9 MiB -1 15.05 - stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 210.13 vpr 2.23 GiB 753 1113 5 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2333568 13 740 25173 25306 1 12716 1903 117 87 10179 io auto 1130.7 MiB 61.79 151917 1239643 452352 735278 52013 2278.9 MiB 28.83 0.25 9.32912 -33745.1 -8.32912 8.97758 0.06 0.0738163 0.0638134 8.87581 7.31746 194710 15.3206 43227 3.40129 29693 108615 25829106 4900313 0 0 1.87944e+08 18463.9 12 2952054 32219012 -1 9.94244 8.79357 -35834.6 -8.94244 0 0 64.11 -1 -1 2278.9 MiB 9.60 12.1982 10.2214 2278.9 MiB -1 18.15 - stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 318.93 vpr 1.67 GiB 117 2338 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1755828 79 38 66795 54922 1 35698 2455 65 48 3120 LAB auto 1328.0 MiB 134.18 278809 1724071 544940 1146248 32883 1591.7 MiB 106.67 0.89 10.5464 -202407 -9.54638 10.5464 0.02 0.1746 0.139886 18.8537 15.1957 365710 10.2454 86560 2.42499 84230 195736 44412238 7890024 0 0 5.74574e+07 18415.8 16 913942 9818425 -1 10.2871 10.2871 -211712 -9.28709 0 0 21.78 -1 -1 1628.9 MiB 18.87 26.6694 21.8451 1591.7 MiB -1 4.70 - stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 189.20 vpr 1.66 GiB 213 1565 26 4 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1740300 139 74 57121 41054 1 24001 1808 75 56 4200 DSP auto 1288.3 MiB 56.40 167389 1300988 426055 839266 35667 1699.5 MiB 56.62 0.52 5.92747 -26440.3 -4.92747 5.12571 0.03 0.163778 0.14022 19.7799 16.8165 226209 9.42655 53807 2.24224 52155 95084 47723189 13084284 0 0 7.74167e+07 18432.5 19 1223026 13250712 -1 6.18889 5.28844 -34182.8 -5.18889 0 0 28.00 -1 -1 1699.5 MiB 17.47 27.5967 23.7139 1699.5 MiB -1 6.59 - stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 104.87 vpr 1.18 GiB 54 665 0 40 0 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1232208 2 52 16673 16662 2 12027 760 37 27 999 LAB auto 1064.4 MiB 40.46 185817 260785 68816 184545 7424 1165.1 MiB 13.84 0.17 6.43593 -22019.6 -5.43593 5.34219 0.01 0.0663137 0.0529365 5.36329 4.35061 252094 20.9676 58089 4.83149 56425 171226 68372675 13142469 0 0 1.81123e+07 18130.5 18 291844 3070977 -1 6.97302 5.70366 -28347.4 -5.97302 0 0 7.59 -1 -1 1183.7 MiB 20.02 8.72317 7.23639 1165.1 MiB -1 1.32 - stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 304.15 vpr 1.76 GiB 445 2156 19 52 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1847692 131 314 57881 45152 1 32833 2672 73 54 3942 io auto 1361.0 MiB 91.84 318946 2041412 717468 1272847 51097 1720.0 MiB 112.21 1.13 221.943 -77080.5 -220.943 221.943 0.03 0.22642 0.192763 26.2516 22.5036 431464 13.1709 103995 3.17455 107179 331669 90059672 17820477 0 0 7.26311e+07 18424.9 19 1148308 12423798 -1 191.341 191.341 -83524.8 -190.341 0 0 25.61 -1 -1 1725.7 MiB 33.11 36.9562 31.8075 1720.0 MiB -1 6.07 - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 56.10 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1212332 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1061.2 MiB 12.53 72155 253216 50624 190930 11662 1175.4 MiB 10.11 0.14 5.18599 -5515.92 -4.18599 2.85104 0.01 0.0377892 0.0327694 2.93008 2.45256 84093 6.76152 20141 1.61944 25550 34715 9357710 1681121 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 5.29142 2.82099 -5638.13 -4.29142 0 0 8.59 -1 -1 1175.4 MiB 3.99 4.67756 3.97624 1175.4 MiB -1 1.60 - stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 339.18 vpr 2.90 GiB 964 1119 19 34 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3043528 542 422 37277 26038 1 20403 2136 147 109 16023 io auto 1148.5 MiB 79.64 272838 1734636 659517 1007756 67363 2972.2 MiB 73.93 0.61 8.43041 -42423.1 -7.43041 8.08995 0.09 0.114426 0.101345 15.7114 13.3677 363091 17.7986 78522 3.84912 59722 139345 87871064 23006283 0 0 2.96647e+08 18513.8 19 4640960 50771684 -1 8.69484 7.49966 -42054.1 -7.69484 0 0 99.20 -1 -1 2972.2 MiB 24.86 21.4146 18.4508 2972.2 MiB -1 30.90 - stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 287.28 vpr 3.37 GiB 1107 725 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3531216 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 1059.1 MiB 60.75 187193 1324022 523278 764997 35747 3448.5 MiB 22.39 0.20 12.7682 -23323.6 -11.7682 6.27217 0.13 0.0592033 0.0490591 7.25586 6.09591 231524 27.1328 38817 4.54905 24809 96129 21440863 3812157 0 0 3.84009e+08 18544.0 14 5987112 65598998 -1 12.9996 6.14541 -26165.8 -11.9996 0 0 128.07 -1 -1 3448.5 MiB 8.23 9.74816 8.27075 3448.5 MiB -1 40.93 - stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 104.00 vpr 1.15 GiB 35 739 0 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1206076 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 1055.9 MiB 57.16 84377 244832 62116 178083 4633 1170.5 MiB 9.34 0.14 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0407227 0.0346923 3.31901 2.66458 119256 18.9777 28323 4.50716 18857 88786 20657004 3728094 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 7.35046 7.35046 -45160 -6.35046 0 0 8.61 -1 -1 1170.5 MiB 7.38 5.40776 4.46635 1170.5 MiB -1 1.72 - stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 25.34 vpr 990.99 MiB 35 78 0 8 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1014772 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 952.6 MiB 5.77 10189 9390 1103 7334 953 991.0 MiB 0.58 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00761951 0.00626889 0.283964 0.242647 14035 9.71280 3656 2.53010 3331 8155 2407464 497474 0 0 3.34790e+06 17437.0 10 54372 558374 -1 5.45077 4.46245 -3957.23 -4.45077 0 0 1.88 -1 -1 991.0 MiB 0.85 0.560139 0.494736 991.0 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 178.61 vpr 1.76 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1847720 22 252 53001 29054 7 22943 1413 89 66 5874 DSP auto 1238.2 MiB 42.50 785441 248898 952533 277008 615830 59695 1804.4 MiB 60.09 0.44 11.048 8.33765 -44315.5 -7.33765 3.31053 0.04 0.128285 0.116554 17.2068 14.794 345230 15.0683 75298 3.28654 62048 127819 110428826 31460146 0 0 1.08074e+08 18398.6 15 1714760 18504579 -1 8.80295 3.22112 -43540.1 -7.80295 0 0 18.55 -1 -1 1804.4 MiB 24.74 22.4983 19.5519 1804.4 MiB -1 10.19 +stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 183.59 vpr 1.47 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1544388 3 33 48977 39238 1 26189 1635 54 40 2160 LAB auto 1259.6 MiB 55.70 913357 292251 954807 280946 652655 21206 1395.6 MiB 73.67 0.73 102.633 87.8923 -93476.3 -86.8923 87.8923 0.01 0.118889 0.106403 14.8002 11.9745 394383 15.0614 93195 3.55910 86770 233493 79349155 17261071 0 0 3.96436e+07 18353.5 23 632584 6763270 -1 72.672 72.672 -124485 -71.672 0 0 6.59 -1 -1 1452.7 MiB 22.92 22.128 18.2926 1395.6 MiB -1 3.32 +stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 360.80 vpr 1.93 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2019012 38 173 62892 59064 3 35490 2705 86 64 5504 M9K auto 1470.0 MiB 114.27 1 617052 1999639 700440 1267006 32193 1878.2 MiB 144.11 1.11 27.1546 13.437 -358967 -12.437 8.02334 0.03 0.255174 0.196212 28.7307 22.3941 840456 23.6868 190561 5.37064 140639 501599 160003214 31544854 0 0 1.01286e+08 18402.3 17 1602300 17340426 -1 13.7513 7.61025 -381512 -12.7513 0 0 17.59 -1 -1 1878.2 MiB 44.84 40.0468 32.041 1878.2 MiB -1 9.80 +stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 429.97 vpr 2.01 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2105408 4 570 66175 54803 2 39253 3378 91 67 6097 io auto 1502.0 MiB 105.57 2 646400 2739558 982870 1670046 86642 1985.6 MiB 156.66 1.38 58.3021 30.6995 -120781 -29.6995 6.48152 0.05 0.223098 0.200113 28.6722 23.0036 931853 23.7427 207645 5.29059 202723 808343 408786124 86440105 0 0 1.12154e+08 18394.9 27 1777086 19206576 -1 31.3244 7.0356 -126420 -30.3244 0 0 19.29 -1 -1 1985.6 MiB 106.14 43.9459 35.9936 1985.6 MiB -1 10.50 +stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 461.22 vpr 4.63 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4858904 19 21 171111 96274 1 69189 3920 194 144 27936 DSP auto 2000.7 MiB 72.95 3 736062 3896690 1544963 2334548 17179 4745.0 MiB 155.85 1.54 8.95431 5.9973 -144922 -4.9973 3.38229 0.14 0.421582 0.369844 55.986 49.4464 859407 12.4217 180010 2.60183 139067 172677 119021364 31947616 0 0 5.18916e+08 18575.2 11 8071764 88644687 -1 6.22445 3.66474 -172467 -5.22445 0 0 88.40 -1 -1 4745.0 MiB 32.65 69.5002 61.9431 4745.0 MiB -1 63.83 +stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 260.17 vpr 1.74 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1828096 227 309 49176 40422 1 28286 2492 85 63 5355 io auto 1318.3 MiB 72.97 1 294102 1944612 718689 1202581 23342 1785.2 MiB 111.92 1.21 334.944 219.151 -136355 -218.151 219.151 0.04 0.23177 0.185498 22.1292 17.849 386971 13.6826 91633 3.23998 84451 274893 65203744 12074645 0 0 9.84380e+07 18382.4 20 1549486 16842765 -1 190.784 190.784 -152276 -189.784 0 0 16.46 -1 -1 1785.2 MiB 23.98 31.3417 25.6009 1785.2 MiB -1 8.74 +stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 201.52 vpr 1.60 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1677448 3 33 52402 39411 1 26915 1592 74 55 4070 M9K auto 1283.6 MiB 64.51 1 313744 856456 241378 601294 13784 1614.5 MiB 64.76 0.67 26.6374 18.392 -352998 -17.392 18.392 0.02 0.161927 0.129227 15.3284 12.2977 436799 16.2337 99324 3.69138 82951 220275 101115757 21740280 0 0 7.49652e+07 18419.0 23 1184216 12823585 -1 18.4565 18.4565 -355164 -17.4565 0 0 12.45 -1 -1 1614.5 MiB 28.40 23.2769 19.1718 1614.5 MiB -1 6.95 +stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 86.54 vpr 1.22 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1278736 55 196 20131 19956 1 8019 1227 44 33 1452 io auto 1106.9 MiB 34.97 264174 123065 585601 181370 380069 24162 1221.6 MiB 16.77 0.15 11.4541 8.37477 -85221.8 -7.37477 8.37477 0.01 0.0459827 0.0401336 6.12669 4.71993 177766 22.1764 41334 5.15644 28198 129628 35934453 6384347 0 0 2.65070e+07 18255.5 15 423692 4510959 -1 8.33268 8.33268 -83249.9 -7.33269 0 0 4.84 -1 -1 1221.6 MiB 9.62 8.49386 6.75426 1221.6 MiB -1 3.41 +stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 191.79 vpr 1.52 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1590420 84 171 36458 36247 3 20790 2367 61 45 2745 LAB auto 1267.3 MiB 81.45 720648 283198 1531863 524079 936471 71313 1468.0 MiB 59.69 0.47 18.575 13.0627 -93585.1 -12.0627 4.74826 0.02 0.133751 0.101046 16.6759 12.8291 395382 19.0307 88123 4.24158 61626 220577 49685974 8803747 0 0 5.05019e+07 18397.8 16 806090 8625815 -1 13.3875 4.68835 -94249.2 -12.3875 0 0 8.71 -1 -1 1486.0 MiB 15.75 22.1054 17.4525 1468.0 MiB -1 4.73 +stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 242.56 vpr 2.10 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2203044 36 33 57796 49182 1 19635 2569 105 78 8190 M9K auto 1407.4 MiB 66.69 791464 250120 2359227 910890 1421031 27306 2151.4 MiB 69.03 0.59 16.1586 10.1368 -104381 -9.13679 10.1368 0.04 0.150021 0.116231 19.0365 14.944 404831 20.6231 91490 4.66072 55298 173053 127957013 34281032 0 0 1.50983e+08 18435.1 14 2375962 25880196 -1 9.14404 9.14404 -149500 -8.14404 0 0 26.91 -1 -1 2151.4 MiB 36.76 25.2394 20.3316 2151.4 MiB -1 15.86 +stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 194.04 vpr 2.02 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2120592 202 276 35125 30509 3 21318 2020 106 79 8374 M9K auto 1222.0 MiB 50.40 986671 267666 1508172 523381 949193 35598 2070.9 MiB 49.00 0.39 11.3759 9.26548 -48475.6 -8.26548 3.33529 0.04 0.141226 0.106959 15.9435 12.2592 429424 20.1494 89684 4.20815 53710 152511 120492230 28061271 0 0 1.54357e+08 18432.8 13 2427254 26454832 -1 9.61434 3.56952 -53683.9 -8.61434 0 0 25.62 -1 -1 2070.9 MiB 29.72 20.7976 16.4493 2070.9 MiB -1 16.05 +stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 85.25 vpr 1.65 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1726980 3 2 14862 10304 26 7561 466 89 66 5874 DSP auto 1055.0 MiB 19.84 270018 117214 172036 45994 123462 2580 1686.5 MiB 10.03 0.10 9.28243 6.01869 -39114.1 -5.01869 4.08518 0.05 0.0630093 0.0580388 6.722 5.63193 170213 22.5896 35826 4.75461 18131 39933 29145420 7349754 0 0 1.08074e+08 18398.6 16 1714760 18504579 -1 6.15886 4.10146 -48278.1 -5.15886 0 0 18.54 -1 -1 1686.5 MiB 8.34 9.0919 7.75971 1686.5 MiB -1 10.44 +stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 244.08 vpr 2.11 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2215808 35 658 51416 37539 1 27424 2511 108 80 8640 io auto 1315.7 MiB 54.87 1 251917 2152071 724984 1286743 140344 2163.9 MiB 89.22 0.66 74.2949 42.7394 -67262.7 -41.7394 42.7394 0.11 0.164209 0.133322 22.9478 19.0876 358128 13.8204 82658 3.18983 77956 237354 113781969 26958054 0 0 1.59375e+08 18446.1 20 2505018 27321913 -1 40.4536 40.4536 -65567.3 -39.4536 0 0 28.03 -1 -1 2163.9 MiB 29.51 30.9219 26.042 2163.9 MiB -1 17.15 +stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 150.60 vpr 2.18 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2288012 13 740 25173 25306 1 12838 1890 117 87 10179 io auto 1157.0 MiB 38.37 599292 157888 1216610 423982 737752 54876 2234.4 MiB 31.48 0.38 14.8829 8.76456 -34576 -7.76456 8.70409 0.05 0.180848 0.151857 10.946 8.66397 200775 15.6476 43818 3.41501 31234 113917 27219910 5157022 0 0 1.87944e+08 18463.9 11 2952054 32219012 -1 9.15588 8.09218 -36950.2 -8.15588 0 0 31.40 -1 -1 2234.4 MiB 9.82 14.7216 11.9704 2234.4 MiB -1 19.18 +stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 279.74 vpr 1.68 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1764116 79 38 66795 54922 1 35224 2428 64 47 3008 LAB auto 1380.9 MiB 97.02 1 268287 1649940 503404 1107473 39063 1560.8 MiB 122.78 1.01 22.8938 10.5192 -202497 -9.51918 10.5192 0.03 0.17581 0.134211 21.3606 16.582 359112 10.1960 84742 2.40601 85648 207489 45894038 8018949 0 0 5.53261e+07 18393.0 17 880106 9448176 -1 10.0961 10.0961 -210217 -9.09605 0 0 9.73 -1 -1 1634.6 MiB 17.85 29.5446 23.5411 1560.8 MiB -1 6.71 +stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 159.55 vpr 1.66 GiB 213 1559 26 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1735592 139 74 57121 41054 1 23901 1802 75 56 4200 DSP auto 1330.0 MiB 48.81 657536 162365 1295200 408181 790147 96872 1664.2 MiB 48.99 0.37 8.96007 5.38815 -26383.2 -4.38815 5.13107 0.03 0.141819 0.116205 18.2948 15.2438 222037 9.29142 53200 2.22622 52616 96447 52913821 14348789 0 0 7.74167e+07 18432.5 22 1223026 13250712 -1 5.68048 5.58104 -33396.3 -4.68048 0 0 13.08 -1 -1 1664.2 MiB 16.85 25.8551 21.9463 1664.2 MiB -1 9.19 +stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 82.77 vpr 1.18 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1232808 2 52 16673 16662 2 11970 759 37 27 999 LAB auto 1087.4 MiB 26.11 329275 182496 253339 66599 180853 5887 1148.2 MiB 14.60 0.17 8.48983 6.31912 -21812.1 -5.31912 5.08034 0.00 0.074231 0.0564117 6.79754 5.19634 250865 20.9648 57898 4.83854 58768 177050 72729449 14016095 0 0 1.81123e+07 18130.5 23 291844 3070977 -1 6.7711 5.47952 -27099.2 -5.7711 0 0 3.13 -1 -1 1183.7 MiB 20.25 10.785 8.59916 1148.2 MiB -1 1.43 +stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 245.81 vpr 1.76 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1844232 131 314 57881 45152 1 32883 2670 73 54 3942 io auto 1411.7 MiB 65.76 1 312017 2002290 686807 1268658 46825 1677.7 MiB 109.35 1.05 300.2 218.773 -77846.7 -217.773 218.773 0.02 0.21645 0.176361 24.8335 20.3604 424105 12.9277 102692 3.13028 95928 287321 76027554 15229747 0 0 7.26311e+07 18424.9 19 1148308 12423798 -1 188.497 188.497 -81903 -187.497 0 0 12.10 -1 -1 1722.3 MiB 24.63 34.6185 28.8296 1677.7 MiB -1 6.42 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 39.89 vpr 1.16 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1213812 13 29 26295 20086 1 12646 791 39 29 1131 LAB auto 1076.6 MiB 8.33 231619 75107 234775 43541 180854 10380 1154.1 MiB 7.86 0.12 5.55061 5.16398 -5504.03 -4.16398 2.86102 0.01 0.0346728 0.0315016 2.55631 2.11207 87307 6.90501 21230 1.67906 25811 34329 9106433 1637889 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.36451 2.98815 -5707.14 -4.36451 0 0 3.52 -1 -1 1154.1 MiB 2.97 3.92388 3.31697 1154.1 MiB -1 1.75 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2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 3470396 403 704 15490 16194 1 8443 1837 167 124 20708 io auto 1075.8 MiB 34.73 580890 183895 1261389 465912 759977 35500 3389.1 MiB 18.07 0.17 21.2837 12.8498 -23740.4 -11.8498 6.01594 0.10 0.0528114 0.0410491 6.17736 4.93541 224259 26.5647 38487 4.55899 24297 97387 21330701 3812192 0 0 3.84009e+08 18544.0 15 5987112 65598998 -1 12.926 6.10097 -26548.2 -11.926 0 0 67.11 -1 -1 3389.1 MiB 6.81 8.38896 6.88343 3389.1 MiB -1 42.72 +stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 70.04 vpr 1.15 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1207840 18 17 16969 16357 1 6487 772 39 29 1131 LAB auto 1073.0 MiB 36.26 189359 78593 245032 60572 181809 2651 1152.0 MiB 7.48 0.10 11.1993 7.7388 -41982.4 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a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt index ad32242d902..a5b66d2ee80 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt @@ -1,41 +1,41 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml alu4.blif common 11.61 vpr 67.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 490 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69184 14 8 1536 1544 0 1075 512 25 25 625 clb auto 27.3 MiB 0.36 13907 125379 37375 86426 1578 67.6 MiB 0.92 0.01 13.7808 -101.412 -13.7808 nan 0.38 0.00351706 0.00307653 0.230026 0.203296 -1 -1 -1 -1 26 21244 40 1.587e+07 1.47e+07 -1 -1 7.83 1.39924 1.1896 22338 287359 -1 19467 17 6635 26447 1985465 198804 17.3063 nan -123.659 -17.3063 0 0 -1 -1 0.05 0.39 0.12 -1 -1 0.05 0.105099 0.0941024 - k4_n4_v7_bidir.xml apex2.blif common 22.22 vpr 70.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 626 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71692 38 3 1916 1919 0 1483 667 28 28 784 clb auto 29.5 MiB 0.29 19984 195838 60682 130920 4236 70.0 MiB 1.45 0.02 17.0385 -49.2963 -17.0385 nan 0.49 0.00449691 0.00389108 0.328393 0.287877 -1 -1 -1 -1 28 30181 48 2.028e+07 1.878e+07 -1 -1 17.00 1.80013 1.5249 28758 383844 -1 28376 15 9150 33071 2590424 247096 20.7907 nan -60.2269 -20.7907 0 0 -1 -1 0.07 0.68 0.22 -1 -1 0.07 0.170018 0.15064 - k4_n4_v7_bidir.xml apex4.blif common 9.32 vpr 64.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 434 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66272 9 19 1271 1290 0 989 462 23 23 529 clb auto 25.3 MiB 0.38 13918 105777 29780 74317 1680 64.7 MiB 0.80 0.01 13.9047 -226.083 -13.9047 nan 0.32 0.00309616 0.00274963 0.190094 0.170268 -1 -1 -1 -1 31 20642 28 1.323e+07 1.302e+07 -1 -1 5.45 1.02556 0.874569 20514 283063 -1 19844 22 7738 30852 2604644 234674 16.6245 nan -269.64 -16.6245 0 0 -1 -1 0.05 0.64 0.16 -1 -1 0.05 0.148675 0.128977 - k4_n4_v7_bidir.xml bigkey.blif common 11.94 vpr 70.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 492 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 69640 229 197 1815 2012 1 1190 869 29 29 841 io auto 27.9 MiB 0.38 11973 394644 125240 259207 10197 68.0 MiB 2.08 0.03 7.81345 -1864.07 -7.81345 7.81345 0.53 0.00544034 0.00496078 0.530962 0.484759 -1 -1 -1 -1 16 17634 29 2.187e+07 1.329e+07 -1 -1 6.87 1.81366 1.63082 24114 234671 -1 15615 17 6539 22470 1305981 155172 8.39336 8.39336 -2240 -8.39336 0 0 -1 -1 0.05 0.52 0.14 -1 -1 0.05 0.212997 0.192439 - k4_n4_v7_bidir.xml elliptic.blif common 38.32 vpr 90.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1023 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 92796 131 114 4855 4969 1 2112 1268 34 34 1156 clb auto 44.4 MiB 0.81 32596 556928 195696 354146 7086 90.6 MiB 3.80 0.04 24.1099 -12023.9 -24.1099 24.1099 0.75 0.0102584 0.0091465 0.934203 0.802866 -1 -1 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66324 9 19 1271 1290 0 989 462 23 23 529 clb auto 25.3 MiB 0.24 13905 125412 38326 85376 1710 64.8 MiB 0.93 0.01 18.3289 -292.406 -18.3289 nan 0.54 0.00295728 0.00263697 0.223166 0.199747 -1 -1 -1 -1 24 15651 33 1.323e+07 1.302e+07 -1 -1 24.88 1.17628 0.99802 39522 283015 -1 14291 16 7091 27457 2432804 329588 18.2498 nan -294.601 -18.2498 0 0 -1 -1 0.06 0.66 0.21 -1 -1 0.06 0.117459 0.103392 - k4_n4_v7_l1_bidir.xml bigkey.blif common 20.11 vpr 79.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 492 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81376 229 197 2152 2349 1 1586 918 29 29 841 io auto 30.2 MiB 0.23 13124 451277 143814 296619 10844 79.3 MiB 2.42 0.03 10.2071 -2455.12 -10.2071 10.2071 0.88 0.005948 0.00536127 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k4_n4_v7_l1_bidir.xml des.blif common 25.77 vpr 92.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 484 256 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 94864 256 245 1847 2092 0 1412 985 34 34 1156 io auto 28.9 MiB 0.48 17257 432097 143595 271357 17145 92.3 MiB 2.26 0.03 18.8241 -3130.1 -18.8241 nan 1.27 0.00658266 0.00603047 0.609402 0.558097 -1 -1 -1 -1 14 17359 30 3.072e+07 1.452e+07 -1 -1 17.02 2.07374 1.87856 59520 367032 -1 16289 18 8044 28971 1902864 353863 18.0321 nan -3199.72 -18.0321 0 0 -1 -1 0.10 0.80 0.29 -1 -1 0.10 0.267971 0.244445 - k4_n4_v7_l1_bidir.xml diffeq.blif common 11.64 vpr 67.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69448 64 39 1935 1974 1 1077 542 23 23 529 clb auto 27.9 MiB 0.36 10163 148545 42077 102375 4093 67.8 MiB 1.08 0.02 12.0441 -2875.38 -12.0441 12.0441 0.56 0.00430479 0.0037965 0.308045 0.272397 -1 -1 -1 -1 16 10332 33 1.323e+07 1.317e+07 -1 -1 6.74 1.30841 1.12025 28434 179743 -1 9483 18 6528 24074 1365996 234850 12.4631 12.4631 -3015.42 -12.4631 0 0 -1 -1 0.04 0.61 0.13 -1 -1 0.04 0.194916 0.171717 - k4_n4_v7_l1_bidir.xml dsip.blif common 18.79 vpr 77.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 443 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79492 229 197 1815 2012 1 1190 869 29 29 841 io auto 28.0 MiB 0.38 12024 411224 134532 266541 10151 77.3 MiB 2.23 0.03 11.1435 -2606.08 -11.1435 11.1435 0.94 0.00566744 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65060 8 63 1072 1135 0 898 438 22 22 484 clb auto 24.2 MiB 0.28 11915 106806 31455 73557 1794 63.5 MiB 0.77 0.01 16.2558 -718.217 -16.2558 nan 0.47 0.00280855 0.00253426 0.195106 0.176517 -1 -1 -1 -1 24 13413 30 1.2e+07 1.101e+07 -1 -1 17.58 1.01507 0.875233 36000 257712 -1 11900 15 6787 23733 1853955 288518 16.2529 nan -726.803 -16.2529 0 0 -1 -1 0.05 0.53 0.19 -1 -1 0.05 0.103489 0.0915351 - k4_n4_v7_l1_bidir.xml frisc.blif common 94.05 vpr 121.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1094 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 123920 20 116 4445 4561 1 2290 1230 36 36 1296 clb auto 44.1 MiB 0.99 38255 580886 202911 367450 10525 120.6 MiB 4.25 0.05 29.223 -16576.9 -29.223 29.223 1.43 0.0105708 0.00897893 0.999254 0.851085 -1 -1 -1 -1 26 40614 39 3.468e+07 3.282e+07 -1 -1 79.50 4.26322 3.57492 104992 763300 -1 37284 18 13336 60167 5347576 900846 28.6821 28.6821 -16996 -28.6821 0 0 -1 -1 0.20 1.82 0.58 -1 -1 0.20 0.421201 0.366517 - k4_n4_v7_l1_bidir.xml misex3.blif common 17.56 vpr 65.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 450 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67284 14 14 1411 1425 0 1056 478 24 24 576 clb auto 26.1 MiB 0.40 13799 121898 36530 83432 1936 65.7 MiB 0.91 0.01 18.1166 -222.755 -18.1166 nan 0.58 0.00323875 0.00286176 0.229781 0.204181 -1 -1 -1 -1 21 15917 38 1.452e+07 1.35e+07 -1 -1 12.60 1.01596 0.869596 39160 271852 -1 13861 19 6925 26912 1892268 324238 17.8372 nan -222.89 -17.8372 0 0 -1 -1 0.06 0.66 0.21 -1 -1 0.06 0.14886 0.130215 - k4_n4_v7_l1_bidir.xml pdc.blif common 418.57 vpr 161.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1606 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 164932 16 40 4591 4631 0 3616 1662 43 43 1849 clb auto 50.4 MiB 1.48 71388 995502 386267 603819 5416 155.6 MiB 7.56 0.07 36.0567 -1232.66 -36.0567 nan 2.15 0.0118231 0.00974149 1.23901 1.02884 -1 -1 -1 -1 34 83956 48 5.043e+07 4.818e+07 -1 -1 394.83 5.32434 4.35296 185730 1416087 -1 74292 16 24740 103095 11970321 1866116 34.9964 nan -1210.26 -34.9964 0 0 -1 -1 0.37 3.72 1.11 -1 -1 0.37 0.501094 0.427155 - k4_n4_v7_l1_bidir.xml s298.blif common 14.97 vpr 70.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 573 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71716 4 6 1942 1948 1 1167 583 26 26 676 clb auto 29.8 MiB 0.37 13721 168529 51547 115716 1266 70.0 MiB 1.27 0.02 26.8992 -206.444 -26.8992 26.8992 0.69 0.00496419 0.00432315 0.361202 0.317423 -1 -1 -1 -1 17 15103 41 1.728e+07 1.719e+07 -1 -1 8.88 1.36971 1.16775 39072 254696 -1 13708 17 7890 40380 2928639 390491 25.7904 25.7904 -205.684 -25.7904 0 0 -1 -1 0.06 0.94 0.21 -1 -1 0.06 0.209805 0.184411 - k4_n4_v7_l1_bidir.xml s38417.blif common 61.66 vpr 189.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1852 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 193636 29 106 7534 7640 1 4623 1987 46 46 2116 clb auto 61.8 MiB 1.63 45682 1150699 423694 711314 15691 189.1 MiB 8.82 0.10 24.016 -14000.6 -24.016 24.016 2.46 0.0169007 0.0139461 1.64128 1.36389 -1 -1 -1 -1 16 41981 27 5.808e+07 5.556e+07 -1 -1 37.78 5.55941 4.54523 118272 756192 -1 39731 15 23886 81328 4350389 861432 23.6137 23.6137 -14728 -23.6137 0 0 -1 -1 0.20 2.01 0.59 -1 -1 0.20 0.647233 0.553971 - k4_n4_v7_l1_bidir.xml s38584.1.blif common 67.22 vpr 183.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1787 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 187696 38 304 7475 7779 1 4320 2129 45 45 2025 clb auto 61.8 MiB 1.45 43799 1343749 517594 801490 24665 183.3 MiB 9.49 0.12 21.0587 -13121.7 -21.0587 21.0587 2.45 0.0167009 0.0137478 1.77708 1.46891 -1 -1 -1 -1 16 39654 47 5.547e+07 5.361e+07 -1 -1 43.54 5.72828 4.70791 113090 722879 -1 37482 13 19902 66283 3641519 680597 20.2436 20.2436 -13770 -20.2436 0 0 -1 -1 0.19 1.67 0.56 -1 -1 0.19 0.58033 0.500952 - k4_n4_v7_l1_bidir.xml seq.blif common 39.62 vpr 69.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 567 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71260 41 35 1791 1826 0 1347 643 26 26 676 clb auto 29.0 MiB 0.45 18608 203145 65187 132320 5638 69.6 MiB 1.44 0.02 18.1385 -520.265 -18.1385 nan 0.69 0.00437225 0.00383137 0.338582 0.298021 -1 -1 -1 -1 24 20201 48 1.728e+07 1.701e+07 -1 -1 33.10 1.88123 1.59699 51072 366016 -1 19098 15 8908 34158 2699342 394310 17.881 nan -530.81 -17.881 0 0 -1 -1 0.08 0.83 0.27 -1 -1 0.08 0.160739 0.141136 - k4_n4_v7_l1_bidir.xml spla.blif common 187.45 vpr 130.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1282 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 133456 16 46 3706 3752 0 2852 1344 38 38 1444 clb auto 43.1 MiB 1.08 48851 705674 261242 438237 6195 129.8 MiB 4.82 0.05 28.2789 -928.469 -28.2789 nan 1.62 0.00923375 0.00767658 0.87033 0.724376 -1 -1 -1 -1 30 55651 36 3.888e+07 3.846e+07 -1 -1 170.35 3.95474 3.27046 133344 1000208 -1 49871 15 17906 78246 6885546 1014380 27.1504 nan -941.372 -27.1504 0 0 -1 -1 0.25 2.27 0.77 -1 -1 0.25 0.36105 0.312454 - k4_n4_v7_l1_bidir.xml tseng.blif common 6.87 vpr 64.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 52 122 1483 1605 1 725 466 20 20 400 clb auto 25.0 MiB 0.16 6135 112438 30480 78177 3781 64.4 MiB 0.46 0.01 11.1777 -2780.46 -11.1777 11.1777 0.26 0.00160816 0.00140359 0.112456 0.0992435 -1 -1 -1 -1 14 6150 30 9.72e+06 8.76e+06 -1 -1 4.21 0.681536 0.590913 19872 120996 -1 5573 18 4232 15969 711167 147306 11.3812 11.3812 -3151.62 -11.3812 0 0 -1 -1 0.03 0.34 0.09 -1 -1 0.03 0.138745 0.122462 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml alu4.blif common 10.51 vpr 68.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 493 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70036 14 8 1536 1544 0 1104 515 25 25 625 clb auto 29.0 MiB 0.19 26012 13956 130484 38677 90196 1611 68.4 MiB 0.65 0.01 30.5457 14.3537 -102.59 -14.3537 nan 0.26 0.00281681 0.00240697 0.187334 0.163939 -1 -1 -1 -1 26 20892 39 1.587e+07 1.479e+07 -1 -1 7.59 1.21065 1.03445 22338 287359 -1 19730 15 6783 25798 1828199 189550 17.7661 nan -122.524 -17.7661 0 0 -1 -1 0.05 0.42 0.10 -1 -1 0.05 0.11421 0.10103 +k4_n4_v7_bidir.xml apex2.blif common 15.85 vpr 70.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 625 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72500 38 3 1916 1919 0 1483 666 27 27 729 clb auto 31.8 MiB 0.33 39268 19969 186714 54978 127506 4230 70.8 MiB 1.05 0.01 37.5467 15.2065 -45.3413 -15.2065 nan 0.31 0.00410554 0.00346209 0.282826 0.239397 -1 -1 -1 -1 28 30325 44 1.875e+07 1.875e+07 -1 -1 11.80 1.43193 1.20336 26754 356103 -1 28518 16 9720 35610 2764503 263934 18.4094 nan -54.9029 -18.4094 0 0 -1 -1 0.06 0.59 0.12 -1 -1 0.06 0.147984 0.134232 +k4_n4_v7_bidir.xml apex4.blif common 6.17 vpr 65.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 430 9 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67436 9 19 1271 1290 0 978 458 23 23 529 clb auto 26.9 MiB 0.18 23165 13695 104534 29903 73052 1579 65.9 MiB 0.54 0.01 28.8439 13.8799 -228.564 -13.8799 nan 0.22 0.00213336 0.00186974 0.144465 0.12771 -1 -1 -1 -1 30 20988 39 1.323e+07 1.29e+07 -1 -1 3.43 0.645416 0.557775 20514 283063 -1 19517 20 7190 27765 2407390 214953 17.1513 nan -274.971 -17.1513 0 0 -1 -1 0.05 0.52 0.10 -1 -1 0.05 0.121889 0.109083 +k4_n4_v7_bidir.xml bigkey.blif common 7.98 vpr 72.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 495 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74280 229 197 2152 2349 1 1362 921 29 29 841 io auto 32.6 MiB 0.19 35109 13449 426426 141391 275290 9745 72.5 MiB 1.50 0.02 17.7693 8.07704 -1976.29 -8.07704 8.07704 0.38 0.00372809 0.00338054 0.394382 0.338936 -1 -1 -1 -1 17 21055 43 2.187e+07 1.485e+07 -1 -1 3.55 1.31321 1.13689 24954 256911 -1 18767 22 7669 28488 1689811 197748 8.90589 8.90589 -2364.61 -8.90589 0 0 -1 -1 0.05 0.57 0.09 -1 -1 0.05 0.211757 0.182394 +k4_n4_v7_bidir.xml clma.blif common 72.81 vpr 204.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2657 62 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 209040 62 82 8460 8542 1 6311 2801 54 54 2916 clb auto 83.4 MiB 1.21 318304 107423 1818513 710165 1094335 14013 185.0 MiB 11.36 0.12 109.907 27.5529 -1348.77 -27.5529 27.5529 1.54 0.0211071 0.015896 2.13139 1.63007 -1 -1 -1 -1 38 141343 26 8.112e+07 7.971e+07 -1 -1 48.13 10.3163 8.13924 126538 2024156 -1 136720 18 37710 139608 13309903 1205243 31.5727 31.5727 -1662.82 -31.5727 0 0 -1 -1 0.44 3.25 0.76 -1 -1 0.44 0.881408 0.751274 +k4_n4_v7_bidir.xml des.blif common 11.20 vpr 70.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 476 256 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72576 256 245 1847 2092 0 1369 977 34 34 1156 io auto 31.1 MiB 0.21 41834 16325 359581 117023 229258 13300 70.9 MiB 1.19 0.02 35.0204 12.3184 -2297.36 -12.3184 nan 0.54 0.0041646 0.00363216 0.330541 0.290991 -1 -1 -1 -1 19 23462 24 3.072e+07 1.428e+07 -1 -1 6.50 1.75122 1.56086 35364 387024 -1 21500 20 8895 34040 2269814 254049 14.4581 nan -2758.91 -14.4581 0 0 -1 -1 0.07 0.67 0.14 -1 -1 0.07 0.210732 0.193886 +k4_n4_v7_bidir.xml diffeq.blif common 6.94 vpr 70.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71700 64 39 1935 1974 1 1075 541 23 23 529 clb auto 29.9 MiB 0.19 23859 10147 137127 36471 96425 4231 70.0 MiB 0.69 0.01 41.0644 13.3365 -2669.73 -13.3365 13.3365 0.22 0.00307747 0.00279215 0.219066 0.191584 -1 -1 -1 -1 22 15029 23 1.323e+07 1.314e+07 -1 -1 4.23 1.25599 1.07312 17346 200431 -1 14015 19 6333 22933 1286086 145452 15.0001 15.0001 -3348.78 -15.0001 0 0 -1 -1 0.03 0.37 0.07 -1 -1 0.03 0.145127 0.125426 +k4_n4_v7_bidir.xml dsip.blif common 8.58 vpr 69.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 389 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71388 229 197 1815 2012 1 807 815 29 29 841 io auto 30.0 MiB 0.16 25997 11221 343265 110526 223443 9296 69.7 MiB 1.08 0.02 17.1219 7.67764 -1783.63 -7.67764 7.67764 0.36 0.00298296 0.0026384 0.281491 0.250692 -1 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112.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1571 10 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 115556 10 10 4608 4618 0 3567 1591 42 42 1764 clb auto 52.9 MiB 0.62 147879 45540 753595 262722 489179 1694 110.2 MiB 4.73 0.06 52.4545 24.5398 -234.737 -24.5398 nan 0.87 0.010526 0.0078576 0.90398 0.714975 -1 -1 -1 -1 28 65394 19 4.8e+07 4.713e+07 -1 -1 22.87 4.65072 3.73099 64374 881208 -1 63107 16 23300 93509 5730584 607346 28.9188 nan -276.935 -28.9188 0 0 -1 -1 0.18 1.67 0.32 -1 -1 0.18 0.416222 0.360241 +k4_n4_v7_bidir.xml ex5p.blif common 6.78 vpr 64.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 8 63 1072 1135 0 892 433 22 22 484 clb auto 25.5 MiB 0.18 19665 12146 83920 21665 60035 2220 64.5 MiB 0.41 0.01 27.1613 14.1695 -641.804 -14.1695 nan 0.26 0.00194483 0.00175051 0.110247 0.100056 -1 -1 -1 -1 28 18857 41 1.2e+07 1.086e+07 -1 -1 4.37 0.597322 0.524339 17814 232968 -1 17191 17 7020 24726 2122321 206092 17.5715 nan -811.991 -17.5715 0 0 -1 -1 0.04 0.43 0.08 -1 -1 0.04 0.0982758 0.0881937 +k4_n4_v7_bidir.xml frisc.blif common 39.90 vpr 90.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1093 20 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 92668 20 116 4445 4561 1 2268 1229 36 36 1296 clb auto 47.9 MiB 0.52 82225 38746 540789 181172 349115 10502 89.0 MiB 2.95 0.03 92.1602 27.8548 -13906.2 -27.8548 27.8548 0.63 0.00762553 0.00692883 0.766368 0.640122 -1 -1 -1 -1 32 55435 34 3.468e+07 3.279e+07 -1 -1 31.30 4.3095 3.55018 51266 747164 -1 51352 19 12718 59152 4839669 471177 31.6271 31.6271 -16668.9 -31.6271 0 0 -1 -1 0.15 1.25 0.27 -1 -1 0.15 0.39857 0.343255 +k4_n4_v7_bidir.xml misex3.blif common 8.20 vpr 67.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 456 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69504 14 14 1411 1425 0 1058 484 24 24 576 clb auto 28.0 MiB 0.19 25286 13398 116323 33249 81241 1833 67.9 MiB 0.59 0.01 27.5808 12.9766 -166.337 -12.9766 nan 0.24 0.00253725 0.00218076 0.16921 0.146768 -1 -1 -1 -1 27 22296 50 1.452e+07 1.368e+07 -1 -1 5.36 1.0053 0.860066 21174 279108 -1 19502 18 7476 29328 2259232 221453 15.1329 nan -197.55 -15.1329 0 0 -1 -1 0.05 0.50 0.10 -1 -1 0.05 0.123896 0.111321 +k4_n4_v7_bidir.xml pdc.blif common 47.91 vpr 121.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1617 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 124552 16 40 4591 4631 0 3619 1673 43 43 1849 clb auto 55.2 MiB 0.79 148382 72050 825614 301727 519289 4598 115.6 MiB 5.29 0.06 57.6272 23.7689 -838.224 -23.7689 nan 0.93 0.0150982 0.0114412 1.21295 0.93889 -1 -1 -1 -1 42 105308 49 5.043e+07 4.851e+07 -1 -1 33.47 5.76976 4.57688 84090 1373187 -1 98071 20 23761 104231 12283114 1054649 28.8448 nan -1019.25 -28.8448 0 0 -1 -1 0.29 2.87 0.57 -1 -1 0.29 0.621586 0.531079 +k4_n4_v7_bidir.xml s298.blif common 7.14 vpr 71.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 574 4 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73680 4 6 1942 1948 1 1159 584 26 26 676 clb auto 32.4 MiB 0.21 26193 13170 154304 44587 108633 1084 72.0 MiB 0.89 0.01 59.8244 21.6938 -165.88 -21.6938 21.6938 0.29 0.00418138 0.00347077 0.284209 0.236941 -1 -1 -1 -1 22 20764 41 1.728e+07 1.722e+07 -1 -1 3.70 1.0034 0.843428 22122 258376 -1 18543 20 6776 35839 2195452 220622 26.0696 26.0696 -206.718 -26.0696 0 0 -1 -1 0.04 0.56 0.09 -1 -1 0.04 0.167447 0.146467 +k4_n4_v7_bidir.xml s38417.blif common 38.14 vpr 133.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1839 29 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 137148 29 106 7534 7640 1 4625 1974 45 45 2025 clb auto 67.5 MiB 0.93 182366 49147 1115994 411126 689649 15219 131.3 MiB 7.02 0.09 69.8886 18.1305 -11126 -18.1305 18.1305 1.12 0.0167919 0.0133128 1.55146 1.22292 -1 -1 -1 -1 26 62916 18 5.547e+07 5.517e+07 -1 -1 22.18 6.66465 5.36506 71818 959559 -1 61826 21 25212 85364 5272227 577542 22.2241 22.2241 -13589.6 -22.2241 0 0 -1 -1 0.20 1.77 0.35 -1 -1 0.20 0.746813 0.639752 +k4_n4_v7_bidir.xml s38584.1.blif common 26.45 vpr 130.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1785 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 134000 38 304 7475 7779 1 4307 2127 45 45 2025 clb auto 67.2 MiB 0.79 169496 43700 1260043 468320 769335 22388 130.9 MiB 6.66 0.09 46.6882 12.4704 -8838.49 -12.4704 12.4704 1.02 0.0150387 0.011511 1.56356 1.2059 -1 -1 -1 -1 22 57407 29 5.547e+07 5.355e+07 -1 -1 11.74 5.32525 4.24948 65746 795487 -1 53993 24 21202 68197 3819694 436287 15.8262 15.8262 -10638.4 -15.8262 0 0 -1 -1 0.17 1.66 0.29 -1 -1 0.17 0.826696 0.695763 +k4_n4_v7_bidir.xml seq.blif common 11.14 vpr 69.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 563 41 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71080 41 35 1791 1826 0 1358 639 26 26 676 clb auto 30.7 MiB 0.24 34655 19019 179454 52780 121688 4986 69.4 MiB 0.97 0.01 28.2438 14.5406 -418.614 -14.5406 nan 0.30 0.00347682 0.00287878 0.275951 0.233536 -1 -1 -1 -1 31 27432 31 1.728e+07 1.689e+07 -1 -1 7.47 1.4478 1.22337 26172 364912 -1 25996 16 8273 30805 2346654 227901 18.1758 nan -502.399 -18.1758 0 0 -1 -1 0.06 0.53 0.13 -1 -1 0.06 0.140373 0.124717 +k4_n4_v7_bidir.xml spla.blif common 39.46 vpr 96.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1295 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 98848 16 46 3706 3752 0 2830 1357 38 38 1444 clb auto 47.2 MiB 0.58 104307 47860 579550 196916 377929 4705 93.3 MiB 3.12 0.04 52.5658 19.3022 -663.123 -19.3022 nan 0.70 0.00738583 0.00664122 0.704824 0.552684 -1 -1 -1 -1 36 71709 36 3.888e+07 3.885e+07 -1 -1 29.89 3.77665 2.98889 59972 912004 -1 67441 20 18417 83736 8422141 758154 24.4024 nan -837.791 -24.4024 0 0 -1 -1 0.21 1.77 0.32 -1 -1 0.21 0.388862 0.328321 +k4_n4_v7_bidir.xml tseng.blif common 4.87 vpr 65.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67424 52 122 1483 1605 1 721 466 20 20 400 clb auto 26.6 MiB 0.14 14453 6266 110632 29522 77317 3793 65.8 MiB 0.50 0.01 29.8881 13.1236 -2386.51 -13.1236 13.1236 0.16 0.00222333 0.00202089 0.166559 0.150191 -1 -1 -1 -1 18 10091 45 9.72e+06 8.76e+06 -1 -1 2.86 0.749946 0.658853 12348 129228 -1 8546 20 3970 14140 657005 83311 15.2834 15.2834 -3062.53 -15.2834 0 0 -1 -1 0.02 0.22 0.04 -1 -1 0.02 0.101198 0.0913371 +k4_n4_v7_l1_bidir.xml alu4.blif common 10.53 vpr 68.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 493 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70036 14 8 1536 1544 0 1104 515 25 25 625 clb auto 28.8 MiB 0.20 26012 13882 144925 44962 98128 1835 68.4 MiB 0.75 0.01 45.0652 18.3459 -138.341 -18.3459 nan 0.38 0.00307527 0.0026122 0.230228 0.198221 -1 -1 -1 -1 21 14740 32 1.587e+07 1.479e+07 -1 -1 6.92 1.0599 0.899376 42642 296151 -1 13671 16 6751 27151 1578234 268986 18.5341 nan -138.309 -18.5341 0 0 -1 -1 0.07 0.51 0.11 -1 -1 0.07 0.117569 0.10406 +k4_n4_v7_l1_bidir.xml apex2.blif common 34.31 vpr 70.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 625 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72144 38 3 1916 1919 0 1483 666 27 27 729 clb auto 31.4 MiB 0.30 39268 20542 218691 70799 142856 5036 70.5 MiB 1.09 0.01 56.8542 22.1453 -63.6176 -22.1453 nan 0.53 0.003642 0.00303919 0.293084 0.248885 -1 -1 -1 -1 23 23305 46 1.875e+07 1.875e+07 -1 -1 29.32 1.46884 1.22779 52650 371955 -1 21163 16 9774 36558 3184705 468372 21.3859 nan -62.3911 -21.3859 0 0 -1 -1 0.08 0.90 0.23 -1 -1 0.08 0.170377 0.150501 +k4_n4_v7_l1_bidir.xml apex4.blif common 23.46 vpr 66.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 430 9 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67932 9 19 1271 1290 0 978 458 23 23 529 clb auto 27.3 MiB 0.16 23165 13634 123938 37969 84511 1458 66.3 MiB 0.63 0.01 45.8408 17.9211 -294.82 -17.9211 nan 0.31 0.00224286 0.00198234 0.174028 0.153204 -1 -1 -1 -1 23 16880 46 1.323e+07 1.29e+07 -1 -1 20.29 0.875708 0.747308 37674 265803 -1 14265 15 7589 28006 2741318 395062 17.6852 nan -291.991 -17.6852 0 0 -1 -1 0.06 0.63 0.10 -1 -1 0.06 0.0994468 0.0886171 +k4_n4_v7_l1_bidir.xml bigkey.blif common 27.07 vpr 72.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 495 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74276 229 197 2152 2349 1 1362 921 29 29 841 io auto 32.6 MiB 0.19 35109 13408 448821 146189 291712 10920 72.5 MiB 1.54 0.02 28.5192 11.8335 -2618.05 -11.8335 11.8335 0.54 0.00381705 0.00331139 0.415039 0.360706 -1 -1 -1 -1 12 13371 38 2.187e+07 1.485e+07 -1 -1 22.31 1.32942 1.14348 39906 235943 -1 12329 17 6865 26060 1290857 258844 11.6984 11.6984 -2776.31 -11.6984 0 0 -1 -1 0.06 0.54 0.09 -1 -1 0.06 0.172038 0.151618 +k4_n4_v7_l1_bidir.xml clma.blif common 278.12 vpr 238.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2657 62 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 243764 62 82 8460 8542 1 6311 2801 54 54 2916 clb auto 83.5 MiB 1.37 318304 106218 1996137 787385 1191682 17070 225.3 MiB 12.34 0.12 180.571 44.0646 -2121.09 -44.0646 44.0646 2.25 0.0221159 0.0166099 2.32684 1.77283 -1 -1 -1 -1 29 111883 49 8.112e+07 7.971e+07 -1 -1 248.93 9.52343 7.40398 263120 1955672 -1 101313 14 37365 145032 12692939 2064304 42.322 42.322 -2255.16 -42.322 0 0 -1 -1 0.53 3.98 0.79 -1 -1 0.53 0.790771 0.664853 +k4_n4_v7_l1_bidir.xml des.blif common 27.55 vpr 85.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 476 256 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87980 256 245 1847 2092 0 1369 977 34 34 1156 io auto 30.7 MiB 0.22 41834 16291 427425 141277 269635 16513 85.9 MiB 1.40 0.02 55.6616 18.2554 -3058.48 -18.2554 nan 0.79 0.00414944 0.00361335 0.389896 0.341364 -1 -1 -1 -1 12 17178 44 3.072e+07 1.428e+07 -1 -1 22.06 1.59014 1.39836 55296 328128 -1 15463 15 7660 27882 2152148 416875 17.1404 nan -3056.03 -17.1404 0 0 -1 -1 0.08 0.59 0.13 -1 -1 0.08 0.154021 0.14055 +k4_n4_v7_l1_bidir.xml diffeq.blif common 10.69 vpr 70.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71700 64 39 1935 1974 1 1075 541 23 23 529 clb auto 29.9 MiB 0.19 23859 10034 152548 43059 105955 3534 70.0 MiB 0.77 0.01 60.266 12.6666 -3104.5 -12.6666 12.6666 0.32 0.00333395 0.00280831 0.247667 0.211717 -1 -1 -1 -1 15 10658 50 1.323e+07 1.314e+07 -1 -1 7.52 1.08277 0.918032 28434 179743 -1 9183 16 6138 22497 1257215 230883 12.6467 12.6467 -3223.39 -12.6467 0 0 -1 -1 0.04 0.42 0.06 -1 -1 0.04 0.130574 0.116547 +k4_n4_v7_l1_bidir.xml dsip.blif common 23.47 vpr 69.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 389 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71388 229 197 1815 2012 1 807 815 29 29 841 io auto 29.7 MiB 0.22 25997 11249 366095 122219 234437 9439 69.7 MiB 1.16 0.02 27.0132 11.1529 -2551.52 -11.1529 11.1529 0.54 0.00305654 0.00270038 0.30737 0.272816 -1 -1 -1 -1 12 11176 33 2.187e+07 1.167e+07 -1 -1 19.30 1.06061 0.935673 39906 235943 -1 10244 13 4283 22052 1030607 200941 10.8718 10.8718 -2615.29 -10.8718 0 0 -1 -1 0.05 0.36 0.09 -1 -1 0.05 0.102932 0.0931994 +k4_n4_v7_l1_bidir.xml elliptic.blif common 111.94 vpr 102.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1023 131 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105300 131 114 4855 4969 1 2121 1268 34 34 1156 clb auto 48.5 MiB 0.47 68213 32052 611808 216720 388087 7001 99.5 MiB 2.86 0.03 93.3266 25.0351 -15271.4 -25.0351 25.0351 0.77 0.00905634 0.00709113 0.855766 0.678841 -1 -1 -1 -1 24 35952 46 3.072e+07 3.069e+07 -1 -1 102.70 3.84755 3.092 89088 639360 -1 31624 16 11873 54886 5140312 855505 24.5872 24.5872 -16149.4 -24.5872 0 0 -1 -1 0.16 1.60 0.24 -1 -1 0.16 0.377302 0.320117 +k4_n4_v7_l1_bidir.xml ex1010.blif common 39.75 vpr 137.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1571 10 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 140920 10 10 4608 4618 0 3567 1591 42 42 1764 clb auto 53.4 MiB 0.67 147879 46435 790731 289845 498934 1952 136.5 MiB 4.98 0.05 83.3245 39.6079 -368.605 -39.6079 nan 1.34 0.00996113 0.00752524 0.973665 0.7587 -1 -1 -1 -1 21 49742 46 4.8e+07 4.713e+07 -1 -1 25.65 3.83175 3.05967 124480 868048 -1 45150 16 22456 89716 4688523 856199 39.8159 nan -369.076 -39.8159 0 0 -1 -1 0.22 1.87 0.43 -1 -1 0.22 0.398072 0.339422 +k4_n4_v7_l1_bidir.xml ex5p.blif common 18.19 vpr 65.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 8 63 1072 1135 0 892 433 22 22 484 clb auto 26.2 MiB 0.16 19665 12180 110112 32722 75037 2353 65.1 MiB 0.52 0.01 42.1132 17.967 -770.979 -17.967 nan 0.28 0.00181833 0.00162281 0.135232 0.122075 -1 -1 -1 -1 23 14643 39 1.2e+07 1.086e+07 -1 -1 15.45 0.747906 0.648695 34320 242040 -1 12274 18 7244 25344 2108210 336035 17.2355 nan -777.274 -17.2355 0 0 -1 -1 0.05 0.49 0.09 -1 -1 0.05 0.0896065 0.0794681 +k4_n4_v7_l1_bidir.xml frisc.blif common 91.55 vpr 110.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1093 20 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 112720 20 116 4445 4561 1 2268 1229 36 36 1296 clb auto 47.9 MiB 0.55 82225 38236 580269 205035 365670 9564 106.0 MiB 3.02 0.03 144.888 28.2628 -15971.6 -28.2628 28.2628 0.97 0.00860906 0.00685372 0.84973 0.678473 -1 -1 -1 -1 26 41144 35 3.468e+07 3.279e+07 -1 -1 81.45 3.93702 3.18952 104992 763300 -1 37445 17 13158 60126 5444826 978154 27.7261 27.7261 -16327.8 -27.7261 0 0 -1 -1 0.18 1.55 0.29 -1 -1 0.18 0.355507 0.299943 +k4_n4_v7_l1_bidir.xml misex3.blif common 25.17 vpr 67.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 456 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69212 14 14 1411 1425 0 1058 484 24 24 576 clb auto 28.1 MiB 0.23 25286 14202 129616 40562 86860 2194 67.6 MiB 0.81 0.01 43.4719 17.7771 -224.903 -17.7771 nan 0.34 0.00245431 0.00214229 0.229478 0.20207 -1 -1 -1 -1 22 16796 43 1.452e+07 1.368e+07 -1 -1 21.57 0.930568 0.795872 39160 271852 -1 14502 17 7277 28246 2125959 376090 17.9267 nan -234.908 -17.9267 0 0 -1 -1 0.06 0.57 0.10 -1 -1 0.06 0.111633 0.0985354 +k4_n4_v7_l1_bidir.xml pdc.blif common 116.26 vpr 159.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1617 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 163788 16 40 4591 4631 0 3619 1673 43 43 1849 clb auto 54.7 MiB 0.83 148382 72670 934811 358856 570141 5814 142.3 MiB 5.29 0.05 93.2356 33.3601 -1166.2 -33.3601 nan 1.32 0.0109056 0.00836527 1.08312 0.834952 -1 -1 -1 -1 36 80097 36 5.043e+07 4.851e+07 -1 -1 99.52 5.50726 4.31544 192618 1479219 -1 75456 17 26040 112622 12244803 1822486 32.6929 nan -1148.81 -32.6929 0 0 -1 -1 0.39 3.43 0.60 -1 -1 0.39 0.480142 0.402737 +k4_n4_v7_l1_bidir.xml s298.blif common 31.82 vpr 71.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 574 4 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73172 4 6 1942 1948 1 1159 584 26 26 676 clb auto 31.7 MiB 0.21 26193 13287 168944 51306 116401 1237 71.5 MiB 0.86 0.01 92.2741 24.9723 -196.835 -24.9723 24.9723 0.42 0.00370694 0.00304842 0.284114 0.236343 -1 -1 -1 -1 16 14492 41 1.728e+07 1.722e+07 -1 -1 27.66 1.50279 1.23825 36672 232432 -1 13188 18 8145 41698 2905801 417656 24.2999 24.2999 -196.112 -24.2999 0 0 -1 -1 0.05 0.83 0.09 -1 -1 0.05 0.170401 0.147693 +k4_n4_v7_l1_bidir.xml s38417.blif common 59.52 vpr 160.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1839 29 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 164724 29 106 7534 7640 1 4625 1974 45 45 2025 clb auto 67.7 MiB 0.80 182366 46669 1140750 409193 715103 16454 160.5 MiB 6.67 0.07 113.119 24.123 -13847.4 -24.123 24.123 1.47 0.0158586 0.0120293 1.55666 1.19069 -1 -1 -1 -1 16 43059 47 5.547e+07 5.517e+07 -1 -1 42.79 5.2201 4.09966 113090 722879 -1 40589 15 24470 82387 4406125 874310 22.9241 22.9241 -14764.6 -22.9241 0 0 -1 -1 0.19 1.91 0.31 -1 -1 0.19 0.638183 0.553447 +k4_n4_v7_l1_bidir.xml s38584.1.blif common 63.67 vpr 161.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1785 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 165740 38 304 7475 7779 1 4307 2127 45 45 2025 clb auto 67.0 MiB 0.78 169496 44382 1342081 511835 806220 24026 161.9 MiB 6.99 0.07 74.1051 20.5353 -13256.6 -20.5353 20.5353 1.52 0.015181 0.0115929 1.64152 1.2783 -1 -1 -1 -1 16 41197 48 5.547e+07 5.355e+07 -1 -1 47.15 4.91191 3.90833 113090 722879 -1 38058 15 20429 66024 3978003 769268 20.3296 20.3296 -14054.5 -20.3296 0 0 -1 -1 0.19 1.58 0.28 -1 -1 0.19 0.576043 0.5016 +k4_n4_v7_l1_bidir.xml seq.blif common 22.25 vpr 69.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 563 41 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71068 41 35 1791 1826 0 1358 639 26 26 676 clb auto 30.3 MiB 0.24 34655 18585 215217 68324 141286 5607 69.4 MiB 1.04 0.01 42.7606 19.0541 -549.348 -19.0541 nan 0.41 0.00343627 0.00285473 0.287666 0.242426 -1 -1 -1 -1 22 21579 50 1.728e+07 1.689e+07 -1 -1 17.99 1.11907 0.938823 46272 321488 -1 18864 15 8903 34453 2990664 524856 19.8932 nan -572.473 -19.8932 0 0 -1 -1 0.07 0.75 0.12 -1 -1 0.07 0.136318 0.119711 +k4_n4_v7_l1_bidir.xml spla.blif common 181.65 vpr 121.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1295 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 124260 16 46 3706 3752 0 2830 1357 38 38 1444 clb auto 47.2 MiB 0.59 104307 48793 654640 238193 412191 4256 116.5 MiB 3.91 0.04 84.8923 28.2789 -955.027 -28.2789 nan 1.02 0.00801147 0.00629725 0.881683 0.69524 -1 -1 -1 -1 30 56845 44 3.888e+07 3.885e+07 -1 -1 169.35 3.86298 3.0794 133344 1000208 -1 50796 19 19477 89020 8037289 1191085 27.773 nan -975.676 -27.773 0 0 -1 -1 0.25 2.48 0.40 -1 -1 0.25 0.407889 0.339434 +k4_n4_v7_l1_bidir.xml tseng.blif common 7.47 vpr 66.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67816 52 122 1483 1605 1 721 466 20 20 400 clb auto 27.0 MiB 0.13 14453 6257 117856 31965 81849 4042 66.2 MiB 0.49 0.01 44.0183 11.512 -2810.26 -11.512 11.512 0.23 0.00229118 0.00204192 0.160486 0.144029 -1 -1 -1 -1 14 6597 40 9.72e+06 8.76e+06 -1 -1 5.23 0.735414 0.639305 19872 120996 -1 5753 18 4097 15290 638053 131747 12.3091 12.3091 -3042.24 -12.3091 0 0 -1 -1 0.03 0.25 0.04 -1 -1 0.03 0.103918 0.0927701 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt index 6a59a733970..07c9b5a2f55 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 45.88 vpr 105.39 MiB -1 -1 6.79 63484 8 3.06 -1 -1 40704 -1 -1 250 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 107916 385 362 4415 4299 1 2365 1000 26 26 676 io auto 53.4 MiB 8.02 30064 545782 201861 320153 23768 96.5 MiB 5.36 0.06 9.17025 -9814.95 -9.17025 9.17025 0.75 0.0154429 0.0143793 1.79153 1.64504 -1 -1 -1 -1 86 44693 20 3.69863e+07 1.49655e+07 3.69198e+06 5461.52 13.35 6.72204 6.1687 89040 769342 -1 41511 17 9662 32287 1739041 311622 9.36868 9.36868 -10331.7 -9.36868 0 0 4.67059e+06 6909.16 0.16 1.11 0.68 -1 -1 0.16 0.681008 0.635643 - k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 15.44 vpr 81.45 MiB -1 -1 3.43 44504 3 1.23 -1 -1 39800 -1 -1 141 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83404 38 36 2739 2488 1 1022 215 17 17 289 clb auto 40.5 MiB 1.96 8926 42010 10393 28489 3128 81.4 MiB 0.91 0.01 10.0828 -2706.04 -10.0828 10.0828 0.30 0.00541664 0.00477131 0.391772 0.345384 -1 -1 -1 -1 62 13454 38 1.34605e+07 7.59905e+06 1.10657e+06 3828.96 3.45 1.77757 1.52314 31771 216973 -1 12449 21 4102 9497 328915 58876 10.8931 10.8931 -3012.43 -10.8931 0 0 1.37508e+06 4758.06 0.05 0.40 0.19 -1 -1 0.05 0.289893 0.256286 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 24.74 vpr 70.58 MiB -1 -1 17.86 45828 3 0.69 -1 -1 35540 -1 -1 48 196 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72272 196 193 1201 1346 1 606 438 15 15 225 io auto 31.2 MiB 0.83 3130 146694 39708 93961 13025 70.6 MiB 0.73 0.01 2.24601 -1081.12 -2.24601 2.24601 0.23 0.00356204 0.00332113 0.333364 0.31069 -1 -1 -1 -1 36 6058 29 1.03862e+07 3.13491e+06 520410. 2312.93 1.93 1.18409 1.08635 21110 102306 -1 5134 10 1618 2340 136007 39516 2.56471 2.56471 -1177.45 -2.56471 0 0 643451. 2859.78 0.02 0.14 0.09 -1 -1 0.02 0.102579 0.095844 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 22.86 vpr 83.41 MiB -1 -1 4.78 42380 3 0.69 -1 -1 37656 -1 -1 129 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85412 236 305 3199 3011 1 1520 677 19 19 361 io auto 42.5 MiB 2.99 12761 268067 88565 164726 14776 83.4 MiB 2.03 0.03 4.74988 -2887.79 -4.74988 4.74988 0.39 0.00859777 0.00794312 0.829104 0.763261 -1 -1 -1 -1 62 24213 37 1.72706e+07 9.87633e+06 1.42198e+06 3939.00 7.32 3.04293 2.76861 40483 281719 -1 20603 18 6062 15441 1381198 347776 4.88181 4.88181 -3127.07 -4.88181 0 0 1.76637e+06 4892.99 0.06 0.66 0.24 -1 -1 0.06 0.38505 0.357195 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 34.15 vpr 101.05 MiB -1 -1 3.84 61860 8 2.89 -1 -1 42304 -1 -1 247 385 2 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 103472 385 362 4415 4299 1 2357 997 26 26 676 io auto 57.1 MiB 5.19 60299 29833 558533 214306 321077 23150 97.4 MiB 4.02 0.05 12.9571 9.08653 -9982.73 -9.08653 9.08653 0.60 0.0122951 0.0115891 1.40221 1.25508 -1 -1 -1 -1 86 44651 39 3.69863e+07 1.48038e+07 3.69198e+06 5461.52 12.13 5.63808 5.09536 89040 769342 -1 41400 21 10076 33666 1743244 311635 9.30121 9.30121 -10341.1 -9.30121 0 0 4.67059e+06 6909.16 0.15 0.96 0.52 -1 -1 0.15 0.591543 0.547933 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 9.26 vpr 83.89 MiB -1 -1 1.74 44312 3 1.07 -1 -1 39956 -1 -1 139 38 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85904 38 36 2739 2488 1 1049 213 16 16 256 clb auto 43.6 MiB 1.17 14059 8662 34503 7871 24229 2403 83.9 MiB 0.49 0.01 11.7745 10.1195 -2670 -10.1195 10.1195 0.19 0.0035954 0.00320083 0.224754 0.197673 -1 -1 -1 -1 62 12786 36 1.21132e+07 7.49127e+06 968026. 3781.35 2.14 1.16173 1.01486 28084 189262 -1 11901 21 4007 8912 293191 53923 10.7115 10.7115 -2827.56 -10.7115 0 0 1.20332e+06 4700.46 0.03 0.27 0.11 -1 -1 0.03 0.207459 0.188642 +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 14.77 vpr 71.92 MiB -1 -1 9.79 45204 3 0.61 -1 -1 35392 -1 -1 47 196 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73648 196 193 1201 1346 1 592 437 15 15 225 io auto 32.8 MiB 0.58 6911 3057 146253 37880 94608 13765 71.9 MiB 0.39 0.01 3.04383 2.21331 -1098.79 -2.21331 2.21331 0.19 0.00181143 0.00167906 0.171476 0.158363 -1 -1 -1 -1 38 5820 21 1.03862e+07 3.08102e+06 544116. 2418.30 1.62 0.679631 0.627147 21558 109668 -1 4978 10 1591 2448 151620 45926 2.57055 2.57055 -1194.35 -2.57055 0 0 690508. 3068.92 0.02 0.09 0.06 -1 -1 0.02 0.0694194 0.066214 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 15.04 vpr 84.71 MiB -1 -1 2.58 42840 3 0.56 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86744 236 305 3199 3011 1 1523 675 19 19 361 io auto 45.6 MiB 1.97 25195 12600 275862 99499 162512 13851 84.7 MiB 1.30 0.02 6.75568 4.64882 -2837.55 -4.64882 4.64882 0.29 0.00513714 0.00475976 0.519055 0.470381 -1 -1 -1 -1 62 23840 49 1.72706e+07 9.76854e+06 1.42198e+06 3939.00 5.43 1.97221 1.78662 40483 281719 -1 20436 15 5933 14959 1286779 322599 4.8554 4.8554 -3009.05 -4.8554 0 0 1.76637e+06 4892.99 0.06 0.45 0.17 -1 -1 0.06 0.248103 0.234994 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt index 4719bdbbc41..743e4766b3c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt @@ -1,15 +1,15 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 86.33 parmys 237.66 MiB -1 -1 59.56 243368 18 8.03 -1 -1 47792 -1 -1 690 257 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 131604 257 32 6023 6055 1 5218 979 30 30 900 clb auto 50.4 MiB 1.32 30778 384840 112160 259942 12738 128.5 MiB 5.07 0.06 6.21971 -2685.64 -6.21971 6.21971 0.00 0.0121286 0.010889 1.07079 0.930807 -1 -1 -1 -1 48326 9.26495 23261 4.45955 24183 85231 10762077 2437584 4.97244e+06 2.691e+06 9.69309e+06 10770.1 19 207906 1928213 -1 6.7296 6.7296 -2945.08 -6.7296 0 0 3.08 -1 -1 128.5 MiB 2.73 1.64504 1.43517 128.5 MiB -1 1.06 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 69.59 parmys 308.92 MiB -1 -1 20.53 316332 11 11.34 -1 -1 60732 -1 -1 1320 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 232392 36 100 10357 10457 1 9801 1456 41 41 1681 clb auto 78.0 MiB 1.62 84812 768613 262427 482842 23344 226.9 MiB 14.06 0.14 4.39308 -1711.02 -4.39308 4.39308 0.01 0.022016 0.0196054 2.33652 1.96707 -1 -1 -1 -1 138657 14.2256 61058 6.26429 47871 161906 24294871 4760787 8.95136e+06 5.148e+06 1.84779e+07 10992.2 18 392750 3677203 -1 4.59418 4.59418 -1851.22 -4.59418 0 0 6.19 -1 -1 226.9 MiB 6.17 3.45481 2.92361 226.9 MiB -1 2.09 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 20.54 vpr 65.45 MiB -1 -1 16.87 31768 7 0.22 -1 -1 34408 -1 -1 84 195 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67016 195 193 1168 1361 1 833 473 15 15 225 io memory auto 25.1 MiB 0.15 4149 116519 30489 77528 8502 65.4 MiB 0.67 0.01 2.05786 -845.694 -2.05786 2.05786 0.00 0.00358265 0.00334889 0.236637 0.220258 -1 -1 -1 -1 5820 7.04600 2934 3.55206 2158 7108 836065 203922 1.16234e+06 410348 2.18283e+06 9701.45 17 48952 428016 -1 2.20416 2.20416 -941.195 -2.20416 -5.04525 -0.362152 0.68 -1 -1 65.4 MiB 0.28 0.370687 0.343567 65.4 MiB -1 0.15 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU8PEEng.v common 274.74 vpr 777.04 MiB -1 -1 83.07 347172 198 58.46 -1 -1 81260 -1 -1 3007 114 84 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 795688 114 102 27514 27424 1 24905 3315 86 86 7396 memory auto 170.7 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14931524 6314811 8578405 38308 2920.1 MiB 540.32 3.31 183.298 68.4997 -205073 -68.4997 68.4997 0.13 0.224889 0.199606 35.6755 28.4271 -1 -1 -1 -1 1429089 16.8680 637842 7.52865 260993 905980 118710487 27205397 1.64515e+08 6.81223e+07 3.31299e+08 11599.7 23 6883162 66233393 -1 73.0461 73.0461 -408864 -73.0461 -158.391 -0.303936 52.19 -1 -1 2920.1 MiB 45.14 49.5464 39.7886 2920.1 MiB -1 52.32 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mcml.v common 4798.35 vpr 2.99 GiB -1 -1 482.74 1402976 107 3634.95 -1 -1 347088 -1 -1 11481 36 318 27 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 3130736 36 356 138376 137161 1 92319 12218 169 169 28561 memory auto 782.0 MiB 15.53 6 1160463 19704338 8803888 10822718 77732 3057.4 MiB 468.78 2.85 140.602 55.2965 -212224 -55.2965 55.2965 0.09 0.202736 0.179676 33.0622 27.398 -1 -1 -1 -1 1073968 11.6336 502193 5.43993 312182 1239709 147666283 34765349 1.64515e+08 7.43047e+07 3.31299e+08 11599.7 22 6883162 66233393 -1 58.2368 58.2368 -298549 -58.2368 -0.797149 -0.124294 52.65 -1 -1 3057.4 MiB 45.35 44.9196 37.5371 3057.4 MiB -1 47.98 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt index 5fc9ae47bce..52cfffff857 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt @@ -1,22 +1,22 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 237.52 vpr 262.28 MiB -1 -1 32.91 121376 20 45.70 -1 -1 67188 -1 -1 857 133 25 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 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3041 63 63 3969 clb auto 300.2 MiB 92.25 247801 2183219 784650 1370393 28176 712.5 MiB 71.53 0.62 19.785 -25840.1 -19.785 19.785 16.56 0.102779 0.0918008 11.5762 9.76479 -1 -1 -1 -1 72 386360 42 2.36641e+08 1.52081e+08 1.98694e+07 5006.15 110.59 42.9221 35.5891 498330 4113940 -1 362013 19 91449 417245 17088983 2690880 20.0733 20.0733 -26346.1 -20.0733 0 0 2.48734e+07 6266.93 1.16 11.31 3.82 -1 -1 1.16 5.98384 5.18194 - k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 81.79 parmys 261.76 MiB -1 -1 16.25 268040 5 3.83 -1 -1 54936 -1 -1 499 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 144920 36 100 10178 7632 1 2726 635 29 29 841 clb auto 89.3 MiB 20.95 42663 237971 70464 152269 15238 136.4 MiB 5.32 0.05 14.7669 -2473.22 -14.7669 14.7669 0.97 0.0211143 0.0190909 2.35792 2.11102 -1 -1 -1 -1 70 69685 21 4.4999e+07 2.68931e+07 3.87716e+06 4610.18 22.40 6.46234 5.5956 101140 791177 -1 63521 14 12660 66318 2601627 385811 14.9702 14.9702 -2667.46 -14.9702 0 0 4.87732e+06 5799.43 0.18 1.24 0.61 -1 -1 0.18 0.765348 0.685884 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 27.98 vpr 70.30 MiB -1 -1 19.04 45836 3 0.71 -1 -1 35388 -1 -1 48 196 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71984 196 193 1201 1346 1 606 438 15 15 225 io auto 31.0 MiB 0.83 3130 146694 39708 93961 13025 70.3 MiB 0.75 0.01 2.24601 -1081.12 -2.24601 2.24601 0.23 0.00372098 0.00347122 0.346766 0.322935 -1 -1 -1 -1 36 6058 29 1.03862e+07 3.13491e+06 520410. 2312.93 4.20 1.65535 1.51569 21110 102306 -1 5134 10 1618 2340 136007 39516 2.56471 2.56471 -1177.45 -2.56471 0 0 643451. 2859.78 0.02 0.14 0.09 -1 -1 0.02 0.105047 0.098196 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.63 vpr 65.72 MiB -1 -1 0.47 18896 3 0.09 -1 -1 33312 -1 -1 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67300 99 130 344 474 1 227 298 12 12 144 clb auto 26.5 MiB 0.17 749 71938 22933 33485 15520 65.7 MiB 0.13 0.00 1.86413 -118.59 -1.86413 1.86413 0.10 0.000549638 0.000516276 0.0433027 0.040723 -1 -1 -1 -1 42 1520 10 5.66058e+06 4.21279e+06 345696. 2400.67 0.59 0.187247 0.170993 13090 66981 -1 1349 11 399 648 28156 8528 2.01841 2.01841 -138.411 -2.01841 0 0 434636. 3018.30 0.01 0.05 0.06 -1 -1 0.01 0.0359727 0.0332907 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 9.83 vpr 68.52 MiB -1 -1 0.57 22264 5 0.15 -1 -1 34252 -1 -1 32 162 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70164 162 96 1075 892 1 665 295 16 16 256 mult_36 auto 29.5 MiB 0.47 5186 94471 34661 52400 7410 68.5 MiB 0.71 0.01 15.8635 -1239.63 -15.8635 15.8635 0.26 0.00331121 0.00311453 0.328384 0.30882 -1 -1 -1 -1 58 10489 28 1.21132e+07 3.70461e+06 904541. 3533.36 5.64 1.61544 1.48773 27572 180683 -1 8500 19 2932 4812 741239 227046 17.067 17.067 -1349.92 -17.067 0 0 1.15318e+06 4504.63 0.04 0.31 0.16 -1 -1 0.04 0.144606 0.134419 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 11.47 vpr 67.82 MiB -1 -1 0.42 21216 5 0.11 -1 -1 33532 -1 -1 21 66 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69452 66 96 778 595 1 467 188 16 16 256 mult_36 auto 28.2 MiB 0.61 3552 38386 11370 22642 4374 67.8 MiB 0.36 0.01 11.8641 -739.791 -11.8641 11.8641 0.26 0.00237331 0.00224591 0.18002 0.170428 -1 -1 -1 -1 56 8238 44 1.21132e+07 3.11177e+06 870502. 3400.40 7.66 1.20105 1.10303 27064 172478 -1 6899 24 3920 8254 1448980 464078 13.0139 13.0139 -835.321 -13.0139 0 0 1.11200e+06 4343.75 0.04 0.43 0.15 -1 -1 0.04 0.125507 0.116065 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 66.31 vpr 349.85 MiB -1 -1 18.06 118764 5 3.19 -1 -1 44732 -1 -1 482 506 44 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 358248 506 553 3236 3734 1 2871 1585 50 50 2500 memory auto 51.8 MiB 6.65 15677 1193158 583612 419742 189804 349.9 MiB 5.89 0.07 7.82454 -2101.77 -7.82454 7.82454 10.39 0.0232107 0.0209756 3.11831 2.78915 -1 -1 -1 -1 38 23230 14 1.47946e+08 5.00895e+07 6.86579e+06 2746.32 11.78 8.44468 7.65217 258216 1426232 -1 22340 13 3999 5540 1044268 276431 8.15652 8.15652 -2449.78 -8.15652 0 0 8.69102e+06 3476.41 0.36 0.62 0.94 -1 -1 0.36 0.474915 0.450631 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 14.83 vpr 75.46 MiB -1 -1 1.65 25776 2 0.13 -1 -1 34240 -1 -1 32 311 15 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77268 311 156 1015 1158 1 965 514 28 28 784 memory auto 31.5 MiB 0.84 8771 212488 81670 120789 10029 71.8 MiB 1.28 0.02 4.24034 -4274.29 -4.24034 4.24034 0.91 0.00591498 0.00525545 0.632092 0.561616 -1 -1 -1 -1 46 13629 17 4.25198e+07 9.94461e+06 2.40571e+06 3068.51 6.49 2.43454 2.16131 81794 492802 -1 13067 13 2559 2889 592994 173675 4.10368 4.10368 -4803.02 -4.10368 -0.000474482 -0.000474482 3.09729e+06 3950.62 0.12 0.33 0.43 -1 -1 0.12 0.19988 0.181279 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 24.37 vpr 81.55 MiB -1 -1 6.55 53024 5 1.65 -1 -1 39496 -1 -1 170 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83508 193 205 2718 2652 1 1367 573 20 20 400 memory auto 40.7 MiB 3.02 11072 243231 85018 132684 25529 81.6 MiB 2.05 0.03 5.05891 -2813.63 -5.05891 5.05891 0.43 0.00798011 0.00703653 0.846187 0.756249 -1 -1 -1 -1 52 19118 33 2.07112e+07 1.1902e+07 1.31074e+06 3276.84 6.44 2.84139 2.53272 42580 268535 -1 16450 14 4598 11278 570237 127961 5.38192 5.38192 -3001.18 -5.38192 0 0 1.72518e+06 4312.96 0.06 0.45 0.23 -1 -1 0.06 0.306487 0.281362 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 66.97 vpr 107.66 MiB -1 -1 6.90 62616 8 3.11 -1 -1 40568 -1 -1 250 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO 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k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 80.41 vpr 230.75 MiB -1 -1 14.04 99996 5 7.02 -1 -1 66224 -1 -1 721 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 236292 169 197 23225 21365 1 6061 1087 34 34 1156 clb auto 145.3 MiB 11.54 37017 593203 196123 370826 26254 203.3 MiB 8.12 0.08 3.50768 -13965.8 -3.50768 3.50768 1.39 0.0314237 0.026993 3.68019 3.10409 -1 -1 -1 -1 46 58126 45 6.50233e+07 3.88578e+07 3.64223e+06 3150.72 21.83 13.775 11.4226 123264 752332 -1 51405 13 15223 24254 807106 167773 3.87082 3.87082 -15222.1 -3.87082 0 0 4.69209e+06 4058.90 0.20 1.57 0.63 -1 -1 0.20 1.51477 1.34949 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 144.19 vpr 269.33 MiB -1 -1 12.21 122580 3 10.12 -1 -1 74072 -1 -1 768 115 0 40 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 275792 115 145 22864 19301 1 9609 1068 40 40 1600 mult_36 auto 143.1 MiB 11.43 79476 584967 186467 369840 28660 213.0 MiB 10.55 0.11 5.41341 -23480.4 -5.41341 5.41341 2.17 0.0319079 0.0275548 3.94511 3.37191 -1 -1 -1 -1 78 126298 33 9.16046e+07 5.72315e+07 8.23220e+06 5145.12 76.60 16.9981 14.2428 204032 1723206 -1 115064 14 29800 47012 6851687 1564903 5.46393 5.46393 -25542.6 -5.46393 0 0 1.04203e+07 6512.68 0.43 3.13 1.54 -1 -1 0.43 1.68782 1.49543 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 305.89 vpr 1.03 GiB -1 -1 16.73 194960 3 6.23 -1 -1 152176 -1 -1 1699 149 0 179 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1075592 149 182 55415 37074 1 28414 2209 80 80 6400 mult_36 auto 293.3 MiB 30.70 276200 2001029 706104 1220084 74841 1050.4 MiB 59.88 0.40 12.9413 -50214.8 -12.9413 12.9413 28.80 0.0899255 0.0755434 13.3433 11.2726 -1 -1 -1 -1 84 389613 48 3.90281e+08 1.62448e+08 3.63717e+07 5683.08 105.23 42.721 36.1082 857088 7768622 -1 366997 20 100923 120240 14759319 3128518 13.8463 13.8463 -54794.6 -13.8463 0 0 4.62462e+07 7225.96 2.39 8.04 7.35 -1 -1 2.39 4.60189 4.03624 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.86 vpr 65.79 MiB -1 -1 0.98 23176 4 0.13 -1 -1 32552 -1 -1 15 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67372 11 2 303 283 2 78 28 7 7 49 clb auto 26.2 MiB 0.22 262 1078 238 765 75 65.8 MiB 0.04 0.00 2.0391 -163.079 -2.0391 1.90116 0.04 0.00079628 0.000729774 0.0247413 0.0227926 -1 -1 -1 -1 28 333 12 1.07788e+06 808410 72669.7 1483.05 0.17 0.112952 0.0979406 3564 12808 -1 288 8 200 345 4799 1871 2.11979 1.94261 -165.174 -2.11979 0 0 87745.0 1790.71 0.00 0.03 0.01 -1 -1 0.00 0.022123 0.0200623 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 497.88 vpr 611.74 MiB -1 -1 77.76 452540 97 80.96 -1 -1 112748 -1 -1 2151 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 626424 114 102 35834 31925 1 16897 2420 56 56 3136 clb auto 279.1 MiB 70.81 224666 1805060 668533 1109456 27071 611.7 MiB 64.72 0.55 75.1122 -53345.7 -75.1122 75.1122 13.40 0.101362 0.0900982 12.5616 10.6146 -1 -1 -1 -1 88 335261 49 1.8697e+08 1.43756e+08 1.84122e+07 5871.24 134.02 47.1194 39.1334 423474 3861999 -1 307396 22 65997 258491 13780558 2468289 76.0017 76.0017 -64554.6 -76.0017 0 0 2.30976e+07 7365.31 1.10 10.19 3.64 -1 -1 1.10 6.17356 5.28565 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 2692.08 vpr 2.42 GiB -1 -1 242.89 1496112 97 858.98 -1 -1 355104 -1 -1 7513 114 168 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2535652 114 102 120350 108159 1 57345 7929 103 103 10609 clb auto 892.1 MiB 262.75 1003045 9728742 4018902 5663791 46049 2004.2 MiB 480.49 3.14 72.4024 -329114 -72.4024 72.4024 47.02 0.346214 0.301919 48.3359 40.4685 -1 -1 -1 -1 124 1323068 31 6.46441e+08 5.09602e+08 8.61045e+07 8116.18 587.22 199.076 163.111 1699828 18865638 -1 1270470 22 208280 903882 50603811 8413337 73.1548 73.1548 -457667 -73.1548 0 0 1.09063e+08 10280.2 5.97 39.87 20.11 -1 -1 5.97 22.9615 19.528 - k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5532.81 vpr 2.11 GiB -1 -1 301.74 1243688 25 2880.43 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 248896 133 179 14228 14085 1 7100 1192 37 37 1369 clb auto 137.3 MiB 29.37 266135 116292 607624 202148 389460 16016 197.5 MiB 11.96 0.11 36.2085 22.0917 -209321 -22.0917 22.0917 1.30 0.0362607 0.0326055 4.24626 3.52876 -1 -1 -1 -1 98 183926 48 7.54166e+07 5.97803e+07 8.55474e+06 6248.90 115.49 17.5043 14.4482 190708 1812325 -1 160975 15 32365 127542 9954229 1823700 23.0474 23.0474 -216590 -23.0474 0 0 1.08529e+07 7927.61 0.42 3.70 1.34 -1 -1 0.42 1.8165 1.60589 +k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 395.52 vpr 711.73 MiB -1 -1 46.70 618468 14 73.53 -1 -1 121516 -1 -1 2726 257 0 11 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 728808 257 32 36080 33722 1 19365 3026 63 63 3969 clb auto 330.3 MiB 62.66 1 247291 2190826 791581 1368690 30555 711.7 MiB 75.23 0.60 57.7426 19.5687 -25817.2 -19.5687 19.5687 14.64 0.100048 0.0915718 12.244 9.79811 -1 -1 -1 -1 72 383840 34 2.36641e+08 1.51273e+08 1.98694e+07 5006.15 77.18 35.852 29.2404 498330 4113940 -1 361511 21 93841 425892 16850398 2639390 19.686 19.686 -26274.8 -19.686 0 0 2.48734e+07 6266.93 1.20 10.41 2.87 -1 -1 1.20 5.89141 5.06974 +k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 57.20 parmys 254.52 MiB -1 -1 10.12 260628 5 3.65 -1 -1 54908 -1 -1 495 36 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 144616 36 100 10178 7632 1 2724 631 29 29 841 clb auto 96.8 MiB 14.41 97439 42545 241376 72681 154090 14605 140.5 MiB 3.96 0.04 27.6725 14.8675 -2411.82 -14.8675 14.8675 0.78 0.0177993 0.0163606 1.88812 1.64858 -1 -1 -1 -1 70 67015 21 4.4999e+07 2.66775e+07 3.87716e+06 4610.18 15.46 5.57727 4.81634 101140 791177 -1 62172 16 12850 65502 2552081 382161 15.0937 15.0937 -2598.2 -15.0937 0 0 4.87732e+06 5799.43 0.26 1.50 0.74 -1 -1 0.26 0.958764 0.852505 +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 16.43 vpr 71.90 MiB -1 -1 10.97 44964 3 0.60 -1 -1 35988 -1 -1 47 196 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73624 196 193 1201 1346 1 592 437 15 15 225 io auto 33.2 MiB 0.53 6911 3057 146253 37880 94608 13765 71.9 MiB 0.66 0.01 3.04383 2.21331 -1098.79 -2.21331 2.21331 0.27 0.00361775 0.00339713 0.322435 0.299654 -1 -1 -1 -1 38 5820 21 1.03862e+07 3.08102e+06 544116. 2418.30 1.87 0.930701 0.862606 21558 109668 -1 4978 10 1591 2448 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33800 -1 -1 32 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72196 162 96 1075 892 1 666 295 16 16 256 mult_36 auto 30.9 MiB 0.48 8583 5421 87604 32328 48998 6278 70.5 MiB 0.52 0.01 17.0345 15.9116 -1282.7 -15.9116 15.9116 0.35 0.00161197 0.00150016 0.239728 0.223735 -1 -1 -1 -1 56 11035 40 1.21132e+07 3.70461e+06 870502. 3400.40 4.56 0.816605 0.758167 27064 172478 -1 9127 22 3456 5983 1005760 304802 17.1604 17.1604 -1414.2 -17.1604 0 0 1.11200e+06 4343.75 0.03 0.27 0.11 -1 -1 0.03 0.101075 0.0953089 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 9.29 vpr 68.90 MiB -1 -1 0.31 21540 5 0.14 -1 -1 33800 -1 -1 21 66 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70552 66 96 778 595 1 468 188 16 16 256 mult_36 auto 29.8 MiB 0.57 6929 3851 46456 15752 25638 5066 68.9 MiB 0.28 0.00 13.1599 11.7559 -749.569 -11.7559 11.7559 0.33 0.0011598 0.00108633 0.134145 0.126067 -1 -1 -1 -1 42 9288 42 1.21132e+07 3.11177e+06 666202. 2602.35 6.12 0.737694 0.68405 24768 131944 -1 7591 22 3377 6818 1297563 374051 12.9969 12.9969 -873.1 -12.9969 0 0 835786. 3264.79 0.03 0.28 0.08 -1 -1 0.03 0.0745914 0.0703876 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 50.48 vpr 316.59 MiB -1 -1 11.09 116552 5 3.66 -1 -1 44796 -1 -1 468 506 44 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 324192 506 553 3236 3734 1 2870 1571 50 50 2500 memory auto 57.5 MiB 3.70 42225 16423 1151825 559617 409148 183060 316.6 MiB 3.18 0.04 9.60271 7.54011 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8 2.83 -1 -1 41916 -1 -1 247 385 2 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 103224 385 362 4415 4299 1 2357 997 26 26 676 io auto 57.2 MiB 5.42 60299 29833 558533 214306 321077 23150 97.5 MiB 4.08 0.05 12.9571 9.08653 -9982.73 -9.08653 9.08653 0.62 0.0118283 0.0111006 1.51022 1.3448 -1 -1 -1 -1 86 44651 39 3.69863e+07 1.48038e+07 3.69198e+06 5461.52 12.41 5.80252 5.20681 89040 769342 -1 41400 21 10076 33666 1743244 311635 9.30121 9.30121 -10341.1 -9.30121 0 0 4.67059e+06 6909.16 0.16 0.99 0.79 -1 -1 0.16 0.617813 0.571762 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 15.37 vpr 84.48 MiB -1 -1 2.70 42844 3 0.56 -1 -1 36996 -1 -1 127 236 1 6 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86512 236 305 3199 3011 1 1523 675 19 19 361 io auto 45.5 MiB 1.98 25195 12600 275862 99499 162512 13851 84.5 MiB 1.35 0.02 6.75568 4.64882 -2837.55 -4.64882 4.64882 0.31 0.00549613 0.00510822 0.566275 0.514224 -1 -1 -1 -1 62 23840 49 1.72706e+07 9.76854e+06 1.42198e+06 3939.00 5.85 2.24814 2.0487 40483 281719 -1 20436 15 5933 14959 1286779 322599 4.8554 4.8554 -3009.05 -4.8554 0 0 1.76637e+06 4892.99 0.06 0.47 0.17 -1 -1 0.06 0.250698 0.237004 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 9.91 vpr 83.59 MiB -1 -1 2.10 44688 3 1.07 -1 -1 39952 -1 -1 139 38 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85596 38 36 2739 2488 1 1049 213 16 16 256 clb auto 43.3 MiB 1.18 14059 8662 34503 7871 24229 2403 83.6 MiB 0.52 0.01 11.7745 10.1195 -2670 -10.1195 10.1195 0.19 0.00383665 0.00344661 0.246909 0.216894 -1 -1 -1 -1 58 13567 49 1.21132e+07 7.49127e+06 904541. 3533.36 2.69 1.35061 1.18242 27572 180683 -1 12180 19 4139 9511 324475 59593 10.8291 10.8291 -2841.73 -10.8291 0 0 1.15318e+06 4504.63 0.04 0.30 0.11 -1 -1 0.04 0.222745 0.202612 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 16.93 vpr 73.76 MiB -1 -1 1.98 32292 16 0.59 -1 -1 34884 -1 -1 61 45 3 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75528 45 32 1192 1151 1 792 142 14 14 196 memory auto 35.0 MiB 2.68 10043 6565 23822 6254 15540 2028 73.8 MiB 0.59 0.01 13.3138 11.239 -7207.5 -11.239 11.239 0.24 0.00448329 0.00410023 0.332932 0.298965 -1 -1 -1 -1 64 12481 30 9.20055e+06 5.32753e+06 762053. 3888.03 8.48 2.38399 2.14556 22040 150681 -1 10537 14 3342 8767 663858 168108 11.6206 11.6206 -7527.99 -11.6206 0 0 953435. 4864.47 0.04 0.35 0.18 -1 -1 0.04 0.188032 0.175235 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 69.35 vpr 236.99 MiB -1 -1 10.22 98344 5 11.48 -1 -1 65608 -1 -1 723 169 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 242676 169 197 23225 21365 1 6048 1089 34 34 1156 clb auto 158.7 MiB 7.61 135279 37585 577889 189065 363964 24860 205.9 MiB 7.38 0.09 6.79679 3.48144 -13874.2 -3.48144 3.48144 1.20 0.0367946 0.0320323 3.53071 2.995 -1 -1 -1 -1 46 59522 44 6.50233e+07 3.89656e+07 3.64223e+06 3150.72 18.71 11.9208 10.1086 123264 752332 -1 52482 14 15977 25751 857559 179259 3.70894 3.70894 -15069.9 -3.70894 0 0 4.69209e+06 4058.90 0.20 1.32 0.74 -1 -1 0.20 1.26195 1.14674 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 107.97 vpr 304.24 MiB -1 -1 10.05 121396 3 10.65 -1 -1 73876 -1 -1 761 115 0 40 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 311540 115 145 22864 19301 1 9598 1061 40 40 1600 mult_36 auto 157.2 MiB 7.70 216707 80047 579824 190762 365771 23291 228.1 MiB 8.16 0.08 7.82034 5.55779 -23040.2 -5.55779 5.55779 2.29 0.0215767 0.0190627 3.0521 2.59567 -1 -1 -1 -1 82 124601 48 9.16046e+07 5.68542e+07 8.58295e+06 5364.35 54.09 17.337 14.8874 207228 1787768 -1 113911 14 29248 44540 5876852 1327853 5.72835 5.72835 -25879.2 -5.72835 0 0 1.07702e+07 6731.38 0.48 2.39 1.35 -1 -1 0.48 1.37334 1.26744 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 273.92 vpr 939.73 MiB -1 -1 13.85 194876 3 5.84 -1 -1 151880 -1 -1 1693 149 0 179 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 962288 149 182 55415 37074 1 28410 2203 80 80 6400 mult_36 auto 318.0 MiB 25.88 1 279853 2022451 708543 1241399 72509 939.7 MiB 46.68 0.31 27.175 13.8922 -50923.4 -13.8922 13.8922 30.81 0.0656328 0.0591708 10.1964 8.76379 -1 -1 -1 -1 84 384146 39 3.90281e+08 1.62125e+08 3.63717e+07 5683.08 102.27 44.1695 37.9463 857088 7768622 -1 367849 21 98815 117998 14005042 3008515 14.8174 14.8174 -56086.4 -14.8174 0 0 4.62462e+07 7225.96 2.53 7.16 5.76 -1 -1 2.53 4.08161 3.62281 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.16 vpr 66.80 MiB -1 -1 0.44 22692 4 0.11 -1 -1 33008 -1 -1 15 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68408 11 2 303 283 2 85 28 7 7 49 clb auto 27.5 MiB 0.20 462 294 1372 325 946 101 66.8 MiB 0.04 0.00 2.20626 2.0391 -157.497 -2.0391 1.90116 0.04 0.000720929 0.000639654 0.0290609 0.0262716 -1 -1 -1 -1 26 435 16 1.07788e+06 808410 68696.0 1401.96 0.33 0.197388 0.171083 3516 12294 -1 372 15 293 527 8455 3007 2.11125 1.89738 -161.275 -2.11125 0 0 84249.8 1719.38 0.00 0.04 0.01 -1 -1 0.00 0.0298989 0.0270866 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 455.11 vpr 590.73 MiB -1 -1 48.28 451352 97 86.37 -1 -1 110592 -1 -1 2144 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 604904 114 102 35834 31925 1 16899 2413 56 56 3136 clb auto 311.6 MiB 54.53 934215 218876 1830527 680211 1116146 34170 590.7 MiB 76.63 0.49 142.326 73.8063 -53329.6 -73.8063 73.8063 12.23 0.089699 0.0819079 14.4758 11.8124 -1 -1 -1 -1 86 331425 45 1.8697e+08 1.43379e+08 1.79819e+07 5734.03 137.97 42.5414 34.9669 420342 3799571 -1 301758 22 66654 261893 13479107 2432831 73.243 73.243 -66857.7 -73.243 0 0 2.27638e+07 7258.87 1.06 8.85 2.83 -1 -1 1.06 5.46509 4.6883 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 5085.56 vpr 2.00 GiB -1 -1 160.14 1452796 97 895.48 -1 -1 354436 -1 -1 7478 114 168 32 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2093276 114 102 120350 108159 1 57530 7894 102 102 10404 clb auto 1002.8 MiB 178.54 5 937620 9671512 3979219 5647220 45073 1897.7 MiB 498.57 2.88 186.365 72.9848 -317425 -72.9848 72.9848 40.28 0.354498 0.271431 49.7107 39.17 -1 -1 -1 -1 112 1263786 24 6.36957e+08 5.07716e+08 7.72010e+07 7420.32 3176.91 152.247 121.841 1584492 16730607 -1 1213440 21 216534 945339 50802610 8610369 74.2493 74.2493 -440401 -74.2493 0 0 9.78368e+07 9403.76 4.47 30.31 13.30 -1 -1 4.47 18.2361 15.3655 +k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 4271.47 vpr 2.07 GiB -1 -1 192.31 1212884 25 2963.89 -1 -1 367440 -1 -1 6759 36 159 27 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2170912 36 356 185159 159806 1 63407 7337 98 98 9604 clb auto 1175.9 MiB 160.15 4 726368 10055420 3866973 6000930 187517 2081.1 MiB 528.58 3.09 138.532 56.0715 -322739 -56.0715 56.0715 35.68 0.267313 0.237876 43.3544 35.7269 -1 -1 -1 -1 124 951238 25 5.9175e+08 4.62062e+08 7.79543e+07 8116.86 256.86 141.996 117.65 1542384 17086260 -1 922124 23 211344 490899 28645964 5116509 55.8407 55.8407 -362186 -55.8407 0 0 9.87684e+07 10284.1 4.81 23.81 14.26 -1 -1 4.81 17.1091 14.4811 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt index cf218b6f42d..8d45c568ac5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -1,20 +1,20 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 220.60 vpr 258.80 MiB -1 -1 32.77 121676 20 41.63 -1 -1 67228 -1 -1 857 133 25 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 265012 133 179 14228 14085 1 7013 1194 37 37 1369 clb auto 123.2 MiB 52.98 117241 583646 194344 373759 15543 184.7 MiB 13.08 0.13 22.6552 -207062 -22.6552 22.6552 1.62 0.0407574 0.0356824 4.19626 3.54119 -1 -1 -1 -1 102 177496 34 7.54166e+07 5.98881e+07 8.84326e+06 6459.65 56.40 16.9397 14.0699 193444 1864326 -1 162723 14 31022 120994 9555365 1733447 24.3598 24.3598 -215921 -24.3598 0 0 1.10984e+07 8106.95 0.39 4.72 1.75 -1 -1 0.39 2.18738 1.88506 - k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 459.06 vpr 747.54 MiB -1 -1 66.92 634636 14 66.21 -1 -1 121812 -1 -1 2741 257 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 765484 257 32 36080 33722 1 19295 3041 63 63 3969 clb auto 299.9 MiB 91.07 246576 2183219 779788 1375542 27889 747.5 MiB 63.52 0.58 18.719 -25586.3 -18.719 18.719 16.30 0.0997124 0.0890543 11.1519 9.38394 -1 -1 -1 -1 70 390691 45 2.36641e+08 1.52081e+08 1.93981e+07 4887.41 92.61 39.2846 32.3608 494362 4028736 -1 366303 20 98427 446372 17944375 2776232 18.5784 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/home/elgamma8/research/release/vtr-verilog-to-routing 67316 99 130 344 474 1 227 298 12 12 144 clb auto 26.6 MiB 0.27 728 65968 18859 34313 12796 65.7 MiB 0.23 0.00 1.84343 -119.549 -1.84343 1.84343 0.14 0.00129356 0.00122501 0.0899037 0.0850148 -1 -1 -1 -1 38 1521 13 5.66058e+06 4.21279e+06 319126. 2216.15 1.20 0.526166 0.481346 12802 62767 -1 1190 8 347 541 19340 5772 2.02505 2.02505 -132.661 -2.02505 0 0 406307. 2821.58 0.01 0.04 0.06 -1 -1 0.01 0.0292785 0.0272629 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 17.74 vpr 68.76 MiB -1 -1 0.55 22212 5 0.17 -1 -1 34256 -1 -1 32 162 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70408 162 96 1075 892 1 665 295 16 16 256 mult_36 auto 29.5 MiB 0.46 5192 86623 30832 48552 7239 68.8 MiB 0.65 0.01 15.9204 -1248.52 -15.9204 15.9204 0.26 0.00323801 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81964 311 156 1015 1158 1 965 514 28 28 784 memory auto 31.4 MiB 0.84 8982 206314 76497 119197 10620 72.3 MiB 1.22 0.02 4.5269 -4391.67 -4.5269 4.5269 0.93 0.00579142 0.00513528 0.604532 0.536129 -1 -1 -1 -1 40 14593 15 4.25198e+07 9.94461e+06 2.13295e+06 2720.61 7.26 2.55624 2.26242 78662 432578 -1 13692 13 2679 3112 717136 216657 4.28969 4.28969 -5035.02 -4.28969 0 0 2.67004e+06 3405.67 0.10 0.36 0.37 -1 -1 0.10 0.216825 0.197387 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 39.85 vpr 81.62 MiB -1 -1 8.43 52680 5 1.64 -1 -1 39440 -1 -1 170 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83584 193 205 2718 2652 1 1367 573 20 20 400 memory auto 40.8 MiB 3.01 10921 238473 79955 132805 25713 81.6 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73824 45 32 1192 1151 1 782 141 14 14 196 memory auto 32.6 MiB 2.64 6823 26859 7335 15944 3580 72.1 MiB 0.56 0.01 10.958 -7233.76 -10.958 10.958 0.20 0.00348886 0.00309362 0.282542 0.250806 -1 -1 -1 -1 66 13449 49 9.20055e+06 5.27364e+06 787562. 4018.17 4.34 1.29546 1.12707 22236 154735 -1 10952 14 3335 8795 693161 168301 11.3764 11.3764 -7707.18 -11.3764 0 0 978561. 4992.66 0.03 0.31 0.14 -1 -1 0.03 0.156586 0.142149 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 70.08 vpr 230.16 MiB -1 -1 13.83 100176 5 5.66 -1 -1 66176 -1 -1 721 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 235688 169 197 23225 21365 1 6061 1087 34 34 1156 clb auto 145.2 MiB 11.37 38474 604375 204189 371506 28680 203.8 MiB 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min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 212.47 vpr 279.51 MiB -1 -1 19.33 119976 20 47.22 -1 -1 68076 -1 -1 855 133 25 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 286220 133 179 14228 14085 1 7100 1192 37 37 1369 clb auto 135.8 MiB 30.67 264290 118331 588673 187049 381129 20495 196.5 MiB 10.93 0.10 32.7899 22.873 -208698 -22.873 22.873 1.43 0.0324797 0.0292432 3.84677 3.23963 -1 -1 -1 -1 110 176725 27 7.54166e+07 5.97803e+07 9.46577e+06 6914.37 87.45 21.2205 17.8322 201652 2027183 -1 162249 14 30432 117983 9007020 1696919 24.0504 24.0504 -216487 -24.0504 0 0 1.20852e+07 8827.75 0.45 3.53 1.54 -1 -1 0.45 1.77327 1.56805 +k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 482.62 vpr 710.52 MiB -1 -1 45.25 619668 14 76.05 -1 -1 122284 -1 -1 2726 257 0 11 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 727576 257 32 36080 33722 1 19365 3026 63 63 3969 clb auto 329.7 MiB 70.76 1 246198 2147070 770352 1350261 26457 710.5 MiB 79.70 0.59 60.4933 18.7554 -25815 -18.7554 18.7554 16.05 0.0947419 0.0860547 13.1929 10.7692 -1 -1 -1 -1 72 383970 26 2.36641e+08 1.51273e+08 1.98694e+07 5006.15 146.80 56.49 46.364 498330 4113940 -1 361584 22 95063 428737 17085321 2684393 19.1335 19.1335 -26346.5 -19.1335 0 0 2.48734e+07 6266.93 1.24 12.09 2.89 -1 -1 1.24 6.67177 5.73047 +k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 68.96 parmys 254.32 MiB -1 -1 10.19 260420 5 3.55 -1 -1 54908 -1 -1 495 36 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 143288 36 100 10178 7632 1 2724 631 29 29 841 clb auto 96.0 MiB 15.82 95360 41180 227851 69677 144196 13978 139.9 MiB 4.01 0.04 22.4661 14.8203 -2362.24 -14.8203 14.8203 0.86 0.0174468 0.0161202 1.90119 1.64273 -1 -1 -1 -1 68 66817 22 4.4999e+07 2.66775e+07 3.78783e+06 4503.96 24.80 6.79508 5.87269 99460 760244 -1 60459 14 12442 64371 2376927 356438 15.0178 15.0178 -2542.17 -15.0178 0 0 4.70015e+06 5588.76 0.18 1.64 0.67 -1 -1 0.18 0.999677 0.893759 +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 15.71 vpr 71.91 MiB -1 -1 11.65 44576 3 0.60 -1 -1 35600 -1 -1 47 196 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73640 196 193 1201 1346 1 592 437 15 15 225 io auto 33.1 MiB 0.52 7097 3082 141282 36274 93188 11820 71.9 MiB 0.39 0.01 2.88013 2.23271 -1111.45 -2.23271 2.23271 0.17 0.00181996 0.00167433 0.170233 0.157242 -1 -1 -1 -1 38 6015 35 1.03862e+07 3.08102e+06 544116. 2418.30 0.99 0.562766 0.519528 21558 109668 -1 5038 10 1765 2614 165080 48924 2.65248 2.65248 -1216.21 -2.65248 0 0 690508. 3068.92 0.02 0.10 0.06 -1 -1 0.02 0.070957 0.0676966 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.27 vpr 66.99 MiB -1 -1 0.38 18464 3 0.07 -1 -1 33120 -1 -1 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68596 99 130 344 474 1 228 298 12 12 144 clb auto 28.3 MiB 0.16 1708 681 71938 21850 35232 14856 67.0 MiB 0.12 0.00 2.12112 1.86413 -119.258 -1.86413 1.86413 0.10 0.000566216 0.000530411 0.0447479 0.0419328 -1 -1 -1 -1 42 1388 10 5.66058e+06 4.21279e+06 345696. 2400.67 0.67 0.20809 0.190737 13090 66981 -1 1237 10 456 706 29446 8797 1.96058 1.96058 -139.503 -1.96058 0 0 434636. 3018.30 0.01 0.03 0.04 -1 -1 0.01 0.0198907 0.018763 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 6.34 vpr 70.60 MiB -1 -1 0.40 22304 5 0.21 -1 -1 33772 -1 -1 32 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72292 162 96 1075 892 1 666 295 16 16 256 mult_36 auto 31.3 MiB 0.47 8262 5112 85642 26726 51784 7132 70.6 MiB 0.61 0.01 16.5991 15.8982 -1286.15 -15.8982 15.8982 0.35 0.00310373 0.00289519 0.287074 0.267623 -1 -1 -1 -1 52 9636 23 1.21132e+07 3.70461e+06 805949. 3148.24 2.31 0.817068 0.760008 26552 162987 -1 8698 17 2587 4144 731400 221181 17.1356 17.1356 -1376.18 -17.1356 0 0 1.06067e+06 4143.25 0.04 0.37 0.15 -1 -1 0.04 0.174555 0.164858 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 18.31 vpr 68.98 MiB -1 -1 0.20 21540 5 0.09 -1 -1 33460 -1 -1 21 66 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70640 66 96 778 595 1 468 188 16 16 256 mult_36 auto 29.4 MiB 0.36 6204 3763 43766 14011 25945 3810 69.0 MiB 0.21 0.00 13.1588 11.8959 -748.769 -11.8959 11.8959 0.19 0.00113406 0.00106371 0.101179 0.0951234 -1 -1 -1 -1 60 7674 24 1.21132e+07 3.11177e+06 934704. 3651.19 15.60 0.842417 0.781631 27828 185084 -1 6554 21 3570 7405 1259231 373839 12.6374 12.6374 -804.724 -12.6374 0 0 1.17753e+06 4599.72 0.05 0.41 0.19 -1 -1 0.05 0.119941 0.113336 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 397.07 vpr 588.61 MiB -1 -1 47.51 442352 97 87.76 -1 -1 111932 -1 -1 2144 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 602736 114 102 35834 31925 1 16899 2413 56 56 3136 clb auto 309.4 MiB 53.73 920886 213746 1814349 675153 1108132 31064 588.6 MiB 55.30 0.51 154.738 72.3421 -53235.9 -72.3421 72.3421 11.14 0.111004 0.0889287 11.5817 9.28701 -1 -1 -1 -1 86 321106 26 1.8697e+08 1.43379e+08 1.79819e+07 5734.03 92.36 40.2067 32.6519 420342 3799571 -1 296141 22 64120 253670 12914238 2332073 74.2773 74.2773 -68437.4 -74.2773 0 0 2.27638e+07 7258.87 1.70 13.36 4.62 -1 -1 1.70 8.68523 7.49958 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 50.68 vpr 315.80 MiB -1 -1 10.11 117064 5 5.53 -1 -1 44796 -1 -1 468 506 44 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 323384 506 553 3236 3734 1 2870 1571 50 50 2500 memory auto 57.7 MiB 3.71 43258 16890 1151825 563056 405712 183057 315.8 MiB 3.48 0.04 10.3136 6.751 -2071.22 -6.751 6.751 9.71 0.012349 0.0113575 1.79514 1.64399 -1 -1 -1 -1 38 24480 15 1.47946e+08 4.9335e+07 6.86579e+06 2746.32 9.05 5.36946 5.00747 258216 1426232 -1 23492 14 4552 6284 1218142 310467 6.93887 6.93887 -2608.52 -6.93887 0 0 8.69102e+06 3476.41 0.38 0.71 1.07 -1 -1 0.38 0.528311 0.503268 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 8.15 vpr 73.20 MiB -1 -1 0.80 25764 2 0.10 -1 -1 34472 -1 -1 32 311 15 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74952 311 156 1015 1158 1 965 514 28 28 784 memory auto 33.9 MiB 0.79 20788 7954 214546 78290 125007 11249 73.2 MiB 0.67 0.01 5.14999 3.96264 -4383.87 -3.96264 3.96264 0.70 0.00278678 0.00248288 0.315079 0.280645 -1 -1 -1 -1 38 13997 22 4.25198e+07 9.94461e+06 2.03941e+06 2601.29 2.23 0.858239 0.774237 77878 418209 -1 12797 12 2813 3148 647576 204191 4.19809 4.19809 -4942.1 -4.19809 -0.00135869 -0.00135869 2.58563e+06 3298.00 0.09 0.23 0.25 -1 -1 0.09 0.125259 0.116996 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 19.47 vpr 83.66 MiB -1 -1 4.55 51492 5 1.45 -1 -1 39328 -1 -1 166 193 5 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85672 193 205 2718 2652 1 1364 569 20 20 400 memory auto 44.0 MiB 1.94 21635 10677 236269 74431 136781 25057 83.7 MiB 1.26 0.01 6.95823 5.89435 -2880.21 -5.89435 5.89435 0.33 0.00448873 0.00407934 0.520725 0.458822 -1 -1 -1 -1 50 19020 48 2.07112e+07 1.16864e+07 1.26946e+06 3173.65 7.33 2.53112 2.27541 41784 253636 -1 16909 18 4979 12133 652802 138307 6.28852 6.28852 -3109.62 -6.28852 -0.00135869 -0.00135869 1.63222e+06 4080.54 0.05 0.37 0.15 -1 -1 0.05 0.246451 0.229778 +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 112.46 vpr 101.39 MiB -1 -1 3.74 61476 8 2.81 -1 -1 41920 -1 -1 247 385 2 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 103820 385 362 4415 4299 1 2357 997 26 26 676 io auto 56.8 MiB 5.49 60367 29168 553555 209559 320264 23732 97.1 MiB 4.21 0.04 12.484 9.22286 -10001.9 -9.22286 9.22286 0.61 0.0109639 0.0102538 1.47142 1.32279 -1 -1 -1 -1 96 41816 25 3.69863e+07 1.48038e+07 4.07810e+06 6032.69 88.96 8.68882 7.83852 93088 846470 -1 40322 20 9413 32446 1640117 290110 9.26797 9.26797 -10463.8 -9.26797 0 0 5.10087e+06 7545.67 0.27 1.53 0.96 -1 -1 0.27 1.0006 0.922311 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 16.70 vpr 84.32 MiB -1 -1 2.91 42012 3 0.56 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86348 236 305 3199 3011 1 1523 675 19 19 361 io auto 45.1 MiB 2.38 25623 12744 275862 97068 164529 14265 84.3 MiB 1.45 0.02 6.4321 4.87079 -2820.2 -4.87079 4.87079 0.30 0.00560063 0.00518298 0.604935 0.553038 -1 -1 -1 -1 60 23814 39 1.72706e+07 9.76854e+06 1.37250e+06 3801.94 6.34 2.17617 1.98275 40123 275431 -1 20936 19 6245 16081 1455169 369652 4.86514 4.86514 -3116.44 -4.86514 0 0 1.72840e+06 4787.81 0.05 0.53 0.17 -1 -1 0.05 0.287741 0.270352 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 14.92 vpr 83.92 MiB -1 -1 2.98 44692 3 1.09 -1 -1 39956 -1 -1 139 38 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85932 38 36 2739 2488 1 1049 213 16 16 256 clb auto 43.6 MiB 1.25 14747 8429 40218 10764 26818 2636 83.9 MiB 0.67 0.01 12.6186 10.0194 -2444.29 -10.0194 10.0194 0.20 0.00478325 0.0044014 0.318391 0.282226 -1 -1 -1 -1 52 14156 42 1.21132e+07 7.49127e+06 805949. 3148.24 6.25 1.87194 1.62272 26552 162987 -1 12220 20 4506 10512 364577 68819 10.9834 10.9834 -2789.57 -10.9834 0 0 1.06067e+06 4143.25 0.03 0.34 0.10 -1 -1 0.03 0.248301 0.225121 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 10.99 vpr 73.14 MiB -1 -1 2.17 32292 16 0.48 -1 -1 34992 -1 -1 61 45 3 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74900 45 32 1192 1151 1 792 142 14 14 196 memory auto 34.6 MiB 2.57 10230 6724 27522 7495 16921 3106 73.1 MiB 0.34 0.00 13.9782 11.2901 -7209.19 -11.2901 11.2901 0.14 0.00197313 0.00176092 0.168386 0.150089 -1 -1 -1 -1 68 12586 25 9.20055e+06 5.32753e+06 806220. 4113.37 3.63 0.879144 0.780585 22432 157909 -1 10569 14 3362 8864 714686 176877 11.347 11.347 -7521.29 -11.347 0 0 1.00082e+06 5106.22 0.03 0.22 0.10 -1 -1 0.03 0.118227 0.11088 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 49.68 vpr 238.52 MiB -1 -1 8.91 99444 5 6.21 -1 -1 65612 -1 -1 723 169 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 244244 169 197 23225 21365 1 6048 1089 34 34 1156 clb auto 159.4 MiB 7.36 138950 37803 566689 185725 358886 22078 206.7 MiB 5.55 0.05 7.50543 3.47733 -14028.3 -3.47733 3.47733 1.08 0.0240631 0.0193328 2.6984 2.20346 -1 -1 -1 -1 46 59195 29 6.50233e+07 3.89656e+07 3.64223e+06 3150.72 9.78 7.53696 6.32877 123264 752332 -1 52144 15 15228 24079 778526 165004 3.95658 3.95658 -15092.4 -3.95658 0 0 4.69209e+06 4058.90 0.19 1.34 0.44 -1 -1 0.19 1.3312 1.21354 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 129.15 vpr 301.43 MiB -1 -1 6.97 121944 3 10.79 -1 -1 73876 -1 -1 761 115 0 40 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 308664 115 145 22864 19301 1 9598 1061 40 40 1600 mult_36 auto 157.2 MiB 8.89 218173 82528 552779 175008 354397 23374 227.7 MiB 12.42 0.08 8.24796 5.97877 -23026.7 -5.97877 5.97877 2.52 0.0296366 0.0232576 5.18169 4.47986 -1 -1 -1 -1 82 129392 40 9.16046e+07 5.68542e+07 8.58295e+06 5364.35 72.16 18.2188 15.5745 207228 1787768 -1 115904 12 29451 44673 6496904 1453626 6.28596 6.28596 -25323 -6.28596 0 0 1.07702e+07 6731.38 0.42 2.40 1.26 -1 -1 0.42 1.27287 1.1697 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 249.03 vpr 927.26 MiB -1 -1 10.71 194260 3 5.49 -1 -1 151880 -1 -1 1693 149 0 179 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 949512 149 182 55415 37074 1 28410 2203 80 80 6400 mult_36 auto 317.6 MiB 24.65 1 282083 1936483 673873 1194432 68178 927.3 MiB 53.04 0.41 29.8396 13.6204 -50663.4 -13.6204 13.6204 26.08 0.0857036 0.0779151 11.8098 10.1507 -1 -1 -1 -1 86 389128 32 3.90281e+08 1.62125e+08 3.72333e+07 5817.70 84.75 35.4904 30.579 863488 7902436 -1 370287 22 99498 118781 13877842 2992969 13.7303 13.7303 -54909.4 -13.7303 0 0 4.71374e+07 7365.22 2.26 7.09 5.78 -1 -1 2.26 4.22602 3.76697 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.81 vpr 66.79 MiB -1 -1 0.48 22692 4 0.11 -1 -1 32964 -1 -1 15 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68392 11 2 303 283 2 85 28 7 7 49 clb auto 27.5 MiB 0.12 405 294 1078 210 791 77 66.8 MiB 0.02 0.00 2.07098 2.04849 -155.044 -2.04849 1.9058 0.02 0.000390247 0.00034808 0.0136362 0.0123455 -1 -1 -1 -1 34 389 13 1.07788e+06 808410 84249.8 1719.38 0.24 0.135196 0.115303 3756 15224 -1 348 10 168 283 4715 1617 2.10231 1.90634 -156.224 -2.10231 0 0 103542. 2113.11 0.00 0.03 0.01 -1 -1 0.00 0.025836 0.0238112 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt index 82805da6c73..41f25935228 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 244.09 vpr 1.63 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1710388 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.8 MiB 72.33 204820 846239 237450 497497 111292 1670.3 MiB 74.90 0.65 7.79489 -43439.9 -6.79489 3.28078 0.10 0.145044 0.126909 16.2828 14.2166 303821 13.2372 69243 3.01686 62436 131482 118528064 33642231 0 0 9.32900e+07 21594.9 16 1265168 16897716 -1 7.83099 3.2527 -39766.3 -6.83099 0 0 28.25 -1 -1 1670.3 MiB 34.12 23.3299 20.6779 1670.3 MiB -1 9.52 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 283.46 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1568820 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.9 MiB 100.65 250483 930441 270744 617644 42053 1427.9 MiB 105.66 1.16 88.0477 -77760.6 -87.0477 88.0477 0.04 0.138248 0.121195 14.6541 12.2965 344948 13.2210 84158 3.22556 78118 205246 82686512 15002058 0 0 5.14202e+07 21425.1 21 702232 9282330 -1 70.8752 70.8752 -96523.7 -69.8752 0 0 15.93 -1 -1 1478.1 MiB 30.26 22.7139 19.3696 1427.9 MiB -1 5.06 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 546.32 vpr 1.95 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2047732 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.8 MiB 197.71 509639 1864099 634981 1176586 52532 1902.3 MiB 202.15 1.98 13.0046 -365555 -12.0046 7.96311 0.08 0.240136 0.202587 26.0846 21.1277 742613 20.9997 172139 4.86777 125805 451636 168920802 27374866 0 0 1.14226e+08 21633.7 20 1553068 20716258 -1 12.6705 7.40682 -365097 -11.6705 0 0 34.41 -1 -1 1902.3 MiB 62.35 40.2332 33.4484 1902.3 MiB -1 12.28 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 585.36 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2009276 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.3 MiB 179.14 542870 2585506 917648 1577326 90532 1765.2 MiB 247.87 2.16 32.1444 -118378 -31.1444 6.23584 0.07 0.26061 0.217278 28.1774 23.7022 787384 20.0781 179841 4.58591 168930 665993 263454811 44272964 0 0 8.35478e+07 21555.2 21 1135740 15114436 -1 31.2519 6.12513 -116198 -30.2519 0 0 26.38 -1 -1 1858.7 MiB 86.58 43.2996 37.0968 1765.2 MiB -1 8.44 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 665.68 vpr 4.50 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4722308 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.9 MiB 143.60 659423 3667920 1455149 2188340 24431 4611.6 MiB 189.33 1.99 5.44974 -115422 -4.44974 3.12297 0.45 0.489655 0.429947 60.4384 53.4484 794955 11.5117 173671 2.51493 139983 173257 122973577 32392189 0 0 5.40274e+08 21813.4 12 7186500 97663758 -1 5.74024 3.40489 -147279 -4.74024 0 0 162.31 -1 -1 4611.6 MiB 45.39 79.3348 71.0438 4611.6 MiB -1 68.45 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 369.28 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1705764 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.4 MiB 132.64 278563 1870082 659393 1159933 50756 1577.3 MiB 148.04 1.40 223.632 -132177 -222.632 223.632 0.05 0.153184 0.136333 19.0846 16.0118 379374 13.4069 91772 3.24317 82642 255456 77638931 11638769 0 0 7.07061e+07 21491.2 20 956596 12773992 -1 190.135 190.135 -130112 -189.135 0 0 21.26 -1 -1 1598.5 MiB 30.66 28.1882 24.0263 1577.3 MiB -1 6.97 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 301.91 vpr 1.70 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1787064 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.6 MiB 111.07 267316 798034 216514 557130 24390 1745.2 MiB 83.83 0.97 17.6841 -330571 -16.6841 17.6841 0.08 0.142592 0.123421 13.5697 11.1733 388393 14.4100 90639 3.36285 77554 201450 104702784 19227779 0 0 1.03316e+08 21578.1 23 1396452 18714052 -1 16.8884 16.8884 -322143 -15.8884 0 0 31.36 -1 -1 1745.2 MiB 37.27 22.9987 19.4136 1745.2 MiB -1 9.87 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 129.79 vpr 1.23 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1288736 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 60.90 109402 531288 160105 346309 24874 1229.7 MiB 21.34 0.27 7.65386 -81772.1 -6.65386 7.65386 0.03 0.0542655 0.0415901 4.69487 3.74852 159807 19.3237 38947 4.70943 27112 111164 42415566 5550679 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 7.62538 7.62538 -77759.3 -6.62538 0 0 10.12 -1 -1 1229.7 MiB 15.08 7.2902 6.0554 1229.7 MiB -1 2.80 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 294.21 vpr 1.53 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1605968 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.4 MiB 149.56 245617 1517216 535912 903537 77767 1503.4 MiB 67.74 0.64 12.3707 -91754.7 -11.3707 4.62772 0.04 0.123763 0.0993875 12.5521 10.1851 366533 18.0443 84029 4.13671 58196 217697 65258498 9131006 0 0 6.38257e+07 21490.1 17 866116 11532596 -1 12.1773 4.52077 -87689.2 -11.1773 0 0 19.45 -1 -1 1503.4 MiB 24.63 19.0845 15.7987 1503.4 MiB -1 5.86 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 373.27 vpr 2.31 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2418176 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.2 MiB 113.69 225912 2286656 861887 1362579 62190 2361.5 MiB 99.88 0.94 9.64748 -102230 -8.64748 9.64748 0.14 0.158799 0.128764 21.1153 17.3148 383721 19.4260 88332 4.47183 55000 174045 129359271 32477749 0 0 2.01410e+08 21605.9 18 2701980 36491882 -1 8.6078 8.6078 -177231 -7.6078 0 0 60.49 -1 -1 2361.5 MiB 43.58 29.7071 24.9856 2361.5 MiB -1 22.04 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 287.89 vpr 2.03 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2130704 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.2 MiB 94.47 222406 1491426 518693 900478 72255 2080.8 MiB 60.89 0.53 9.27552 -41609.1 -8.27552 3.17342 0.13 0.131124 0.103107 15.5709 12.4005 371010 17.4897 81992 3.86518 55375 161185 120683489 26150077 0 0 1.70845e+08 21669.8 17 2296616 31015204 -1 9.29871 3.26388 -44629 -8.29871 0 0 50.69 -1 -1 2080.8 MiB 36.84 22.1828 18.2794 2080.8 MiB -1 17.67 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 115.46 vpr 1.42 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1487204 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 45.32 98385 149036 34562 99301 15173 1452.3 MiB 10.21 0.11 5.55968 -32411 -4.55968 4.12503 0.05 0.05808 0.0509959 5.30612 4.48561 158711 21.0019 34047 4.50536 20479 45132 33648692 7897451 0 0 7.61223e+07 21576.6 14 1038076 13772104 -1 5.83812 3.95731 -37986.2 -4.83812 0 0 22.99 -1 -1 1452.3 MiB 10.69 8.06663 7.00321 1452.3 MiB -1 7.95 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 308.79 vpr 1.75 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1838356 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1276.3 MiB 90.95 215620 2002487 658856 1202364 141267 1795.3 MiB 112.04 0.92 42.7601 -66808.9 -41.7601 42.7601 0.09 0.161772 0.13883 20.582 17.6888 320121 12.3518 76529 2.95285 71977 215082 87258601 20096356 0 0 1.07584e+08 21568.7 22 1452444 19486512 -1 38.7113 38.7113 -63596.1 -37.7113 0 0 32.70 -1 -1 1795.3 MiB 31.75 30.3911 26.5086 1795.3 MiB -1 11.75 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 194.32 vpr 1.76 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1848104 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1132.2 MiB 67.11 123583 1109975 381766 683735 44474 1804.8 MiB 39.31 0.39 9.15523 -32316.9 -8.15523 9.15523 0.10 0.0795356 0.0699448 8.32413 7.00496 172751 13.5928 41221 3.24345 30616 114657 28576108 5137032 0 0 1.28005e+08 21615.1 15 1733724 23216534 -1 8.8255 8.62305 -32652.3 -7.8255 0 0 39.07 -1 -1 1804.8 MiB 12.08 12.4456 10.6768 1804.8 MiB -1 13.32 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 379.96 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1788552 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1329.9 MiB 152.43 244085 1624747 493620 1093099 38028 1607.0 MiB 139.05 1.16 10.4142 -184930 -9.41415 10.4142 0.05 0.16033 0.126535 18.0534 14.5425 331959 9.29987 79923 2.23905 99630 253842 70436166 10502572 0 0 7.07061e+07 21491.2 17 956596 12773992 -1 9.6278 9.6278 -188775 -8.6278 0 0 21.47 -1 -1 1660.8 MiB 28.25 26.8951 22.1285 1607.0 MiB -1 7.63 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 241.84 vpr 1.65 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1727976 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.3 MiB 91.18 155434 1168868 372786 754711 41371 1617.1 MiB 70.29 0.65 5.78947 -22744 -4.78947 5.78947 0.06 0.166564 0.140884 17.2708 14.567 220363 9.18294 52613 2.19248 52262 94777 51757158 12255510 0 0 7.61223e+07 21576.6 17 1038076 13772104 -1 6.13383 6.13383 -28632.3 -5.13383 0 0 23.67 -1 -1 1626.7 MiB 20.25 25.2854 21.7301 1617.1 MiB -1 7.50 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 123.74 vpr 1.21 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1272416 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.6 MiB 48.17 156959 264252 69818 174977 19457 1223.8 MiB 19.40 0.22 6.30018 -21278.5 -5.30018 5.08848 0.02 0.0625285 0.0502951 5.37481 4.40679 214370 17.8300 51439 4.27838 52424 159985 69493207 10252744 0 0 3.29272e+07 21437.0 19 447460 5950766 -1 6.55525 5.17583 -23692.3 -5.55525 0 0 10.23 -1 -1 1223.8 MiB 22.52 9.11353 7.72653 1223.8 MiB -1 2.91 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 378.16 vpr 1.77 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1853480 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1362.9 MiB 112.93 299223 1985810 694705 1211569 79536 1665.8 MiB 167.05 1.45 220.781 -74322.2 -219.781 220.781 0.07 0.200934 0.169269 24.1803 20.5128 416847 12.7247 100775 3.07625 94693 283672 85089101 14646952 0 0 7.61223e+07 21576.6 21 1038076 13772104 -1 190.574 190.574 -74796.5 -189.574 0 0 22.90 -1 -1 1729.6 MiB 34.84 36.1614 31.133 1665.8 MiB -1 7.44 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 60.08 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1240452 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1062.9 MiB 15.84 61122 230944 38935 173615 18394 1188.2 MiB 11.81 0.18 4.96737 -5434.49 -3.96737 2.8073 0.02 0.0387336 0.0317178 2.57184 2.12328 72725 5.84747 18233 1.46603 25673 34471 10834392 1619170 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.00956 2.55962 -5093.98 -4.00956 0 0 8.03 -1 -1 1188.2 MiB 4.50 4.29731 3.66237 1188.2 MiB -1 2.18 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 297.39 vpr 2.16 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2263120 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.4 MiB 73.81 204576 1445886 511132 869441 65313 2210.1 MiB 89.30 0.98 8.29539 -39922.7 -7.29539 8.29539 0.17 0.107171 0.0943286 12.3686 10.4512 291171 14.2731 67635 3.31544 59148 140903 91946515 22482953 0 0 1.96207e+08 21685.1 19 2627776 35613460 -1 7.77837 7.50651 -37244.2 -6.77837 0 0 58.79 -1 -1 2210.1 MiB 28.79 18.2832 15.7996 2210.1 MiB -1 21.60 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 209.37 vpr 2.38 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2494924 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.9 MiB 49.01 125640 1144742 417642 695010 32090 2436.4 MiB 27.60 0.29 12.1377 -20404.2 -11.1377 5.98066 0.18 0.0583692 0.0490098 6.35528 5.34844 169403 19.8527 34281 4.01746 23768 95388 22780638 3618006 0 0 2.47896e+08 21669.2 14 3325632 44947178 -1 12.3671 6.09382 -23278.4 -11.3671 0 0 74.30 -1 -1 2436.4 MiB 9.07 9.00673 7.74787 2436.4 MiB -1 27.37 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 116.44 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1231712 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.8 MiB 66.58 77598 237654 57043 175228 5383 1183.4 MiB 12.28 0.19 7.75636 -48829.2 -6.75636 7.75636 0.02 0.0387637 0.0330252 3.16043 2.55192 107783 17.1520 26590 4.23138 18971 91032 29347868 3748700 0 0 2.50861e+07 21331.7 15 342304 4525318 -1 7.25059 7.25059 -44231.5 -6.25059 0 0 7.74 -1 -1 1183.4 MiB 10.12 5.32204 4.46908 1183.4 MiB -1 2.14 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 23.94 vpr 993.17 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1017004 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.6 MiB 6.88 10123 9091 942 7112 1037 993.2 MiB 0.58 0.01 5.30858 -4060.6 -4.30858 4.62312 0.00 0.00627854 0.00548745 0.259054 0.223136 13428 9.29273 3606 2.49550 3290 8079 3159547 482733 0 0 5.17151e+06 19890.4 10 69776 908778 -1 5.28356 4.46405 -3916.13 -4.28356 0 0 1.74 -1 -1 993.2 MiB 1.11 0.547712 0.492658 993.2 MiB -1 0.20 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 165.23 vpr 1.63 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1709648 22 252 53001 29054 7 22943 1413 54 40 4320 DSP auto 1236.1 MiB 40.53 578922 181131 841569 239646 513371 88552 1669.6 MiB 53.63 0.52 11.8556 7.81898 -42319.1 -6.81898 3.29835 0.03 0.135616 0.124385 16.0465 13.8938 277230 12.1003 64381 2.81005 62818 132705 116667443 33165919 0 0 9.32900e+07 21594.9 18 1265168 16897716 -1 7.55982 3.09933 -38446.9 -6.55982 0 0 17.20 -1 -1 1669.6 MiB 26.52 22.7893 20.0135 1669.6 MiB -1 6.41 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 194.29 vpr 1.51 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1578392 3 33 48977 39238 1 26189 1635 40 30 2400 LAB auto 1260.5 MiB 55.04 757873 274435 916295 263230 624392 28673 1444.8 MiB 77.31 0.86 103.199 88.716 -80010.6 -87.716 88.716 0.02 0.137583 0.112092 13.1911 10.6825 374986 14.3206 89842 3.43105 87924 246005 97241593 17317420 0 0 5.14202e+07 21425.1 24 702232 9282330 -1 70.9171 70.9171 -98532.9 -69.9171 0 0 9.76 -1 -1 1487.4 MiB 27.11 20.5289 17.0272 1444.8 MiB -1 3.90 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 377.31 vpr 1.95 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2045912 38 173 62892 59064 3 35490 2705 60 44 5280 M9K auto 1469.8 MiB 114.90 1 523120 1867766 631559 1187077 49130 1908.1 MiB 152.42 1.10 23.156 13.2224 -362193 -12.2224 8.03046 0.05 0.195577 0.167935 25.6333 19.9211 754105 21.2532 173913 4.90144 133627 487188 180124176 29221336 0 0 1.14226e+08 21633.7 18 1553068 20716258 -1 12.6128 7.39073 -357104 -11.6128 0 0 20.95 -1 -1 1908.1 MiB 48.70 36.7578 29.411 1908.1 MiB -1 9.39 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 417.05 vpr 1.91 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2006360 4 570 66175 54803 2 39253 3378 51 38 3876 LAB auto 1498.7 MiB 101.02 1 535331 2587548 913566 1578253 95729 1776.7 MiB 183.46 1.34 45.2277 30.3105 -116990 -29.3105 6.52897 0.04 0.195666 0.174112 25.6084 20.3089 792100 20.1819 180091 4.58854 202831 840406 332686158 55982239 0 0 8.35478e+07 21555.2 23 1135740 15114436 -1 29.4773 6.2883 -117164 -28.4773 0 0 15.61 -1 -1 1855.5 MiB 80.57 38.7669 31.6392 1776.7 MiB -1 5.93 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 443.03 vpr 4.50 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4723060 19 21 171111 96274 1 69189 3920 129 96 24768 DSP auto 2000.8 MiB 71.06 2 636893 3680425 1441522 2221827 17076 4612.4 MiB 140.90 1.75 6.62096 5.38274 -122739 -4.38274 3.41533 0.15 0.428725 0.373986 45.4388 39.5342 777057 11.2314 170068 2.45813 137555 171570 117628280 30536280 0 0 5.40274e+08 21813.4 12 7186500 97663758 -1 5.58128 3.52408 -142033 -4.58128 0 0 98.71 -1 -1 4612.4 MiB 33.17 59.5818 52.6569 4612.4 MiB -1 53.06 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 274.78 vpr 1.63 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1713652 227 309 49176 40422 1 28286 2492 47 35 3290 io auto 1318.4 MiB 72.05 1 275433 1843284 648037 1152717 42530 1590.5 MiB 139.26 1.07 289.572 222.374 -130782 -221.374 222.374 0.02 0.149074 0.117901 20.4499 16.2564 372383 13.1668 90057 3.18425 84611 265316 75779256 12463701 0 0 7.07061e+07 21491.2 21 956596 12773992 -1 190.263 190.263 -132409 -189.263 0 0 12.88 -1 -1 1605.6 MiB 23.30 28.2031 22.9215 1590.5 MiB -1 4.64 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 203.70 vpr 1.70 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1786780 3 33 52402 39411 1 26915 1592 57 42 4788 M9K auto 1285.8 MiB 61.57 876864 264364 791412 212031 554916 24465 1744.9 MiB 65.16 0.65 24.0259 17.4002 -332154 -16.4002 17.4002 0.05 0.142536 0.112127 13.0905 10.2581 382383 14.2113 89662 3.33229 75758 194667 95589814 17130134 0 0 1.03316e+08 21578.1 21 1396452 18714052 -1 16.7321 16.7321 -316694 -15.7321 0 0 19.24 -1 -1 1744.9 MiB 26.75 20.6792 16.8831 1744.9 MiB -1 8.15 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 88.03 vpr 1.23 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1290232 55 196 20131 19956 1 8019 1227 32 24 1536 LAB auto 1105.6 MiB 35.07 223666 106034 533073 154980 351492 26601 1251.9 MiB 15.87 0.20 10.5638 7.98463 -82831 -6.98463 7.98463 0.01 0.0581793 0.0521859 5.06741 3.88947 155185 19.3594 37908 4.72904 26635 120171 44318653 5861047 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 8.10181 8.10181 -79267.3 -7.10181 0 0 6.32 -1 -1 1251.9 MiB 12.19 7.83315 6.28675 1251.9 MiB -1 2.07 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 181.25 vpr 1.53 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1603172 84 171 36458 36247 3 20790 2367 44 33 2904 LAB auto 1268.1 MiB 81.14 599300 255080 1437255 479979 885421 71855 1501.7 MiB 46.87 0.45 17.1545 12.4465 -91330.5 -11.4465 4.45992 0.02 0.120982 0.0894776 12.0224 9.07078 364406 17.5398 83448 4.01656 55999 185251 56555792 7754659 0 0 6.23802e+07 21480.8 16 847384 11269474 -1 12.7357 4.18797 -90999.3 -11.7357 0 0 11.56 -1 -1 1501.7 MiB 16.62 17.272 13.5403 1501.7 MiB -1 4.42 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 249.79 vpr 2.31 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2419068 36 33 57796 49182 1 19635 2569 79 59 9322 M144K auto 1407.1 MiB 63.37 687588 226099 2218531 834530 1355192 28809 2362.4 MiB 68.81 0.68 18.0423 9.78823 -106228 -8.78823 9.78823 0.06 0.156822 0.12818 17.4559 14.0039 383131 19.5176 88177 4.49195 55287 189555 142027050 36001459 0 0 2.01410e+08 21605.9 18 2701980 36491882 -1 8.62869 8.62869 -135986 -7.62869 0 0 36.79 -1 -1 2362.4 MiB 36.89 23.9234 19.6875 2362.4 MiB -1 17.24 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 183.23 vpr 2.03 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2129380 202 276 35125 30509 3 21318 2020 73 54 7884 M9K auto 1220.8 MiB 49.25 782109 226940 1316712 439612 818763 58337 2079.5 MiB 41.20 0.36 10.3029 9.12883 -43356.7 -8.12883 3.36482 0.05 0.110797 0.0823899 12.5992 9.50036 371195 17.4172 82710 3.88091 55579 159944 111563169 23433137 0 0 1.70845e+08 21669.8 15 2296616 31015204 -1 9.1859 3.56835 -47482.5 -8.1859 0 0 30.53 -1 -1 2079.5 MiB 25.86 17.6423 13.833 2079.5 MiB -1 13.21 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 70.27 vpr 1.42 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1485336 3 2 14862 10304 26 7561 466 49 36 3528 DSP auto 1055.8 MiB 19.02 184798 85297 135916 31512 94725 9679 1450.5 MiB 7.99 0.10 7.29278 5.55968 -34908.3 -4.55968 4.09325 0.02 0.0617226 0.0506659 4.97988 4.16457 139805 18.5541 31297 4.15355 18124 38759 27933959 6509280 0 0 7.61223e+07 21576.6 14 1038076 13772104 -1 5.63749 3.99239 -40563.9 -4.63749 0 0 14.25 -1 -1 1450.5 MiB 7.47 7.35481 6.30369 1450.5 MiB -1 5.97 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 241.81 vpr 1.75 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1838024 35 658 51416 37539 1 27424 2511 58 43 4988 io auto 1316.4 MiB 51.04 948323 229942 1896171 635436 1127325 133410 1794.9 MiB 106.03 0.65 67.4142 43.6805 -67218.9 -42.6805 43.6805 0.05 0.147176 0.118236 22.3082 17.9517 337800 13.0359 80019 3.08799 92021 297464 123311075 28490887 0 0 1.07584e+08 21568.7 23 1452444 19486512 -1 38.5807 38.5807 -63507.4 -37.5807 0 0 19.82 -1 -1 1794.9 MiB 33.41 30.8252 25.4394 1794.9 MiB -1 8.55 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 124.50 vpr 1.76 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1844452 13 740 25173 25306 1 12838 1890 63 47 5922 io auto 1153.9 MiB 36.81 511809 123464 1123170 386810 683070 53290 1801.2 MiB 25.01 0.25 14.0109 8.89156 -32729.6 -7.89156 8.89156 0.04 0.0798946 0.060212 7.54908 5.83542 174594 13.6072 41482 3.23295 30417 111693 28104765 5049543 0 0 1.28005e+08 21615.1 12 1733724 23216534 -1 9.312 7.90522 -32948 -8.312 0 0 24.14 -1 -1 1801.2 MiB 8.53 10.4774 8.39933 1801.2 MiB -1 10.73 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 253.88 vpr 1.71 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1795052 79 38 66795 54922 1 35224 2428 47 35 3290 LAB auto 1380.7 MiB 94.09 1 250576 1568380 463687 1064695 39998 1616.6 MiB 99.48 0.83 19.7664 10.4808 -184122 -9.48083 10.4808 0.02 0.157661 0.119423 16.476 12.6508 340352 9.66333 81776 2.32180 86206 207566 53826209 8209764 0 0 7.07061e+07 21491.2 16 956596 12773992 -1 10.0058 10.0058 -194535 -9.00582 0 0 13.02 -1 -1 1666.0 MiB 17.88 23.576 18.6595 1616.6 MiB -1 5.01 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 152.90 vpr 1.65 GiB 213 1559 26 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1730980 139 74 57121 41054 1 23901 1802 49 36 3528 DSP auto 1330.5 MiB 46.92 523367 148917 1108863 331082 721190 56591 1626.9 MiB 48.59 0.49 7.59102 5.69228 -22418.3 -4.69228 5.69228 0.03 0.128597 0.102115 13.8422 11.2402 213091 8.91706 51264 2.14521 51274 92514 47975319 11532374 0 0 7.61223e+07 21576.6 18 1038076 13772104 -1 6.06924 6.06924 -28283.6 -5.06924 0 0 14.31 -1 -1 1629.7 MiB 14.95 20.3691 17.088 1626.9 MiB -1 5.62 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 78.09 vpr 1.21 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1270700 2 52 16673 16662 2 11970 759 32 24 1536 M9K auto 1087.8 MiB 25.88 316622 151272 249879 62506 169778 17595 1222.8 MiB 12.56 0.16 8.23152 6.10201 -21277.5 -5.10201 5.06369 0.01 0.0608657 0.0448446 4.65112 3.49451 206638 17.2688 49600 4.14508 49955 156078 65896959 9506054 0 0 3.29272e+07 21437.0 17 447460 5950766 -1 5.95759 5.05709 -22801.2 -4.95759 0 0 6.24 -1 -1 1222.8 MiB 16.01 7.6001 6.00867 1222.8 MiB -1 1.96 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 278.89 vpr 1.77 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1856896 131 314 57881 45152 1 32883 2670 49 36 3528 DSP auto 1414.2 MiB 62.82 1 299910 2002290 699814 1233269 69207 1675.6 MiB 138.83 1.39 284.301 222.426 -75627 -221.426 222.426 0.03 0.236157 0.194737 23.5659 19.1088 418537 12.7579 101272 3.08700 110009 337269 96294911 17389823 0 0 7.61223e+07 21576.6 20 1038076 13772104 -1 194.866 194.866 -77192.9 -193.866 0 0 14.01 -1 -1 1735.4 MiB 30.32 33.6401 27.7968 1675.6 MiB -1 5.73 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 39.68 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1240084 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1077.4 MiB 8.17 181772 63669 220151 34297 170189 15665 1190.5 MiB 7.36 0.10 5.43671 4.9834 -5379.72 -3.9834 2.7577 0.01 0.029861 0.0231527 2.09146 1.68198 74208 5.86903 18737 1.48189 26177 36020 11211877 1692426 0 0 2.60031e+07 21349.0 16 354380 4692432 -1 5.06256 2.57234 -4972.33 -4.06256 0 0 4.88 -1 -1 1190.5 MiB 3.58 3.54136 2.96155 1190.5 MiB -1 1.45 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 204.51 vpr 2.16 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2260468 542 422 37277 26038 1 20404 2145 78 58 9048 io auto 1178.0 MiB 40.79 750296 228064 1467913 515344 879432 73137 2207.5 MiB 68.52 0.66 12.737 8.18785 -41350.9 -7.18785 8.18785 0.06 0.0966519 0.0771184 11.0478 8.92438 322744 15.8200 73105 3.58340 59794 137322 91182231 22125715 0 0 1.96207e+08 21685.1 20 2627776 35613460 -1 7.30285 7.27939 -40357.2 -6.30285 0 0 35.70 -1 -1 2207.5 MiB 22.97 16.1253 13.4219 2207.5 MiB -1 15.77 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 134.50 vpr 2.38 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2492860 403 704 15490 16194 1 8443 1837 88 65 11440 io auto 1075.7 MiB 26.81 420969 123874 1171421 444803 693731 32887 2434.4 MiB 18.14 0.17 15.5138 11.646 -20021 -10.646 5.46969 0.09 0.0503342 0.0392748 5.60953 4.44327 169038 20.0235 34647 4.10412 24224 99582 23849257 3883264 0 0 2.47896e+08 21669.2 17 3325632 44947178 -1 11.6834 5.38195 -22298.1 -10.6834 0 0 44.54 -1 -1 2434.4 MiB 7.35 7.87318 6.44077 2434.4 MiB -1 19.44 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 69.67 vpr 1.17 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1229912 18 17 16969 16357 1 6487 772 28 21 1176 LAB auto 1072.8 MiB 35.55 163040 72492 241492 59461 177034 4997 1184.0 MiB 7.88 0.12 10.8841 7.97919 -43930.8 -6.97919 7.97919 0.01 0.0361636 0.0267893 2.69 2.03031 103493 15.9638 25861 3.98905 17521 69428 20784533 3065429 0 0 2.50861e+07 21331.7 13 342304 4525318 -1 7.06018 7.06018 -41291.6 -6.06018 0 0 4.79 -1 -1 1184.0 MiB 5.57 4.20349 3.36329 1184.0 MiB -1 1.39 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 19.55 vpr 995.23 MiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1019120 18 17 2291 2142 1 1462 118 13 10 260 LAB auto 956.8 MiB 4.11 13715 10389 9077 1002 7044 1031 995.2 MiB 0.43 0.01 5.45489 5.30858 -4076.26 -4.30858 4.57983 0.00 0.00509865 0.00456934 0.219625 0.189235 13990 9.58876 3763 2.57916 3281 7657 3126738 496499 0 0 5.17151e+06 19890.4 10 69776 908778 -1 5.24165 4.31206 -3750.06 -4.24165 0 0 1.11 -1 -1 995.2 MiB 0.80 0.440544 0.395044 995.2 MiB -1 0.12 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt index 46f57bf760a..8c5e0d1eb21 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 245.62 vpr 1.63 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1710616 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.9 MiB 75.60 184944 854209 237356 546771 70082 1670.5 MiB 72.88 0.69 7.97251 -43075.7 -6.97251 3.30339 0.08 0.146166 0.132698 17.0437 15.0301 301371 13.1305 69191 3.01460 59225 124430 116802792 31972323 0 0 9.32900e+07 21594.9 16 1265168 16897716 -1 8.04852 3.11041 -39249.7 -7.04852 0 0 28.37 -1 -1 1670.5 MiB 33.95 23.995 21.3968 1670.5 MiB -1 9.57 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 270.96 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1570676 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.8 MiB 102.33 228282 920766 279042 595583 46141 1429.0 MiB 88.59 0.94 88.2845 -80659 -87.2845 88.2845 0.04 0.14392 0.1195 14.5711 12.2042 355838 13.6383 86376 3.31057 77310 201105 89811404 15105784 0 0 5.14202e+07 21425.1 24 702232 9282330 -1 70.4773 70.4773 -94845.6 -69.4773 0 0 15.57 -1 -1 1479.9 MiB 33.28 23.5591 20.0191 1429.0 MiB -1 4.91 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 509.62 vpr 1.95 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2047208 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.5 MiB 198.26 451048 1864099 647919 1164574 51606 1901.9 MiB 164.98 1.47 13.1506 -361183 -12.1506 7.9921 0.08 0.247442 0.196485 26.6398 21.6013 732955 20.7266 171188 4.84088 124728 456761 177820618 26065245 0 0 1.14226e+08 21633.7 19 1553068 20716258 -1 12.8769 7.53335 -363190 -11.8769 0 0 34.42 -1 -1 1901.9 MiB 62.40 40.217 33.3925 1901.9 MiB -1 11.90 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 567.58 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2010460 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.8 MiB 182.98 484271 2560191 884458 1582491 93242 1765.5 MiB 199.71 1.77 30.1698 -117772 -29.1698 6.32625 0.06 0.250873 0.209174 27.8047 23.3414 819023 20.8849 185777 4.73728 196681 798495 366587115 55913961 0 0 8.35478e+07 21555.2 22 1135740 15114436 -1 29.383 6.18561 -115406 -28.383 0 0 25.30 -1 -1 1859.5 MiB 114.24 42.8002 36.5375 1765.5 MiB -1 8.24 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 659.64 vpr 4.50 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4722024 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.9 MiB 143.54 633199 3760290 1490720 2235840 33730 4611.4 MiB 182.36 1.64 5.44974 -120174 -4.44974 3.48061 0.38 0.500711 0.446581 64.3668 57.2048 792964 11.4829 169052 2.44804 136130 168139 120657048 30423925 0 0 5.40274e+08 21813.4 11 7186500 97663758 -1 5.66375 3.85682 -156124 -4.66375 0 0 164.59 -1 -1 4611.4 MiB 43.21 81.7626 73.4249 4611.4 MiB -1 67.85 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 346.58 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1706888 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1277.2 MiB 130.96 235454 1785192 630171 1108259 46762 1578.0 MiB 123.59 1.24 223.973 -131867 -222.973 223.973 0.06 0.15399 0.137707 18.3847 15.5681 381869 13.4950 92844 3.28105 78342 247729 91337050 11782368 0 0 7.07061e+07 21491.2 19 956596 12773992 -1 184.913 184.913 -126417 -183.913 0 0 21.19 -1 -1 1599.2 MiB 34.88 27.0233 23.1993 1578.0 MiB -1 6.86 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 293.47 vpr 1.70 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1786932 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.4 MiB 111.19 242706 816556 231855 560850 23851 1745.1 MiB 73.99 0.84 17.4268 -331657 -16.4268 17.4268 0.09 0.152091 0.122991 14.1776 11.6814 398717 14.7930 92932 3.44793 77467 205644 117024334 20394306 0 0 1.03316e+08 21578.1 21 1396452 18714052 -1 16.917 16.917 -320368 -15.917 0 0 31.30 -1 -1 1745.1 MiB 38.71 22.7388 19.2113 1745.1 MiB -1 9.99 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 125.97 vpr 1.23 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1288384 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 59.12 92593 557464 169405 360888 27171 1229.7 MiB 20.18 0.28 7.84939 -78165.6 -6.8494 7.84939 0.02 0.0579092 0.0459609 5.05811 4.04769 159733 19.3148 38820 4.69408 24505 101419 42311105 5071555 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 7.81851 7.81851 -71908.7 -6.81851 0 0 10.15 -1 -1 1229.7 MiB 14.27 7.7811 6.44817 1229.7 MiB -1 2.82 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 281.85 vpr 1.53 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1606428 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.5 MiB 149.46 215765 1517216 518543 921536 77137 1503.3 MiB 58.02 0.60 11.9872 -86085.7 -10.9872 4.67996 0.04 0.124604 0.100056 12.4857 10.1291 368614 18.1467 84927 4.18092 54529 192216 59535264 7516911 0 0 6.38257e+07 21490.1 16 866116 11532596 -1 12.0375 4.6146 -82845.8 -11.0375 0 0 19.13 -1 -1 1503.3 MiB 22.39 18.634 15.5175 1503.3 MiB -1 6.30 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 351.01 vpr 2.30 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2416864 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.1 MiB 113.80 191652 2198126 837039 1305954 55133 2360.2 MiB 85.43 0.84 9.95158 -103978 -8.95158 9.95158 0.14 0.157427 0.126297 20.3063 16.4066 380882 19.2822 88412 4.47588 48910 148956 112086751 26603030 0 0 2.01410e+08 21605.9 17 2701980 36491882 -1 9.01423 9.01423 -137565 -8.01423 0 0 60.43 -1 -1 2360.2 MiB 36.97 28.4438 23.7031 2360.2 MiB -1 21.63 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 283.30 vpr 2.03 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2130904 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.7 MiB 91.45 212379 1465966 513016 878305 74645 2081.0 MiB 57.22 0.51 9.02677 -43039.7 -8.02677 3.39009 0.15 0.130982 0.112127 16.0361 12.8184 388469 18.3128 85167 4.01485 54060 155006 126101728 25409947 0 0 1.70845e+08 21669.8 17 2296616 31015204 -1 9.33987 3.47782 -46390.5 -8.33987 0 0 50.94 -1 -1 2081.0 MiB 38.16 22.6708 18.6622 2081.0 MiB -1 18.21 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 116.04 vpr 1.42 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1487240 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 44.85 91640 143465 34428 97411 11626 1452.4 MiB 9.56 0.11 5.55968 -32627.3 -4.55968 4.03585 0.05 0.0580242 0.0511336 5.23009 4.40266 162858 21.5506 34640 4.58383 20772 47469 39442838 8696473 0 0 7.61223e+07 21576.6 17 1038076 13772104 -1 5.83812 3.81128 -37803.8 -4.83812 0 0 22.95 -1 -1 1452.4 MiB 12.55 8.31954 7.18554 1452.4 MiB -1 7.74 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 307.88 vpr 1.76 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1842824 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1280.9 MiB 92.83 193340 1985246 651294 1194899 139053 1799.6 MiB 104.91 0.90 42.817 -66341.8 -41.817 42.817 0.08 0.174464 0.149553 21.4513 18.52 318648 12.2949 76857 2.96551 72321 215661 101797360 20420450 0 0 1.07584e+08 21568.7 26 1452444 19486512 -1 38.0834 38.0834 -61419.7 -37.0834 0 0 32.89 -1 -1 1799.6 MiB 36.69 32.4273 28.3397 1799.6 MiB -1 11.41 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 191.13 vpr 1.76 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1848728 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1133.0 MiB 66.11 114187 1121763 389127 687964 44672 1805.4 MiB 36.03 0.35 9.10047 -33210.9 -8.10047 9.10047 0.10 0.0829476 0.0672165 8.6028 7.09879 180406 14.1951 42811 3.36856 29439 106878 36794843 4980523 0 0 1.28005e+08 21615.1 13 1733724 23216534 -1 8.86459 8.53756 -33502.4 -7.86459 0 0 39.09 -1 -1 1805.4 MiB 13.39 12.4192 10.5234 1805.4 MiB -1 13.65 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 365.42 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1789484 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.0 MiB 148.46 220034 1575085 472174 1056131 46780 1607.4 MiB 128.88 1.19 10.366 -185682 -9.366 10.366 0.05 0.166017 0.132704 17.7166 14.3298 340742 9.54593 82334 2.30660 86785 211666 72987830 8810844 0 0 7.07061e+07 21491.2 18 956596 12773992 -1 10.3348 10.3348 -186105 -9.33478 0 0 21.58 -1 -1 1659.8 MiB 29.02 26.9646 22.2301 1607.4 MiB -1 7.36 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 236.24 vpr 1.65 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1729420 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1290.4 MiB 89.13 143448 1223918 387573 791889 44456 1618.2 MiB 69.23 0.62 6.15923 -22935.6 -5.15923 6.15923 0.06 0.160924 0.134554 18.8103 16.0328 226941 9.45706 54238 2.26020 51698 93187 54990565 12041480 0 0 7.61223e+07 21576.6 16 1038076 13772104 -1 6.33927 6.33927 -28490.3 -5.33927 0 0 23.07 -1 -1 1627.8 MiB 19.85 26.0631 22.6082 1618.2 MiB -1 7.69 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 121.12 vpr 1.21 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1272616 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.8 MiB 48.71 145866 267719 70212 178005 19502 1223.6 MiB 17.33 0.21 6.32104 -21443.6 -5.32104 5.1317 0.02 0.0642369 0.0519236 5.54676 4.5538 218475 18.1714 52270 4.34750 52154 158487 72130661 9975959 0 0 3.29272e+07 21437.0 17 447460 5950766 -1 6.2459 4.96992 -24617.9 -5.2459 0 0 10.12 -1 -1 1223.6 MiB 22.65 9.07986 7.70719 1223.6 MiB -1 2.99 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 360.73 vpr 1.77 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1854860 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1363.2 MiB 112.86 262777 1930208 669923 1189043 71242 1666.5 MiB 145.10 1.38 223.441 -74881.2 -222.441 223.441 0.05 0.211297 0.180427 24.3293 20.7548 427696 13.0558 103553 3.16106 90894 273726 106018598 14702817 0 0 7.61223e+07 21576.6 21 1038076 13772104 -1 190.035 190.035 -73399.2 -189.035 0 0 23.08 -1 -1 1732.8 MiB 39.37 36.0725 31.1574 1666.5 MiB -1 7.54 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 60.38 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1239040 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1061.9 MiB 15.77 60924 230944 39979 176254 14711 1186.8 MiB 11.56 0.18 5.04063 -5430.36 -4.04063 2.87222 0.02 0.0364742 0.0318647 2.60212 2.17525 74753 6.01053 18783 1.51025 25814 34889 12202224 1634430 0 0 2.60031e+07 21349.0 17 354380 4692432 -1 5.24483 2.65773 -5067.06 -4.24483 0 0 8.10 -1 -1 1186.8 MiB 4.94 4.43218 3.80588 1186.8 MiB -1 2.32 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 296.54 vpr 2.16 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2262908 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.3 MiB 72.90 213411 1459636 524477 868204 66955 2209.9 MiB 84.09 0.87 8.12716 -41041.3 -7.12716 8.12716 0.14 0.11422 0.095868 12.9019 10.9024 322533 15.8104 73202 3.58833 58164 135585 115660664 26279570 0 0 1.96207e+08 21685.1 19 2627776 35613460 -1 7.60563 7.60563 -38875.6 -6.60563 0 0 58.66 -1 -1 2209.9 MiB 34.96 18.71 16.1454 2209.9 MiB -1 20.83 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 209.98 vpr 2.38 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2494688 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.9 MiB 49.31 117261 1200767 458957 708379 33431 2436.2 MiB 25.42 0.26 11.7854 -20675.2 -10.7854 5.73126 0.18 0.0562212 0.0465333 6.50332 5.46368 182292 21.3632 36297 4.25372 22684 88666 28845037 3461649 0 0 2.47896e+08 21669.2 14 3325632 44947178 -1 11.9953 5.82624 -23038.5 -10.9953 0 0 74.42 -1 -1 2436.2 MiB 10.82 9.12659 7.84634 2436.2 MiB -1 27.36 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 115.88 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1230928 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.5 MiB 66.57 64446 230476 54244 170900 5332 1183.1 MiB 10.85 0.17 7.74825 -47724 -6.74825 7.74825 0.02 0.0458274 0.0351245 3.17308 2.53234 105547 16.7961 26043 4.14433 16938 75501 27527280 3256994 0 0 2.50861e+07 21331.7 14 342304 4525318 -1 7.60467 7.60467 -45348.9 -6.60467 0 0 7.98 -1 -1 1183.1 MiB 9.47 5.27867 4.40168 1183.1 MiB -1 2.23 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 23.87 vpr 993.03 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1016864 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.3 MiB 6.57 8979 9091 989 7145 957 993.0 MiB 0.57 0.01 5.30858 -4141.38 -4.30858 4.67064 0.00 0.00654281 0.00572201 0.265779 0.231578 13865 9.59516 3702 2.56194 3278 7822 3354574 494732 0 0 5.17151e+06 19890.4 12 69776 908778 -1 5.46939 4.48287 -3903.7 -4.46939 0 0 1.75 -1 -1 993.0 MiB 1.23 0.606378 0.546433 993.0 MiB -1 0.21 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 163.02 vpr 1.63 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1710280 22 252 53001 29054 7 22943 1413 54 40 4320 DSP auto 1236.7 MiB 39.44 553143 184563 873273 250110 551395 71768 1670.2 MiB 51.56 0.44 11.8556 7.87174 -43548.4 -6.87174 3.3085 0.04 0.123505 0.111445 15.5558 13.296 304060 13.2714 69338 3.02641 61073 128176 122419449 33174955 0 0 9.32900e+07 21594.9 19 1265168 16897716 -1 7.53553 3.06212 -39277 -6.53553 0 0 17.19 -1 -1 1670.2 MiB 28.45 21.8553 18.9725 1670.2 MiB -1 6.50 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 180.22 vpr 1.51 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1579152 3 33 48977 39238 1 26189 1635 40 30 2400 LAB auto 1260.6 MiB 54.69 675596 228461 906667 263743 600906 42018 1445.6 MiB 65.17 0.61 103.199 89.4627 -80347.1 -88.4627 89.4627 0.02 0.123029 0.0986105 14.199 11.4265 356523 13.6155 87289 3.33355 78260 206743 90689914 14925324 0 0 5.14202e+07 21425.1 22 702232 9282330 -1 70.9785 70.9785 -96386.4 -69.9785 0 0 9.85 -1 -1 1487.0 MiB 25.33 21.059 17.3632 1445.6 MiB -1 3.35 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 340.01 vpr 1.95 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2048992 38 173 62892 59064 3 35490 2705 60 44 5280 M9K auto 1470.4 MiB 113.22 1 466891 1867766 638347 1188962 40457 1908.5 MiB 119.16 1.11 23.156 12.9703 -351376 -11.9703 8.02903 0.05 0.215422 0.185865 24.9657 19.578 756272 21.3142 175267 4.93960 128214 464786 184257221 27767301 0 0 1.14226e+08 21633.7 19 1553068 20716258 -1 12.3378 7.46737 -352387 -11.3378 0 0 20.97 -1 -1 1908.5 MiB 48.79 36.2864 29.2693 1908.5 MiB -1 7.98 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 373.89 vpr 1.91 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2007384 4 570 66175 54803 2 39253 3378 51 38 3876 LAB auto 1499.1 MiB 99.87 1 482306 2562213 886867 1580400 94946 1776.8 MiB 144.28 1.36 45.2277 30.0102 -117157 -29.0102 6.49654 0.03 0.212298 0.19009 25.7913 20.7174 808619 20.6028 183919 4.68607 176656 706881 320986661 49813509 0 0 8.35478e+07 21555.2 21 1135740 15114436 -1 29.0374 6.24338 -115391 -28.0374 0 0 15.81 -1 -1 1856.1 MiB 78.25 38.3522 31.5254 1776.8 MiB -1 5.73 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 429.60 vpr 4.50 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4722240 19 21 171111 96274 1 69189 3920 129 96 24768 DSP auto 2001.1 MiB 73.03 2 602918 3649530 1421026 2196167 32337 4611.6 MiB 132.23 1.27 6.62096 5.16746 -108678 -4.16746 3.16445 0.24 0.404496 0.351859 49.8836 43.962 760441 10.9913 164698 2.38051 138720 171477 121850186 30999203 0 0 5.40274e+08 21813.4 12 7186500 97663758 -1 5.18984 3.41724 -137387 -4.18984 0 0 98.44 -1 -1 4611.6 MiB 32.70 63.1285 56.2041 4611.6 MiB -1 49.27 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 217.11 vpr 1.63 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1714264 227 309 49176 40422 1 28286 2492 47 35 3290 io auto 1318.1 MiB 72.14 949337 230310 1809508 633583 1119861 56064 1590.1 MiB 79.93 0.86 289.572 220.521 -127261 -219.521 220.521 0.02 0.156112 0.125918 17.0682 13.7681 371393 13.1318 90754 3.20890 78062 243708 86098619 10967186 0 0 7.07061e+07 21491.2 19 956596 12773992 -1 183.258 183.258 -122529 -182.258 0 0 13.56 -1 -1 1605.5 MiB 23.90 23.9832 19.7076 1590.1 MiB -1 4.56 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 198.54 vpr 1.70 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1786688 3 33 52402 39411 1 26915 1592 57 42 4788 M9K auto 1285.6 MiB 61.21 807202 237745 809996 223571 562388 24037 1744.8 MiB 56.29 0.57 24.0259 17.5288 -339439 -16.5288 17.5288 0.05 0.140741 0.109909 14.9895 12.1055 395902 14.7137 92407 3.43431 79357 212916 121957158 21173533 0 0 1.03316e+08 21578.1 22 1396452 18714052 -1 17.0616 17.0616 -326321 -16.0616 0 0 19.00 -1 -1 1744.8 MiB 31.88 22.557 18.3795 1744.8 MiB -1 7.95 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 81.67 vpr 1.23 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1291604 55 196 20131 19956 1 8019 1227 32 24 1536 LAB auto 1106.5 MiB 34.94 197415 91389 533073 155258 350786 27029 1252.7 MiB 12.28 0.15 10.5638 7.9694 -84401.8 -6.9694 7.9694 0.01 0.0391724 0.0337257 4.13053 3.13542 156922 19.5761 38124 4.75599 24144 106283 43472187 5062582 0 0 3.29272e+07 21437.0 17 447460 5950766 -1 8.0038 8.0038 -76147.9 -7.0038 0 0 6.09 -1 -1 1252.7 MiB 10.82 6.4594 5.1443 1252.7 MiB -1 1.83 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 174.35 vpr 1.53 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1603028 84 171 36458 36247 3 20790 2367 44 33 2904 LAB auto 1266.2 MiB 81.48 546571 214795 1437255 480391 886927 69937 1498.7 MiB 38.24 0.40 17.1545 12.2615 -90825 -11.2615 4.44627 0.02 0.118854 0.087873 11.8695 8.93815 368296 17.7270 84627 4.07331 55785 195975 64857507 8108532 0 0 6.23802e+07 21480.8 14 847384 11269474 -1 12.4986 4.24047 -87839 -11.4986 0 0 11.58 -1 -1 1498.7 MiB 18.31 16.6314 13.0164 1498.7 MiB -1 4.08 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 233.35 vpr 2.31 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2417992 36 33 57796 49182 1 19635 2569 79 59 9322 M144K auto 1406.8 MiB 62.54 653233 192546 2183357 844340 1310310 28707 2361.3 MiB 58.92 0.56 18.0423 9.76693 -96722.1 -8.76693 9.76693 0.06 0.125515 0.0975704 16.3759 12.9715 379198 19.3173 88012 4.48355 51383 170986 126474373 30291745 0 0 2.01410e+08 21605.9 16 2701980 36491882 -1 8.56238 8.56238 -127393 -7.56238 0 0 36.63 -1 -1 2361.3 MiB 32.09 22.3007 18.2177 2361.3 MiB -1 16.38 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 183.95 vpr 2.03 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2129820 202 276 35125 30509 3 21318 2020 73 54 7884 M9K auto 1221.4 MiB 50.16 716729 207560 1380532 469949 847523 63060 2079.9 MiB 35.53 0.34 10.3029 9.20592 -44245.9 -8.20592 3.37783 0.05 0.134527 0.101332 13.395 10.226 376235 17.6537 83221 3.90489 56995 167645 133187361 25954915 0 0 1.70845e+08 21669.8 16 2296616 31015204 -1 9.30202 3.57682 -47252 -8.30202 0 0 31.53 -1 -1 2079.9 MiB 31.26 18.6275 14.7303 2079.9 MiB -1 13.18 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 67.96 vpr 1.42 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1486328 3 2 14862 10304 26 7561 466 49 36 3528 DSP auto 1055.6 MiB 18.96 169108 90003 135916 31625 92700 11591 1451.5 MiB 6.45 0.08 7.29278 5.55968 -33241.7 -4.55968 3.91952 0.02 0.0505029 0.0412837 4.05288 3.36705 161880 21.4837 34654 4.59907 19262 41383 32535712 7242694 0 0 7.61223e+07 21576.6 14 1038076 13772104 -1 5.7478 3.7418 -36662.8 -4.7478 0 0 13.92 -1 -1 1451.5 MiB 7.99 6.02567 5.12234 1451.5 MiB -1 5.58 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 204.01 vpr 1.75 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1838636 35 658 51416 37539 1 27424 2511 58 43 4988 io auto 1316.9 MiB 49.69 873485 208058 1947351 617969 1190949 138433 1795.5 MiB 71.44 0.68 67.4142 43.3331 -66203.9 -42.3331 43.3331 0.05 0.15867 0.129165 19.3481 15.9045 342451 13.2154 80916 3.12260 78710 239308 118664359 23155496 0 0 1.07584e+08 21568.7 28 1452444 19486512 -1 38.8692 38.8692 -61793.9 -37.8692 0 0 19.67 -1 -1 1795.5 MiB 32.19 28.9085 24.1772 1795.5 MiB -1 8.02 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 119.98 vpr 1.76 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1845228 13 740 25173 25306 1 12838 1890 63 47 5922 io auto 1153.9 MiB 36.41 470725 111381 1111490 384644 673635 53211 1802.0 MiB 22.09 0.20 14.0109 8.87029 -33339 -7.87029 8.87029 0.04 0.0714492 0.0529662 7.49782 5.77897 179395 13.9814 42811 3.33653 29405 105946 37157864 4956640 0 0 1.28005e+08 21615.1 12 1733724 23216534 -1 9.27318 8.25275 -33374.7 -8.27318 0 0 23.38 -1 -1 1802.0 MiB 10.17 10.396 8.3228 1802.0 MiB -1 9.19 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 245.62 vpr 1.71 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1796636 79 38 66795 54922 1 35224 2428 47 35 3290 LAB auto 1382.7 MiB 93.98 1 215377 1486820 430516 1012081 44223 1618.4 MiB 86.33 0.85 19.7664 10.4506 -183686 -9.45055 10.4506 0.02 0.156777 0.119319 15.6084 11.9943 339321 9.63405 80812 2.29443 96886 244258 86910997 10095189 0 0 7.07061e+07 21491.2 16 956596 12773992 -1 9.53723 9.53723 -187005 -8.53723 0 0 12.88 -1 -1 1667.2 MiB 23.92 22.6479 18.0205 1618.4 MiB -1 5.24 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 151.40 vpr 1.65 GiB 213 1559 26 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1731440 139 74 57121 41054 1 23901 1802 49 36 3528 DSP auto 1329.9 MiB 46.56 503320 137704 1108863 333769 717933 57161 1626.9 MiB 43.96 0.51 7.59102 5.46013 -22573.5 -4.46013 5.46013 0.03 0.180195 0.165554 16.5709 13.7008 220251 9.21668 53111 2.22250 52406 96881 61898013 13579685 0 0 7.61223e+07 21576.6 19 1038076 13772104 -1 5.99682 5.99682 -24267.2 -4.99682 0 0 14.28 -1 -1 1630.1 MiB 17.88 23.1986 19.4889 1626.9 MiB -1 5.57 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 75.64 vpr 1.21 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1271256 2 52 16673 16662 2 11970 759 32 24 1536 M9K auto 1088.2 MiB 25.74 287692 137368 242959 60191 164382 18386 1223.0 MiB 10.25 0.13 8.23152 6.34257 -21161.6 -5.34257 5.09376 0.01 0.0560926 0.0414855 4.32633 3.28263 205192 17.1479 49371 4.12594 47973 149300 66746671 9307991 0 0 3.29272e+07 21437.0 18 447460 5950766 -1 6.25468 5.09564 -22684.1 -5.25468 0 0 6.19 -1 -1 1223.0 MiB 15.98 7.17592 5.75226 1223.0 MiB -1 1.87 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 230.76 vpr 1.77 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1856468 131 314 57881 45152 1 32883 2670 49 36 3528 DSP auto 1412.8 MiB 63.31 1 257536 1909715 654346 1173189 82180 1674.1 MiB 92.41 1.05 284.301 220.986 -75834.1 -219.986 220.986 0.02 0.196207 0.158753 21.9219 17.9789 420532 12.8188 102359 3.12013 89184 263712 101905909 14381353 0 0 7.61223e+07 21576.6 20 1038076 13772104 -1 184.902 184.902 -76513.8 -183.902 0 0 13.99 -1 -1 1734.2 MiB 28.86 31.23 26.0791 1674.1 MiB -1 5.28 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 39.93 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1239412 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1076.4 MiB 8.18 177076 60430 220151 37040 166912 16199 1189.7 MiB 7.30 0.11 5.43671 4.98186 -5389.45 -3.98186 2.74369 0.01 0.0330879 0.0259898 2.22718 1.78099 73991 5.85187 18405 1.45563 25780 35867 12871709 1745504 0 0 2.60031e+07 21349.0 14 354380 4692432 -1 5.1649 2.66536 -5084.57 -4.1649 0 0 4.88 -1 -1 1189.7 MiB 3.94 3.62393 3.00964 1189.7 MiB -1 1.45 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 183.79 vpr 2.15 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2259360 542 422 37277 26038 1 20404 2145 78 58 9048 io auto 1178.3 MiB 40.93 718781 204992 1467913 504698 890114 73101 2206.4 MiB 50.27 0.49 12.737 8.21006 -40868.3 -7.21006 8.21006 0.06 0.0958342 0.0782222 10.5753 8.68058 311797 15.2834 70688 3.46493 55201 125849 88584799 20461803 0 0 1.96207e+08 21685.1 17 2627776 35613460 -1 7.63571 7.3669 -38752.7 -6.63571 0 0 36.77 -1 -1 2206.4 MiB 20.74 14.778 12.4345 2206.4 MiB -1 15.04 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 144.61 vpr 2.38 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2493348 403 704 15490 16194 1 8443 1837 88 65 11440 io auto 1076.0 MiB 26.78 391708 113907 1227651 472143 719270 36238 2434.9 MiB 19.47 0.16 15.5138 11.322 -19964.1 -10.322 5.3194 0.08 0.0431255 0.0386447 6.67046 5.26228 181646 21.5169 36609 4.33653 23247 92055 29218683 3595560 0 0 2.47896e+08 21669.2 15 3325632 44947178 -1 11.1981 5.14875 -21508.2 -10.1981 0 0 45.58 -1 -1 2434.9 MiB 8.58 8.83493 7.15206 2434.9 MiB -1 24.64 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 70.10 vpr 1.17 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1229776 18 17 16969 16357 1 6487 772 28 21 1176 LAB auto 1072.2 MiB 36.08 142961 59688 234412 55116 174656 4640 1183.5 MiB 7.02 0.10 10.8841 7.86052 -43530.3 -6.86052 7.86052 0.01 0.0355175 0.0260839 2.6175 1.99269 97980 15.1134 24516 3.78158 16004 64606 24187188 2810280 0 0 2.50861e+07 21331.7 13 342304 4525318 -1 7.19078 7.19078 -42143.8 -6.19078 0 0 4.71 -1 -1 1183.5 MiB 6.19 4.18474 3.37608 1183.5 MiB -1 1.41 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 17.77 vpr 996.36 MiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1020276 18 17 2291 2142 1 1462 118 13 10 260 LAB auto 957.7 MiB 3.86 11981 9290 8499 834 6799 866 996.4 MiB 0.38 0.01 5.45489 5.30858 -4057.33 -4.30858 4.57404 0.00 0.00478301 0.00426942 0.190791 0.165029 13985 9.58533 3795 2.60110 3319 7859 3369135 512682 0 0 5.17151e+06 19890.4 9 69776 908778 -1 5.24356 4.64087 -3951.05 -4.24356 0 0 1.07 -1 -1 996.4 MiB 0.83 0.393205 0.353496 996.4 MiB -1 0.12 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt index 1a9fa971299..baf8b675296 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 1172.59 vpr 1.65 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1734316 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.6 MiB 73.64 214653 894059 251005 559264 83790 1693.7 MiB 79.53 0.65 7.70472 -37826.5 -6.70472 3.17657 0.08 0.149615 0.135881 18.4856 16.2276 346942 15.1160 80330 3.49991 71500 157095 1535090931 789230213 0 0 8.89497e+07 20590.2 18 1365594 16211305 -1 7.67229 3.07739 -42724.4 -6.67229 0 0 29.57 -1 -1 1693.7 MiB 940.94 26.0477 23.0694 1693.7 MiB -1 23.96 -3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 329.77 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1576816 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.5 MiB 99.18 252169 969141 295922 624406 48813 1444.1 MiB 90.56 0.89 82.4495 -56586.4 -81.4495 82.4495 0.03 0.133831 0.117153 15.353 12.8639 420916 16.1326 105895 4.05868 118615 321172 291100673 58952034 0 0 4.91306e+07 20471.1 26 758110 8921656 -1 72.0146 72.0146 -132785 -71.0146 0 0 16.42 -1 -1 1484.9 MiB 85.29 24.7756 21.0909 1444.1 MiB -1 12.23 -3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 641.04 vpr 1.96 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2050760 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.2 MiB 203.13 510171 1939307 680820 1206280 52207 1927.9 MiB 173.07 1.61 11.2616 -300285 -10.2616 7.35058 0.09 0.251364 0.202792 27.6684 22.4451 799864 22.6187 198121 5.60249 142256 518619 474643655 110260894 0 0 1.08858e+08 20617.0 17 1675578 19868374 -1 14.7898 8.01616 -421363 -13.7898 0 0 36.05 -1 -1 1927.9 MiB 161.55 40.1269 33.3458 1927.9 MiB -1 29.72 -3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 991.70 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2018452 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.4 MiB 179.88 509692 2712081 968624 1648149 95308 1790.4 MiB 217.33 1.88 26.7071 -106583 -25.7071 4.92953 0.06 0.265658 0.222085 30.753 25.8577 822920 20.9843 201896 5.14831 185617 735052 1296414490 366645497 0 0 7.97022e+07 20563.0 20 1225854 14507865 -1 30.288 6.57341 -120054 -29.288 0 0 26.21 -1 -1 1867.6 MiB 509.93 45.4244 38.8563 1790.4 MiB -1 20.62 -3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 1067.25 vpr 4.62 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4842056 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.7 MiB 144.01 645363 3760290 1509060 2226895 24335 4728.6 MiB 196.62 2.32 6.72849 -100513 -5.72849 2.73028 0.43 0.510597 0.454713 66.2712 58.6699 801246 11.6028 176582 2.55708 136809 169565 554939068 253332108 0 0 5.14406e+08 20769.0 10 7758968 93673935 -1 6.25252 4.02616 -144264 -5.25252 0 0 173.36 -1 -1 4728.6 MiB 346.30 83.0597 74.3223 4728.6 MiB -1 149.18 -3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 397.31 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1713464 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.8 MiB 127.62 267729 1921016 704204 1175385 41427 1599.4 MiB 134.02 1.32 194.73 -111174 -193.73 194.73 0.05 0.16753 0.141447 20.6062 17.3755 409980 14.4885 103027 3.64092 98368 318292 234678586 45271456 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 196.841 196.841 -137573 -195.841 0 0 22.11 -1 -1 1604.7 MiB 66.77 29.7244 25.3562 1599.4 MiB -1 17.48 -3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 413.22 vpr 1.73 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1814172 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.2 MiB 110.44 272716 825817 229328 570617 25872 1771.7 MiB 82.01 0.93 15.8733 -287969 -14.8733 15.8733 0.07 0.156169 0.134842 15.1402 12.4708 427395 15.8570 107058 3.97203 83662 216621 348016314 94876303 0 0 9.85096e+07 20574.3 20 1507654 17957159 -1 18.2989 18.2989 -351435 -17.2989 0 0 32.91 -1 -1 1771.7 MiB 133.99 23.8154 20.073 1771.7 MiB -1 25.41 -3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 136.48 vpr 1.24 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1295860 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 59.84 106751 583640 180621 371614 31405 1246.6 MiB 21.31 0.25 7.0989 -65567.9 -6.0989 7.0989 0.02 0.0579001 0.0443717 5.41731 4.32489 176951 21.3967 45151 5.45961 29990 122737 58119884 11106318 0 0 3.14199e+07 20455.7 16 483264 5705245 -1 8.58513 8.58513 -82449.9 -7.58513 0 0 10.90 -1 -1 1246.6 MiB 18.17 8.28886 6.85025 1246.6 MiB -1 6.97 -3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 490.96 vpr 1.54 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1612568 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.2 MiB 149.78 250819 1565561 553633 923794 88134 1522.9 MiB 59.74 0.57 10.3141 -74446.1 -9.31412 4.16669 0.05 0.122453 0.0982616 12.7928 10.36 417504 20.5535 99339 4.89042 64295 236643 559755019 162046743 0 0 6.09438e+07 20519.8 16 935204 11078823 -1 14.1009 4.7173 -100461 -13.1009 0 0 19.72 -1 -1 1522.9 MiB 220.56 19.1309 15.8639 1522.9 MiB -1 14.15 -3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 456.82 vpr 2.35 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2459944 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.5 MiB 116.70 208658 2198126 841464 1306315 50347 2402.3 MiB 88.77 0.83 9.15792 -77023.4 -8.15792 9.15792 0.15 0.152102 0.123811 20.4428 16.5197 386740 19.5788 94929 4.80580 57777 193960 262282869 78128583 0 0 1.92002e+08 20596.6 16 2917968 35039980 -1 9.09509 9.09509 -148250 -8.09509 0 0 62.97 -1 -1 2402.3 MiB 105.94 28.2563 23.5085 2402.3 MiB -1 49.55 -3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 391.83 vpr 2.07 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2167360 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.5 MiB 91.51 224050 1542346 541947 927260 73139 2116.6 MiB 59.94 0.50 9.32745 -27918.9 -8.32745 3.0761 0.12 0.131152 0.102135 16.6741 13.2554 393714 18.5600 91424 4.30981 54848 152461 310286597 88766009 0 0 1.62738e+08 20641.5 15 2479452 29744051 -1 9.42064 3.77724 -50913.7 -8.42064 0 0 53.44 -1 -1 2116.6 MiB 114.73 22.9686 18.8221 2116.6 MiB -1 44.42 -3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 148.74 vpr 1.44 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1511644 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1036.2 MiB 45.72 83064 154607 38752 101305 14550 1476.2 MiB 10.09 0.11 5.67702 -19756.2 -4.67702 3.74463 0.05 0.0597777 0.0527936 5.58527 4.74534 152254 20.1474 35176 4.65476 19877 43738 72454580 21374549 0 0 7.26079e+07 20580.5 14 1120110 13214470 -1 5.84516 4.10311 -39834.2 -4.84516 0 0 24.01 -1 -1 1476.2 MiB 28.04 8.35092 7.24512 1476.2 MiB -1 22.29 -3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 346.43 vpr 1.78 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1868112 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1276.9 MiB 93.13 219255 2157656 730879 1273796 152981 1824.3 MiB 109.67 0.89 40.2879 -60979.5 -39.2879 40.2879 0.08 0.170403 0.154539 23.7513 20.5481 349212 13.4742 85186 3.28688 77275 233364 143562765 36702160 0 0 1.02587e+08 20566.7 21 1568252 18700371 -1 38.5591 38.5591 -67167.5 -37.5591 0 0 34.79 -1 -1 1824.3 MiB 50.23 33.5444 29.3581 1824.3 MiB -1 28.83 -3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 218.13 vpr 1.79 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1877276 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1133.0 MiB 66.22 123520 1204279 427315 726664 50300 1833.3 MiB 39.61 0.36 9.02181 -27438.3 -8.02181 9.02181 0.09 0.0790484 0.0694683 9.30633 7.78111 180566 14.2077 43756 3.44291 31272 116811 38575938 8660251 0 0 1.22008e+08 20602.6 13 1871156 22275272 -1 10.1297 8.7558 -37422.6 -9.12975 0 0 40.27 -1 -1 1833.3 MiB 15.13 13.1986 11.2705 1833.3 MiB -1 33.84 -3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 395.83 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1795672 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.1 MiB 147.79 247450 1624747 516348 1068765 39634 1627.6 MiB 129.80 1.19 9.58554 -169343 -8.58554 9.58554 0.05 0.181629 0.143035 18.586 15.0291 368099 10.3123 95475 2.67474 86257 200403 122474916 27418708 0 0 6.75216e+07 20523.3 17 1033138 12274942 -1 10.0787 10.0787 -216795 -9.07872 0 0 22.36 -1 -1 1667.7 MiB 46.86 27.3022 22.6133 1627.6 MiB -1 18.57 -3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 251.39 vpr 1.66 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1735768 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.7 MiB 85.10 145328 1179878 360849 786061 32968 1640.5 MiB 69.36 0.64 5.18803 -16009.3 -4.18803 4.71553 0.06 0.152706 0.134393 18.4109 15.5777 214240 8.92778 54586 2.27470 53253 96856 65663526 17180534 0 0 7.26079e+07 20580.5 19 1120110 13214470 -1 5.62731 5.62731 -28524.3 -4.62731 0 0 23.91 -1 -1 1640.5 MiB 26.16 26.596 22.9352 1640.5 MiB -1 19.18 -3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 136.47 vpr 1.23 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1290392 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1065.8 MiB 47.70 152283 278120 75325 183121 19674 1260.1 MiB 18.99 0.21 5.35599 -16505.5 -4.35599 4.51559 0.02 0.0653283 0.0529731 5.96357 4.87661 239529 19.9226 64112 5.33245 57238 170600 111195486 21263938 0 0 3.14199e+07 20455.7 20 483264 5705245 -1 6.61831 5.4172 -26290.3 -5.61831 0 0 10.52 -1 -1 1260.1 MiB 32.71 9.93276 8.38713 1260.1 MiB -1 7.29 -3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 437.55 vpr 1.78 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1867528 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1362.4 MiB 112.91 292652 2022878 726716 1212218 83944 1695.6 MiB 151.83 1.37 193.523 -65237.6 -192.523 193.523 0.06 0.213557 0.18157 25.9931 22.1715 453070 13.8304 113197 3.45545 117143 365096 327048949 70274290 0 0 7.26079e+07 20580.5 21 1120110 13214470 -1 201.969 201.969 -83602 -200.969 0 0 23.94 -1 -1 1743.7 MiB 97.67 37.8603 32.6631 1695.6 MiB -1 18.81 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 67.95 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1235488 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1063.1 MiB 15.63 63489 256928 52638 188949 15341 1198.2 MiB 13.00 0.16 4.8555 -4307.79 -3.8555 2.47976 0.02 0.0366363 0.0322351 3.02693 2.52688 81757 6.57369 23123 1.85921 26483 36571 27721140 5378093 0 0 2.48366e+07 20391.3 14 382818 4502703 -1 4.99885 2.78104 -5808.83 -3.99885 0 0 8.34 -1 -1 1198.2 MiB 8.51 4.71161 4.0282 1198.2 MiB -1 5.30 -3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 447.54 vpr 2.19 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2300520 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.3 MiB 74.85 225689 1597136 573868 950177 73091 2246.6 MiB 97.02 0.89 7.40155 -34081.7 -6.40155 7.40155 0.16 0.121776 0.101863 14.3979 12.1212 339854 16.6595 81624 4.00118 64892 154040 296022532 107475224 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.54909 8.54909 -42257.7 -7.54909 0 0 62.88 -1 -1 2246.6 MiB 134.16 19.8788 17.0808 2246.6 MiB -1 53.46 -3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 304.70 vpr 2.43 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2550580 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.6 MiB 49.77 123671 1380047 554552 786292 39203 2490.8 MiB 31.02 0.26 10.5993 -16629.2 -9.59931 4.97242 0.18 0.0546677 0.0486849 7.77113 6.51315 175220 20.5344 38433 4.50404 23623 93265 107849323 36421682 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 12.8766 5.81047 -24731 -11.8766 0 0 79.59 -1 -1 2490.8 MiB 52.92 10.6013 9.06122 2490.8 MiB -1 68.45 -3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 117.22 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1225656 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.5 MiB 63.70 72669 252010 65056 180799 6155 1192.1 MiB 11.10 0.16 7.46032 -42922.1 -6.46033 7.46032 0.02 0.0386153 0.0330756 3.3215 2.67044 118105 18.7946 31588 5.02673 19732 92762 36148054 6649139 0 0 2.39639e+07 20377.5 15 369794 4343188 -1 7.99918 7.99918 -51485.8 -6.99918 0 0 8.05 -1 -1 1192.1 MiB 11.26 5.50251 4.59387 1192.1 MiB -1 5.21 -3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 24.11 vpr 992.77 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1016600 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.8 MiB 6.88 9528 9390 1205 7155 1030 992.8 MiB 0.57 0.01 5.30062 -3506.54 -4.30062 4.33661 0.00 0.00633989 0.00552195 0.266113 0.231235 16243 11.2408 5134 3.55294 3509 8574 4051674 833095 0 0 4.97530e+06 19135.8 10 75766 878809 -1 5.2881 4.86207 -4539.08 -4.2881 0 0 1.87 -1 -1 992.8 MiB 1.27 0.557486 0.502971 992.8 MiB -1 0.41 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 262.73 vpr 1.65 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1734948 22 252 53001 29054 7 22943 1413 54 40 4320 DSP auto 1237.0 MiB 40.61 553143 199178 920829 267183 541717 111929 1694.3 MiB 53.87 0.43 9.17101 7.5216 -35787.7 -6.5216 3.21182 0.04 0.16305 0.149822 18.4612 15.68 322466 14.0747 77116 3.36589 65350 138528 312160453 107280244 0 0 8.89497e+07 20590.2 18 1365594 16211305 -1 7.74971 3.11486 -42530.8 -6.74971 0 0 17.72 -1 -1 1694.3 MiB 111.17 24.7092 21.2822 1694.3 MiB -1 18.30 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 218.36 vpr 1.51 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1586640 3 33 48977 39238 1 26189 1635 40 30 2400 LAB auto 1260.7 MiB 55.85 675596 255759 897039 258557 606947 31535 1458.8 MiB 57.70 0.68 88.3086 81.3363 -53562.1 -80.3363 81.3363 0.02 0.116071 0.101917 12.5335 10.2057 414968 15.8475 103107 3.93764 93456 268271 242027202 52796438 0 0 4.91306e+07 20471.1 24 758110 8921656 -1 72.6061 72.6061 -112440 -71.6061 0 0 9.98 -1 -1 1494.3 MiB 64.92 19.6347 16.356 1458.8 MiB -1 8.68 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 457.48 vpr 1.96 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2060360 38 173 62892 59064 3 35490 2705 60 44 5280 M9K auto 1471.4 MiB 113.33 1 520068 1924283 670353 1216654 37276 1942.0 MiB 131.56 1.10 15.2717 11.5238 -301358 -10.5238 7.39686 0.05 0.213567 0.18504 27.6637 21.7347 817382 23.0365 199937 5.63489 142706 522733 461856750 113156179 0 0 1.08858e+08 20617.0 17 1675578 19868374 -1 13.8204 7.75079 -387049 -12.8204 0 0 22.95 -1 -1 1942.0 MiB 135.56 38.2071 30.7885 1942.0 MiB -1 24.32 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 652.90 vpr 1.93 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2028064 4 570 66175 54803 2 39253 3378 51 38 3876 LAB auto 1499.6 MiB 99.84 1 500409 2638218 943482 1600815 93921 1829.0 MiB 158.67 1.26 33.2636 26.8304 -103428 -25.8304 5.04591 0.03 0.211943 0.190267 27.9403 22.4025 815041 20.7664 199378 5.07995 180000 713197 1112642923 293988107 0 0 7.97022e+07 20563.0 19 1225854 14507865 -1 29.4376 6.2205 -118224 -28.4376 0 0 15.52 -1 -1 1877.4 MiB 329.08 39.5382 32.3284 1829.0 MiB -1 19.13 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 891.67 vpr 4.62 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4842964 19 21 171111 96274 1 69189 3920 129 96 24768 DSP auto 2000.7 MiB 71.30 2 645543 3742215 1460860 2253546 27809 4729.5 MiB 143.23 1.55 6.26745 5.38646 -75141.3 -4.38646 2.661 0.21 0.381461 0.352014 50.6194 44.9049 793742 11.4726 177452 2.56485 138089 170387 641489720 283501353 0 0 5.14406e+08 20769.0 13 7758968 93673935 -1 5.52629 3.53475 -126958 -4.52629 0 0 103.08 -1 -1 4729.5 MiB 405.15 65.0255 58.2156 4729.5 MiB -1 124.42 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 256.11 vpr 1.63 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1714208 227 309 49176 40422 1 28286 2492 47 35 3290 io auto 1318.7 MiB 72.10 949337 273836 1826396 645111 1142297 38988 1612.8 MiB 96.72 0.93 225.36 192.733 -109545 -191.733 192.733 0.02 0.156504 0.126676 20.8925 16.8363 408295 14.4366 100640 3.55845 86047 274415 147097876 28755122 0 0 6.75216e+07 20523.3 21 1033138 12274942 -1 200.665 200.665 -142282 -199.665 0 0 13.32 -1 -1 1612.8 MiB 36.86 29.3018 24.1342 1612.8 MiB -1 13.65 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 269.17 vpr 1.73 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1812688 3 33 52402 39411 1 26915 1592 57 42 4788 M9K auto 1284.6 MiB 61.12 807203 272165 819288 227842 565954 25492 1770.2 MiB 52.22 0.49 18.2161 15.3889 -291282 -14.3889 15.3889 0.05 0.120302 0.107221 13.5276 10.7971 422804 15.7135 103735 3.85532 81547 210905 297118544 78086054 0 0 9.85096e+07 20574.3 19 1507654 17957159 -1 16.9508 16.9508 -333506 -15.9508 0 0 19.51 -1 -1 1770.2 MiB 88.24 20.4969 16.8404 1770.2 MiB -1 24.30 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 89.89 vpr 1.24 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1302480 55 196 20131 19956 1 8019 1227 32 24 1536 LAB auto 1106.6 MiB 34.90 197415 104963 533073 153234 353035 26804 1272.0 MiB 12.26 0.14 8.14098 7.01338 -66863.1 -6.01338 7.01338 0.01 0.039475 0.0343628 4.18838 3.15967 176313 21.9951 44706 5.57710 30256 140591 66330875 12196118 0 0 3.14199e+07 20455.7 18 483264 5705245 -1 8.49466 8.49466 -83973.4 -7.49466 0 0 6.31 -1 -1 1272.0 MiB 15.31 6.65714 5.25964 1272.0 MiB -1 4.97 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 299.01 vpr 1.55 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1621904 84 171 36458 36247 3 20790 2367 44 33 2904 LAB auto 1267.4 MiB 80.84 546571 238344 1484559 494119 911634 78806 1532.2 MiB 40.61 0.36 12.4149 9.92645 -70892.9 -8.92645 4.01682 0.02 0.116517 0.0861493 12.2531 9.24683 412828 19.8704 97692 4.70216 64195 234317 420279392 124136285 0 0 5.95688e+07 20512.7 16 914964 10827114 -1 11.9935 4.50781 -88218.8 -10.9935 0 0 11.79 -1 -1 1532.2 MiB 133.15 17.7182 13.8758 1532.2 MiB -1 11.09 +3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 373.19 vpr 2.35 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2462636 36 33 57796 49182 1 19635 2569 79 59 9322 M144K auto 1407.5 MiB 62.12 653233 219853 2183357 820965 1334147 28245 2404.9 MiB 59.41 0.49 12.995 9.21965 -66996.8 -8.21965 9.21965 0.06 0.128267 0.100412 17.0634 13.614 394289 20.0860 93339 4.75492 57830 186027 364956321 126736164 0 0 1.92002e+08 20596.6 18 2917968 35039980 -1 8.77433 8.77433 -145846 -7.77433 0 0 38.68 -1 -1 2404.9 MiB 142.35 23.6694 19.4579 2404.9 MiB -1 44.19 +3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 392.27 vpr 2.07 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2167316 202 276 35125 30509 3 21318 2020 73 54 7884 M9K auto 1222.1 MiB 49.37 716730 226089 1457116 486885 913306 56925 2116.5 MiB 42.81 0.35 9.52583 8.88073 -26635 -7.88073 3.18285 0.07 0.119653 0.0909611 14.637 11.0787 399097 18.7264 91130 4.27599 54535 154132 519438963 188622732 0 0 1.62738e+08 20641.5 16 2479452 29744051 -1 9.08319 3.80572 -49812 -8.08319 0 0 32.24 -1 -1 2116.5 MiB 209.16 19.8689 15.6003 2116.5 MiB -1 36.86 +3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 85.50 vpr 1.44 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1509716 3 2 14862 10304 26 7561 466 49 36 3528 DSP auto 1056.3 MiB 18.88 169108 85844 135916 30477 93312 12127 1474.3 MiB 6.51 0.07 5.73048 5.557 -19015 -4.557 3.62644 0.03 0.0456596 0.0411065 4.08767 3.43596 157309 20.8771 36213 4.80597 18870 41509 57269136 14229362 0 0 7.26079e+07 20580.5 15 1120110 13214470 -1 5.78387 4.12666 -38218.5 -4.78387 0 0 14.31 -1 -1 1474.3 MiB 14.90 6.20184 5.31676 1474.3 MiB -1 15.38 +3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 248.43 vpr 1.78 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1866084 35 658 51416 37539 1 27424 2511 58 43 4988 io auto 1316.8 MiB 50.40 873485 226954 1964411 652069 1171686 140656 1822.3 MiB 73.09 0.61 49.8814 40.4001 -59333.6 -39.4001 40.4001 0.03 0.158116 0.128524 19.1544 15.9201 355332 13.7125 84607 3.26504 77692 234589 195988135 57038734 0 0 1.02587e+08 20566.7 20 1568252 18700371 -1 38.7069 38.7069 -65173.3 -37.7069 0 0 20.54 -1 -1 1822.3 MiB 56.96 26.6827 22.5702 1822.3 MiB -1 23.14 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 141.37 vpr 1.79 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1874180 13 740 25173 25306 1 12838 1890 63 47 5922 io auto 1153.9 MiB 36.12 470725 123620 1228290 428597 741781 57912 1830.3 MiB 24.74 0.23 10.849 8.56701 -26610 -7.56701 8.56701 0.05 0.083452 0.064458 8.41672 6.65404 186843 14.5618 44606 3.47642 30689 112737 37690136 7677659 0 0 1.22008e+08 20602.6 12 1871156 22275272 -1 9.76611 8.4502 -37527.7 -8.76611 0 0 24.66 -1 -1 1830.3 MiB 11.13 11.422 9.27304 1830.3 MiB -1 26.23 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 285.30 vpr 1.73 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1811880 79 38 66795 54922 1 35224 2428 47 35 3290 LAB auto 1382.5 MiB 92.81 1 237877 1503132 446447 1022533 34152 1655.8 MiB 78.24 0.76 13.2451 9.5537 -149791 -8.5537 9.5537 0.02 0.152306 0.114957 15.7483 12.0158 358747 10.1856 91140 2.58766 88569 216835 204329717 50299933 0 0 6.75216e+07 20523.3 18 1033138 12274942 -1 9.9587 9.9587 -197744 -8.9587 0 0 13.29 -1 -1 1682.4 MiB 65.08 23.1672 18.3775 1655.8 MiB -1 12.44 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 213.89 vpr 1.66 GiB 213 1559 26 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1740508 139 74 57121 41054 1 23901 1802 49 36 3528 DSP auto 1330.9 MiB 48.02 503320 154131 1174629 363761 769595 41273 1652.4 MiB 45.14 0.39 5.50142 5.06937 -14829.9 -4.06937 4.54902 0.03 0.138834 0.113113 15.68 12.9864 226482 9.47742 56073 2.34645 53387 100788 162800398 52833452 0 0 7.26079e+07 20580.5 19 1120110 13214470 -1 5.71253 5.71253 -26580.8 -4.71253 0 0 14.37 -1 -1 1652.4 MiB 63.76 22.1086 18.5194 1652.4 MiB -1 20.85 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 89.86 vpr 1.23 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1290592 2 52 16673 16662 2 11970 759 32 24 1536 M9K auto 1088.0 MiB 26.43 287692 161090 263719 72038 171536 20145 1260.3 MiB 11.76 0.13 6.37147 5.55664 -16395.7 -4.55664 4.47275 0.01 0.050566 0.0440543 5.03152 3.8482 241810 20.2081 60678 5.07087 57910 175927 97879920 19640107 0 0 3.14199e+07 20455.7 19 483264 5705245 -1 6.59971 5.40287 -26695.4 -5.59971 0 0 6.31 -1 -1 1260.3 MiB 24.34 8.27622 6.64124 1260.3 MiB -1 5.29 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 264.05 vpr 1.77 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1859132 131 314 57881 45152 1 32883 2670 49 36 3528 DSP auto 1415.0 MiB 62.59 1 282089 1946745 666918 1199261 80566 1701.5 MiB 104.89 1.01 225.053 191.914 -65212.8 -190.914 191.914 0.03 0.201041 0.162936 22.616 18.5359 440255 13.4200 111096 3.38645 97832 293933 160920714 33139153 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 194.207 194.207 -87739.7 -193.207 0 0 14.29 -1 -1 1736.8 MiB 41.90 32.0428 26.7006 1701.5 MiB -1 15.35 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 48.49 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1234732 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1076.6 MiB 8.80 177076 64046 227463 40446 173214 13803 1199.8 MiB 8.23 0.15 5.037 4.98027 -4032.99 -3.98027 2.30436 0.01 0.0456958 0.0355344 2.82114 2.35786 82605 6.53314 22481 1.77800 26837 36867 19813331 3639454 0 0 2.48366e+07 20391.3 15 382818 4502703 -1 5.12354 2.59981 -5253.47 -4.12354 0 0 5.41 -1 -1 1199.8 MiB 5.89 4.54065 3.86566 1199.8 MiB -1 4.08 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 272.56 vpr 2.19 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2297736 542 422 37277 26038 1 20404 2145 78 58 9048 io auto 1177.8 MiB 41.32 718781 227527 1550881 568722 914128 68031 2243.9 MiB 60.56 0.59 9.1469 7.25001 -32266.1 -6.25001 7.25001 0.08 0.111702 0.0914081 11.9361 9.76182 338642 16.5993 80909 3.96593 60739 140963 198511353 67181932 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.14337 8.14337 -40401.7 -7.14337 0 0 39.17 -1 -1 2243.9 MiB 66.88 16.2467 13.6205 2243.9 MiB -1 42.87 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 217.37 vpr 2.43 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2549592 403 704 15490 16194 1 8443 1837 88 65 11440 io auto 1076.1 MiB 26.90 391708 129482 1351357 540069 773475 37813 2489.8 MiB 18.66 0.17 12.456 10.282 -15333.7 -9.28198 4.73291 0.06 0.0436402 0.0391903 6.14215 4.89907 181658 21.5184 37765 4.47347 23596 95797 116291029 41210250 0 0 2.36204e+08 20647.2 14 3590540 43137666 -1 12.3059 5.94528 -23194.4 -11.3059 0 0 46.11 -1 -1 2489.8 MiB 49.68 8.25084 6.75286 2489.8 MiB -1 56.27 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 73.98 vpr 1.17 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1223460 18 17 16969 16357 1 6487 772 28 21 1176 LAB auto 1072.6 MiB 35.91 142961 68762 237952 59303 174205 4444 1190.2 MiB 7.64 0.11 8.63391 7.26898 -38694.5 -6.26898 7.26898 0.01 0.0364213 0.0268054 2.9362 2.27444 111711 17.2314 29470 4.54573 17605 69986 22583565 4090868 0 0 2.39639e+07 20377.5 17 369794 4343188 -1 8.03719 8.03719 -45879 -7.03719 0 0 4.86 -1 -1 1190.2 MiB 6.10 4.74059 3.843 1190.2 MiB -1 4.07 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 18.64 vpr 996.46 MiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1020380 18 17 2291 2142 1 1462 118 13 10 260 LAB auto 958.0 MiB 3.90 11981 9495 9077 1082 6988 1007 996.5 MiB 0.40 0.01 5.34371 5.28494 -3500.46 -4.28494 4.32118 0.00 0.00526682 0.00474166 0.209093 0.18422 16213 11.1124 5131 3.51679 3569 8497 3648403 741386 0 0 4.97530e+06 19135.8 10 75766 878809 -1 5.33265 4.71601 -4254.84 -4.33265 0 0 1.12 -1 -1 996.5 MiB 0.87 0.456072 0.414736 996.5 MiB -1 0.26 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt index 08e1f46286a..262c8456a37 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 536.55 vpr 1.66 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1736116 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1203.7 MiB 75.33 195509 902029 259905 557804 84320 1695.4 MiB 84.98 0.74 7.68567 -37648.9 -6.68567 3.28584 0.07 0.153024 0.133083 18.1163 15.7769 347393 15.1356 91110 3.96959 68562 144013 571183324 243523602 0 0 8.89497e+07 20590.2 16 1365594 16211305 -1 7.79531 3.22903 -48240.7 -6.79531 0 0 29.52 -1 -1 1695.4 MiB 297.68 25.2358 22.2605 1695.4 MiB -1 24.01 -3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 315.33 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1577588 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.4 MiB 101.58 259626 940116 279572 621693 38851 1444.2 MiB 104.57 1.20 82.1047 -56021.6 -81.1047 82.1047 0.03 0.137922 0.120416 14.543 12.1914 423885 16.2464 113939 4.36698 96228 253395 185059095 38347475 0 0 4.91306e+07 20471.1 24 758110 8921656 -1 72.5235 72.5235 -115556 -71.5235 0 0 16.27 -1 -1 1486.1 MiB 54.76 23.4199 19.9723 1444.2 MiB -1 12.10 -3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 679.10 vpr 1.96 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2051156 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.4 MiB 202.36 543821 1995713 704501 1236982 54230 1927.9 MiB 222.49 2.01 11.2639 -298285 -10.2639 7.34492 0.09 0.259679 0.207609 28.5947 23.0535 806716 22.8124 200624 5.67327 143147 517766 456418331 103863687 0 0 1.08858e+08 20617.0 18 1675578 19868374 -1 13.9133 7.76735 -393376 -12.9133 0 0 36.17 -1 -1 1927.9 MiB 150.24 41.7265 34.527 1927.9 MiB -1 29.72 -3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1027.30 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2017832 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.1 MiB 179.29 547789 2661451 958041 1608713 94697 1789.9 MiB 260.36 2.34 27.0929 -106609 -26.0929 5.35183 0.06 0.27456 0.228129 29.5628 24.7422 829210 21.1447 207429 5.28940 184705 723383 1302091086 364260887 0 0 7.97022e+07 20563.0 18 1225854 14507865 -1 30.5677 6.54028 -121409 -29.5677 0 0 25.79 -1 -1 1868.9 MiB 503.91 43.0657 36.7123 1789.9 MiB -1 20.41 -3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 925.95 vpr 4.62 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4842080 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.6 MiB 147.82 619747 3698710 1495912 2184534 18264 4728.6 MiB 198.02 2.37 6.78648 -99082.3 -5.78648 3.44108 0.45 0.48725 0.430185 61.9462 54.5962 814845 11.7998 205031 2.96905 140099 173436 458459419 150453276 0 0 5.14406e+08 20769.0 14 7758968 93673935 -1 6.45787 3.53717 -145075 -5.45787 0 0 172.18 -1 -1 4728.6 MiB 193.32 83.1106 74.2663 4728.6 MiB -1 156.75 -3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 409.69 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1712060 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.6 MiB 131.22 276554 1921016 711963 1138812 70241 1598.4 MiB 145.73 1.42 195.512 -113504 -194.512 195.512 0.05 0.160338 0.134313 19.3452 16.1804 416656 14.7244 107078 3.78408 104021 334271 218912879 40948386 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 198.006 198.006 -143215 -197.006 0 0 22.05 -1 -1 1607.4 MiB 63.92 28.3971 24.123 1598.4 MiB -1 16.81 -3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 443.45 vpr 1.73 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1814380 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.5 MiB 110.53 271211 807295 220659 561442 25194 1771.9 MiB 87.02 0.90 15.8645 -293903 -14.8645 15.8645 0.07 0.137468 0.119486 13.9778 11.464 446897 16.5806 122453 4.54320 84683 217412 421161484 116638965 0 0 9.85096e+07 20574.3 19 1507654 17957159 -1 17.551 17.551 -341289 -16.551 0 0 33.12 -1 -1 1771.9 MiB 157.72 22.3148 18.7943 1771.9 MiB -1 26.51 -3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 141.26 vpr 1.24 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1296500 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.2 MiB 59.31 113956 557464 166863 359124 31477 1246.8 MiB 24.59 0.29 7.08326 -66257.5 -6.08326 7.08326 0.02 0.055314 0.0441799 5.26138 4.20946 182605 22.0804 50112 6.05949 29285 119606 66293828 12593582 0 0 3.14199e+07 20455.7 15 483264 5705245 -1 8.63522 8.63522 -90099.9 -7.63522 0 0 10.47 -1 -1 1246.8 MiB 20.00 8.06464 6.66092 1246.8 MiB -1 7.35 -3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 368.03 vpr 1.54 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1613076 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.2 MiB 152.28 248422 1517216 526978 905843 84395 1523.2 MiB 71.70 0.64 10.4991 -73576.7 -9.49906 4.26563 0.04 0.123293 0.0990031 12.7883 10.3856 402144 19.7974 109429 5.38714 60309 208858 232045575 52278765 0 0 6.09438e+07 20519.8 18 935204 11078823 -1 12.8865 4.78217 -92799.1 -11.8865 0 0 20.13 -1 -1 1523.2 MiB 81.81 19.2634 16.033 1523.2 MiB -1 15.82 -3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 464.20 vpr 2.35 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2461196 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.2 MiB 116.23 224613 2251244 886249 1326045 38950 2403.5 MiB 95.91 0.83 9.49151 -92147.5 -8.49151 9.49151 0.14 0.154631 0.123533 20.7936 16.7804 397126 20.1046 99400 5.03215 58343 180947 261415498 79896454 0 0 1.92002e+08 20596.6 16 2917968 35039980 -1 8.83504 8.83504 -160829 -7.83504 0 0 63.50 -1 -1 2403.5 MiB 101.27 28.5358 23.7007 2403.5 MiB -1 55.56 -3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 411.57 vpr 2.07 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2167564 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.7 MiB 93.64 225707 1580536 560957 948186 71393 2116.8 MiB 74.70 0.59 9.27529 -27528.6 -8.27529 3.13114 0.14 0.130328 0.10251 17.2693 13.6101 391848 18.4721 94302 4.44548 55624 156547 339484601 88142541 0 0 1.62738e+08 20641.5 16 2479452 29744051 -1 9.56018 3.68158 -50102.5 -8.56018 0 0 53.61 -1 -1 2116.8 MiB 117.38 23.7611 19.3642 2116.8 MiB -1 45.57 -3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 144.75 vpr 1.44 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1510544 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 46.50 89280 149036 37755 99315 11966 1475.1 MiB 9.68 0.11 5.67702 -19268.5 -4.67702 3.75675 0.06 0.0566391 0.0498904 5.10516 4.33648 154058 20.3861 37061 4.90419 20488 44948 78925296 21606068 0 0 7.26079e+07 20580.5 14 1120110 13214470 -1 5.90336 3.89257 -40281.1 -4.90336 0 0 23.32 -1 -1 1475.1 MiB 26.78 7.88124 6.86256 1475.1 MiB -1 16.54 -3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 359.04 vpr 1.78 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1871392 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1280.5 MiB 91.15 211809 2071451 692754 1236953 141744 1827.5 MiB 125.31 1.09 40.9771 -61336.3 -39.9771 40.9771 0.07 0.171234 0.145898 21.8018 18.6515 342831 13.2280 87296 3.36829 76962 231011 136781567 33406286 0 0 1.02587e+08 20566.7 22 1568252 18700371 -1 39.0683 39.0683 -66985.6 -38.0683 0 0 34.25 -1 -1 1827.5 MiB 47.65 31.738 27.5672 1827.5 MiB -1 27.89 -3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 229.59 vpr 1.79 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1876484 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1132.6 MiB 66.93 129881 1180703 418671 705083 56949 1832.5 MiB 43.61 0.38 9.05339 -27832.3 -8.05339 9.05339 0.11 0.0813991 0.0719295 9.16919 7.64919 190989 15.0279 45936 3.61445 31437 116923 44250090 9507104 0 0 1.22008e+08 20602.6 13 1871156 22275272 -1 9.68529 8.62738 -38151.5 -8.68529 0 0 40.96 -1 -1 1832.5 MiB 16.73 13.1394 11.2088 1832.5 MiB -1 34.19 -3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 497.04 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1795972 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.1 MiB 155.39 246824 1707517 542100 1124665 40752 1627.5 MiB 155.77 1.28 9.48565 -168709 -8.48565 9.48565 0.05 0.168989 0.135904 19.3486 15.5394 380234 10.6523 107944 3.02407 107615 274456 330281609 74151890 0 0 6.75216e+07 20523.3 18 1033138 12274942 -1 10.455 10.455 -199956 -9.45504 0 0 22.28 -1 -1 1670.4 MiB 111.91 28.4097 23.3845 1627.5 MiB -1 17.60 -3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 327.67 vpr 1.66 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1742392 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.0 MiB 84.58 151125 1190888 390352 769055 31481 1646.6 MiB 73.69 0.67 5.16253 -15574.5 -4.16253 4.57572 0.06 0.14295 0.12611 17.3522 14.6159 255867 10.6625 71175 2.96600 55302 103707 208615694 72938344 0 0 7.26079e+07 20580.5 15 1120110 13214470 -1 5.91719 5.91719 -30815.6 -4.91719 0 0 23.62 -1 -1 1646.6 MiB 95.34 24.5543 21.0784 1646.6 MiB -1 19.49 -3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 139.09 vpr 1.23 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1291272 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.0 MiB 49.80 156611 278120 76189 183016 18915 1261.0 MiB 18.22 0.20 5.5971 -16655.2 -4.5971 4.5816 0.03 0.0587051 0.0472882 5.12731 4.2098 232871 19.3688 64465 5.36181 56972 170063 109738115 20757776 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.60942 5.3536 -26554.6 -5.60942 0 0 10.35 -1 -1 1261.0 MiB 31.51 8.7766 7.46125 1261.0 MiB -1 6.22 -3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 468.75 vpr 1.78 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1866664 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1361.4 MiB 115.86 298766 2022878 721872 1209208 91798 1694.5 MiB 174.52 1.53 192.881 -65340.9 -191.881 192.881 0.06 0.202016 0.181173 25.4109 21.5614 461781 14.0963 121424 3.70658 122316 378159 341015575 70726261 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 198.296 198.296 -88522.8 -197.296 0 0 24.15 -1 -1 1743.6 MiB 98.43 37.004 31.8471 1694.5 MiB -1 19.45 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.67 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1237180 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1063.0 MiB 15.45 60926 230944 41654 173553 15737 1197.6 MiB 9.59 0.15 4.84629 -4259.39 -3.84629 2.46064 0.02 0.0310798 0.0251181 2.06236 1.71947 97856 7.86814 33858 2.72236 28683 39681 30714017 6195766 0 0 2.48366e+07 20391.3 17 382818 4502703 -1 5.05177 2.69405 -5674.91 -4.05177 0 0 8.19 -1 -1 1197.6 MiB 8.55 3.63438 3.14676 1197.6 MiB -1 4.10 -3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 544.98 vpr 2.19 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2300396 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.1 MiB 76.17 219742 1555886 562141 922870 70875 2246.5 MiB 103.91 1.05 7.36593 -33948.8 -6.36593 7.36593 0.16 0.106572 0.0952071 13.4562 11.2916 354299 17.3676 93322 4.57461 68078 159956 457518312 185590185 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.09599 7.40175 -42456.2 -7.09599 0 0 61.24 -1 -1 2246.5 MiB 222.11 18.7938 16.1322 2246.5 MiB -1 52.95 -3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 302.19 vpr 2.43 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2550728 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.8 MiB 47.82 130160 1380047 560321 782548 37178 2490.9 MiB 35.48 0.32 10.5854 -18606.9 -9.58537 4.72024 0.18 0.0600238 0.0497498 7.88269 6.58458 172969 20.2706 38383 4.49818 23174 90029 105109403 34944955 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 11.6218 5.22111 -24845.6 -10.6218 0 0 75.93 -1 -1 2490.9 MiB 48.99 10.7341 9.14711 2490.9 MiB -1 68.06 -3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 124.32 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1226084 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1058.1 MiB 67.46 76143 241243 58815 176856 5572 1192.4 MiB 11.31 0.19 7.29112 -42594.5 -6.29112 7.29112 0.02 0.0414227 0.0316342 2.95997 2.38508 119636 19.0382 33085 5.26496 19940 91849 40304260 7468528 0 0 2.39639e+07 20377.5 15 369794 4343188 -1 7.77921 7.77921 -50567.3 -6.77921 0 0 7.94 -1 -1 1192.4 MiB 12.02 5.00754 4.21584 1192.4 MiB -1 4.51 -3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 27.66 vpr 993.31 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1017148 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.6 MiB 6.88 10156 8194 784 6524 886 993.3 MiB 0.47 0.01 5.3048 -3531.01 -4.3048 4.2956 0.00 0.00511192 0.00432104 0.195587 0.167728 15985 11.0623 5210 3.60554 3642 8882 4445146 900786 0 0 4.97530e+06 19135.8 9 75766 878809 -1 5.28906 4.84614 -4691.92 -4.28906 0 0 1.76 -1 -1 993.3 MiB 1.25 0.451107 0.405755 993.3 MiB -1 0.36 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 334.95 vpr 1.65 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1735176 22 252 53001 29054 7 22943 1413 54 40 4320 DSP auto 1236.8 MiB 39.56 578922 193642 857421 247994 504680 104747 1694.5 MiB 48.13 0.42 9.17101 7.49087 -36142.8 -6.49087 3.19653 0.03 0.125295 0.104169 14.4295 12.058 338207 14.7618 86292 3.76640 66292 141868 450896868 183262088 0 0 8.89497e+07 20590.2 19 1365594 16211305 -1 7.56673 3.20701 -45359.7 -6.56673 0 0 17.56 -1 -1 1694.5 MiB 186.32 20.7375 17.6809 1694.5 MiB -1 23.62 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 229.90 vpr 1.51 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1586264 3 33 48977 39238 1 26189 1635 40 30 2400 LAB auto 1260.0 MiB 55.36 757873 257834 897039 257029 596223 43787 1458.1 MiB 74.24 0.63 88.3086 81.3317 -50053.5 -80.3317 81.3317 0.01 0.105146 0.0940116 13.4495 10.8945 432701 16.5248 116936 4.46576 99467 278823 244875822 51834154 0 0 4.91306e+07 20471.1 23 758110 8921656 -1 71.1894 71.1894 -102916 -70.1894 0 0 9.90 -1 -1 1494.0 MiB 58.04 20.5097 16.9797 1458.1 MiB -1 9.97 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 494.51 vpr 1.96 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2056344 38 173 62892 59064 3 35490 2705 60 44 5280 M9K auto 1470.1 MiB 116.07 1 558842 1961961 687531 1237166 37264 1941.6 MiB 152.18 1.23 15.2717 11.52 -300506 -10.52 7.39565 0.05 0.236798 0.17913 26.1522 20.084 824365 23.2333 200032 5.63756 146563 541686 515541383 132244076 0 0 1.08858e+08 20617.0 19 1675578 19868374 -1 13.8006 7.7343 -390362 -12.8006 0 0 22.18 -1 -1 1941.6 MiB 149.83 37.4367 29.7549 1941.6 MiB -1 24.01 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 662.52 vpr 1.93 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2026664 4 570 66175 54803 2 39253 3378 51 38 3876 LAB auto 1498.9 MiB 100.63 1 538340 2663553 950678 1615590 97285 1811.8 MiB 189.07 1.51 33.2636 26.617 -103747 -25.617 4.66626 0.04 0.204109 0.182168 26.6617 21.2063 826051 21.0470 204139 5.20126 184571 733534 1066947846 281994208 0 0 7.97022e+07 20563.0 19 1225854 14507865 -1 29.0017 6.47485 -117845 -28.0017 0 0 16.59 -1 -1 1876.0 MiB 304.20 38.0144 31.0233 1811.8 MiB -1 22.95 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 974.86 vpr 4.62 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4843184 19 21 171111 96274 1 69189 3920 129 96 24768 DSP auto 2001.6 MiB 69.32 2 693471 3680425 1453106 2210247 17072 4729.7 MiB 146.15 1.30 6.26745 5.16452 -76724.7 -4.16452 2.59078 0.20 0.344722 0.312168 45.7424 39.8709 901905 13.0359 216953 3.13579 142016 174861 855691927 377239464 0 0 5.14406e+08 20769.0 10 7758968 93673935 -1 5.31158 3.88513 -129968 -4.31158 0 0 101.81 -1 -1 4729.7 MiB 487.76 58.3922 51.6098 4729.7 MiB -1 126.58 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 284.01 vpr 1.63 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1713088 227 309 49176 40422 1 28286 2492 47 35 3290 io auto 1318.4 MiB 72.69 1 270518 1843284 652509 1144115 46660 1612.7 MiB 112.42 1.09 225.36 192.167 -108313 -191.167 192.167 0.02 0.148363 0.117332 17.6108 14.0433 406382 14.3689 104909 3.70939 100739 322484 200315606 38175430 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 196.52 196.52 -140707 -195.52 0 0 13.37 -1 -1 1612.7 MiB 46.00 25.1451 20.5144 1612.7 MiB -1 14.43 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 286.50 vpr 1.73 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1814284 3 33 52402 39411 1 26915 1592 57 42 4788 M9K auto 1285.8 MiB 60.43 876865 266910 800704 217304 559963 23437 1771.8 MiB 61.41 0.60 18.2161 15.0487 -283662 -14.0487 15.0487 0.03 0.110665 0.0983698 12.2775 9.72807 437688 16.2667 118184 4.39231 80387 205200 336070247 92235784 0 0 9.85096e+07 20574.3 20 1507654 17957159 -1 16.6851 16.6851 -328192 -15.6851 0 0 19.81 -1 -1 1771.8 MiB 101.20 19.235 15.792 1771.8 MiB -1 21.91 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 97.20 vpr 1.24 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1295424 55 196 20131 19956 1 8019 1227 32 24 1536 LAB auto 1107.6 MiB 34.37 223666 104762 559337 165202 365871 28264 1250.3 MiB 15.54 0.18 8.14098 6.99011 -68950.8 -5.99011 6.99011 0.01 0.0412032 0.0359422 5.27129 3.9879 170106 21.2208 45801 5.71370 28180 132530 75236077 14372313 0 0 3.14199e+07 20455.7 16 483264 5705245 -1 8.3729 8.3729 -83722.3 -7.3729 0 0 6.22 -1 -1 1250.3 MiB 17.56 7.62394 6.01773 1250.3 MiB -1 5.04 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 384.18 vpr 1.54 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1619368 84 171 36458 36247 3 20790 2367 44 33 2904 LAB auto 1265.7 MiB 81.25 599300 249465 1358415 445363 846750 66302 1530.9 MiB 48.88 0.49 12.4149 9.90769 -70053.9 -8.90769 4.01156 0.02 0.125113 0.0930825 11.8346 9.00012 421592 20.2923 115009 5.53567 63988 231128 634239024 190371172 0 0 5.95688e+07 20512.7 14 914964 10827114 -1 12.3773 4.33722 -90025.8 -11.3773 0 0 12.02 -1 -1 1530.9 MiB 205.64 16.8356 13.2434 1530.9 MiB -1 12.70 +3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 364.66 vpr 2.35 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2462692 36 33 57796 49182 1 19635 2569 79 59 9322 M144K auto 1407.8 MiB 61.04 687588 229258 2165770 799905 1343807 22058 2405.0 MiB 66.46 0.56 12.995 9.11916 -68399.8 -8.11916 9.11916 0.05 0.11569 0.101098 16.3766 13.1783 408880 20.8293 101695 5.18059 58162 198761 352431329 112609659 0 0 1.92002e+08 20596.6 16 2917968 35039980 -1 9.21014 9.21014 -149701 -8.21014 0 0 38.27 -1 -1 2405.0 MiB 126.74 22.5268 18.6422 2405.0 MiB -1 45.70 +3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 334.46 vpr 2.07 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2166380 202 276 35125 30509 3 21318 2020 73 54 7884 M9K auto 1221.1 MiB 49.26 782110 235668 1444352 491382 903107 49863 2115.6 MiB 47.98 0.37 9.52583 8.86655 -25610.5 -7.86655 2.99007 0.05 0.113388 0.0837706 13.9235 10.3647 409338 19.2069 95423 4.47743 56405 161834 452534869 126896454 0 0 1.62738e+08 20641.5 17 2479452 29744051 -1 9.06444 3.63902 -49136.6 -8.06444 0 0 32.05 -1 -1 2115.6 MiB 143.44 19.4196 15.1436 2115.6 MiB -1 38.29 +3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 93.02 vpr 1.44 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1509456 3 2 14862 10304 26 7561 466 49 36 3528 DSP auto 1055.2 MiB 18.70 184798 80217 134110 31670 91390 11050 1474.1 MiB 6.31 0.08 5.73048 5.557 -20016.6 -4.557 3.71419 0.02 0.0465293 0.0376548 3.66706 3.03776 144728 19.2074 35518 4.71374 19254 41730 71856535 20086137 0 0 7.26079e+07 20580.5 14 1120110 13214470 -1 5.72459 4.15885 -44268.6 -4.72459 0 0 14.02 -1 -1 1474.1 MiB 23.72 6.15974 5.26532 1474.1 MiB -1 12.92 +3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 241.71 vpr 1.78 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1867272 35 658 51416 37539 1 27424 2511 58 43 4988 io auto 1317.8 MiB 48.90 948323 227264 1964411 655805 1166964 141642 1823.5 MiB 85.85 0.67 49.8814 40.5997 -59715.9 -39.5997 40.5997 0.04 0.133507 0.12216 18.3999 15.2293 359668 13.8798 88521 3.41608 73222 220528 152022396 37203782 0 0 1.02587e+08 20566.7 20 1568252 18700371 -1 40.8996 40.8996 -65115.3 -39.8996 0 0 20.34 -1 -1 1823.5 MiB 39.38 26.0518 21.9742 1823.5 MiB -1 22.82 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 147.75 vpr 1.79 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1876732 13 740 25173 25306 1 12838 1890 63 47 5922 io auto 1156.9 MiB 35.93 511809 124272 1134850 394535 689272 51043 1832.7 MiB 28.51 0.25 10.849 8.55919 -26577.3 -7.55919 8.55919 0.03 0.0667231 0.0595066 7.86607 6.21979 187381 14.6038 45597 3.55366 31219 114564 45280930 9170650 0 0 1.22008e+08 20602.6 12 1871156 22275272 -1 8.85362 8.18245 -36071.1 -7.85362 0 0 23.97 -1 -1 1832.7 MiB 12.64 10.8902 8.85884 1832.7 MiB -1 26.57 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 296.29 vpr 1.73 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1809912 79 38 66795 54922 1 35224 2428 47 35 3290 LAB auto 1382.3 MiB 92.47 1 244493 1601004 478977 1083677 38350 1655.1 MiB 108.35 0.97 13.2451 9.45262 -152441 -8.45262 9.45262 0.02 0.180003 0.141249 17.875 13.8444 383139 10.8781 107986 3.06595 89630 211664 136543668 29891467 0 0 6.75216e+07 20523.3 18 1033138 12274942 -1 10.5596 10.5596 -195977 -9.55964 0 0 13.38 -1 -1 1681.6 MiB 41.09 25.8122 20.6734 1655.1 MiB -1 14.63 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 193.20 vpr 1.66 GiB 213 1559 26 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1739984 139 74 57121 41054 1 23901 1802 49 36 3528 DSP auto 1330.9 MiB 45.46 523367 143054 1119824 339931 747988 31905 1653.1 MiB 46.98 0.41 5.50142 5.05519 -14801.7 -4.05519 4.55656 0.03 0.111545 0.100323 13.4118 10.9396 233997 9.79190 63575 2.66038 54368 101664 139712299 42351509 0 0 7.26079e+07 20580.5 19 1120110 13214470 -1 5.90983 5.90983 -28470.6 -4.90983 0 0 14.30 -1 -1 1653.1 MiB 48.30 19.8642 16.6405 1653.1 MiB -1 14.85 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 101.42 vpr 1.22 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1279356 2 52 16673 16662 2 11970 759 32 24 1536 M9K auto 1087.6 MiB 26.11 316622 152696 263719 67846 176857 19016 1238.4 MiB 13.70 0.18 6.37147 5.42709 -16155.6 -4.42709 4.492 0.01 0.0855605 0.0661458 5.59717 4.06858 233040 19.4752 63998 5.34832 55775 171602 116320989 22499207 0 0 3.14199e+07 20455.7 18 483264 5705245 -1 6.05833 5.08903 -23533.3 -5.05833 0 0 6.36 -1 -1 1238.4 MiB 29.49 8.83367 6.8784 1238.4 MiB -1 6.59 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 292.25 vpr 1.77 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1857400 131 314 57881 45152 1 32883 2670 49 36 3528 DSP auto 1413.6 MiB 63.48 1 297270 2002290 694221 1220745 87324 1700.3 MiB 124.60 1.21 225.053 189.331 -63929.8 -188.331 189.331 0.09 0.21317 0.174938 22.1816 17.9981 462294 14.0918 121369 3.69960 100939 303602 159579775 32291150 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 192.009 192.009 -84741.7 -191.009 0 0 14.68 -1 -1 1735.5 MiB 40.29 31.8982 26.4487 1700.3 MiB -1 21.53 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 44.47 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1236332 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1077.5 MiB 8.12 181772 60454 212839 35803 162171 14865 1200.7 MiB 6.20 0.10 5.037 4.84997 -4107.52 -3.84997 2.38954 0.01 0.0265953 0.0205781 1.71761 1.36841 96083 7.59910 31864 2.52009 28520 38733 28269527 5661726 0 0 2.48366e+07 20391.3 15 382818 4502703 -1 4.9803 2.58263 -5331.74 -3.9803 0 0 4.91 -1 -1 1200.7 MiB 6.11 2.96918 2.47893 1200.7 MiB -1 3.15 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 329.98 vpr 2.19 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2299956 542 422 37277 26038 1 20404 2145 78 58 9048 io auto 1179.3 MiB 39.88 750296 213881 1564709 559535 935357 69817 2246.1 MiB 69.17 0.63 9.1469 7.11198 -32381.7 -6.11198 7.11198 0.08 0.0974836 0.0779271 11.5163 9.28631 341769 16.7526 89371 4.38072 60396 139032 295235636 115037667 0 0 1.86852e+08 20651.1 18 2837414 34147767 -1 7.84316 7.84316 -40742.7 -6.84316 0 0 37.49 -1 -1 2246.1 MiB 117.77 16.1021 13.3782 2246.1 MiB -1 43.62 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 211.58 vpr 2.43 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2549800 403 704 15490 16194 1 8443 1837 88 65 11440 io auto 1076.7 MiB 26.61 420969 124674 1306373 513997 754918 37458 2490.0 MiB 21.13 0.19 12.456 10.0834 -15995.3 -9.08343 4.54503 0.06 0.0524896 0.0408569 6.33274 5.00588 170906 20.2447 36943 4.37610 23908 97711 100577096 33451296 0 0 2.36204e+08 20647.2 14 3590540 43137666 -1 11.8824 5.51915 -23728.3 -10.8824 0 0 46.41 -1 -1 2490.0 MiB 40.76 8.49023 6.9148 2490.0 MiB -1 56.37 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 74.16 vpr 1.17 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1222316 18 17 16969 16357 1 6487 772 28 21 1176 LAB auto 1071.6 MiB 34.98 163040 70478 237952 59222 174028 4702 1189.2 MiB 8.18 0.11 8.63391 7.28108 -38373.3 -6.28108 7.28108 0.01 0.0359793 0.0322549 3.04189 2.44357 109926 16.9560 30088 4.64106 17978 72156 23692991 4307201 0 0 2.39639e+07 20377.5 18 369794 4343188 -1 7.70533 7.70533 -42097.5 -6.70533 0 0 4.95 -1 -1 1189.2 MiB 6.63 5.04612 4.213 1189.2 MiB -1 3.26 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 19.87 vpr 996.40 MiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1020316 18 17 2291 2142 1 1462 118 13 10 260 LAB auto 957.9 MiB 3.90 13715 9496 7921 840 6234 847 996.4 MiB 0.32 0.01 5.34371 5.29372 -3553.58 -4.29372 4.35136 0.00 0.00350229 0.00303545 0.139546 0.120047 16149 11.0685 5505 3.77313 3716 8872 3987965 814573 0 0 4.97530e+06 19135.8 10 75766 878809 -1 5.46481 4.6943 -4312.85 -4.46481 0 0 1.11 -1 -1 996.4 MiB 0.84 0.330704 0.297098 996.4 MiB -1 0.23 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt index 37bf9a4b00b..38d2cb49a09 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt @@ -1,23 +1,23 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 5977.17 vpr 18.15 GiB 373 16802 116 5043 16 0 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan 19027644 178 195 583584 0 2 400505 22350 450 333 149850 -1 titan_extra_large -1 -1 8 13800219 48167472 20323894 27731780 111798 18581.7 MiB 4325.24 9.70 -1 -1 -1 -1 -1 -1 0 0 0 0 14590895 36.4326 2750092 6.86682 839764 1658253 951523382 215783707 0 0 2.82057e+09 18822.7 11 43073670 476336488 -1 -1 -1 -1 -1 -1 -1 786.18 -1 -1 18581.7 MiB 264.68 0 0 18581.7 MiB -1 431.81 -stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6231.23 vpr 12.33 GiB 446 31279 112 1175 0 2 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 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sparcT1_core_stratixiv_arch_timing.blif common 593.70 vpr 2.30 GiB 310 4048 1 127 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2408112 173 137 91964 0 1 52595 4486 100 74 7400 -1 titan_extra_small -1 -1 1 701026 3665704 1199971 2414430 51303 2342.3 MiB 507.92 0.94 -1 -1 -1 -1 -1 -1 0 0 0 0 933577 17.7516 222529 4.23131 115794 398921 86466898 16450293 0 0 1.36295e+08 18418.2 10 2149958 23360463 -1 -1 -1 -1 -1 -1 -1 23.07 -1 -1 2342.7 MiB 21.26 0 0 2342.3 MiB -1 15.04 +stratixiv_arch.timing.xml sparcT2_core_stratixiv_arch_timing.blif common 2428.42 vpr 6.32 GiB 451 14815 0 260 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6622024 239 212 299957 0 1 174676 15526 225 167 37575 -1 titan_medium -1 -1 8 3000892 22279641 8949040 13229480 101121 6466.8 MiB 2086.27 5.15 -1 -1 -1 -1 -1 -1 0 0 0 0 3694237 21.1496 850013 4.86634 392535 1469224 301011264 53478430 0 0 6.95906e+08 18520.5 11 10840348 119192345 -1 -1 -1 -1 -1 -1 -1 118.82 -1 -1 6466.8 MiB 75.27 0 0 6466.8 MiB -1 80.99 +stratixiv_arch.timing.xml stap_qrd_stratixiv_arch_timing.blif common 1555.59 vpr 5.68 GiB 150 16236 75 553 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 5958512 68 82 237991 0 1 132235 17014 225 167 37575 -1 titan_medium -1 -1 4 1577017 32169883 12567240 19371382 231261 5818.9 MiB 1258.31 3.41 -1 -1 -1 -1 -1 -1 0 0 0 0 1918789 14.5267 433717 3.28357 242067 559136 213519358 50500725 0 0 6.95906e+08 18520.5 9 10840348 119192345 -1 -1 -1 -1 -1 -1 -1 116.17 -1 -1 5818.9 MiB 47.24 0 0 5818.9 MiB -1 85.73 +stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 384.55 vpr 2.93 GiB 506 3281 77 113 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 3067304 172 334 94412 0 3 58023 3977 150 111 16650 -1 titan_small -1 -1 727715 437837 2933105 904764 1973968 54373 2995.4 MiB 262.89 0.38 -1 -1 -1 -1 -1 -1 0 0 0 0 500495 8.62670 115929 1.99819 109749 157743 47396298 10426845 0 0 3.08275e+08 18515.0 8 4815530 52742011 -1 -1 -1 -1 -1 -1 -1 50.78 -1 -1 2995.4 MiB 10.64 0 0 2995.4 MiB -1 34.16 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt index 718952957d1..eceaa56b4b1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt @@ -1,17 +1,17 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 430.27 vpr 7.22 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7572608 22 252 53001 29054 7 22984 1419 89 66 5874 DSP auto 2999.7 MiB 77.55 248316 1021579 298715 629192 93672 3552.4 MiB 75.43 0.60 7.79847 -44076.4 -6.79847 3.16357 0.04 0.145495 0.126331 19.1685 16.7404 337990 6.38090 73939 1.39589 113486 262947 123939600 20677912 0 0 1.48102e+08 25213.2 18 3168173 32237029 53333 8.13811 2.93957 -42084.8 -7.13811 0 0 30.24 37.78 22.78 7394.9 MiB 150.02 24.6012 21.633 3552.4 MiB 61.30 11.40 -stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 423.49 vpr 6.82 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7148500 3 33 48977 39238 1 26095 1641 54 40 2160 LAB auto 3019.2 MiB 103.15 286068 978816 295772 657268 25776 3171.0 MiB 80.85 0.83 87.9237 -89444.7 -86.9237 87.9237 0.02 0.133548 0.111652 14.7315 12.3725 377246 7.70314 89630 1.83019 136470 456181 107134305 13321542 0 0 5.45421e+07 25251.0 24 2489089 26482784 65639 72.0152 72.0152 -145316 -71.0152 0 0 10.89 30.08 16.61 6981.0 MiB 142.54 20.844 17.5112 3143.2 MiB 62.59 3.96 -stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 711.87 vpr 7.51 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7875556 4 570 66175 54803 2 39221 3376 91 67 6097 io auto 3239.4 MiB 185.13 637050 2737396 996225 1655508 85663 3733.5 MiB 161.80 1.29 31.0835 -120493 -30.0835 7.14678 0.06 0.211633 0.187447 26.5121 22.2855 899864 13.5993 200525 3.03045 250269 1330369 403832098 58432790 0 0 1.53687e+08 25207.0 23 4527063 53934418 131001 31.4743 7.04434 -123107 -30.4743 0 0 31.82 48.91 25.68 7690.6 MiB 229.13 35.3927 29.9033 3733.5 MiB 54.44 12.02 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 490.17 vpr 7.44 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7802588 3 33 52402 39411 1 26961 1588 73 54 3942 M9K auto 3038.9 MiB 115.22 308817 862861 247827 593176 21858 3344.5 MiB 70.28 0.75 18.2872 -344515 -17.2872 18.2872 0.04 0.144193 0.116967 14.4383 11.7329 388387 7.41281 89501 1.70823 127828 482181 86633732 10962711 0 0 9.96402e+07 25276.6 23 3049699 30612935 82279 18.1508 18.1508 -339276 -17.1508 0 0 19.96 46.42 29.95 7619.5 MiB 155.40 20.4894 16.7826 3344.5 MiB 62.62 7.54 -stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 264.87 vpr 6.35 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6658268 55 196 20131 19956 1 8273 1224 44 33 1452 io auto 2885.6 MiB 59.05 121891 590184 190135 382049 18000 3003.9 MiB 21.76 0.23 8.00991 -79285.3 -7.00991 8.00991 0.01 0.0550621 0.0436789 5.54087 4.43725 168265 8.35975 39603 1.96756 52203 214680 35422307 3611930 0 0 3.65459e+07 25169.4 13 1361186 16140321 53661 8.2494 8.2494 -80319.6 -7.2494 0 0 7.63 18.91 10.40 6502.2 MiB 101.02 6.87899 5.53912 2972.4 MiB 65.45 3.08 -stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 461.02 vpr 6.99 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7325496 84 171 36458 36247 3 20327 2406 62 46 2852 LAB auto 3026.4 MiB 149.19 282856 1613906 577988 956437 79481 3228.2 MiB 60.47 0.55 12.7635 -89890.6 -11.7635 4.81564 0.03 0.118349 0.0946709 13.1884 10.6839 385220 10.5702 85805 2.35443 120726 551439 87035965 8547461 0 0 7.20342e+07 25257.4 15 2649463 32096142 68009 12.7106 4.59591 -89170.4 -11.7106 0 0 14.69 35.95 19.46 7153.8 MiB 138.86 16.8557 13.6644 3228.2 MiB 62.61 5.90 -stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 536.44 vpr 7.68 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 8052732 202 276 35125 30509 3 21219 2016 106 79 8374 M9K auto 2979.7 MiB 92.45 275268 1593266 551386 986614 55266 3817.0 MiB 63.87 0.46 9.2665 -49067 -8.2665 3.57275 0.06 0.128588 0.0997349 17.2665 13.8123 330934 9.42322 69644 1.98309 96626 409213 76592480 17612840 0 0 2.11296e+08 25232.4 22 3960168 43100363 65824 7.92317 3.74791 -72552.8 -6.92317 0 0 43.69 57.06 35.19 7864.0 MiB 168.53 22.5205 18.1449 3817.0 MiB 63.34 20.57 -stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 316.30 vpr 6.89 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7222344 3 2 14862 10304 26 7583 476 89 66 5874 DSP auto 2832.3 MiB 45.71 124138 182462 49732 129080 3650 3434.9 MiB 11.57 0.11 5.88079 -31819.8 -4.88079 4.5134 0.05 0.0575387 0.0481419 6.23293 5.24991 151302 10.1983 29977 2.02056 41602 169090 28196463 3392334 0 0 1.48102e+08 25213.2 14 2293667 23918971 38105 5.43555 4.34297 -36900.7 -4.43555 0 0 31.66 30.81 19.91 7053.1 MiB 114.27 8.0475 6.8139 3434.9 MiB 67.70 13.08 -stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 542.79 vpr 7.40 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7764172 35 658 51416 37539 1 27427 2531 108 80 8640 io auto 3075.8 MiB 93.41 241934 2243861 754419 1344439 145003 3917.1 MiB 110.58 0.77 41.8615 -66574.8 -40.8615 41.8615 0.09 0.160304 0.137258 23.4482 20.061 335308 6.71879 78438 1.57171 166276 681051 158387837 20955778 0 0 2.18142e+08 25247.9 25 4407721 50162159 84809 37.8945 37.8945 -63952.6 -36.8945 0 0 44.15 46.45 23.73 7582.2 MiB 178.57 31.4578 26.962 3917.1 MiB 63.71 20.46 -stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 387.65 vpr 7.01 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7354908 13 740 25173 25306 1 12716 1903 117 87 10179 io auto 2928.2 MiB 67.88 151917 1239643 452352 735278 52013 3981.2 MiB 35.57 0.31 9.32912 -33745.1 -8.32912 8.97758 0.07 0.0799309 0.0699705 9.04546 7.55642 187992 7.47008 41392 1.64476 64808 295441 45317315 4493718 0 0 2.57088e+08 25256.7 13 4146271 46119125 60560 9.51895 7.86886 -41989.5 -8.51895 0 0 53.18 36.15 16.47 7182.2 MiB 123.92 11.2875 9.41327 3981.2 MiB 65.19 23.64 -stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 286.07 vpr 6.67 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6992700 2 52 16673 16662 2 12027 760 37 27 999 LAB auto 2863.8 MiB 48.35 185817 260785 68816 184545 7424 2969.0 MiB 17.52 0.22 6.43593 -22019.6 -5.43593 5.34219 0.01 0.0671365 0.0537497 5.45437 4.46867 243748 14.6228 55949 3.35647 70980 378754 80104321 9851562 0 0 2.50403e+07 25065.4 18 1109643 11618783 35248 6.97929 5.65113 -27162.3 -5.97929 0 0 5.11 17.57 11.32 6828.4 MiB 118.26 7.83981 6.43355 2903.7 MiB 66.65 1.88 -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 191.95 vpr 6.21 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6512136 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 2859.5 MiB 15.81 72155 253216 50624 190930 11662 2954.0 MiB 12.28 0.16 5.18599 -5515.92 -4.18599 2.85104 0.01 0.0356803 0.031132 2.85133 2.36966 82362 3.13247 19973 0.759632 54490 69977 15062795 1948535 0 0 2.84316e+07 25138.5 15 1246468 12354669 14284 3.84664 2.85129 -5700.97 -2.84664 0 0 5.78 12.08 6.10 6359.5 MiB 88.58 3.91742 3.26807 2899.6 MiB 66.17 2.25 -stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 545.23 vpr 7.47 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7832592 542 422 37277 26038 1 20403 2136 147 109 16023 io auto 2946.3 MiB 79.74 272838 1734636 659517 1007756 67363 4655.4 MiB 94.94 0.83 8.43041 -42423.1 -7.43041 8.08995 0.12 0.108337 0.0956704 15.1499 12.7644 351764 9.43725 76208 2.04454 89867 266535 93690673 14464239 0 0 4.05150e+08 25285.5 17 5915256 66794449 49681 8.39022 7.49893 -50294.9 -7.39022 0 0 83.08 50.78 21.66 7649.0 MiB 158.81 18.8518 16.0306 4655.4 MiB 64.94 40.50 -stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 445.21 vpr 7.31 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7666364 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 2857.1 MiB 56.44 187193 1324022 523278 764997 35747 5137.0 MiB 26.81 0.24 12.7682 -23323.6 -11.7682 6.27217 0.15 0.0586464 0.0483811 7.15433 5.97963 227077 14.6605 37744 2.43683 40915 222692 34388107 3312547 0 0 5.23918e+08 25300.3 17 6721105 74589014 36638 11.3367 5.96529 -32928.6 -10.3367 0 0 108.17 38.65 9.61 7486.7 MiB 125.03 9.2614 7.7773 5137.0 MiB 64.95 52.28 -stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 247.80 vpr 6.23 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6530136 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 2855.4 MiB 65.95 84377 244832 62116 178083 4633 2954.7 MiB 10.90 0.16 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0380001 0.0324758 3.26975 2.63245 117354 6.91742 28009 1.65099 42731 188939 30663841 3241611 0 0 2.84316e+07 25138.5 16 1092397 12303174 43762 7.24996 7.24996 -46266.9 -6.24996 0 0 5.81 13.06 7.12 6376.9 MiB 93.57 4.60783 3.72572 2904.9 MiB 65.30 2.17 -stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 143.49 vpr 5.89 GiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6175112 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 2752.7 MiB 6.96 10189 9390 1103 7334 953 2822.6 MiB 0.78 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00661338 0.00538061 0.265542 0.227477 13189 5.76442 3423 1.49607 7406 28929 4207039 458732 0 0 4.71840e+06 24575.0 16 154367 1513720 4558 4.32353 4.32353 -3831.79 -3.32353 0 0 1.05 2.34 1.56 6030.2 MiB 71.16 0.476743 0.411197 2791.2 MiB 66.66 0.13 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 307.76 vpr 7.22 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7570660 22 252 53001 29054 7 22943 1413 89 66 5874 DSP auto 3091.9 MiB 38.56 785441 248898 952533 277008 615830 59695 3553.0 MiB 58.72 0.42 11.048 8.33765 -44315.5 -7.33765 3.31053 0.05 0.113159 0.101872 15.1213 12.8155 335814 6.33982 72558 1.36982 112366 258577 120602969 20086295 0 0 1.48102e+08 25213.2 22 3167005 32167053 52611 8.18405 2.97937 -42387.2 -7.18405 0 0 17.95 20.24 13.22 7393.2 MiB 105.27 20.5108 17.3765 3553.0 MiB 45.06 11.83 +stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 295.25 vpr 6.82 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7146600 3 33 48977 39238 1 26189 1635 54 40 2160 LAB auto 3111.9 MiB 55.69 913357 292251 954807 280946 652655 21206 3167.9 MiB 64.31 0.69 102.633 87.8923 -93476.3 -86.8923 87.8923 0.01 0.121167 0.109007 12.9627 10.3995 392169 8.00786 92776 1.89443 131896 428998 101231115 12788547 0 0 5.45421e+07 25251.0 22 2488874 26464161 65179 72.6371 72.6371 -155945 -71.6371 0 0 6.58 15.88 9.56 6979.1 MiB 97.37 18.0468 14.5179 3126.4 MiB 44.79 3.09 +stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 613.29 vpr 7.51 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7873588 4 570 66175 54803 2 39253 3378 91 67 6097 io auto 3351.8 MiB 97.41 2 646400 2739558 982870 1670046 86642 3736.8 MiB 161.18 1.35 58.3021 30.6995 -120781 -29.6995 6.48152 0.04 0.227064 0.202621 28.3082 22.6242 933895 14.1136 207960 3.14281 243517 1313252 476687912 77203454 0 0 1.53687e+08 25207.0 24 4526159 53918290 131473 29.867 6.58528 -125533 -28.8671 0 0 19.50 30.20 17.91 7689.1 MiB 239.13 39.9958 32.2561 3736.8 MiB 46.13 13.16 +stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 343.46 vpr 7.45 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7809824 3 33 52402 39411 1 26915 1592 74 55 4070 M9K auto 3137.9 MiB 60.29 1 313744 856456 241378 601294 13784 3367.6 MiB 56.98 0.53 26.6374 18.392 -352998 -17.392 18.392 0.03 0.127652 0.0989751 13.2638 10.4714 393956 7.51911 89554 1.70924 123845 444274 79417493 9945038 0 0 1.02834e+08 25266.3 24 3087425 31058302 82003 18.2351 18.2351 -353089 -17.2351 0 0 12.20 24.60 16.53 7626.8 MiB 102.44 19.149 15.2376 3367.6 MiB 43.75 6.15 +stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 191.30 vpr 6.35 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6654744 55 196 20131 19956 1 8019 1227 44 33 1452 io auto 2959.2 MiB 34.98 264174 123065 585601 181370 380069 24162 3001.9 MiB 14.48 0.15 11.4541 8.37477 -85221.8 -7.37477 8.37477 0.01 0.0435657 0.0381802 4.91609 3.72033 171879 8.53930 40193 1.99687 53315 220453 36996311 3799813 0 0 3.65459e+07 25169.4 17 1360469 16108772 53595 8.25592 8.25592 -83672.5 -7.25592 0 0 4.49 10.24 6.25 6498.8 MiB 73.99 7.12109 5.46457 2962.2 MiB 47.31 2.36 +stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 321.12 vpr 6.98 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7315800 84 171 36458 36247 3 20790 2367 61 45 2745 LAB auto 3120.3 MiB 80.93 720648 283198 1531863 524079 936471 71313 3240.9 MiB 53.41 0.48 18.575 13.0627 -93585.1 -12.0627 4.74826 0.02 0.135818 0.102003 15.2067 11.7347 383302 10.5176 85503 2.34615 122093 565734 90030158 8803236 0 0 6.93753e+07 25273.3 15 2618803 31747680 67913 12.8798 4.63258 -92475 -11.8798 0 0 8.61 19.57 11.78 7144.3 MiB 97.12 19.0364 14.7691 3240.9 MiB 46.87 5.47 +stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 384.22 vpr 7.68 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 8054852 202 276 35125 30509 3 21318 2020 106 79 8374 M9K auto 3074.5 MiB 51.00 986671 267666 1508172 523381 949193 35598 3817.7 MiB 47.09 0.37 11.3759 9.26548 -48475.6 -8.26548 3.33529 0.04 0.124097 0.0915348 15.1053 11.4683 328144 9.34377 68354 1.94635 96064 399914 79957226 23499170 0 0 2.11296e+08 25232.4 21 3960955 43098624 64956 7.95847 3.473 -71149.3 -6.95847 0 0 26.34 31.74 20.98 7866.1 MiB 120.27 19.7897 15.1067 3817.7 MiB 46.45 15.33 +stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 209.11 vpr 6.86 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7192244 3 2 14862 10304 26 7561 466 89 66 5874 DSP auto 2906.5 MiB 19.29 270018 117214 172036 45994 123462 2580 3432.3 MiB 8.33 0.08 9.28243 6.01869 -39114.1 -5.01869 4.08518 0.03 0.0454291 0.0406349 5.15593 4.32319 142371 9.59632 28892 1.94743 41759 169140 29445405 3626320 0 0 1.48102e+08 25213.2 15 2293067 23897973 38057 4.93599 4.08638 -46486.1 -3.93599 0 0 18.14 15.12 10.24 7023.7 MiB 70.97 6.81564 5.74588 3432.3 MiB 44.34 9.65 +stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 373.15 vpr 7.40 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7755920 35 658 51416 37539 1 27424 2511 108 80 8640 io auto 3164.2 MiB 50.50 1 251917 2152071 724984 1286743 140344 3911.0 MiB 82.56 0.70 74.2949 42.7394 -67262.7 -41.7394 42.7394 0.07 0.162863 0.131205 20.6635 16.9624 352057 7.05454 81260 1.62829 152474 598323 166291976 23812913 0 0 2.18142e+08 25247.9 24 4403936 50039004 85327 39.992 39.992 -64895.1 -38.992 0 0 26.33 24.60 14.40 7574.1 MiB 123.27 27.3283 22.5689 3911.0 MiB 44.86 15.47 +stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 273.02 vpr 7.01 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7350572 13 740 25173 25306 1 12838 1890 117 87 10179 io auto 3006.8 MiB 37.42 599292 157888 1216610 423982 737752 54876 3977.7 MiB 30.17 0.24 14.8829 8.76456 -34576 -7.76456 8.70409 0.05 0.0816179 0.061816 10.1241 8.14491 194824 7.74156 42136 1.67432 66192 303102 47030761 4682931 0 0 2.57088e+08 25256.7 12 4146225 46138065 61038 9.03984 7.63094 -42209.6 -8.03984 0 0 32.63 17.95 9.14 7177.9 MiB 81.09 12.1021 9.70391 3977.7 MiB 45.61 23.31 +stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 200.36 vpr 6.67 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6988952 2 52 16673 16662 2 11970 759 37 27 999 LAB auto 2939.6 MiB 26.52 329275 182496 253339 66599 180853 5887 2975.1 MiB 13.24 0.15 8.48983 6.31912 -21812.1 -5.31912 5.08034 0.00 0.0629579 0.0470018 5.79269 4.52835 240918 14.4531 55334 3.31958 72352 385020 82634034 10266678 0 0 2.50403e+07 25065.4 19 1109231 11603273 35282 6.63264 5.37296 -26077.9 -5.63264 0 0 3.16 9.01 5.97 6825.1 MiB 80.01 7.98711 6.27754 2941.1 MiB 45.18 1.43 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 138.01 vpr 6.21 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6510184 13 29 26295 20086 1 12646 791 39 29 1131 LAB auto 2927.9 MiB 8.63 231619 75107 234775 43541 180854 10380 2952.5 MiB 7.46 0.10 5.55061 5.16398 -5504.03 -4.16398 2.86102 0.01 0.0337965 0.0307351 2.48103 2.06348 86091 3.27429 21138 0.803940 55083 69816 15088501 1963151 0 0 2.84316e+07 25138.5 14 1246298 12345793 14184 3.88416 2.98764 -5833.91 -2.88416 0 0 3.69 6.67 3.76 6357.2 MiB 59.58 3.41906 2.82928 2931.6 MiB 45.54 1.83 +stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 346.89 vpr 7.47 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7832876 542 422 37277 26038 1 20404 2145 147 109 16023 io auto 3028.2 MiB 42.13 995805 278436 1702989 641501 993647 67841 4655.2 MiB 55.90 0.45 15.3312 8.52855 -42700.6 -7.52855 8.52855 0.08 0.0906128 0.0733202 12.1681 9.84201 356776 9.57171 77090 2.06820 91226 273124 91865170 14105223 0 0 4.05150e+08 25285.5 18 5916678 66826775 49123 8.38836 8.09375 -49929.1 -7.38836 0 0 48.82 24.65 12.08 7648.9 MiB 99.97 15.4125 12.5496 4655.2 MiB 43.04 30.94 +stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 299.76 vpr 7.31 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7664032 403 704 15490 16194 1 8443 1837 167 124 20708 io auto 2928.3 MiB 31.79 580890 183895 1261389 465912 759977 35500 5134.5 MiB 17.64 0.16 21.2837 12.8498 -23740.4 -11.8498 6.01594 0.10 0.0512241 0.0393914 5.96074 4.75489 219953 14.2006 37215 2.40267 39483 211384 32469655 3103625 0 0 5.23918e+08 25300.3 17 6721158 74643089 37962 12.6526 5.87741 -32674.5 -11.6526 0 0 66.37 18.22 5.91 7484.0 MiB 79.20 7.59275 6.10237 5134.5 MiB 45.29 41.40 +stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 160.44 vpr 6.23 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6528224 18 17 16969 16357 1 6487 772 39 29 1131 LAB auto 2925.7 MiB 35.22 189359 78593 245032 60572 181809 2651 2959.4 MiB 7.11 0.10 11.1993 7.7388 -41982.4 -6.7388 7.7388 0.00 0.0307985 0.0270914 2.63105 2.05162 107149 6.31589 25659 1.51247 41788 165445 26862215 2865069 0 0 2.84316e+07 25138.5 14 1092494 12305361 43638 7.36438 7.36438 -43648.4 -6.36438 0 0 3.64 6.84 4.06 6375.2 MiB 59.12 3.5915 2.81489 2928.7 MiB 43.15 1.47 +stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 106.51 vpr 5.89 GiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6171076 18 17 2291 2142 1 1462 118 16 12 192 LAB M9K auto 2808.7 MiB 4.24 14517 10381 9366 1088 7475 803 2819.8 MiB 0.57 0.01 5.48653 5.31416 -4115.07 -4.31416 4.57209 0.00 0.00439936 0.00390185 0.191396 0.163419 13233 5.78365 3460 1.51224 7262 27758 4096440 441394 0 0 4.71840e+06 24575.0 14 154247 1512402 4624 4.15021 4.15021 -3988.57 -3.15021 0 0 0.67 1.23 0.84 6026.4 MiB 47.88 0.339888 0.292276 2809.1 MiB 45.05 0.08 From b6c3a3d90448ea9529f1f29f36afbcbbc9f1c5ef Mon Sep 17 00:00:00 2001 From: Mohamed Elgammal Date: Tue, 13 May 2025 15:44:18 -0400 Subject: [PATCH 117/176] add pointer to VTR9 paper in the readme --- README.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 75ad2239398..41afe56d4b3 100644 --- a/README.md +++ b/README.md @@ -36,15 +36,15 @@ See the [full license](LICENSE.md) for details. ## How to Cite The following paper may be used as a general citation for VTR: -K. E. Murray, O. Petelin, S. Zhong, J. M. Wang, M. ElDafrawy, J.-P. Legault, E. Sha, A. G. Graham, J. Wu, M. J. P. Walker, H. Zeng, P. Patros, J. Luu, K. B. Kent and V. Betz "VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling", ACM TRETS, 2020. +M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Kosar, K. Talaei, J. Fife, D. Khadivi, K. Murray, A. Boutros, K. B. Kent, J. Geoders, and V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration", ACM TRETS, 2025. Bibtex: ``` -@article{vtr8, - title={VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling}, - author={Murray, Kevin E. and Petelin, Oleg and Zhong, Sheng and Wang, Jai Min and ElDafrawy, Mohamed and Legault, Jean-Philippe and Sha, Eugene and Graham, Aaron G. and Wu, Jean and Walker, Matthew J. P. and Zeng, Hanqing and Patros, Panagiotis and Luu, Jason and Kent, Kenneth B. and Betz, Vaughn}, +@article{vtr9, + title={VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration}, + author={Elgammal, Mohamed A. and Mohaghegh, Amin and Shahrouz, Soheil G. and Mahmoudi, Fatemehsadat and Kosar, Fahrican and Talaei, Kimia and Fife, Joshua and Khadivi, Daniel and Murray, Kevin and Boutros, Andrew and Kent, Kenneth B. and Goeders, Jeff and Betz, Vaughn}, journal={ACM Trans. Reconfigurable Technol. Syst.}, - year={2020} + year={2025} } ``` From 0ea67006bd02a8a47fd72aeb2eddb3c1423bae63 Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Wed, 14 May 2025 11:34:56 -0400 Subject: [PATCH 118/176] Add documentation to explain which parts of VPR are parellel --- doc/src/vpr/command_line_usage.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 61dd775abb9..960aedc484c 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -223,6 +223,12 @@ General Options If this option is not specified it may be set from the ``VPR_NUM_WORKERS`` environment variable; otherwise the default is used. + If this option is set to something other than 1, the following algorithms can be run in parallel: + + * Timing Analysis + * Routing (If routing algorithm is set to parallel or parallel_decomp; See :option:`--router_algorithm`) + * Portions of analytical placement (If using the analytical placement flow and compiled VPR with Eigen enabled; See :option:`--analytical_place`) + .. note:: To compile VPR to allow the usage of parallel workers, ``libtbb-dev`` must be installed in the system. **Default:** ``1`` From d453bce2bab4841899e40345ce89d44837e1b4a7 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Wed, 14 May 2025 12:37:39 -0400 Subject: [PATCH 119/176] pass t_chan_width by reference --- vpr/src/route/rr_graph.cpp | 2 +- vpr/src/route/rr_graph2.cpp | 6 +++--- vpr/src/route/rr_graph2.h | 7 +++---- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 718a21ca9fb..a0957a76953 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1250,7 +1250,7 @@ static void build_rr_graph(e_graph_type graph_type, // Add routing resources to rr_graph lookup table alloc_and_load_rr_node_indices(device_ctx.rr_graph_builder, - &nodes_per_chan, + nodes_per_chan, grid, &num_rr_nodes, chan_details_x, diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 0c716b8dc3b..0a304f3b92f 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1441,7 +1441,7 @@ static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, /* As the rr_indices builders modify a local copy of indices, use the local copy in the builder */ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, const DeviceGrid& grid, int* index, const t_chan_details& chan_details_x, @@ -1464,9 +1464,9 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, load_block_rr_indices(rr_graph_builder, grid, index, is_flat); /* Load the data for x and y channels */ - load_chan_rr_indices(nodes_per_chan->x_max, grid, grid.width(), grid.height(), + load_chan_rr_indices(nodes_per_chan.x_max, grid, grid.width(), grid.height(), e_rr_type::CHANX, chan_details_x, rr_graph_builder, index); - load_chan_rr_indices(nodes_per_chan->y_max, grid, grid.height(), grid.width(), + load_chan_rr_indices(nodes_per_chan.y_max, grid, grid.height(), grid.width(), e_rr_type::CHANY, chan_details_y, rr_graph_builder, index); } diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h index b783e993d6b..4922ec70baa 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph2.h @@ -1,5 +1,5 @@ -#ifndef RR_GRAPH2_H -#define RR_GRAPH2_H +#pragma once + #include #include "build_switchblocks.h" @@ -15,7 +15,7 @@ /******************* Subroutines exported by rr_graph2.c *********************/ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, const DeviceGrid& grid, int* index, const t_chan_details& chan_details_x, @@ -252,4 +252,3 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map, FILE* fp); inline int get_chan_width(enum e_side side, const t_chan_width& nodes_per_channel); -#endif From b11be1322c6abc1160b7002e4f56b9066a811003 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Wed, 14 May 2025 12:43:07 -0400 Subject: [PATCH 120/176] doxygen comment for alloc_and_load_rr_node_indices --- vpr/src/route/rr_graph2.cpp | 4 ---- vpr/src/route/rr_graph2.h | 7 +++++++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 0a304f3b92f..07cc9f4ae9f 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1439,7 +1439,6 @@ static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, } } -/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder */ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_width& nodes_per_chan, const DeviceGrid& grid, @@ -1447,9 +1446,6 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, bool is_flat) { - /* Allocates and loads all the structures needed for fast lookups of the - * index of an rr_node. rr_node_indices is a matrix containing the index - * of the *first* rr_node at a given (i,j) location. */ /* Alloc the lookup table */ for (e_rr_type rr_type : RR_TYPES) { diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h index 4922ec70baa..55bf7304c94 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph2.h @@ -14,6 +14,12 @@ /******************* Subroutines exported by rr_graph2.c *********************/ +/** + * @brief Allocates and populates data structures for efficient rr_node index lookups. + * + * This function sets up the `rr_node_indices` structure, which maps a physical location + * and type to the index of the first corresponding rr_node. + */ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_width& nodes_per_chan, const DeviceGrid& grid, @@ -22,6 +28,7 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_y, bool is_flat); + /** * @brief allocates extra nodes within the RR graph to support 3D custom switch blocks for multi-die FPGAs * From 1a911ecfdbda28a65889b9a06d290409817fdf83 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Wed, 14 May 2025 12:57:34 -0400 Subject: [PATCH 121/176] add doxygen comments for load_block_rr_indices() --- libs/librrgraph/src/base/rr_spatial_lookup.cpp | 2 +- vpr/src/route/rr_graph2.cpp | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index aa9e17a1d5b..7606da19a84 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -338,7 +338,7 @@ void RRSpatialLookup::resize_nodes(int layer, || (x >= int(rr_node_indices_[type].dim_size(1))) || (y >= int(rr_node_indices_[type].dim_size(2))) || (size_t(side) >= rr_node_indices_[type].dim_size(3))) { - rr_node_indices_[type].resize({std::max(rr_node_indices_[type].dim_size(0),size_t(layer)+1), + rr_node_indices_[type].resize({std::max(rr_node_indices_[type].dim_size(0), size_t(layer)+1), std::max(rr_node_indices_[type].dim_size(1), size_t(x) + 1), std::max(rr_node_indices_[type].dim_size(2), size_t(y) + 1), std::max(rr_node_indices_[type].dim_size(3), size_t(side) + 1)}); diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 07cc9f4ae9f..63ed87fcb36 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -33,6 +33,18 @@ static void load_chan_rr_indices(const int max_chan_width, RRGraphBuilder& rr_graph_builder, int* index); +/** + * @brief Assigns and loads rr_node indices for block-level routing resources (SOURCE, SINK, IPIN, OPIN). + * + * This function walks through the device grid and assigns unique rr_node indices to the routing resources + * associated with each block (tiles). + * + * For SINKs and SOURCEs, it uses side 0 by convention (since they have no geometric side). For IPINs and OPINs, + * it determines the correct sides based on the tile's position in the grid, following special rules for + * edge and corner tiles. + * + * The index counter is passed and updated as rr_nodes are added. + */ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grid, int* index, @@ -1347,6 +1359,7 @@ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, } } } + static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, t_physical_tile_type_ptr physical_type_ptr, const std::vector& pin_num_vec, From a427f9cbd494bee40d10e74f4004485b1aef0e0f Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Tue, 13 May 2025 22:01:27 -0400 Subject: [PATCH 122/176] [AP][Solver] Enabled Parallel Eigen The Eigen solver has the ability to use OpenMP to run the solver computations in parallel. Made the AP flow use the num_workers option to set the number of threads that Eigen can use. VPR did not have the ability to build with OpenMP in its CMAKE. Added an option to the CMAKE to allow the user to enable OpenMP. --- vpr/CMakeLists.txt | 17 +++++++++++++++++ .../analytical_placement_flow.cpp | 1 + vpr/src/analytical_place/analytical_solver.cpp | 17 +++++++++++++++++ vpr/src/analytical_place/analytical_solver.h | 1 + vpr/src/analytical_place/global_placer.cpp | 4 ++++ vpr/src/analytical_place/global_placer.h | 2 ++ vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/vpr_types.h | 4 ++++ 8 files changed, 47 insertions(+) diff --git a/vpr/CMakeLists.txt b/vpr/CMakeLists.txt index 4e3ccc0b12c..67d9bcbd25c 100644 --- a/vpr/CMakeLists.txt +++ b/vpr/CMakeLists.txt @@ -12,6 +12,8 @@ set_property(CACHE VPR_PGO_CONFIG PROPERTY STRINGS prof_gen prof_use none) set(VPR_PGO_DATA_DIR "." CACHE PATH "Where to store and retrieve PGO data") +set(VPR_ENABLE_OPEN_MP "on" CACHE STRING "Enable OpenMP when compiling VPR") + #Handle graphics setup set(GRAPHICS_DEFINES "") @@ -295,6 +297,21 @@ else() message(FATAL_ERROR "VPR: Unrecognized execution engine '${VPR_USE_EXECUTION_ENGINE}'") endif() +# +# OpenMP configuration +# +if (VPR_ENABLE_OPEN_MP STREQUAL "on") + find_package(OpenMP) + if (OpenMP_CXX_FOUND) + target_link_libraries(libvpr OpenMP::OpenMP_CXX) + message(STATUS "OpenMP: Enabled") + else() + message(STATUS "OpenMP: Disabled (requested but not found)") + endif() +else() + message(STATUS "OpenMP: Disabled") +endif() + # # Signal handler configuration # diff --git a/vpr/src/analytical_place/analytical_placement_flow.cpp b/vpr/src/analytical_place/analytical_placement_flow.cpp index 1b0f3885559..cd07b601198 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.cpp +++ b/vpr/src/analytical_place/analytical_placement_flow.cpp @@ -144,6 +144,7 @@ static PartialPlacement run_global_placer(const t_ap_opts& ap_opts, device_ctx.physical_tile_types, pre_cluster_timing_manager, ap_opts.ap_timing_tradeoff, + ap_opts.num_threads, ap_opts.log_verbosity); return global_placer->place(); } diff --git a/vpr/src/analytical_place/analytical_solver.cpp b/vpr/src/analytical_place/analytical_solver.cpp index 2bc1ec19565..0c9467a3435 100644 --- a/vpr/src/analytical_place/analytical_solver.cpp +++ b/vpr/src/analytical_place/analytical_solver.cpp @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include "PreClusterTimingManager.h" @@ -32,6 +33,7 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wnull-dereference" +#include #include #include #include @@ -48,7 +50,22 @@ std::unique_ptr make_analytical_solver(e_ap_analytical_solver const AtomNetlist& atom_netlist, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity) { +#ifdef EIGEN_INSTALLED + // Set the number of threads that Eigen can use. + unsigned eigen_num_threads = num_threads; + if (num_threads == 0) { + eigen_num_threads = std::thread::hardware_concurrency(); + } + // Set the number of threads globally used by Eigen (if OpenMP is enabled). + // NOTE: Since this is a global update, all solvers will have this number + // of threads. + Eigen::setNbThreads(eigen_num_threads); +#else + (void)num_threads; +#endif // EIGEN_INSTALLED + // Based on the solver type passed in, build the solver. switch (solver_type) { case e_ap_analytical_solver::QP_Hybrid: diff --git a/vpr/src/analytical_place/analytical_solver.h b/vpr/src/analytical_place/analytical_solver.h index 2d748e2a493..2209349fdaf 100644 --- a/vpr/src/analytical_place/analytical_solver.h +++ b/vpr/src/analytical_place/analytical_solver.h @@ -138,6 +138,7 @@ std::unique_ptr make_analytical_solver(e_ap_analytical_solver const AtomNetlist& atom_netlist, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity); // The Eigen library is used to solve matrix equations in the following solvers. diff --git a/vpr/src/analytical_place/global_placer.cpp b/vpr/src/analytical_place/global_placer.cpp index d9131e85308..ebf506a3432 100644 --- a/vpr/src/analytical_place/global_placer.cpp +++ b/vpr/src/analytical_place/global_placer.cpp @@ -37,6 +37,7 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic const std::vector& physical_tile_types, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity) { return std::make_unique(analytical_solver_type, partial_legalizer_type, @@ -48,6 +49,7 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic physical_tile_types, pre_cluster_timing_manager, ap_timing_tradeoff, + num_threads, log_verbosity); } @@ -61,6 +63,7 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty const std::vector& physical_tile_types, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity) : GlobalPlacer(ap_netlist, log_verbosity) { // This can be a long method. Good to time this to see how long it takes to @@ -75,6 +78,7 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty atom_netlist, pre_cluster_timing_manager, ap_timing_tradeoff, + num_threads, log_verbosity_); // Build the density manager used by the partial legalizer. diff --git a/vpr/src/analytical_place/global_placer.h b/vpr/src/analytical_place/global_placer.h index 7772aa302bb..6b59484db65 100644 --- a/vpr/src/analytical_place/global_placer.h +++ b/vpr/src/analytical_place/global_placer.h @@ -83,6 +83,7 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic const std::vector& physical_tile_types, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity); /** @@ -148,6 +149,7 @@ class SimPLGlobalPlacer : public GlobalPlacer { const std::vector& physical_tile_types, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity); /** diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 25556636617..8bb61ac1149 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -559,6 +559,7 @@ void SetupAPOpts(const t_options& options, apOpts.detailed_placer_type = options.ap_detailed_placer.value(); apOpts.ap_timing_tradeoff = options.ap_timing_tradeoff.value(); apOpts.appack_max_dist_th = options.appack_max_dist_th.value(); + apOpts.num_threads = options.num_workers.value(); apOpts.log_verbosity = options.ap_verbosity.value(); } diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 8fc929ed06a..9974de549a0 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1116,6 +1116,8 @@ struct t_placer_opts { * @param appack_max_dist_th * Array of string passed by the user to configure the max candidate * distance thresholds. + * @param num_threads + * The number of threads the AP flow can use. * @param log_verbosity * The verbosity level of log messages in the AP flow, with higher * values leading to more verbose messages. @@ -1135,6 +1137,8 @@ struct t_ap_opts { std::vector appack_max_dist_th; + unsigned num_threads; + int log_verbosity; }; From 328efeeffb80d222e095d9f7295d66ca88bd5cce Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Wed, 14 May 2025 17:03:16 -0400 Subject: [PATCH 123/176] remove unused is_flat argument from alloc_and_load_rr_node_indices() and load_block_rr_indices() --- vpr/src/route/rr_graph.cpp | 3 +-- vpr/src/route/rr_graph2.cpp | 28 +++++++++++----------------- vpr/src/route/rr_graph2.h | 3 +-- 3 files changed, 13 insertions(+), 21 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index a0957a76953..9073fe24151 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1254,8 +1254,7 @@ static void build_rr_graph(e_graph_type graph_type, grid, &num_rr_nodes, chan_details_x, - chan_details_y, - is_flat); + chan_details_y); size_t expected_node_count = num_rr_nodes; if (clock_modeling == DEDICATED_NETWORK) { diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 63ed87fcb36..32c0401210d 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -47,8 +47,8 @@ static void load_chan_rr_indices(const int max_chan_width, */ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grid, - int* index, - bool is_flat); + int* index); + static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, t_physical_tile_type_ptr physical_type_ptr, @@ -1091,6 +1091,7 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map, } } } + static void load_chan_rr_indices(const int max_chan_width, const DeviceGrid& grid, const int chan_len, @@ -1106,11 +1107,12 @@ static void load_chan_rr_indices(const int max_chan_width, if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { continue; } + for (int chan = 0; chan < num_chans - 1; ++chan) { for (int seg = 1; seg < chan_len - 1; ++seg) { /* Assign an inode to the starts of tracks */ - int x = (type == e_rr_type::CHANX ? seg : chan); - int y = (type == e_rr_type::CHANX ? chan : seg); + int x = type == e_rr_type::CHANX ? seg : chan; + int y = type == e_rr_type::CHANX ? chan : seg; const t_chan_seg_details* seg_details = chan_details[x][y].data(); /* Reserve nodes in lookup to save memory */ @@ -1130,8 +1132,7 @@ static void load_chan_rr_indices(const int max_chan_width, std::swap(node_x, node_y); } - /* If the start of the wire doesn't have an inode, - * assign one to it. */ + // If the start of the wire doesn't have an inode, assign one to it. RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, node_x, node_y, type, track); if (!inode) { inode = RRNodeId(*index); @@ -1268,8 +1269,7 @@ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, */ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grid, - int* index, - bool /*is_flat*/) { + int* index) { //Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN for (int layer = 0; layer < grid.get_num_layers(); layer++) { for (int x = 0; x < (int)grid.width(); x++) { @@ -1457,20 +1457,14 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grid, int* index, const t_chan_details& chan_details_x, - const t_chan_details& chan_details_y, - bool is_flat) { - + const t_chan_details& chan_details_y) { /* Alloc the lookup table */ for (e_rr_type rr_type : RR_TYPES) { - if (rr_type == e_rr_type::CHANX) { - rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.height(), grid.width(), rr_type, NUM_2D_SIDES); - } else { - rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.width(), grid.height(), rr_type, NUM_2D_SIDES); - } + rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.width(), grid.height(), rr_type, NUM_2D_SIDES); } /* Assign indices for block nodes */ - load_block_rr_indices(rr_graph_builder, grid, index, is_flat); + load_block_rr_indices(rr_graph_builder, grid, index); /* Load the data for x and y channels */ load_chan_rr_indices(nodes_per_chan.x_max, grid, grid.width(), grid.height(), diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h index 55bf7304c94..066e63af0cd 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph2.h @@ -25,8 +25,7 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grid, int* index, const t_chan_details& chan_details_x, - const t_chan_details& chan_details_y, - bool is_flat); + const t_chan_details& chan_details_y); /** From a6c0049ac1630b9456993f10621f431179cf15a7 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Wed, 14 May 2025 18:05:19 -0400 Subject: [PATCH 124/176] use (x, y) convention for CHANX instead of (y, x) --- libs/librrgraph/src/base/rr_graph_builder.cpp | 14 +++--- .../librrgraph/src/base/rr_spatial_lookup.cpp | 40 ++++------------- vpr/src/route/clock_network_builders.cpp | 3 +- vpr/src/route/rr_graph.cpp | 5 +-- vpr/src/route/rr_graph2.cpp | 44 +++++++++---------- vpr/src/route/rr_graph2.h | 4 +- 6 files changed, 39 insertions(+), 71 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 48852706c52..4bf9680322a 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -31,31 +31,29 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { short node_layer = node_storage_.node_layer(node); short node_twist = node_storage_.node_ptc_twist(node); int node_offset = 0; + for (int ix = node_storage_.node_xlow(node); ix <= node_storage_.node_xhigh(node); ix++) { for (int iy = node_storage_.node_ylow(node); iy <= node_storage_.node_yhigh(node); iy++) { node_ptc_num += node_twist * node_offset; node_offset++; + switch (node_type) { case e_rr_type::SOURCE: case e_rr_type::SINK: case e_rr_type::CHANY: - node_lookup_.add_node(node, node_layer, ix, iy, node_type, node_ptc_num, TOTAL_2D_SIDES[0]); - break; case e_rr_type::CHANX: - /* Currently need to swap x and y for CHANX because of chan, seg convention - * TODO: Once the builders is reworked for use consistent (x, y) convention, - * the following swapping can be removed - */ - node_lookup_.add_node(node, node_layer, iy, ix, node_type, node_ptc_num, TOTAL_2D_SIDES[0]); + node_lookup_.add_node(node, node_layer, ix, iy, node_type, node_ptc_num, TOTAL_2D_SIDES[0]); break; + case e_rr_type::OPIN: case e_rr_type::IPIN: - for (const e_side& side : TOTAL_2D_SIDES) { + for (const e_side side : TOTAL_2D_SIDES) { if (node_storage_.is_node_on_specific_side(node, side)) { node_lookup_.add_node(node,node_layer, ix, iy, node_type, node_ptc_num, side); } } break; + default: VTR_LOG_ERROR("Invalid node type for node '%lu' in the routing resource graph file", size_t(node)); break; diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 7606da19a84..5faacf182e8 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -33,18 +33,6 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - /* Currently need to swap x and y for CHANX because of chan, seg convention - * This is due to that the fast look-up builders uses (y, x) coordinate when - * registering a CHANX node in the look-up - * TODO: Once the builders is reworked for use consistent (x, y) convention, - * the following swapping can be removed - */ - size_t node_x = x; - size_t node_y = y; - if (type == e_rr_type::CHANX) { - std::swap(node_x, node_y); - } - VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* Sanity check to ensure the layer, x, y, side and ptc are in range @@ -59,11 +47,11 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - if (node_x >= rr_node_indices_[type].dim_size(1)) { + if (x >= rr_node_indices_[type].dim_size(1)) { return RRNodeId::INVALID(); } - if(node_y >= rr_node_indices_[type].dim_size(2)){ + if(y >= rr_node_indices_[type].dim_size(2)){ return RRNodeId::INVALID(); } @@ -71,11 +59,11 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - if (size_t(ptc) >= rr_node_indices_[type][layer][node_x][node_y][node_side].size()) { + if (size_t(ptc) >= rr_node_indices_[type][layer][x][y][node_side].size()) { return RRNodeId::INVALID(); } - return rr_node_indices_[type][layer][node_x][node_y][node_side][ptc]; + return rr_node_indices_[type][layer][x][y][node_side][ptc]; } std::vector RRSpatialLookup::find_nodes_in_range(int layer, @@ -114,18 +102,6 @@ std::vector RRSpatialLookup::find_nodes(int layer, return nodes; } - /* Currently need to swap x and y for CHANX because of chan, seg convention - * This is due to that the fast look-up builders uses (y, x) coordinate when - * registering a CHANX node in the look-up - * TODO: Once the builders is reworked for use consistent (x, y) convention, - * the following swapping can be removed - */ - size_t node_x = x; - size_t node_y = y; - if (type == e_rr_type::CHANX) { - std::swap(node_x, node_y); - } - VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* Sanity check to ensure the x, y, side are in range @@ -140,11 +116,11 @@ std::vector RRSpatialLookup::find_nodes(int layer, return nodes; } - if (node_x >= rr_node_indices_[type].dim_size(1)) { + if (x >= rr_node_indices_[type].dim_size(1)) { return nodes; } - if(node_y >= rr_node_indices_[type].dim_size(2)){ + if(y >= rr_node_indices_[type].dim_size(2)){ return nodes; } @@ -154,14 +130,14 @@ std::vector RRSpatialLookup::find_nodes(int layer, /* Reserve space to avoid memory fragmentation */ size_t num_nodes = 0; - for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { + for (const auto& node : rr_node_indices_[type][layer][x][y][side]) { if (node.is_valid()) { num_nodes++; } } nodes.reserve(num_nodes); - for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { + for (const auto& node : rr_node_indices_[type][layer][x][y][side]) { if (node.is_valid()) { nodes.emplace_back(node); } diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/clock_network_builders.cpp index 9347cf28cd4..73932d99f3a 100644 --- a/vpr/src/route/clock_network_builders.cpp +++ b/vpr/src/route/clock_network_builders.cpp @@ -372,8 +372,7 @@ int ClockRib::create_chanx_wire(int layer, /* TODO: Will replace these codes with an API add_node_to_all_locs() of RRGraphBuilder */ for (int ix = rr_graph.node_xlow(chanx_node); ix <= rr_graph.node_xhigh(chanx_node); ++ix) { for (int iy = rr_graph.node_ylow(chanx_node); iy <= rr_graph.node_yhigh(chanx_node); ++iy) { - //TODO: CHANX uses odd swapped x/y indices here. Will rework once rr_node_indices is shadowed - rr_graph_builder.node_lookup().add_node(chanx_node, layer, iy, ix, rr_graph.node_type(chanx_node), rr_graph.node_track_num(chanx_node)); + rr_graph_builder.node_lookup().add_node(chanx_node, layer, ix, iy, rr_graph.node_type(chanx_node), rr_graph.node_track_num(chanx_node)); } } diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 9073fe24151..3f77949d96b 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1336,11 +1336,10 @@ static void build_rr_graph(e_graph_type graph_type, */ if (grid.get_num_layers() > 1 && sb_type == CUSTOM) { //keep how many nodes each switchblock requires for each x,y location - auto extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map, custom_3d_sb_fanin_fanout, device_ctx.rr_graph_builder); + vtr::NdMatrix extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map, custom_3d_sb_fanin_fanout, device_ctx.rr_graph_builder); //allocate new nodes in each switchblocks - alloc_and_load_inter_die_rr_node_indices(device_ctx.rr_graph_builder, &nodes_per_chan, grid, extra_nodes_per_switchblock, &num_rr_nodes); + alloc_and_load_inter_die_rr_node_indices(device_ctx.rr_graph_builder, nodes_per_chan, grid, extra_nodes_per_switchblock, &num_rr_nodes); device_ctx.rr_graph_builder.resize_nodes(num_rr_nodes); - extra_nodes_per_switchblock.clear(); } /* START IPIN MAP */ diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 32c0401210d..74576e692e5 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1103,19 +1103,19 @@ static void load_chan_rr_indices(const int max_chan_width, const auto& device_ctx = g_vpr_ctx.device(); for (int layer = 0; layer < grid.get_num_layers(); layer++) { - /* Skip the current die if architecture file specifies that it doesn't require global resource routing */ + // Skip the current die if architecture file specifies that it doesn't require global resource routing if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { continue; } for (int chan = 0; chan < num_chans - 1; ++chan) { for (int seg = 1; seg < chan_len - 1; ++seg) { - /* Assign an inode to the starts of tracks */ - int x = type == e_rr_type::CHANX ? seg : chan; - int y = type == e_rr_type::CHANX ? chan : seg; + // Assign an inode to the starts of tracks + const int x = (type == e_rr_type::CHANX) ? seg : chan; + const int y = (type == e_rr_type::CHANX) ? chan : seg; const t_chan_seg_details* seg_details = chan_details[x][y].data(); - /* Reserve nodes in lookup to save memory */ + // Reserve nodes in lookup to save memory rr_graph_builder.node_lookup().reserve_nodes(layer, chan, seg, type, max_chan_width); for (int track = 0; track < max_chan_width; ++track) { @@ -1124,24 +1124,19 @@ static void load_chan_rr_indices(const int max_chan_width, continue; int start = get_seg_start(seg_details, track, chan, seg); + int node_start_x = (type == e_rr_type::CHANX) ? start : chan; + int node_start_y = (type == e_rr_type::CHANX) ? chan : start; - /* TODO: Now we still use the (y, x) convention here for CHANX. Should rework later */ - int node_x = chan; - int node_y = start; - if (e_rr_type::CHANX == type) { - std::swap(node_x, node_y); - } - - // If the start of the wire doesn't have an inode, assign one to it. - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, node_x, node_y, type, track); + // If the start of the wire doesn't have an RRNodeId, assign one to it. + RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, node_start_x, node_start_y, type, track); if (!inode) { inode = RRNodeId(*index); ++(*index); rr_graph_builder.node_lookup().add_node(inode, layer, chan, start, type, track); } - /* Assign inode of start of wire to current position */ - rr_graph_builder.node_lookup().add_node(inode, layer, chan, seg, type, track); + // Assign RRNodeId of start of wire to current position + rr_graph_builder.node_lookup().add_node(inode, layer, x, y, type, track); } } } @@ -1219,7 +1214,7 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m } void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, const DeviceGrid& grid, const vtr::NdMatrix& extra_nodes_per_switchblock, int* index) { @@ -1232,31 +1227,32 @@ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, * 3) ptc = [max_chanx_width:max_chanx_width+number_of_connection-1] * 4) direction = NONE */ - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); for (int layer = 0; layer < grid.get_num_layers(); layer++) { /* Skip the current die if architecture file specifies that it doesn't have global resource routing */ if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { continue; } + for (size_t y = 0; y < grid.height() - 1; ++y) { for (size_t x = 1; x < grid.width() - 1; ++x) { - //count how many track-to-track connection go from current layer to other layers + // count how many track-to-track connection go from current layer to other layers int conn_count = extra_nodes_per_switchblock[x][y]; - //skip if no connection is required + // skip if no connection is required if (conn_count == 0) { continue; } - //reserve extra nodes for inter-die track-to-track connection - rr_graph_builder.node_lookup().reserve_nodes(layer, y, x, e_rr_type::CHANX, conn_count + nodes_per_chan->max); + // reserve extra nodes for inter-die track-to-track connection + rr_graph_builder.node_lookup().reserve_nodes(layer, x, y, e_rr_type::CHANX, conn_count + nodes_per_chan.max); for (int rr_node_offset = 0; rr_node_offset < conn_count; rr_node_offset++) { - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x, y, e_rr_type::CHANX, nodes_per_chan->max + rr_node_offset); + RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x, y, e_rr_type::CHANX, nodes_per_chan.max + rr_node_offset); if (!inode) { inode = RRNodeId(*index); ++(*index); - rr_graph_builder.node_lookup().add_node(inode, layer, y, x, e_rr_type::CHANX, nodes_per_chan->max + rr_node_offset); + rr_graph_builder.node_lookup().add_node(inode, layer, x, y, e_rr_type::CHANX, nodes_per_chan.max + rr_node_offset); } } } diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h index 066e63af0cd..2d058252387 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph2.h @@ -29,7 +29,7 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, /** - * @brief allocates extra nodes within the RR graph to support 3D custom switch blocks for multi-die FPGAs + * @brief Allocates extra nodes within the RR graph to support 3D custom switch blocks for multi-die FPGAs * * @param rr_graph_builder RRGraphBuilder data structure which allows data modification on a routing resource graph * @param nodes_per_chan number of tracks per channel (x, y) @@ -39,7 +39,7 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, * @param index RRNodeId that should be assigned to add a new RR node to the RR graph */ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, const DeviceGrid& grid, const vtr::NdMatrix& extra_nodes_per_switchblock, int* index); From da5ce31483354ade589ada44aec74ef199262084 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Wed, 14 May 2025 18:12:04 -0400 Subject: [PATCH 125/176] make format --- vpr/src/route/rr_graph2.cpp | 1 - vpr/src/route/rr_graph2.h | 1 - 2 files changed, 2 deletions(-) diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 74576e692e5..a389fbaf150 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -49,7 +49,6 @@ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grid, int* index); - static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, t_physical_tile_type_ptr physical_type_ptr, const std::vector& pin_num_vec, diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h index 2d058252387..99486512591 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph2.h @@ -27,7 +27,6 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y); - /** * @brief Allocates extra nodes within the RR graph to support 3D custom switch blocks for multi-die FPGAs * From 3f3a5a986a6cdefebdc0bd33d631e2dca81e9cff Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Wed, 14 May 2025 18:20:46 -0400 Subject: [PATCH 126/176] cast x/y to size_t --- libs/librrgraph/src/base/rr_spatial_lookup.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 5faacf182e8..3b661b1eeb6 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -47,11 +47,11 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - if (x >= rr_node_indices_[type].dim_size(1)) { + if (size_t(x) >= rr_node_indices_[type].dim_size(1)) { return RRNodeId::INVALID(); } - if(y >= rr_node_indices_[type].dim_size(2)){ + if (size_t(y) >= rr_node_indices_[type].dim_size(2)){ return RRNodeId::INVALID(); } From 052461dde10628274f4425727cc2179c5a3d698e Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Wed, 14 May 2025 18:22:45 -0400 Subject: [PATCH 127/176] get rid of warnings in RRSpatialLookup::find_nodes() --- libs/librrgraph/src/base/rr_spatial_lookup.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 3b661b1eeb6..d052936eb57 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -116,11 +116,11 @@ std::vector RRSpatialLookup::find_nodes(int layer, return nodes; } - if (x >= rr_node_indices_[type].dim_size(1)) { + if (size_t(x) >= rr_node_indices_[type].dim_size(1)) { return nodes; } - if(y >= rr_node_indices_[type].dim_size(2)){ + if (size_t(y) >= rr_node_indices_[type].dim_size(2)){ return nodes; } From ac721fdf2229807e55d8f49e15c4f506e401449a Mon Sep 17 00:00:00 2001 From: mohamedElgammal Date: Thu, 15 May 2025 00:45:43 -0400 Subject: [PATCH 128/176] Add references to the main VTR papers in the documentation. --- doc/src/zreferences.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/doc/src/zreferences.rst b/doc/src/zreferences.rst index 76df654a14a..3de491b7c5b 100644 --- a/doc/src/zreferences.rst +++ b/doc/src/zreferences.rst @@ -1,5 +1,18 @@ Publications & References ========================= +How to cite +----------- +`M. A. Elgammal`, `A. Mohaghegh`, `S. G. Shahrouz`, `F. Mahmoudi`, `F. Kosar`, `K. Talaei`, `J. Fife`, `D. Khadivi`, `K. Murray`, `A. Boutros`, `K. B. Kent`, `J. Geoders`, and `V. Betz`, "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration," *ACM TRETS*, 2025. + +Previous Publications +--------------------- +* `K. E. Murray`, `O. Petelin`, `S. Zhong`, `J. M. Wang`, `M. ElDafrawy`, `J.-P. Legault`, `E. Sha`, `A. G. Graham`, `J. Wu`, `M. J. P. Walker`, `H. Zeng`, `P. Patros`, `J. Luu`, `K. B. Kent` and `V. Betz`, "VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling", *ACM TRETS*, 2020. + +* `J. LUU`, `J. Geoders`, `M. Wainberg`, `A. Somerville`, `T. Yu`, `K. Nasartschuk`, `M. Nasr`, `S. Wang`, `T. L`, `N. Ahmed`, `K. B. Kent`, `J. Anderson`, `J. Rose`, `V. Betz`, "VTR 7.0: Next Generation Architecture and CAD System for FPGAs", *ACM TRETS*, 2014. + +References +---------- + .. bibliography:: z_references.bib :all: From 52f5a51a10003aa8d3f7deda4a9202db03f5e7ce Mon Sep 17 00:00:00 2001 From: mohamedElgammal Date: Thu, 15 May 2025 00:54:20 -0400 Subject: [PATCH 129/176] Add link to the VTR 9 paper in the documentation --- doc/src/zreferences.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/src/zreferences.rst b/doc/src/zreferences.rst index 3de491b7c5b..f8b63f4a901 100644 --- a/doc/src/zreferences.rst +++ b/doc/src/zreferences.rst @@ -3,7 +3,7 @@ Publications & References How to cite ----------- -`M. A. Elgammal`, `A. Mohaghegh`, `S. G. Shahrouz`, `F. Mahmoudi`, `F. Kosar`, `K. Talaei`, `J. Fife`, `D. Khadivi`, `K. Murray`, `A. Boutros`, `K. B. Kent`, `J. Geoders`, and `V. Betz`, "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration," *ACM TRETS*, 2025. +`M. A. Elgammal`, `A. Mohaghegh`, `S. G. Shahrouz`, `F. Mahmoudi`, `F. Kosar`, `K. Talaei`, `J. Fife`, `D. Khadivi`, `K. Murray`, `A. Boutros`, `K. B. Kent`, `J. Geoders`, and `V. Betz`, "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration," *ACM TRETS*, 2025. [`PDF `__] Previous Publications --------------------- From 76eb26fbc68a1c7d1cf92289d764f5fcd017a644 Mon Sep 17 00:00:00 2001 From: mohamedElgammal Date: Thu, 15 May 2025 00:56:42 -0400 Subject: [PATCH 130/176] Add link to the VTR 9 paper in the README --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 41afe56d4b3..21d5e02bc09 100644 --- a/README.md +++ b/README.md @@ -36,7 +36,7 @@ See the [full license](LICENSE.md) for details. ## How to Cite The following paper may be used as a general citation for VTR: -M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Kosar, K. Talaei, J. Fife, D. Khadivi, K. Murray, A. Boutros, K. B. Kent, J. Geoders, and V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration", ACM TRETS, 2025. +M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Kosar, K. Talaei, J. Fife, D. Khadivi, K. Murray, A. Boutros, K. B. Kent, J. Geoders, and V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration", ACM TRETS, 2025. [PDF](https://dl.acm.org/doi/epdf/10.1145/3734798) Bibtex: ``` From 095087738fc346eb99b1ceea04dfc3762bca790f Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Thu, 15 May 2025 11:03:41 -0400 Subject: [PATCH 131/176] add a closing ) to the text printed by node_coordinate_to_string() --- libs/librrgraph/src/base/rr_graph_view.h | 4 ++-- libs/librrgraph/src/base/rr_spatial_lookup.cpp | 9 +++------ libs/librrgraph/src/base/rr_spatial_lookup.h | 7 ++----- vpr/src/route/rr_graph2.cpp | 1 + 4 files changed, 8 insertions(+), 13 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index e420e46ddd8..49a3f92bf97 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -351,7 +351,7 @@ class RRGraphView { start_x = " (" + std::to_string(node_xhigh(node)) + ","; //start coordinates have large value start_y = std::to_string(node_yhigh(node)) + ","; - start_layer_str = std::to_string(node_layer_num); + start_layer_str = std::to_string(node_layer_num) + ")"; end_x = " (" + std::to_string(node_xlow(node)) + ","; //end coordinates have smaller value end_y = std::to_string(node_ylow(node)) + ","; end_layer_str = std::to_string(node_layer_num) + ")"; @@ -360,7 +360,7 @@ class RRGraphView { else { // signal travels in increasing direction, stays at same point, or can travel both directions start_x = " (" + std::to_string(node_xlow(node)) + ","; //start coordinates have smaller value start_y = std::to_string(node_ylow(node)) + ","; - start_layer_str = std::to_string(node_layer_num); + start_layer_str = std::to_string(node_layer_num) + ")"; end_x = " (" + std::to_string(node_xhigh(node)) + ","; //end coordinates have larger value end_y = std::to_string(node_yhigh(node)) + ","; end_layer_str = std::to_string(node_layer_num) + ")"; //layer number diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index d052936eb57..731dc147fde 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -1,9 +1,6 @@ #include "vtr_assert.h" #include "rr_spatial_lookup.h" -RRSpatialLookup::RRSpatialLookup() { -} - RRNodeId RRSpatialLookup::find_node(int layer, int x, int y, @@ -130,14 +127,14 @@ std::vector RRSpatialLookup::find_nodes(int layer, /* Reserve space to avoid memory fragmentation */ size_t num_nodes = 0; - for (const auto& node : rr_node_indices_[type][layer][x][y][side]) { + for (RRNodeId node : rr_node_indices_[type][layer][x][y][side]) { if (node.is_valid()) { num_nodes++; } } nodes.reserve(num_nodes); - for (const auto& node : rr_node_indices_[type][layer][x][y][side]) { + for (RRNodeId node : rr_node_indices_[type][layer][x][y][side]) { if (node.is_valid()) { nodes.emplace_back(node); } @@ -328,7 +325,7 @@ void RRSpatialLookup::reorder(const vtr::vector& dest_order) for (size_t x = 0; x < grid.dim_size(1); x++) { for (size_t y = 0; y < grid.dim_size(2); y++) { for (size_t s = 0; s < grid.dim_size(3); s++) { - for (auto &node: grid[l][x][y][s]) { + for (RRNodeId &node: grid[l][x][y][s]) { if (node.is_valid()) { node = dest_order[node]; } diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.h b/libs/librrgraph/src/base/rr_spatial_lookup.h index 1af0b6652af..c69f34b791a 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.h +++ b/libs/librrgraph/src/base/rr_spatial_lookup.h @@ -1,5 +1,4 @@ -#ifndef RR_SPATIAL_LOOKUP_H -#define RR_SPATIAL_LOOKUP_H +#pragma once /** * @file @@ -25,7 +24,7 @@ class RRSpatialLookup { /* -- Constructors -- */ public: /* Explicitly define the only way to create an object */ - explicit RRSpatialLookup(); + explicit RRSpatialLookup() = default; /* Disable copy constructors and copy assignment operator * This is to avoid accidental copy because it could be an expensive operation considering that the @@ -293,5 +292,3 @@ class RRSpatialLookup { /* Fast look-up: TODO: Should rework the data type. Currently it is based on a 3-dimensional array mater where some dimensions must always be accessed with a specific index. Such limitation should be overcome */ t_rr_node_indices rr_node_indices_; }; - -#endif diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index a389fbaf150..37d0a0bf0d2 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1547,6 +1547,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, } else { nodes_from_lookup = rr_graph.node_lookup().find_grid_nodes_at_all_sides(l, x, y, rr_type); } + for (RRNodeId inode : nodes_from_lookup) { rr_node_counts[inode]++; From cb8a3cb715dab5656eda5e95bed92609e8d8eb12 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Thu, 15 May 2025 11:21:19 -0400 Subject: [PATCH 132/176] fix the x/y mismatch for CHANX nodes in rr_nodes and rr_node_indices --- vpr/src/route/rr_graph2.cpp | 11 +---------- vpr/src/route/rr_graph2.h | 9 +++++++++ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 37d0a0bf0d2..d015533e0c5 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1131,7 +1131,7 @@ static void load_chan_rr_indices(const int max_chan_width, if (!inode) { inode = RRNodeId(*index); ++(*index); - rr_graph_builder.node_lookup().add_node(inode, layer, chan, start, type, track); + rr_graph_builder.node_lookup().add_node(inode, layer, node_start_x, node_start_y, type, track); } // Assign RRNodeId of start of wire to current position @@ -1516,15 +1516,6 @@ void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_build } } -/** - * Validate the node look-up matches all the node-level information - * in the storage of a routing resource graph - * This function will check the following aspects: - * - The type of each node matches its type that is indexed in the node look-up - * - For bounding box (xlow, ylow, xhigh, yhigh) of each node is indexable in the node look-up - * - The number of unique indexable nodes in the node look up matches the number of nodes in the storage - * This ensures that every node in the storage is indexable and there are no hidden nodes in the look-up - */ bool verify_rr_node_indices(const DeviceGrid& grid, const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h index 99486512591..05e723470e4 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph2.h @@ -56,6 +56,15 @@ void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_build const vtr::vector>& pin_chains_num, int* index); +/** + * Validate the node look-up matches all the node-level information + * in the storage of a routing resource graph + * This function will check the following aspects: + * - The type of each node matches its type that is indexed in the node look-up + * - For bounding box (xlow, ylow, xhigh, yhigh) of each node is indexable in the node look-up + * - The number of unique indexable nodes in the node look up matches the number of nodes in the storage + * This ensures that every node in the storage is indexable and there are no hidden nodes in the look-up + */ bool verify_rr_node_indices(const DeviceGrid& grid, const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, From 9297ad1edd56437f175ce2e9e9ad2dbed857ae80 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Thu, 15 May 2025 12:36:52 -0400 Subject: [PATCH 133/176] reserve nodes using x/y instead of chan/seg --- vpr/src/route/rr_graph2.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index d015533e0c5..7bc71b57a78 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1115,7 +1115,7 @@ static void load_chan_rr_indices(const int max_chan_width, const t_chan_seg_details* seg_details = chan_details[x][y].data(); // Reserve nodes in lookup to save memory - rr_graph_builder.node_lookup().reserve_nodes(layer, chan, seg, type, max_chan_width); + rr_graph_builder.node_lookup().reserve_nodes(layer, x, y, type, max_chan_width); for (int track = 0; track < max_chan_width; ++track) { /* TODO: May let the length() == 0 case go through, to model muxes */ From 5317468703742cf8551f431871e7656ef9ca8fd2 Mon Sep 17 00:00:00 2001 From: mohamedElgammal Date: Thu, 15 May 2025 13:09:40 -0400 Subject: [PATCH 134/176] fix a typo --- README.md | 2 +- doc/src/zreferences.rst | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 21d5e02bc09..da545289d0a 100644 --- a/README.md +++ b/README.md @@ -36,7 +36,7 @@ See the [full license](LICENSE.md) for details. ## How to Cite The following paper may be used as a general citation for VTR: -M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Kosar, K. Talaei, J. Fife, D. Khadivi, K. Murray, A. Boutros, K. B. Kent, J. Geoders, and V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration", ACM TRETS, 2025. [PDF](https://dl.acm.org/doi/epdf/10.1145/3734798) +M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Kosar, K. Talaei, J. Fife, D. Khadivi, K. Murray, A. Boutros, K. B. Kent, J. Goeders, and V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration", ACM TRETS, 2025. [PDF](https://dl.acm.org/doi/epdf/10.1145/3734798) Bibtex: ``` diff --git a/doc/src/zreferences.rst b/doc/src/zreferences.rst index f8b63f4a901..af178fe070a 100644 --- a/doc/src/zreferences.rst +++ b/doc/src/zreferences.rst @@ -3,13 +3,13 @@ Publications & References How to cite ----------- -`M. A. Elgammal`, `A. Mohaghegh`, `S. G. Shahrouz`, `F. Mahmoudi`, `F. Kosar`, `K. Talaei`, `J. Fife`, `D. Khadivi`, `K. Murray`, `A. Boutros`, `K. B. Kent`, `J. Geoders`, and `V. Betz`, "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration," *ACM TRETS*, 2025. [`PDF `__] +`M. A. Elgammal`, `A. Mohaghegh`, `S. G. Shahrouz`, `F. Mahmoudi`, `F. Kosar`, `K. Talaei`, `J. Fife`, `D. Khadivi`, `K. Murray`, `A. Boutros`, `K. B. Kent`, `J. Goeders`, and `V. Betz`, "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration," *ACM TRETS*, 2025. [`PDF `__] Previous Publications --------------------- * `K. E. Murray`, `O. Petelin`, `S. Zhong`, `J. M. Wang`, `M. ElDafrawy`, `J.-P. Legault`, `E. Sha`, `A. G. Graham`, `J. Wu`, `M. J. P. Walker`, `H. Zeng`, `P. Patros`, `J. Luu`, `K. B. Kent` and `V. Betz`, "VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling", *ACM TRETS*, 2020. -* `J. LUU`, `J. Geoders`, `M. Wainberg`, `A. Somerville`, `T. Yu`, `K. Nasartschuk`, `M. Nasr`, `S. Wang`, `T. L`, `N. Ahmed`, `K. B. Kent`, `J. Anderson`, `J. Rose`, `V. Betz`, "VTR 7.0: Next Generation Architecture and CAD System for FPGAs", *ACM TRETS*, 2014. +* `J. LUU`, `J. Goeders`, `M. Wainberg`, `A. Somerville`, `T. Yu`, `K. Nasartschuk`, `M. Nasr`, `S. Wang`, `T. L`, `N. Ahmed`, `K. B. Kent`, `J. Anderson`, `J. Rose`, `V. Betz`, "VTR 7.0: Next Generation Architecture and CAD System for FPGAs", *ACM TRETS*, 2014. References ---------- From 302efd4f4f776daab7aca1f09f95342037c8420b Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Thu, 15 May 2025 13:56:10 -0400 Subject: [PATCH 135/176] add rr_graph_genearion directory --- vpr/src/route/{ => rr_graph_generation}/build_switchblocks.cpp | 0 vpr/src/route/{ => rr_graph_generation}/build_switchblocks.h | 0 vpr/src/route/{ => rr_graph_generation}/cb_metrics.cpp | 0 vpr/src/route/{ => rr_graph_generation}/cb_metrics.h | 0 .../{ => rr_graph_generation}/clock_connection_builders.cpp | 0 .../{ => rr_graph_generation}/clock_connection_builders.h | 0 vpr/src/route/{ => rr_graph_generation}/clock_fwd.h | 0 .../route/{ => rr_graph_generation}/clock_network_builders.cpp | 0 .../route/{ => rr_graph_generation}/clock_network_builders.h | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph.cpp | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph.h | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph2.cpp | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph2.h | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph_area.cpp | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph_area.h | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph_clock.cpp | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph_clock.h | 0 .../route/{ => rr_graph_generation}/rr_graph_indexed_data.cpp | 0 .../route/{ => rr_graph_generation}/rr_graph_indexed_data.h | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph_sbox.cpp | 0 vpr/src/route/{ => rr_graph_generation}/rr_graph_sbox.h | 0 .../route/{ => rr_graph_generation}/rr_graph_timing_params.cpp | 0 .../route/{ => rr_graph_generation}/rr_graph_timing_params.h | 0 vpr/src/route/{ => rr_graph_generation}/rr_types.h | 3 ++- 24 files changed, 2 insertions(+), 1 deletion(-) rename vpr/src/route/{ => rr_graph_generation}/build_switchblocks.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/build_switchblocks.h (100%) rename vpr/src/route/{ => rr_graph_generation}/cb_metrics.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/cb_metrics.h (100%) rename vpr/src/route/{ => rr_graph_generation}/clock_connection_builders.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/clock_connection_builders.h (100%) rename vpr/src/route/{ => rr_graph_generation}/clock_fwd.h (100%) rename vpr/src/route/{ => rr_graph_generation}/clock_network_builders.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/clock_network_builders.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph2.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph2.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_area.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_area.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_clock.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_clock.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_indexed_data.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_indexed_data.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_sbox.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_sbox.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_timing_params.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_timing_params.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_types.h (99%) diff --git a/vpr/src/route/build_switchblocks.cpp b/vpr/src/route/rr_graph_generation/build_switchblocks.cpp similarity index 100% rename from vpr/src/route/build_switchblocks.cpp rename to vpr/src/route/rr_graph_generation/build_switchblocks.cpp diff --git a/vpr/src/route/build_switchblocks.h b/vpr/src/route/rr_graph_generation/build_switchblocks.h similarity index 100% rename from vpr/src/route/build_switchblocks.h rename to vpr/src/route/rr_graph_generation/build_switchblocks.h diff --git a/vpr/src/route/cb_metrics.cpp b/vpr/src/route/rr_graph_generation/cb_metrics.cpp similarity index 100% rename from vpr/src/route/cb_metrics.cpp rename to vpr/src/route/rr_graph_generation/cb_metrics.cpp diff --git a/vpr/src/route/cb_metrics.h b/vpr/src/route/rr_graph_generation/cb_metrics.h similarity index 100% rename from vpr/src/route/cb_metrics.h rename to vpr/src/route/rr_graph_generation/cb_metrics.h diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp similarity index 100% rename from vpr/src/route/clock_connection_builders.cpp rename to vpr/src/route/rr_graph_generation/clock_connection_builders.cpp diff --git a/vpr/src/route/clock_connection_builders.h b/vpr/src/route/rr_graph_generation/clock_connection_builders.h similarity index 100% rename from vpr/src/route/clock_connection_builders.h rename to vpr/src/route/rr_graph_generation/clock_connection_builders.h diff --git a/vpr/src/route/clock_fwd.h b/vpr/src/route/rr_graph_generation/clock_fwd.h similarity index 100% rename from vpr/src/route/clock_fwd.h rename to vpr/src/route/rr_graph_generation/clock_fwd.h diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/rr_graph_generation/clock_network_builders.cpp similarity index 100% rename from vpr/src/route/clock_network_builders.cpp rename to vpr/src/route/rr_graph_generation/clock_network_builders.cpp diff --git a/vpr/src/route/clock_network_builders.h b/vpr/src/route/rr_graph_generation/clock_network_builders.h similarity index 100% rename from vpr/src/route/clock_network_builders.h rename to vpr/src/route/rr_graph_generation/clock_network_builders.h diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph_generation/rr_graph.cpp similarity index 100% rename from vpr/src/route/rr_graph.cpp rename to vpr/src/route/rr_graph_generation/rr_graph.cpp diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph_generation/rr_graph.h similarity index 100% rename from vpr/src/route/rr_graph.h rename to vpr/src/route/rr_graph_generation/rr_graph.h diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph_generation/rr_graph2.cpp similarity index 100% rename from vpr/src/route/rr_graph2.cpp rename to vpr/src/route/rr_graph_generation/rr_graph2.cpp diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph_generation/rr_graph2.h similarity index 100% rename from vpr/src/route/rr_graph2.h rename to vpr/src/route/rr_graph_generation/rr_graph2.h diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_generation/rr_graph_area.cpp similarity index 100% rename from vpr/src/route/rr_graph_area.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_area.cpp diff --git a/vpr/src/route/rr_graph_area.h b/vpr/src/route/rr_graph_generation/rr_graph_area.h similarity index 100% rename from vpr/src/route/rr_graph_area.h rename to vpr/src/route/rr_graph_generation/rr_graph_area.h diff --git a/vpr/src/route/rr_graph_clock.cpp b/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp similarity index 100% rename from vpr/src/route/rr_graph_clock.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_clock.cpp diff --git a/vpr/src/route/rr_graph_clock.h b/vpr/src/route/rr_graph_generation/rr_graph_clock.h similarity index 100% rename from vpr/src/route/rr_graph_clock.h rename to vpr/src/route/rr_graph_generation/rr_graph_clock.h diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.cpp similarity index 100% rename from vpr/src/route/rr_graph_indexed_data.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_indexed_data.cpp diff --git a/vpr/src/route/rr_graph_indexed_data.h b/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.h similarity index 100% rename from vpr/src/route/rr_graph_indexed_data.h rename to vpr/src/route/rr_graph_generation/rr_graph_indexed_data.h diff --git a/vpr/src/route/rr_graph_sbox.cpp b/vpr/src/route/rr_graph_generation/rr_graph_sbox.cpp similarity index 100% rename from vpr/src/route/rr_graph_sbox.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_sbox.cpp diff --git a/vpr/src/route/rr_graph_sbox.h b/vpr/src/route/rr_graph_generation/rr_graph_sbox.h similarity index 100% rename from vpr/src/route/rr_graph_sbox.h rename to vpr/src/route/rr_graph_generation/rr_graph_sbox.h diff --git a/vpr/src/route/rr_graph_timing_params.cpp b/vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp similarity index 100% rename from vpr/src/route/rr_graph_timing_params.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp diff --git a/vpr/src/route/rr_graph_timing_params.h b/vpr/src/route/rr_graph_generation/rr_graph_timing_params.h similarity index 100% rename from vpr/src/route/rr_graph_timing_params.h rename to vpr/src/route/rr_graph_generation/rr_graph_timing_params.h diff --git a/vpr/src/route/rr_types.h b/vpr/src/route/rr_graph_generation/rr_types.h similarity index 99% rename from vpr/src/route/rr_types.h rename to vpr/src/route/rr_graph_generation/rr_types.h index 8e093faca75..620427a2d11 100644 --- a/vpr/src/route/rr_types.h +++ b/vpr/src/route/rr_graph_generation/rr_types.h @@ -1,5 +1,6 @@ #ifndef RR_TYPES_H #define RR_TYPES_H + #include #include "vtr_ndmatrix.h" @@ -14,7 +15,7 @@ typedef std::vector, 5>> t_pin_to_track_lookup; -/* AA: t_pin_to_track_lookup is alloacted first and is then converted to t_track_to_pin lookup by simply redefining the accessing order. +/* AA: t_pin_to_track_lookup is alloacted first and is then converted to t_track_to_pin lookup by simply redefining the accessing order. * As a result, the matrix should be accessed as follow as a result after allocation in rr_graph.cpp: alloc_track_to_pin_lookup (used by unidir and bidir) * [0..device_ctx.physical_tile_types.size()-1][0..max_chan_width-1][0..width][0..height][0..layer-1][0..3] * From 9017ac1af8e42d7d1aaec5d0a0ff822385339d3f Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Thu, 15 May 2025 14:10:02 -0400 Subject: [PATCH 136/176] resize node lookup for CHANX nodes in RR graph serializer --- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 1ee3676dda4..fe3f5a66930 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1848,16 +1848,11 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { /* Alloc the lookup table */ for (e_rr_type rr_type : RR_TYPES) { - if (rr_type == e_rr_type::CHANX) { - rr_graph_builder.node_lookup().resize_nodes(grid_.get_num_layers(), grid_.height(), grid_.width(), rr_type, NUM_2D_SIDES); - } else { - rr_graph_builder.node_lookup().resize_nodes(grid_.get_num_layers(), grid_.width(), grid_.height(), rr_type, NUM_2D_SIDES); - } + rr_graph_builder.node_lookup().resize_nodes(grid_.get_num_layers(), grid_.width(), grid_.height(), rr_type, NUM_2D_SIDES); } /* Add the correct node into the vector */ - for (size_t inode = 0; inode < rr_nodes_->size(); inode++) { - auto node = (*rr_nodes_)[inode]; + for (const t_rr_node& node : *rr_nodes_) { rr_graph_builder.add_node_to_all_locs(node.id()); } } From 0cb4c48f5e3e580c724b8ff0b906255a10150cba Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Thu, 15 May 2025 14:34:36 -0400 Subject: [PATCH 137/176] add rr_node_indices.cpp/.h --- .../route/rr_graph_generation/rr_graph.cpp | 1 + .../route/rr_graph_generation/rr_graph2.cpp | 598 +---------------- vpr/src/route/rr_graph_generation/rr_graph2.h | 56 -- .../rr_graph_generation/rr_node_indices.cpp | 600 ++++++++++++++++++ .../rr_graph_generation/rr_node_indices.h | 66 ++ 5 files changed, 669 insertions(+), 652 deletions(-) create mode 100644 vpr/src/route/rr_graph_generation/rr_node_indices.cpp create mode 100644 vpr/src/route/rr_graph_generation/rr_node_indices.h diff --git a/vpr/src/route/rr_graph_generation/rr_graph.cpp b/vpr/src/route/rr_graph_generation/rr_graph.cpp index 3f77949d96b..b993ed7ded5 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph.cpp @@ -33,6 +33,7 @@ #include "edge_groups.h" #include "rr_graph_builder.h" #include "rr_types.h" +#include "rr_node_indices.h" //#define VERBOSE //used for getting the exact count of each edge type and printing it to std out. diff --git a/vpr/src/route/rr_graph_generation/rr_graph2.cpp b/vpr/src/route/rr_graph_generation/rr_graph2.cpp index 7bc71b57a78..a703bad0418 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph2.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph2.cpp @@ -1,6 +1,5 @@ #include -#include "describe_rr_node.h" #include "physical_types_util.h" #include "vtr_util.h" #include "vtr_assert.h" @@ -24,52 +23,8 @@ static void get_switch_type(bool is_from_sb, const int switch_override, short switch_types[2]); -static void load_chan_rr_indices(const int max_chan_width, - const DeviceGrid& grid, - const int chan_len, - const int num_chans, - const e_rr_type type, - const t_chan_details& chan_details, - RRGraphBuilder& rr_graph_builder, - int* index); - -/** - * @brief Assigns and loads rr_node indices for block-level routing resources (SOURCE, SINK, IPIN, OPIN). - * - * This function walks through the device grid and assigns unique rr_node indices to the routing resources - * associated with each block (tiles). - * - * For SINKs and SOURCEs, it uses side 0 by convention (since they have no geometric side). For IPINs and OPINs, - * it determines the correct sides based on the tile's position in the grid, following special rules for - * edge and corner tiles. - * - * The index counter is passed and updated as rr_nodes are added. - */ -static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grid, - int* index); - -static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_type_ptr, - const std::vector& pin_num_vec, - int layer, - int root_x, - int root_y, - int* index, - const std::vector& wanted_sides); - -static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_type_ptr, - const std::vector& class_num_vec, - int layer, - int x, - int y, - int block_width, - int block_height, - int* index); - static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, - const std::vector conn_tracks, + const std::vector& conn_tracks, const int layer, const int to_chan, const int to_seg, @@ -1091,57 +1046,6 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map, } } -static void load_chan_rr_indices(const int max_chan_width, - const DeviceGrid& grid, - const int chan_len, - const int num_chans, - const e_rr_type type, - const t_chan_details& chan_details, - RRGraphBuilder& rr_graph_builder, - int* index) { - const auto& device_ctx = g_vpr_ctx.device(); - - for (int layer = 0; layer < grid.get_num_layers(); layer++) { - // Skip the current die if architecture file specifies that it doesn't require global resource routing - if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { - continue; - } - - for (int chan = 0; chan < num_chans - 1; ++chan) { - for (int seg = 1; seg < chan_len - 1; ++seg) { - // Assign an inode to the starts of tracks - const int x = (type == e_rr_type::CHANX) ? seg : chan; - const int y = (type == e_rr_type::CHANX) ? chan : seg; - const t_chan_seg_details* seg_details = chan_details[x][y].data(); - - // Reserve nodes in lookup to save memory - rr_graph_builder.node_lookup().reserve_nodes(layer, x, y, type, max_chan_width); - - for (int track = 0; track < max_chan_width; ++track) { - /* TODO: May let the length() == 0 case go through, to model muxes */ - if (seg_details[track].length() <= 0) - continue; - - int start = get_seg_start(seg_details, track, chan, seg); - int node_start_x = (type == e_rr_type::CHANX) ? start : chan; - int node_start_y = (type == e_rr_type::CHANX) ? chan : start; - - // If the start of the wire doesn't have an RRNodeId, assign one to it. - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, node_start_x, node_start_y, type, track); - if (!inode) { - inode = RRNodeId(*index); - ++(*index); - rr_graph_builder.node_lookup().add_node(inode, layer, node_start_x, node_start_y, type, track); - } - - // Assign RRNodeId of start of wire to current position - rr_graph_builder.node_lookup().add_node(inode, layer, x, y, type, track); - } - } - } - } -} - static bool is_sb_conn_layer_crossing(enum e_side src_side, enum e_side dest_side) { if (src_side < NUM_2D_SIDES && dest_side < NUM_2D_SIDES) { return false; @@ -1212,471 +1116,6 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m return extra_nodes_per_switchblocks; } -void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width& nodes_per_chan, - const DeviceGrid& grid, - const vtr::NdMatrix& extra_nodes_per_switchblock, - int* index) { - /* - * In case of multi-die FPGAs, we add extra nodes (could have used either CHANX or CHANY; we chose to use all CHANX) to - * support inter-die communication coming from switch blocks (connection between two tracks in different layers) - * The extra nodes have the following attribute: - * 1) type = CHANX - * 2) length = 0 (xhigh = xlow, yhigh = ylow) - * 3) ptc = [max_chanx_width:max_chanx_width+number_of_connection-1] - * 4) direction = NONE - */ - const auto& device_ctx = g_vpr_ctx.device(); - - for (int layer = 0; layer < grid.get_num_layers(); layer++) { - /* Skip the current die if architecture file specifies that it doesn't have global resource routing */ - if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { - continue; - } - - for (size_t y = 0; y < grid.height() - 1; ++y) { - for (size_t x = 1; x < grid.width() - 1; ++x) { - // count how many track-to-track connection go from current layer to other layers - int conn_count = extra_nodes_per_switchblock[x][y]; - - // skip if no connection is required - if (conn_count == 0) { - continue; - } - - // reserve extra nodes for inter-die track-to-track connection - rr_graph_builder.node_lookup().reserve_nodes(layer, x, y, e_rr_type::CHANX, conn_count + nodes_per_chan.max); - for (int rr_node_offset = 0; rr_node_offset < conn_count; rr_node_offset++) { - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x, y, e_rr_type::CHANX, nodes_per_chan.max + rr_node_offset); - if (!inode) { - inode = RRNodeId(*index); - ++(*index); - rr_graph_builder.node_lookup().add_node(inode, layer, x, y, e_rr_type::CHANX, nodes_per_chan.max + rr_node_offset); - } - } - } - } - } -} - -/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder - * TODO: these building functions should only talk to a RRGraphBuilder object - */ -static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grid, - int* index) { - //Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN - for (int layer = 0; layer < grid.get_num_layers(); layer++) { - for (int x = 0; x < (int)grid.width(); x++) { - for (int y = 0; y < (int)grid.height(); y++) { - //Process each block from its root location - if (grid.is_root_location({x, y, layer})) { - t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); - - //Assign indices for SINKs and SOURCEs - // Note that SINKS/SOURCES have no side, so we always use side 0 - std::vector class_num_vec = get_tile_root_classes(physical_type); - std::vector pin_num_vec = get_tile_root_pins(physical_type); - - add_classes_spatial_lookup(rr_graph_builder, - physical_type, - class_num_vec, - layer, - x, - y, - physical_type->width, - physical_type->height, - index); - - /* Limited sides for grids - * The wanted side depends on the location of the grid. - * In particular for perimeter grid, - * ------------------------------------------------------- - * Grid location | IPIN side - * ------------------------------------------------------- - * TOP | BOTTOM - * ------------------------------------------------------- - * RIGHT | LEFT - * ------------------------------------------------------- - * BOTTOM | TOP - * ------------------------------------------------------- - * LEFT | RIGHT - * ------------------------------------------------------- - * TOP-LEFT | BOTTOM & RIGHT - * ------------------------------------------------------- - * TOP-RIGHT | BOTTOM & LEFT - * ------------------------------------------------------- - * BOTTOM-LEFT | TOP & RIGHT - * ------------------------------------------------------- - * BOTTOM-RIGHT | TOP & LEFT - * ------------------------------------------------------- - * Other | First come first fit - * ------------------------------------------------------- - * - * Special for IPINs: - * If there are multiple wanted sides, first come first fit is applied - * This guarantee that there is only a unique rr_node - * for the same input pin on multiple sides, and thus avoid multiple driver problems - */ - std::vector wanted_sides; - if ((int)grid.height() - 1 == y) { /* TOP side */ - wanted_sides.push_back(BOTTOM); - } - if ((int)grid.width() - 1 == x) { /* RIGHT side */ - wanted_sides.push_back(LEFT); - } - if (0 == y) { /* BOTTOM side */ - wanted_sides.push_back(TOP); - } - if (0 == x) { /* LEFT side */ - wanted_sides.push_back(RIGHT); - } - - /* If wanted sides is empty still, this block does not have specific wanted sides, - * Deposit all the sides - */ - if (wanted_sides.empty()) { - for (e_side side : TOTAL_2D_SIDES) { - wanted_sides.push_back(side); - } - } - - add_pins_spatial_lookup(rr_graph_builder, - physical_type, - pin_num_vec, - layer, - x, - y, - index, - wanted_sides); - } - } - } - } -} - -static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_type_ptr, - const std::vector& pin_num_vec, - int layer, - int root_x, - int root_y, - int* index, - const std::vector& wanted_sides) { - for (e_side side : wanted_sides) { - for (int width_offset = 0; width_offset < physical_type_ptr->width; ++width_offset) { - int x_tile = root_x + width_offset; - for (int height_offset = 0; height_offset < physical_type_ptr->height; ++height_offset) { - int y_tile = root_y + height_offset; - //only nodes on the tile may be located in a location other than the root-location - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::OPIN, physical_type_ptr->num_pins, side); - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::IPIN, physical_type_ptr->num_pins, side); - } - } - } - - for (const int pin_num : pin_num_vec) { - bool assigned_to_rr_node = false; - const auto [x_offset, y_offset, pin_sides] = get_pin_coordinates(physical_type_ptr, pin_num, wanted_sides); - e_pin_type pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); - for (int pin_coord_idx = 0; pin_coord_idx < (int)pin_sides.size(); pin_coord_idx++) { - int x_tile = root_x + x_offset[pin_coord_idx]; - int y_tile = root_y + y_offset[pin_coord_idx]; - e_side side = pin_sides[pin_coord_idx]; - if (pin_type == DRIVER) { - rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::OPIN, pin_num, side); - assigned_to_rr_node = true; - } else { - VTR_ASSERT(pin_type == RECEIVER); - rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::IPIN, pin_num, side); - assigned_to_rr_node = true; - } - } - /* A pin may locate on multiple sides of a tile. - * Instead of allocating multiple rr_nodes for the pin, - * we just create a rr_node and make it indexable on these sides - * As such, we can avoid redundant rr_node to be allocated - * and multiple nets to be mapped to the pin - * - * Considering that some pin could be just dangling, we do not need - * to create a void rr_node for it. - * As such, we only allocate a rr node when the pin is indeed located - * on at least one side - */ - if (assigned_to_rr_node) { - ++(*index); - } - } -} - -static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_type_ptr, - const std::vector& class_num_vec, - int layer, - int root_x, - int root_y, - int block_width, - int block_height, - int* index) { - for (int x_tile = root_x; x_tile < (root_x + block_width); x_tile++) { - for (int y_tile = root_y; y_tile < (root_y + block_height); y_tile++) { - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::SOURCE, class_num_vec.size(), TOTAL_2D_SIDES[0]); - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::SINK, class_num_vec.size(), TOTAL_2D_SIDES[0]); - } - } - - for (const int class_num : class_num_vec) { - e_pin_type class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); - e_rr_type node_type = e_rr_type::SINK; - if (class_type == DRIVER) { - node_type = e_rr_type::SOURCE; - } else { - VTR_ASSERT(class_type == RECEIVER); - } - - for (int x_offset = 0; x_offset < block_width; x_offset++) { - for (int y_offset = 0; y_offset < block_height; y_offset++) { - int curr_x = root_x + x_offset; - int curr_y = root_y + y_offset; - - rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, curr_x, curr_y, node_type, class_num); - } - } - - ++(*index); - } -} - -void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width& nodes_per_chan, - const DeviceGrid& grid, - int* index, - const t_chan_details& chan_details_x, - const t_chan_details& chan_details_y) { - /* Alloc the lookup table */ - for (e_rr_type rr_type : RR_TYPES) { - rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.width(), grid.height(), rr_type, NUM_2D_SIDES); - } - - /* Assign indices for block nodes */ - load_block_rr_indices(rr_graph_builder, grid, index); - - /* Load the data for x and y channels */ - load_chan_rr_indices(nodes_per_chan.x_max, grid, grid.width(), grid.height(), - e_rr_type::CHANX, chan_details_x, rr_graph_builder, index); - load_chan_rr_indices(nodes_per_chan.y_max, grid, grid.height(), grid.width(), - e_rr_type::CHANY, chan_details_y, rr_graph_builder, index); -} - -void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grid, - const vtr::vector& pin_chains, - const vtr::vector>& pin_chains_num, - int* index) { - for (int layer = 0; layer < grid.get_num_layers(); layer++) { - for (int x = 0; x < (int)grid.width(); x++) { - for (int y = 0; y < (int)grid.height(); y++) { - //Process each block from its root location - if (grid.is_root_location({x, y, layer})) { - t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); - //Assign indices for SINKs and SOURCEs - // Note that SINKS/SOURCES have no side, so we always use side 0 - std::vector class_num_vec; - std::vector pin_num_vec; - class_num_vec = get_cluster_netlist_intra_tile_classes_at_loc(layer, x, y, physical_type); - pin_num_vec = get_cluster_netlist_intra_tile_pins_at_loc(layer, - x, - y, - pin_chains, - pin_chains_num, - physical_type); - add_classes_spatial_lookup(rr_graph_builder, - physical_type, - class_num_vec, - layer, - x, - y, - physical_type->width, - physical_type->height, - index); - - std::vector wanted_sides; - wanted_sides.push_back(e_side::TOP); - add_pins_spatial_lookup(rr_graph_builder, - physical_type, - pin_num_vec, - layer, - x, - y, - index, - wanted_sides); - } - } - } - } -} - -bool verify_rr_node_indices(const DeviceGrid& grid, - const RRGraphView& rr_graph, - const vtr::vector& rr_indexed_data, - const t_rr_graph_storage& rr_nodes, - bool is_flat) { - std::unordered_map rr_node_counts; - - int width = grid.width(); - int height = grid.height(); - int layer = grid.get_num_layers(); - - for (int l = 0; l < layer; ++l) { - for (int x = 0; x < width; ++x) { - for (int y = 0; y < height; ++y) { - for (e_rr_type rr_type : RR_TYPES) { - /* Get the list of nodes at a specific location (x, y) */ - std::vector nodes_from_lookup; - if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { - nodes_from_lookup = rr_graph.node_lookup().find_channel_nodes(l, x, y, rr_type); - } else { - nodes_from_lookup = rr_graph.node_lookup().find_grid_nodes_at_all_sides(l, x, y, rr_type); - } - - for (RRNodeId inode : nodes_from_lookup) { - rr_node_counts[inode]++; - - if (rr_graph.node_type(inode) != rr_type) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node type does not match between rr_nodes and rr_node_indices (%s/%s): %s", - rr_node_typename[rr_graph.node_type(inode)], - rr_node_typename[rr_type], - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - - if (rr_graph.node_type(inode) == e_rr_type::CHANX) { - VTR_ASSERT_MSG(rr_graph.node_ylow(inode) == rr_graph.node_yhigh(inode), "CHANX should be horizontal"); - if (y != rr_graph.node_ylow(inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node y position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", - rr_graph.node_ylow(inode), - y, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - - if (!rr_graph.x_in_node_range(x, inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", - rr_graph.node_xlow(inode), - rr_graph.node_xlow(inode), - x, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - } else if (rr_graph.node_type(inode) == e_rr_type::CHANY) { - VTR_ASSERT_MSG(rr_graph.node_xlow(inode) == rr_graph.node_xhigh(inode), "CHANY should be vertical"); - - if (x != rr_graph.node_xlow(inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node x position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", - rr_graph.node_xlow(inode), - x, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - - if (!rr_graph.y_in_node_range(y, inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node y positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", - rr_graph.node_ylow(inode), - rr_graph.node_ylow(inode), - y, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { - // Sources have co-ordinates covering the entire block they are in, but not sinks - if (!rr_graph.x_in_node_range(x, inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", - rr_graph.node_xlow(inode), - rr_graph.node_xlow(inode), - x, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - - if (!rr_graph.y_in_node_range(y, inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node y positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", - rr_graph.node_ylow(inode), - rr_graph.node_ylow(inode), - y, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - } else { - VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::IPIN || rr_graph.node_type(inode) == e_rr_type::OPIN); - /* As we allow a pin to be indexable on multiple sides, - * This check code should be invalid - * if (rr_node.xlow() != x) { - * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%d/%d): %s", - * rr_node.xlow(), - * x, - * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); - * } - * - * if (rr_node.ylow() != y) { - * VPR_ERROR(VPR_ERROR_ROUTE, "RR node ylow does not match between rr_nodes and rr_node_indices (%d/%d): %s", - * rr_node.ylow(), - * y, - * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); - * } - */ - } - - if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { - /* As we allow a pin to be indexable on multiple sides, - * This check code should be invalid - * if (rr_node.side() != side) { - * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%s/%s): %s", - * TOTAL_2D_SIDE_STRINGS[rr_node.side()], - * TOTAL_2D_SIDE_STRINGS[side], - * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); - * } else { - * VTR_ASSERT(rr_node.side() == side); - * } - */ - } - } - } - } - } - } - - if (rr_node_counts.size() != rr_nodes.size()) { - VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch in number of unique RR nodes in rr_nodes (%zu) and rr_node_indices (%zu)", - rr_nodes.size(), - rr_node_counts.size()); - } - - for (auto kv : rr_node_counts) { - RRNodeId inode = kv.first; - int count = kv.second; - - auto& rr_node = rr_nodes[size_t(inode)]; - - if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { - int rr_width = (rr_graph.node_xhigh(rr_node.id()) - rr_graph.node_xlow(rr_node.id()) + 1); - int rr_height = (rr_graph.node_yhigh(rr_node.id()) - rr_graph.node_ylow(rr_node.id()) + 1); - int rr_area = rr_width * rr_height; - if (count != rr_area) { - VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node size (%d) and count within rr_node_indices (%d): %s", - rr_area, - rr_node.length(), - count, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - /* As we allow a pin to be indexable on multiple sides, - * This check code should not be applied to input and output pins - */ - } else if ((e_rr_type::OPIN != rr_graph.node_type(inode)) && (e_rr_type::IPIN != rr_graph.node_type(inode))) { - if (count != rr_node.length() + 1) { - VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node length (%d) and count within rr_node_indices (%d, should be length + 1): %s", - rr_node.length(), - count, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - } - } - - return true; -} - int get_track_to_pins(RRGraphBuilder& rr_graph_builder, int layer, int seg, @@ -2007,41 +1446,8 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, return num_conn; } -void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_tile, - int layer, - int x, - int y, - int* num_rr_nodes) { - std::vector wanted_sides{TOP, BOTTOM, LEFT, RIGHT}; - auto class_num_range = get_flat_tile_primitive_classes(physical_tile); - auto pin_num_vec = get_flat_tile_pins(physical_tile); - - std::vector class_num_vec(class_num_range.total_num()); - std::iota(class_num_vec.begin(), class_num_vec.end(), class_num_range.low); - - add_classes_spatial_lookup(rr_graph_builder, - physical_tile, - class_num_vec, - layer, - x, - y, - physical_tile->width, - physical_tile->height, - num_rr_nodes); - - add_pins_spatial_lookup(rr_graph_builder, - physical_tile, - pin_num_vec, - layer, - x, - y, - num_rr_nodes, - wanted_sides); -} - static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, - const std::vector conn_tracks, + const std::vector& conn_tracks, const int layer, const int to_chan, const int to_seg, diff --git a/vpr/src/route/rr_graph_generation/rr_graph2.h b/vpr/src/route/rr_graph_generation/rr_graph2.h index 05e723470e4..c4b24569993 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph2.h +++ b/vpr/src/route/rr_graph_generation/rr_graph2.h @@ -14,62 +14,6 @@ /******************* Subroutines exported by rr_graph2.c *********************/ -/** - * @brief Allocates and populates data structures for efficient rr_node index lookups. - * - * This function sets up the `rr_node_indices` structure, which maps a physical location - * and type to the index of the first corresponding rr_node. - */ -void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width& nodes_per_chan, - const DeviceGrid& grid, - int* index, - const t_chan_details& chan_details_x, - const t_chan_details& chan_details_y); - -/** - * @brief Allocates extra nodes within the RR graph to support 3D custom switch blocks for multi-die FPGAs - * - * @param rr_graph_builder RRGraphBuilder data structure which allows data modification on a routing resource graph - * @param nodes_per_chan number of tracks per channel (x, y) - * @param grid device grid - * @param extra_nodes_per_switchblock keeps how many extra length-0 CHANX node is required for each unique (x,y) location within the grid. - * Number of these extra nodes are exactly the same for all layers. Hence, we only keep it for one layer. ([0..grid.width-1][0..grid.height-1) - * @param index RRNodeId that should be assigned to add a new RR node to the RR graph - */ -void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width& nodes_per_chan, - const DeviceGrid& grid, - const vtr::NdMatrix& extra_nodes_per_switchblock, - int* index); - -void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_tile, - int layer, - int x, - int y, - int* num_rr_nodes); - -void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grid, - const vtr::vector& pin_chains, - const vtr::vector>& pin_chains_num, - int* index); - -/** - * Validate the node look-up matches all the node-level information - * in the storage of a routing resource graph - * This function will check the following aspects: - * - The type of each node matches its type that is indexed in the node look-up - * - For bounding box (xlow, ylow, xhigh, yhigh) of each node is indexable in the node look-up - * - The number of unique indexable nodes in the node look up matches the number of nodes in the storage - * This ensures that every node in the storage is indexable and there are no hidden nodes in the look-up - */ -bool verify_rr_node_indices(const DeviceGrid& grid, - const RRGraphView& rr_graph, - const vtr::vector& rr_indexed_data, - const t_rr_graph_storage& rr_nodes, - bool is_flat); /** * @brief goes through 3D custom switch blocks and counts how many connections are crossing dice for each switch block. * diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp new file mode 100644 index 00000000000..5012b2d67c0 --- /dev/null +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -0,0 +1,600 @@ + +#include "rr_node_indices.h" + +#include "describe_rr_node.h" +#include "globals.h" +#include "physical_types_util.h" + + +/** + * @brief Assigns and loads rr_node indices for block-level routing resources (SOURCE, SINK, IPIN, OPIN). + * + * This function walks through the device grid and assigns unique rr_node indices to the routing resources + * associated with each block (tiles). + * + * For SINKs and SOURCEs, it uses side 0 by convention (since they have no geometric side). For IPINs and OPINs, + * it determines the correct sides based on the tile's position in the grid, following special rules for + * edge and corner tiles. + * + * The index counter is passed and updated as rr_nodes are added. + */ +static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grid, + int* index); + +static void load_chan_rr_indices(const int max_chan_width, + const DeviceGrid& grid, + const int chan_len, + const int num_chans, + const e_rr_type type, + const t_chan_details& chan_details, + RRGraphBuilder& rr_graph_builder, + int* index); + +static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_type_ptr, + const std::vector& class_num_vec, + int layer, + int x, + int y, + int block_width, + int block_height, + int* index); + +static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_type_ptr, + const std::vector& pin_num_vec, + int layer, + int root_x, + int root_y, + int* index, + const std::vector& wanted_sides); + +/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder + * TODO: these building functions should only talk to a RRGraphBuilder object + */ +static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grid, + int* index) { + //Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN + for (int layer = 0; layer < grid.get_num_layers(); layer++) { + for (int x = 0; x < (int)grid.width(); x++) { + for (int y = 0; y < (int)grid.height(); y++) { + //Process each block from its root location + if (grid.is_root_location({x, y, layer})) { + t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); + + //Assign indices for SINKs and SOURCEs + // Note that SINKS/SOURCES have no side, so we always use side 0 + std::vector class_num_vec = get_tile_root_classes(physical_type); + std::vector pin_num_vec = get_tile_root_pins(physical_type); + + add_classes_spatial_lookup(rr_graph_builder, + physical_type, + class_num_vec, + layer, + x, + y, + physical_type->width, + physical_type->height, + index); + + /* Limited sides for grids + * The wanted side depends on the location of the grid. + * In particular for perimeter grid, + * ------------------------------------------------------- + * Grid location | IPIN side + * ------------------------------------------------------- + * TOP | BOTTOM + * ------------------------------------------------------- + * RIGHT | LEFT + * ------------------------------------------------------- + * BOTTOM | TOP + * ------------------------------------------------------- + * LEFT | RIGHT + * ------------------------------------------------------- + * TOP-LEFT | BOTTOM & RIGHT + * ------------------------------------------------------- + * TOP-RIGHT | BOTTOM & LEFT + * ------------------------------------------------------- + * BOTTOM-LEFT | TOP & RIGHT + * ------------------------------------------------------- + * BOTTOM-RIGHT | TOP & LEFT + * ------------------------------------------------------- + * Other | First come first fit + * ------------------------------------------------------- + * + * Special for IPINs: + * If there are multiple wanted sides, first come first fit is applied + * This guarantee that there is only a unique rr_node + * for the same input pin on multiple sides, and thus avoid multiple driver problems + */ + std::vector wanted_sides; + if ((int)grid.height() - 1 == y) { /* TOP side */ + wanted_sides.push_back(BOTTOM); + } + if ((int)grid.width() - 1 == x) { /* RIGHT side */ + wanted_sides.push_back(LEFT); + } + if (0 == y) { /* BOTTOM side */ + wanted_sides.push_back(TOP); + } + if (0 == x) { /* LEFT side */ + wanted_sides.push_back(RIGHT); + } + + /* If wanted sides is empty still, this block does not have specific wanted sides, + * Deposit all the sides + */ + if (wanted_sides.empty()) { + for (e_side side : TOTAL_2D_SIDES) { + wanted_sides.push_back(side); + } + } + + add_pins_spatial_lookup(rr_graph_builder, + physical_type, + pin_num_vec, + layer, + x, + y, + index, + wanted_sides); + } + } + } + } +} + +static void load_chan_rr_indices(const int max_chan_width, + const DeviceGrid& grid, + const int chan_len, + const int num_chans, + const e_rr_type type, + const t_chan_details& chan_details, + RRGraphBuilder& rr_graph_builder, + int* index) { + const auto& device_ctx = g_vpr_ctx.device(); + + for (int layer = 0; layer < grid.get_num_layers(); layer++) { + // Skip the current die if architecture file specifies that it doesn't require global resource routing + if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { + continue; + } + + for (int chan = 0; chan < num_chans - 1; ++chan) { + for (int seg = 1; seg < chan_len - 1; ++seg) { + // Assign an inode to the starts of tracks + const int x = (type == e_rr_type::CHANX) ? seg : chan; + const int y = (type == e_rr_type::CHANX) ? chan : seg; + const t_chan_seg_details* seg_details = chan_details[x][y].data(); + + // Reserve nodes in lookup to save memory + rr_graph_builder.node_lookup().reserve_nodes(layer, x, y, type, max_chan_width); + + for (int track = 0; track < max_chan_width; ++track) { + /* TODO: May let the length() == 0 case go through, to model muxes */ + if (seg_details[track].length() <= 0) + continue; + + int start = get_seg_start(seg_details, track, chan, seg); + int node_start_x = (type == e_rr_type::CHANX) ? start : chan; + int node_start_y = (type == e_rr_type::CHANX) ? chan : start; + + // If the start of the wire doesn't have an RRNodeId, assign one to it. + RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, node_start_x, node_start_y, type, track); + if (!inode) { + inode = RRNodeId(*index); + ++(*index); + rr_graph_builder.node_lookup().add_node(inode, layer, node_start_x, node_start_y, type, track); + } + + // Assign RRNodeId of start of wire to current position + rr_graph_builder.node_lookup().add_node(inode, layer, x, y, type, track); + } + } + } + } +} + +static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_type_ptr, + const std::vector& class_num_vec, + int layer, + int root_x, + int root_y, + int block_width, + int block_height, + int* index) { + for (int x_tile = root_x; x_tile < (root_x + block_width); x_tile++) { + for (int y_tile = root_y; y_tile < (root_y + block_height); y_tile++) { + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::SOURCE, class_num_vec.size(), TOTAL_2D_SIDES[0]); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::SINK, class_num_vec.size(), TOTAL_2D_SIDES[0]); + } + } + + for (const int class_num : class_num_vec) { + e_pin_type class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); + e_rr_type node_type = e_rr_type::SINK; + if (class_type == DRIVER) { + node_type = e_rr_type::SOURCE; + } else { + VTR_ASSERT(class_type == RECEIVER); + } + + for (int x_offset = 0; x_offset < block_width; x_offset++) { + for (int y_offset = 0; y_offset < block_height; y_offset++) { + int curr_x = root_x + x_offset; + int curr_y = root_y + y_offset; + + rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, curr_x, curr_y, node_type, class_num); + } + } + + ++(*index); + } +} + +static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_type_ptr, + const std::vector& pin_num_vec, + int layer, + int root_x, + int root_y, + int* index, + const std::vector& wanted_sides) { + for (e_side side : wanted_sides) { + for (int width_offset = 0; width_offset < physical_type_ptr->width; ++width_offset) { + int x_tile = root_x + width_offset; + for (int height_offset = 0; height_offset < physical_type_ptr->height; ++height_offset) { + int y_tile = root_y + height_offset; + //only nodes on the tile may be located in a location other than the root-location + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::OPIN, physical_type_ptr->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::IPIN, physical_type_ptr->num_pins, side); + } + } + } + + for (const int pin_num : pin_num_vec) { + bool assigned_to_rr_node = false; + const auto [x_offset, y_offset, pin_sides] = get_pin_coordinates(physical_type_ptr, pin_num, wanted_sides); + e_pin_type pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); + for (int pin_coord_idx = 0; pin_coord_idx < (int)pin_sides.size(); pin_coord_idx++) { + int x_tile = root_x + x_offset[pin_coord_idx]; + int y_tile = root_y + y_offset[pin_coord_idx]; + e_side side = pin_sides[pin_coord_idx]; + if (pin_type == DRIVER) { + rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::OPIN, pin_num, side); + assigned_to_rr_node = true; + } else { + VTR_ASSERT(pin_type == RECEIVER); + rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::IPIN, pin_num, side); + assigned_to_rr_node = true; + } + } + /* A pin may locate on multiple sides of a tile. + * Instead of allocating multiple rr_nodes for the pin, + * we just create a rr_node and make it indexable on these sides + * As such, we can avoid redundant rr_node to be allocated + * and multiple nets to be mapped to the pin + * + * Considering that some pin could be just dangling, we do not need + * to create a void rr_node for it. + * As such, we only allocate a rr node when the pin is indeed located + * on at least one side + */ + if (assigned_to_rr_node) { + ++(*index); + } + } +} + +void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const t_chan_width& nodes_per_chan, + const DeviceGrid& grid, + int* index, + const t_chan_details& chan_details_x, + const t_chan_details& chan_details_y) { + /* Alloc the lookup table */ + for (e_rr_type rr_type : RR_TYPES) { + rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.width(), grid.height(), rr_type, NUM_2D_SIDES); + } + + /* Assign indices for block nodes */ + load_block_rr_indices(rr_graph_builder, grid, index); + + /* Load the data for x and y channels */ + load_chan_rr_indices(nodes_per_chan.x_max, grid, grid.width(), grid.height(), + e_rr_type::CHANX, chan_details_x, rr_graph_builder, index); + load_chan_rr_indices(nodes_per_chan.y_max, grid, grid.height(), grid.width(), + e_rr_type::CHANY, chan_details_y, rr_graph_builder, index); +} + +void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const t_chan_width& nodes_per_chan, + const DeviceGrid& grid, + const vtr::NdMatrix& extra_nodes_per_switchblock, + int* index) { + /* + * In case of multi-die FPGAs, we add extra nodes (could have used either CHANX or CHANY; we chose to use all CHANX) to + * support inter-die communication coming from switch blocks (connection between two tracks in different layers) + * The extra nodes have the following attribute: + * 1) type = CHANX + * 2) length = 0 (xhigh = xlow, yhigh = ylow) + * 3) ptc = [max_chanx_width:max_chanx_width+number_of_connection-1] + * 4) direction = NONE + */ + const auto& device_ctx = g_vpr_ctx.device(); + + for (int layer = 0; layer < grid.get_num_layers(); layer++) { + /* Skip the current die if architecture file specifies that it doesn't have global resource routing */ + if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { + continue; + } + + for (size_t y = 0; y < grid.height() - 1; ++y) { + for (size_t x = 1; x < grid.width() - 1; ++x) { + // count how many track-to-track connection go from current layer to other layers + int conn_count = extra_nodes_per_switchblock[x][y]; + + // skip if no connection is required + if (conn_count == 0) { + continue; + } + + // reserve extra nodes for inter-die track-to-track connection + rr_graph_builder.node_lookup().reserve_nodes(layer, x, y, e_rr_type::CHANX, conn_count + nodes_per_chan.max); + for (int rr_node_offset = 0; rr_node_offset < conn_count; rr_node_offset++) { + RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x, y, e_rr_type::CHANX, nodes_per_chan.max + rr_node_offset); + if (!inode) { + inode = RRNodeId(*index); + ++(*index); + rr_graph_builder.node_lookup().add_node(inode, layer, x, y, e_rr_type::CHANX, nodes_per_chan.max + rr_node_offset); + } + } + } + } + } +} + +void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_tile, + int layer, + int x, + int y, + int* num_rr_nodes) { + std::vector wanted_sides{TOP, BOTTOM, LEFT, RIGHT}; + auto class_num_range = get_flat_tile_primitive_classes(physical_tile); + auto pin_num_vec = get_flat_tile_pins(physical_tile); + + std::vector class_num_vec(class_num_range.total_num()); + std::iota(class_num_vec.begin(), class_num_vec.end(), class_num_range.low); + + add_classes_spatial_lookup(rr_graph_builder, + physical_tile, + class_num_vec, + layer, + x, + y, + physical_tile->width, + physical_tile->height, + num_rr_nodes); + + add_pins_spatial_lookup(rr_graph_builder, + physical_tile, + pin_num_vec, + layer, + x, + y, + num_rr_nodes, + wanted_sides); +} + +void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grid, + const vtr::vector& pin_chains, + const vtr::vector>& pin_chains_num, + int* index) { + for (int layer = 0; layer < grid.get_num_layers(); layer++) { + for (int x = 0; x < (int)grid.width(); x++) { + for (int y = 0; y < (int)grid.height(); y++) { + //Process each block from its root location + if (grid.is_root_location({x, y, layer})) { + t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); + //Assign indices for SINKs and SOURCEs + // Note that SINKS/SOURCES have no side, so we always use side 0 + std::vector class_num_vec; + std::vector pin_num_vec; + class_num_vec = get_cluster_netlist_intra_tile_classes_at_loc(layer, x, y, physical_type); + pin_num_vec = get_cluster_netlist_intra_tile_pins_at_loc(layer, + x, + y, + pin_chains, + pin_chains_num, + physical_type); + add_classes_spatial_lookup(rr_graph_builder, + physical_type, + class_num_vec, + layer, + x, + y, + physical_type->width, + physical_type->height, + index); + + std::vector wanted_sides; + wanted_sides.push_back(e_side::TOP); + add_pins_spatial_lookup(rr_graph_builder, + physical_type, + pin_num_vec, + layer, + x, + y, + index, + wanted_sides); + } + } + } + } +} + +bool verify_rr_node_indices(const DeviceGrid& grid, + const RRGraphView& rr_graph, + const vtr::vector& rr_indexed_data, + const t_rr_graph_storage& rr_nodes, + bool is_flat) { + std::unordered_map rr_node_counts; + + int width = grid.width(); + int height = grid.height(); + int layer = grid.get_num_layers(); + + for (int l = 0; l < layer; ++l) { + for (int x = 0; x < width; ++x) { + for (int y = 0; y < height; ++y) { + for (e_rr_type rr_type : RR_TYPES) { + /* Get the list of nodes at a specific location (x, y) */ + std::vector nodes_from_lookup; + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { + nodes_from_lookup = rr_graph.node_lookup().find_channel_nodes(l, x, y, rr_type); + } else { + nodes_from_lookup = rr_graph.node_lookup().find_grid_nodes_at_all_sides(l, x, y, rr_type); + } + + for (RRNodeId inode : nodes_from_lookup) { + rr_node_counts[inode]++; + + if (rr_graph.node_type(inode) != rr_type) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node type does not match between rr_nodes and rr_node_indices (%s/%s): %s", + rr_node_typename[rr_graph.node_type(inode)], + rr_node_typename[rr_type], + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + + if (rr_graph.node_type(inode) == e_rr_type::CHANX) { + VTR_ASSERT_MSG(rr_graph.node_ylow(inode) == rr_graph.node_yhigh(inode), "CHANX should be horizontal"); + if (y != rr_graph.node_ylow(inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node y position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", + rr_graph.node_ylow(inode), + y, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + + if (!rr_graph.x_in_node_range(x, inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", + rr_graph.node_xlow(inode), + rr_graph.node_xlow(inode), + x, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + } else if (rr_graph.node_type(inode) == e_rr_type::CHANY) { + VTR_ASSERT_MSG(rr_graph.node_xlow(inode) == rr_graph.node_xhigh(inode), "CHANY should be vertical"); + + if (x != rr_graph.node_xlow(inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node x position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", + rr_graph.node_xlow(inode), + x, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + + if (!rr_graph.y_in_node_range(y, inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node y positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", + rr_graph.node_ylow(inode), + rr_graph.node_ylow(inode), + y, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { + // Sources have co-ordinates covering the entire block they are in, but not sinks + if (!rr_graph.x_in_node_range(x, inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", + rr_graph.node_xlow(inode), + rr_graph.node_xlow(inode), + x, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + + if (!rr_graph.y_in_node_range(y, inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node y positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", + rr_graph.node_ylow(inode), + rr_graph.node_ylow(inode), + y, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + } else { + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::IPIN || rr_graph.node_type(inode) == e_rr_type::OPIN); + /* As we allow a pin to be indexable on multiple sides, + * This check code should be invalid + * if (rr_node.xlow() != x) { + * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%d/%d): %s", + * rr_node.xlow(), + * x, + * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); + * } + * + * if (rr_node.ylow() != y) { + * VPR_ERROR(VPR_ERROR_ROUTE, "RR node ylow does not match between rr_nodes and rr_node_indices (%d/%d): %s", + * rr_node.ylow(), + * y, + * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); + * } + */ + } + + if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { + /* As we allow a pin to be indexable on multiple sides, + * This check code should be invalid + * if (rr_node.side() != side) { + * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%s/%s): %s", + * TOTAL_2D_SIDE_STRINGS[rr_node.side()], + * TOTAL_2D_SIDE_STRINGS[side], + * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); + * } else { + * VTR_ASSERT(rr_node.side() == side); + * } + */ + } + } + } + } + } + } + + if (rr_node_counts.size() != rr_nodes.size()) { + VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch in number of unique RR nodes in rr_nodes (%zu) and rr_node_indices (%zu)", + rr_nodes.size(), + rr_node_counts.size()); + } + + for (auto kv : rr_node_counts) { + RRNodeId inode = kv.first; + int count = kv.second; + + auto& rr_node = rr_nodes[size_t(inode)]; + + if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { + int rr_width = (rr_graph.node_xhigh(rr_node.id()) - rr_graph.node_xlow(rr_node.id()) + 1); + int rr_height = (rr_graph.node_yhigh(rr_node.id()) - rr_graph.node_ylow(rr_node.id()) + 1); + int rr_area = rr_width * rr_height; + if (count != rr_area) { + VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node size (%d) and count within rr_node_indices (%d): %s", + rr_area, + rr_node.length(), + count, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + /* As we allow a pin to be indexable on multiple sides, + * This check code should not be applied to input and output pins + */ + } else if ((e_rr_type::OPIN != rr_graph.node_type(inode)) && (e_rr_type::IPIN != rr_graph.node_type(inode))) { + if (count != rr_node.length() + 1) { + VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node length (%d) and count within rr_node_indices (%d, should be length + 1): %s", + rr_node.length(), + count, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + } + } + + return true; +} \ No newline at end of file diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.h b/vpr/src/route/rr_graph_generation/rr_node_indices.h new file mode 100644 index 00000000000..0be90e07c6a --- /dev/null +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.h @@ -0,0 +1,66 @@ +#pragma once + +#include "rr_graph_builder.h" +#include "rr_graph_view.h" +#include "device_grid.h" +#include "rr_types.h" +#include "rr_graph_type.h" +#include "rr_graph_utils.h" +#include "clustered_netlist_fwd.h" + +/** + * @brief Allocates and populates data structures for efficient rr_node index lookups. + * + * This function sets up the `rr_node_indices` structure, which maps a physical location + * and type to the index of the first corresponding rr_node. + */ +void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const t_chan_width& nodes_per_chan, + const DeviceGrid& grid, + int* index, + const t_chan_details& chan_details_x, + const t_chan_details& chan_details_y); + +/** + * @brief Allocates extra nodes within the RR graph to support 3D custom switch blocks for multi-die FPGAs + * + * @param rr_graph_builder RRGraphBuilder data structure which allows data modification on a routing resource graph + * @param nodes_per_chan number of tracks per channel (x, y) + * @param grid device grid + * @param extra_nodes_per_switchblock keeps how many extra length-0 CHANX node is required for each unique (x,y) location within the grid. + * Number of these extra nodes are exactly the same for all layers. Hence, we only keep it for one layer. ([0..grid.width-1][0..grid.height-1) + * @param index RRNodeId that should be assigned to add a new RR node to the RR graph + */ +void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const t_chan_width& nodes_per_chan, + const DeviceGrid& grid, + const vtr::NdMatrix& extra_nodes_per_switchblock, + int* index); + +void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_tile, + int layer, + int x, + int y, + int* num_rr_nodes); + +void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grid, + const vtr::vector& pin_chains, + const vtr::vector>& pin_chains_num, + int* index); + +/** + * Validate the node look-up matches all the node-level information + * in the storage of a routing resource graph + * This function will check the following aspects: + * - The type of each node matches its type that is indexed in the node look-up + * - For bounding box (xlow, ylow, xhigh, yhigh) of each node is indexable in the node look-up + * - The number of unique indexable nodes in the node look up matches the number of nodes in the storage + * This ensures that every node in the storage is indexable and there are no hidden nodes in the look-up + */ +bool verify_rr_node_indices(const DeviceGrid& grid, + const RRGraphView& rr_graph, + const vtr::vector& rr_indexed_data, + const t_rr_graph_storage& rr_nodes, + bool is_flat); From 7b9c22627b3117705d80120f2239bc57bb53c490 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Thu, 15 May 2025 14:42:05 -0400 Subject: [PATCH 138/176] add doxygen comment for load_chan_rr_indices() --- .../rr_graph_generation/rr_node_indices.cpp | 34 +++++++++++++------ 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp index 5012b2d67c0..062b4e79b90 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -5,7 +5,6 @@ #include "globals.h" #include "physical_types_util.h" - /** * @brief Assigns and loads rr_node indices for block-level routing resources (SOURCE, SINK, IPIN, OPIN). * @@ -22,13 +21,28 @@ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grid, int* index); +/** + * @brief Populates the lookup indices for channel (CHANX or CHANY) RR nodes. + * + * This function builds part of the RR spatial lookup structure, specifically + * the RR nodes associated with routing channels (CHANX or CHANY). + * + * @param max_chan_width Maximum channel width (number of tracks). + * @param grid Device grid layout. + * @param chan_len Length of the channel being processed. + * @param num_chans Total number of channels in the direction being processed. + * @param type RR node type: should be CHANX or CHANY. + * @param chan_details Channel details used to determine segment and track information. + * @param node_lookup Spatial RR node lookup to be filled by this function. + * @param index The next available RR node index. + */ static void load_chan_rr_indices(const int max_chan_width, const DeviceGrid& grid, const int chan_len, const int num_chans, const e_rr_type type, const t_chan_details& chan_details, - RRGraphBuilder& rr_graph_builder, + RRSpatialLookup& node_lookup, int* index); static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, @@ -152,7 +166,7 @@ static void load_chan_rr_indices(const int max_chan_width, const int num_chans, const e_rr_type type, const t_chan_details& chan_details, - RRGraphBuilder& rr_graph_builder, + RRSpatialLookup& node_lookup, int* index) { const auto& device_ctx = g_vpr_ctx.device(); @@ -170,7 +184,7 @@ static void load_chan_rr_indices(const int max_chan_width, const t_chan_seg_details* seg_details = chan_details[x][y].data(); // Reserve nodes in lookup to save memory - rr_graph_builder.node_lookup().reserve_nodes(layer, x, y, type, max_chan_width); + node_lookup.reserve_nodes(layer, x, y, type, max_chan_width); for (int track = 0; track < max_chan_width; ++track) { /* TODO: May let the length() == 0 case go through, to model muxes */ @@ -182,15 +196,15 @@ static void load_chan_rr_indices(const int max_chan_width, int node_start_y = (type == e_rr_type::CHANX) ? chan : start; // If the start of the wire doesn't have an RRNodeId, assign one to it. - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, node_start_x, node_start_y, type, track); + RRNodeId inode = node_lookup.find_node(layer, node_start_x, node_start_y, type, track); if (!inode) { inode = RRNodeId(*index); ++(*index); - rr_graph_builder.node_lookup().add_node(inode, layer, node_start_x, node_start_y, type, track); + node_lookup.add_node(inode, layer, node_start_x, node_start_y, type, track); } // Assign RRNodeId of start of wire to current position - rr_graph_builder.node_lookup().add_node(inode, layer, x, y, type, track); + node_lookup.add_node(inode, layer, x, y, type, track); } } } @@ -305,9 +319,9 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, /* Load the data for x and y channels */ load_chan_rr_indices(nodes_per_chan.x_max, grid, grid.width(), grid.height(), - e_rr_type::CHANX, chan_details_x, rr_graph_builder, index); + e_rr_type::CHANX, chan_details_x, rr_graph_builder.node_lookup(), index); load_chan_rr_indices(nodes_per_chan.y_max, grid, grid.height(), grid.width(), - e_rr_type::CHANY, chan_details_y, rr_graph_builder, index); + e_rr_type::CHANY, chan_details_y, rr_graph_builder.node_lookup(), index); } void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, @@ -597,4 +611,4 @@ bool verify_rr_node_indices(const DeviceGrid& grid, } return true; -} \ No newline at end of file +} From 2b9aa9a512c37fc17ca398346ed12418a2daf895 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Thu, 15 May 2025 15:02:27 -0400 Subject: [PATCH 139/176] [Infra] Updated Install Packages Script For Backwards Compatibility The install_apt_packages.sh script is no longer backward compatible with older versions of Ubuntu due to the dependency on clang-format-18. Added an if statement to check if the distribution can support clang-format-18 and only installing it if it can. Added this script to the CI build process so it can always be tested within the CI to prevent future regression. --- .github/scripts/install_dependencies.sh | 17 +++++------------ .github/scripts/install_jammy_dependencies.sh | 17 +++++------------ Dockerfile | 5 +---- install_apt_packages.sh | 17 +++++++++++++---- 4 files changed, 24 insertions(+), 32 deletions(-) diff --git a/.github/scripts/install_dependencies.sh b/.github/scripts/install_dependencies.sh index 383b237a89e..0d05ecdc7d1 100755 --- a/.github/scripts/install_dependencies.sh +++ b/.github/scripts/install_dependencies.sh @@ -2,40 +2,32 @@ sudo apt update +# Required packages specifically for the CI and not VTR in general. sudo apt install -y \ autoconf \ automake \ bash \ - bison \ binutils \ binutils-gold \ - build-essential \ capnproto \ exuberant-ctags \ curl \ doxygen \ - flex \ fontconfig \ gdb \ - git \ gperf \ libcairo2-dev \ libcapnp-dev \ - libgtk-3-dev \ libevent-dev \ libfontconfig1-dev \ liblist-moreutils-perl \ libncurses5-dev \ - libx11-dev \ libxft-dev \ libxml2-utils \ libxml++2.6-dev \ - libreadline-dev \ tcllib \ tcl8.6-dev \ - libffi-dev \ perl \ - pkg-config \ texinfo \ time \ valgrind \ @@ -54,9 +46,10 @@ sudo apt install -y \ clang-15 \ clang-16 \ clang-17 \ - clang-18 \ - clang-format-18 \ - libtbb-dev + clang-18 + +# Standard packages install script. +./install_apt_packages.sh pip install -r requirements.txt diff --git a/.github/scripts/install_jammy_dependencies.sh b/.github/scripts/install_jammy_dependencies.sh index aa6631f8a04..82fc6d587bd 100755 --- a/.github/scripts/install_jammy_dependencies.sh +++ b/.github/scripts/install_jammy_dependencies.sh @@ -2,40 +2,32 @@ sudo apt update +# Required packages specifically for the CI and not VTR in general. sudo apt install -y \ autoconf \ automake \ bash \ - bison \ binutils \ binutils-gold \ - build-essential \ capnproto \ exuberant-ctags \ curl \ doxygen \ - flex \ fontconfig \ gdb \ - git \ gperf \ libcairo2-dev \ libcapnp-dev \ - libgtk-3-dev \ libevent-dev \ libfontconfig1-dev \ liblist-moreutils-perl \ libncurses5-dev \ - libx11-dev \ libxft-dev \ libxml2-utils \ libxml++2.6-dev \ - libreadline-dev \ tcllib \ tcl8.6-dev \ - libffi-dev \ perl \ - pkg-config \ texinfo \ time \ valgrind \ @@ -50,9 +42,10 @@ sudo apt install -y \ g++-11 \ gcc-11 \ g++-12 \ - gcc-12 \ - clang-format-14 \ - libtbb-dev + gcc-12 + +# Standard packages install script. +./install_apt_packages.sh pip install -r requirements.txt diff --git a/Dockerfile b/Dockerfile index 29c3cd94c66..1d25efe0304 100644 --- a/Dockerfile +++ b/Dockerfile @@ -11,18 +11,15 @@ ENV PIP_BREAK_SYSTEM_PACKAGES=1 # Install and cleanup is done in one command to minimize the build cache size RUN apt-get update -qq \ # Extract package names from install_apt_packages.sh - && sed '/sudo/d' install_apt_packages.sh | sed '/#/d' | sed 's/ \\//g' | sed '/^$/d' | sed '/^[[:space:]]*$/d' \ + && sed '/sudo/d' install_apt_packages.sh | sed '/#/d' | sed '/if\s.*then$/d' | sed '/else$/d' | sed '/fi$/d' | sed '/echo\s/d' | sed 's/ \\//g' | sed '/^$/d' | sed '/^[[:space:]]*$/d' | sed 's/\s//g' \ # Install packages | xargs apt-get -y install --no-install-recommends \ # Additional packages not listed in install_apt_packages.sh && apt-get -y install --no-install-recommends \ wget \ ninja-build \ - default-jre \ libeigen3-dev \ - libtbb-dev \ python3-pip \ - git \ time \ # Install python packages && pip install -r requirements.txt \ diff --git a/install_apt_packages.sh b/install_apt_packages.sh index 2d0dbf399e2..8fc5d929ce2 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -10,7 +10,11 @@ sudo apt-get install -y \ flex \ python3-dev \ python3-venv - + +# Packages for more complex features of VTR that most people will use. +sudo apt-get install -y \ + libtbb-dev + # Required for graphics sudo apt-get install -y \ libgtk-3-dev \ @@ -42,6 +46,11 @@ sudo apt-get install -y \ sphinx-common # Required for code formatting -sudo apt-get install -y \ - clang-format-18 - +# NOTE: clang-format-18 may only be found on specific distributions. Only +# install it if the distribution has this version of clang format. +if apt-cache search '^clang-format-18$' | grep -q 'clang-format-18'; then + sudo apt-get install -y \ + clang-format-18 +else + echo "clang-format-18 not found in apt-cache. Skipping installation." +fi From 55a40c6a29be41543e7c2fc8c17f0062b8fd6ebe Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Thu, 15 May 2025 17:20:59 -0400 Subject: [PATCH 140/176] [RegTest] Disabled `strong_multiclock` test for parallel connection router Temporarily disabled the `strong_multiclock` test in `vtr_reg_strong` CI regression tests for the parallel connection router, due to some random failures as mentioned in Issue #3029. After fixing the problem with the `strong_multiclock` test, this will be reactivated. --- .../vtr_reg_strong/strong_multiclock/config/config.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt index 1a19286d997..3734b81c3cf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt @@ -27,6 +27,6 @@ pass_requirements_file=pass_requirements_multiclock.txt script_params_common=-starting_stage vpr -sdc_file tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/multiclock.sdc script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 -script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +# script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +# script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +# script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 From 403b9457f39519dcfda0bfe2aba36bd4e7adbf37 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 15 May 2025 17:51:15 -0400 Subject: [PATCH 141/176] [doc] update the doc with new report format --- doc/src/vpr/command_line_usage.rst | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 608d0bbf1d5..b450b9d661e 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1520,15 +1520,26 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout .. option:: --generate_net_timing_report {on | off} - Generates a net timing report for each net in the design. For each net, the timing information written in the following format: + Generates a report that lists the bounding box, slack, and delay of every routed connection in a design in csv format. Fields in the report are: .. code-block:: none - - netname : Fanout : - (bounding_box_xmin,bounding_box_ymin,bounding_box_layer_min),(bounding_box_xmax,bounding_box_ymax,bounding_box_layer_max) : - source_instance : - : - : ... + netname: The name assigned to the net in atom netlist + Fanout : Net's fanout + bb_xmin: X coordinate of the net's bounding box's bottom left corner + bb_ymin: Y coordinate of the net's bounding box's bottom left corner + bb_layer_min: Lowest layer number of the net's bounding box + bb_xmax: X coordinate of the net's bounding box's top right corner + bb_ymax: Y coordinate of the net's bounding box's top right corner + bb_layer_max: Highest layer number of the net's bounding box + src_pin_name: Name of the net's source pin + src_pin_slack: Slack of the net's source pin + sink_1_pin_name: Name of the net's first sink pin + sink_1_pin_slack: Slack of the net's first sink pin + sink_1_pin_delay: Delay of the net's first sink pin + sink_2_pin_name: Name of the net's second sink pin + sink_2_pin_slack: Slack of the net's second sink pin + sink_2_pin_delay: Delay of the net's second sink pin + ... **Default:** ``off`` From 16769129c56b7eaf14c50e4b77c59db4cf6e4123 Mon Sep 17 00:00:00 2001 From: Hang Yan Date: Thu, 15 May 2025 18:32:37 -0400 Subject: [PATCH 142/176] [RegTest] Updated golden results for `strong_multiclock` regression test Removed the golden results of parallel connection router test cases for `strong_multiclock` regression test. --- .../vtr_reg_strong/strong_multiclock/config/golden_results.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 266c7161ad8..d61417eb846 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,6 +1,3 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 From 77799b6383e40cb13de4b0ccad6556ebc4339d0c Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 16 May 2025 12:13:03 -0400 Subject: [PATCH 143/176] [vpr][analysis] use std::min/max instead of if condition --- doc/src/vpr/command_line_usage.rst | 2 +- vpr/src/analysis/timing_reports.cpp | 24 ++++++++++-------------- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index b450b9d661e..f6e5b831476 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1520,7 +1520,7 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout .. option:: --generate_net_timing_report {on | off} - Generates a report that lists the bounding box, slack, and delay of every routed connection in a design in csv format. Fields in the report are: + Generates a report that lists the bounding box, slack, and delay of every routed connection in a design in csv format (``report_net_timing.csv``). Fields in the report are: .. code-block:: none netname: The name assigned to the net in atom netlist diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 36cb99c0207..4d87fa2c8f7 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -18,12 +18,14 @@ #include "VprTimingGraphResolver.h" /** - * @brief Get the bounding box of a net. + * @brief Get the bounding box of a routed net. * If the net is completely absorbed into a cluster block, return the bounding box of the cluster block. * Otherwise, return the bounding box of the net's route tree. - * If a net is not routed, bounding box is returned with default values (OPEN). * * @param atom_net_id The id of the atom net to get the bounding box of. + * + * @return The bounding box of the net. If the net is not routed, a bounding box + * is returned with default values (OPEN). */ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { const auto& route_trees = g_vpr_ctx.routing().route_trees; @@ -46,20 +48,14 @@ static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { for (auto& rt_node : route_tree.all_nodes()) { RRNodeId inode = rt_node.inode; - if (rr_graph.node_xlow(inode) < bb.xmin) - bb.xmin = rr_graph.node_xlow(inode); - if (rr_graph.node_xhigh(inode) > bb.xmax) - bb.xmax = rr_graph.node_xhigh(inode); + bb.xmin = std::min(static_cast(rr_graph.node_xlow(inode)), bb.xmin); + bb.xmax = std::max(static_cast(rr_graph.node_xhigh(inode)), bb.xmax); - if (rr_graph.node_ylow(inode) < bb.ymin) - bb.ymin = rr_graph.node_ylow(inode); - if (rr_graph.node_yhigh(inode) > bb.ymax) - bb.ymax = rr_graph.node_yhigh(inode); + bb.ymin = std::min(static_cast(rr_graph.node_ylow(inode)), bb.ymin); + bb.ymax = std::max(static_cast(rr_graph.node_yhigh(inode)), bb.ymax); - if (rr_graph.node_layer(inode) < bb.layer_min) - bb.layer_min = rr_graph.node_layer(inode); - if (rr_graph.node_layer(inode) > bb.layer_max) - bb.layer_max = rr_graph.node_layer(inode); + bb.layer_min = std::min(static_cast(rr_graph.node_layer(inode)), bb.layer_min); + bb.layer_max = std::max(static_cast(rr_graph.node_layer(inode)), bb.layer_max); } return bb; }; From 0ba6614ce1f4e59e8db6c944ef928fcdb64df64d Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Fri, 16 May 2025 12:13:11 -0400 Subject: [PATCH 144/176] Add documentation for include sanitization --- README.developers.md | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/README.developers.md b/README.developers.md index 866f8ca1dac..4c05edfedca 100644 --- a/README.developers.md +++ b/README.developers.md @@ -179,6 +179,29 @@ For large scale reformatting (should only be performed by VTR maintainers) the s Python files are automatically checked using `pylint` to ensure they follow established Python conventions. You can run `pylint` on the entire repository by running `./dev/pylint_check.py`. Certain files which were created before we adopted Python lint checking are grandfathered and are not checked. To check *all* files, provide the `--check_grandfathered` argument. You can also manually check individual files using `./dev/pylint_check.py ...`. +# Sanitizing Includes + +You can use include-what-you-use or the clangd language server to make sure includes are correct and you don't have missing or unused includes. + +## include-what-you-use + +First, install include-what-you-use. Ubuntu/Debian users can run `sudo apt install iwyu` and Fedora/RHEL users can run `sudo dnf install iwyu`. You can then compile VTR with include-what-you-use enabled to get diagnostic messages about includes in all files with the following command: + +``` +make CMAKE_PARAMS="-DCMAKE_CXX_INCLUDE_WHAT_YOU_USE=include-what-you-use" +``` + +Note that this method checks all source files and the diagnostic messages can be very long. + +## clangd language server + +Alternatively, if your editor supports clangd, you can use it to get diagnostic messages for the specific file you are working with. Visual Studio Code users can use the clangd extension to use clangd instead of Microsoft's C/C++ extension. To enable include diagnostics, create a file named `.clangd` in VTR root directory and add the following lines to it: +``` +Diagnostics: + UnusedIncludes: Strict + MissingIncludes: Strict +``` + # Running Tests VTR has a variety of tests which are used to check for correctness, performance and Quality of Result (QoR). From e03f90c568a86ee89eeb826c635eea60001b8a2e Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 16 May 2025 12:28:15 -0400 Subject: [PATCH 145/176] [vpr][analysis] change report_net_timing format to csv --- vpr/src/analysis/timing_reports.cpp | 76 +++++++++++------------------ 1 file changed, 28 insertions(+), 48 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 4d87fa2c8f7..dcb05ea7781 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -180,75 +180,55 @@ void generate_hold_timing_stats(const std::string& prefix, timing_reporter.report_unconstrained_hold(prefix + "report_unconstrained_timing.hold.rpt", *timing_info.hold_analyzer()); } -void generate_net_timing_report(const std::string& prefix, - const SetupHoldTimingInfo& timing_info, - const AnalysisDelayCalculator& delay_calc) { - /* Create a report file for net timing information */ - std::ofstream os(prefix + "report_net_timing.rpt"); +void generate_net_timing_report_csv(const std::string& prefix, + const SetupHoldTimingInfo& timing_info, + const AnalysisDelayCalculator& delay_calc) { + std::ofstream os(prefix + "report_net_timing.csv"); const auto& atom_netlist = g_vpr_ctx.atom().netlist(); const auto& atom_lookup = g_vpr_ctx.atom().lookup(); - const auto& timing_ctx = g_vpr_ctx.timing(); const auto& timing_graph = timing_ctx.graph; - os << "# This file is generated by VTR" << std::endl; - os << "# Version: " << vtr::VERSION << std::endl; - os << "# Revision: " << vtr::VCS_REVISION << std::endl; - os << "# For each net, the timing information is reported in the following format:" << std::endl; - os << "# netname : Fanout : " - << "(bounding_box_xmin,bounding_box_ymin,bounding_box_layermin),(bounding_box_xmax,bounding_box_ymax,bounding_box_layermax) : " - << "source_instance : " - << " : " - << " : ..." - << std::endl; - - os << std::endl; + // Write CSV header + os << "netname,Fanout,bb_xmin,bb_ymin,bb_layer_min," + << "bb_xmax,bb_ymax,bb_layer_max," + << "src_pin_name,src_pin_slack,sinks" << std::endl; for (const auto& net : atom_netlist.nets()) { - /* Skip constant nets */ - if (atom_netlist.net_is_constant(net)) { - continue; - } + if (atom_netlist.net_is_constant(net)) continue; const auto& net_name = atom_netlist.net_name(net); - - /* Get source pin and its timing information */ const auto& source_pin = *atom_netlist.net_pins(net).begin(); auto source_pin_slack = timing_info.setup_pin_slack(source_pin); - /* Timing graph node id corresponding to the net's source pin */ auto tg_source_node = atom_lookup.atom_pin_tnode(source_pin); VTR_ASSERT(tg_source_node.is_valid()); const size_t fanout = atom_netlist.net_sinks(net).size(); const auto& net_bb = get_net_bounding_box(net); - os << net_name << " : " - << fanout << " : " - << "(" << net_bb.xmin << "," << net_bb.ymin << "," << net_bb.layer_min << "),(" - << net_bb.xmax << "," << net_bb.ymax << "," << net_bb.layer_max << ") : " - << atom_netlist.pin_name(source_pin).c_str() << " " << source_pin_slack << " : "; - - /* Iterate over all fanout pins and print their timing information */ - for (size_t net_pin_index = 1; net_pin_index <= fanout; ++net_pin_index) { - const auto& pin = *(atom_netlist.net_pins(net).begin() + net_pin_index); - - /* Get timing graph node id corresponding to the fanout pin */ - const auto& tg_sink_node = atom_lookup.atom_pin_tnode(pin); + + os << "\"" << net_name << "\"," // netname (quoted for safety) + << fanout << "," + << net_bb.xmin << "," << net_bb.ymin << "," << net_bb.layer_min << "," + << net_bb.xmax << "," << net_bb.ymax << "," << net_bb.layer_max << "," + << "\"" << atom_netlist.pin_name(source_pin) << "\"," << source_pin_slack << ","; + + // Write sinks column (quoted, semicolon-delimited, each sink: name,slack,delay) + os << "\""; + for (size_t i = 0; i < fanout; ++i) { + const auto& pin = *(atom_netlist.net_pins(net).begin() + i + 1); + auto tg_sink_node = atom_lookup.atom_pin_tnode(pin); VTR_ASSERT(tg_sink_node.is_valid()); - /* Get timing graph edge id between atom pins */ - const auto& tg_edge_id = timing_graph->find_edge(tg_source_node, tg_sink_node); + auto tg_edge_id = timing_graph->find_edge(tg_source_node, tg_sink_node); VTR_ASSERT(tg_edge_id.is_valid()); - /* Get timing information for the fanout pin */ - const auto& pin_setup_slack = timing_info.setup_pin_slack(pin); - const auto& pin_delay = delay_calc.max_edge_delay(*timing_graph, tg_edge_id); - + auto pin_setup_slack = timing_info.setup_pin_slack(pin); + auto pin_delay = delay_calc.max_edge_delay(*timing_graph, tg_edge_id); const auto& pin_name = atom_netlist.pin_name(pin); - os << pin_name << " " << std::scientific << pin_setup_slack << " " << pin_delay; - if (net_pin_index < fanout) { - os << " : "; - } + + os << pin_name << "," << pin_setup_slack << "," << pin_delay; + if (i != fanout - 1) os << ";"; } - os << "," << std::endl; + os << "\"" << std::endl; // Close quoted sinks field and finish the row } } From b8a60ea636faf99a996fa6880c94b89d799f18c9 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 16 May 2025 13:08:58 -0400 Subject: [PATCH 146/176] [vpr][analysis] update comments --- doc/src/vpr/command_line_usage.rst | 36 +++++++++++++++--------------- vpr/src/analysis/timing_reports.h | 28 ++++++++++++++--------- 2 files changed, 36 insertions(+), 28 deletions(-) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index f6e5b831476..40fc5de3813 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1520,26 +1520,26 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout .. option:: --generate_net_timing_report {on | off} - Generates a report that lists the bounding box, slack, and delay of every routed connection in a design in csv format (``report_net_timing.csv``). Fields in the report are: + Generates a report that lists the bounding box, slack, and delay of every routed connection in a design in CSV format (``report_net_timing.csv``). Each row in the CSV corresponds to a single net. + + Fields in the report are: .. code-block:: none - netname: The name assigned to the net in atom netlist - Fanout : Net's fanout - bb_xmin: X coordinate of the net's bounding box's bottom left corner - bb_ymin: Y coordinate of the net's bounding box's bottom left corner - bb_layer_min: Lowest layer number of the net's bounding box - bb_xmax: X coordinate of the net's bounding box's top right corner - bb_ymax: Y coordinate of the net's bounding box's top right corner - bb_layer_max: Highest layer number of the net's bounding box - src_pin_name: Name of the net's source pin - src_pin_slack: Slack of the net's source pin - sink_1_pin_name: Name of the net's first sink pin - sink_1_pin_slack: Slack of the net's first sink pin - sink_1_pin_delay: Delay of the net's first sink pin - sink_2_pin_name: Name of the net's second sink pin - sink_2_pin_slack: Slack of the net's second sink pin - sink_2_pin_delay: Delay of the net's second sink pin - ... + netname : The name assigned to the net in the atom netlist + Fanout : Net's fanout (number of sinks) + bb_xmin : X coordinate of the net's bounding box's bottom-left corner + bb_ymin : Y coordinate of the net's bounding box's bottom-left corner + bb_layer_min : Lowest layer number of the net's bounding box + bb_xmax : X coordinate of the net's bounding box's top-right corner + bb_ymax : Y coordinate of the net's bounding box's top-right corner + bb_layer_max : Highest layer number of the net's bounding box + src_pin_name : Name of the net's source pin + src_pin_slack : Setup slack of the net's source pin + sinks : A semicolon-separated list of sink pin entries, each in the format: + ,, + + Example value for the ``sinks`` field: + ``"U2.B,0.12,0.5;U3.C,0.10,0.6;U4.D,0.08,0.7"`` **Default:** ``off`` diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index 0aec721d76a..f8ae0c6fc67 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -22,17 +22,25 @@ void generate_hold_timing_stats(const std::string& prefix, const BlkLocRegistry& blk_loc_registry); /** - * @brief Generates timing information for each net in atom netlist. For each net, the timing information - * is reported in the following format: - * netname : Fanout : - * (bounding_box_xmin,bounding_box_ymin,bounding_box_layermin),(bounding_box_xmax,bounding_box_ymax,bounding_box_layermax) : - * source_instance : - * : - * : ... + * @brief Generates a CSV report of timing information for each net in the atom netlist. * - * @param prefix The prefix for the report file to be added to filename: report_net_timing.rpt - * @param timing_info Updated timing information - * @param delay_calc Delay calculator + * Each row in the CSV corresponds to a single net and includes: + * - Net name + * - Fanout count + * - Bounding box (xmin, ymin, layer_min, xmax, ymax, layer_max) + * - Source pin name and slack + * - A single "sinks" field that encodes information for all sink pins + * + * The "sinks" field is a semicolon-separated list of all sink pins. + * Each sink pin is represented as a comma-separated triple: + * ,, + * + * Example row: + * netA,2,0,0,0,5,5,1,U1.A,0.25,"U2.B,0.12,0.5;U3.C,0.10,0.6" + * + * @param prefix Prefix for the output file name (report will be saved as report_net_timing.csv) + * @param timing_info Timing analysis results (slacks) + * @param delay_calc Delay calculator used to extract delay between nodes */ void generate_net_timing_report(const std::string& prefix, const SetupHoldTimingInfo& timing_info, From 87d161ca5d6e2ec9b2d88e07d8700e558ffac9c7 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 16 May 2025 13:12:31 -0400 Subject: [PATCH 147/176] [vpr][analysis] print constant nets in the net timing report --- vpr/src/analysis/timing_reports.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index dcb05ea7781..5a0180672d8 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -195,8 +195,6 @@ void generate_net_timing_report_csv(const std::string& prefix, << "src_pin_name,src_pin_slack,sinks" << std::endl; for (const auto& net : atom_netlist.nets()) { - if (atom_netlist.net_is_constant(net)) continue; - const auto& net_name = atom_netlist.net_name(net); const auto& source_pin = *atom_netlist.net_pins(net).begin(); auto source_pin_slack = timing_info.setup_pin_slack(source_pin); From 7649fdd81cd30db9017ef30f759c125b3fadddfc Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 16 May 2025 13:16:07 -0400 Subject: [PATCH 148/176] [vpr][analysis] apply comments --- vpr/src/analysis/timing_reports.cpp | 1 + vpr/src/base/read_options.cpp | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 5a0180672d8..ce90e501fd9 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -197,6 +197,7 @@ void generate_net_timing_report_csv(const std::string& prefix, for (const auto& net : atom_netlist.nets()) { const auto& net_name = atom_netlist.net_name(net); const auto& source_pin = *atom_netlist.net_pins(net).begin(); + // for the driver/source, this is the worst slack to any fanout. auto source_pin_slack = timing_info.setup_pin_slack(source_pin); auto tg_source_node = atom_lookup.atom_pin_tnode(source_pin); VTR_ASSERT(tg_source_node.is_valid()); diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index f092f77ae0d..6b73aa52385 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -3089,7 +3089,10 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .show_in(argparse::ShowIn::HELP_ONLY); analysis_grp.add_argument(args.generate_net_timing_report, "--generate_net_timing_report") - .help("Generates a net timing report for each net in the design.") + .help( + "Generates a net timing report in CSV format, reporting the delay and slack\n" + "for every routed connection in the design.\n" + "The report is saved as 'report_net_timing.csv'.") .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); From f699b3011d67704a562fff8b39ddba389e6d569f Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 16 May 2025 13:25:53 -0400 Subject: [PATCH 149/176] [vpr][analysis] fix function name --- vpr/src/analysis/timing_reports.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index ce90e501fd9..eeffe27e01a 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -180,9 +180,9 @@ void generate_hold_timing_stats(const std::string& prefix, timing_reporter.report_unconstrained_hold(prefix + "report_unconstrained_timing.hold.rpt", *timing_info.hold_analyzer()); } -void generate_net_timing_report_csv(const std::string& prefix, - const SetupHoldTimingInfo& timing_info, - const AnalysisDelayCalculator& delay_calc) { +void generate_net_timing_report(const std::string& prefix, + const SetupHoldTimingInfo& timing_info, + const AnalysisDelayCalculator& delay_calc) { std::ofstream os(prefix + "report_net_timing.csv"); const auto& atom_netlist = g_vpr_ctx.atom().netlist(); const auto& atom_lookup = g_vpr_ctx.atom().lookup(); From aaf2569de4ce34f770f0dd8215859771068cbdd6 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 16 May 2025 13:33:27 -0400 Subject: [PATCH 150/176] [doc] add net timing report use case --- doc/src/vpr/command_line_usage.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 40fc5de3813..1f15da623ff 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1522,6 +1522,8 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout Generates a report that lists the bounding box, slack, and delay of every routed connection in a design in CSV format (``report_net_timing.csv``). Each row in the CSV corresponds to a single net. + The report can later be used by other tools to enable further optimizations. For example, the Synopsys synthesis tool (Synplify) can use this information to re-synthesize the design and improve the Quality of Results (QoR). + Fields in the report are: .. code-block:: none From 33291d362cad9383d9f8125329fd22370a891b01 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 16 May 2025 15:17:11 -0400 Subject: [PATCH 151/176] fix a typo --- doc/src/vpr/command_line_usage.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 1f15da623ff..94c4a4f6d7c 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1527,6 +1527,7 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout Fields in the report are: .. code-block:: none + netname : The name assigned to the net in the atom netlist Fanout : Net's fanout (number of sinks) bb_xmin : X coordinate of the net's bounding box's bottom-left corner From ced55e7cdf0213c85be3a01d009a7842e7e96bca Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Sat, 17 May 2025 00:14:57 -0400 Subject: [PATCH 152/176] [Infra] Cleaned Up Include Files in VPR Base Directory Many include files in the base directory contained includes to other headers which they do not use. This causes many CPP files to include way more header files than they need, increasing the incremental build time. This process needs to be done on the entire VTR repo, but I found that the base directory was one of the biggest culprits of this and the hardest to untangle. --- libs/libarchfpga/src/arch_types.h | 2 +- libs/libarchfpga/src/arch_util.cpp | 2 +- libs/libarchfpga/src/read_xml_arch_file.cpp | 8 ++++---- libs/librrgraph/src/base/rr_graph_storage.cpp | 8 ++++---- .../src/utils/alloc_and_load_rr_indexed_data.cpp | 12 ++++++------ vpr/src/base/CheckArch.cpp | 4 +--- vpr/src/base/CheckArch.h | 2 ++ vpr/src/base/atom_lookup.h | 4 ---- vpr/src/base/atom_netlist.cpp | 1 + vpr/src/base/atom_netlist.h | 1 - vpr/src/base/clock_modeling.cpp | 1 + vpr/src/base/clustered_netlist.cpp | 2 ++ vpr/src/base/clustered_netlist.h | 3 --- vpr/src/base/constant_nets.cpp | 1 + vpr/src/base/constraints_load.h | 4 ---- vpr/src/base/echo_files.h | 2 ++ vpr/src/base/netlist.h | 4 ---- vpr/src/base/netlist.tpp | 1 + vpr/src/base/partition.h | 3 +-- vpr/src/base/partition_region.h | 1 - vpr/src/base/place_and_route.h | 1 - vpr/src/base/read_netlist.h | 4 +++- vpr/src/base/read_options.h | 3 ++- vpr/src/base/read_place.h | 2 ++ vpr/src/base/setup_noc.h | 1 - vpr/src/base/stats.cpp | 2 ++ vpr/src/base/stats.h | 8 +++++--- vpr/src/base/user_route_constraints.cpp | 2 ++ vpr/src/base/user_route_constraints.h | 3 +-- vpr/src/base/vpr_api.h | 4 ---- vpr/src/base/vpr_constraints_reader.cpp | 1 + vpr/src/base/vpr_constraints_serializer.h | 4 +--- vpr/src/base/vpr_context.h | 1 + vpr/src/base/vpr_types.cpp | 1 + vpr/src/base/vpr_types.h | 9 --------- vpr/src/pack/lb_type_rr_graph.cpp | 2 +- vpr/src/pack/noc_aware_cluster_util.cpp | 1 + vpr/src/power/power_sizing.cpp | 1 + vpr/src/route/check_route.cpp | 1 + vpr/src/route/clock_connection_builders.cpp | 1 + vpr/src/route/connection_router.tpp | 3 ++- vpr/src/route/overuse_report.cpp | 1 + vpr/src/route/route.cpp | 2 +- vpr/src/route/route_utilization.cpp | 3 +-- vpr/src/route/route_utils.cpp | 1 + vpr/src/route/router_lookahead_extended_map.cpp | 6 ++---- vpr/src/route/router_lookahead_map_utils.cpp | 1 + vpr/src/route/rr_graph2.cpp | 1 + vpr/test/test_compressed_grid.cpp | 7 +------ 49 files changed, 65 insertions(+), 78 deletions(-) diff --git a/libs/libarchfpga/src/arch_types.h b/libs/libarchfpga/src/arch_types.h index 8ea9c44b67f..bc2e65a4ca2 100644 --- a/libs/libarchfpga/src/arch_types.h +++ b/libs/libarchfpga/src/arch_types.h @@ -16,7 +16,7 @@ #define TOKENS " \t\n" /* Value for UNDEFINED data */ -constexpr int UNDEFINED = -1; +constexpr int ARCH_FPGA_UNDEFINED_VAL = -1; /* Maximum value for minimum channel width to avoid overflows of short data type. */ constexpr int MAX_CHANNEL_WIDTH = 8000; diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index b09bddb0382..ea72d18c6e9 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -444,7 +444,7 @@ t_physical_tile_type get_empty_physical_type(const char* name /*= EMPTY_BLOCK_NA type.capacity = 0; type.num_drivers = 0; type.num_receivers = 0; - type.area = UNDEFINED; + type.area = ARCH_FPGA_UNDEFINED_VAL; type.switchblock_locations = vtr::Matrix({{size_t(type.width), size_t(type.height)}}, e_sb_type::FULL); type.switchblock_switch_overrides = vtr::Matrix({{size_t(type.width), size_t(type.height)}}, DEFAULT_SWITCH); type.is_input_type = false; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 3661516a530..b684a9e834e 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -2887,7 +2887,7 @@ static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pu "Unknown property %s for chan_width_distr x\n", Prop); } - chan->peak = get_attribute(Node, "peak", loc_data).as_float(UNDEFINED); + chan->peak = get_attribute(Node, "peak", loc_data).as_float(ARCH_FPGA_UNDEFINED_VAL); chan->width = get_attribute(Node, "width", loc_data, hasWidth).as_float(0); chan->xpeak = get_attribute(Node, "xpeak", loc_data, hasXpeak).as_float(0); chan->dc = get_attribute(Node, "dc", loc_data, hasDc).as_float(0); @@ -2994,7 +2994,7 @@ static void ProcessTileProps(pugi::xml_node Node, /* Load properties */ PhysicalTileType->width = get_attribute(Node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1); PhysicalTileType->height = get_attribute(Node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1); - PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED); + PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); if (atof(Prop) < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), @@ -4264,8 +4264,8 @@ static std::vector ProcessSwitches(pugi::xml_node Parent, static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data) { /* check if switch node has the Tdel property */ bool has_Tdel_prop = false; - float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED); - if (Tdel_prop_value != UNDEFINED) { + float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); + if (Tdel_prop_value != ARCH_FPGA_UNDEFINED_VAL) { has_Tdel_prop = true; } diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 28da321cc1f..216d3770cac 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -464,7 +464,7 @@ size_t t_rr_graph_storage::count_rr_switches( if (arch_switch_inf[iswitch].fixed_Tdel()) { //If delay is independent of fanin drop the unique fanin info - fanin = UNDEFINED; + fanin = ARCH_FPGA_UNDEFINED_VAL; } if (arch_switch_fanins[iswitch].count(fanin) == 0) { //New fanin for this switch @@ -482,7 +482,7 @@ size_t t_rr_graph_storage::count_rr_switches( for(size_t iswitch = 0; iswitch < arch_switch_counts.size(); ++iswitch) { if(arch_switch_fanins[iswitch].empty()){ if(arch_switch_inf[iswitch].fixed_Tdel()){ - arch_switch_fanins[iswitch][UNDEFINED] = num_rr_switches++; + arch_switch_fanins[iswitch][ARCH_FPGA_UNDEFINED_VAL] = num_rr_switches++; } } } @@ -504,8 +504,8 @@ void t_rr_graph_storage::remap_rr_node_switch_indices(const t_arch_switch_fanin& int switch_index = edge_switch_[edge]; int fanin = node_fan_in_[to_node]; - if (switch_fanin[switch_index].count(UNDEFINED) == 1) { - fanin = UNDEFINED; + if (switch_fanin[switch_index].count(ARCH_FPGA_UNDEFINED_VAL) == 1) { + fanin = ARCH_FPGA_UNDEFINED_VAL; } auto itr = switch_fanin[switch_index].find(fanin); diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index a3d4a554f90..5d65c348205 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -516,7 +516,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, vtr::vector> switch_R_total(rr_indexed_data.size()); vtr::vector> switch_T_total(rr_indexed_data.size()); vtr::vector> switch_Cinternal_total(rr_indexed_data.size()); - vtr::vector switches_buffered(rr_indexed_data.size(), UNDEFINED); + vtr::vector switches_buffered(rr_indexed_data.size(), ARCH_FPGA_UNDEFINED_VAL); /* * Walk through the RR graph and collect all R and C values of all the nodes, @@ -542,7 +542,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, double avg_switch_Cinternal = 0; int num_switches = 0; int num_shorts = 0; - short buffered = UNDEFINED; + short buffered = ARCH_FPGA_UNDEFINED_VAL; calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, num_shorts, buffered, fan_in_list); if (num_switches == 0) { @@ -561,13 +561,13 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, switch_R_total[cost_index].push_back(avg_switch_R); switch_T_total[cost_index].push_back(avg_switch_T); switch_Cinternal_total[cost_index].push_back(avg_switch_Cinternal); - if (buffered == UNDEFINED) { + if (buffered == ARCH_FPGA_UNDEFINED_VAL) { /* this segment does not have any outgoing edges to other general routing wires */ continue; } /* need to make sure all wire switches of a given wire segment type have the same 'buffered' value */ - if (switches_buffered[cost_index] == UNDEFINED) { + if (switches_buffered[cost_index] == ARCH_FPGA_UNDEFINED_VAL) { switches_buffered[cost_index] = buffered; } else { if (switches_buffered[cost_index] != buffered) { @@ -644,7 +644,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou avg_switch_Cinternal = 0; num_switches = 0; num_shorts = 0; - buffered = UNDEFINED; + buffered = ARCH_FPGA_UNDEFINED_VAL; for (const auto& edge : fan_in_list[node]) { /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */ if (rr_graph.node_type(node) == e_rr_type::CHANX || rr_graph.node_type(node) == e_rr_type::CHANY) { @@ -659,7 +659,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou avg_switch_T += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Tdel; avg_switch_Cinternal += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cinternal; - if (buffered == UNDEFINED) { + if (buffered == ARCH_FPGA_UNDEFINED_VAL) { if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).buffered()) { buffered = 1; } else { diff --git a/vpr/src/base/CheckArch.cpp b/vpr/src/base/CheckArch.cpp index 93e77db3429..e37ec0a21f4 100644 --- a/vpr/src/base/CheckArch.cpp +++ b/vpr/src/base/CheckArch.cpp @@ -1,8 +1,6 @@ +#include "arch_util.h" #include "vpr_types.h" #include "vpr_error.h" -#include "globals.h" -#include "echo_files.h" -#include "read_xml_arch_file.h" #include "CheckArch.h" /******** Function Prototypes ********/ diff --git a/vpr/src/base/CheckArch.h b/vpr/src/base/CheckArch.h index d4a617cea32..5b47ded2acb 100644 --- a/vpr/src/base/CheckArch.h +++ b/vpr/src/base/CheckArch.h @@ -1,6 +1,8 @@ #ifndef CHECKARCH_H #define CHECKARCH_H +#include "physical_types.h" + void CheckArch(const t_arch& Arch); #endif diff --git a/vpr/src/base/atom_lookup.h b/vpr/src/base/atom_lookup.h index 8a218fae207..0eedbc7dc41 100644 --- a/vpr/src/base/atom_lookup.h +++ b/vpr/src/base/atom_lookup.h @@ -2,15 +2,11 @@ #define ATOM_LOOKUP_H #include "atom_lookup_fwd.h" -#include - -#include "vtr_bimap.h" #include "vtr_vector_map.h" #include "vtr_range.h" #include "atom_netlist_fwd.h" #include "clustered_netlist_fwd.h" -#include "vpr_types.h" #include "tatum/TimingGraphFwd.hpp" #include "vtr_optional.h" diff --git a/vpr/src/base/atom_netlist.cpp b/vpr/src/base/atom_netlist.cpp index 63132e95500..c0453db3c65 100644 --- a/vpr/src/base/atom_netlist.cpp +++ b/vpr/src/base/atom_netlist.cpp @@ -2,6 +2,7 @@ #include "atom_netlist.h" #include "logic_types.h" +#include "netlist_utils.h" #include "vpr_error.h" #include "vtr_assert.h" diff --git a/vpr/src/base/atom_netlist.h b/vpr/src/base/atom_netlist.h index d7c47b13da0..639af85c428 100644 --- a/vpr/src/base/atom_netlist.h +++ b/vpr/src/base/atom_netlist.h @@ -68,7 +68,6 @@ #include #include -#include "vtr_range.h" #include "vtr_logic.h" #include "vtr_vector_map.h" diff --git a/vpr/src/base/clock_modeling.cpp b/vpr/src/base/clock_modeling.cpp index 3873aca4310..e8d70d69bbd 100644 --- a/vpr/src/base/clock_modeling.cpp +++ b/vpr/src/base/clock_modeling.cpp @@ -1,5 +1,6 @@ #include "clock_modeling.h" #include "globals.h" +#include "vpr_utils.h" #include "vtr_assert.h" void ClockModeling::treat_clock_pins_as_non_globals() { diff --git a/vpr/src/base/clustered_netlist.cpp b/vpr/src/base/clustered_netlist.cpp index 8e446d2b4c8..9bd350b2f9b 100644 --- a/vpr/src/base/clustered_netlist.cpp +++ b/vpr/src/base/clustered_netlist.cpp @@ -2,8 +2,10 @@ #include "globals.h" #include "logic_types.h" #include "physical_types_util.h" +#include "vpr_utils.h" #include "vtr_assert.h" +#include #include /** diff --git a/vpr/src/base/clustered_netlist.h b/vpr/src/base/clustered_netlist.h index e8399484adb..c711b13262a 100644 --- a/vpr/src/base/clustered_netlist.h +++ b/vpr/src/base/clustered_netlist.h @@ -106,9 +106,6 @@ * */ #include "vpr_types.h" -#include "vpr_utils.h" - -#include "vtr_util.h" #include "netlist.h" #include "clustered_netlist_fwd.h" diff --git a/vpr/src/base/constant_nets.cpp b/vpr/src/base/constant_nets.cpp index 36862e490be..cbd92491f25 100644 --- a/vpr/src/base/constant_nets.cpp +++ b/vpr/src/base/constant_nets.cpp @@ -1,5 +1,6 @@ #include "constant_nets.h" +#include "atom_netlist.h" #include "clustered_netlist.h" #include "vtr_assert.h" diff --git a/vpr/src/base/constraints_load.h b/vpr/src/base/constraints_load.h index 783be088a32..bf57b571aac 100644 --- a/vpr/src/base/constraints_load.h +++ b/vpr/src/base/constraints_load.h @@ -1,11 +1,7 @@ #ifndef CONSTRAINTS_LOAD_H_ #define CONSTRAINTS_LOAD_H_ -#include "region.h" -#include "partition.h" -#include "partition_region.h" #include "user_place_constraints.h" -#include "vtr_vector.h" ///@brief Used to print vpr's floorplanning constraints to an echo file "vpr_constraints.echo" void echo_constraints(char* filename, const UserPlaceConstraints& constraints); diff --git a/vpr/src/base/echo_files.h b/vpr/src/base/echo_files.h index 0ebd371fa04..9828ef62ec8 100644 --- a/vpr/src/base/echo_files.h +++ b/vpr/src/base/echo_files.h @@ -1,6 +1,8 @@ #ifndef ECHO_FILES_H #define ECHO_FILES_H +#include + enum e_echo_files { //Input netlist diff --git a/vpr/src/base/netlist.h b/vpr/src/base/netlist.h index 0eb0cb536b6..2af6b3e378f 100644 --- a/vpr/src/base/netlist.h +++ b/vpr/src/base/netlist.h @@ -417,13 +417,9 @@ #include #include #include "vtr_range.h" -#include "vtr_logic.h" #include "vtr_vector_map.h" -#include "logic_types.h" - #include "netlist_fwd.h" -#include "netlist_utils.h" //Forward declaration for private methods template diff --git a/vpr/src/base/netlist.tpp b/vpr/src/base/netlist.tpp index 3987670aa63..5b5563ff16f 100644 --- a/vpr/src/base/netlist.tpp +++ b/vpr/src/base/netlist.tpp @@ -1,6 +1,7 @@ #include #include +#include "netlist_utils.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vpr_error.h" diff --git a/vpr/src/base/partition.h b/vpr/src/base/partition.h index 9c8984b8c86..1772d47a0fc 100644 --- a/vpr/src/base/partition.h +++ b/vpr/src/base/partition.h @@ -4,9 +4,8 @@ #include #include "vtr_strong_id.h" -#include "region.h" -#include "atom_netlist_fwd.h" #include "partition_region.h" + /** * @file * @brief This file defines the data for a partition: a grouping of atoms that are constrained to a portion of an FPGA. diff --git a/vpr/src/base/partition_region.h b/vpr/src/base/partition_region.h index 2e9949fceea..80f3a2f36a7 100644 --- a/vpr/src/base/partition_region.h +++ b/vpr/src/base/partition_region.h @@ -2,7 +2,6 @@ #define PARTITION_REGIONS_H #include "region.h" -#include "atom_netlist_fwd.h" #include "vpr_types.h" /** diff --git a/vpr/src/base/place_and_route.h b/vpr/src/base/place_and_route.h index da27077cfac..935f678841e 100644 --- a/vpr/src/base/place_and_route.h +++ b/vpr/src/base/place_and_route.h @@ -9,7 +9,6 @@ #include "vpr_types.h" #include "timing_info.h" #include "RoutingDelayCalculator.h" -#include "rr_graph.h" struct t_fmap_cell { int fs; /// class PlacerState; +class BlkLocRegistry; +class DeviceGrid; class ClusterBlockId; struct t_block_loc; diff --git a/vpr/src/base/setup_noc.h b/vpr/src/base/setup_noc.h index 9b728e0f0ab..4b11f59259a 100644 --- a/vpr/src/base/setup_noc.h +++ b/vpr/src/base/setup_noc.h @@ -32,7 +32,6 @@ */ #include -#include #include "device_grid.h" #include "vpr_context.h" diff --git a/vpr/src/base/stats.cpp b/vpr/src/base/stats.cpp index dbd88cebb0b..109147e337b 100644 --- a/vpr/src/base/stats.cpp +++ b/vpr/src/base/stats.cpp @@ -6,8 +6,10 @@ #include #include +#include "physical_types.h" #include "physical_types_util.h" #include "route_tree.h" +#include "vpr_utils.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_ndmatrix.h" diff --git a/vpr/src/base/stats.h b/vpr/src/base/stats.h index 5f9e50e0700..eb79a2c3946 100644 --- a/vpr/src/base/stats.h +++ b/vpr/src/base/stats.h @@ -1,9 +1,11 @@ #pragma once + +#include #include -#include -#include -#include "vpr_types.h" #include "netlist.h" +#include "rr_graph_type.h" + +class DeviceGrid; /** * @brief Prints out various statistics about the current routing. diff --git a/vpr/src/base/user_route_constraints.cpp b/vpr/src/base/user_route_constraints.cpp index b6d3f1b0384..fa97ed6163c 100644 --- a/vpr/src/base/user_route_constraints.cpp +++ b/vpr/src/base/user_route_constraints.cpp @@ -1,4 +1,6 @@ #include "user_route_constraints.h" +#include +#include "vpr_error.h" void UserRouteConstraints::add_route_constraint(std::string net_name, RoutingScheme route_scheme) { route_constraints_.insert({net_name, route_scheme}); diff --git a/vpr/src/base/user_route_constraints.h b/vpr/src/base/user_route_constraints.h index 62ba08cda1d..0510072a36a 100644 --- a/vpr/src/base/user_route_constraints.h +++ b/vpr/src/base/user_route_constraints.h @@ -2,9 +2,8 @@ #define USER_ROUTE_CONSTRAINTS_H #include "clock_modeling.h" -#include "vpr_error.h" +#include #include -#include /** * @brief This class specifies a routing scheme for a global net. diff --git a/vpr/src/base/vpr_api.h b/vpr/src/base/vpr_api.h index 54d4f8bf5c6..02fb56a46b4 100644 --- a/vpr/src/base/vpr_api.h +++ b/vpr/src/base/vpr_api.h @@ -31,10 +31,6 @@ #include "physical_types.h" #include "vpr_types.h" #include "read_options.h" -#include "globals.h" -#include "read_xml_arch_file.h" -#include "vpr_utils.h" -#include "place_macro.h" #include "timing_info_fwd.h" #include "echo_files.h" #include "RoutingDelayCalculator.h" diff --git a/vpr/src/base/vpr_constraints_reader.cpp b/vpr/src/base/vpr_constraints_reader.cpp index 57c17d73019..f4a806deeb3 100644 --- a/vpr/src/base/vpr_constraints_reader.cpp +++ b/vpr/src/base/vpr_constraints_reader.cpp @@ -1,3 +1,4 @@ +#include "constraints_load.h" #include "vpr_constraints_serializer.h" #include "vpr_constraints_uxsdcxx.h" diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index 409a7702661..08d6bee73cb 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -1,14 +1,12 @@ #ifndef VPR_CONSTRAINTS_SERIALIZER_H_ #define VPR_CONSTRAINTS_SERIALIZER_H_ +#include #include "region.h" #include "vpr_constraints.h" #include "partition.h" #include "partition_region.h" -#include "echo_files.h" -#include "constraints_load.h" #include "vtr_log.h" -#include "vtr_error.h" #include "globals.h" //for the g_vpr_ctx #include "clock_modeling.h" diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 3a5ca67df21..2f225b01149 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -11,6 +11,7 @@ #include "user_place_constraints.h" #include "user_route_constraints.h" #include "vpr_types.h" +#include "vtr_cache.h" #include "vtr_optional.h" #include "vtr_vector.h" #include "vtr_vector_map.h" diff --git a/vpr/src/base/vpr_types.cpp b/vpr/src/base/vpr_types.cpp index 4d97816558b..84437530f1c 100644 --- a/vpr/src/base/vpr_types.cpp +++ b/vpr/src/base/vpr_types.cpp @@ -3,6 +3,7 @@ #include "vpr_types.h" #include "globals.h" #include "logic_types.h" +#include "vpr_utils.h" t_ext_pin_util_targets::t_ext_pin_util_targets(float default_in_util, float default_out_util) { defaults_.input_pin_util = default_in_util; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 180c236112b..ea8ea024814 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -24,12 +24,9 @@ #pragma once #include -#include -#include #include #include #include "ap_flow_enums.h" -#include "arch_types.h" #include "atom_netlist_fwd.h" #include "clustered_netlist_fwd.h" #include "constant_nets.h" @@ -37,18 +34,12 @@ #include "heap_type.h" #include "vtr_assert.h" -#include "vtr_ndmatrix.h" #include "vtr_vector.h" -#include "vtr_util.h" #include "vtr_flat_map.h" -#include "vtr_cache.h" -#include "vtr_string_view.h" -#include "vtr_dynamic_bitset.h" #include "rr_node_types.h" #include "rr_graph_fwd.h" #include "rr_graph_cost.h" #include "rr_graph_type.h" -#include "vtr_vector_map.h" /******************************************************************************* * Global data types and constants diff --git a/vpr/src/pack/lb_type_rr_graph.cpp b/vpr/src/pack/lb_type_rr_graph.cpp index 99a859c3aba..bb93177ffd2 100644 --- a/vpr/src/pack/lb_type_rr_graph.cpp +++ b/vpr/src/pack/lb_type_rr_graph.cpp @@ -23,8 +23,8 @@ #include #include +#include "vpr_utils.h" #include "vtr_assert.h" -#include "vtr_memory.h" #include "vtr_util.h" #include "physical_types.h" diff --git a/vpr/src/pack/noc_aware_cluster_util.cpp b/vpr/src/pack/noc_aware_cluster_util.cpp index 3b14608d47a..27ef2a49e94 100644 --- a/vpr/src/pack/noc_aware_cluster_util.cpp +++ b/vpr/src/pack/noc_aware_cluster_util.cpp @@ -4,6 +4,7 @@ #include "globals.h" #include "logic_types.h" #include "vpr_types.h" +#include "vpr_utils.h" #include diff --git a/vpr/src/power/power_sizing.cpp b/vpr/src/power/power_sizing.cpp index 31738a8eb6e..37f06028dc3 100644 --- a/vpr/src/power/power_sizing.cpp +++ b/vpr/src/power/power_sizing.cpp @@ -24,6 +24,7 @@ #include #include +#include "arch_types.h" #include "logic_types.h" #include "vtr_util.h" #include "vtr_assert.h" diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index 0eeae4e86cc..51fdc4603cb 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -3,6 +3,7 @@ #include "physical_types_util.h" #include "route_common.h" +#include "vpr_utils.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_time.h" diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp index 5a2455bdaa1..074e3b7565c 100644 --- a/vpr/src/route/clock_connection_builders.cpp +++ b/vpr/src/route/clock_connection_builders.cpp @@ -3,6 +3,7 @@ #include "globals.h" #include "arch_util.h" #include "rr_rc_data.h" +#include "vpr_utils.h" #include #include diff --git a/vpr/src/route/connection_router.tpp b/vpr/src/route/connection_router.tpp index baadcd644f2..f74b213235f 100644 --- a/vpr/src/route/connection_router.tpp +++ b/vpr/src/route/connection_router.tpp @@ -3,8 +3,9 @@ #include "connection_router.h" #include -#include "rr_graph.h" +#include "describe_rr_node.h" #include "rr_graph_fwd.h" +#include "vpr_utils.h" /** Used for the flat router. The node isn't relevant to the target if * it is an intra-block node outside of our target block */ diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 028a4e85e70..c8c2b6135a4 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -2,6 +2,7 @@ #include #include "physical_types_util.h" +#include "vpr_utils.h" #include "vtr_log.h" /** diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index ca1589fdeaa..8bc82be0052 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -7,9 +7,9 @@ #include "route.h" #include "route_common.h" #include "route_debug.h" -#include "route_export.h" #include "route_profiling.h" #include "route_utils.h" +#include "rr_graph.h" #include "vtr_time.h" bool route(const Netlist<>& net_list, diff --git a/vpr/src/route/route_utilization.cpp b/vpr/src/route/route_utilization.cpp index 53badb9297c..bb9c5e736e3 100644 --- a/vpr/src/route/route_utilization.cpp +++ b/vpr/src/route/route_utilization.cpp @@ -1,7 +1,6 @@ #include "route_utilization.h" #include "globals.h" -#include "draw_types.h" -#include "draw_global.h" +#include "vpr_utils.h" vtr::Matrix calculate_routing_usage(e_rr_type rr_type, bool is_flat, bool is_print) { VTR_ASSERT(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index c5f498a9500..198d64197e7 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -15,6 +15,7 @@ #include "route_debug.h" #include "VprTimingGraphResolver.h" +#include "rr_graph.h" #include "tatum/TimingReporter.hpp" bool check_net_delays(const Netlist<>& net_list, NetPinsMatrix& net_delay) { diff --git a/vpr/src/route/router_lookahead_extended_map.cpp b/vpr/src/route/router_lookahead_extended_map.cpp index 8ae1c02f708..0dabadb438b 100644 --- a/vpr/src/route/router_lookahead_extended_map.cpp +++ b/vpr/src/route/router_lookahead_extended_map.cpp @@ -4,15 +4,13 @@ #include #include "connection_router_interface.h" -#include "rr_node.h" +#include "describe_rr_node.h" #include "router_lookahead_map_utils.h" #include "router_lookahead_sampling.h" #include "globals.h" -#include "vtr_math.h" +#include "vpr_utils.h" #include "vtr_time.h" #include "vtr_geometry.h" -#include "echo_files.h" -#include "rr_graph.h" #include "route_common.h" #include "route_debug.h" diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index ce3e484f90a..782c4ed5d91 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -14,6 +14,7 @@ #include "globals.h" #include "physical_types_util.h" #include "vpr_context.h" +#include "vpr_utils.h" #include "vtr_math.h" #include "vtr_time.h" #include "route_common.h" diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 7bc71b57a78..acb094fa8da 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -2,6 +2,7 @@ #include "describe_rr_node.h" #include "physical_types_util.h" +#include "vpr_utils.h" #include "vtr_util.h" #include "vtr_assert.h" diff --git a/vpr/test/test_compressed_grid.cpp b/vpr/test/test_compressed_grid.cpp index 028a1164af9..cd65133ca5c 100644 --- a/vpr/test/test_compressed_grid.cpp +++ b/vpr/test/test_compressed_grid.cpp @@ -1,15 +1,10 @@ +#include "arch_util.h" #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "compressed_grid.h" #include "globals.h" #include "physical_types.h" -// for comparing floats -#include "vtr_math.h" - -#include - namespace { void set_type_tile_to_empty(const int x, const int y, vtr::NdMatrix& grid) { From 8f770d000ca9a417c85a6b8aeedc780ee7fcde55 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Sat, 17 May 2025 15:53:51 -0400 Subject: [PATCH 153/176] [Infra] Cleaned Up Header Files in Pack Folder Went through the header files in the pack folder and resolved any unused header files. --- vpr/src/pack/atom_pb_bimap.cpp | 1 - vpr/src/pack/cluster_feasibility_filter.cpp | 6 +----- vpr/src/pack/cluster_feasibility_filter.h | 3 ++- vpr/src/pack/cluster_placement.cpp | 1 - vpr/src/pack/cluster_router.cpp | 1 - vpr/src/pack/cluster_router.h | 4 ++++ vpr/src/pack/cluster_util.cpp | 1 - vpr/src/pack/pack_report.cpp | 1 - vpr/src/pack/pack_types.h | 3 +-- vpr/src/pack/pb_type_graph.cpp | 4 ---- vpr/src/pack/pb_type_graph.h | 2 ++ vpr/src/pack/pb_type_graph_annotations.cpp | 8 ++------ vpr/src/pack/pb_type_graph_annotations.h | 2 ++ vpr/src/pack/sync_netlists_to_routing_flat.h | 2 -- vpr/src/pack/verify_flat_placement.cpp | 1 - 15 files changed, 14 insertions(+), 26 deletions(-) diff --git a/vpr/src/pack/atom_pb_bimap.cpp b/vpr/src/pack/atom_pb_bimap.cpp index df837cfea6b..bb9cb70946f 100644 --- a/vpr/src/pack/atom_pb_bimap.cpp +++ b/vpr/src/pack/atom_pb_bimap.cpp @@ -8,7 +8,6 @@ */ #include "atom_pb_bimap.h" -#include "atom_netlist.h" AtomPBBimap::AtomPBBimap(const vtr::bimap& atom_to_pb) { atom_to_pb_ = atom_to_pb; diff --git a/vpr/src/pack/cluster_feasibility_filter.cpp b/vpr/src/pack/cluster_feasibility_filter.cpp index dec597aa41e..86e4d13906b 100644 --- a/vpr/src/pack/cluster_feasibility_filter.cpp +++ b/vpr/src/pack/cluster_feasibility_filter.cpp @@ -28,16 +28,12 @@ */ #include +#include "physical_types.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vtr_memory.h" -#include "read_xml_arch_file.h" -#include "vpr_types.h" -#include "globals.h" #include "hash.h" #include "cluster_feasibility_filter.h" -#include "vpr_utils.h" /* header functions that identify pin classes */ static void alloc_pin_classes_in_pb_graph_node(t_pb_graph_node* pb_graph_node); diff --git a/vpr/src/pack/cluster_feasibility_filter.h b/vpr/src/pack/cluster_feasibility_filter.h index b6c9cebffd5..e56f3a67a90 100644 --- a/vpr/src/pack/cluster_feasibility_filter.h +++ b/vpr/src/pack/cluster_feasibility_filter.h @@ -21,7 +21,8 @@ #ifndef CLUSTER_FEASIBILITY_CHECK_H #define CLUSTER_FEASIBILITY_CHECK_H -#include "arch_types.h" + +class t_pb_graph_node; void load_pin_classes_in_pb_graph_head(t_pb_graph_node* pb_graph_node); diff --git a/vpr/src/pack/cluster_placement.cpp b/vpr/src/pack/cluster_placement.cpp index 297212c4ff1..fb2cb5298f5 100644 --- a/vpr/src/pack/cluster_placement.cpp +++ b/vpr/src/pack/cluster_placement.cpp @@ -21,7 +21,6 @@ #include "hash.h" #include "physical_types.h" #include "prepack.h" -#include "vpr_types.h" #include "vpr_utils.h" #include "vtr_assert.h" diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index db2c58d6da9..1f08f5d3ea1 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -24,7 +24,6 @@ #include "vpr_error.h" #include "vpr_types.h" -#include "echo_files.h" #include "physical_types.h" #include "globals.h" diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index cd68f7eea38..40d689b514d 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -6,9 +6,13 @@ */ #ifndef CLUSTER_ROUTER_H #define CLUSTER_ROUTER_H + #include #include "atom_netlist_fwd.h" +#include "atom_pb_bimap.h" #include "pack_types.h" +#include "vpr_types.h" +#include "vpr_utils.h" /* Constructors/Destructors */ t_lb_router_data* alloc_and_load_router_data(std::vector* lb_type_graph, t_logical_block_type_ptr type); diff --git a/vpr/src/pack/cluster_util.cpp b/vpr/src/pack/cluster_util.cpp index 1ed359ca0c1..60c67f3c7d1 100644 --- a/vpr/src/pack/cluster_util.cpp +++ b/vpr/src/pack/cluster_util.cpp @@ -12,7 +12,6 @@ #include "prepack.h" #include "vpr_context.h" #include "vtr_vector.h" -#include "vtr_vector_map.h" /*Print the contents of each cluster to an echo file*/ static void echo_clusters(char* filename, const ClusterLegalizer& cluster_legalizer) { diff --git a/vpr/src/pack/pack_report.cpp b/vpr/src/pack/pack_report.cpp index 2dded7cda8b..154b75258a0 100644 --- a/vpr/src/pack/pack_report.cpp +++ b/vpr/src/pack/pack_report.cpp @@ -2,7 +2,6 @@ #include "vtr_ostream_guard.h" -#include "vpr_types.h" #include "vpr_utils.h" #include "histogram.h" diff --git a/vpr/src/pack/pack_types.h b/vpr/src/pack/pack_types.h index 8ebaf22b26b..994dbd73f1f 100644 --- a/vpr/src/pack/pack_types.h +++ b/vpr/src/pack/pack_types.h @@ -10,9 +10,8 @@ #include #include -#include "arch_types.h" #include "atom_netlist_fwd.h" -#include "attraction_groups.h" +#include "physical_types.h" struct t_pack_molecule; diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 6bd874f6e2b..62055d7e192 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -13,7 +13,6 @@ #include #include -#include #include #include "vtr_util.h" @@ -23,7 +22,6 @@ #include "vtr_token.h" #include "vpr_error.h" -#include "vpr_types.h" #include "physical_types.h" #include "globals.h" @@ -31,8 +29,6 @@ #include "pb_type_graph.h" #include "pb_type_graph_annotations.h" #include "cluster_feasibility_filter.h" -#include "power.h" -#include "read_xml_arch_file.h" /* variable global to this section that indexes each pb graph pin within a cluster */ static vtr::t_linked_vptr* edges_head; diff --git a/vpr/src/pack/pb_type_graph.h b/vpr/src/pack/pb_type_graph.h index f2d8cdeb5d9..cda5bdf1696 100644 --- a/vpr/src/pack/pb_type_graph.h +++ b/vpr/src/pack/pb_type_graph.h @@ -1,6 +1,8 @@ #ifndef PB_TYPE_GRAPH_H #define PB_TYPE_GRAPH_H +#include "physical_types.h" + struct t_pb_graph_edge_comparator { int input_pin_id_in_cluster; int output_pin_id_in_cluster; diff --git a/vpr/src/pack/pb_type_graph_annotations.cpp b/vpr/src/pack/pb_type_graph_annotations.cpp index a01fec982b5..e0988af7143 100644 --- a/vpr/src/pack/pb_type_graph_annotations.cpp +++ b/vpr/src/pack/pb_type_graph_annotations.cpp @@ -2,24 +2,20 @@ * April 15, 2011 * Loads statistical information (min/max delays, power) onto the pb_graph. */ +#include #include #include #include +#include "arch_util.h" #include "vtr_assert.h" #include "vtr_util.h" -#include "vtr_memory.h" #include "vtr_token.h" -#include "vpr_types.h" #include "vpr_error.h" -#include "arch_types.h" -#include "globals.h" -#include "vpr_utils.h" #include "pb_type_graph.h" #include "pb_type_graph_annotations.h" -#include "read_xml_arch_file.h" static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const char* value); diff --git a/vpr/src/pack/pb_type_graph_annotations.h b/vpr/src/pack/pb_type_graph_annotations.h index 3f93d96fa14..317f63b394c 100644 --- a/vpr/src/pack/pb_type_graph_annotations.h +++ b/vpr/src/pack/pb_type_graph_annotations.h @@ -7,6 +7,8 @@ #ifndef PB_TYPE_GRAPH_ANNOTATIONS_H #define PB_TYPE_GRAPH_ANNOTATIONS_H +class t_pb_graph_node; + void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node); #endif diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.h b/vpr/src/pack/sync_netlists_to_routing_flat.h index 0c1bc7d77d3..ef6b743fe30 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.h +++ b/vpr/src/pack/sync_netlists_to_routing_flat.h @@ -1,5 +1,3 @@ -#include "netlist.h" - /******************************************************************** * Top-level function to synchronize packing results to routing results. * Flat routing invalidates the ClusteredNetlist since nets may be routed diff --git a/vpr/src/pack/verify_flat_placement.cpp b/vpr/src/pack/verify_flat_placement.cpp index 76a893d66a6..59bb36bbbf8 100644 --- a/vpr/src/pack/verify_flat_placement.cpp +++ b/vpr/src/pack/verify_flat_placement.cpp @@ -4,7 +4,6 @@ #include "atom_netlist.h" #include "atom_netlist_fwd.h" #include "prepack.h" -#include "vpr_types.h" #include "vtr_log.h" unsigned verify_flat_placement_for_packing(const FlatPlacementInfo& flat_placement_info, From 175da0016fb038ebbfcf9e1d1f77d83900284001 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Sat, 17 May 2025 16:12:10 -0400 Subject: [PATCH 154/176] [AP] Removed Old Cluster-Level AP Flow Prior to the flat AP flow, a cluster-level AP flow existed in VPR which performed a SimPL-style algorithm on the clusters created during packing before performing a placement quench. Although well-written, this flow was not shown to outperform the SA placer in VPR. It has also been becoming confusing to keep in VPR since the new flat AP flow supercedes it. It is unclear if a cluster-level AP flow will work well with the flat AP flow; however in that case the cluster-level AP flow would be made using the new AP APIs written. Removed the old cluster-level AP flow to reduce confusion. --- CMakeLists.txt | 3 - vpr/CMakeLists.txt | 15 - vpr/src/base/SetupVPR.cpp | 1 - vpr/src/base/read_options.cpp | 7 - vpr/src/base/read_options.h | 1 - vpr/src/base/vpr_types.h | 8 - vpr/src/place/analytic_placer.cpp | 865 ------------ vpr/src/place/analytic_placer.h | 326 ----- vpr/src/place/cut_spreader.cpp | 1174 ----------------- vpr/src/place/cut_spreader.h | 378 ------ vpr/src/place/placer.cpp | 20 - .../strong_analytic_placer/config/config.txt | 28 - .../config/golden_results.txt | 2 - .../vtr_reg_strong/task_list.txt | 1 - .../strong_analytic_placer/config/config.txt | 28 - .../config/golden_results.txt | 2 - .../vtr_reg_strong_odin/task_list.txt | 1 - 17 files changed, 2860 deletions(-) delete mode 100644 vpr/src/place/analytic_placer.cpp delete mode 100644 vpr/src/place/analytic_placer.h delete mode 100644 vpr/src/place/cut_spreader.cpp delete mode 100644 vpr/src/place/cut_spreader.h delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/config.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/config.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index 5a1a2150b84..8f86cefb295 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -42,9 +42,6 @@ option(VTR_ENABLE_CAPNPROTO "Enable capnproto binary serialization support in VP #Allow the user to decide whether to compile the server module option(VPR_USE_SERVER "Specify whether vpr enables the server mode" ON) -#Allow the user to enable/disable VPR analytic placement -#VPR option --enable_analytic_placer is also required for Analytic Placement -option(VPR_ANALYTIC_PLACE "Enable analytic placement in VPR." ON) option(VPR_ENABLE_INTERCHANGE "Enable FPGA interchange." ON) option(VPR_ENABLE_NOC_SAT_ROUTING "Enable NoC SAT routing." OFF) diff --git a/vpr/CMakeLists.txt b/vpr/CMakeLists.txt index 67d9bcbd25c..530928ac612 100644 --- a/vpr/CMakeLists.txt +++ b/vpr/CMakeLists.txt @@ -91,21 +91,6 @@ else () message(STATUS "Eigen3: Not Found. Some features may be disabled.") endif (TARGET Eigen3::Eigen) -#VPR_ANALYTIC_PLACE is initialized in the root CMakeLists -# NOTE: This is the cluster-level Analytical Placement which existed before the -# flat Analytical Placement flow. -if(${VPR_ANALYTIC_PLACE}) - message(STATUS "VPR Analytic Placement: Requested") - if (TARGET Eigen3::Eigen) - message(STATUS "VPR Analytic Placement dependency (Eigen3): Found") - message(STATUS "VPR Analytic Placement: Enabled") - target_compile_definitions(libvpr PUBLIC -DENABLE_ANALYTIC_PLACE) - else () - message(STATUS "VPR Analytic Placement dependency (Eigen3): Not Found (Download manually with sudo apt install libeigen3-dev, and rebuild)") - message(STATUS "VPR Analytic Placement: Disabled") - endif(TARGET Eigen3::Eigen) -endif() - if (${VPR_ENABLE_NOC_SAT_ROUTING}) message(STATUS "VPR NoC SAT Routing: Requested") find_package(ortools CONFIG REQUIRED) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 3c5d7e06d1e..676f6378bda 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -673,7 +673,6 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts) PlacerOpts->effort_scaling = Options.place_effort_scaling; PlacerOpts->timing_update_type = Options.timing_update_type; - PlacerOpts->enable_analytic_placer = Options.enable_analytic_placer; PlacerOpts->place_static_move_prob = vtr::vector(Options.place_static_move_prob.value().begin(), Options.place_static_move_prob.value().end()); PlacerOpts->place_high_fanout_net = Options.place_high_fanout_net; diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 6b73aa52385..553a964d306 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -2244,13 +2244,6 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); - place_grp.add_argument(args.enable_analytic_placer, "--enable_analytic_placer") - .help( - "Enables the analytic placer. " - "Once analytic placement is done, the result is passed through the quench phase of the annealing placer for local improvement") - .default_value("false") - .show_in(argparse::ShowIn::HELP_ONLY); - place_grp.add_argument(args.place_static_move_prob, "--place_static_move_prob") .help( "The percentage probabilities of different moves in Simulated Annealing placement. " diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index bc162194461..5e26d36725b 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -139,7 +139,6 @@ struct t_options { argparse::ArgValue placement_saves_per_temperature; argparse::ArgValue place_effort_scaling; argparse::ArgValue place_delta_delay_matrix_calculation_method; - argparse::ArgValue enable_analytic_placer; argparse::ArgValue> place_static_move_prob; argparse::ArgValue place_high_fanout_net; argparse::ArgValue place_bounding_box_mode; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index ea8ea024814..c9b17f94ce9 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1071,14 +1071,6 @@ struct t_placer_opts { std::string allowed_tiles_for_delay_model; e_place_delta_delay_algorithm place_delta_delay_matrix_calculation_method; - - /* - * @brief enables the analytic placer. - * - * Once analytic placement is done, the result is passed through the quench phase - * of the annealing placer for local improvement - */ - bool enable_analytic_placer; }; /****************************************************************** diff --git a/vpr/src/place/analytic_placer.cpp b/vpr/src/place/analytic_placer.cpp deleted file mode 100644 index e460c5bd58f..00000000000 --- a/vpr/src/place/analytic_placer.cpp +++ /dev/null @@ -1,865 +0,0 @@ -#include "place_macro.h" -#ifdef ENABLE_ANALYTIC_PLACE - -#include "analytic_placer.h" - -// The eigen library contains a warning in GCC13 for a null dereference. This -// causes the CI build to fail due to the warning. Ignoring the warning for -// these include files. Using push to return to the state of GCC diagnostics. -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wnull-dereference" -#include -#include -// Pop the GCC diagnostics state back to what it was before. -#pragma GCC diagnostic pop - -#include -#include -#include - -#include "vpr_types.h" -#include "vtr_time.h" -#include "read_place.h" -#include "globals.h" -#include "vtr_log.h" -#include "cut_spreader.h" -#include "vpr_utils.h" -#include "place_util.h" - -// Templated struct for constructing and solving matrix equations in analytic placer -template -struct EquationSystem { - EquationSystem(size_t rows, size_t cols) { - A.resize(cols); - rhs.resize(rows); - } - - // A[col] is an entire column of the sparse matrix - // each entry in A[col][index] is a pair with {row_number, matrix value}. - // - // The strategy of skipping 0 row entries in each column enables easy conversion to - // Compressed Column Storage scheme supported by Eigen to reduce memory consumption - // and increase performance - std::vector>> A; - // right hand side vector, i.e. b in Ax = b - std::vector rhs; - - // System of equation is reset by: - // Clearing all entries in A's column, but size of A (number of columns) is preserved - // right hand side vector is set to default value of its templated type - void reset() { - for (auto& col : A) - col.clear(); - std::fill(rhs.begin(), rhs.end(), T()); - } - - // Add val to the matrix entry at (row, col) - // create entry if it doesn't exist - void add_coeff(int row, int col, T val) { - auto& A_col = A.at(col); - // Binary search for the row entry in column col - int begin_i = 0, end_i = int(A_col.size()) - 1; - while (begin_i <= end_i) { - int i = (begin_i + end_i) / 2; - if (A_col.at(i).first == row) { - A_col.at(i).second += val; - return; - } - if (A_col.at(i).first > row) - end_i = i - 1; - else - begin_i = i + 1; - } - A_col.insert(A_col.begin() + begin_i, std::make_pair(row, val)); - } - - // Add val to the "row"-th entry of right hand side vector - void add_rhs(int row, T val) { rhs[row] += val; } - - // Solving Ax = b, using current x as an initial guess, returns x by reference. - // (x must be of correct size, A and rhs must have their entries filled in) - // tolerance is residual error from solver: |Ax-b|/|b|, 1e-5 works well, - // can be tuned in ap_cfg in AnalyticPlacer constructor - void solve(std::vector& x, float tolerance) { - using namespace Eigen; - - VTR_ASSERT(x.size() == A.size()); - - // Converting A into SparseMatrix format from Eigen - VectorXd vec_x_guess(x.size()), vec_rhs(rhs.size()); - SparseMatrix mat(A.size(), A.size()); - - std::vector colnnz; // vector containing number of entries in each column - for (auto& A_col : A) - colnnz.push_back(int(A_col.size())); - mat.reserve(colnnz); // reserve memory for mat depending on number of entries in each row - for (int col = 0; col < int(A.size()); col++) { - auto& A_col = A.at(col); - for (auto& row_entry : A_col) - mat.insert(row_entry.first, col) = row_entry.second; - } - - // use current value of x as guess for iterative solver - for (int i_row = 0; i_row < int(x.size()); i_row++) - vec_x_guess[i_row] = x.at(i_row); - - for (int i_row = 0; i_row < int(rhs.size()); i_row++) - vec_rhs[i_row] = rhs.at(i_row); - - ConjugateGradient, Lower | Upper> solver; - solver.setTolerance(tolerance); - VectorXd x_res = solver.compute(mat).solveWithGuess(vec_rhs, vec_x_guess); - for (int i_row = 0; i_row < int(x.size()); i_row++) - x.at(i_row) = x_res[i_row]; - } -}; - -// Stop optimizing once this many iterations of solve-legalize lead to negligible wirelength improvement -constexpr int HEAP_STALLED_ITERATIONS_STOP = 15; - -/* - * AnalyticPlacer constructor - * Currently only initializing AP configuration parameters - * Placement & device info is accessed via g_vpr_ctx - */ - -AnalyticPlacer::AnalyticPlacer(BlkLocRegistry& blk_loc_registry, - const PlaceMacros& place_macros) - : blk_loc_registry_ref_(blk_loc_registry) - , place_macros_(place_macros) { - //Eigen::initParallel(); - - // TODO: PlacerHeapCfg should be externally configured & supplied - // TODO: tune these parameters for better performance - ap_cfg.alpha = 0.1; // anchoring strength, after first AP iteration the legal position of each block - // becomes anchors. In the next AP iteration, pseudo-connection between each blocks - // current location and its anchor is formed with strength (alph * iter) - // @see build_equations() - - ap_cfg.beta = 1; // utilization factor, <= 1, used to determine if a cut-spreading region is - // overutilized with the formula: bool overutilized = (num_blks / num_tiles) > beta - // for beta < 1, a region must have more tiles than logical blks to not be overutilized - - ap_cfg.solverTolerance = 1e-5; // solver parameter, refers to residual error from solver, defined as |Ax-b|/|b| - - ap_cfg.buildSolveIter = 5; // number of build-solve iteration when calculating placement, used in - // build_solve_direction() - // for each build-solve iteration, the solution from previous build-solve iteration - // is used as a guess for the iterative solver. therefore more buildSolveIter should - // should improve result at the expense of runtime - - // following two parameters are used in CutSpreader::expand_regions(). - // they determine the number of steps to expand in x or y direction before switching to expand in the other direction. - ap_cfg.spread_scale_x = 1; - ap_cfg.spread_scale_y = 1; - - // following two timing parameters are used to add timing weights in matrix equation, currently not used - // see comment in add_pin_to_pin_connection() for usage - ap_cfg.criticalityExponent = 1; - ap_cfg.timingWeight = 10; -} - -/* - * Main function of analytic placement - * Takes the random initial placement from place.cpp through g_vpr_ctx - * Repeat the following until stopping criteria is met: - * * Formulate and solve equations in x & y directions for 1 type of logical block - * * Instantiate CutSpreader to spread and strict_legalize - * - * The final legal placement is passed back to annealer in g_vpr_ctx.mutable_placement() - */ -void AnalyticPlacer::ap_place() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - vtr::ScopedStartFinishTimer timer("Analytic Placement"); - - init(); // transfer placement from g_vpr_ctx to AnalyticPlacer data members - build_legal_locations(); - int hpwl = total_hpwl(); - VTR_LOG("Creating analytic placement for %d cells, random placement hpwl = %d.\n", - int(clb_nlist.blocks().size()), int(hpwl)); - - // the order in which different logical block types are placed; - // going through ap_runs once completes 1 iteration of AP - std::vector ap_runs; - std::unordered_set all_blktypes; // set of all logical block types - - // setup ap_runs, run build/solve/legalize once for every block type - // each type is placed separately, but influenced by the current location of other types - for (auto blk : place_blks) { - if (!all_blktypes.count(clb_nlist.block_type(blk))) { - ap_runs.push_back(clb_nlist.block_type(blk)); - all_blktypes.insert(clb_nlist.block_type(blk)); - } - } - - // setup and solve matrix multiple times for all logic block types before main loop - // this helps eliminating randomness from initial placement (when placing one block type, the random placement - // of the other types may have residual effect on the result, since not all blocks are solved at the same time) - for (int i = 0; i < 1; i++) { // can tune number of iterations - for (auto run : ap_runs) { - build_solve_type(run, -1); - } - } - - int iter = 0, stalled = 0; - // variables for stats - int solved_hpwl = 0, spread_hpwl = 0, legal_hpwl = 0, best_hpwl = std::numeric_limits::max(); - float iter_start, iter_t, run_start, run_t, solve_t, spread_start, spread_t, legal_start, legal_t; - - print_AP_status_header(); - - // main loop for AP - // stopping criteria: stop after HEAP_STALLED_ITERATIONS_STOP iterations of no improvement - while (stalled < HEAP_STALLED_ITERATIONS_STOP) { - // TODO: investigate better stopping criteria - iter_start = timer.elapsed_sec(); - for (auto blk_type : ap_runs) { // for each type of logic blocks - run_start = timer.elapsed_sec(); - - // lower bound placement for blk_type - // build and solve matrix equation for blocks of type "blk_type" in both x and y directions - build_solve_type(blk_type, iter); - solve_t = timer.elapsed_sec() - run_start; - solved_hpwl = total_hpwl(); - // lower bound placement complete - - // upper bound placement - // cut-spreading logic blocks of type "blk_type", this will mostly legalize lower bound placement - spread_start = timer.elapsed_sec(); - CutSpreader spreader{this, blk_type}; // Legalizer - if (blk_type->name != "io") { - /* skip cut-spreading for IO blocks; they tend to cluster on 1 edge of the FPGA due to how cut-spreader works - * in HeAP, cut-spreading is invoked only on LUT, DSP, RAM etc. - * here, greedy legalization by spreader.strict_legalize() should be sufficient for IOs - */ - spreader.cutSpread(); - update_macros(); - spread_hpwl = total_hpwl(); - spread_t = timer.elapsed_sec() - spread_start; - } else { - spread_hpwl = -1; - spread_t = 0; - } - - // greedy legalizer for fully legal placement - legal_start = timer.elapsed_sec(); - spreader.strict_legalize(); // greedy legalization snaps blocks to the closest legal location - update_macros(); - legal_t = timer.elapsed_sec() - legal_start; - legal_hpwl = total_hpwl(); - - // upper bound placement complete - - run_t = timer.elapsed_sec() - run_start; - print_run_stats(iter, timer.elapsed_sec(), run_t, blk_type->name.c_str(), solve_blks.size(), solve_t, - spread_t, legal_t, solved_hpwl, spread_hpwl, legal_hpwl); - } - - // TODO: update timing info here after timing weights are implemented in build_equations() - - if (legal_hpwl < best_hpwl) { - best_hpwl = legal_hpwl; - stalled = 0; - } else { - ++stalled; - } - - // update legal locations for all blocks for pseudo-connections in next iteration - for (auto& bl : blk_locs) { - bl.legal_loc = bl.loc; - } - iter_t = timer.elapsed_sec() - iter_start; - print_iter_stats(iter, iter_t, timer.elapsed_sec(), best_hpwl, stalled); - ++iter; - } -} - -// build matrix equations and solve for block type "run" in both x and y directions -// macro member positions are updated after solving -void AnalyticPlacer::build_solve_type(t_logical_block_type_ptr run, int iter) { - setup_solve_blks(run); - // build and solve matrix equation for both x, y - // passing -1 as iter to build_solve_direction() signals build_equation() not to add pseudo-connections - build_solve_direction(false, (iter == 0) ? -1 : iter, ap_cfg.buildSolveIter); - build_solve_direction(true, (iter == 0) ? -1 : iter, ap_cfg.buildSolveIter); - update_macros(); // update macro member locations, since only macro head is solved -} - -// build legal_pos similar to initial_placement.cpp -// Go through the placement grid and saving all legal positions for each type of sub_tile -// (stored in legal_pos). For a type of sub_tile_t found in tile_t, legal_pos[tile_t][sub_tile_t] -// gives a vector containing all positions (t_pl_loc type) for this sub_tile_t. -void AnalyticPlacer::build_legal_locations() { - // invoking same function used in initial_placement.cpp (can ignore function name) - alloc_and_load_legal_placement_locations(legal_pos); -} - -// transfer initial placement from g_vpr_ctx to AnalyticPlacer data members, such as: blk_locs, place_blks -// initialize other data members -void AnalyticPlacer::init() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - auto& init_block_locs = blk_loc_registry_ref_.block_locs(); - - for (auto blk_id : clb_nlist.blocks()) { - blk_locs.insert(blk_id, BlockLocation{}); - blk_locs[blk_id].loc = init_block_locs[blk_id].loc; // transfer of initial placement - row_num.insert(blk_id, DONT_SOLVE); // no blocks are moved by default, until they are setup in setup_solve_blks() - } - - // only blocks with connections are considered - auto has_connections = [&](ClusterBlockId blk_id) { - for (auto pin : clb_nlist.block_pins(blk_id)) { - int logical_pin_index = clb_nlist.pin_logical_index(pin); - if (clb_nlist.block_net(blk_id, logical_pin_index) != ClusterNetId::INVALID()) - return true; - } - return false; - }; - - for (auto blk_id : clb_nlist.blocks()) { - if (!init_block_locs[blk_id].is_fixed && has_connections(blk_id)) - // not fixed and has connections - // matrix equation is formulated based on connections, so requires at least one connection - if (place_macros_.get_imacro_from_iblk(blk_id) == NO_MACRO || place_macros_.macro_head(blk_id) == blk_id) { - // not in macro or head of macro - // for macro, only the head (base) block of the macro is a free variable, the location of other macro - // blocks can be calculated using offset of the head. They are not free variables in the equation system - place_blks.push_back(blk_id); - } - } -} - -// get hpwl of a net, taken from place.cpp get_bb_from_scratch() -// TODO: factor out this function from place.cpp and put into vpr_util -int AnalyticPlacer::get_net_hpwl(ClusterNetId net_id) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - // position is not accurate for tiles spanning multiple grid locations - // need to add pin offset in that case: physical_tile_type(bnum)->pin_width_offset[pnum] - // see place.cpp get_non_updateable_bb(); - // TODO: map net_pin to tile_pin and add pin offset to x, y locations (refer to place.cpp) - ClusterBlockId bnum = clb_nlist.net_driver_block(net_id); - int x = std::max(std::min(blk_locs[bnum].loc.x, max_x - 1), 1); - int y = std::max(std::min(blk_locs[bnum].loc.y, max_y - 1), 1); - - vtr::Rect bb = {x, y, x, y}; - - for (auto pin_id : clb_nlist.net_sinks(net_id)) { - bnum = clb_nlist.pin_block(pin_id); - x = std::max(std::min(blk_locs[bnum].loc.x, max_x - 1), 1); - y = std::max(std::min(blk_locs[bnum].loc.y, max_y - 1), 1); - - bb.expand_bounding_box({x, y, x, y}); - } - - return (bb.ymax() - bb.ymin()) + (bb.xmax() - bb.xmin()); -} - -// get hpwl for all nets -int AnalyticPlacer::total_hpwl() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - int hpwl = 0; - for (auto net_id : clb_nlist.nets()) { - if (!clb_nlist.net_is_ignored(net_id)) { - hpwl += get_net_hpwl(net_id); - } - } - return hpwl; -} - -/* - * Setup the blocks of type blkTypes (ex. clb, io) to be solved. These blocks are put into - * solve_blks vector. Each of them is a free variable in the matrix equation (thus excluding - * macro members, as they are formulated into the equation for the macro's head) - * A row number is assigned to each of these blocks, which corresponds to its equation in - * the matrix (the equation acquired from differentiating the objective function w.r.t its - * x or y location). - */ -void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - int row = 0; - solve_blks.clear(); - // clear row_num of all cells, so no blocks are solved - for (auto& blk : row_num) { - blk = DONT_SOLVE; - } - // update blks to be solved/placed, excluding macro members (macro head included) - for (auto blk_id : place_blks) { // find blocks of type blkTypes in place_blks - if (blkTypes == (clb_nlist.block_type(blk_id))) { - row_num[blk_id] = row++; - solve_blks.push_back(blk_id); - } - } - // update row_num of macro members - for (auto& macro : place_macros_.macros()) { - for (auto& member : macro.members) { - row_num[member.blk_index] = row_num[place_macros_.macro_head(member.blk_index)]; - } - } -} - -/* - * Update the location of all members of all macros based on location of macro_head - * since only macro_head is solved (connections to macro members are also taken into account - * when formulating the matrix equations), an update for members is necessary - */ -void AnalyticPlacer::update_macros() { - for (auto& macro : place_macros_.macros()) { - ClusterBlockId head_id = macro.members[0].blk_index; - bool mac_can_be_placed = macro_can_be_placed(macro, blk_locs[head_id].loc, false, blk_loc_registry_ref_); - - //if macro can not be placed in this head pos, change the head pos - if (!mac_can_be_placed) { - size_t macro_size = macro.members.size(); - blk_locs[head_id].loc -= macro.members[macro_size - 1].offset; - } - - //macro should be placed successfully after changing the head position - VTR_ASSERT(macro_can_be_placed(macro, blk_locs[head_id].loc, false, blk_loc_registry_ref_)); - - //update other member's location based on head pos - for (auto member = ++macro.members.begin(); member != macro.members.end(); ++member) { - blk_locs[member->blk_index].loc = blk_locs[head_id].loc + member->offset; - } - } -} - -/* - * Build and solve in one direction - * Solved solutions are written back to block_locs[blk].rawx/rawy for double float raw solution, - * rounded int solutions are written back to block_locs[blk].loc, for each blk in solve_blks - * - * yaxis chooses x or y location of each block from blk_locs to formulate the matrix equation. - * true for y-directed, false for x-directed - * - * iter is the number of AnalyticPlacement iterations (solving and legalizing all types of logic - * blocks once). When iter != -1, at least one iteration has completed. It signals build_equations() - * to create pseudo-connections between each block and its prior legal position. - * - * build_solve_iter determines number of iterations of building and solving for the iterative solver, - * the solution from the previous build-solve iteration is used as a guess for the iterative solver. - * More build_solve_iter means better result, with runtime tradeoff. This parameter can be - * tuned for better performance. - */ -void AnalyticPlacer::build_solve_direction(bool yaxis, int iter, int build_solve_iter) { - for (int i = 0; i < build_solve_iter; i++) { - EquationSystem esx(solve_blks.size(), solve_blks.size()); - build_equations(esx, yaxis, iter); - solve_equations(esx, yaxis); - } -} - -/* - * stamp 1 weight for a connection on matrix or rhs vector. - * - * Block "eqn" specifies which equation (row in matrix system) the weight is added into. - * let eqn have row_num i, var have row_num j (which is also the column in eqn that corresponds to var). - * - * if eqn is not movable, return (eqn doesn't really have an equation as it's not a free variable) - * if var is movable, weight is added in matrix [j][i] - * if var is not movable, (var_pos * weight) is added in rhs vector[j] - * if var is a macro member, weight is added in matrix [j][i], and (-offset_from_head_block * weight) is added to rhs vector[j] - * - * for detailed derivation see comment for add_pin_to_pin_connection() - */ -void AnalyticPlacer::stamp_weight_on_matrix(EquationSystem& es, - bool dir, - ClusterBlockId var, - ClusterBlockId eqn, - double weight) { - // Return the x or y position of a block - auto blk_p = [&](ClusterBlockId blk_id) { return dir ? blk_locs[blk_id].loc.y : blk_locs[blk_id].loc.x; }; - - int eqn_row = row_num[eqn]; - if (eqn_row == DONT_SOLVE) // if eqn is not of the right type or is locked down - return; - int v_pos = blk_p(var); - int var_row = row_num[var]; - if (var_row != DONT_SOLVE) { // var is movable, stamp weight on matrix - es.add_coeff(eqn_row, var_row, weight); - } else { // var is not movable, stamp weight on rhs vector - es.add_rhs(eqn_row, -v_pos * weight); - } - if (place_macros_.get_imacro_from_iblk(var) != NO_MACRO) { // var is part of a macro, stamp on rhs vector - auto& members = place_macros_[place_macros_.get_imacro_from_iblk(var)].members; - for (auto& member : members) { // go through macro members to find the right member block - if (member.blk_index == var) - es.add_rhs(eqn_row, -(dir ? member.offset.y : member.offset.x) * weight); - } - } -} - -/* - * Add weights to matrix for the pin-to-pin connection between bound_blk and this_blk (bound2bound model) - * - * The matrix A in system of equation Ax=b is a symmetric sparse matrix. - * Each row of A corresponds to an equation for a free variable. This equation is acquired by differentiating - * the objective function with respect to the free variable (movable block's x or y location) and setting it - * to 0. - * - * Pin-to-pin connection between 2 movable blocks (call them b1 and b2, with connection weight W12) is the - * simplest case. Differentiating with respect to b1 and setting to 0 produces W12 * b1 - W12 * b2 = 0, where - * b1, b2 are the location variables to calculate. When cast into matrix form, the row number of this equation - * corresponds to b1. Let's assume b1 and b2's equations are in rows i, j. Row number for each free variable also - * indicates its position in other variable's equation. In our example, assume there are 5 free variables (free - * blocks), and i=2, j=4. Then, after adding weights to b1's equation, the system will look like the following: - * | x x x x x | |x | = | x | - * | 0 W12 0 -W12 0 | |b1| = | 0 | - * | x x x x x | * |x | = | x | - * | x x x x x | |b2| = | x | - * | x x x x x | |x | = | x | - * Differentiating with respect to b2 will result in same equation except flipped signs for the weight. This creates - * symmetry in the matrix, resulting in: - * | x x x x x | |x | = | x | - * | 0 W12 0 -W12 0 | |b1| = | 0 | - * | x x x x x | * |x | = | x | - * | 0 -W12 0 W12 0 | |b2| = | 0 | - * | x x x x x | |x | = | x | - * To generalize, for movable blocks b1, b2 in row i,j, with connection weight W, the W is added to matrix position - * [i][i] and [j][j], -W added to [i][j] and [j][i]. This is why stamp_weight_on_matrix is invoked 4 times below. - * - * Special Case: immovable/fixed block. - * Assume b2 in the above example is fixed, then it does not have an equation in the system as it's not a free variable. - * The new equation is now W12 * b1 = W12 * b2, where b2 is just a constant. (This makes sense as b1=b2 is optimal, - * since it has wirelength of 0). The matrix equation now looks like the following: - * | x x x x x | |x | = | x | - * | 0 W12 0 0 0 | |b1| = |W12*b2| - * | x x x x x | * |x | = | x | - * | x x x x x | |x | = | x | - * | x x x x x | |x | = | x | - * - * Special Case: connection to macro member. - * Assume b1 is the head block of a macro, b3 is its macro member with offset d. b3 has a connection with movable block - * b2, with weight W23. b3's location is then (b1 + d). The new equation w.r.t. b1 is W23 * (b1 + d - b2) = 0. - * New equation w.r.t. b3 is symmetrical, producing matrix: - * | x x x x x | |x | = | x | - * | 0 W23 0 -W23 0 | |b1| = |-W23*d| - * | x x x x x | * |x | = | x | - * | 0 -W23 0 W23 0 | |b2| = | W23*d| - * | x x x x x | |x | = | x | - * As shown here, connection to macro members are formulated into macro's head block's equation. This is why macro members - * are not formulated in equation system. - * - * EquationSystem is passed in for adding weights, dir selects x/y direction, num_pins is used in weight calculation - * (bound2bound model). bound_pin and this_pin specifies the 2 pins in the connection (one of them is always bound_pin). - */ -void AnalyticPlacer::add_pin_to_pin_connection(EquationSystem& es, - bool dir, - int num_pins, - ClusterPinId bound_pin, - ClusterPinId this_pin) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - if (this_pin == bound_pin) - // no connection if 2 pins are the same - return; - - // this_blk and bound_blk locations may not be accurate for larger tiles spanning multiple grid locations - // need block_locs[blk_id].loc.x + physical_tile_type(bnum)->pin_width_offset[pnum] - // however, in order to do so, need place_sync_external_block_connections(blk_id) for all blocks - // TODO: map logical pin to physical pin and add this offset for more accurate pin location - ClusterBlockId this_blk = clb_nlist.pin_block(this_pin); - int this_pos = dir ? blk_locs[this_blk].loc.y : blk_locs[this_blk].loc.x; - ClusterBlockId bound_blk = clb_nlist.pin_block(bound_pin); - int bound_pos = dir ? blk_locs[bound_blk].loc.y : blk_locs[bound_blk].loc.x; - // implementing the bound-to-bound net model detailed in HeAP paper, where each bound blk has (num_pins - 1) connections - // (bound_pos - this_pos) in the denominator "linearizes" the quadratic term (bound_pos - this_pos)^2 in the objective function - // This ensures that the objective function target HPWL, rather than quadratic wirelength. - double weight = 1.0 / ((num_pins - 1) * std::max(1, std::abs(bound_pos - this_pos))); - - /* - * TODO: adding timing weights to matrix entries - *if (this_pin != 0){ - * weight *= (1.0 + tmpCfg.timingWeight * std::pow(place_crit.criticality(net_id, this_pin), tmgCfg.criticalityExponent)); - * } - */ - - stamp_weight_on_matrix(es, dir, this_blk, this_blk, weight); - stamp_weight_on_matrix(es, dir, this_blk, bound_blk, -weight); - stamp_weight_on_matrix(es, dir, bound_blk, bound_blk, weight); - stamp_weight_on_matrix(es, dir, bound_blk, this_blk, -weight); -} - -// Build the system of equations for either X or Y -void AnalyticPlacer::build_equations(EquationSystem& es, bool yaxis, int iter) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - // Return the x or y position of a block - auto blk_p = [&](ClusterBlockId blk_id) { return yaxis ? blk_locs[blk_id].loc.y : blk_locs[blk_id].loc.x; }; - // Return legal position from legalization, after first iteration - auto legal_p = [&](ClusterBlockId blk_id) { return yaxis ? blk_locs[blk_id].legal_loc.y : blk_locs[blk_id].legal_loc.x; }; - es.reset(); - - /* - * Bound2bound model is used in HeAP: - * For each net, the left-most and right-most (or down, up in y direction) are bound blocks - * These 2 blocks form connections with each other and all the other blocks (internal blocks) - * These connections are used to formulate the matrix equation - */ - for (auto net_id : clb_nlist.nets()) { - if (clb_nlist.net_is_ignored(net_id) - || clb_nlist.net_driver(net_id) == ClusterPinId::INVALID() - || clb_nlist.net_sinks(net_id).empty()) { - // ensure net is not ignored (ex. clk nets), has valid driver, has at least 1 sink - continue; - } - - // find the 2 bound pins (min and max pin) - ClusterPinId min_pin = ClusterPinId::INVALID(), max_pin = ClusterPinId::INVALID(); - int min_pos = std::numeric_limits::max(), max_pos = std::numeric_limits::min(); - for (auto pin_id : clb_nlist.net_pins(net_id)) { - int pos = blk_p(clb_nlist.pin_block(pin_id)); - if (pos < min_pos) { - min_pos = pos; - min_pin = pin_id; - } - if (pos > max_pos) { - max_pos = pos; - max_pin = pin_id; - } - } - VTR_ASSERT(min_pin != ClusterPinId::INVALID()); - VTR_ASSERT(max_pin != ClusterPinId::INVALID()); - - int num_pins = clb_nlist.net_pins(net_id).size(); - for (int ipin = 0; ipin < num_pins; ipin++) { - ClusterPinId pin_id = clb_nlist.net_pin(net_id, ipin); - // for each pin in net, connect to 2 bound pins (bound2bound model) - add_pin_to_pin_connection(es, yaxis, num_pins, min_pin, pin_id); - if (pin_id != min_pin) - // avoid adding min_pin to max_pin connection twice - add_pin_to_pin_connection(es, yaxis, num_pins, max_pin, pin_id); - } - } - - // Add pseudo-connections to anchor points (legalized position for each block) after first iteration - // These pseudo-connections pull blocks towards their legal locations, which tends to reduce overlaps in the placement, - // also so that the next iteration of build-solving matrix doesn't destroy the placement from last iteration. - // As weight increases with number of iterations, solver's solution converges with the legal placement. - if (iter != -1) { // if not the first AP iteration - for (size_t row = 0; row < solve_blks.size(); row++) { - int l_pos = legal_p(solve_blks.at(row)); // legalized position from last iteration (anchors) - int solver_blk_pos = blk_p(solve_blks.at(row)); // matrix solved block position from last iteration - - // weight increases with iteration --> psudo-connection strength increases to force convergence to legal placement - // weight is also higher for blocks that haven't moved much from their solver location to their legal location - double weight = ap_cfg.alpha * iter / std::max(1, std::abs(l_pos - solver_blk_pos)); - - // Adding coefficient to Matrix[row][row] and adding weight to rhs vector is equivalent to adding connection - // to an immovable block at legal position. - // The equation becomes Weight * (blk_pos - legal_pos) = 0, where blk_pos is the variable to solve in rhs[row], - // legal_pos is a constant - // see comment for add_pin_to_pin_connection() -> special_case: immovable/fixed block - es.add_coeff(row, row, weight); - es.add_rhs(row, weight * l_pos); - } - } -} - -/* - * Solve the system of equations - * A formulated system of equation es is passed in - * yaxis represents if it's x-directed or y-directed location problem - * Solved solution is moved to loc, rawx, rawy in blk_locs for each block - */ -void AnalyticPlacer::solve_equations(EquationSystem& es, bool yaxis) { - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - auto blk_pos = [&](ClusterBlockId blk_id) { return yaxis ? blk_locs[blk_id].rawy : blk_locs[blk_id].rawx; }; - std::vector solve_blks_pos; // each row of solve_blks_pos is a free variable (movable block of the right type to be placed) - // put current location of solve_blks into solve_blks_pos as guess for iterative solver - std::transform(solve_blks.begin(), solve_blks.end(), std::back_inserter(solve_blks_pos), blk_pos); - es.solve(solve_blks_pos, ap_cfg.solverTolerance); - - // move solved locations of solve_blks from solve_blks_pos into blk_locs - // ensure that new location is strictly within [0, grid.width/height - 1]; - for (size_t i_row = 0; i_row < solve_blks_pos.size(); i_row++) - if (yaxis) { - blk_locs[solve_blks.at(i_row)].rawy = std::max(0.0, solve_blks_pos.at(i_row)); - blk_locs[solve_blks.at(i_row)].loc.y = std::min(max_y - 1, std::max(0, int(solve_blks_pos.at(i_row) + 0.5))); - } else { - blk_locs[solve_blks.at(i_row)].rawx = std::max(0.0, solve_blks_pos.at(i_row)); - blk_locs[solve_blks.at(i_row)].loc.x = std::min(max_x - 1, std::max(0, int(solve_blks_pos.at(i_row) + 0.5))); - } -} - -// Debug use, finds # of blocks on each tile location -void AnalyticPlacer::find_overlap(vtr::Matrix& overlap) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - size_t max_x = g_vpr_ctx.device().grid.width(); - size_t max_y = g_vpr_ctx.device().grid.height(); - - overlap.resize({max_y, max_x}, 0); - - for (auto blk : clb_nlist.blocks()) { - overlap[blk_locs[blk].loc.y][blk_locs[blk].loc.x] += 1; - } -} - -// prints a simple figure of FPGA fabric, with numbers on each tile showing usage -// called in AnalyticPlacer::print_place() -std::string AnalyticPlacer::print_overlap(vtr::Matrix& overlap, FILE* fp) { - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - std::string out = ""; - fprintf(fp, "%5s", ""); - for (int i = 0; i < max_x; i++) { - fprintf(fp, "%-5d", i); - } - fprintf(fp, "\n%4s", ""); - fprintf(fp, "%s\n", std::string(5 * max_x + 2, '-').c_str()); - for (int i = 0; i < max_y; i++) { - fprintf(fp, "%-4d|", i); - for (int j = 0; j < max_x; j++) { - int count = overlap[i][j]; - fprintf(fp, "%-5s", ((count == 0) ? "0" : std::to_string(count)).c_str()); - } - fprintf(fp, "|\n"); - } - fprintf(fp, "%4s", ""); - fprintf(fp, "%s\n", std::string(5 * max_x + 2, '-').c_str()); - return out; -} - -/* - * Prints the location of each block, and a simple drawing of FPGA fabric, showing num of blocks on each tile - * Very useful for debugging - * Usage: - * std::string filename = vtr::string_fmt("%s.post_AP.place", clb_nlist.netlist_name().substr(0, clb_nlist.netlist_name().size()-4).c_str()); - * print_place(filename.c_str()); - */ -void AnalyticPlacer::print_place(const char* place_file) { - const DeviceContext& device_ctx = g_vpr_ctx.device(); - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - auto& block_locs = blk_loc_registry_ref_.block_locs(); - - FILE* fp; - - fp = fopen(place_file, "w"); - - fprintf(fp, "Netlist_File: %s Netlist_ID: %s\n", - clb_nlist.netlist_name().c_str(), - clb_nlist.netlist_id().c_str()); - fprintf(fp, "Array size: %zu x %zu logic blocks\n\n", device_ctx.grid.width(), device_ctx.grid.height()); - fprintf(fp, "%-25s %-18s %-12s %-25s %-5s %-5s %-10s %-14s %-8s\n", - "block name", - "logic block type", - "pb_type", - "pb_name", - "x", - "y", - "subblk", - "block number", - "is_fixed"); - fprintf(fp, "%-25s %-18s %-12s %-25s %-5s %-5s %-10s %-14s %-8s\n", - "----------", - "----------------", - "-------", - "-------", - "--", - "--", - "------", - "------------", - "--------"); - - if (!block_locs.empty()) { //Only if placement exists - for (auto blk_id : clb_nlist.blocks()) { - fprintf(fp, "%-25s %-18s %-12s %-25s %-5d %-5d %-10d #%-13zu %-8s\n", - clb_nlist.block_name(blk_id).c_str(), - clb_nlist.block_type(blk_id)->name.c_str(), - clb_nlist.block_type(blk_id)->pb_type->name, - clb_nlist.block_pb(blk_id)->name, - blk_locs[blk_id].loc.x, - blk_locs[blk_id].loc.y, - blk_locs[blk_id].loc.sub_tile, - size_t(blk_id), - (block_locs[blk_id].is_fixed ? "true" : "false")); - } - fprintf(fp, "\ntotal_HPWL: %d\n", total_hpwl()); - vtr::Matrix overlap; - find_overlap(overlap); - fprintf(fp, "Occupancy diagram: \n"); - print_overlap(overlap, fp); - } - fclose(fp); -} - -void AnalyticPlacer::print_AP_status_header() { - VTR_LOG("\n"); - VTR_LOG("---- ------ ------ -------- ------- | ------ --------- ------ ------ ------ ------ -------- -------- --------\n"); - VTR_LOG("Iter Time Iter Best Stall | Run BlockType Solve Solve Spread Legal Solved Spread Legal\n"); - VTR_LOG(" Time hpwl | Time Block Time Time Time hpwl hpwl hpwl\n"); - VTR_LOG(" (sec) (sec) | (sec) Num (sec) (sec) (sec) \n"); - VTR_LOG("---- ------ ------ -------- ------- | ------ --------- ------ ------ ------ ------ -------- -------- --------\n"); -} - -void AnalyticPlacer::print_run_stats(const int iter, - const float time, - const float runTime, - const char* blockType, - const int blockNum, - const float solveTime, - const float spreadTime, - const float legalTime, - const int solvedHPWL, - const int spreadHPWL, - const int legalHPWL) { - VTR_LOG( - "%4zu " - "%6.3f " - " | " - "%6.3f " - "%9s " - "%6d " - "%6.3f " - "%6.3f " - "%6.3f " - "%8d " - "%8d " - "%8d \n", - iter, - time, - runTime, - blockType, - blockNum, - solveTime, - spreadTime, - legalTime, - solvedHPWL, - spreadHPWL, - legalHPWL); -} - -void AnalyticPlacer::print_iter_stats(const int iter, - const float iterTime, - const float time, - const int bestHPWL, - const int stall) { - VTR_LOG( - "%4zu " - "%6.3f " - "%6.3f " - "%8d " - "%7d |\n", - iter, - time, - iterTime, - bestHPWL, - stall); - VTR_LOG(" |\n"); -} - -// sentinel for blks not solved in current iteration -int DONT_SOLVE = std::numeric_limits::max(); - -// sentinel for blks not part of a placement macro -int NO_MACRO = -1; - -#endif /* ENABLE_ANALYTIC_PLACE */ diff --git a/vpr/src/place/analytic_placer.h b/vpr/src/place/analytic_placer.h deleted file mode 100644 index 86e31481858..00000000000 --- a/vpr/src/place/analytic_placer.h +++ /dev/null @@ -1,326 +0,0 @@ -#ifndef VPR_ANALYTIC_PLACEMENT_H -#define VPR_ANALYTIC_PLACEMENT_H - -#ifdef ENABLE_ANALYTIC_PLACE -/** - * @file - * @brief This file implements the analytic placer, described as lower-bound placement in SimPL. It formulates - * the placement problem into a set of linear equations, in the form of a matrix equation. Solving the matrix - * equation gives the minimum of the objective function, in this case wirelength. The result placement, although - * most optimal in terms of optimization, thus the name lower-bound placement, almost always is not legal. This - * lower-bound solution is then legalized using Cut-Spreading (@see cut_spreader.h). - * - ************************************************************************************************************** - * Algorithm Overview * - ************************************************************************************************************** - * - * The most common objective function for placement is the sum of half-perimeter wirelengths (HPWL) over all nets. - * Efficient AP techniques approximate this objective function with a function that can be minimized efficiently. - * - * First, all multi-pin nets are converted into a set of 2-pin connections. In SimPL/HeAP, the Bound2bound net - * model is used. For each multi-pin net, the blocks with the minimum and maximum locations (in either x or y directon - * as build-solve operates on only 1 direction at a time) on a net (so-called bound-blocks) are connected to each - * other and to each internal block on the net. In other words, for a p-terminal net, each internal block has 2 connections, - * one to each bound block, and each bound block has p-1 connections, one to every block other than itself. - * - * Then, the weighted sum of the squared lengths of these 2-pin connections are minimized. This objective function - * can be separated into x and y components and cast in matrix form. To minimize this degree-2 polynomial, partial - * derivative is taken with respect to each variable. Setting the resulting system of linear equations to 0 gives - * the following equation (only x direction shown): - * Qx = -c - * where Q is a matrix capturing all connection between movable objects (objects to solve), x is a vector of all - * movable block locations (free variables), and c is a vector representing connections between movable and fixed objects. - * *** for detailed derivation and an example, refer to comments for add_pin_to_pin_connection() in analytic_placer.cpp. - * - * After formulating Q and c, a standard off-the-shelf solver (Eigen package) is used to solve for x. This completes - * the lower-bound placement. - * - * However, since the objective function does not take placement constraints into consideration, the generated - * solution is not legal. It generally has many blocks overlapping with one another, and the blocks may be on - * incompatible physical tiles. To legalize this solution, a geometric partitioning and spreading technique, introduced - * in SimPL, is used (@see cut_sreader.h). This completes the upper-bound placement. - * - * After the completion of 1 iteration of lower-bound & upper-bound placement, artificial pseudo connections are created - * between each block and its target location in the legalized overlap-free placement. When the mathematical system is - * again formulated and solved, the pseudo connections pull blocks towards their target locations, which tends to reduce - * overlaps in the placement. The strength of pseudo-connections increase with iterations, making lower-bound and - * upper-bound solutions converge. - * - * This process of formulating the system, solving, and legalizing is repeated until sufficiently good placement is - * acquired. Currently the stopping criterion is HEAP_STALLED_ITERATIONS_STOP iterations without improvement in total_hpwl. - * - * - * Parameters to tweak & things to try out - * ======================================= - * Currently the QoR of AP+quench combination is slightly worse than SA. See PR #1504 for comparison. - * The following parameters/things can be tweaked to find the best configuration: - * - * * Stopping criteria when to stop AP iterations, see (AnalyticPlacer::ap_place()) - * * PlacerHeapCfg.alpha anchoring strength of pseudo-connection - * * PlacerHeapCfg.beta overutilization factor (@see CutSpreader::SpreaderRegion.overused()) - * * PlacerHeapCfg.timingWeight implement timing in AP (@see AnalyticPlacer::build_equations()) - * * PlacerHeapCfg.criticality same as above - * * Interaction with SA: - * * init_t Initial temperature of annealer after AP (currently init_t = 0) - * * quench inner_num how much swapping in quenching to attemp - * * quench_recompute_limit frequency of criticality update in quenching to improve quench results - * - * @cite SimPL - * Original analytic placer with cut-spreading legalizing was intended for ASIC design, proposed in SimPL. - * SimPL: An Effective Placement Algorithm, Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov - * http://www.ece.umich.edu/cse/awards/pdfs/iccad10-simpl.pdf - * - * @cite HeAP - * FPGA adaptation of SimPL, targeting FPGAs with heterogeneous blocks located at discrete locations. - * Analytical Placement for Heterogeneous FPGAs, Marcel Gort and Jason H. Anderson - * https://janders.eecg.utoronto.ca/pdfs/marcelfpl12.pdf - * - * @cite nextpnr - * An implementation of HeAP, which the cut-spreader and legalizer here is based off of. Implementation details - * have been modified for the architecture and netlist specification of VTR, and better performance. - * nextpnr -- Next Generation Place and Route, placer_heap, David Shah - * https://github.com/YosysHQ/nextpnr - */ - -#include "vpr_context.h" -#include "PlacementDelayCalculator.h" - -class PlaceMacros; - -/* - * @brief Templated struct for constructing and solving matrix equations in analytic placer - * Eigen library is used in EquationSystem::solve() - */ -template -struct EquationSystem; - -// sentinel for blks not solved in current iteration -extern int DONT_SOLVE; - -// sentinel for blks not part of a placement macro -extern int NO_MACRO; - -class AnalyticPlacer { - public: - /* - * @brief Constructor of AnalyticPlacer, currently initializes AnalyticPlacerCfg for the analytic placer - * To tune these parameters, change directly in constructor - */ - AnalyticPlacer() = delete; - explicit AnalyticPlacer(BlkLocRegistry& blk_loc_registry, const PlaceMacros& place_macros); - - /* - * @brief main function of analytic placement - * Takes the random initial placement from place.cpp through g_vpr_ctx - * Repeat the following until stopping criteria is met: - * * Formulate and solve equations in x, y directions for 1 type of logial block - * * Instantiate CutSpreader to spread and strict_legalize() to strictly legalize - * - * The final legal placement is passed back to annealer in g_vpr_ctx.mutable_placement() - */ - void ap_place(); - - private: - // for CutSpreader to access placement info from solver (legal_pos, block_locs, etc). - friend class CutSpreader; - - // AP parameters that can influence it's behavior - struct AnalyticPlacerCfg { - float alpha; // anchoring strength of pseudo-connections - float beta; // over-utilization factor - int criticalityExponent; // not currently used, @see build_equations() - int timingWeight; // not currently used, @see build_equations() - float solverTolerance; // parameter of the solver - int buildSolveIter; // build_solve iterations for iterative solver - int spread_scale_x, spread_scale_y; // see CutSpreader::expand_regions() - }; - - AnalyticPlacerCfg ap_cfg; // TODO: PlacerHeapCfg should be externally configured & supplied - - // Lokup of all sub_tiles by sub_tile type - // legal_pos[0..device_ctx.num_block_types-1][0..num_sub_tiles - 1][0..num_legal - 1] = t_pl_loc for a single - // placement location of the proper tile type and sub_tile type. - std::vector>> legal_pos; - - // row number in the system of linear equations for each block - // which corresponds to the equation produced by differentiating objective function w.r.t that block location - vtr::vector_map row_num; - - // Encapsulates 3 types of locations for each logic block - struct BlockLocation { - t_pl_loc loc; // real, up-to-date location of the logic block in the AP process - // first initiated with initial random placement from g_vpr_ctx - // then, eath time after solving equations, it's updated with rounded - // raw solutions from solver - // finally, it is accessed and modified by legalizer to store legal placement - // at the end of each AP iteration - - t_pl_loc legal_loc; // legalized location, used to create psudo connections in the next AP iteration - // updated in AP main loop in ap_place() at the end of each iteration - - double rawx, rawy; // raw location storing float result from matrix solver - // used by cut_speader to spread out logic blocks using linear interpolation - }; - - // Lookup from blockID to block location - vtr::vector_map blk_locs; - - // reference to the placement location variables - BlkLocRegistry& blk_loc_registry_ref_; - - // Reference to the placement macros. - const PlaceMacros& place_macros_; - - /* - * The set of blks of different types to be placed by AnalyticPlacement process, - * i.e. the free variable blocks. - * Excludes non-head macro blocks (blocks part of placement macros but not the head), fixed blocks, and blocks - * with no connections. - */ - std::vector place_blks; - - // blocks of the same type to be solved in the current formulation of matrix equation - // which are a subset of place_blks - std::vector solve_blks; - - /* - * Prints the location of each block, and a simple drawing of FPGA fabric, showing num of blocks on each tile - * Very useful for debugging - * See implementation for usage - */ - void print_place(const char* place_file); - - //build fast lookup of compatible tiles/subtiles by tile, x, y, subtiles - void build_fast_tiles(); - - // build legal_pos - void build_legal_locations(); - - // build blk_locs based on initial placement from place_ctx. - // put blocks that needs to be placed in place_blks; - void init(); - - // get hpwl for a net - int get_net_hpwl(ClusterNetId net_id); - - // get hpwl for all nets - int total_hpwl(); - - // build matrix equations and solve for block type "run" in both x and y directions - // macro member positions are updated after solving - // iter is used to determine pseudo-connection strength - void build_solve_type(t_logical_block_type_ptr run, int iter); - - /* - * Setup the blocks of type blkTypes (ex. clb, io) to be solved. These blocks are put into - * solve_blks vector. Each of them is a free variable in the matrix equation (thus excluding - * macro members, as they are formulated into the equation for the macro's head) - * A row number is assigned to each of these blocks, which corresponds to its equation in - * the matrix (the equation acquired from differentiating the objective function w.r.t its - * x or y location). - */ - void setup_solve_blks(t_logical_block_type_ptr blkTypes); - - /* - * Update the location of all members of all macros based on location of macro_head - * since only macro_head is solved (connections to macro members are also taken into account - * when formulating the matrix equations), a location update for members is necessary - */ - void update_macros(); - - /* - * Build and solve in one direction - * yaxis chooses x or y location of each block from blk_locs to formulate the matrix equation - * Solved solutions are written back to block_locs[blk].rawx/rawy for double float raw solution, - * rounded int solutions are written back to block_locs[blk].loc, for each blk in solve_blks - * - * iter is the number of AnalyticPlacement iterations (solving and legalizing all types of logic - * blocks once). When iter != -1, at least one iteration has completed. It signals build_equations() - * to create pseudo-connections between each block and its prior legal position. - * - * build_solve_iter determines number of iterations of building and solving for the iterative solver - * (i.e. more build_solve_iter means better result, with runtime tradeoff. This parameter can be - * tuned for better performance) - * the solution from the previous build-solve iteration is used as a guess for the iterative solver - */ - void build_solve_direction(bool yaxis, int iter, int build_solve_iter); - - /* - * Stamp 1 weight for 1 connection on matrix or rhs vector - * if var is movable objects, weight is added on matrix - * if var is immovable objects, weight*-var_pos is added on rhs - * if var is a macro member (not macro head), weight*-offset_from_macro_head is added on rhs - * - * for detailed derivation and examples, see comments for add_pin_to_pin_connection() in analytic_placer.cpp - */ - void stamp_weight_on_matrix(EquationSystem& es, - bool dir, - ClusterBlockId var, - ClusterBlockId eqn, - double weight); - - /* - * Add weights for connection between bound_pin and this_pin into matrix - * Calculate weight for connection and stamp them into appropriate position in matrix by invoking - * stamp_weight_on_matrix() multiple times. For more detail, see comments in implementation. - */ - void add_pin_to_pin_connection(EquationSystem& es, - bool dir, - int num_pins, - ClusterPinId bound_pin, - ClusterPinId this_pin); - - /* - * Build the system of equations for either X or Y - * When iter != -1, for each block, psudo-conenction to its prior legal location is formed, - * the strength is determined by ap_cfg.alpha and iter - */ - void build_equations(EquationSystem& es, bool yaxis, int iter = -1); - - /* - * Solve the system of equations passed in by es, for the set of blocks in data member solve_blks - * yaxis is used to select current x or y location of these blocks from blk_locs - * this current location is provided to iterative solver as a guess - * the solved location is written back to blk_locs, and is used as guess for the next - * iteration of solving (@see build_solve_direct()) - */ - void solve_equations(EquationSystem& es, bool yaxis); - - /* - * Debug use - * finds # of blocks on each tile location, returned in overlap matrix - */ - void find_overlap(vtr::Matrix& overlap); - - /* - * Debug use - * prints a simple figure of FPGA fabric, with numbers on each tile showing usage. - * called in AnalyticPlacer::print_place() - */ - std::string print_overlap(vtr::Matrix& overlap, FILE* fp); - - // header of VTR_LOG for AP - void print_AP_status_header(); - - void print_run_stats(const int iter, - const float time, - const float runTime, - const char* blockType, - const int blockNum, - const float solveTime, - const float spreadTime, - const float legalTime, - const int solvedHPWL, - const int spreadHPWL, - const int legalHPWL); - - void print_iter_stats(const int iter, - const float iterTime, - const float time, - const int bestHPWL, - const int stall); -}; - -#endif /* ENABLE_ANALYTIC_PLACE */ - -#endif /* VPR_ANALYTIC_PLACEMENT_H */ diff --git a/vpr/src/place/cut_spreader.cpp b/vpr/src/place/cut_spreader.cpp deleted file mode 100644 index 9dfe17f83c6..00000000000 --- a/vpr/src/place/cut_spreader.cpp +++ /dev/null @@ -1,1174 +0,0 @@ -#include "place_macro.h" -#ifdef ENABLE_ANALYTIC_PLACE - -#include "cut_spreader.h" -#include -#include -#include -#include - -#include "analytic_placer.h" -#include "vpr_types.h" -#include "vtr_time.h" -#include "globals.h" -#include "vtr_log.h" -#include "place_util.h" -#include "grid_block.h" - -// sentinel for base case in CutSpreader (i.e. only 1 block left in region) -constexpr std::pair BASE_CASE = {-2, -2}; - -// sentinel for cut-spreading fail, the other direction is run next -constexpr std::pair CUT_FAIL = {-1, -1}; - -// sentinel for a grid location that is not covered by any regions, for reg_id_at_grid data member -constexpr int AP_NO_REGION = -1; - -/* - * Constructor of CutSpreader - * @param analytic_placer: used to access AnalyticPlacer data members (lower-bound solutions) - * @param blk_t: logical block type to legalize - */ -CutSpreader::CutSpreader(AnalyticPlacer* analytic_placer, t_logical_block_type_ptr blk_t) - : ap(analytic_placer) - , blk_type(blk_t) { - // builds n_subtiles_at_location data member, which is a quick lookup of number of compatible subtiles at x, y. - size_t max_x = g_vpr_ctx.device().grid.width(); - size_t max_y = g_vpr_ctx.device().grid.height(); - subtiles_at_location.resize({max_x, max_y}); - for (auto& tile : blk_type->equivalent_tiles) { - for (auto sub_tile : tile->sub_tiles) { - // find all sub_tile types compatible with blk_t - auto result = std::find(sub_tile.equivalent_sites.begin(), sub_tile.equivalent_sites.end(), blk_type); - if (result != sub_tile.equivalent_sites.end()) { - for (auto loc : ap->legal_pos.at(tile->index).at(sub_tile.index)) { - subtiles_at_location[loc.x][loc.y].push_back(loc); - } - } - } - } -} - -/* - * @brief: Executes the cut-spreader algorithm described in algorithm overview in header file. - * Does not include strict_legalize so placement result is not guaranteed to be legal. - * Strict_legalize must be run after for legal placement result, and for legal placement to - * be passed to annealer through vpr_ctx. - * - * Input placement is passed by data members (blk_locs) in analytic_placer - * - * @return result placement is passed to strict legalizer by modifying blk_locs in analytic_placer - */ -void CutSpreader::cutSpread() { - init(); // initialize data members based on solved solutions from AnalyticPlacer - find_overused_regions(); //find all overused regions bordered by non-overused regions - expand_regions(); // expand overused regions until they have enough sub_tiles to accommodate their logic blks - - /* - * workqueue is a FIFO queue used to recursively cut-spread. - * - * In the region vector, the regions not in merged_regions (not absorbed in expansion process) - * are the initial regions placed in workqueue to cut-spread. - * - * After each of these initial regions are cut and spread, their child sub-regions - * (left and right) are placed at the back of workqueue, with alternated cut direction. - * This process continues until base case of region with only 1 block is reached, - * indicated by BASE_CASE return value. - * - * Return value of CUT_FAIL indicates that cutting is unsuccessful. This usually happens - * when regions are quite small: for example, region only has 1 column so a vertical cut - * is impossible. In this case cut in the other direction is attempted. - */ - std::queue> workqueue; - - // put initial regions into workqueue - for (auto& r : regions) { - if (!merged_regions.count(r.id)) - workqueue.emplace(r.id, false); - } - - while (!workqueue.empty()) { - auto front = workqueue.front(); - workqueue.pop(); - auto& r = regions.at(front.first); - - auto res = cut_region(r, front.second); - if (res == BASE_CASE) // only 1 block left, base case - continue; - if (res != CUT_FAIL) { // cut-spread successful - // place children regions in workqueue - workqueue.emplace(res.first, !front.second); - workqueue.emplace(res.second, !front.second); - } else { // cut-spread unsuccessful - auto res2 = cut_region(r, !front.second); // try other direction - if (res2 != CUT_FAIL) { - // place children regions in workqueue - workqueue.emplace(res2.first, front.second); - workqueue.emplace(res2.second, front.second); - } - } - } -} - -// setup CutSpreader data structures using information from AnalyticPlacer -void CutSpreader::init() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->place_macros_; - - size_t max_x = g_vpr_ctx.device().grid.width(); - size_t max_y = g_vpr_ctx.device().grid.height(); - - occupancy.resize({max_x, max_y}, 0); - macro_extent.resize({max_x, max_y}); - reg_id_at_grid.resize({max_x, max_y}, AP_NO_REGION); - blk_extents.resize(ap->blk_locs.size(), vtr::Rect{-1, -1, -1, -1}); - blks_at_location.resize({max_x, max_y}, std::vector{}); - - // Initialize occupancy matrix, reg_id_at_grid and macros matrix - for (int x = 0; x < (int)max_x; x++) { - for (int y = 0; y < (int)max_y; y++) { - occupancy[x][y] = 0; - reg_id_at_grid[x][y] = AP_NO_REGION; - macro_extent[x][y] = {x, y, x, y}; - } - } - - // lambda function to absorb x, y in blk's macro's extent - auto set_macro_ext = [&](ClusterBlockId blk, int x, int y) { - if (blk_extents[blk] == vtr::Rect{-1, -1, -1, -1}) { - blk_extents.update(blk, {x, y, x, y}); - } else { - blk_extents[blk].expand_bounding_box({x, y, x, y}); - } - }; - - for (size_t i = 0; i < ap->blk_locs.size(); i++) { // loop through ap->blk_locs - auto blk = ClusterBlockId{(int)i}; - if (clb_nlist.block_type(blk) == blk_type) { - auto loc = ap->blk_locs[blk].loc; - occupancy[loc.x][loc.y]++; - // compute extent of macro member - if (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) { // if blk is a macro member - // only update macro heads' extent in blk_extents - set_macro_ext(place_macros.macro_head(blk), loc.x, loc.y); - } - } - } - - for (size_t i = 0; i < ap->blk_locs.size(); i++) { // loop through ap->blk_locs - ClusterBlockId blk = ClusterBlockId{(int)i}; - if (clb_nlist.block_type(blk) == blk_type) { - // Transfer macro extents to the actual macros structure; - if (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) { // if blk is a macro member - // update macro_extent for all macro members in macros - // for single blocks (not in macro), macros[x][y] = {x, y, x, y} - vtr::Rect& me = blk_extents[place_macros.macro_head(blk)]; - auto loc = ap->blk_locs[blk].loc; - auto& lme = macro_extent[loc.x][loc.y]; - lme.expand_bounding_box(me); - } - } - } - - // get solved_solution from AnalyticPlacer - for (auto blk : ap->solve_blks) { - if (clb_nlist.block_type(blk) == blk_type) - blks_at_location[ap->blk_locs[blk].loc.x][ap->blk_locs[blk].loc.y].push_back(blk); - } -} - -int CutSpreader::occ_at(int x, int y) { - //TODO: layer_num should be passed - if (!is_loc_on_chip({x, y, 0})) { - return 0; - } - return occupancy[x][y]; -} - -int CutSpreader::tiles_at(int x, int y) { - //TODO: layer_num should be passed - if (!is_loc_on_chip({x, y, 0})) { - return 0; - } - return int(subtiles_at_location[x][y].size()); -} - -/* - * When expanding a region, it might overlap with another region, one of them (merger) will absorb - * the other (mergee) by merging. @see expand_regions() below; - * - * Merge mergee into merged by: - * * change group id at mergee grids to merged id - * * adds all n_blks and n_tiles from mergee to merged region - * * grow merged to include all mergee grids - */ -void CutSpreader::merge_regions(SpreaderRegion& merged, SpreaderRegion& mergee) { - for (int x = mergee.bb.xmin(); x <= mergee.bb.xmax(); x++) - for (int y = mergee.bb.ymin(); y <= mergee.bb.ymax(); y++) { - //TODO: layer_num should be passed - if (!is_loc_on_chip({x, y, 0})) { //location is not within the chip - continue; - } - //x and y might belong to "merged" region already, no further action is required - if (merged.id == reg_id_at_grid[x][y]) { - continue; - } - reg_id_at_grid[x][y] = merged.id; //change group id at mergee grids to merged id - //adds all n_blks and n_tiles from mergee to merged region - merged.n_blks += occ_at(x, y); - merged.n_tiles += tiles_at(x, y); - } - merged_regions.insert(mergee.id); // all merged_regions are ignored in main loop - grow_region(merged, mergee.bb); // grow merged to include all mergee grids -} - -/* - * grow r to include a rectangular region rect_to_include - * - * when init == true, grow_region() initializes SpreaderRegion r - * in this case, both r and rect_to_include contains the same 1 tile location: the initial overused tile - * see find_overused_regions where SpreaderRegion r is created. - * this tile location is processed although it's technically included. - */ -void CutSpreader::grow_region(SpreaderRegion& r, vtr::Rect rect_to_include, bool init) { - // when given location is within SpreaderRegion - if ((r.bb.contains(rect_to_include)) && !init) - return; - - vtr::Rect r_old = r.bb; - r_old.set_xmin(r.bb.xmin() + (init ? 1 : 0)); // ensure the initial location is processed in the for-loop later, when init == 1 - r.bb.expand_bounding_box(rect_to_include); - - auto process_location = [&](int x, int y) { - //x and y should represent a location on the chip, otherwise no processing is required - //TODO: layer_num should be passed - if (!is_loc_on_chip({x, y, 0})) { - return; - } - // kicks in only when grid is not claimed, claimed by another region, or part of a macro - // Merge with any overlapping regions - if (reg_id_at_grid[x][y] == AP_NO_REGION) { - r.n_tiles += tiles_at(x, y); - r.n_blks += occ_at(x, y); - } - if (reg_id_at_grid[x][y] != AP_NO_REGION && reg_id_at_grid[x][y] != r.id) - merge_regions(r, regions.at(reg_id_at_grid[x][y])); - reg_id_at_grid[x][y] = r.id; - // Grow to cover any macros - auto& macro_bb = macro_extent[x][y]; - grow_region(r, macro_bb); - }; - // process new areas after including rect_to_include, while avoiding double counting old region - for (int x = r.bb.xmin(); x < r_old.xmin(); x++) - for (int y = r.bb.ymin(); y <= r.bb.ymax(); y++) - process_location(x, y); - for (int x = r_old.xmax() + 1; x <= r.bb.xmax(); x++) - for (int y = r.bb.ymin(); y <= r.bb.ymax(); y++) - process_location(x, y); - for (int y = r.bb.ymin(); y < r_old.ymin(); y++) - for (int x = r.bb.xmin(); x <= r.bb.xmax(); x++) - process_location(x, y); - for (int y = r_old.ymax() + 1; y <= r.bb.ymax(); y++) - for (int x = r.bb.xmin(); x <= r.bb.xmax(); x++) - process_location(x, y); -} - -// Find overutilized regions surrounded by non-overutilized regions -void CutSpreader::find_overused_regions() { - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - for (int x = 0; x < max_x; x++) - for (int y = 0; y < max_y; y++) { - if (reg_id_at_grid[x][y] != AP_NO_REGION || (occ_at(x, y) <= tiles_at(x, y))) - // already in a region or not over-utilized - continue; - - // create new overused region - int id = int(regions.size()); - reg_id_at_grid[x][y] = id; - SpreaderRegion reg; - reg.id = id; - reg.bb = {x, y, x, y}; - reg.n_tiles = reg.n_blks = 0; - reg.n_tiles += tiles_at(x, y); - reg.n_blks += occ_at(x, y); - - // initialize reg and ensure it covers macros - grow_region(reg, {x, y, x, y}, true); - - bool expanded = true; - while (expanded) { - expanded = false; - // keep expanding in x and y, until expansion in x, y cannot find overutilised blks - - // try expanding in x - if (reg.bb.xmax() < max_x - 1) { - bool over_occ_x = false; - for (int y1 = reg.bb.ymin(); y1 <= reg.bb.ymax(); y1++) { - if (occ_at(reg.bb.xmax() + 1, y1) > tiles_at(reg.bb.xmax() + 1, y1)) { - over_occ_x = true; - break; - } - } - if (over_occ_x) { - expanded = true; - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin(), reg.bb.xmax() + 1, reg.bb.ymax()}); - } - } - // try expanding in y - if (reg.bb.ymax() < max_y - 1) { - bool over_occ_y = false; - for (int x1 = reg.bb.xmin(); x1 <= reg.bb.xmax(); x1++) { - if (occ_at(x1, reg.bb.ymax() + 1) > tiles_at(x1, reg.bb.ymax() + 1)) { - over_occ_y = true; - break; - } - } - if (over_occ_y) { - expanded = true; - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin(), reg.bb.xmax(), reg.bb.ymax() + 1}); - } - } - } - regions.push_back(reg); - } -} - -/* - * Expand all utilized regions until they satisfy n_tiles * beta >= n_blocks - * If overutilized regions overlap in this process, they are merged - */ -void CutSpreader::expand_regions() { - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - std::queue overused_regions; - float beta = ap->ap_cfg.beta; - for (auto& r : regions) - // if region is not merged and is overused, move into overused_regions queue - if (!merged_regions.count(r.id) && r.overused(beta)) - overused_regions.push(r.id); - - while (!overused_regions.empty()) { // expand all overused regions - int rid = overused_regions.front(); - overused_regions.pop(); - if (merged_regions.count(rid)) - continue; - auto& reg = regions.at(rid); - while (reg.overused(beta)) { - bool changed = false; - - // spread_scale determines steps in x or y direction to expand each time - for (int j = 0; j < ap->ap_cfg.spread_scale_x; j++) { - if (reg.bb.xmin() > 0) { // expand in -x direction - grow_region(reg, {reg.bb.xmin() - 1, reg.bb.ymin(), reg.bb.xmax(), reg.bb.ymax()}); - changed = true; - if (!reg.overused(beta)) - break; - } - if (reg.bb.xmax() < max_x - 1) { // expand in +x direction - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin(), reg.bb.xmax() + 1, reg.bb.ymax()}); - changed = true; - if (!reg.overused(beta)) - break; - } - } - - for (int j = 0; j < ap->ap_cfg.spread_scale_y; j++) { - if (reg.bb.ymin() > 0) { // expand in -y direction - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin() - 1, reg.bb.xmax(), reg.bb.ymax()}); - changed = true; - if (!reg.overused(beta)) - break; - } - if (reg.bb.ymax() < max_y - 1) { // expand in +y direction - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin(), reg.bb.xmax(), reg.bb.ymax() + 1}); - changed = true; - if (!reg.overused(beta)) - break; - } - } - VTR_ASSERT(changed || reg.n_tiles >= reg.n_blks); - } - VTR_ASSERT(reg.n_blks <= reg.n_tiles); - } -} - -/* - * Recursive cut-based spreading in HeAP paper - * "left" denotes "-x, -y", "right" denotes "+x, +y" depending on dir - * - * @param r region to cut & spread - * @param dir direction, true for y, false for x - * - * @return a pair of sub-region IDs created from cutting region r. - * BASE_CASE if base case is reached - * CUT_FAIL if cut unsuccessful, need to cut in the other direction - */ -std::pair CutSpreader::cut_region(SpreaderRegion& r, bool dir) { - const DeviceContext& device_ctx = g_vpr_ctx.device(); - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->place_macros_; - - // TODO: CutSpreader is not compatible with 3D FPGA - VTR_ASSERT(device_ctx.grid.get_num_layers() == 1); - int layer_num = 0; - - std::vector cut_blks; - init_cut_blks(r, cut_blks); // copy all logic blocks to cut into cut_blks - - // Trim the boundaries of the region in axis-of-interest, skipping any rows/cols without any tiles of the right type - int trimmed_l, trimmed_r; - std::pair(trimmed_l, trimmed_r) = trim_region(r, dir); - - // base case (only 1 block left in region) - if (cut_blks.size() == 1) { - // ensure placement of last block is on right type of tile - auto blk = cut_blks.at(0); - auto& tiles_type = clb_nlist.block_type(blk)->equivalent_tiles; - auto loc = ap->blk_locs[blk].loc; - if (std::find(tiles_type.begin(), tiles_type.end(), device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer})) == tiles_type.end()) { - // logic block type doesn't match tile type - // exhaustive search for tile of right type - // this search should be fast as region must be small at this point (only 1 logic block left) - for (int x = r.bb.xmin(); x <= r.bb.xmax(); x++) - for (int y = r.bb.ymin(); y <= r.bb.ymax(); y++) { - if (std::find(tiles_type.begin(), tiles_type.end(), device_ctx.grid.get_physical_type({x, y, layer_num})) != tiles_type.end()) { - VTR_ASSERT(blks_at_location[x][y].empty()); - ap->blk_locs[blk].rawx = x; - ap->blk_locs[blk].rawy = y; - ap->blk_locs[blk].loc.x = x; - ap->blk_locs[blk].loc.y = y; - blks_at_location[x][y].push_back(blk); - blks_at_location[loc.x][loc.y].clear(); - return BASE_CASE; - } - } - } - return BASE_CASE; - } - - // sort blks based on raw location - std::stable_sort(cut_blks.begin(), cut_blks.end(), [&](const ClusterBlockId a, const ClusterBlockId b) { - return dir ? (ap->blk_locs[a].rawy < ap->blk_locs[b].rawy) : (ap->blk_locs[a].rawx < ap->blk_locs[b].rawx); - }); - - /* - * Generate initial source cut. It cuts logic blocks in region r into 2 partitions. - * Initially, ensure that both partitions have similar numbers of logic blocks. - * Find the midpoint (in terms of total block size, including macros) in sorted cut_blks - * This is the initial source cut - */ - int clearance_l, clearance_r; - int pivot = initial_source_cut(r, cut_blks, dir, clearance_l, clearance_r); - - /* - * Generate initial target cut. It cuts the physical tiles into 2 sub-areas, into which - * the 2 partitions of logic blocks will be placed. - * - * The difference in utilization (# blocks / # tiles) should be smallest, while meeting - * clearance requirement for macros - */ - int left_blks_n, right_blks_n, left_tiles_n, right_tiles_n; - int best_tgt_cut = initial_target_cut(r, cut_blks, pivot, dir, trimmed_l, trimmed_r, - clearance_l, clearance_r, left_blks_n, right_blks_n, left_tiles_n, right_tiles_n); - if (best_tgt_cut == -1) // target cut fails clearance requirement for macros - return CUT_FAIL; - - // Once target_cut is acquired, define left and right subareas - // The boundaries are defined using the trimmed edges and best target cut - // The n_tiles will be final while n_blks may change by perturbing the source cut to eliminate - // overutilization in subareas - SpreaderRegion rl, rr; - rl.id = int(regions.size()); - rl.bb = dir ? vtr::Rect{r.bb.xmin(), trimmed_l, r.bb.xmax(), best_tgt_cut} - : vtr::Rect{trimmed_l, r.bb.ymin(), best_tgt_cut, r.bb.ymax()}; - rl.n_blks = left_blks_n; - rl.n_tiles = left_tiles_n; - rr.id = int(regions.size()) + 1; - rr.bb = dir ? vtr::Rect{r.bb.xmin(), best_tgt_cut + 1, r.bb.xmax(), trimmed_r} - : vtr::Rect{best_tgt_cut + 1, r.bb.ymin(), trimmed_r, r.bb.ymax()}; - rr.n_blks = right_blks_n; - rr.n_tiles = right_tiles_n; - // change the region IDs in each subarea's grid location to subarea's id - for (int x = rl.bb.xmin(); x <= rl.bb.xmax(); x++) - for (int y = rl.bb.ymin(); y <= rl.bb.ymax(); y++) - reg_id_at_grid[x][y] = rl.id; - for (int x = rr.bb.xmin(); x <= rr.bb.xmax(); x++) - for (int y = rr.bb.ymin(); y <= rr.bb.ymax(); y++) - reg_id_at_grid[x][y] = rr.id; - - /* - * Perturb source cut to eliminate over-utilization - * This is done by moving logic blocks from overused subarea to the other subarea one at a time - * until they are no longer overused. - */ - // while left subarea is over-utilized, move logic blocks to the right subarea one at a time - while (pivot > 0 && rl.overused(ap->ap_cfg.beta)) { - auto& move_blk = cut_blks.at(pivot); - int size = (place_macros.get_imacro_from_iblk(move_blk) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(move_blk)].members.size() : 1; - rl.n_blks -= size; - rr.n_blks += size; - pivot--; - } - // while right subarea is over-utilized, move logic blocks to the left subarea one at a time - while (pivot < int(cut_blks.size()) - 1 && rr.overused(ap->ap_cfg.beta)) { - auto& move_blk = cut_blks.at(pivot + 1); - int size = (place_macros.get_imacro_from_iblk(move_blk) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(move_blk)].members.size() : 1; - rl.n_blks += size; - rr.n_blks -= size; - pivot++; - } - - // within each subarea, spread the logic blocks into bins to make them more evenly spread out - linear_spread_subarea(cut_blks, dir, 0, pivot + 1, rl); - linear_spread_subarea(cut_blks, dir, pivot + 1, cut_blks.size(), rr); - - // push subareas back to regions so that they can be accessed by their IDs later - regions.push_back(rl); - regions.push_back(rr); - - return std::make_pair(rl.id, rr.id); -} - -// copy all logic blocks to cut into cut_blks -void CutSpreader::init_cut_blks(SpreaderRegion& r, std::vector& cut_blks) { - cut_blks.clear(); - for (int x = r.bb.xmin(); x <= r.bb.xmax(); x++) { - for (int y = r.bb.ymin(); y <= r.bb.ymax(); y++) { - std::copy(blks_at_location[x][y].begin(), blks_at_location[x][y].end(), std::back_inserter(cut_blks)); - } - } -} - -/* - * Trim the boundaries of the region r in axis-of-interest dir, skipping any rows/cols without - * tiles of the right type. - * Afterwards, move blocks in trimmed locations to new trimmed boundaries - */ -std::pair CutSpreader::trim_region(SpreaderRegion& r, bool dir) { - int bb_min = dir ? r.bb.ymin() : r.bb.xmin(); - int bb_max = dir ? r.bb.ymax() : r.bb.xmax(); - int trimmed_l = bb_min, trimmed_r = bb_max; - bool have_tiles = false; - while (trimmed_l < bb_max && !have_tiles) { // trim from left - for (int i = bb_min; i <= bb_max; i++) - if (tiles_at(dir ? i : trimmed_l, dir ? trimmed_l : i) > 0) { - have_tiles = true; - break; - } - if (!have_tiles) // trim when the row/col doesn't have tiles - trimmed_l++; - } - - have_tiles = false; - while (trimmed_r > bb_min && !have_tiles) { // trim from right - for (int i = bb_min; i <= bb_max; i++) - if (tiles_at(dir ? i : trimmed_r, dir ? trimmed_r : i) > 0) { - have_tiles = true; - break; - } - if (!have_tiles) // trim when the row/col doesn't have tiles - trimmed_r--; - } - - // move blocks from trimmed locations to new boundaries - for (int x = r.bb.xmin(); x < (dir ? r.bb.xmax() + 1 : trimmed_l); x++) { - for (int y = r.bb.ymin(); y < (dir ? trimmed_l : r.bb.ymax() + 1); y++) { - for (auto& blk : blks_at_location[x][y]) { - // new location is the closest trimmed boundary - int blk_new_x = dir ? x : trimmed_l, blk_new_y = dir ? trimmed_l : y; - ap->blk_locs[blk].rawx = blk_new_x; - ap->blk_locs[blk].rawy = blk_new_y; - ap->blk_locs[blk].loc.x = blk_new_x; - ap->blk_locs[blk].loc.y = blk_new_y; - blks_at_location[blk_new_x][blk_new_y].push_back(blk); - } - blks_at_location[x][y].clear(); // clear blocks at old location - } - } - - for (int x = (dir ? r.bb.xmin() : trimmed_r + 1); x <= r.bb.xmax(); x++) { - for (int y = (dir ? trimmed_r + 1 : r.bb.ymin()); y <= r.bb.ymax(); y++) { - for (auto& blk : blks_at_location[x][y]) { - // new location is the closest trimmed boundary - int blk_new_x = dir ? x : trimmed_r, blk_new_y = dir ? trimmed_r : y; - ap->blk_locs[blk].rawx = blk_new_x; - ap->blk_locs[blk].rawy = blk_new_y; - ap->blk_locs[blk].loc.x = blk_new_x; - ap->blk_locs[blk].loc.y = blk_new_y; - blks_at_location[blk_new_x][blk_new_y].push_back(blk); - } - blks_at_location[x][y].clear(); // clear blocks at old location - } - } - - return {trimmed_l, trimmed_r}; -} - -/* - * generate the initial source_cut for region r, ensure there is enough clearance on either side of the - * initial cut to accommodate macros - * returns the initial source cut (index into cut_blks) - * returns the clearance in clearance_l, clearance_r - * returns -1 if cannot generate initial source_cut (not enough clearance for macros) - * - * see CutSpreader::cut_region() invocation of initial_source_cut for more detail - */ -int CutSpreader::initial_source_cut(SpreaderRegion& r, - std::vector& cut_blks, - bool dir, - int& clearance_l, - int& clearance_r) { - const auto& place_macros = ap->place_macros_; - - // pivot is the midpoint of cut_blks in terms of total block size (counting macro members) - // this ensures the initial partitions have similar number of blocks - int pivot_blks = 0; // midpoint in terms of total number of blocks - int pivot = 0; // midpoint in terms of index of cut_blks - for (auto& blk : cut_blks) { - // if blk is part of macro (only macro heads in cut_blks, no macro members), add that macro's size - pivot_blks += (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(blk)].members.size() : 1; - if (pivot_blks >= r.n_blks / 2) - break; - pivot++; - } - if (pivot >= int(cut_blks.size())) - pivot = int(cut_blks.size()) - 1; - - // Find clearance required on either side of the pivot - // i.e. minimum distance from left and right bounds of region to pivot - // (no cut within clearance to accommodate macros) - clearance_l = 0, clearance_r = 0; - for (size_t i = 0; i < cut_blks.size(); i++) { - int size; - if (blk_extents.count(cut_blks.at(i))) { - auto& be = blk_extents[cut_blks.at(i)]; - size = dir ? (be.ymax() - be.ymin() + 1) : (be.xmax() - be.xmin() + 1); - } else { - size = 1; - } - if (int(i) < pivot) - clearance_l = std::max(clearance_l, size); - else - clearance_r = std::max(clearance_r, size); - } - return pivot; -} - -/* - * generate the initial target_cut for region r, ensure that utilization in 2 subareas are closest possible - * while meeting clearance requirements for macros - * returns best target cut - */ -int CutSpreader::initial_target_cut(SpreaderRegion& r, - std::vector& cut_blks, - int init_source_cut, - bool dir, - int trimmed_l, - int trimmed_r, - int clearance_l, - int clearance_r, - int& left_blks_n, - int& right_blks_n, - int& left_tiles_n, - int& right_tiles_n) { - const auto& place_macros = ap->place_macros_; - - // To achieve smallest difference in utilization, first move all tiles to right partition - left_blks_n = 0, right_blks_n = 0; - left_tiles_n = 0, right_tiles_n = r.n_tiles; - // count number of blks in each partition, from initial source cut - for (int i = 0; i <= init_source_cut; i++) - left_blks_n += (place_macros.get_imacro_from_iblk(cut_blks.at(i)) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(cut_blks.at(i))].members.size() : 1; - for (int i = init_source_cut + 1; i < int(cut_blks.size()); i++) - right_blks_n += (place_macros.get_imacro_from_iblk(cut_blks.at(i)) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(cut_blks.at(i))].members.size() : 1; - - int best_tgt_cut = -1; - double best_deltaU = std::numeric_limits::max(); - - // sweep source cut from left to right, moving tiles from right partition to the left - // calculate the difference in utilization for all target cuts, return the best result - for (int i = trimmed_l; i <= trimmed_r; i++) { - int slither_tiles = 0; - for (int j = dir ? r.bb.xmin() : r.bb.ymin(); j <= (dir ? r.bb.xmax() : r.bb.ymax()); j++) { - slither_tiles += dir ? tiles_at(j, i) : tiles_at(i, j); - } - - left_tiles_n += slither_tiles; - right_tiles_n -= slither_tiles; - - if (((i - trimmed_l) + 1) >= clearance_l && ((trimmed_r - i) + 1) >= clearance_r) { - // if solution accommodates macro clearances - // compare difference in utilization - double tmpU = std::abs(double(left_blks_n) / double(std::max(left_tiles_n, 1)) - double(right_blks_n) / double(std::max(right_tiles_n, 1))); - if (tmpU < best_deltaU) { - best_deltaU = tmpU; - best_tgt_cut = i; - } - } - } - - if (best_tgt_cut == -1) // failed clearance requirement for macros - return best_tgt_cut; - - // update number of tiles for each subarea - left_tiles_n = 0, right_tiles_n = 0; - for (int x = r.bb.xmin(); x <= (dir ? r.bb.xmax() : best_tgt_cut); x++) - for (int y = r.bb.ymin(); y <= (dir ? best_tgt_cut : r.bb.ymax()); y++) - left_tiles_n += tiles_at(x, y); - for (int x = dir ? r.bb.xmin() : (best_tgt_cut + 1); x <= r.bb.xmax(); x++) - for (int y = dir ? (best_tgt_cut + 1) : r.bb.ymin(); y <= r.bb.ymax(); y++) - right_tiles_n += tiles_at(x, y); - - if (left_tiles_n == 0 || right_tiles_n == 0) - // target cut failed since all tiles are still in one subarea - return -1; - - return best_tgt_cut; -} - -/* - * Spread blocks in subarea by linear interpolation - * blks_start and blks_end are indices into cut_blks. The blks between these indices will be spread by: - * * first split the subarea boundaries (area_l and area_r) - * into min(number_of_logic_blocks_in_subarea, 10) number of bins. - * * split the logic blocks into the corresponding number of groups - * * place the logic blocks from their group to their bin, by linear interpolation using their original - * locations to map to a new location in the bin. - */ -void CutSpreader::linear_spread_subarea(std::vector& cut_blks, - bool dir, - int blks_start, - int blks_end, - SpreaderRegion& sub_area) { - double area_l = dir ? sub_area.bb.ymin() : sub_area.bb.xmin(); // left boundary - double area_r = dir ? sub_area.bb.ymax() : sub_area.bb.xmax(); // right boundary - int N = blks_end - blks_start; // number of logic blocks in subarea - if (N <= 2) { // only 1 bin, skip binning and directly linear interpolate - for (int i = blks_start; i < blks_end; i++) { - auto& pos = dir ? ap->blk_locs[cut_blks.at(i)].rawy - : ap->blk_locs[cut_blks.at(i)].rawx; - pos = area_l + (i - blks_start) * ((area_r - area_l) / N); - } - } else { - // Split tiles into K bins, split blocks into K groups - // Since cut_blks are sorted, to specify block groups, only need the index of the left and right block - // Each block group has its original left and right bounds, the goal is to map this group's bound into - // bin's bounds, and assign new locations to blocks using linear interpolation - int K = std::min(N, 10); // number of bins/groups - std::vector> bin_bounds; // (0-th group's first block, 0-th bin's left bound) - bin_bounds.emplace_back(blks_start, area_l); - for (int i_bin = 1; i_bin < K; i_bin++) - // find i-th group's first block, i-th bin's left bound - bin_bounds.emplace_back(blks_start + (N * i_bin) / K, area_l + ((area_r - area_l + 0.99) * i_bin) / K); - bin_bounds.emplace_back(blks_end, area_r + 0.99); // find K-th group's last block, K-th bin's right bound - for (int i_bin = 0; i_bin < K; i_bin++) { - auto &bl = bin_bounds.at(i_bin), br = bin_bounds.at(i_bin + 1); // i-th bin's left and right bound - // i-th group's original bounds (left and right most block's original location) - double group_left = dir ? ap->blk_locs[cut_blks.at(bl.first)].rawy - : ap->blk_locs[cut_blks.at(bl.first)].rawx; - double group_right = dir ? ap->blk_locs[cut_blks.at(br.first - 1)].rawy - : ap->blk_locs[cut_blks.at(br.first - 1)].rawx; - double bin_left = bl.second; - double bin_right = br.second; - // mapping from i-th block group's original bounds to i-th bin's bounds - double mapping = (bin_right - bin_left) / std::max(0.00001, group_right - group_left); // prevent division by 0 - // map blks in i-th group to new location in i-th bin using linear interpolation - for (int i_blk = bl.first; i_blk < br.first; i_blk++) { - // new location is stored back into rawx/rawy - auto& blk_pos = dir ? ap->blk_locs[cut_blks.at(i_blk)].rawy - : ap->blk_locs[cut_blks.at(i_blk)].rawx; - - blk_pos = bin_left + mapping * (blk_pos - group_left); // linear interpolation - } - } - } - - // Update blks_at_location for each block with their new location - for (int x = sub_area.bb.xmin(); x <= sub_area.bb.xmax(); x++) - for (int y = sub_area.bb.ymin(); y <= sub_area.bb.ymax(); y++) { - blks_at_location[x][y].clear(); - } - for (int i_blk = blks_start; i_blk < blks_end; i_blk++) { - auto& bl = ap->blk_locs[cut_blks[i_blk]]; - bl.loc.x = std::min(sub_area.bb.xmax(), std::max(sub_area.bb.xmin(), int(bl.rawx))); - bl.loc.y = std::min(sub_area.bb.ymax(), std::max(sub_area.bb.ymin(), int(bl.rawy))); - blks_at_location[bl.loc.x][bl.loc.y].push_back(cut_blks[i_blk]); - } -} - -/* - * @brief: Greedy strict legalize using algorithm described in algorithm overview above. - * - * Input illegal placement from data members (blk_locs) in analytic_placer - * - * @return: both ap->blk_locs and vpr_ctx.mutable_placement() are modified with legal placement, - * to be used in next solve/spread/legalize iteration or to pass back to annealer. - */ -void CutSpreader::strict_legalize() { - auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& block_locs = ap->blk_loc_registry_ref_.block_locs(); - const auto& place_macros = ap->place_macros_; - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - // clear the location of all blocks in place_ctx - for (auto blk : clb_nlist.blocks()) { - if (!block_locs[blk].is_fixed && (ap->row_num[blk] != DONT_SOLVE || (place_macros.get_imacro_from_iblk(blk) != NO_MACRO && ap->row_num[place_macros.macro_head(blk)] != DONT_SOLVE))) { - unbind_tile(block_locs[blk].loc); - } - } - - // Greedy largest-macro-first approach - // put all blocks being placed in current AP in priority_queue "remaining" with the priority being the - // length of the macro they are in (for single blocks, priority = 1). - // This prioritizes the placement of longest macros over single blocks - std::priority_queue> remaining; - for (ClusterBlockId blk : ap->solve_blks) { - if (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) { // blk is head block of a macro (only head blks are solved) - remaining.emplace(place_macros[place_macros.get_imacro_from_iblk(blk)].members.size(), blk); - } else { - remaining.emplace(1, blk); - } - } - - /* - * ripup_radius determines at which point already placed single logic blocks will be "ripped up" for placement of - * the current block. Specifically, when radius of random selection (determined by availability of compatible sub_tiles) - * is larger than ripup_radius, occupied sub_tiles are also considered for blk's placement (not just unoccupied sub_tiles). - * - * Therefore, a small ripup_radius honors the current location of blk (from spreading) more, as it allows placement at - * occupied sub_tiles when random selection radius around current location is still small. When ripup_radius is large, - * blk can only search unoccupied sub_tiles in a large area before it can rip up placed blks. This will make blk more likely - * to stray far from current location. - * - * ripup_radius is doubled every time outer while-loop executes (ap->solve_blks.size()) times, - * i.e. after trying to place each block once, if there's still block to place (some block displaced/ripped up other blocks), - * ripup_radius is doubled, allowing these ripped up blocks to look for unoccupied sub_tiles in a larger area. - * - * Only applies for single blocks - */ - int ripup_radius = 2; - // num of iters of outer most while loop, cleared when it equals the number of blocks that needs to be place for this - // build-solve-legalize iteration. When cleared, ripup_radius is doubled. - int total_iters = 0; - // total_iters without clearing, used for time-out - int total_iters_noreset = 0; - - // outer while loop, each loop iteration aims to place one solve_blk (either single blk or head blk of a macro) - while (!remaining.empty()) { - auto top = remaining.top(); - remaining.pop(); - ClusterBlockId blk = top.second; - - if (is_placed(blk)) // ignore if already placed - continue; - - int radius = 0; // radius of 0 means initial candidate location is the current location of blk after spreading - int iter = 0; // iterations of the inner while-loop, used for timeout - - /* - * iter_at_radius: number of inner-loop iterations (number of proposed candidate locations) at current radius - * used to determine whether to explore more candidate locations (iter_at_radius < explore limit) - * or take the current best_subtile for blk - * - * only applies for single blocks - */ - int iter_at_radius = 0; - bool placed = false; // flag for inner-loop - t_pl_loc best_subtile = t_pl_loc{}; // current best candidate with smallest best_inp_len, only for single blocks - int best_inp_len = std::numeric_limits::max(); // used to choose best_subtile, only for single blocks - - total_iters++; - total_iters_noreset++; - - // clear total_iters and double ripup_radius when all solve_blks have been attempted to place once - if (total_iters > int(ap->solve_blks.size())) { - total_iters = 0; - ripup_radius = std::min(std::max(max_x - 1, max_y - 1), ripup_radius * 2); - } - - // timeout - // VTR_ASSERT(total_iters_noreset <= std::max(5000, 8 * int(clb_nlist.blocks().size()))); - - while (!placed) { // while blk is not placed - // timeout - VTR_ASSERT(iter <= std::max(10000, 3 * int(clb_nlist.blocks().size()))); - - // randomly choose a location within radius around current location (given by spreading) - int nx = rand() % (2 * radius + 1) + std::max(ap->blk_locs[blk].loc.x - radius, 0); - int ny = rand() % (2 * radius + 1) + std::max(ap->blk_locs[blk].loc.y - radius, 0); - - iter++; - iter_at_radius++; - if (iter >= (10 * (radius + 1))) { // a heuristic to determine when to increase radius - // check if there's sub_tiles of right type within radius. - // If no, increase radius until at least 1 compatible sub_tile is found - radius = std::min(std::max(max_x - 1, max_y - 1), radius + 1); - while (radius < std::max(max_x - 1, max_y - 1)) { - // search every location within radius for compatible sub_tiles - for (int x = std::max(0, ap->blk_locs[blk].loc.x - radius); - x <= std::min(max_x - 1, ap->blk_locs[blk].loc.x + radius); - x++) { - for (int y = std::max(0, ap->blk_locs[blk].loc.y - radius); - y <= std::min(max_y - 1, ap->blk_locs[blk].loc.y + radius); - y++) { - if (subtiles_at_location[x][y].size() > 0) // compatible sub_tiles found within radius - goto notempty; - } - } - // no sub_tiles found, increase radius - radius = std::min(std::max(max_x - 1, max_y - 1), radius + 1); - } - notempty: - iter_at_radius = 0; - iter = 0; - } - - if (nx < 0 || nx >= max_x || ny < 0 || ny >= max_y || subtiles_at_location[nx][ny].empty()) - // try another random location if candidate location is illegal or has no sub_tiles - continue; - - /* - * explore_limit determines when to stop exploring for better sub_tiles for blk - * When explore_limit is not met (iter_at_radius < explore_limit), each candidate sub_tile is evaluated based on - * their resulting total input wirelength (a heuristic) for blk. - * When explore_limit is met and a best_sub_tile is found, blk is placed there. - * - * Only applies for single blocks - * @see comments for try_place_blk() - */ - int explore_limit = 2 * radius; - - // if blk is not a macro member - if (place_macros.get_imacro_from_iblk(blk) == NO_MACRO) { - placed = try_place_blk(blk, - nx, - ny, - radius > ripup_radius, // bool ripup_radius_met - iter_at_radius >= explore_limit, // bool exceeds_explore_limit - best_inp_len, - best_subtile, - remaining); - } else { - placed = try_place_macro(blk, - nx, - ny, - remaining); - } - } - } -} - -/* - * Helper function in strict_legalize() - * Place blk on sub_tile location by modifying place_ctx.grid_blocks, place_ctx.block_locs, and ap->blk_locs[blk].loc - */ -void CutSpreader::bind_tile(t_pl_loc sub_tile, ClusterBlockId blk) { - auto& grid_blocks = ap->blk_loc_registry_ref_.mutable_grid_blocks(); - auto& block_locs = ap->blk_loc_registry_ref_.mutable_block_locs(); - - VTR_ASSERT(grid_blocks.block_at_location(sub_tile) == ClusterBlockId::INVALID()); - VTR_ASSERT(block_locs[blk].is_fixed == false); - grid_blocks.set_block_at_location(sub_tile, blk); - block_locs[blk].loc = sub_tile; - grid_blocks.increment_usage({sub_tile.x, sub_tile.y, sub_tile.layer}); - ap->blk_locs[blk].loc = sub_tile; -} - -/* - * Helper function in strict_legalize() - * Remove placement at sub_tile location by clearing place_ctx.block_locs and place_Ctx.grid_blocks - */ -void CutSpreader::unbind_tile(t_pl_loc sub_tile) { - auto& grid_blocks = ap->blk_loc_registry_ref_.mutable_grid_blocks(); - auto& block_locs = ap->blk_loc_registry_ref_.mutable_block_locs(); - - VTR_ASSERT(grid_blocks.block_at_location(sub_tile) != ClusterBlockId::INVALID()); - ClusterBlockId blk = grid_blocks.block_at_location(sub_tile); - VTR_ASSERT(block_locs[blk].is_fixed == false); - block_locs[blk].loc = t_pl_loc{}; - grid_blocks.set_block_at_location(sub_tile, ClusterBlockId::INVALID()); - grid_blocks.decrement_usage({sub_tile.x, sub_tile.y, sub_tile.layer}); -} - -/* - * Helper function in strict_legalze() - * Check if the block is placed in place_ctx (place_ctx.block_locs[blk] has a location that matches - * the block in place_ctx.grid_blocks) - */ -bool CutSpreader::is_placed(ClusterBlockId blk) { - const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); - const auto& block_locs = ap->blk_loc_registry_ref_.block_locs(); - - if (block_locs[blk].loc != t_pl_loc{}) { - auto loc = block_locs[blk].loc; - VTR_ASSERT(grid_blocks.block_at_location(loc) == blk); - return true; - } - return false; -} - -/* - * Sub-routine of strict_legalize() - * Tries to place a single block "blk" at a candidate location nx, ny. Returns whether the blk is successfully placed. - * - * If number of iterations at current radius has exceeded the exploration limit (exceeds_explore_limit), - * and a candidate sub_tile is already found (best_subtile), then candidate location is ignored, and blk is - * placed in best_subtile. - * - * Else, if exploration limit is not exceeded, the sub_tiles at nx, ny are evaluated on the blk's resulting total - * input wirelength (a heuristic). If this total input wirelength is shorter than current best_inp_len, it becomes - * the new best_subtile. - * If exploration limit is exceeded and no candidate sub_tile is available in (best_subtile), then blk is placed at - * next compatible sub_tile at candidate location nx, ny. - * - * If blk displaces a logic block by taking its sub_tile, the displaced logic block is put back into remaining queue. - */ -bool CutSpreader::try_place_blk(ClusterBlockId blk, - int nx, - int ny, - bool ripup_radius_met, - bool exceeds_explore_limit, - int& best_inp_len, - t_pl_loc& best_subtile, - std::priority_queue>& remaining) { - const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->place_macros_; - - // iteration at current radius has exceeded exploration limit, and a candidate sub_tile (best_subtile) is found - // then blk is placed in best_subtile - if (exceeds_explore_limit && best_subtile != t_pl_loc{}) { - // find the logic block bound to (placed on) best_subtile - ClusterBlockId bound_blk = grid_blocks.block_at_location(best_subtile); - if (bound_blk) { // if best_subtile has a logic block - unbind_tile(best_subtile); // clear bound_block and best_subtile's placement info - remaining.emplace(1, bound_blk); // put bound_blk back into remaining blocks to place - } - bind_tile(best_subtile, blk); // place blk on best_subtile - return true; - } - - // if exploration limit is not met or a candidate sub_tile is not found yet - for (auto sub_t : subtiles_at_location[nx][ny]) { // for each available sub_tile at random location - ClusterBlockId bound_blk = grid_blocks.block_at_location(sub_t); // logic blk at [nx, ny] - if (bound_blk == ClusterBlockId::INVALID() - || ripup_radius_met - || rand() % (20000) < 10) { - /* conditions when a sub_tile at nx, ny is considered: - * - sub_tile is not occupied (no bound_blk) - * - occupied sub_tile is considered when: - * 1) current radius > ripup-radius. (see strict_legalize() for more details) - * OR - * 2) a 0.05% chance of acceptance. - */ - if (bound_blk && place_macros.get_imacro_from_iblk(bound_blk) != NO_MACRO) - // do not sub_tiles when the block placed on it is part of a macro, as they have higher priority - continue; - if (!exceeds_explore_limit) { // if still in exploration phase, find best_subtile with smallest best_inp_len - int input_len = 0; - // find all input pins and add up input wirelength - for (auto pin : clb_nlist.block_input_pins(blk)) { - ClusterNetId net = clb_nlist.pin_net(pin); - if (net == ClusterNetId::INVALID() - || clb_nlist.net_is_ignored(net) - || clb_nlist.net_driver(net) == ClusterPinId::INVALID()) - continue; - ClusterBlockId driver = clb_nlist.pin_block(clb_nlist.net_driver(net)); - auto driver_loc = ap->blk_locs[driver].loc; - input_len += std::abs(driver_loc.x - nx) + std::abs(driver_loc.y - ny); - } - if (input_len < best_inp_len) { - // update best_subtile - best_inp_len = input_len; - best_subtile = sub_t; - } - break; - } else { // exploration phase passed and still no best_subtile yet, choose the next compatible sub_tile - if (bound_blk) { - remaining.emplace(1, bound_blk); - unbind_tile(sub_t); // remove bound_blk and place blk on sub_t - } - bind_tile(sub_t, blk); - return true; - } - } - } - return false; -} - -/* - * Sub-routine of strict_legalize() - * - * Tries to place the macro with the head block on candidate location nx, ny. Returns if the macro is successfully placed. - * - * For each possible macro placement starting from nx, ny, if any block's position in the macro does not have compatible - * sub_tiles or overlaps with another macro, the placement is impossible. - * - * If a possible placement is found, it's applied to all blocks. - */ -bool CutSpreader::try_place_macro(ClusterBlockId blk, - int nx, - int ny, - std::priority_queue>& remaining) { - const auto& place_macros = ap->place_macros_; - const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - for (auto sub_t : subtiles_at_location[nx][ny]) { - std::vector> targets; // contains the target placement location for each macro block - std::queue> visit; // visit goes through all macro members once - visit.emplace(blk, sub_t); // push head block and target sub_tile first - bool placement_impossible = false; // once set to true, break while loop and try next sub_t - while (!visit.empty()) { // go through every macro block - ClusterBlockId visit_blk = visit.front().first; - VTR_ASSERT(!is_placed(visit_blk)); - t_pl_loc target = visit.front().second; // target location - visit.pop(); - - // ensure the target location has compatible tile - auto blk_t = clb_nlist.block_type(blk); - auto result = std::find(blk_t->equivalent_tiles.begin(), blk_t->equivalent_tiles.end(), g_vpr_ctx.device().grid.get_physical_type({target.x, target.y, target.layer})); - if (result == blk_t->equivalent_tiles.end()) { - placement_impossible = true; - break; - } - - // if the target location has a logic block, ensure it's not part of a macro - // because a macro placed before the current one has higher priority (longer chain) - ClusterBlockId bound = grid_blocks.block_at_location(target); - if (bound && place_macros.get_imacro_from_iblk(bound) != NO_MACRO) { - placement_impossible = true; - break; - } - // place macro block into target vector along with its target location - targets.emplace_back(visit_blk, target); - if (place_macros.macro_head(visit_blk) == visit_blk) { // if visit_blk is the head block of the macro - // push all macro members to visit queue along with their calculated positions - const std::vector& members = place_macros[place_macros.get_imacro_from_iblk(blk)].members; - for (auto member = members.begin() + 1; member != members.end(); ++member) { - t_pl_loc mloc = target + member->offset; // calculate member_loc using (head blk location + offset) - visit.emplace(member->blk_index, mloc); - } - } - } - - if (!placement_impossible) { // if placement is possible, apply this placement - for (auto& target : targets) { - ClusterBlockId bound = grid_blocks.block_at_location(target.second); - if (bound) { - // if target location has a logic block, displace it and put it in remaining queue to be placed later - unbind_tile(target.second); - remaining.emplace(1, bound); - } - bind_tile(target.second, target.first); - } - return true; - } - } - return false; -} - -#endif /* ENABLE_ANALYTIC_PLACE */ diff --git a/vpr/src/place/cut_spreader.h b/vpr/src/place/cut_spreader.h deleted file mode 100644 index 5be5f0ed79d..00000000000 --- a/vpr/src/place/cut_spreader.h +++ /dev/null @@ -1,378 +0,0 @@ -#ifndef VPR_SRC_PLACE_LEGALIZER_H_ -#define VPR_SRC_PLACE_LEGALIZER_H_ - -#ifdef ENABLE_ANALYTIC_PLACE - -/** - * @file - * @brief This file defines the cut-spreader class with a greedy legalizer as a member method. - * Cut-spreader roughly legalizes overutilized tiles present in illegal placement from the matrix equation - * solution (lower-bound placement), using geometric partitioning to recursively cut and spread tiles within - * these regions, eliminating most overutilizations. - * Legalizer then strictly legalizes the placement using a greedy strategy, ensuring logic block to physical - * subtile type-matching and eliminating all overutilizations. This completes the lower-bound placement. - * - ************************************************************************************************************** - * Algorithm Overview * - ************************************************************************************************************** - * The solution produced by the solver almost always contains 2 types of illegality: overutilization and - * logical-physical type mismatch. - * - * Cut-Spreader - * ============ - * To resolve overutilization, a recursive partitioning-style placement approach is used. It consists of the following - * steps: - * - * find_overused_regions & expand_regions - * -------------------------------------- - * @see find_overused_regions() - * @see expand_regions() - * The first step is to find an area of the FPGA that is overutilized for which the blocks contained within - * must be spread to a larger area. To obtain this overutilized area, adjacent locations on the FPGA that are - * occupied by more than one block (also overutilized) are repeatedly clustered together, until all clusters - * are bordered on all sides by non-overutilized locations. Next, the area is expanded in both the x and y - * directions until it's large enough to accommodate all blocks contained. Overutilization is defined as follows: - * (Occupancy / Capacity) > beta, where beta is a constant <=1, currently defined in AnalyticPlacer::PlacerHeapCfg. - * - * cut_region - * ---------- - * @see cut_region() - * @see run() - * In the second step, two cuts are generated: a source cut and a target cut. The source cut pertains to the blocks - * being placed; the target cut pertains to the area into which the blocks are placed. The source cut splits the - * blocks into two partitions, while the target cut splits the area into two sub-areas, into which the blocks in - * each partition are spread. Two objectives are minimized during this process: the imbalance between the number of - * blocks in each partition, and the difference in the utilization (Occupancy / Capacity) of each subarea. - * - * To generate the source cut, the logic blocks are sorted by their raw_x or raw_y location, depending on the - * orientation of the desired cut. After sorting, a pivot is chosen, all blocks to the left of the pivot are - * assigned to the left partition, and all blocks to the right are assigned to the right partition (we use left - * for left/top, right for right/bottom in x/y directions respectively in the implementation). - * - * The target cut is an x or y cut of the area such that all blocks in each partition fit in their respective - * subareas, and the difference in utilization is minimized. This is difficult due to the discrete nature of FPGA - * architecture. To achieve this, first assign all tiles to right region, then move tiles to the left one by one, - * calculating the difference in utilization for each move. The move with smallest delta_utilization is chosen as - * the target cut. To eliminate possible overutilization in either subarea, perturb the source cut by moving a - * single block from the over-utilized sub-area to the other, until neither is overutilized. - * - * Next, the blocks in sub-areas are spread to distribute them evenly. We split the sub-area into 10 equally-sized - * bins and logic blocks into 10 equal-capacity source bins. Then linearly interpolate to map blocks from their - * original locations in their source bins to new spread location in target bins. - * - * This cutting and spreading is repeated recursively. The cut-spreading process returns the left and right - * (or top and bottom) subareas, which are pushed into a workqueue FIFO. Their direction of cut in the next - * cut-spreading process is alternated, i.e. if the first cut is in y direction, the resulting left and right - * sub-areas are further cut in x direction, each producing 2 subareas top and bottom, and so forth. - * The first region in the FIFO is then popped and goes through cut-spreading. This process is repeated until the base - * case of only 1 block in the region is reached. At this point the placement is mostly not overutilized and ready - * for strict legalization. - * - * ************************************************************************************************************** - * - * Strict Legalizer - * ================ - * @see strict_legalize() - * Strict Legalizer ensures that the placement is strictly legal. It does so using a greedy approach. - * - * All blocks are sorted in descending macro lengths order and put in a priority queue (only macro heads are - * considered, while the rest of the macro members are ignored; single blocks have length 1). Each block goes through - * the following procedure: - * - * * Find all compatible sub_tile types, based on which all potential sub_tile locations are found (this process is - * made computationally cheap by legal_pos data member in AnalyticPlacer) - * * Within a radius (starting from 0) of the block's currently location, randomly choose a location as candidate. - * * If the block is a single block (not in macro), multiple candidates are potentially chosen, and the one that - * results in the smallest input wirelength (sum of wirelengths to its inputs) for the block is chosen. - * * If the block is a macro head, the location for all member blocks are calculated using member offsets. If all - * member locations have compatible sub_tile and does not overlap with another macro, then place the macro. - * * In either case, if the candidate fails to satisfy legality constraints, the radius may increase (depending on - * number of iterations at current radius), and a new candidate will be chosen. - * - * - * @cite SimPL - * Original analytic placer with cut-spreading legalizing was intended for ASIC design, proposed in SimPL. - * SimPL: An Effective Placement Algorithm, Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov - * http://www.ece.umich.edu/cse/awards/pdfs/iccad10-simpl.pdf - * - * @cite HeAP - * FPGA adaptation of SimPL, targeting FPGAs with heterogeneous blocks located at discrete locations. - * Analytical Placement for Heterogeneous FPGAs, Marcel Gort and Jason H. Anderson - * https://janders.eecg.utoronto.ca/pdfs/marcelfpl12.pdf - * - * @cite nextpnr - * An implementation of HeAP, which the cut-spreader and legalizer here is based off of. Implementation details - * have been modified for the architecture and netlist specification of VTR, and better performance. - * nextpnr -- Next Generation Place and Route, placer_heap, David Shah - * https://github.com/YosysHQ/nextpnr - * - */ -#include "vpr_context.h" -#include - -// declaration of used types; -class AnalyticPlacer; -struct t_logical_block_type; - -// Cut-spreader, as described in HeAP/SimPL papers -class CutSpreader { - public: - /* - * @brief: Constructor of CutSpreader - * - * @param analytic_placer pointer to the analytic_placer that invokes this instance of CutSpreader. - * passed for CutSpreader to directly access data members in analytic_placer such as - * blk_locs, blk_info, solve_blks, etc, without re-packaging the data to pass to - * CutSpreader. - * - * @param blk_t logical_block_type for CutSpreader to legalize. Currently can only legalize one - * type each time. - */ - CutSpreader(AnalyticPlacer* analytic_placer, t_logical_block_type_ptr blk_t); - - /* - * @brief: Executes the cut-spreader algorithm described in algorithm overview above. - * Does not include strict_legalize so placement result is not guaranteed to be legal. - * Strict_legalize must run after for legal placement result, and for legal placement to - * be passed to annealer through vpr_ctx. - * - * Input placement is passed by data members (blk_locs) in analytic_placer - * - * @return result placement is passed to strict legalizer by modifying blk_locs in analytic_placer - */ - void cutSpread(); - - /* - * @brief: Greedy strict legalize using algorithm described in algorithm overview above. - * - * Input illegal placement from data members (blk_locs) in analytic_placer, - * previously modified by cut_spreader - * - * @return: both ap->blk_locs and vpr_ctx.mutable_placement() are modified with legal placement, - * to be used in next solve/spread/legalize iteration or to pass back to annealer. - */ - void strict_legalize(); - - private: - // pointer to analytic_placer to access its data members - AnalyticPlacer* ap; - - // block type to legalize - t_logical_block_type_ptr blk_type; - - // struct describing regions on FPGA to cut_spread - struct SpreaderRegion { - int id; // index of regions in regions vector - vtr::Rect bb; // bounding box of the region - int n_blks, n_tiles; // number of netlist blocks and compatible tiles (placement locations) - bool overused(float beta) const { - // determines whether region is overutilized: overused = (Occupancy / Capacity) > beta - if (n_blks > beta * n_tiles) - return true; - else - return false; - } - }; - - // Utilization of each tile, indexed by x, y - vtr::Matrix occupancy; - - // Region ID of each tile, indexed by x, y. AP_NO_REGION if not covered by any region - // Used to check ownership of a grid position by region. - vtr::Matrix reg_id_at_grid; - - // Extent of macro at x, y location. If blk is not in any macros, it only covers a single location - vtr::Matrix> macro_extent; - - // List of logic blocks of blk_type at x, y location, indexed by x, y - // ex. to find all logic blocks occupying location x, y, blks_at_location[x][y] gives a vector of - // block IDs at that location - vtr::Matrix> blks_at_location; - - // List of all compatible sub_tiles for the type of blocks being cut-spread, at location x, y. - // usage: subtiles_at_location[x][y] - vtr::Matrix> subtiles_at_location; - - // List of all SpreaderRegion, index of vector members is the id of the region - std::vector regions; - - // List of all merged_regions, these regions are merged in larger regions and should be skipped when - // recursively cut_spreading. Each entry is the region's ID, which is also the index into the regions vector - std::unordered_set merged_regions; - - // Lookup of macro's extent by block ID. If block is a single block, it contains only 1 tile location - vtr::vector_map> blk_extents; - - // Setup CutSpreader data structures using information from AnalyticPlacer - // including blks_at_location, macros, groups, etc. - void init(); - - // Returns number of logical blocks at x, y location - int occ_at(int x, int y); - - // Returns number of compatible sub_tiles at x, y location - int tiles_at(int x, int y); - - /* - * When expanding a region, it might overlap with another region, one of them (merger) will absorb - * the other (mergee) by merging. @see expand_regions() below; - * - * Merge mergee into merged by: - * * change group id at mergee grids to merged id - * * adds all n_blks and n_tiles from mergee to merged region - * * grow merged to include all mergee grids - */ - void merge_regions(SpreaderRegion& merged, SpreaderRegion& mergee); - - /* - * Grow region r to include a rectangular region - * Pass init = true if first time calling for a newly created region - */ - void grow_region(SpreaderRegion& r, vtr::Rect rect_to_include, bool init = false); - - /* - * Expand all over-utilized regions until they satisfy n_tiles * beta >= n_blocks - * If overutilized regions overlap in this process, they are merged - */ - void expand_regions(); - - /* - * Find overutilized regions surrounded by non-overutilized regions - * Start off at an overutilized tile and expand in x, y directions 1 step at a time in both directions - * until the region is surrounded by non-overutilized regions. - */ - void find_overused_regions(); - - // copy all logic blocks that needs to be cut into cut_blks - void init_cut_blks(SpreaderRegion& r, std::vector& cut_blks); - - /* - * generate the initial source_cut for region r, ensure there is enough clearance on either side of the - * initial cut to accommodate macros - * returns the initial source cut (index into cut_blks) - * returns the clearance in clearance_l, clearance_r - * returns -1 if cannot generate initial source_cut (not enough clearance for macros) - */ - int initial_source_cut(SpreaderRegion& r, - std::vector& cut_blks, - bool dir, - int& clearance_l, - int& clearance_r); - - /* - * generate the initial target_cut for region r, ensure that utilization in 2 subareas are closest possible - * while meeting clearance requirements for macros - * returns best target cut - * returns the resulting number of blocks in left and right partitions in left_blks_n, right_blks_n - * returns the resulting number of tiles in left and right subareas in left_tiles_n, right_tiles_n - */ - int initial_target_cut(SpreaderRegion& r, - std::vector& cut_blks, - int init_source_cut, - bool dir, - int trimmed_l, - int trimmed_r, - int clearance_l, - int clearance_r, - int& left_blks_n, - int& right_blks_n, - int& left_tiles_n, - int& right_tiles_n); - - /* - * Trim the boundaries of the region in axis-of-interest, skipping any rows/cols without any tiles - * of the right type. - * Afterwards, move blocks in trimmed locations to new trimmed boundaries - */ - std::pair trim_region(SpreaderRegion& r, bool dir); - - /* - * Spread blocks in subarea by linear interpolation - * blks_start and blks_end are indices into cut_blks. The blks between these indices will be spread by: - * * first split the subarea (between boundaries area_l and area_r) into - * min(number_of_logic_blocks_in_subarea, 10) number of bins. - * * split the logic blocks into the corresponding number of groups - * * place the logic blocks from their group to their bin, by linear interpolation using their original - * locations to map to a new location in the bin. - */ - void linear_spread_subarea(std::vector& cut_blks, - bool dir, - int blks_start, - int blks_end, - SpreaderRegion& sub_area); - - /* - * Recursive cut-based spreading in HeAP paper - * "left" denotes "-x, -y", "right" denotes "+x, +y" depending on dir - * - * @param r region to cut & spread - * @param dir direction, true for y, false for x - * - * @return a pair of sub-region IDs created from cutting region r. - * BASE_CASE if base case is reached - * CUT_FAIL if cut unsuccessful, need to cut in the other direction - */ - std::pair cut_region(SpreaderRegion& r, bool dir); - - /* - * Helper function in strict_legalize() - * Place blk on sub_tile location by modifying place_ctx.grid_blocks and place_ctx.block_locs - */ - void bind_tile(t_pl_loc sub_tile, ClusterBlockId blk); - - /* - * Helper function in strict_legalize() - * Remove placement at sub_tile location by clearing place_ctx.block_locs and place_Ctx.grid_blocks - */ - void unbind_tile(t_pl_loc sub_tile); - - /* - * Helper function in strict_legalize() - * Check if the block is placed in place_ctx (place_ctx.block_locs[blk] has a location that matches - * the block in place_ctx.grid_blocks) - */ - bool is_placed(ClusterBlockId blk); - - /* - * Sub-routine of strict_legalize() - * Tries to place a single block "blk" at a candidate location nx, ny. Returns whether the blk is succesfully placed. - * - * If number of iterations at current radius has exceeded the exploration limit (exceeds_explore_limit), - * and a candidate sub_tile is already found (best_subtile), then candidate location is ignored, and blk is - * placed in best_subtile. - * - * Else, if exploration limit is not exceeded, the subtiles at nx, ny are evaluated on the blk's resulting total - * input wirelength (a heuristic). If this total input wirelength is shorter than current best_inp_len, it becomes - * the new best_subtile. - * If exploration limit is exceeded and no candidate sub_tile is available in (best_subtile), then blk is placed at - * next sub_tile at candidate location nx, ny. - * - * If blk displaces a logic block by taking its sub_tile, the displaced logic block is put back into remaining queue. - */ - bool try_place_blk(ClusterBlockId blk, - int nx, - int ny, - bool ripup_radius_met, - bool exceeds_need_to_explore, - int& best_inp_len, - t_pl_loc& best_subtile, - std::priority_queue>& remaining); - - /* - * Sub-routine of strict_legalize() - * - * Tries to place the macro with the head block on candidate location nx, ny. Returns if the macro is successfully placed. - * - * For each possible macro placement starting from nx, ny, if any block's position in the macro does not have compatible - * sub_tiles or overlaps with another macro, the placement is impossible. - * - * If a possible placement is found, it's applied to all blocks. - */ - bool try_place_macro(ClusterBlockId blk, - int nx, - int ny, - std::priority_queue>& remaining); -}; -#endif /* ENABLE_ANALYTIC_PLACE */ - -#endif /* VPR_SRC_PLACE_LEGALIZER_H_ */ diff --git a/vpr/src/place/placer.cpp b/vpr/src/place/placer.cpp index d850fb0144b..b2ea7078e95 100644 --- a/vpr/src/place/placer.cpp +++ b/vpr/src/place/placer.cpp @@ -11,7 +11,6 @@ #include "vtr_time.h" #include "draw.h" #include "read_place.h" -#include "analytic_placer.h" #include "initial_placement.h" #include "load_flat_place.h" #include "concrete_timing_info.h" @@ -94,19 +93,6 @@ Placer::Placer(const Netlist<>& net_list, print_place(nullptr, nullptr, placer_opts.write_initial_place_file.c_str(), placer_state_.block_locs()); } -#ifdef ENABLE_ANALYTIC_PLACE - /* - * Cluster-level Analytic Placer: - * Passes in the initial_placement via vpr_context, and passes its placement back via locations marked on - * both the clb_netlist and the gird. - * Most of anneal is disabled later by setting initial temperature to 0 and only further optimizes in quench - */ - if (placer_opts.enable_analytic_placer) { - AnalyticPlacer{blk_loc_registry, place_macros}.ap_place(); - } - -#endif /* ENABLE_ANALYTIC_PLACE */ - // Update physical pin values for (const ClusterBlockId block_id : cluster_ctx.clb_nlist.blocks()) { blk_loc_registry.place_sync_external_block_connections(block_id); @@ -291,12 +277,6 @@ void Placer::place() { const auto& timing_ctx = g_vpr_ctx.timing(); const auto& cluster_ctx = g_vpr_ctx.clustering(); bool analytic_place_enabled = false; -#ifdef ENABLE_ANALYTIC_PLACE - // Cluster-level analytic placer: when enabled, skip most of the annealing and go straight to quench - if (placer_opts_.enable_analytic_placer) { - analytic_place_enabled = true; - } -#endif if (!analytic_place_enabled && !quench_only_) { // Table header diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/config.txt deleted file mode 100644 index b1a0c921261..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/config.txt +++ /dev/null @@ -1,28 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics.v - -# Add architectures to list to sweep -arch_list_add=k6_frac_N10_mem32K_40nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements.txt - -# Script parameters -#script_params="" -script_params = -track_memory_usage --enable_analytic_placer true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt deleted file mode 100644 index 249ce143daf..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt +++ /dev/null @@ -1,2 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.60 vpr 66.94 MiB -1 -1 0.22 18440 3 0.06 -1 -1 33128 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68544 99 130 344 474 1 228 298 12 12 144 clb auto 27.5 MiB 0.10 863 800 1293 264 867 162 66.9 MiB 0.04 0.00 1.86362 1.90582 -117.68 -1.90582 1.90582 0.09 0.000566314 0.000530143 0.0035014 0.00338303 -1 -1 -1 -1 40 1473 16 5.66058e+06 4.21279e+06 333335. 2314.82 0.32 0.11664 0.106115 12666 64609 -1 1318 11 405 616 29250 9869 1.99389 1.99389 -129.176 -1.99389 -0.260939 -0.108257 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0187502 0.0175858 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 443a41856f0..303cdc93c8a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -13,7 +13,6 @@ regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver regression_tests/vtr_reg_strong/strong_absorb_buffers regression_tests/vtr_reg_strong/strong_analysis_only -regression_tests/vtr_reg_strong/strong_analytic_placer regression_tests/vtr_reg_strong/strong_bidir regression_tests/vtr_reg_strong/strong_binary regression_tests/vtr_reg_strong/strong_binary_heap diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/config.txt deleted file mode 100644 index 4dd0bc69c73..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/config.txt +++ /dev/null @@ -1,28 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics.v - -# Add architectures to list to sweep -arch_list_add=k6_frac_N10_mem32K_40nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements.txt - -# Script parameters -#script_params="" -script_params =-start odin -track_memory_usage --enable_analytic_placer true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt deleted file mode 100644 index 300983f84f2..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt +++ /dev/null @@ -1,2 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.81 odin 100.50 MiB 2.18 102912 -1 -1 3 0.19 -1 -1 34104 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67628 99 130 363 493 1 252 298 12 12 144 clb auto 26.8 MiB 0.07 1168 1026 1293 339 819 135 66.0 MiB 0.05 0.00 2.24785 2.1902 -216.85 -2.1902 2.1902 0.09 0.000548458 0.000511942 0.00340329 0.00328177 -1 -1 -1 -1 38 1909 17 5.66058e+06 4.21279e+06 319130. 2216.18 0.37 0.116514 0.106136 12522 62564 -1 1585 12 545 712 54323 17831 2.61371 2.61371 -231.046 -2.61371 0 0 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0185263 0.0173288 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt index 37eedf040f0..4df0977db16 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt @@ -1,6 +1,5 @@ regression_tests/vtr_reg_strong_odin/strong_absorb_buffers regression_tests/vtr_reg_strong_odin/strong_analysis_only -regression_tests/vtr_reg_strong_odin/strong_analytic_placer regression_tests/vtr_reg_strong_odin/strong_bidir regression_tests/vtr_reg_strong_odin/strong_binary regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs From 0d4c7c0f501f7bd127d0f2c3a817ec537883b032 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Sun, 18 May 2025 16:08:14 -0400 Subject: [PATCH 155/176] [Infra] Cleaned Up Header Files in Place Folder --- vpr/src/place/compressed_grid.h | 1 - vpr/src/place/grid_tile_lookup.cpp | 1 + vpr/src/place/grid_tile_lookup.h | 7 +++++-- vpr/src/place/initial_noc_placement.cpp | 5 ----- vpr/src/place/move_transactions.h | 1 - vpr/src/place/move_utils.cpp | 3 --- vpr/src/place/noc_place_checkpoint.h | 4 ++-- vpr/src/place/place_checkpoint.h | 2 -- vpr/src/place/place_constraints.h | 2 +- vpr/src/place/place_util.h | 4 ---- vpr/src/place/placement_log_printer.h | 1 - vpr/src/place/placer_breakpoint.cpp | 5 +++++ vpr/src/place/placer_breakpoint.h | 4 ---- 13 files changed, 14 insertions(+), 26 deletions(-) diff --git a/vpr/src/place/compressed_grid.h b/vpr/src/place/compressed_grid.h index 6f9575fb670..8d6ecd9097b 100644 --- a/vpr/src/place/compressed_grid.h +++ b/vpr/src/place/compressed_grid.h @@ -5,7 +5,6 @@ #include "physical_types.h" #include "vtr_assert.h" -#include "vtr_geometry.h" #include "vtr_flat_map.h" struct t_compressed_block_grid { diff --git a/vpr/src/place/grid_tile_lookup.cpp b/vpr/src/place/grid_tile_lookup.cpp index 45aad729647..aef14f286a2 100644 --- a/vpr/src/place/grid_tile_lookup.cpp +++ b/vpr/src/place/grid_tile_lookup.cpp @@ -1,4 +1,5 @@ #include "grid_tile_lookup.h" +#include "globals.h" #include "physical_types_util.h" GridTileLookup::GridTileLookup() diff --git a/vpr/src/place/grid_tile_lookup.h b/vpr/src/place/grid_tile_lookup.h index b155bf99410..74b858d6238 100644 --- a/vpr/src/place/grid_tile_lookup.h +++ b/vpr/src/place/grid_tile_lookup.h @@ -1,8 +1,11 @@ #ifndef VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ #define VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ -#include "place_util.h" -#include "globals.h" +#include +#include "physical_types.h" +#include "vtr_ndmatrix.h" + +class Region; /** * @class GridTileLookup diff --git a/vpr/src/place/initial_noc_placement.cpp b/vpr/src/place/initial_noc_placement.cpp index 2c97ee4f788..40376e3a187 100644 --- a/vpr/src/place/initial_noc_placement.cpp +++ b/vpr/src/place/initial_noc_placement.cpp @@ -8,13 +8,8 @@ #include "noc_place_checkpoint.h" #include "place_constraints.h" -#include "sat_routing.h" - -#include "vtr_math.h" #include "vtr_time.h" -#include - /** * @brief Evaluates whether a NoC router swap should be accepted or not. * If delta cost is non-positive, the move is always accepted. If the cost diff --git a/vpr/src/place/move_transactions.h b/vpr/src/place/move_transactions.h index ce1095c365d..78cde262e54 100644 --- a/vpr/src/place/move_transactions.h +++ b/vpr/src/place/move_transactions.h @@ -2,7 +2,6 @@ #define VPR_MOVE_TRANSACTIONS_H #include "vpr_types.h" -#include "clustered_netlist_utils.h" class BlkLocRegistry; class GridBlock; diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index f3cc457d0bb..88dd5505777 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -7,9 +7,6 @@ #include "place_macro.h" #include "vtr_random.h" -#include "draw_debug.h" -#include "draw.h" - #include "place_constraints.h" #include "placer_state.h" #include "PlacerCriticalities.h" diff --git a/vpr/src/place/noc_place_checkpoint.h b/vpr/src/place/noc_place_checkpoint.h index e794e3e2d65..963acee281c 100644 --- a/vpr/src/place/noc_place_checkpoint.h +++ b/vpr/src/place/noc_place_checkpoint.h @@ -1,8 +1,6 @@ #ifndef VTR_ROUTERPLACEMENTCHECKPOINT_H #define VTR_ROUTERPLACEMENTCHECKPOINT_H -class NocCostHandler; - /** * @brief NoC router placement checkpoint * @@ -20,6 +18,8 @@ class NocCostHandler; #include "vpr_types.h" #include "place_util.h" +class NocCostHandler; + /** * @brief A NoC router placement checkpoint * diff --git a/vpr/src/place/place_checkpoint.h b/vpr/src/place/place_checkpoint.h index 9a3fe76d5d8..86700c9dd44 100644 --- a/vpr/src/place/place_checkpoint.h +++ b/vpr/src/place/place_checkpoint.h @@ -1,11 +1,9 @@ #ifndef PLACE_CHECKPOINT_H #define PLACE_CHECKPOINT_H -#include "vtr_util.h" #include "vpr_types.h" #include "vtr_vector_map.h" #include "place_util.h" -#include "globals.h" #include "timing_info.h" #include "place_delay_model.h" diff --git a/vpr/src/place/place_constraints.h b/vpr/src/place/place_constraints.h index 77952144795..b1d2b5a556f 100644 --- a/vpr/src/place/place_constraints.h +++ b/vpr/src/place/place_constraints.h @@ -8,9 +8,9 @@ * Created on: Mar. 1, 2021 * Author: khalid88 */ +#include "globals.h" #include "move_transactions.h" #include "region.h" -#include "clustered_netlist_utils.h" #include "partition_region.h" #include "place_macro.h" #include "grid_tile_lookup.h" diff --git a/vpr/src/place/place_util.h b/vpr/src/place/place_util.h index 6faa963106a..f21761b9e31 100644 --- a/vpr/src/place/place_util.h +++ b/vpr/src/place/place_util.h @@ -7,11 +7,7 @@ #ifndef PLACE_UTIL_H #define PLACE_UTIL_H -#include - #include "vpr_types.h" -#include "vtr_util.h" -#include "vtr_vector_map.h" #include "globals.h" /** diff --git a/vpr/src/place/placement_log_printer.h b/vpr/src/place/placement_log_printer.h index e349fbe051f..56d18835078 100644 --- a/vpr/src/place/placement_log_printer.h +++ b/vpr/src/place/placement_log_printer.h @@ -10,7 +10,6 @@ #pragma once -#include #include #include "timing_info_fwd.h" diff --git a/vpr/src/place/placer_breakpoint.cpp b/vpr/src/place/placer_breakpoint.cpp index d71430f2090..4ca967ab85d 100644 --- a/vpr/src/place/placer_breakpoint.cpp +++ b/vpr/src/place/placer_breakpoint.cpp @@ -1,4 +1,9 @@ #include "placer_breakpoint.h" +#include "breakpoint_state_globals.h" +#include "draw.h" +#include "draw_debug.h" +#include "draw_global.h" +#include "vtr_expr_eval.h" //map of the available move types and their corresponding type number std::map available_move_types = { diff --git a/vpr/src/place/placer_breakpoint.h b/vpr/src/place/placer_breakpoint.h index 159e9c40b38..d23e927ae7f 100644 --- a/vpr/src/place/placer_breakpoint.h +++ b/vpr/src/place/placer_breakpoint.h @@ -1,11 +1,7 @@ #pragma once -#include "globals.h" -#include "vpr_types.h" #include "move_utils.h" -#include "breakpoint.h" -#include "draw.h" //transforms the vector moved_blocks to a vector of ints and adds it in glob_breakpoint_state void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected); From 0588e708824920c1ad4cb47bba1769b5f2e9de26 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 19 May 2025 13:44:44 -0400 Subject: [PATCH 156/176] [lib][rr_graph] replace t_rr_type with e_rr_type --- libs/librrgraph/src/base/rr_graph_builder.cpp | 20 +++++++++---------- libs/librrgraph/src/base/rr_graph_builder.h | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 96aca5d447a..5f1852a8c77 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -75,10 +75,10 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { } } -RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side) { +RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, e_rr_type type, int ptc, e_side side) { e_side node_side = TOTAL_2D_SIDES[0]; /* Only OPIN and IPIN nodes have sides, otherwise force to use a default side */ - if (OPIN == type || IPIN == type) { + if (e_rr_type::OPIN == type || e_rr_type::IPIN == type) { node_side = side; } node_storage_.emplace_back(); @@ -88,11 +88,11 @@ RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, t_rr_type type, in node_storage_.set_node_type(new_node, type); node_storage_.set_node_coordinates(new_node, x, y, x, y); node_storage_.set_node_ptc_num(new_node, ptc); - if (OPIN == type || IPIN == type) { + if (e_rr_type::OPIN == type || e_rr_type::IPIN == type) { node_storage_.add_node_side(new_node, node_side); } /* Special for CHANX, being consistent with the rule in find_node() */ - if (CHANX == type) { + if (e_rr_type::CHANX == type) { node_lookup_.add_node(new_node, layer, y, x, type, ptc, node_side); } else { node_lookup_.add_node(new_node, layer, x, y, type, ptc, node_side); @@ -278,7 +278,7 @@ bool RRGraphBuilder::node_contain_multiple_ptc(RRNodeId node) const { void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_offset, short track_id) { VTR_ASSERT(size_t(node) < node_storage_.size()); VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); - VTR_ASSERT_MSG(node_storage_.node_type(node) == CHANX || node_storage_.node_type(node) == CHANY, "Track number valid only for CHANX/CHANY RR nodes"); + VTR_ASSERT_MSG(node_storage_.node_type(node) == e_rr_type::CHANX || node_storage_.node_type(node) == e_rr_type::CHANY, "Track number valid only for CHANX/CHANY RR nodes"); size_t node_length = std::abs(node_storage_.node_xhigh(node) - node_storage_.node_xlow(node)) + std::abs(node_storage_.node_yhigh(node) - node_storage_.node_ylow(node)); @@ -293,7 +293,7 @@ void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_o } void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { - VTR_ASSERT_MSG(node_storage_.node_type(node) == CHANX || node_storage_.node_type(node) == CHANY, "Update track node look-up is only valid to CHANX/CHANY nodes"); + VTR_ASSERT_MSG(node_storage_.node_type(node) == e_rr_type::CHANX || node_storage_.node_type(node) == e_rr_type::CHANY, "Update track node look-up is only valid to CHANX/CHANY nodes"); /* Compute the track id based on the (x, y) coordinate */ size_t x_start = std::min(node_storage_.node_xlow(node), node_storage_.node_xhigh(node)); @@ -314,12 +314,12 @@ void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { * Find the track ids using the x/y offset * FIXME: Special case on assigning CHANX (x,y) should be changed to a natural way! */ - if (CHANX == node_storage_.node_type(node)) { + if (e_rr_type::CHANX == node_storage_.node_type(node)) { ptc = node_ptc_nums_[node][x - node_storage_.node_xlow(node)]; - node_lookup_.add_node(node, node_storage_.node_layer(node), y, x, CHANX, ptc); - } else if (CHANY == node_storage_.node_type(node)) { + node_lookup_.add_node(node, node_storage_.node_layer(node), y, x, e_rr_type::CHANX, ptc); + } else if (e_rr_type::CHANY == node_storage_.node_type(node)) { ptc = node_ptc_nums_[node][y - node_storage_.node_ylow(node)]; - node_lookup_.add_node(node, node_storage_.node_layer(node), x, y, CHANY, ptc); + node_lookup_.add_node(node, node_storage_.node_layer(node), x, y, e_rr_type::CHANY, ptc); } } } diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 5ef14839340..576d28c2101 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -131,7 +131,7 @@ class RRGraphBuilder { /** @brief Create a new rr_node in the node storage and register it to the node look-up. * Return a valid node id if succeed. Otherwise, return an invalid id. */ - RRNodeId create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side = NUM_2D_SIDES); + RRNodeId create_node(int layer, int x, int y, e_rr_type type, int ptc, e_side side = NUM_2D_SIDES); /** @brief Set the node name with a given valid id */ inline void set_node_name(RRNodeId id, std::string name) { From 4e9b249715dec501d4bc4de642df51371c462939 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 19 May 2025 13:48:24 -0400 Subject: [PATCH 157/176] [vpr][tileable] remove t_rr_type usage --- vpr/src/tileable_rr_graph/rr_chan.cpp | 14 ++-- vpr/src/tileable_rr_graph/rr_chan.h | 8 +- .../rr_graph_builder_utils.cpp | 20 ++--- .../rr_graph_builder_utils.h | 8 +- vpr/src/tileable_rr_graph/rr_graph_types.h | 6 +- .../tileable_rr_graph/rr_graph_view_util.cpp | 12 +-- .../tileable_rr_graph/rr_graph_view_util.h | 6 +- vpr/src/tileable_rr_graph/rr_gsb.cpp | 82 ++++++++++--------- vpr/src/tileable_rr_graph/rr_gsb.h | 30 +++---- .../tileable_rr_graph_gsb.cpp | 76 ++++++++--------- .../tileable_rr_graph_node_builder.cpp | 70 ++++++++-------- vpr/src/util/vpr_utils.cpp | 12 +-- vpr/src/util/vpr_utils.h | 2 +- 13 files changed, 174 insertions(+), 172 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp index c6a991ea524..99bad8645ef 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.cpp +++ b/vpr/src/tileable_rr_graph/rr_chan.cpp @@ -10,7 +10,7 @@ ***********************************************************************/ /* default constructor */ RRChan::RRChan() { - type_ = NUM_RR_TYPES; + type_ = e_rr_type::NUM_RR_TYPES; nodes_.resize(0); node_segments_.resize(0); } @@ -18,7 +18,7 @@ RRChan::RRChan() { /************************************************************************ * Accessors ***********************************************************************/ -t_rr_type RRChan::get_type() const { +e_rr_type RRChan::get_type() const { return type_; } @@ -124,7 +124,7 @@ void RRChan::set(const RRChan& rr_chan) { } /* modify type */ -void RRChan::set_type(const t_rr_type& type) { +void RRChan::set_type(const e_rr_type& type) { VTR_ASSERT(valid_type(type)); type_ = type; } @@ -141,7 +141,7 @@ void RRChan::add_node(const RRGraphView& rr_graph, const RRNodeId& node, const R nodes_.push_back(node); node_segments_.push_back(node_segment); - if (NUM_RR_TYPES == type_) { + if (e_rr_type::NUM_RR_TYPES == type_) { type_ = rr_graph.node_type(node); } else { VTR_ASSERT(type_ == rr_graph.node_type(node)); @@ -160,8 +160,8 @@ void RRChan::clear() { * Internal validators ***********************************************************************/ /* for type, only valid type is CHANX and CHANY */ -bool RRChan::valid_type(const t_rr_type& type) const { - if ((CHANX == type) || (CHANY == type)) { +bool RRChan::valid_type(const e_rr_type& type) const { + if ((e_rr_type::CHANX == type) || (e_rr_type::CHANY == type)) { return true; } return false; @@ -170,7 +170,7 @@ bool RRChan::valid_type(const t_rr_type& type) const { /* Check each node, see if the node type is consistent with the type */ bool RRChan::valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const { valid_type(rr_graph.node_type(node)); - if (NUM_RR_TYPES == type_) { + if (e_rr_type::NUM_RR_TYPES == type_) { return true; } valid_type(type_); diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h index 5ba9bc09af5..727c50e5c1b 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.h +++ b/vpr/src/tileable_rr_graph/rr_chan.h @@ -40,7 +40,7 @@ class RRChan { RRChan(); public: /* Accessors */ - t_rr_type get_type() const; + e_rr_type get_type() const; size_t get_chan_width() const; /* get the number of tracks in this channel */ int get_node_track_id(const RRNodeId& node) const; /* get the track_id of a node */ RRNodeId get_node(const size_t& track_num) const; /* get the rr_node with the track_id */ @@ -53,7 +53,7 @@ class RRChan { void set(const RRChan&); /* modify the type of routing channel */ - void set_type(const t_rr_type& type); + void set_type(const e_rr_type& type); /* reseve a number of nodes to the array */ void reserve_node(const size_t& node_size); @@ -66,7 +66,7 @@ class RRChan { private: /* internal functions */ /* For the type of a routing channel, only valid type is CHANX and CHANY */ - bool valid_type(const t_rr_type& type) const; + bool valid_type(const e_rr_type& type) const; /* Check each node, see if the node type is consistent with the type of routing channel */ bool valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const; @@ -75,7 +75,7 @@ class RRChan { bool valid_node_id(const size_t& node_id) const; private: /* Internal Data */ - t_rr_type type_; /* channel type: CHANX or CHANY */ + e_rr_type type_; /* channel type: CHANX or CHANY */ std::vector nodes_; /* rr nodes of each track in the channel */ std::vector node_segments_; /* segment of each track */ }; diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 9bd38254b69..c0f8e7d083c 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -509,8 +509,8 @@ short get_track_rr_node_end_track_id(const RRGraph& rr_graph, const RRNodeId& track_rr_node, const vtr::vector>& tileable_rr_graph_node_track_ids) { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) - || (CHANY == rr_graph.node_type(track_rr_node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(track_rr_node)) + || (e_rr_type::CHANY == rr_graph.node_type(track_rr_node))); if (Direction::INC == rr_graph.node_direction(track_rr_node)) { return tileable_rr_graph_node_track_ids[track_rr_node].back(); @@ -525,7 +525,7 @@ short get_track_rr_node_end_track_id(const RRGraph& rr_graph, * in a routing resource graph ************************************************************************/ short find_rr_graph_num_nodes(const RRGraph& rr_graph, - const std::vector& node_types) { + const std::vector& node_types) { short counter = 0; for (const RRNodeId& node : rr_graph.nodes()) { @@ -544,7 +544,7 @@ short find_rr_graph_num_nodes(const RRGraph& rr_graph, * in a routing resource graph ************************************************************************/ short find_rr_graph_max_fan_in(const RRGraph& rr_graph, - const std::vector& node_types) { + const std::vector& node_types) { short max_fan_in = 0; for (const RRNodeId& node : rr_graph.nodes()) { @@ -563,7 +563,7 @@ short find_rr_graph_max_fan_in(const RRGraph& rr_graph, * in a routing resource graph ************************************************************************/ short find_rr_graph_min_fan_in(const RRGraph& rr_graph, - const std::vector& node_types) { + const std::vector& node_types) { short min_fan_in = 0; for (const RRNodeId& node : rr_graph.nodes()) { @@ -582,7 +582,7 @@ short find_rr_graph_min_fan_in(const RRGraph& rr_graph, * in a routing resource graph ************************************************************************/ short find_rr_graph_average_fan_in(const RRGraph& rr_graph, - const std::vector& node_types) { + const std::vector& node_types) { /* Get the maximum SB mux size */ size_t sum = 0; size_t counter = 0; @@ -605,9 +605,9 @@ short find_rr_graph_average_fan_in(const RRGraph& rr_graph, ************************************************************************/ void print_rr_graph_mux_stats(const RRGraph& rr_graph) { /* Print MUX size distribution */ - std::vector sb_node_types; - sb_node_types.push_back(CHANX); - sb_node_types.push_back(CHANY); + std::vector sb_node_types; + sb_node_types.push_back(e_rr_type::CHANX); + sb_node_types.push_back(e_rr_type::CHANY); /* Print statistics */ VTR_LOG("------------------------------------------------\n"); @@ -622,7 +622,7 @@ void print_rr_graph_mux_stats(const RRGraph& rr_graph) { VTR_LOG("------------------------------------------------\n"); /* Get the maximum CB mux size */ - std::vector cb_node_types(1, IPIN); + std::vector cb_node_types(1, e_rr_type::IPIN); VTR_LOG("------------------------------------------------\n"); VTR_LOG("Total No. of Connection Block Multiplexer size: %d\n", diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index e1869ed4d4a..2b096e4842b 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -105,16 +105,16 @@ short get_track_rr_node_end_track_id(const RRGraph& rr_graph, const vtr::vector>& tileable_rr_graph_node_track_ids); short find_rr_graph_num_nodes(const RRGraph& rr_graph, - const std::vector& node_types); + const std::vector& node_types); short find_rr_graph_max_fan_in(const RRGraph& rr_graph, - const std::vector& node_types); + const std::vector& node_types); short find_rr_graph_min_fan_in(const RRGraph& rr_graph, - const std::vector& node_types); + const std::vector& node_types); short find_rr_graph_average_fan_in(const RRGraph& rr_graph, - const std::vector& node_types); + const std::vector& node_types); void print_rr_graph_mux_stats(const RRGraph& rr_graph); diff --git a/vpr/src/tileable_rr_graph/rr_graph_types.h b/vpr/src/tileable_rr_graph/rr_graph_types.h index ca97d7d38a9..813752d62ed 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_types.h +++ b/vpr/src/tileable_rr_graph/rr_graph_types.h @@ -28,7 +28,7 @@ constexpr std::array DIRECTION_STRING_WRITE_XML = { * -- i.e., the gate that generates a signal. * * SINK: A dummy node that is a logical input within a block * * -- i.e. the gate that needs a signal. */ -typedef enum e_rr_type : unsigned char { +typedef enum class e_rr_type : unsigned char { SOURCE = 0, SINK, IPIN, @@ -36,10 +36,10 @@ typedef enum e_rr_type : unsigned char { CHANX, CHANY, NUM_RR_TYPES -} t_rr_type; +}; #endif -// constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; +// constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; // constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; #endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 7816e46134c..cbc29f4850e 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -38,11 +38,11 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type, + const e_rr_type& rr_type, const int& ptc) { std::vector indices; - if (rr_type == IPIN || rr_type == OPIN) { + if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { //For pins we need to look at all the sides of the current grid tile for (e_side side : TOTAL_2D_SIDES) { @@ -71,10 +71,10 @@ std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type) { + const e_rr_type& rr_type) { std::vector indices; - VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); + VTR_ASSERT(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); for (const RRNodeId& rr_node_index : rr_graph.node_lookup().find_channel_nodes(layer, x, y, rr_type)) { if (rr_node_index != RRNodeId::INVALID()) { @@ -93,12 +93,12 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type, + const e_rr_type& rr_type, const e_side& side, bool include_clock) { std::vector indices; - VTR_ASSERT(rr_type == IPIN || rr_type == OPIN); + VTR_ASSERT(rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN); /* Ensure that (x, y) is a valid location in grids */ if (size_t(x) > device_grid.width() - 1 || size_t(y) > device_grid.height() - 1) { diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.h b/vpr/src/tileable_rr_graph/rr_graph_view_util.h index 4ccb1c614e1..e14fc645910 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.h +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.h @@ -17,21 +17,21 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type, + const e_rr_type& rr_type, const int& ptc); std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type); + const e_rr_type& rr_type); std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const DeviceGrid& device_grid, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type, + const e_rr_type& rr_type, const e_side& side, bool include_clock = false); diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 58c721a06b1..5e5d98c99c2 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -53,7 +53,7 @@ size_t RRGSB::get_chan_width(const e_side& side) const { } /* Get the number of routing tracks on a side */ -t_rr_type RRGSB::get_chan_type(const e_side& side) const { +e_rr_type RRGSB::get_chan_type(const e_side& side) const { SideManager side_manager(side); VTR_ASSERT(side_manager.validate()); return chan_node_[side_manager.to_size_t()].get_type(); @@ -74,12 +74,12 @@ const RRChan& RRGSB::chan(const e_side& chan_side) const { } /* Get the number of routing tracks of a X/Y-direction CB */ -size_t RRGSB::get_cb_chan_width(const t_rr_type& cb_type) const { +size_t RRGSB::get_cb_chan_width(const e_rr_type& cb_type) const { return get_chan_width(get_cb_chan_side(cb_type)); } /* Get the sides of ipin_nodes belong to the cb */ -std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) const { +std::vector RRGSB::get_cb_ipin_sides(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); std::vector ipin_sides; @@ -88,11 +88,11 @@ std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) cons ipin_sides.clear(); switch (cb_type) { - case CHANX: + case e_rr_type::CHANX: ipin_sides.push_back(TOP); ipin_sides.push_back(BOTTOM); break; - case CHANY: + case e_rr_type::CHANY: ipin_sides.push_back(RIGHT); ipin_sides.push_back(LEFT); break; @@ -105,7 +105,7 @@ std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) cons } /* Get the sides of ipin_nodes belong to the cb */ -std::vector RRGSB::get_cb_opin_sides(const t_rr_type& cb_type) const { +std::vector RRGSB::get_cb_opin_sides(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); std::vector opin_sides; @@ -114,8 +114,8 @@ std::vector RRGSB::get_cb_opin_sides(const t_rr_type& cb_type) cons opin_sides.clear(); switch (cb_type) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: opin_sides.push_back(TOP); opin_sides.push_back(RIGHT); opin_sides.push_back(BOTTOM); @@ -290,7 +290,7 @@ RRNodeId RRGSB::get_opin_node(const e_side& side, const size_t& node_id) const { } /* Get the number of OPIN rr_nodes on a side */ -size_t RRGSB::get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side) const { +size_t RRGSB::get_num_cb_opin_nodes(const e_rr_type& cb_type, const e_side& side) const { SideManager side_manager(side); VTR_ASSERT(side_manager.validate()); size_t icb_type = get_cb_opin_type_id(cb_type); @@ -298,7 +298,7 @@ size_t RRGSB::get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side } /* get a opin_node at a given side and track_id */ -RRNodeId RRGSB::get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const { +RRNodeId RRGSB::get_cb_opin_node(const e_rr_type& cb_type, const e_side& side, const size_t& node_id) const { SideManager side_manager(side); VTR_ASSERT(side_manager.validate()); @@ -325,7 +325,7 @@ RRNodeId RRGSB::get_medium_node(const size_t& ptc) const { } /* Get the node index of a routing track of a connection block, return -1 if not found */ -int RRGSB::get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const { +int RRGSB::get_cb_chan_node_index(const e_rr_type& cb_type, const RRNodeId& node) const { enum e_side chan_side = get_cb_chan_side(cb_type); return get_chan_node_index(chan_side, node); } @@ -349,8 +349,8 @@ int RRGSB::get_node_index(const RRGraphView& rr_graph, /* Depending on the type of rr_node, we search different arrays */ switch (rr_graph.node_type(node)) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) { if ((node == chan_node_[size_t(node_side)].get_node(inode)) /* Check if direction meets specification */ @@ -361,7 +361,7 @@ int RRGSB::get_node_index(const RRGraphView& rr_graph, } } break; - case IPIN: + case e_rr_type::IPIN: for (size_t inode = 0; inode < get_num_ipin_nodes(node_side); ++inode) { if (node == ipin_node_[size_t(node_side)][inode]) { cnt++; @@ -370,7 +370,7 @@ int RRGSB::get_node_index(const RRGraphView& rr_graph, } } break; - case OPIN: + case e_rr_type::OPIN: for (size_t inode = 0; inode < get_num_opin_nodes(node_side); ++inode) { if (node == opin_node_[size_t(node_side)][inode]) { cnt++; @@ -433,7 +433,7 @@ bool RRGSB::is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, SideManager side_manager(node_side); int index; - VTR_ASSERT((CHANX == rr_graph.node_type(node)) || (CHANY == rr_graph.node_type(node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(node)) || (e_rr_type::CHANY == rr_graph.node_type(node))); /* See if we can find the same src_rr_node in the opposite chan_side * if there is one, it means a shorted wire across the SB @@ -490,7 +490,7 @@ bool RRGSB::is_chan_node(const RRNodeId& node) const { } /* check if the CB exist in this GSB */ -bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const { +bool RRGSB::is_cb_exist(const e_rr_type& cb_type) const { /* if channel width is zero, there is no CB */ return (0 != get_cb_chan_width(cb_type)); } @@ -656,22 +656,22 @@ vtr::Point RRGSB::get_sb_coordinate() const { } /* get the x coordinate of this X/Y-direction block */ -size_t RRGSB::get_cb_x(const t_rr_type& cb_type) const { +size_t RRGSB::get_cb_x(const e_rr_type& cb_type) const { return get_cb_coordinate(cb_type).x(); } /* get the y coordinate of this X/Y-direction block */ -size_t RRGSB::get_cb_y(const t_rr_type& cb_type) const { +size_t RRGSB::get_cb_y(const e_rr_type& cb_type) const { return get_cb_coordinate(cb_type).y(); } /* Get the coordinate of the X/Y-direction CB */ -vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { +vtr::Point RRGSB::get_cb_coordinate(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); switch (cb_type) { - case CHANX: + case e_rr_type::CHANX: return coordinate_; - case CHANY: + case e_rr_type::CHANY: return coordinate_; default: VTR_LOG("Invalid type of connection block!\n"); @@ -679,12 +679,12 @@ vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { } } -e_side RRGSB::get_cb_chan_side(const t_rr_type& cb_type) const { +e_side RRGSB::get_cb_chan_side(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); switch (cb_type) { - case CHANX: + case e_rr_type::CHANX: return LEFT; - case CHANY: + case e_rr_type::CHANY: return BOTTOM; default: VTR_LOG("Invalid type of connection block!\n"); @@ -884,11 +884,11 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, VTR_ASSERT(NUM_2D_SIDES != side); VTR_ASSERT(OPEN != index); - if (OPIN == rr_graph.node_type(src_node)) { + if (e_rr_type::OPIN == rr_graph.node_type(src_node)) { from_grid_edge_map[side][index] = edge; } else { - VTR_ASSERT((CHANX == rr_graph.node_type(src_node)) - || (CHANY == rr_graph.node_type(src_node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(src_node)) + || (e_rr_type::CHANY == rr_graph.node_type(src_node))); from_track_edge_map[side][index] = edge; } @@ -964,7 +964,8 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ - if (CHANX != rr_graph.node_type(src_node) && CHANY != rr_graph.node_type(src_node)) { + if ((e_rr_type::CHANX != rr_graph.node_type(src_node)) + && (e_rr_type::CHANY != rr_graph.node_type(src_node))) { continue; } /* The driver routing channel node can be either an input or an output to the GSB. @@ -998,7 +999,8 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, VTR_ASSERT(OPEN != index); - VTR_ASSERT(CHANX == rr_graph.node_type(src_node) || CHANY == rr_graph.node_type(src_node)); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(src_node)) + || (e_rr_type::CHANY == rr_graph.node_type(src_node))); from_track_edge_map[index] = edge; edge_counter++; } @@ -1007,7 +1009,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ - if (OPIN != rr_graph.node_type(src_node)) { + if (e_rr_type::OPIN != rr_graph.node_type(src_node)) { continue; } enum e_side cb_opin_side = NUM_2D_SIDES; @@ -1061,7 +1063,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ ipin_node_in_edges_.resize(get_num_sides()); - for (t_rr_type cb_type : {CHANX, CHANY}) { + for (e_rr_type cb_type : {e_rr_type::CHANX, e_rr_type::CHANY}) { for (e_side ipin_side : get_cb_ipin_sides(cb_type)) { SideManager side_manager(ipin_side); ipin_node_in_edges_[size_t(ipin_side)].resize(ipin_node_[size_t(ipin_side)].size()); @@ -1073,8 +1075,8 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { } void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { - for (t_rr_type cb_type : {CHANX, CHANY}) { - size_t icb_type = cb_type == CHANX ? 0 : 1; + for (e_rr_type cb_type : {e_rr_type::CHANX, e_rr_type::CHANY}) { + size_t icb_type = cb_type == e_rr_type::CHANX ? 0 : 1; std::vector cb_ipin_sides = get_cb_ipin_sides(cb_type); for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { enum e_side cb_ipin_side = cb_ipin_sides[iside]; @@ -1084,7 +1086,7 @@ void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); for (const RREdgeId curr_edge : driver_rr_edges) { RRNodeId cand_node = rr_graph.edge_src_node(curr_edge); - if (OPIN != rr_graph.node_type(cand_node)) { + if (e_rr_type::OPIN != rr_graph.node_type(cand_node)) { continue; } enum e_side cb_opin_side = NUM_2D_SIDES; @@ -1224,7 +1226,7 @@ bool RRGSB::validate_opin_node_id(const e_side& side, const size_t& node_id) con } /* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */ -bool RRGSB::validate_cb_opin_node_id(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const { +bool RRGSB::validate_cb_opin_node_id(const e_rr_type& cb_type, const e_side& side, const size_t& node_id) const { if (false == validate_side(side)) { return false; } @@ -1240,11 +1242,11 @@ bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) con return (node_id < ipin_node_[size_t(side)].size()); } -bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const { - return ((CHANX == cb_type) || (CHANY == cb_type)); +bool RRGSB::validate_cb_type(const e_rr_type& cb_type) const { + return ((e_rr_type::CHANX == cb_type) || (e_rr_type::CHANY == cb_type)); } -size_t RRGSB::get_cb_opin_type_id(const t_rr_type& cb_type) const { +size_t RRGSB::get_cb_opin_type_id(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); - return cb_type == CHANX ? 0 : 1; + return cb_type == e_rr_type::CHANX ? 0 : 1; } diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 30d8e80372b..c9e49f90609 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -59,21 +59,21 @@ class RRGSB { size_t get_chan_width(const e_side& side) const; /* Get the type of routing tracks on a side */ - t_rr_type get_chan_type(const e_side& side) const; + e_rr_type get_chan_type(const e_side& side) const; /* Get the maximum number of routing tracks on all sides */ size_t get_max_chan_width() const; /* Get the number of routing tracks of a X/Y-direction CB */ - size_t get_cb_chan_width(const t_rr_type& cb_type) const; + size_t get_cb_chan_width(const e_rr_type& cb_type) const; /* Return read-only object of the routing channels with a given side */ const RRChan& chan(const e_side& chan_side) const; /* Get the sides of CB ipins in the array */ - std::vector get_cb_ipin_sides(const t_rr_type& cb_type) const; + std::vector get_cb_ipin_sides(const e_rr_type& cb_type) const; /* Get the sides of CB opins in the array, OPINs can only be at the same sides of IPINs. Differently, they are inputs to a connection block */ - std::vector get_cb_opin_sides(const t_rr_type& cb_type) const; + std::vector get_cb_opin_sides(const e_rr_type& cb_type) const; /* Get the direction of a rr_node at a given side and track_id */ enum PORTS get_chan_node_direction(const e_side& side, const size_t& track_id) const; @@ -110,12 +110,12 @@ class RRGSB { /* Get the number of OPIN rr_nodes on a side */ size_t get_num_opin_nodes(const e_side& side) const; /* Get the number of OPIN rr_nodes on a side of a connection block */ - size_t get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side) const; + size_t get_num_cb_opin_nodes(const e_rr_type& cb_type, const e_side& side) const; /* get a rr_node at a given side and track_id */ RRNodeId get_opin_node(const e_side& side, const size_t& node_id) const; /* get a rr_node at a given side and track_id for a connection block */ - RRNodeId get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; + RRNodeId get_cb_opin_node(const e_rr_type& cb_type, const e_side& side, const size_t& node_id) const; /* Get the number of MEDIUM rr_nodes */ size_t get_num_medium_nodes() const; @@ -123,7 +123,7 @@ class RRGSB { /* get a rr_node at a given ptc number */ RRNodeId get_medium_node(const size_t& ptc) const; - int get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const; + int get_cb_chan_node_index(const e_rr_type& cb_type, const RRNodeId& node) const; int get_chan_node_index(const e_side& node_side, const RRNodeId& node) const; @@ -143,7 +143,7 @@ class RRGSB { public: /* Accessors: to identify mirrors */ /* check if the connect block exists in the GSB */ - bool is_cb_exist(const t_rr_type& cb_type) const; + bool is_cb_exist(const e_rr_type& cb_type) const; /* check if the switch block exists in the GSB, this function checks if a switch block physically exists (no routing wires, no OPIN nodes, and no interconnecting wires) */ bool is_sb_exist(const RRGraphView& rr_graph) const; @@ -162,10 +162,10 @@ class RRGSB { size_t get_sb_x() const; /* get the x coordinate of this switch block */ size_t get_sb_y() const; /* get the y coordinate of this switch block */ vtr::Point get_sb_coordinate() const; /* Get the coordinate of the SB */ - size_t get_cb_x(const t_rr_type& cb_type) const; /* get the x coordinate of this X/Y-direction block */ - size_t get_cb_y(const t_rr_type& cb_type) const; /* get the y coordinate of this X/Y-direction block */ - vtr::Point get_cb_coordinate(const t_rr_type& cb_type) const; /* Get the coordinate of the X/Y-direction CB */ - e_side get_cb_chan_side(const t_rr_type& cb_type) const; /* get the side of a Connection block */ + size_t get_cb_x(const e_rr_type& cb_type) const; /* get the x coordinate of this X/Y-direction block */ + size_t get_cb_y(const e_rr_type& cb_type) const; /* get the y coordinate of this X/Y-direction block */ + vtr::Point get_cb_coordinate(const e_rr_type& cb_type) const; /* Get the coordinate of the X/Y-direction CB */ + e_side get_cb_chan_side(const e_rr_type& cb_type) const; /* get the side of a Connection block */ e_side get_cb_chan_side(const e_side& ipin_side) const; /* get the side of a Connection block */ vtr::Point get_side_block_coordinate(const e_side& side) const; vtr::Point get_grid_coordinate() const; @@ -240,11 +240,11 @@ class RRGSB { bool validate_num_sides() const; bool validate_side(const e_side& side) const; bool validate_track_id(const e_side& side, const size_t& track_id) const; - bool validate_cb_opin_node_id(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; + bool validate_cb_opin_node_id(const e_rr_type& cb_type, const e_side& side, const size_t& node_id) const; bool validate_opin_node_id(const e_side& side, const size_t& node_id) const; bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const; - bool validate_cb_type(const t_rr_type& cb_type) const; - size_t get_cb_opin_type_id(const t_rr_type& cb_type) const; + bool validate_cb_type(const e_rr_type& cb_type) const; + size_t get_cb_opin_type_id(const e_rr_type& cb_type) const; private: /* Internal Data */ /* Coordinator */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index c76320b29c3..410eb3ec0e0 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -578,10 +578,10 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, - CHANY); + e_rr_type::CHANY); for (auto inode : rr_nodes) { - VTR_ASSERT(rr_graph.node_type(inode) == CHANY); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANY); Direction direction = rr_graph.node_direction(inode); size_t xlow = rr_graph.node_xlow(inode); size_t ylow = rr_graph.node_ylow(inode); @@ -614,10 +614,10 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), - CHANX); + e_rr_type::CHANX); for (auto inode : rr_nodes) { - VTR_ASSERT(rr_graph.node_type(inode) == CHANX); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANX); Direction direction = rr_graph.node_direction(inode); size_t xlow = rr_graph.node_xlow(inode); size_t ylow = rr_graph.node_ylow(inode); @@ -649,10 +649,10 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y(), - CHANY); + e_rr_type::CHANY); for (auto inode : rr_nodes) { - VTR_ASSERT(rr_graph.node_type(inode) == CHANY); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANY); Direction direction = rr_graph.node_direction(inode); size_t xhigh = rr_graph.node_xhigh(inode); size_t yhigh = rr_graph.node_yhigh(inode); @@ -684,10 +684,10 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y(), - CHANX); + e_rr_type::CHANX); for (auto inode : rr_nodes) { - VTR_ASSERT(rr_graph.node_type(inode) == CHANX); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANX); Direction direction = rr_graph.node_direction(inode); size_t xhigh = rr_graph.node_xhigh(inode); size_t yhigh = rr_graph.node_yhigh(inode); @@ -770,7 +770,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, /* Build a RRChan Object with the given channel type and coorindators */ static RRChan build_one_tileable_rr_chan(const size_t& layer, const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, + const e_rr_type& chan_type, const RRGraphView& rr_graph, const ChanNodeDetails& chan_details) { std::vector chan_rr_nodes; @@ -900,7 +900,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Routing channels*/ /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANY, rr_graph, chany_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, e_rr_type::CHANY, rr_graph, chany_details); chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ @@ -914,11 +914,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Include Grid[x][y+1] RIGHT side outputs pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, - OPIN, opin_grid_side[0]); + e_rr_type::OPIN, opin_grid_side[0]); /* Include Grid[x+1][y+1] Left side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, - OPIN, opin_grid_side[1]); + e_rr_type::OPIN, opin_grid_side[1]); break; case RIGHT: /* RIGHT = 1 */ @@ -931,7 +931,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANX, rr_graph, chanx_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, e_rr_type::CHANX, rr_graph, chanx_details); chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ @@ -945,11 +945,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* include Grid[x+1][y+1] Bottom side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, - OPIN, opin_grid_side[0]); + e_rr_type::OPIN, opin_grid_side[0]); /* include Grid[x+1][y] Top side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), - OPIN, opin_grid_side[1]); + e_rr_type::OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ if (!perimeter_cb && gsb_coordinate.y() == 0) { @@ -960,7 +960,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANY, rr_graph, chany_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, e_rr_type::CHANY, rr_graph, chany_details); chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ @@ -974,11 +974,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* include Grid[x+1][y] Left side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), - OPIN, opin_grid_side[0]); + e_rr_type::OPIN, opin_grid_side[0]); /* include Grid[x][y] Right side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x(), gsb_coordinate.y(), - OPIN, opin_grid_side[1]); + e_rr_type::OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ if (!perimeter_cb && gsb_coordinate.x() == 0) { @@ -989,7 +989,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for left: chanx[x][y] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANX, rr_graph, chanx_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, e_rr_type::CHANX, rr_graph, chanx_details); chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ @@ -1002,11 +1002,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* include Grid[x][y+1] Bottom side outputs pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, - OPIN, opin_grid_side[0]); + e_rr_type::OPIN, opin_grid_side[0]); /* include Grid[x][y] Top side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x(), gsb_coordinate.y(), - OPIN, opin_grid_side[1]); + e_rr_type::OPIN, opin_grid_side[1]); break; default: @@ -1135,7 +1135,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, } /* Collect IPIN rr_nodes*/ temp_ipin_rr_nodes = find_rr_graph_grid_nodes(rr_graph, grids, - layer, ix, iy, IPIN, ipin_rr_node_grid_side); + layer, ix, iy, e_rr_type::IPIN, ipin_rr_node_grid_side); /* Fill the ipin nodes of RRGSB */ for (const RRNodeId& inode : temp_ipin_rr_nodes) { rr_gsb.add_ipin_node(inode, side_manager.get_side()); @@ -1145,27 +1145,27 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, } /* Find all MEDIUM rr_nodes */ - std::vector medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y(), MEDIUM); + std::vector medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y(), e_rr_type::MEDIUM); for (auto medium_rr_node : medium_rr_nodes) { rr_gsb.add_medium_node(medium_rr_node); } /* For TOP and RIGHT borders, we need to add extra medium nodes. */ if (gsb_coordinate.y() == grids.height() - 2) { - std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, MEDIUM); + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, e_rr_type::MEDIUM); for (auto medium_rr_node : extra_medium_rr_nodes) { rr_gsb.add_medium_node(medium_rr_node); } } if (gsb_coordinate.x() == grids.width() - 2) { - std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), MEDIUM); + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), e_rr_type::MEDIUM); for (auto medium_rr_node : extra_medium_rr_nodes) { rr_gsb.add_medium_node(medium_rr_node); } } if ((gsb_coordinate.x() == grids.width() - 2) && (gsb_coordinate.y() == grids.height() - 2)) { - std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, MEDIUM); + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, e_rr_type::MEDIUM); for (auto medium_rr_node : extra_medium_rr_nodes) { rr_gsb.add_medium_node(medium_rr_node); } @@ -1211,8 +1211,8 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, /* For TRACKs to IPINs, we only care LEFT and TOP sides * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs */ - if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) - || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY))) { + if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(e_rr_type::CHANX)) + || (side_manager.get_side() == rr_gsb.get_cb_chan_side(e_rr_type::CHANY))) { /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); @@ -1272,8 +1272,8 @@ void build_edges_for_one_tileable_rr_gsb_vib(RRGraphBuilder& rr_graph_builder, /* For TRACKs to IPINs, we only care LEFT and TOP sides * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs */ - if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) - || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY))) { + if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(e_rr_type::CHANX)) + || (side_manager.get_side() == rr_gsb.get_cb_chan_side(e_rr_type::CHANY))) { /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); @@ -1771,11 +1771,11 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, RRNodeId opin_node_id = rr_graph.node_lookup().find_node(layer, from_grid_coordinate.x() - from_grid_width_ofs, from_grid_coordinate.y() - from_grid_height_ofs, - OPIN, opin, opin_grid_side[0]); + e_rr_type::OPIN, opin, opin_grid_side[0]); RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(layer, to_grid_coordinate.x() - to_grid_width_ofs, to_grid_coordinate.y() - to_grid_height_ofs, - IPIN, ipin, ipin_grid_side[0]); + e_rr_type::IPIN, ipin, ipin_grid_side[0]); /* add edges to the opin_node */ VTR_ASSERT(opin_node_id && ipin_node_id); @@ -1806,7 +1806,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, const std::vector first_stages = vib->get_first_stages(); for (size_t i_first_stage = 0; i_first_stage < first_stages.size(); i_first_stage++) { std::vector froms = first_stages[i_first_stage].froms; - RRNodeId to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, i_first_stage); + RRNodeId to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::MEDIUM, i_first_stage); VTR_ASSERT(to_node.is_valid()); VTR_ASSERT(rr_gsb.is_medium_node(to_node)); for (auto from : froms) { @@ -1820,7 +1820,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } for (e_side side : TOTAL_2D_SIDES) { - from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::OPIN, from.phy_pin_index, side); if (from_node.is_valid()) break; } @@ -1885,7 +1885,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } else if (from.from_type == MUX) { size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); - from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::MEDIUM, from_mux_index); if (!rr_gsb.is_medium_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); @@ -1928,7 +1928,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } for (e_side side : TOTAL_2D_SIDES) { - to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), IPIN, to.phy_pin_index, side); + to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::IPIN, to.phy_pin_index, side); if (to_node.is_valid()) break; } @@ -2015,7 +2015,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } for (e_side side : TOTAL_2D_SIDES) { - from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::OPIN, from.phy_pin_index, side); if (from_node.is_valid()) break; } @@ -2080,7 +2080,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } else if (from.from_type == MUX) { size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); - from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::MEDIUM, from_mux_index); if (!rr_gsb.is_medium_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 5b48ec0f2e6..107a987f87d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -27,7 +27,7 @@ ***********************************************************************/ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, const size_t& layer, - const t_rr_type& node_type, + const e_rr_type& node_type, const bool& perimeter_cb) { size_t num_grid_rr_nodes = 0; @@ -55,19 +55,19 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, } switch (node_type) { - case OPIN: + case e_rr_type::OPIN: /* get the number of OPINs */ num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, DRIVER, io_side); break; - case IPIN: + case e_rr_type::IPIN: /* get the number of IPINs */ num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, RECEIVER, io_side); break; - case SOURCE: + case e_rr_type::SOURCE: /* SOURCE: number of classes whose type is DRIVER */ num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, DRIVER); break; - case SINK: + case e_rr_type::SINK: /* SINK: number of classes whose type is RECEIVER */ num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, RECEIVER); break; @@ -363,7 +363,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, /************************************************************************ * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ -static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, +static vtr::vector estimate_num_rr_nodes(const DeviceGrid& grids, const VibDeviceGrid& vib_grid, const size_t& layer, const vtr::Point& chan_width, @@ -375,20 +375,20 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, const bool& through_channel) { /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ - std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); + vtr::vector num_rr_nodes_per_type(static_cast(e_rr_type::NUM_RR_TYPES), 0); /** * 1 Find number of rr nodes related to grids */ if (!vib_grid.is_empty()) - num_rr_nodes_per_type[MEDIUM] = estimate_num_medium_rr_nodes(grids, vib_grid, layer); + num_rr_nodes_per_type[e_rr_type::MEDIUM] = estimate_num_medium_rr_nodes(grids, vib_grid, layer); else - num_rr_nodes_per_type[MEDIUM] = 0; + num_rr_nodes_per_type[e_rr_type::MEDIUM] = 0; - num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, OPIN, perimeter_cb); - num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, IPIN, perimeter_cb); - num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE, perimeter_cb); - num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK, perimeter_cb); + num_rr_nodes_per_type[e_rr_type::OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, e_rr_type::OPIN, perimeter_cb); + num_rr_nodes_per_type[e_rr_type::IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, e_rr_type::IPIN, perimeter_cb); + num_rr_nodes_per_type[e_rr_type::SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, e_rr_type::SOURCE, perimeter_cb); + num_rr_nodes_per_type[e_rr_type::SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, e_rr_type::SINK, perimeter_cb); /** * 2. Assign the segments for each routing channel, @@ -405,14 +405,14 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, * in X-direction and Y-direction channels!!! * So we will load segment details for different channels */ - num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, layer, + num_rr_nodes_per_type[e_rr_type::CHANX] = estimate_num_chanx_rr_nodes(grids, layer, chan_width.x(), segment_inf_x, device_grid_annotation, shrink_boundary, perimeter_cb, through_channel); - num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, layer, + num_rr_nodes_per_type[e_rr_type::CHANY] = estimate_num_chany_rr_nodes(grids, layer, chan_width.y(), segment_inf_y, device_grid_annotation, @@ -444,7 +444,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const bool& through_channel) { VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); - std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, + vtr::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, vib_grid, layer, chan_width, @@ -496,7 +496,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder width, height); for (const int& pin_num : opin_list) { /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, OPIN, pin_num, side); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, e_rr_type::OPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -553,7 +553,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder std::vector ipin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), RECEIVER, side_manager.get_side(), width, height); for (const int& pin_num : ipin_list) { /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, IPIN, pin_num, side); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, e_rr_type::IPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -605,7 +605,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build } /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), e_rr_type::SOURCE, iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -654,7 +654,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder } /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), e_rr_type::SINK, iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -692,7 +692,7 @@ static void load_one_grid_medium_nodes_basic_info(RRGraphBuilder& rr_graph_build size_t num_medium_nodes = vib->get_first_stages().size(); for (size_t i_medium = 0; i_medium < num_medium_nodes; i_medium++) { /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), MEDIUM, i_medium, TOTAL_2D_SIDES[0]); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), e_rr_type::MEDIUM, i_medium, TOTAL_2D_SIDES[0]); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), grid_coordinate.y(), @@ -755,8 +755,8 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, int x_tile = ix + width_offset; for (int height_offset = 0; height_offset < grids.get_physical_type(tile_loc)->height; ++height_offset) { int y_tile = iy + height_offset; - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, OPIN, grids.get_physical_type(tile_loc)->num_pins, side); - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, IPIN, grids.get_physical_type(tile_loc)->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::OPIN, grids.get_physical_type(tile_loc)->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::IPIN, grids.get_physical_type(tile_loc)->num_pins, side); } } } @@ -807,7 +807,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(vib_grid.vib_pbtype_name(layer, ix, iy) == grids.get_physical_type(tile_loc)->name); vtr::Point grid_coordinate(ix, iy); - rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, MEDIUM, vib_grid.num_medium_nodes(layer, ix, iy), TOTAL_2D_SIDES[0]); + rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, e_rr_type::MEDIUM, vib_grid.num_medium_nodes(layer, ix, iy), TOTAL_2D_SIDES[0]); load_one_grid_medium_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, @@ -832,12 +832,12 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_graph_builder.node_lookup().mirror_nodes(0, vtr::Point(root_x, root_y), vtr::Point(x, y), - SOURCE, + e_rr_type::SOURCE, TOTAL_2D_SIDES[0]); rr_graph_builder.node_lookup().mirror_nodes(0, vtr::Point(root_x, root_y), vtr::Point(x, y), - SINK, + e_rr_type::SINK, TOTAL_2D_SIDES[0]); } } @@ -856,7 +856,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, std::vector& rr_rc_data, const size_t& layer, const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, + const e_rr_type& chan_type, ChanNodeDetails& chan_details, const std::vector& segment_infs, const t_unified_to_parallel_seg_index& seg_index_map, @@ -885,7 +885,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, /* assign switch id */ size_t seg_id = chan_details.get_track_segment_id(itrack); - e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + e_parallel_axis wanted_axis = chan_type == e_rr_type::CHANX ? X_AXIS : Y_AXIS; size_t parallel_seg_id = find_parallel_seg_index(seg_id, seg_index_map, wanted_axis); rr_node_driver_switches[node] = RRSwitchId(segment_infs[parallel_seg_id].arch_opin_switch); @@ -932,7 +932,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, } /* Finish node RC attributes */ size_t seg_id = chan_details.get_track_segment_id(itrack); - e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + e_parallel_axis wanted_axis = chan_type == e_rr_type::CHANX ? X_AXIS : Y_AXIS; size_t parallel_seg_id = find_parallel_seg_index(seg_id, seg_index_map, wanted_axis); float node_R = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Rmetal; float node_C = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Cmetal; @@ -1107,7 +1107,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_node_driver_switches, rr_node_track_ids, rr_rc_data, - layer, chanx_coord, CHANX, + layer, chanx_coord, e_rr_type::CHANX, chanx_details, segment_infs, segment_index_map, @@ -1248,7 +1248,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_node_driver_switches, rr_node_track_ids, rr_rc_data, - layer, chany_coord, CHANY, + layer, chany_coord, e_rr_type::CHANY, chany_details, segment_infs, seg_index_map, @@ -1271,7 +1271,7 @@ static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, // this should call rr_graph_builder to do the job for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ - if (CHANX != rr_graph.node_type(node) && CHANY != rr_graph.node_type(node)) { + if (e_rr_type::CHANX != rr_graph.node_type(node) && e_rr_type::CHANY != rr_graph.node_type(node)) { continue; } /* Reach here, we must have a node of CHANX or CHANY */ @@ -1311,8 +1311,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, /* Alloc the lookup table * .. warning: It is mandatory. There are bugs in resize() when called incrementally in RRSpatialLookup. * When comment the following block out, you will see errors */ - for (t_rr_type rr_type : RR_TYPES) { - if (rr_type == CHANX) { + for (e_rr_type rr_type : RR_TYPES) { + if (rr_type == e_rr_type::CHANX) { rr_graph_builder.node_lookup().resize_nodes(layer, grids.height(), grids.width(), rr_type, NUM_2D_SIDES); } else { rr_graph_builder.node_lookup().resize_nodes(layer, grids.width(), grids.height(), rr_type, NUM_2D_SIDES); @@ -1360,7 +1360,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, /* Update node look-up for CHANX and CHANY nodes */ for (const RRNodeId& rr_node_id : rr_graph.nodes()) { - if (CHANX == rr_graph.node_type(rr_node_id) || CHANY == rr_graph.node_type(rr_node_id)) { + if (e_rr_type::CHANX == rr_graph.node_type(rr_node_id) || e_rr_type::CHANY == rr_graph.node_type(rr_node_id)) { rr_graph_builder.add_track_node_to_lookup(rr_node_id); } } diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 238763f4576..7efa231e348 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -1702,20 +1702,20 @@ std::vector get_all_pb_graph_node_primitives(const t_pb_ bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, const VibInf* vib, - t_rr_type node_type, + e_rr_type node_type, int node_ptc) { - if (node_type == CHANX || node_type == CHANY) { + if (node_type == e_rr_type::CHANX || node_type == e_rr_type::CHANY) { return true; - } else if (node_type == MEDIUM) { // This function will check all types of nodes. MEDIUM is added for avoiding errors. + } else if (node_type == e_rr_type::MEDIUM) { // This function will check all types of nodes. MEDIUM is added for avoiding errors. VTR_ASSERT(vib != nullptr); return (node_ptc < (int)vib->get_first_stages().size()); } else { - VTR_ASSERT(node_type == IPIN || node_type == OPIN || node_type == SINK || node_type == SOURCE); - if (node_type == IPIN || node_type == OPIN) { + VTR_ASSERT(node_type == e_rr_type::IPIN || node_type == e_rr_type::OPIN || node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE); + if (node_type == e_rr_type::IPIN || node_type == e_rr_type::OPIN) { return is_pin_on_tile(physical_tile, node_ptc); } else { - VTR_ASSERT(node_type == SINK || node_type == SOURCE); + VTR_ASSERT(node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE); return is_class_on_tile(physical_tile, node_ptc); } } diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 24ad258c187..1928e3e7bc8 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -241,7 +241,7 @@ std::vector get_all_pb_graph_node_primitives(const t_pb_ bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, const VibInf* vib, - t_rr_type node_type, + e_rr_type node_type, int node_ptc); bool is_inter_cluster_node(const RRGraphView& rr_graph_view, From c12350d73032f3a61ef7cd0f775dc003b1d0c447 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 19 May 2025 14:22:26 -0400 Subject: [PATCH 158/176] make is_io_type() a member function of t_physical_tile_type --- libs/libarchfpga/src/physical_types.cpp | 4 ++++ libs/libarchfpga/src/physical_types.h | 3 +++ libs/libarchfpga/src/physical_types_util.cpp | 15 --------------- libs/libarchfpga/src/physical_types_util.h | 7 ------- vpr/src/util/vpr_utils.h | 5 +---- 5 files changed, 8 insertions(+), 26 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index 9b72cb95758..fa83dfecc86 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -172,6 +172,10 @@ bool t_physical_tile_type::is_empty() const { return name == std::string(EMPTY_BLOCK_NAME); } +bool t_physical_tile_type::is_io_type() const { + return is_input_type || is_output_type; +} + int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_port) const { int ipin = OPEN; int port_base_ipin = 0; diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index c2459721d93..62224dcbcb5 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -725,6 +725,9 @@ struct t_physical_tile_type { ///@brief Is this t_physical_tile_type an empty type? bool is_empty() const; + ///@brief Returns true if the physical tile type can implement either a .input or .output block type + bool is_io_type() const; + ///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port int find_pin(std::string_view port_name, int pin_index_in_port) const; diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp index 2ecc7fbd41c..74ad3aa6f1e 100644 --- a/libs/libarchfpga/src/physical_types_util.cpp +++ b/libs/libarchfpga/src/physical_types_util.cpp @@ -637,21 +637,6 @@ bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from return false; } -// TODO: Remove is_input_type / is_output_type / is_io_type as part of -// https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193 -bool is_input_type(t_physical_tile_type_ptr type) { - return type->is_input_type; -} - -bool is_output_type(t_physical_tile_type_ptr type) { - return type->is_output_type; -} - -bool is_io_type(t_physical_tile_type_ptr type) { - return is_input_type(type) - || is_output_type(type); -} - std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_physical_num, bool is_flat) { int max_ptc = get_tile_pin_max_ptc(type, is_flat); VTR_ASSERT(pin_physical_num < max_ptc); diff --git a/libs/libarchfpga/src/physical_types_util.h b/libs/libarchfpga/src/physical_types_util.h index a081683faeb..84cad62a845 100644 --- a/libs/libarchfpga/src/physical_types_util.h +++ b/libs/libarchfpga/src/physical_types_util.h @@ -120,13 +120,6 @@ bool is_opin(int ipin, t_physical_tile_type_ptr type); ///@brief Returns true if the specified pin is located at "from_layer" and it is connected to "to_layer" bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from_layer, int to_layer, int num_of_avail_layer); -///@brief Returns true if the given physical tile type can implement a .input block type -bool is_input_type(t_physical_tile_type_ptr type); -///@brief Returns true if the given physical tile type can implement a .output block type -bool is_output_type(t_physical_tile_type_ptr type); -///@brief Returns true if the given physical tile type can implement either a .input or .output block type -bool is_io_type(t_physical_tile_type_ptr type); - /** * @brief Returns the corresponding physical pin based on the input parameters: * diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 762efd36c5d..d9f279a47a3 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -1,5 +1,4 @@ -#ifndef VPR_UTILS_H -#define VPR_UTILS_H +#pragma once #include "arch_util.h" #include "atom_netlist.h" @@ -362,5 +361,3 @@ class PortPinToBlockPinConverter { */ std::vector>>> blk_pin_from_port_pin_; }; - -#endif From 490740eca9262285d2b583c4ba7fe32efe898dd0 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 19 May 2025 14:40:52 -0400 Subject: [PATCH 159/176] replace calls to is_io_type() with t_physical_tile_type::is_io() --- libs/libarchfpga/src/physical_types.cpp | 2 +- libs/libarchfpga/src/physical_types.h | 2 +- vpr/src/base/ShowSetup.cpp | 2 +- vpr/src/base/check_netlist.cpp | 3 +- vpr/src/base/read_route.cpp | 15 ++++--- vpr/src/base/stats.cpp | 9 ++-- vpr/src/pack/appack_max_dist_th_manager.cpp | 2 +- vpr/src/place/initial_placement.cpp | 8 ++-- vpr/src/route/route_common.cpp | 2 +- .../rr_graph_generation/rr_node_indices.cpp | 41 +++++++++---------- vpr/src/util/vpr_utils.h | 7 ---- 11 files changed, 42 insertions(+), 51 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index fa83dfecc86..f3934f34de6 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -172,7 +172,7 @@ bool t_physical_tile_type::is_empty() const { return name == std::string(EMPTY_BLOCK_NAME); } -bool t_physical_tile_type::is_io_type() const { +bool t_physical_tile_type::is_io() const { return is_input_type || is_output_type; } diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 62224dcbcb5..db1f9193030 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -726,7 +726,7 @@ struct t_physical_tile_type { bool is_empty() const; ///@brief Returns true if the physical tile type can implement either a .input or .output block type - bool is_io_type() const; + bool is_io() const; ///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port int find_pin(std::string_view port_name, int pin_index_in_port) const; diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index fa81fa9f1ac..ccf900f8ef8 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -135,7 +135,7 @@ ClusteredNetlistStats::ClusteredNetlistStats() { auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); auto physical_tile = pick_physical_type(logical_block); num_blocks_type[logical_block->index]++; - if (is_io_type(physical_tile)) { + if (physical_tile->is_io()) { for (int j = 0; j < logical_block->pb_type->num_pins; j++) { int physical_pin = get_physical_pin(physical_tile, logical_block, j); diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp index 3d777f3ec4b..d8ad7fab6f6 100644 --- a/vpr/src/base/check_netlist.cpp +++ b/vpr/src/base/check_netlist.cpp @@ -110,8 +110,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi int log_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id); int pin_index = get_physical_pin(physical_type, logical_type, log_index); - if (physical_type->is_ignored_pin[pin_index] != net_is_ignored - && !is_io_type(physical_type)) { + if (physical_type->is_ignored_pin[pin_index] != net_is_ignored && !physical_type->is_io()) { VTR_LOGV_WARN(verbosity > 2, "Global net '%s' connects to non-global architecture pin '%s' (netlist pin '%s')\n", cluster_ctx.clb_nlist.net_name(net_id).c_str(), diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index 0b8231925e7..be2c4aa18bc 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -296,7 +296,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN /* Verify types and ptc*/ if (tokens[2] == "SOURCE" || tokens[2] == "SINK" || tokens[2] == "OPIN" || tokens[2] == "IPIN") { const auto& type = device_ctx.grid.get_physical_type({x, y, layer_num}); - if (tokens[4 + offset] == "Pad:" && !is_io_type(type)) { + if (tokens[4 + offset] == "Pad:" && !type->is_io()) { vpr_throw(VPR_ERROR_ROUTE, filename, lineno, "Node %d is of the wrong type", inode); } @@ -319,7 +319,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN if (tokens[6 + offset] != "Switch:") { /*This is an opin or ipin, process its pin nums*/ auto type = device_ctx.grid.get_physical_type({x, y, layer_num}); - if (!is_io_type(type) && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) { + if (!type->is_io() && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) { int pin_num = rr_graph.node_pin_num(RRNodeId(inode)); int width_offset = device_ctx.grid.get_width_offset({x, y, layer_num}); int height_offset = device_ctx.grid.get_height_offset({x, y, layer_num}); @@ -592,10 +592,13 @@ void print_route(const Netlist<>& net_list, fprintf(fp, "to (%d,%d,%d) ", rr_graph.node_xhigh(inode), rr_graph.node_yhigh(inode), layer_num); + t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({ilow, jlow, layer_num}); + switch (rr_type) { case e_rr_type::IPIN: case e_rr_type::OPIN: - if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) { + + if (physical_tile->is_io()) { fprintf(fp, " Pad: "); } else { /* IO Pad. */ fprintf(fp, " Pin: "); @@ -609,7 +612,7 @@ void print_route(const Netlist<>& net_list, case e_rr_type::SOURCE: case e_rr_type::SINK: - if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) { + if (physical_tile->is_io()) { fprintf(fp, " Pad: "); } else { /* IO Pad. */ fprintf(fp, " Class: "); @@ -625,8 +628,8 @@ void print_route(const Netlist<>& net_list, fprintf(fp, "%d ", rr_graph.node_ptc_num(inode)); - auto physical_tile = device_ctx.grid.get_physical_type({ilow, jlow, layer_num}); - if (!is_io_type(physical_tile) && (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN)) { + + if (!physical_tile->is_io() && (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN)) { int pin_num = rr_graph.node_pin_num(inode); int xoffset = device_ctx.grid.get_width_offset({ilow, jlow, layer_num}); int yoffset = device_ctx.grid.get_height_offset({ilow, jlow, layer_num}); diff --git a/vpr/src/base/stats.cpp b/vpr/src/base/stats.cpp index 109147e337b..08927b500ea 100644 --- a/vpr/src/base/stats.cpp +++ b/vpr/src/base/stats.cpp @@ -91,10 +91,7 @@ void routing_stats(const Netlist<>& net_list, auto type = device_ctx.grid.get_physical_type({i, j, layer_num}); int width_offset = device_ctx.grid.get_width_offset({i, j, layer_num}); int height_offset = device_ctx.grid.get_height_offset({i, j, layer_num}); - if (width_offset == 0 - && height_offset == 0 - && !is_io_type(type) - && type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + if (width_offset == 0 && height_offset == 0 && !type->is_io() && !type->is_empty()) { if (type->area == UNDEFINED) { area += grid_logic_tile_area * type->width * type->height; } else { @@ -111,7 +108,7 @@ void routing_stats(const Netlist<>& net_list, for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { t_pl_loc block_loc = block_locs[blk_id].loc; auto type = physical_tile_type(block_loc); - if (!is_io_type(type)) { + if (!type->is_io()) { if (type->area == UNDEFINED) { used_area += grid_logic_tile_area * type->width * type->height; } else { @@ -473,7 +470,7 @@ void print_lambda() { t_pl_loc block_loc = block_locs[blk_id].loc; auto type = physical_tile_type(block_loc); VTR_ASSERT(type != nullptr); - if (!is_io_type(type)) { + if (!type->is_io()) { for (int ipin = 0; ipin < type->num_pins; ipin++) { if (get_pin_type_from_pin_physical_num(type, ipin) == RECEIVER) { ClusterNetId net_id = cluster_ctx.clb_nlist.block_net(blk_id, ipin); diff --git a/vpr/src/pack/appack_max_dist_th_manager.cpp b/vpr/src/pack/appack_max_dist_th_manager.cpp index 9f9a39815a7..c5c9b685b73 100644 --- a/vpr/src/pack/appack_max_dist_th_manager.cpp +++ b/vpr/src/pack/appack_max_dist_th_manager.cpp @@ -100,7 +100,7 @@ void APPackMaxDistThManager::auto_set_max_distance_thresholds(const std::vector< // Find which type(s) this logical block type looks like. bool has_memory = has_memory_pbs(lb_ty.pb_type); bool is_logic_block_type = (lb_ty.index == logic_block_type->index); - bool is_io_block = is_io_type(pick_physical_type(&lb_ty)); + bool is_io_block = pick_physical_type(&lb_ty)->is_io(); // Update the max distance threshold based on the type. If the logical // block type looks like many block types at the same time (for example diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 3dc8650a3e2..bcf6e3b7094 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -1012,10 +1012,10 @@ static inline void fix_IO_block_types(const t_pl_macro& pl_macro, vtr::vector_map& block_locs) { const auto& device_ctx = g_vpr_ctx.device(); - //If the user marked the IO block pad_loc_type as RANDOM, that means it should be randomly - //placed and then stay fixed to that location, which is why the macro members are marked as fixed. - const auto& type = device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer}); - if (is_io_type(type) && pad_loc_type == e_pad_loc_type::RANDOM) { + // If the user marked the IO block pad_loc_type as RANDOM, that means it should be randomly + // placed and then stay fixed to that location, which is why the macro members are marked as fixed. + const t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer}); + if (type->is_io() && pad_loc_type == e_pad_loc_type::RANDOM) { for (const t_pl_macro_member& pl_macro_member : pl_macro.members) { block_locs[pl_macro_member.blk_index].is_fixed = true; } diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 43501cd04aa..3f6d574b601 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -358,7 +358,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() { clb_opins_used_locally[blk_id].resize((int)type->class_inf.size()); - if (is_io_type(type)) continue; + if (type->is_io()) continue; const auto [pin_low, pin_high] = get_pin_range_for_block(blk_id); diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp index 062b4e79b90..99c1a729e6c 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -4,6 +4,7 @@ #include "describe_rr_node.h" #include "globals.h" #include "physical_types_util.h" +#include "vpr_utils.h" /** * @brief Assigns and loads rr_node indices for block-level routing resources (SOURCE, SINK, IPIN, OPIN). @@ -70,7 +71,7 @@ static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grid, int* index) { - //Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN + // Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN for (int layer = 0; layer < grid.get_num_layers(); layer++) { for (int x = 0; x < (int)grid.width(); x++) { for (int y = 0; y < (int)grid.height(); y++) { @@ -78,7 +79,7 @@ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, if (grid.is_root_location({x, y, layer})) { t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); - //Assign indices for SINKs and SOURCEs + // Assign indices for SINKs and SOURCEs // Note that SINKS/SOURCES have no side, so we always use side 0 std::vector class_num_vec = get_tile_root_classes(physical_type); std::vector pin_num_vec = get_tile_root_pins(physical_type); @@ -124,22 +125,20 @@ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, * for the same input pin on multiple sides, and thus avoid multiple driver problems */ std::vector wanted_sides; - if ((int)grid.height() - 1 == y) { /* TOP side */ + if ((int)grid.height() - 1 == y) { // TOP side wanted_sides.push_back(BOTTOM); } - if ((int)grid.width() - 1 == x) { /* RIGHT side */ + if ((int)grid.width() - 1 == x) { // RIGHT side wanted_sides.push_back(LEFT); } - if (0 == y) { /* BOTTOM side */ + if (0 == y) { // BOTTOM side wanted_sides.push_back(TOP); } - if (0 == x) { /* LEFT side */ + if (0 == x) { // LEFT side wanted_sides.push_back(RIGHT); } - /* If wanted sides is empty still, this block does not have specific wanted sides, - * Deposit all the sides - */ + // If wanted sides is empty still, this block does not have specific wanted sides, Deposit all the sides if (wanted_sides.empty()) { for (e_side side : TOTAL_2D_SIDES) { wanted_sides.push_back(side); @@ -262,7 +261,7 @@ static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, int x_tile = root_x + width_offset; for (int height_offset = 0; height_offset < physical_type_ptr->height; ++height_offset) { int y_tile = root_y + height_offset; - //only nodes on the tile may be located in a location other than the root-location + // only nodes on the tile may be located in a location other than the root-location rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::OPIN, physical_type_ptr->num_pins, side); rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::IPIN, physical_type_ptr->num_pins, side); } @@ -309,15 +308,15 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, int* index, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y) { - /* Alloc the lookup table */ + // Alloc the lookup table for (e_rr_type rr_type : RR_TYPES) { rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.width(), grid.height(), rr_type, NUM_2D_SIDES); } - /* Assign indices for block nodes */ + // Assign indices for block nodes load_block_rr_indices(rr_graph_builder, grid, index); - /* Load the data for x and y channels */ + // Load the data for x and y channels load_chan_rr_indices(nodes_per_chan.x_max, grid, grid.width(), grid.height(), e_rr_type::CHANX, chan_details_x, rr_graph_builder.node_lookup(), index); load_chan_rr_indices(nodes_per_chan.y_max, grid, grid.height(), grid.width(), @@ -341,7 +340,7 @@ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, const auto& device_ctx = g_vpr_ctx.device(); for (int layer = 0; layer < grid.get_num_layers(); layer++) { - /* Skip the current die if architecture file specifies that it doesn't have global resource routing */ + // Skip the current die if architecture file specifies that it doesn't have global resource routing if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { continue; } @@ -412,10 +411,10 @@ void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_build for (int layer = 0; layer < grid.get_num_layers(); layer++) { for (int x = 0; x < (int)grid.width(); x++) { for (int y = 0; y < (int)grid.height(); y++) { - //Process each block from its root location + // Process each block from its root location if (grid.is_root_location({x, y, layer})) { t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); - //Assign indices for SINKs and SOURCEs + // Assign indices for SINKs and SOURCEs // Note that SINKS/SOURCES have no side, so we always use side 0 std::vector class_num_vec; std::vector pin_num_vec; @@ -467,7 +466,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, for (int x = 0; x < width; ++x) { for (int y = 0; y < height; ++y) { for (e_rr_type rr_type : RR_TYPES) { - /* Get the list of nodes at a specific location (x, y) */ + // Get the list of nodes at a specific location (x, y) std::vector nodes_from_lookup; if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { nodes_from_lookup = rr_graph.node_lookup().find_channel_nodes(l, x, y, rr_type); @@ -584,7 +583,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, RRNodeId inode = kv.first; int count = kv.second; - auto& rr_node = rr_nodes[size_t(inode)]; + const t_rr_node& rr_node = rr_nodes[size_t(inode)]; if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { int rr_width = (rr_graph.node_xhigh(rr_node.id()) - rr_graph.node_xlow(rr_node.id()) + 1); @@ -597,9 +596,9 @@ bool verify_rr_node_indices(const DeviceGrid& grid, count, describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } - /* As we allow a pin to be indexable on multiple sides, - * This check code should not be applied to input and output pins - */ + // As we allow a pin to be indexable on multiple sides, + // This check code should not be applied to input and output pins + } else if ((e_rr_type::OPIN != rr_graph.node_type(inode)) && (e_rr_type::IPIN != rr_graph.node_type(inode))) { if (count != rr_node.length() + 1) { VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node length (%d) and count within rr_node_indices (%d, should be length + 1): %s", diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index d9f279a47a3..842b18fef47 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -286,13 +286,6 @@ std::vector get_cluster_netlist_intra_tile_classes_at_loc(int layer, /** * @brief Returns the list of pins inside the tile located at (layer, i, j), except for the ones which are on a chain - * @param layer - * @param i - * @param j - * @param pin_chains - * @param pin_chains_num - * @param physical_type - * @return */ std::vector get_cluster_netlist_intra_tile_pins_at_loc(const int layer, const int i, From 236515018ed37c8954ad51f608bfc289a9e8d5fe Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 19 May 2025 14:41:53 -0400 Subject: [PATCH 160/176] make format --- vpr/src/base/read_route.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index be2c4aa18bc..3ede11a9f98 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -628,7 +628,6 @@ void print_route(const Netlist<>& net_list, fprintf(fp, "%d ", rr_graph.node_ptc_num(inode)); - if (!physical_tile->is_io() && (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN)) { int pin_num = rr_graph.node_pin_num(inode); int xoffset = device_ctx.grid.get_width_offset({ilow, jlow, layer_num}); From e2b2993d049622f0af3d8b7cb012b4073864c883 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 19 May 2025 14:48:52 -0400 Subject: [PATCH 161/176] fix compiler bugs --- .../src/io/rr_graph_uxsdcxx_serializer.h | 2 +- libs/librrgraph/src/utils/describe_rr_node.cpp | 2 +- vpr/src/base/read_blif.cpp | 1 + vpr/src/base/read_route.cpp | 2 +- vpr/src/route/router_lookahead_map.cpp | 8 +------- .../openfpga_rr_graph_utils.cpp | 16 ++++++++-------- .../tileable_rr_graph_edge_builder.cpp | 8 ++++---- 7 files changed, 17 insertions(+), 22 deletions(-) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 71e79d4b93f..81e2ead5ef7 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -2051,7 +2051,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { return uxsd::enum_node_type::OPIN; case e_rr_type::IPIN: return uxsd::enum_node_type::IPIN; - case MEDIUM: + case e_rr_type::MEDIUM: return uxsd::enum_node_type::MEDIUM; default: report_error( diff --git a/libs/librrgraph/src/utils/describe_rr_node.cpp b/libs/librrgraph/src/utils/describe_rr_node.cpp index 2263714e107..80ee74027c5 100644 --- a/libs/librrgraph/src/utils/describe_rr_node.cpp +++ b/libs/librrgraph/src/utils/describe_rr_node.cpp @@ -36,7 +36,7 @@ std::string describe_rr_node(const RRGraphView& rr_graph, msg += vtr::string_fmt(" pin: %d pin_name: %s", rr_graph.node_pin_num(inode), pin_name.c_str()); - } else if (rr_graph.node_type(inode) == MEDIUM) { + } else if (rr_graph.node_type(inode) == e_rr_type::MEDIUM) { auto index = rr_graph.node_ptc_num(inode); msg += vtr::string_fmt(" medium index: %d", diff --git a/vpr/src/base/read_blif.cpp b/vpr/src/base/read_blif.cpp index 57dfada9de3..9e0668e39d1 100644 --- a/vpr/src/base/read_blif.cpp +++ b/vpr/src/base/read_blif.cpp @@ -19,6 +19,7 @@ #include #include #include //std::isdigit +#include //std::regex #include "blifparse.hpp" #include "atom_netlist.h" diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index 0715fd4dd02..f08ca215000 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -616,7 +616,7 @@ void print_route(const Netlist<>& net_list, } break; - case MEDIUM: + case e_rr_type::MEDIUM: fprintf(fp, " INDEX: "); break; diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 4ef6aa6e4fe..8f4909e2671 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -200,13 +200,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI t_physical_tile_type_ptr from_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node), rr_graph.node_layer(current_node)}); - const VibInf* vib; - if (!device_ctx.arch->vib_infs.empty()) { - vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(current_node), rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node)); - } else { - vib = nullptr; - } - //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(current_node)][rr_graph.node_xlow(current_node)][rr_graph.node_ylow(current_node)]; + int from_node_ptc_num = rr_graph.node_ptc_num(current_node); t_physical_tile_type_ptr to_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(target_node), rr_graph.node_ylow(target_node), diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index 986339d96a9..cd2de438df8 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -24,8 +24,8 @@ vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_graph, const RRNodeId& track_rr_node) { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) - || (CHANY == rr_graph.node_type(track_rr_node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(track_rr_node)) + || (e_rr_type::CHANY == rr_graph.node_type(track_rr_node))); vtr::Point start_coordinator; @@ -50,8 +50,8 @@ vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_grap vtr::Point get_track_rr_node_end_coordinate(const RRGraphView& rr_graph, const RRNodeId& track_rr_node) { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) - || (CHANY == rr_graph.node_type(track_rr_node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(track_rr_node)) + || (e_rr_type::CHANY == rr_graph.node_type(track_rr_node))); vtr::Point end_coordinator; @@ -141,7 +141,7 @@ std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraphVi bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, const RRNodeId& node) { /* We only accept OPIN */ - VTR_ASSERT(OPIN == rr_graph.node_type(node)); + VTR_ASSERT(e_rr_type::OPIN == rr_graph.node_type(node)); if (1 != rr_graph.node_out_edges(node).size()) { return false; @@ -150,7 +150,7 @@ bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, VTR_ASSERT(1 == rr_graph.node_out_edges(node).size()); for (auto edge : rr_graph.node_out_edges(node)) { const RRNodeId& sink_node = rr_graph.edge_sink_node(node, edge); - if (IPIN != rr_graph.node_type(sink_node)) { + if (e_rr_type::IPIN != rr_graph.node_type(sink_node)) { return false; } } @@ -167,7 +167,7 @@ bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, const RRNodeId& node) { /* We only accept IPIN */ - VTR_ASSERT(IPIN == rr_graph.node_type(node)); + VTR_ASSERT(e_rr_type::IPIN == rr_graph.node_type(node)); if (1 != rr_graph.node_in_edges(node).size()) { return false; @@ -176,7 +176,7 @@ bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, VTR_ASSERT(1 == rr_graph.node_in_edges(node).size()); for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { const RRNodeId& src_node = rr_graph.edge_src_node(edge); - if (OPIN != rr_graph.node_type(src_node)) { + if (e_rr_type::OPIN != rr_graph.node_type(src_node)) { return false; } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 4b32fcab7cf..94d2c0dfd9a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -28,7 +28,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, size_t edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non OPIN nodes */ - if (OPIN != rr_graph.node_type(node)) { + if (e_rr_type::OPIN != rr_graph.node_type(node)) { continue; } /* Now, we have an OPIN node, we get the source node index */ @@ -41,7 +41,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, RRNodeId src_node = rr_graph.node_lookup().find_node(layer, xlow - grids.get_width_offset(tile_loc), ylow - grids.get_height_offset(tile_loc), - SOURCE, src_node_class_num); + e_rr_type::SOURCE, src_node_class_num); VTR_ASSERT(true == rr_graph.valid_node(src_node)); /* add edges to the src_node */ @@ -66,7 +66,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, size_t edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non IPIN nodes */ - if (IPIN != rr_graph.node_type(node)) { + if (e_rr_type::IPIN != rr_graph.node_type(node)) { continue; } /* Now, we have an OPIN node, we get the source node index */ @@ -79,7 +79,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, const RRNodeId& sink_node = rr_graph.node_lookup().find_node(layer, xlow - grids.get_width_offset(tile_loc), ylow - grids.get_height_offset(tile_loc), - SINK, sink_node_class_num, TOTAL_2D_SIDES[0]); + e_rr_type::SINK, sink_node_class_num, TOTAL_2D_SIDES[0]); VTR_ASSERT(true == rr_graph.valid_node(sink_node)); /* add edges to connect the IPIN node to SINK nodes */ From 6aa559f41f5f45b7a54adb5503bf776e30ef6eab Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 19 May 2025 14:49:22 -0400 Subject: [PATCH 162/176] make format --- vpr/src/base/SetupGrid.h | 1 - vpr/src/base/SetupVPR.cpp | 1 - vpr/src/route/router_lookahead_map.cpp | 2 +- .../tileable_rr_graph_node_builder.cpp | 60 +++++++++---------- 4 files changed, 31 insertions(+), 33 deletions(-) diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 3f2568d673f..9686f1b7546 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -24,7 +24,6 @@ DeviceGrid create_device_grid(const std::string& layout_name, ///@brief Find the device close in size to the specified dimensions DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); - /** * @brief Returns the effective size of the device * (size of the bounding box of non-empty grid tiles) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 4eafc22647e..21b98f50848 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -449,7 +449,6 @@ static void SetupRoutingArch(const t_arch& Arch, RoutingArch.opin2all_sides = Arch.opin2all_sides; RoutingArch.concat_wire = Arch.concat_wire; RoutingArch.concat_pass_wire = Arch.concat_pass_wire; - } static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 8f4909e2671..c3aae0cabbe 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -200,7 +200,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI t_physical_tile_type_ptr from_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node), rr_graph.node_layer(current_node)}); - + int from_node_ptc_num = rr_graph.node_ptc_num(current_node); t_physical_tile_type_ptr to_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(target_node), rr_graph.node_ylow(target_node), diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 107a987f87d..96fa44f6686 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -364,15 +364,15 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ static vtr::vector estimate_num_rr_nodes(const DeviceGrid& grids, - const VibDeviceGrid& vib_grid, - const size_t& layer, - const vtr::Point& chan_width, - const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - const DeviceGridAnnotation& device_grid_annotation, - const bool& shrink_boundary, - const bool& perimeter_cb, - const bool& through_channel) { + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& chan_width, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel) { /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ vtr::vector num_rr_nodes_per_type(static_cast(e_rr_type::NUM_RR_TYPES), 0); @@ -406,19 +406,19 @@ static vtr::vector estimate_num_rr_nodes(const DeviceGrid& gr * So we will load segment details for different channels */ num_rr_nodes_per_type[e_rr_type::CHANX] = estimate_num_chanx_rr_nodes(grids, layer, - chan_width.x(), - segment_inf_x, - device_grid_annotation, - shrink_boundary, - perimeter_cb, - through_channel); + chan_width.x(), + segment_inf_x, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); num_rr_nodes_per_type[e_rr_type::CHANY] = estimate_num_chany_rr_nodes(grids, layer, - chan_width.y(), - segment_inf_y, - device_grid_annotation, - shrink_boundary, - perimeter_cb, - through_channel); + chan_width.y(), + segment_inf_y, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); return num_rr_nodes_per_type; } @@ -445,15 +445,15 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); vtr::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, - vib_grid, - layer, - chan_width, - segment_inf_x, - segment_inf_y, - device_grid_annotation, - shrink_boundary, - perimeter_cb, - through_channel); + vib_grid, + layer, + chan_width, + segment_inf_x, + segment_inf_y, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); /* Reserve the number of node to be memory efficient */ size_t num_nodes = 0; From ab37b7c10ee3c22d0a11cfcad51b9fb1b3dd1dfd Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 19 May 2025 16:23:34 -0400 Subject: [PATCH 163/176] [lib][libutil] fix size_t issue --- libs/libvtrutil/src/vtr_logic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libvtrutil/src/vtr_logic.h b/libs/libvtrutil/src/vtr_logic.h index 21b08fea22b..3ad2deb7f97 100644 --- a/libs/libvtrutil/src/vtr_logic.h +++ b/libs/libvtrutil/src/vtr_logic.h @@ -31,7 +31,7 @@ enum class LogicValue { NUM_LOGIC_VALUE_TYPES }; -constexpr std::array LOGIC_VALUE_STRING = {{"false", "true", "don't care", "unknown"}}; +constexpr std::array LOGIC_VALUE_STRING = {{"false", "true", "don't care", "unknown"}}; } // namespace vtr From ee82313bae78c3bef6f698017d7d117ba378243b Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 19 May 2025 17:15:14 -0400 Subject: [PATCH 164/176] inline t_physical_tile_type::is_io() --- libs/libarchfpga/src/physical_types.cpp | 4 ---- libs/libarchfpga/src/physical_types.h | 4 +++- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index f3934f34de6..9b72cb95758 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -172,10 +172,6 @@ bool t_physical_tile_type::is_empty() const { return name == std::string(EMPTY_BLOCK_NAME); } -bool t_physical_tile_type::is_io() const { - return is_input_type || is_output_type; -} - int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_port) const { int ipin = OPEN; int port_base_ipin = 0; diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index db1f9193030..94e486afd51 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -726,7 +726,9 @@ struct t_physical_tile_type { bool is_empty() const; ///@brief Returns true if the physical tile type can implement either a .input or .output block type - bool is_io() const; + inline bool is_io() const { + return is_input_type || is_output_type; + } ///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port int find_pin(std::string_view port_name, int pin_index_in_port) const; From d83b07cd747b56c7e5283f250336480ad0520a5a Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 19 May 2025 17:25:25 -0400 Subject: [PATCH 165/176] add doxygen comments for alloc_and_load_tile_rr_node_indices() --- vpr/src/route/router_lookahead_map.cpp | 2 +- .../route/rr_graph_generation/rr_node_indices.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index b8782a45c5a..b9dde54cd95 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -89,7 +89,7 @@ static void compute_tiles_lookahead(std::unordered_map cost * @param physical_tile * @param det_routing_arch diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.h b/vpr/src/route/rr_graph_generation/rr_node_indices.h index 0be90e07c6a..00c555416bc 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.h +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.h @@ -37,6 +37,21 @@ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, const vtr::NdMatrix& extra_nodes_per_switchblock, int* index); +/** + * @brief Allocates and loads RR node indices for a specific tile. + * + * This function assigns RR node IDs to all classes (SOURCE/SINK) and pins (IPIN/OPIN) + * associated with a given physical tile at a specific grid location and layer. + * It is primarily used in scenarios where a standalone tile's routing resources + * need to be initialized independently. + * + * @param rr_graph_builder Reference to the RR graph builder with spatial lookup. + * @param physical_tile Pointer to the physical tile type being processed. + * @param layer Layer index of the tile in the device grid. + * @param x X-coordinate of the tile's root position in the grid. + * @param y Y-coordinate of the tile's root position in the grid. + * @param num_rr_nodes Pointer to the global RR node index counter (will be incremented). + */ void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, t_physical_tile_type_ptr physical_tile, int layer, From 6d9276143f57859c89746415ec5ccd6a6a2f7554 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Mon, 19 May 2025 17:32:08 -0400 Subject: [PATCH 166/176] [libs][vtrutil] use generate instead of fill to avoid getting potential null pointer dereference --- libs/libvtrutil/src/vtr_ndmatrix.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libvtrutil/src/vtr_ndmatrix.h b/libs/libvtrutil/src/vtr_ndmatrix.h index a9a41ff41b4..7c3eb5d7c49 100644 --- a/libs/libvtrutil/src/vtr_ndmatrix.h +++ b/libs/libvtrutil/src/vtr_ndmatrix.h @@ -248,7 +248,7 @@ class NdMatrixBase { public: //Mutators ///@brief Set all elements to 'value' void fill(T value) { - std::fill(data_.get(), data_.get() + size(), value); + std::generate(data_.get(), data_.get() + size(), [=]() { return value; }); } /** From 2c47c52a3cb21b5ef7e96aa78adf9ea7e4e99147 Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 19 May 2025 17:32:45 -0400 Subject: [PATCH 167/176] document alloc_and_load_rr_node_indices() arguments --- .../rr_graph_generation/rr_node_indices.h | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.h b/vpr/src/route/rr_graph_generation/rr_node_indices.h index 00c555416bc..76373c1cc70 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.h +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.h @@ -13,6 +13,13 @@ * * This function sets up the `rr_node_indices` structure, which maps a physical location * and type to the index of the first corresponding rr_node. + * + * @param rr_graph_builder Reference to the RRGraphBuilder used to construct and populate RR node spatial lookups. + * @param nodes_per_chan Specifies the maximum number of routing tracks per channel in the x and y directions. + * @param grid The device grid representing the physical layout of tiles in the FPGA fabric. + * @param index Pointer to the global RR node index counter; incremented as new RR nodes are assigned. + * @param chan_details_x Channel details describing segment and track properties for CHANX (horizontal) routing tracks. + * @param chan_details_y Channel details describing segment and track properties for CHANY (vertical) routing tracks. */ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_width& nodes_per_chan, @@ -24,12 +31,12 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, /** * @brief Allocates extra nodes within the RR graph to support 3D custom switch blocks for multi-die FPGAs * - * @param rr_graph_builder RRGraphBuilder data structure which allows data modification on a routing resource graph - * @param nodes_per_chan number of tracks per channel (x, y) - * @param grid device grid - * @param extra_nodes_per_switchblock keeps how many extra length-0 CHANX node is required for each unique (x,y) location within the grid. - * Number of these extra nodes are exactly the same for all layers. Hence, we only keep it for one layer. ([0..grid.width-1][0..grid.height-1) - * @param index RRNodeId that should be assigned to add a new RR node to the RR graph + * @param rr_graph_builder RRGraphBuilder data structure which allows data modification on a routing resource graph + * @param nodes_per_chan number of tracks per channel (x, y) + * @param grid The device grid representing the physical layout of tiles in the FPGA fabric. + * @param extra_nodes_per_switchblock keeps how many extra length-0 CHANX node is required for each unique (x,y) location within the grid. + * Number of these extra nodes are exactly the same for all layers. Hence, we only keep it for one layer. ([0..grid.width-1][0..grid.height-1) + * @param index Pointer to the global RR node index counter; incremented as new RR nodes are assigned. */ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_width& nodes_per_chan, From 1681fa1ac2d67a7153b0c78e4df80838ebe0d03c Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 19 May 2025 17:47:37 -0400 Subject: [PATCH 168/176] made a few function operating on t_pb_type its member functions --- libs/libarchfpga/src/physical_types.cpp | 66 ++++++++++++++++++++++++- libs/libarchfpga/src/physical_types.h | 4 ++ vpr/src/util/vpr_utils.cpp | 60 ---------------------- vpr/src/util/vpr_utils.h | 3 -- 4 files changed, 69 insertions(+), 64 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index 9b72cb95758..6032bcb6d26 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -252,7 +252,71 @@ const t_port* t_logical_block_type::get_port_by_pin(int pin) const { return nullptr; } -/** +/* + * t_pb_type + */ + +int t_pb_type::get_max_primitives() const { + int max_size; + + if (modes == nullptr) { + max_size = 1; + } else { + max_size = 0; + int temp_size = 0; + for (int i = 0; i < num_modes; i++) { + for (int j = 0; j < modes[i].num_pb_type_children; j++) { + temp_size += modes[i].pb_type_children[j].num_pb * modes[i].pb_type_children[j].get_max_primitives(); + } + if (temp_size > max_size) { + max_size = temp_size; + } + } + } + + return max_size; +} + +/* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */ +int t_pb_type::get_max_nets() const { + int max_nets; + if (modes == nullptr) { + max_nets = num_output_pins; + } else { + max_nets = 0; + + for (int i = 0; i < num_modes; i++) { + int temp_nets = 0; + for (int j = 0; j < modes[i].num_pb_type_children; j++) { + temp_nets += modes[i].pb_type_children[j].num_pb * modes[i].pb_type_children[j].get_max_nets(); + } + + if (temp_nets > max_nets) { + max_nets = temp_nets; + } + } + } + + if (is_root()) { + max_nets += num_input_pins + num_output_pins + num_clock_pins; + } + + return max_nets; +} + +int t_pb_type::get_max_depth() const { + int max_depth = depth; + + for (int i = 0; i < num_modes; i++) { + for (int j = 0; j < modes[i].num_pb_type_children; j++) { + int temp_depth = modes[i].pb_type_children[j].get_max_depth(); + max_depth = std::max(max_depth, temp_depth); + } + } + return max_depth; +} + +/* * t_pb_graph_node */ diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 94e486afd51..27b787f7c6b 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1092,6 +1092,10 @@ struct t_pb_type { inline bool is_primitive() const { return num_modes == 0; } + + int get_max_primitives() const; + int get_max_depth() const; + int get_max_nets() const; }; /** Describes an operational mode of a clustered logic block diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 34c2156b98f..82b019676f9 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -729,66 +729,6 @@ static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::reg return false; } -int get_max_primitives_in_pb_type(t_pb_type* pb_type) { - int max_size; - if (pb_type->modes == nullptr) { - max_size = 1; - } else { - max_size = 0; - int temp_size = 0; - for (int i = 0; i < pb_type->num_modes; i++) { - for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - temp_size += pb_type->modes[i].pb_type_children[j].num_pb - * get_max_primitives_in_pb_type( - &pb_type->modes[i].pb_type_children[j]); - } - if (temp_size > max_size) { - max_size = temp_size; - } - } - } - return max_size; -} - -/* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */ -int get_max_nets_in_pb_type(const t_pb_type* pb_type) { - int max_nets; - if (pb_type->modes == nullptr) { - max_nets = pb_type->num_output_pins; - } else { - max_nets = 0; - for (int i = 0; i < pb_type->num_modes; i++) { - int temp_nets = 0; - for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - temp_nets += pb_type->modes[i].pb_type_children[j].num_pb - * get_max_nets_in_pb_type( - &pb_type->modes[i].pb_type_children[j]); - } - if (temp_nets > max_nets) { - max_nets = temp_nets; - } - } - } - if (pb_type->is_root()) { - max_nets += pb_type->num_input_pins + pb_type->num_output_pins - + pb_type->num_clock_pins; - } - return max_nets; -} - -int get_max_depth_of_pb_type(t_pb_type* pb_type) { - int max_depth = pb_type->depth; - for (int i = 0; i < pb_type->num_modes; i++) { - for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - int temp_depth = get_max_depth_of_pb_type(&pb_type->modes[i].pb_type_children[j]); - if (temp_depth > max_depth) { - max_depth = temp_depth; - } - } - } - return max_depth; -} - /** * given an atom block and physical primitive type, is the mapping legal */ diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 842b18fef47..b6828859bd9 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -180,9 +180,6 @@ InstPort parse_inst_port(const std::string& str); //Returns the block type which is most likely the logic block t_logical_block_type_ptr infer_logic_block_type(const DeviceGrid& grid); -int get_max_primitives_in_pb_type(t_pb_type* pb_type); -int get_max_depth_of_pb_type(t_pb_type* pb_type); -int get_max_nets_in_pb_type(const t_pb_type* pb_type); bool primitive_type_feasible(AtomBlockId blk_id, const t_pb_type* cur_pb_type); t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* model_port, const int model_pin, const t_pb_graph_node* pb_graph_node); /// @brief Gets the pb_graph_node pin at the given pin index for the given From 322ba276887b0fabda0e0e9bd7cf0a15cc80a0fd Mon Sep 17 00:00:00 2001 From: soheilshahrouz Date: Mon, 19 May 2025 18:56:54 -0400 Subject: [PATCH 169/176] add router_lookahead directory --- vpr/src/route/{ => router_lookahead}/router_lookahead.cpp | 0 vpr/src/route/{ => router_lookahead}/router_lookahead.h | 0 .../{ => router_lookahead}/router_lookahead_compressed_map.cpp | 0 .../{ => router_lookahead}/router_lookahead_compressed_map.h | 0 .../route/{ => router_lookahead}/router_lookahead_cost_map.cpp | 0 vpr/src/route/{ => router_lookahead}/router_lookahead_cost_map.h | 0 .../{ => router_lookahead}/router_lookahead_extended_map.cpp | 0 .../route/{ => router_lookahead}/router_lookahead_extended_map.h | 0 vpr/src/route/{ => router_lookahead}/router_lookahead_map.cpp | 0 vpr/src/route/{ => router_lookahead}/router_lookahead_map.h | 0 .../route/{ => router_lookahead}/router_lookahead_map_utils.cpp | 0 vpr/src/route/{ => router_lookahead}/router_lookahead_map_utils.h | 0 .../route/{ => router_lookahead}/router_lookahead_sampling.cpp | 0 vpr/src/route/{ => router_lookahead}/router_lookahead_sampling.h | 0 14 files changed, 0 insertions(+), 0 deletions(-) rename vpr/src/route/{ => router_lookahead}/router_lookahead.cpp (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_compressed_map.cpp (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_compressed_map.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_cost_map.cpp (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_cost_map.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_extended_map.cpp (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_extended_map.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_map.cpp (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_map.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_map_utils.cpp (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_map_utils.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_sampling.cpp (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_sampling.h (100%) diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead/router_lookahead.cpp similarity index 100% rename from vpr/src/route/router_lookahead.cpp rename to vpr/src/route/router_lookahead/router_lookahead.cpp diff --git a/vpr/src/route/router_lookahead.h b/vpr/src/route/router_lookahead/router_lookahead.h similarity index 100% rename from vpr/src/route/router_lookahead.h rename to vpr/src/route/router_lookahead/router_lookahead.h diff --git a/vpr/src/route/router_lookahead_compressed_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp similarity index 100% rename from vpr/src/route/router_lookahead_compressed_map.cpp rename to vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp diff --git a/vpr/src/route/router_lookahead_compressed_map.h b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h similarity index 100% rename from vpr/src/route/router_lookahead_compressed_map.h rename to vpr/src/route/router_lookahead/router_lookahead_compressed_map.h diff --git a/vpr/src/route/router_lookahead_cost_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_cost_map.cpp similarity index 100% rename from vpr/src/route/router_lookahead_cost_map.cpp rename to vpr/src/route/router_lookahead/router_lookahead_cost_map.cpp diff --git a/vpr/src/route/router_lookahead_cost_map.h b/vpr/src/route/router_lookahead/router_lookahead_cost_map.h similarity index 100% rename from vpr/src/route/router_lookahead_cost_map.h rename to vpr/src/route/router_lookahead/router_lookahead_cost_map.h diff --git a/vpr/src/route/router_lookahead_extended_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_extended_map.cpp similarity index 100% rename from vpr/src/route/router_lookahead_extended_map.cpp rename to vpr/src/route/router_lookahead/router_lookahead_extended_map.cpp diff --git a/vpr/src/route/router_lookahead_extended_map.h b/vpr/src/route/router_lookahead/router_lookahead_extended_map.h similarity index 100% rename from vpr/src/route/router_lookahead_extended_map.h rename to vpr/src/route/router_lookahead/router_lookahead_extended_map.h diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_map.cpp similarity index 100% rename from vpr/src/route/router_lookahead_map.cpp rename to vpr/src/route/router_lookahead/router_lookahead_map.cpp diff --git a/vpr/src/route/router_lookahead_map.h b/vpr/src/route/router_lookahead/router_lookahead_map.h similarity index 100% rename from vpr/src/route/router_lookahead_map.h rename to vpr/src/route/router_lookahead/router_lookahead_map.h diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp similarity index 100% rename from vpr/src/route/router_lookahead_map_utils.cpp rename to vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead/router_lookahead_map_utils.h similarity index 100% rename from vpr/src/route/router_lookahead_map_utils.h rename to vpr/src/route/router_lookahead/router_lookahead_map_utils.h diff --git a/vpr/src/route/router_lookahead_sampling.cpp b/vpr/src/route/router_lookahead/router_lookahead_sampling.cpp similarity index 100% rename from vpr/src/route/router_lookahead_sampling.cpp rename to vpr/src/route/router_lookahead/router_lookahead_sampling.cpp diff --git a/vpr/src/route/router_lookahead_sampling.h b/vpr/src/route/router_lookahead/router_lookahead_sampling.h similarity index 100% rename from vpr/src/route/router_lookahead_sampling.h rename to vpr/src/route/router_lookahead/router_lookahead_sampling.h From 57611fac04e7ab40f3121a44d1cd3e4f314a07b8 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Mon, 19 May 2025 20:10:04 -0400 Subject: [PATCH 170/176] [STA] Added Multiclock Incremental STA Consistency Check The incremental STA consistency coverage was very good, but was just missing a multiclock circuit with an SDC file. Added a quick test. --- .../vtr_reg_strong/strong_multiclock/config/config.txt | 1 + .../strong_multiclock/config/golden_results.txt | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt index 3734b81c3cf..6e72a741485 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt @@ -26,6 +26,7 @@ pass_requirements_file=pass_requirements_multiclock.txt script_params_common=-starting_stage vpr -sdc_file tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/multiclock.sdc script_params_list_add = +script_params_list_add = --route_chan_width 30 -check_incremental_sta_consistency script_params_list_add = --router_algorithm parallel --num_workers 4 # script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 # script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index d61417eb846..86cec1613d1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,3 +1,4 @@ -arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack -k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 + arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--route_chan_width_30_-check_incremental_sta_consistency 1.3344 0.595 0.781297 -1 -1 0.57 0.757256 -1 1.3344 -1 1.16524 -1 1.77873 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.6593 -1 -1 0.268 3.18526 -1 1.18303 -1 3.40324 -1 -1.46764 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 From fcbb726d8ccdf6c081bbb8654281217c4e96e295 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 20 May 2025 10:54:20 -0400 Subject: [PATCH 171/176] [libs][rr_graph] don't reverse xy when calling node lookup --- libs/librrgraph/src/base/rr_graph_builder.cpp | 16 +++++----------- .../tileable_rr_graph_node_builder.cpp | 6 +----- 2 files changed, 6 insertions(+), 16 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 5f1852a8c77..33ea035f0fe 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -92,11 +92,7 @@ RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, e_rr_type type, in node_storage_.add_node_side(new_node, node_side); } /* Special for CHANX, being consistent with the rule in find_node() */ - if (e_rr_type::CHANX == type) { - node_lookup_.add_node(new_node, layer, y, x, type, ptc, node_side); - } else { - node_lookup_.add_node(new_node, layer, x, y, type, ptc, node_side); - } + node_lookup_.add_node(new_node, layer, x, y, type, ptc, node_side); return new_node; } @@ -310,16 +306,14 @@ void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { for (const size_t& x : node_x) { for (const size_t& y : node_y) { size_t ptc = node_storage_.node_ptc_num(node); + e_rr_type node_type = node_storage_.node_type(node); /* Routing channel nodes may have different ptc num * Find the track ids using the x/y offset * FIXME: Special case on assigning CHANX (x,y) should be changed to a natural way! */ - if (e_rr_type::CHANX == node_storage_.node_type(node)) { - ptc = node_ptc_nums_[node][x - node_storage_.node_xlow(node)]; - node_lookup_.add_node(node, node_storage_.node_layer(node), y, x, e_rr_type::CHANX, ptc); - } else if (e_rr_type::CHANY == node_storage_.node_type(node)) { - ptc = node_ptc_nums_[node][y - node_storage_.node_ylow(node)]; - node_lookup_.add_node(node, node_storage_.node_layer(node), x, y, e_rr_type::CHANY, ptc); + if (e_rr_type::CHANX == node_type || e_rr_type::CHANY == node_type) { + ptc = node_type == e_rr_type::CHANX ? node_ptc_nums_[node][x - node_storage_.node_xlow(node)] : node_ptc_nums_[node][y - node_storage_.node_ylow(node)]; + node_lookup_.add_node(node, node_storage_.node_layer(node), x, y, node_type, ptc); } } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 96fa44f6686..887b876defd 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -1312,11 +1312,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, * .. warning: It is mandatory. There are bugs in resize() when called incrementally in RRSpatialLookup. * When comment the following block out, you will see errors */ for (e_rr_type rr_type : RR_TYPES) { - if (rr_type == e_rr_type::CHANX) { - rr_graph_builder.node_lookup().resize_nodes(layer, grids.height(), grids.width(), rr_type, NUM_2D_SIDES); - } else { - rr_graph_builder.node_lookup().resize_nodes(layer, grids.width(), grids.height(), rr_type, NUM_2D_SIDES); - } + rr_graph_builder.node_lookup().resize_nodes(layer, grids.width(), grids.height(), rr_type, NUM_2D_SIDES); } load_grid_nodes_basic_info(rr_graph_builder, From d13d30c19a8444317bc0caafe82d9900afcd2c8e Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 20 May 2025 11:39:06 -0400 Subject: [PATCH 172/176] [vpr][util] consider medium node type as inter cluster node --- vpr/src/util/vpr_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 7efa231e348..71def992328 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -1724,7 +1724,7 @@ bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, bool is_inter_cluster_node(const RRGraphView& rr_graph_view, RRNodeId node_id) { auto node_type = rr_graph_view.node_type(node_id); - if (node_type == e_rr_type::CHANX || node_type == e_rr_type::CHANY) { + if (node_type == e_rr_type::CHANX || node_type == e_rr_type::CHANY || node_type == e_rr_type::MEDIUM) { return true; } else { int x_low = rr_graph_view.node_xlow(node_id); From 93aba7cd789ab927ac5925974c5ec6afa9f22427 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Tue, 20 May 2025 11:15:09 -0400 Subject: [PATCH 173/176] [Infra] Cleaned Up Header Files in Route Folder Continued the header file cleanup effort in the route folder. Some of these files may need to be revisited in more detail, but got some of the major header include issues. Found that some definitions were in the wrong place, so moved them to the correct implementation file. --- vpr/src/route/NestedNetlistRouter.h | 1 + vpr/src/route/SerialNetlistRouter.tpp | 2 + vpr/src/route/annotate_routing.cpp | 3 +- vpr/src/route/annotate_routing.h | 8 +- vpr/src/route/check_route.h | 4 +- vpr/src/route/connection_based_routing.h | 4 +- vpr/src/route/connection_router.h | 4 +- vpr/src/route/connection_router.tpp | 1 + vpr/src/route/connection_router_interface.h | 3 - vpr/src/route/edge_groups.cpp | 1 + vpr/src/route/edge_groups.h | 3 +- vpr/src/route/heap_type.h | 3 - vpr/src/route/netlist_routers.h | 4 +- vpr/src/route/overuse_report.cpp | 1 + vpr/src/route/overuse_report.h | 3 +- vpr/src/route/parallel_connection_router.cpp | 1 + vpr/src/route/parallel_connection_router.h | 1 - vpr/src/route/partition_tree.cpp | 2 + vpr/src/route/partition_tree.h | 7 +- vpr/src/route/route_budgets.cpp | 22 --- vpr/src/route/route_budgets.h | 2 +- vpr/src/route/route_common.cpp | 1 + vpr/src/route/route_common.h | 2 - vpr/src/route/route_export.h | 14 +- vpr/src/route/route_net.cpp | 130 +----------------- vpr/src/route/route_net.h | 10 -- vpr/src/route/route_net.tpp | 2 + vpr/src/route/route_path_manager.cpp | 2 +- vpr/src/route/route_path_manager.h | 8 +- vpr/src/route/route_tree.h | 3 - vpr/src/route/route_utilization.cpp | 2 + vpr/src/route/route_utilization.h | 6 +- vpr/src/route/route_utils.cpp | 133 +++++++++++++++++++ vpr/src/route/route_utils.h | 1 - vpr/src/route/router_delay_profiling.cpp | 1 - vpr/src/route/router_delay_profiling.h | 5 +- vpr/src/route/routing_predictor.cpp | 1 - vpr/src/route/segment_stats.cpp | 2 - vpr/src/route/segment_stats.h | 5 + vpr/src/route/serial_connection_router.cpp | 2 +- vpr/src/route/serial_connection_router.h | 2 - vpr/src/route/sink_sampling.h | 1 - vpr/src/route/spatial_route_tree_lookup.h | 2 + vpr/src/util/vpr_utils.h | 1 + 44 files changed, 196 insertions(+), 220 deletions(-) diff --git a/vpr/src/route/NestedNetlistRouter.h b/vpr/src/route/NestedNetlistRouter.h index e776d0a42da..87a3fdd880c 100644 --- a/vpr/src/route/NestedNetlistRouter.h +++ b/vpr/src/route/NestedNetlistRouter.h @@ -2,6 +2,7 @@ /** @file Nested parallel case for NetlistRouter */ #include "netlist_routers.h" +#include "partition_tree.h" #include "vtr_optional.h" #include "vtr_thread_pool.h" #include "serial_connection_router.h" diff --git a/vpr/src/route/SerialNetlistRouter.tpp b/vpr/src/route/SerialNetlistRouter.tpp index b84acfbd58f..ae7c8117db7 100644 --- a/vpr/src/route/SerialNetlistRouter.tpp +++ b/vpr/src/route/SerialNetlistRouter.tpp @@ -3,7 +3,9 @@ /** @file Templated implementations for SerialNetlistRouter */ #include "SerialNetlistRouter.h" +#include "partition_tree.h" #include "route_net.h" +#include "route_utils.h" #include "vtr_time.h" template diff --git a/vpr/src/route/annotate_routing.cpp b/vpr/src/route/annotate_routing.cpp index 71c78a2498c..4f3fdc4c52d 100644 --- a/vpr/src/route/annotate_routing.cpp +++ b/vpr/src/route/annotate_routing.cpp @@ -3,13 +3,12 @@ * from VPR to OpenFPGA. (i.e. create a mapping from RRNodeIds to ClusterNetIds) *******************************************************************/ +#include "describe_rr_node.h" #include "vpr_error.h" -#include "vtr_assert.h" #include "vtr_time.h" #include "vtr_log.h" #include "route_utils.h" -#include "rr_graph.h" #include "annotate_routing.h" diff --git a/vpr/src/route/annotate_routing.h b/vpr/src/route/annotate_routing.h index e00be549259..b4026562175 100644 --- a/vpr/src/route/annotate_routing.h +++ b/vpr/src/route/annotate_routing.h @@ -1,7 +1,13 @@ #ifndef ANNOTATE_ROUTING_H #define ANNOTATE_ROUTING_H -#include "vpr_context.h" +#include "clustered_netlist_fwd.h" +#include "rr_graph_fwd.h" +#include "vtr_vector.h" + +struct AtomContext; +struct ClusteringContext; +struct DeviceContext; /******************************************************************** * Create a mapping between each rr_node and its mapped nets diff --git a/vpr/src/route/check_route.h b/vpr/src/route/check_route.h index feff233156e..609a2fcb8d4 100644 --- a/vpr/src/route/check_route.h +++ b/vpr/src/route/check_route.h @@ -1,8 +1,8 @@ #ifndef VPR_CHECK_ROUTE_H #define VPR_CHECK_ROUTE_H -#include "physical_types.h" + +#include "netlist.h" #include "vpr_types.h" -#include "route_common.h" void check_route(const Netlist<>& net_list, enum e_route_type route_type, diff --git a/vpr/src/route/connection_based_routing.h b/vpr/src/route/connection_based_routing.h index 0f0faaaace5..2b7915bf6d5 100644 --- a/vpr/src/route/connection_based_routing.h +++ b/vpr/src/route/connection_based_routing.h @@ -1,10 +1,10 @@ #pragma once + #include #include -#include "route_tree_fwd.h" -#include "vpr_types.h" #include "timing_info.h" #include "vpr_net_pins_matrix.h" +#include "connection_based_routing_fwd.h" /***************** Connection based rerouting **********************/ // encompasses both incremental rerouting through route tree pruning diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/connection_router.h index f5bb7c57aa9..ad888834896 100644 --- a/vpr/src/route/connection_router.h +++ b/vpr/src/route/connection_router.h @@ -22,12 +22,12 @@ */ #include "connection_router_interface.h" +#include "globals.h" #include "rr_graph_storage.h" -#include "route_common.h" #include "router_lookahead.h" #include "route_tree.h" -#include "rr_rc_data.h" #include "router_stats.h" +#include "rr_graph_view.h" #include "spatial_route_tree_lookup.h" /** diff --git a/vpr/src/route/connection_router.tpp b/vpr/src/route/connection_router.tpp index f74b213235f..34774ccf9d5 100644 --- a/vpr/src/route/connection_router.tpp +++ b/vpr/src/route/connection_router.tpp @@ -4,6 +4,7 @@ #include #include "describe_rr_node.h" +#include "route_common.h" #include "rr_graph_fwd.h" #include "vpr_utils.h" diff --git a/vpr/src/route/connection_router_interface.h b/vpr/src/route/connection_router_interface.h index 178768bf5d5..c5b63e57fbf 100644 --- a/vpr/src/route/connection_router_interface.h +++ b/vpr/src/route/connection_router_interface.h @@ -1,9 +1,6 @@ #ifndef _CONNECTION_ROUTER_INTERFACE_H #define _CONNECTION_ROUTER_INTERFACE_H -#include - -#include "heap_type.h" #include "route_tree_fwd.h" #include "rr_graph_fwd.h" #include "vpr_types.h" diff --git a/vpr/src/route/edge_groups.cpp b/vpr/src/route/edge_groups.cpp index 6ca1e36692a..d23d4d248ee 100644 --- a/vpr/src/route/edge_groups.cpp +++ b/vpr/src/route/edge_groups.cpp @@ -2,6 +2,7 @@ #include #include "rr_graph_fwd.h" +#include "vpr_context.h" // Adds non-configurable (undirected) edge to be grouped. // diff --git a/vpr/src/route/edge_groups.h b/vpr/src/route/edge_groups.h index 90236ce3d65..a5521b6d2ec 100644 --- a/vpr/src/route/edge_groups.h +++ b/vpr/src/route/edge_groups.h @@ -7,7 +7,8 @@ #include #include "vpr_types.h" -#include "vpr_context.h" + +struct DeviceContext; // Class for identifying the components of a graph as sets of nodes. // Each node is reachable from any other node in the same set, and diff --git a/vpr/src/route/heap_type.h b/vpr/src/route/heap_type.h index dd722928bcc..6330fc4c0d9 100644 --- a/vpr/src/route/heap_type.h +++ b/vpr/src/route/heap_type.h @@ -2,10 +2,7 @@ #define _HEAP_TYPE_H #include -#include "physical_types.h" #include "device_grid.h" -#include "vtr_memory.h" -#include "vtr_array_view.h" #include "rr_graph_fwd.h" #include "route_path_manager.h" diff --git a/vpr/src/route/netlist_routers.h b/vpr/src/route/netlist_routers.h index eb8a220f51f..d4cb0a32840 100644 --- a/vpr/src/route/netlist_routers.h +++ b/vpr/src/route/netlist_routers.h @@ -19,13 +19,11 @@ #include "NetPinTimingInvalidator.h" #include "clustered_netlist_utils.h" #include "connection_based_routing_fwd.h" -#include "globals.h" +#include "d_ary_heap.h" #include "heap_type.h" #include "netlist_fwd.h" -#include "partition_tree.h" #include "routing_predictor.h" #include "route_budgets.h" -#include "route_utils.h" #include "router_stats.h" #include "timing_info.h" #include "vpr_net_pins_matrix.h" diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index c8c2b6135a4..25348e0f5fb 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -1,6 +1,7 @@ #include "overuse_report.h" #include +#include "globals.h" #include "physical_types_util.h" #include "vpr_utils.h" #include "vtr_log.h" diff --git a/vpr/src/route/overuse_report.h b/vpr/src/route/overuse_report.h index bae9da1d135..04b52f5846a 100644 --- a/vpr/src/route/overuse_report.h +++ b/vpr/src/route/overuse_report.h @@ -1,8 +1,7 @@ #pragma once -#include "rr_graph_storage.h" +#include "netlist.h" #include "rr_graph_view.h" -#include "globals.h" #include #include diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp index f3111f156f0..b8d97ceedf7 100644 --- a/vpr/src/route/parallel_connection_router.cpp +++ b/vpr/src/route/parallel_connection_router.cpp @@ -1,6 +1,7 @@ #include "parallel_connection_router.h" #include +#include "d_ary_heap.h" #include "route_tree.h" #include "rr_graph_fwd.h" diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h index 18d873e0c6e..b6db78a0d0f 100644 --- a/vpr/src/route/parallel_connection_router.h +++ b/vpr/src/route/parallel_connection_router.h @@ -3,7 +3,6 @@ #include "connection_router.h" -#include "d_ary_heap.h" #include "multi_queue_d_ary_heap.h" #include diff --git a/vpr/src/route/partition_tree.cpp b/vpr/src/route/partition_tree.cpp index 497f887cf74..7073db231be 100644 --- a/vpr/src/route/partition_tree.cpp +++ b/vpr/src/route/partition_tree.cpp @@ -1,7 +1,9 @@ #include "partition_tree.h" #include #include +#include #include +#include "globals.h" /** Minimum number of nets inside a partition to continue further partitioning. * Mostly an arbitrary limit. At a certain point, the quality lost due to disturbed net ordering diff --git a/vpr/src/route/partition_tree.h b/vpr/src/route/partition_tree.h index d30d5121492..229ba522152 100644 --- a/vpr/src/route/partition_tree.h +++ b/vpr/src/route/partition_tree.h @@ -1,13 +1,10 @@ #pragma once -#include "serial_connection_router.h" -#include "netlist_fwd.h" -#include "router_stats.h" +#include "netlist.h" +#include "vpr_types.h" #include -#include #include -#include #ifdef VPR_USE_TBB #include diff --git a/vpr/src/route/route_budgets.cpp b/vpr/src/route/route_budgets.cpp index 677450ee034..a223c5629c8 100644 --- a/vpr/src/route/route_budgets.cpp +++ b/vpr/src/route/route_budgets.cpp @@ -22,33 +22,11 @@ #include #include "vpr_error.h" #include "globals.h" -#include "tatum/util/tatum_assert.hpp" - -#include "tatum/timing_analyzers.hpp" -#include "tatum/graph_walkers.hpp" -#include "tatum/analyzer_factory.hpp" - -#include "tatum/TimingGraph.hpp" -#include "tatum/TimingConstraints.hpp" -#include "tatum/TimingReporter.hpp" -#include "tatum/timing_paths.hpp" - -#include "tatum/delay_calc/FixedDelayCalculator.hpp" - -#include "tatum/report/graphviz_dot_writer.hpp" -#include "tatum/base/sta_util.hpp" -#include "tatum/echo_writer.hpp" #include "tatum/TimingGraphFwd.hpp" -#include "slack_evaluation.h" #include "tatum/TimingGraphFwd.hpp" #include "vtr_assert.h" -#include "vtr_log.h" -#include "tatum/report/TimingPathFwd.hpp" -#include "tatum/base/TimingType.hpp" #include "concrete_timing_info.h" -#include "tatum/echo_writer.hpp" -#include "net_delay.h" #include "route_budgets.h" #include "vtr_time.h" diff --git a/vpr/src/route/route_budgets.h b/vpr/src/route/route_budgets.h index 7518027b85f..4d3e1fc03c4 100644 --- a/vpr/src/route/route_budgets.h +++ b/vpr/src/route/route_budgets.h @@ -4,10 +4,10 @@ #ifndef ROUTE_BUDGETS_H #define ROUTE_BUDGETS_H -#include #include #include #include "RoutingDelayCalculator.h" +#include "timing_info.h" enum analysis_type { SETUP, diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 3f6d574b601..7ead8f73cd5 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -7,6 +7,7 @@ #include "logic_types.h" #include "physical_types_util.h" #include "route_export.h" +#include "vpr_utils.h" #if defined(VPR_USE_TBB) #include diff --git a/vpr/src/route/route_common.h b/vpr/src/route/route_common.h index 1d6bfb58082..49ac82a690e 100644 --- a/vpr/src/route/route_common.h +++ b/vpr/src/route/route_common.h @@ -4,8 +4,6 @@ * router files and some used globally. */ #include -#include "clustered_netlist.h" -#include "rr_node_fwd.h" #include "router_stats.h" #include "globals.h" diff --git a/vpr/src/route/route_export.h b/vpr/src/route/route_export.h index 971aeba966b..b9c6a28620e 100644 --- a/vpr/src/route/route_export.h +++ b/vpr/src/route/route_export.h @@ -3,13 +3,13 @@ /** @file Function prototypes for functions in route_common.cpp that * are used outside the router modules. */ -#include - -#include "route_common.h" -#include "timing_info_fwd.h" -#include "vpr_types.h" - -#include "RoutingDelayCalculator.h" +#include +#include "clustered_netlist_fwd.h" +#include "netlist.h" +#include "route_tree.h" +#include "rr_graph_fwd.h" +#include "vtr_optional.h" +#include "vtr_vector.h" std::vector collect_congested_rr_nodes(); diff --git a/vpr/src/route/route_net.cpp b/vpr/src/route/route_net.cpp index 4d89ae04cfe..c2718fbf494 100644 --- a/vpr/src/route/route_net.cpp +++ b/vpr/src/route/route_net.cpp @@ -1,7 +1,7 @@ /** @file Impls for non-templated net routing fns & utils */ #include "route_net.h" -#include "stats.h" +#include "connection_based_routing.h" bool check_hold(const t_router_opts& router_opts, float worst_neg_slack) { if (router_opts.routing_budgets_algorithm != YOYO) { @@ -174,16 +174,6 @@ bool should_route_net(const Netlist<>& net_list, return true; } -bool early_exit_heuristic(const t_router_opts& router_opts, const WirelengthInfo& wirelength_info) { - if (wirelength_info.used_wirelength_ratio() > router_opts.init_wirelength_abort_threshold) { - VTR_LOG("Wire length usage ratio %g exceeds limit of %g, fail routing.\n", - wirelength_info.used_wirelength_ratio(), - router_opts.init_wirelength_abort_threshold); - return true; - } - return false; -} - float get_net_pin_criticality(const SetupHoldTimingInfo* timing_info, const ClusteredPinAtomPinsLookup& netlist_pin_lookup, float max_criticality, @@ -221,124 +211,6 @@ float get_net_pin_criticality(const SetupHoldTimingInfo* timing_info, return pin_criticality; } -size_t calculate_wirelength_available() { - auto& device_ctx = g_vpr_ctx.device(); - const auto& rr_graph = device_ctx.rr_graph; - - size_t available_wirelength = 0; - // But really what's happening is that this for loop iterates over every node and determines the available wirelength - for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { - const e_rr_type channel_type = rr_graph.node_type(rr_id); - if (channel_type == e_rr_type::CHANX || channel_type == e_rr_type::CHANY) { - available_wirelength += rr_graph.node_capacity(rr_id) * rr_graph.node_length(rr_id); - } - } - return available_wirelength; -} - -WirelengthInfo calculate_wirelength_info(const Netlist<>& net_list, size_t available_wirelength) { - size_t used_wirelength = 0; - VTR_ASSERT(available_wirelength > 0); - - auto& route_ctx = g_vpr_ctx.routing(); - -#ifdef VPR_USE_TBB - tbb::combinable thread_used_wirelength(0); - - tbb::parallel_for_each(net_list.nets().begin(), net_list.nets().end(), [&](ParentNetId net_id) { - if (!net_list.net_is_ignored(net_id) - && net_list.net_sinks(net_id).size() != 0 /* Globals don't count. */ - && route_ctx.route_trees[net_id]) { - int bends, wirelength, segments; - bool is_absorbed; - get_num_bends_and_length(net_id, &bends, &wirelength, &segments, &is_absorbed); - - thread_used_wirelength.local() += wirelength; - } - }); - - used_wirelength = thread_used_wirelength.combine(std::plus()); -#else - for (auto net_id : net_list.nets()) { - if (!net_list.net_is_ignored(net_id) - && net_list.net_sinks(net_id).size() != 0 /* Globals don't count. */ - && route_ctx.route_trees[net_id]) { - int bends = 0, wirelength = 0, segments = 0; - bool is_absorbed; - get_num_bends_and_length(net_id, &bends, &wirelength, &segments, &is_absorbed); - - used_wirelength += wirelength; - } - } -#endif - - return WirelengthInfo(available_wirelength, used_wirelength); -} - -t_bb calc_current_bb(const RouteTree& tree) { - auto& device_ctx = g_vpr_ctx.device(); - const auto& rr_graph = device_ctx.rr_graph; - auto& grid = device_ctx.grid; - - t_bb bb; - bb.xmin = grid.width() - 1; - bb.ymin = grid.height() - 1; - bb.layer_min = grid.get_num_layers() - 1; - bb.xmax = 0; - bb.ymax = 0; - bb.layer_max = 0; - - for (auto& rt_node : tree.all_nodes()) { - //The router interprets RR nodes which cross the boundary as being - //'within' of the BB. Only those which are *strictly* out side the - //box are excluded, hence we use the nodes xhigh/yhigh for xmin/xmax, - //and xlow/ylow for xmax/ymax calculations - bb.xmin = std::min(bb.xmin, rr_graph.node_xhigh(rt_node.inode)); - bb.ymin = std::min(bb.ymin, rr_graph.node_yhigh(rt_node.inode)); - bb.layer_min = std::min(bb.layer_min, rr_graph.node_layer(rt_node.inode)); - bb.xmax = std::max(bb.xmax, rr_graph.node_xlow(rt_node.inode)); - bb.ymax = std::max(bb.ymax, rr_graph.node_ylow(rt_node.inode)); - bb.layer_max = std::max(bb.layer_max, rr_graph.node_layer(rt_node.inode)); - } - - VTR_ASSERT(bb.xmin <= bb.xmax); - VTR_ASSERT(bb.ymin <= bb.ymax); - - return bb; -} - -// Initializes net_delay based on best-case delay estimates from the router lookahead -void init_net_delay_from_lookahead(const RouterLookahead& router_lookahead, - const Netlist<>& net_list, - const vtr::vector>& net_rr_terminals, - NetPinsMatrix& net_delay, - const RRGraphView& rr_graph, - bool is_flat) { - t_conn_cost_params cost_params; - cost_params.criticality = 1.; // Ensures lookahead returns delay value - - for (auto net_id : net_list.nets()) { - if (net_list.net_is_ignored(net_id)) continue; - - RRNodeId source_rr = net_rr_terminals[net_id][0]; - - for (size_t ipin = 1; ipin < net_list.net_pins(net_id).size(); ++ipin) { - RRNodeId sink_rr = net_rr_terminals[net_id][ipin]; - - float est_delay = get_cost_from_lookahead(router_lookahead, - rr_graph, - source_rr, - sink_rr, - 0., - cost_params, - is_flat); - VTR_ASSERT(std::isfinite(est_delay) && est_delay < std::numeric_limits::max()); - - net_delay[net_id][ipin] = est_delay; - } - } -} - void update_net_delays_from_route_tree(float* net_delay, const Netlist<>& net_list, ParentNetId inet, diff --git a/vpr/src/route/route_net.h b/vpr/src/route/route_net.h index f996be8b64c..e03b010c5ec 100644 --- a/vpr/src/route/route_net.h +++ b/vpr/src/route/route_net.h @@ -2,20 +2,10 @@ /** @file Net and sink routing functions, and other utils used by them. */ -#include #include -#include "connection_based_routing.h" -#include "connection_router_interface.h" -#include "heap_type.h" #include "netlist.h" #include "route_budgets.h" -#include "route_utils.h" -#include "router_stats.h" -#include "router_lookahead.h" -#include "routing_predictor.h" -#include "rr_graph_type.h" -#include "spatial_route_tree_lookup.h" #include "timing_info_fwd.h" #include "vpr_types.h" #include "vpr_utils.h" diff --git a/vpr/src/route/route_net.tpp b/vpr/src/route/route_net.tpp index 1a5715b7341..dc1cc75dab4 100644 --- a/vpr/src/route/route_net.tpp +++ b/vpr/src/route/route_net.tpp @@ -6,12 +6,14 @@ #include +#include "connection_based_routing.h" #include "connection_router_interface.h" #include "describe_rr_node.h" #include "draw.h" #include "route_common.h" #include "route_debug.h" #include "route_profiling.h" +#include "routing_predictor.h" #include "rr_graph_fwd.h" #include "vtr_dynamic_bitset.h" diff --git a/vpr/src/route/route_path_manager.cpp b/vpr/src/route/route_path_manager.cpp index 03dec823993..58aa565aee5 100644 --- a/vpr/src/route/route_path_manager.cpp +++ b/vpr/src/route/route_path_manager.cpp @@ -1,5 +1,5 @@ #include "route_path_manager.h" -#include "globals.h" +#include "vpr_context.h" PathManager::PathManager() { // Only init data structure if required by RCV diff --git a/vpr/src/route/route_path_manager.h b/vpr/src/route/route_path_manager.h index f1673772193..f46ca565088 100644 --- a/vpr/src/route/route_path_manager.h +++ b/vpr/src/route/route_path_manager.h @@ -1,13 +1,11 @@ +#ifndef _PATH_MANAGER_H +#define _PATH_MANAGER_H + #include "rr_graph_fwd.h" -#include "vtr_assert.h" #include -#include #include -#ifndef _PATH_MANAGER_H -#define _PATH_MANAGER_H - /* Extra path data needed by RCV, separated from RTExploredNode struct for performance reasons * Can be accessed by a pointer, won't be initialized unless by RCV * Use PathManager class to handle this structure's allocation and deallocation diff --git a/vpr/src/route/route_tree.h b/vpr/src/route/route_tree.h index 37e89db16ae..36b5dcabfac 100644 --- a/vpr/src/route/route_tree.h +++ b/vpr/src/route/route_tree.h @@ -81,19 +81,16 @@ */ #include -#include #include #include #include #include "connection_based_routing_fwd.h" #include "route_tree_fwd.h" -#include "vtr_assert.h" #include "spatial_route_tree_lookup.h" #include "vtr_dynamic_bitset.h" #include "vtr_optional.h" #include "vtr_range.h" -#include "vtr_vec_id_set.h" /** * @brief A single route tree node diff --git a/vpr/src/route/route_utilization.cpp b/vpr/src/route/route_utilization.cpp index bb9c5e736e3..e4bb2df36af 100644 --- a/vpr/src/route/route_utilization.cpp +++ b/vpr/src/route/route_utilization.cpp @@ -1,4 +1,6 @@ #include "route_utilization.h" +#include "draw_global.h" +#include "draw_types.h" #include "globals.h" #include "vpr_utils.h" diff --git a/vpr/src/route/route_utilization.h b/vpr/src/route/route_utilization.h index 194df6deb14..d9d3f45af14 100644 --- a/vpr/src/route/route_utilization.h +++ b/vpr/src/route/route_utilization.h @@ -1,8 +1,8 @@ #ifndef VPR_ROUTE_UTIL_H #define VPR_ROUTE_UTIL_H -#include "vpr_types.h" -#include "draw_types.h" -#include "draw_global.h" + +#include "rr_node_types.h" +#include "vtr_ndmatrix.h" vtr::Matrix calculate_routing_avail(e_rr_type rr_type); diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index 198d64197e7..c152a332d41 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -12,12 +12,17 @@ #include "overuse_report.h" #include "physical_types_util.h" #include "place_and_route.h" +#include "route_common.h" #include "route_debug.h" #include "VprTimingGraphResolver.h" #include "rr_graph.h" #include "tatum/TimingReporter.hpp" +#ifdef VPR_USE_TBB +#include "stats.h" +#endif // VPR_USE_TBB + bool check_net_delays(const Netlist<>& net_list, NetPinsMatrix& net_delay) { constexpr float ERROR_TOL = 0.0001; @@ -504,6 +509,134 @@ void try_graph(int width_fac, is_flat); } +bool early_exit_heuristic(const t_router_opts& router_opts, const WirelengthInfo& wirelength_info) { + if (wirelength_info.used_wirelength_ratio() > router_opts.init_wirelength_abort_threshold) { + VTR_LOG("Wire length usage ratio %g exceeds limit of %g, fail routing.\n", + wirelength_info.used_wirelength_ratio(), + router_opts.init_wirelength_abort_threshold); + return true; + } + return false; +} + +size_t calculate_wirelength_available() { + auto& device_ctx = g_vpr_ctx.device(); + const auto& rr_graph = device_ctx.rr_graph; + + size_t available_wirelength = 0; + // But really what's happening is that this for loop iterates over every node and determines the available wirelength + for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { + const e_rr_type channel_type = rr_graph.node_type(rr_id); + if (channel_type == e_rr_type::CHANX || channel_type == e_rr_type::CHANY) { + available_wirelength += rr_graph.node_capacity(rr_id) * rr_graph.node_length(rr_id); + } + } + return available_wirelength; +} + +WirelengthInfo calculate_wirelength_info(const Netlist<>& net_list, size_t available_wirelength) { + size_t used_wirelength = 0; + VTR_ASSERT(available_wirelength > 0); + + auto& route_ctx = g_vpr_ctx.routing(); + +#ifdef VPR_USE_TBB + tbb::combinable thread_used_wirelength(0); + + tbb::parallel_for_each(net_list.nets().begin(), net_list.nets().end(), [&](ParentNetId net_id) { + if (!net_list.net_is_ignored(net_id) + && net_list.net_sinks(net_id).size() != 0 /* Globals don't count. */ + && route_ctx.route_trees[net_id]) { + int bends, wirelength, segments; + bool is_absorbed; + get_num_bends_and_length(net_id, &bends, &wirelength, &segments, &is_absorbed); + + thread_used_wirelength.local() += wirelength; + } + }); + + used_wirelength = thread_used_wirelength.combine(std::plus()); +#else + for (auto net_id : net_list.nets()) { + if (!net_list.net_is_ignored(net_id) + && net_list.net_sinks(net_id).size() != 0 /* Globals don't count. */ + && route_ctx.route_trees[net_id]) { + int bends = 0, wirelength = 0, segments = 0; + bool is_absorbed; + get_num_bends_and_length(net_id, &bends, &wirelength, &segments, &is_absorbed); + + used_wirelength += wirelength; + } + } +#endif + + return WirelengthInfo(available_wirelength, used_wirelength); +} + +t_bb calc_current_bb(const RouteTree& tree) { + auto& device_ctx = g_vpr_ctx.device(); + const auto& rr_graph = device_ctx.rr_graph; + auto& grid = device_ctx.grid; + + t_bb bb; + bb.xmin = grid.width() - 1; + bb.ymin = grid.height() - 1; + bb.layer_min = grid.get_num_layers() - 1; + bb.xmax = 0; + bb.ymax = 0; + bb.layer_max = 0; + + for (auto& rt_node : tree.all_nodes()) { + //The router interprets RR nodes which cross the boundary as being + //'within' of the BB. Only those which are *strictly* out side the + //box are excluded, hence we use the nodes xhigh/yhigh for xmin/xmax, + //and xlow/ylow for xmax/ymax calculations + bb.xmin = std::min(bb.xmin, rr_graph.node_xhigh(rt_node.inode)); + bb.ymin = std::min(bb.ymin, rr_graph.node_yhigh(rt_node.inode)); + bb.layer_min = std::min(bb.layer_min, rr_graph.node_layer(rt_node.inode)); + bb.xmax = std::max(bb.xmax, rr_graph.node_xlow(rt_node.inode)); + bb.ymax = std::max(bb.ymax, rr_graph.node_ylow(rt_node.inode)); + bb.layer_max = std::max(bb.layer_max, rr_graph.node_layer(rt_node.inode)); + } + + VTR_ASSERT(bb.xmin <= bb.xmax); + VTR_ASSERT(bb.ymin <= bb.ymax); + + return bb; +} + +// Initializes net_delay based on best-case delay estimates from the router lookahead +void init_net_delay_from_lookahead(const RouterLookahead& router_lookahead, + const Netlist<>& net_list, + const vtr::vector>& net_rr_terminals, + NetPinsMatrix& net_delay, + const RRGraphView& rr_graph, + bool is_flat) { + t_conn_cost_params cost_params; + cost_params.criticality = 1.; // Ensures lookahead returns delay value + + for (auto net_id : net_list.nets()) { + if (net_list.net_is_ignored(net_id)) continue; + + RRNodeId source_rr = net_rr_terminals[net_id][0]; + + for (size_t ipin = 1; ipin < net_list.net_pins(net_id).size(); ++ipin) { + RRNodeId sink_rr = net_rr_terminals[net_id][ipin]; + + float est_delay = get_cost_from_lookahead(router_lookahead, + rr_graph, + source_rr, + sink_rr, + 0., + cost_params, + is_flat); + VTR_ASSERT(std::isfinite(est_delay) && est_delay < std::numeric_limits::max()); + + net_delay[net_id][ipin] = est_delay; + } + } +} + #ifndef NO_GRAPHICS void update_draw_pres_fac(const float new_pres_fac) { #else diff --git a/vpr/src/route/route_utils.h b/vpr/src/route/route_utils.h index 5cac4fbb045..71e3dc895dd 100644 --- a/vpr/src/route/route_utils.h +++ b/vpr/src/route/route_utils.h @@ -6,7 +6,6 @@ #include "router_stats.h" #include "timing_info.h" #include "vpr_net_pins_matrix.h" -#include "vpr_types.h" #include "RoutingDelayCalculator.h" diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index 28c553c5d8f..c85c97ff4ab 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -5,7 +5,6 @@ #include "route_export.h" #include "route_tree.h" #include "rr_graph.h" -#include "vtr_time.h" RouterDelayProfiler::RouterDelayProfiler(const Netlist<>& net_list, const RouterLookahead* lookahead, diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h index 082349a9a07..abdc402a7ff 100644 --- a/vpr/src/route/router_delay_profiling.h +++ b/vpr/src/route/router_delay_profiling.h @@ -1,7 +1,10 @@ #ifndef ROUTER_DELAY_PROFILING_H_ #define ROUTER_DELAY_PROFILING_H_ -#include "vpr_types.h" +#include "d_ary_heap.h" +#include "netlist.h" +#include "router_lookahead.h" +#include "router_stats.h" #include "serial_connection_router.h" #include diff --git a/vpr/src/route/routing_predictor.cpp b/vpr/src/route/routing_predictor.cpp index 4f0f69a28a0..4b8e156d52c 100644 --- a/vpr/src/route/routing_predictor.cpp +++ b/vpr/src/route/routing_predictor.cpp @@ -1,7 +1,6 @@ #include #include #include -#include #include "vtr_assert.h" diff --git a/vpr/src/route/segment_stats.cpp b/vpr/src/route/segment_stats.cpp index 3d7de733ce3..968a12d0c6d 100644 --- a/vpr/src/route/segment_stats.cpp +++ b/vpr/src/route/segment_stats.cpp @@ -1,8 +1,6 @@ #include "vtr_log.h" -#include "vtr_memory.h" -#include "vpr_types.h" #include "globals.h" #include "segment_stats.h" diff --git a/vpr/src/route/segment_stats.h b/vpr/src/route/segment_stats.h index 346355c168a..a040ab08b0d 100644 --- a/vpr/src/route/segment_stats.h +++ b/vpr/src/route/segment_stats.h @@ -1 +1,6 @@ +#pragma once + +#include +#include "physical_types.h" + void get_segment_usage_stats(std::vector& segment_inf); diff --git a/vpr/src/route/serial_connection_router.cpp b/vpr/src/route/serial_connection_router.cpp index 3bb2d2b64a2..4a5c074970c 100644 --- a/vpr/src/route/serial_connection_router.cpp +++ b/vpr/src/route/serial_connection_router.cpp @@ -1,7 +1,7 @@ #include "serial_connection_router.h" #include -#include "rr_graph.h" +#include "d_ary_heap.h" #include "rr_graph_fwd.h" /** Used to update router statistics for serial connection router */ diff --git a/vpr/src/route/serial_connection_router.h b/vpr/src/route/serial_connection_router.h index 2cd23f1460e..990c93c29fb 100644 --- a/vpr/src/route/serial_connection_router.h +++ b/vpr/src/route/serial_connection_router.h @@ -3,8 +3,6 @@ #include "connection_router.h" -#include "d_ary_heap.h" - /** * @class SerialConnectionRouter implements the AIR's serial timing-driven connection router * @details This class routes from some initial set of sources (via the input rt tree) to a diff --git a/vpr/src/route/sink_sampling.h b/vpr/src/route/sink_sampling.h index 341a292db7f..6277d554075 100644 --- a/vpr/src/route/sink_sampling.h +++ b/vpr/src/route/sink_sampling.h @@ -14,7 +14,6 @@ #include "globals.h" #include "partition_tree.h" #include "route_common.h" -#include "router_lookahead_sampling.h" /** Sink container for geometry operations */ struct SinkPoint { diff --git a/vpr/src/route/spatial_route_tree_lookup.h b/vpr/src/route/spatial_route_tree_lookup.h index 9ac1ac3c23f..15e165aedd3 100644 --- a/vpr/src/route/spatial_route_tree_lookup.h +++ b/vpr/src/route/spatial_route_tree_lookup.h @@ -1,5 +1,6 @@ #ifndef VPR_SPATIAL_ROUTE_TREE_LOOKUP_H #define VPR_SPATIAL_ROUTE_TREE_LOOKUP_H + #include #include "vpr_types.h" @@ -7,6 +8,7 @@ #include "netlist.h" #include "route_tree_fwd.h" +#include "vtr_vector.h" typedef vtr::Matrix>> SpatialRouteTreeLookup; diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index b6828859bd9..4ec2c860953 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -7,6 +7,7 @@ #include "vpr_types.h" #include "vtr_vector.h" #include "atom_pb_bimap.h" +#include #include #include From 5a141a06037dec503c0916654aed5de533855818 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Tue, 20 May 2025 12:49:37 -0400 Subject: [PATCH 174/176] [Infra] Updated Header Files Based on Comments Moved to pragma once symantics and cleaned up some less than ideal code. --- vpr/src/route/multi_queue_d_ary_heap.h | 5 +---- vpr/src/route/route_path_manager.h | 5 +---- vpr/src/route/route_utilization.h | 5 +---- vpr/src/route/route_utils.cpp | 9 +++++---- vpr/src/route/router_delay_profiling.h | 5 +---- vpr/src/route/spatial_route_tree_lookup.h | 5 +---- 6 files changed, 10 insertions(+), 24 deletions(-) diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h index 5a49dadae50..c5f43e5aa3c 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.h +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -17,8 +17,7 @@ * Modified: February 2025 ********************************************************************/ -#ifndef _MULTI_QUEUE_D_ARY_HEAP_H -#define _MULTI_QUEUE_D_ARY_HEAP_H +#pragma once #include "device_grid.h" #include "heap_type.h" @@ -129,5 +128,3 @@ class MultiQueueDAryHeap { private: std::unique_ptr pq_; }; - -#endif diff --git a/vpr/src/route/route_path_manager.h b/vpr/src/route/route_path_manager.h index f46ca565088..30377805f03 100644 --- a/vpr/src/route/route_path_manager.h +++ b/vpr/src/route/route_path_manager.h @@ -1,5 +1,4 @@ -#ifndef _PATH_MANAGER_H -#define _PATH_MANAGER_H +#pragma once #include "rr_graph_fwd.h" @@ -113,5 +112,3 @@ class PathManager { // Required by RCV so the router doesn't expand already visited nodes std::set route_tree_nodes_; }; - -#endif diff --git a/vpr/src/route/route_utilization.h b/vpr/src/route/route_utilization.h index d9d3f45af14..228ac842c85 100644 --- a/vpr/src/route/route_utilization.h +++ b/vpr/src/route/route_utilization.h @@ -1,5 +1,4 @@ -#ifndef VPR_ROUTE_UTIL_H -#define VPR_ROUTE_UTIL_H +#pragma once #include "rr_node_types.h" #include "vtr_ndmatrix.h" @@ -17,5 +16,3 @@ vtr::Matrix calculate_routing_avail(e_rr_type rr_type); */ vtr::Matrix calculate_routing_usage(e_rr_type rr_type, bool is_flat, bool is_print); float routing_util(float used, float avail); - -#endif diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index c152a332d41..d61b6bb56c9 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -16,6 +16,7 @@ #include "route_debug.h" #include "VprTimingGraphResolver.h" +#include "route_tree.h" #include "rr_graph.h" #include "tatum/TimingReporter.hpp" @@ -525,7 +526,7 @@ size_t calculate_wirelength_available() { size_t available_wirelength = 0; // But really what's happening is that this for loop iterates over every node and determines the available wirelength - for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { + for (RRNodeId rr_id : device_ctx.rr_graph.nodes()) { const e_rr_type channel_type = rr_graph.node_type(rr_id); if (channel_type == e_rr_type::CHANX || channel_type == e_rr_type::CHANY) { available_wirelength += rr_graph.node_capacity(rr_id) * rr_graph.node_length(rr_id); @@ -586,7 +587,7 @@ t_bb calc_current_bb(const RouteTree& tree) { bb.ymax = 0; bb.layer_max = 0; - for (auto& rt_node : tree.all_nodes()) { + for (const RouteTreeNode& rt_node : tree.all_nodes()) { //The router interprets RR nodes which cross the boundary as being //'within' of the BB. Only those which are *strictly* out side the //box are excluded, hence we use the nodes xhigh/yhigh for xmin/xmax, @@ -615,7 +616,7 @@ void init_net_delay_from_lookahead(const RouterLookahead& router_lookahead, t_conn_cost_params cost_params; cost_params.criticality = 1.; // Ensures lookahead returns delay value - for (auto net_id : net_list.nets()) { + for (ParentNetId net_id : net_list.nets()) { if (net_list.net_is_ignored(net_id)) continue; RRNodeId source_rr = net_rr_terminals[net_id][0]; @@ -627,7 +628,7 @@ void init_net_delay_from_lookahead(const RouterLookahead& router_lookahead, rr_graph, source_rr, sink_rr, - 0., + 0.0f /* R_upstream */, cost_params, is_flat); VTR_ASSERT(std::isfinite(est_delay) && est_delay < std::numeric_limits::max()); diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h index abdc402a7ff..e03d62abbd9 100644 --- a/vpr/src/route/router_delay_profiling.h +++ b/vpr/src/route/router_delay_profiling.h @@ -1,5 +1,4 @@ -#ifndef ROUTER_DELAY_PROFILING_H_ -#define ROUTER_DELAY_PROFILING_H_ +#pragma once #include "d_ary_heap.h" #include "netlist.h" @@ -63,5 +62,3 @@ void alloc_routing_structs(const t_chan_width& chan_width, bool is_flat); void free_routing_structs(); - -#endif /* ROUTER_DELAY_PROFILING_H_ */ diff --git a/vpr/src/route/spatial_route_tree_lookup.h b/vpr/src/route/spatial_route_tree_lookup.h index 15e165aedd3..1766f972c58 100644 --- a/vpr/src/route/spatial_route_tree_lookup.h +++ b/vpr/src/route/spatial_route_tree_lookup.h @@ -1,5 +1,4 @@ -#ifndef VPR_SPATIAL_ROUTE_TREE_LOOKUP_H -#define VPR_SPATIAL_ROUTE_TREE_LOOKUP_H +#pragma once #include @@ -23,5 +22,3 @@ size_t grid_to_bin_x(size_t grid_x, const SpatialRouteTreeLookup& spatial_lookup size_t grid_to_bin_y(size_t grid_y, const SpatialRouteTreeLookup& spatial_lookup); bool validate_route_tree_spatial_lookup(const RouteTreeNode& rt_node, const SpatialRouteTreeLookup& spatial_lookup); - -#endif From b83dd94202cd52d118218a296e4113293691c9e4 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 20 May 2025 15:40:18 -0400 Subject: [PATCH 175/176] [vpr][tileable] use is_io in t_physcial_tile --- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 887b876defd..68bee2bbebf 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -48,7 +48,7 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, std::vector io_side = {TOP, RIGHT, BOTTOM, LEFT}; /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids.get_physical_type(tile_loc))) { + if (grids.get_physical_type(tile_loc)->is_io()) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); vtr::Point grid_coordinate(ix, iy); io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb); @@ -745,7 +745,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, std::vector wanted_sides{TOP, RIGHT, BOTTOM, LEFT}; /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids.get_physical_type(tile_loc))) { + if (grids.get_physical_type(tile_loc)->is_io()) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); wanted_sides = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb); } From c3cf08b149e7e6616c32d6229e96adf2c38d7552 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Tue, 20 May 2025 18:19:24 -0400 Subject: [PATCH 176/176] [vpr][route] update rr node indices to include medium type --- vpr/src/route/rr_graph_generation/rr_node_indices.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp index 99c1a729e6c..5fed7376669 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -517,8 +517,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, y, describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } - } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { - // Sources have co-ordinates covering the entire block they are in, but not sinks + } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK || rr_graph.node_type(inode) == e_rr_type::MEDIUM) { if (!rr_graph.x_in_node_range(x, inode)) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", rr_graph.node_xlow(inode),