diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index ea72d18c6e..031ab0b4ac 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -162,10 +162,6 @@ void free_arch(t_arch* arch) { vtr::free(arch->architecture_id); - if (arch->clocks) { - vtr::free(arch->clocks->clock_inf); - } - delete (arch->noc); } @@ -309,8 +305,7 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) { static void free_pb_type(t_pb_type* pb_type) { vtr::free(pb_type->name); - if (pb_type->blif_model) - vtr::free(pb_type->blif_model); + vtr::free(pb_type->blif_model); for (int i = 0; i < pb_type->num_modes; ++i) { for (int j = 0; j < pb_type->modes[i].num_pb_type_children; ++j) { @@ -324,66 +319,34 @@ static void free_pb_type(t_pb_type* pb_type) { vtr::free(pb_type->modes[i].interconnect[j].name); for (int k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; ++k) { - if (pb_type->modes[i].interconnect[j].annotations[k].clock) - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].clock); - if (pb_type->modes[i].interconnect[j].annotations[k].input_pins) { - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].input_pins); - } - if (pb_type->modes[i].interconnect[j].annotations[k].output_pins) { - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].output_pins); - } - for (int m = 0; m < pb_type->modes[i].interconnect[j].annotations[k].num_value_prop_pairs; ++m) { - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]); - } - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].prop); - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value); + vtr::free(pb_type->modes[i].interconnect[j].annotations[k].clock); + vtr::free(pb_type->modes[i].interconnect[j].annotations[k].input_pins); + vtr::free(pb_type->modes[i].interconnect[j].annotations[k].output_pins); } - vtr::free(pb_type->modes[i].interconnect[j].annotations); - if (pb_type->modes[i].interconnect[j].interconnect_power) - vtr::free(pb_type->modes[i].interconnect[j].interconnect_power); + delete[] pb_type->modes[i].interconnect[j].annotations; + delete pb_type->modes[i].interconnect[j].interconnect_power; } - if (pb_type->modes[i].interconnect) - delete[] pb_type->modes[i].interconnect; - if (pb_type->modes[i].mode_power) - vtr::free(pb_type->modes[i].mode_power); + delete[] pb_type->modes[i].interconnect; + delete (pb_type->modes[i].mode_power); } - if (pb_type->modes) - delete[] pb_type->modes; + + delete[] pb_type->modes; for (int i = 0; i < pb_type->num_annotations; ++i) { - for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) { - vtr::free(pb_type->annotations[i].value[j]); - } - vtr::free(pb_type->annotations[i].value); - vtr::free(pb_type->annotations[i].prop); - if (pb_type->annotations[i].input_pins) { - vtr::free(pb_type->annotations[i].input_pins); - } - if (pb_type->annotations[i].output_pins) { - vtr::free(pb_type->annotations[i].output_pins); - } - if (pb_type->annotations[i].clock) { - vtr::free(pb_type->annotations[i].clock); - } - } - if (pb_type->num_annotations > 0) { - vtr::free(pb_type->annotations); + vtr::free(pb_type->annotations[i].input_pins); + vtr::free(pb_type->annotations[i].output_pins); + vtr::free(pb_type->annotations[i].clock); } + delete[] pb_type->annotations; - if (pb_type->pb_type_power) { - vtr::free(pb_type->pb_type_power); - } + delete pb_type->pb_type_power; for (int i = 0; i < pb_type->num_ports; ++i) { vtr::free(pb_type->ports[i].name); - if (pb_type->ports[i].port_class) { - vtr::free(pb_type->ports[i].port_class); - } - if (pb_type->ports[i].port_power) { - vtr::free(pb_type->ports[i].port_power); - } + vtr::free(pb_type->ports[i].port_class); + delete pb_type->ports[i].port_power; } - vtr::free(pb_type->ports); + delete[] pb_type->ports; } t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, int* low_index) { @@ -476,7 +439,7 @@ std::unordered_set get_equivalent_sites_set(t_physical void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, char* new_name, t_pb_type* copy) { - int i, j; + int i; char* dot; VTR_ASSERT(pb_type->blif_model != nullptr); @@ -495,13 +458,12 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->num_pb = 1; /* Power */ - copy->pb_type_power = (t_pb_type_power*)vtr::calloc(1, - sizeof(t_pb_type_power)); + copy->pb_type_power = new t_pb_type_power(); copy->pb_type_power->estimation_method = power_method_inherited(pb_type->pb_type_power->estimation_method); /* Ports */ copy->num_ports = pb_type->num_ports; - copy->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port)); + copy->ports = new t_port[pb_type->num_ports](); for (i = 0; i < pb_type->num_ports; i++) { copy->ports[i].is_clock = pb_type->ports[i].is_clock; copy->ports[i].model_port = pb_type->ports[i].model_port; @@ -514,8 +476,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->ports[i].index = pb_type->ports[i].index; copy->ports[i].absolute_first_pin_index = pb_type->ports[i].absolute_first_pin_index; - copy->ports[i].port_power = (t_port_power*)vtr::calloc(1, - sizeof(t_port_power)); + copy->ports[i].port_power = new t_port_power(); //Defaults if (copy->pb_type_power->estimation_method == POWER_METHOD_AUTO_SIZES) { copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_AUTO; @@ -527,7 +488,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, } } - copy->annotations = (t_pin_to_pin_annotation*)vtr::calloc(pb_type->num_annotations, sizeof(t_pin_to_pin_annotation)); + copy->annotations = new t_pin_to_pin_annotation[pb_type->num_annotations](); copy->num_annotations = pb_type->num_annotations; for (i = 0; i < copy->num_annotations; i++) { copy->annotations[i].clock = vtr::strdup(pb_type->annotations[i].clock); @@ -548,13 +509,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->annotations[i].line_num = pb_type->annotations[i].line_num; copy->annotations[i].format = pb_type->annotations[i].format; copy->annotations[i].type = pb_type->annotations[i].type; - copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs; - copy->annotations[i].prop = (int*)vtr::malloc(sizeof(int) * pb_type->annotations[i].num_value_prop_pairs); - copy->annotations[i].value = (char**)vtr::malloc(sizeof(char*) * pb_type->annotations[i].num_value_prop_pairs); - for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) { - copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j]; - copy->annotations[i].value[j] = vtr::strdup(pb_type->annotations[i].value[j]); - } + copy->annotations[i].annotation_entries = pb_type->annotations[i].annotation_entries; } } @@ -563,7 +518,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { char* default_name; t_port* in_port; t_port* out_port; - int i, j; + int i; if (strcmp(lut_pb_type->name, "lut") != 0) { default_name = vtr::strdup("lut"); @@ -580,8 +535,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].parent_pb_type = lut_pb_type; lut_pb_type->modes[0].index = 0; lut_pb_type->modes[0].num_pb_type_children = 0; - lut_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1, - sizeof(t_mode_power)); + lut_pb_type->modes[0].mode_power = new t_mode_power(); /* Process interconnect */ /* TODO: add timing annotations to route-through */ @@ -613,10 +567,9 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0; lut_pb_type->modes[0].interconnect[0].parent_mode = &lut_pb_type->modes[0]; - lut_pb_type->modes[0].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power)); + lut_pb_type->modes[0].interconnect[0].interconnect_power = new t_interconnect_power(); - lut_pb_type->modes[0].interconnect[0].annotations = (t_pin_to_pin_annotation*)vtr::calloc(lut_pb_type->num_annotations, - sizeof(t_pin_to_pin_annotation)); + lut_pb_type->modes[0].interconnect[0].annotations = new t_pin_to_pin_annotation[lut_pb_type->num_annotations](); lut_pb_type->modes[0].interconnect[0].num_annotations = lut_pb_type->num_annotations; for (i = 0; i < lut_pb_type->modes[0].interconnect[0].num_annotations; i++) { @@ -626,15 +579,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].interconnect[0].annotations[i].line_num = lut_pb_type->annotations[i].line_num; lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format; lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type; - lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs; - lut_pb_type->modes[0].interconnect[0].annotations[i].prop = (int*)vtr::malloc(sizeof(int) - * lut_pb_type->annotations[i].num_value_prop_pairs); - lut_pb_type->modes[0].interconnect[0].annotations[i].value = (char**)vtr::malloc(sizeof(char*) - * lut_pb_type->annotations[i].num_value_prop_pairs); - for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { - lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j]; - lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]); - } + + lut_pb_type->modes[0].interconnect[0].annotations[i].annotation_entries = lut_pb_type->annotations[i].annotation_entries; } /* Second mode, LUT */ @@ -643,30 +589,18 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].parent_pb_type = lut_pb_type; lut_pb_type->modes[1].index = 1; lut_pb_type->modes[1].num_pb_type_children = 1; - lut_pb_type->modes[1].mode_power = (t_mode_power*)vtr::calloc(1, - sizeof(t_mode_power)); + lut_pb_type->modes[1].mode_power = new t_mode_power(); lut_pb_type->modes[1].pb_type_children = new t_pb_type[1]; alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name, lut_pb_type->modes[1].pb_type_children); /* moved annotations to child so delete old annotations */ for (i = 0; i < lut_pb_type->num_annotations; i++) { - for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { - free(lut_pb_type->annotations[i].value[j]); - } - free(lut_pb_type->annotations[i].value); - free(lut_pb_type->annotations[i].prop); - if (lut_pb_type->annotations[i].input_pins) { - free(lut_pb_type->annotations[i].input_pins); - } - if (lut_pb_type->annotations[i].output_pins) { - free(lut_pb_type->annotations[i].output_pins); - } - if (lut_pb_type->annotations[i].clock) { - free(lut_pb_type->annotations[i].clock); - } + vtr::free(lut_pb_type->annotations[i].input_pins); + vtr::free(lut_pb_type->annotations[i].output_pins); + vtr::free(lut_pb_type->annotations[i].clock); } lut_pb_type->num_annotations = 0; - free(lut_pb_type->annotations); + delete[] lut_pb_type->annotations; lut_pb_type->annotations = nullptr; lut_pb_type->modes[1].pb_type_children[0].depth = lut_pb_type->depth + 1; lut_pb_type->modes[1].pb_type_children[0].parent_mode = &lut_pb_type->modes[1]; @@ -694,7 +628,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].interconnect[0].parent_mode_index = 1; lut_pb_type->modes[1].interconnect[0].parent_mode = &lut_pb_type->modes[1]; - lut_pb_type->modes[1].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power)); + lut_pb_type->modes[1].interconnect[0].interconnect_power = new t_interconnect_power(); lut_pb_type->modes[1].interconnect[1].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 11, sizeof(char)); sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s", @@ -713,7 +647,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].interconnect[1].parent_mode_index = 1; lut_pb_type->modes[1].interconnect[1].parent_mode = &lut_pb_type->modes[1]; - lut_pb_type->modes[1].interconnect[1].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power)); + lut_pb_type->modes[1].interconnect[1].interconnect_power = new t_interconnect_power(); free(default_name); @@ -738,8 +672,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { mem_pb_type->modes[0].name = vtr::strdup(default_name); mem_pb_type->modes[0].parent_pb_type = mem_pb_type; mem_pb_type->modes[0].index = 0; - mem_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1, - sizeof(t_mode_power)); + mem_pb_type->modes[0].mode_power = new t_mode_power(); num_pb = OPEN; for (i = 0; i < mem_pb_type->num_ports; i++) { if (mem_pb_type->ports[i].port_class != nullptr @@ -835,8 +768,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { } /* Allocate interconnect power structures */ - mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power(); i_inter++; } else { for (j = 0; j < num_pb; j++) { @@ -876,8 +808,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { } /* Allocate interconnect power structures */ - mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power(); i_inter++; } } @@ -944,7 +875,7 @@ void SyncModelsPbTypes_rec(t_arch* arch, pb_type->model_id = model_match_prim_id; vtr::t_linked_vptr* old = model_match_prim.pb_types; - model_match_prim.pb_types = (vtr::t_linked_vptr*)vtr::malloc(sizeof(vtr::t_linked_vptr)); + model_match_prim.pb_types = new vtr::t_linked_vptr; model_match_prim.pb_types->next = old; model_match_prim.pb_types->data_vptr = pb_type; @@ -1109,8 +1040,8 @@ const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_ty const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot]; InstPort annot_in(annot->input_pins); if (annot_in.port_name() == port->name) { - for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) { - if (annot->prop[iprop] == annot_type) { + for (const auto& [key, val] : annot->annotation_entries) { + if (key == annot_type) { return annot; } } @@ -1128,9 +1059,9 @@ const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb for (const auto& annot_out_str : vtr::split(annot->output_pins)) { InstPort out_pins(annot_out_str); if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) { - for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) { - if (annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MIN) { + for (const auto& [key, val] : annot->annotation_entries) { + if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) { return annot; } } diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 2e08c19694..bd7b1de863 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -335,19 +335,19 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { fprintf(Echo, "*************************************************\n"); fprintf(Echo, "Clock:\n"); if (arch->clocks) { - for (int i = 0; i < arch->clocks->num_global_clocks; i++) { - if (arch->clocks->clock_inf[i].autosize_buffer) { - fprintf(Echo, "\tClock[%d]: buffer_size auto C_wire %e", i + 1, - arch->clocks->clock_inf->C_wire); + for (size_t i = 0; i < arch->clocks->size(); i++) { + if ((*arch->clocks)[i].autosize_buffer) { + fprintf(Echo, "\tClock[%zu]: buffer_size auto C_wire %e", i + 1, + (*arch->clocks)[i].C_wire); } else { - fprintf(Echo, "\tClock[%d]: buffer_size %e C_wire %e", i + 1, - arch->clocks->clock_inf[i].buffer_size, - arch->clocks->clock_inf[i].C_wire); + fprintf(Echo, "\tClock[%zu]: buffer_size %e C_wire %e", i + 1, + (*arch->clocks)[i].buffer_size, + (*arch->clocks)[i].C_wire); } fprintf(Echo, "\t\t\t\tstat_prob %f switch_density %f period %e", - arch->clocks->clock_inf[i].prob, - arch->clocks->clock_inf[i].dens, - arch->clocks->clock_inf[i].period); + (*arch->clocks)[i].prob, + (*arch->clocks)[i].dens, + (*arch->clocks)[i].period); } } @@ -381,51 +381,45 @@ static void print_model(FILE* echo, const t_model& model) { } static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models) { - char* tabs; + std::string tabs = std::string(level, '\t'); - tabs = (char*)vtr::malloc((level + 1) * sizeof(char)); - for (int i = 0; i < level; i++) { - tabs[i] = '\t'; - } - tabs[level] = '\0'; - - fprintf(Echo, "%spb_type name: %s\n", tabs, pb_type->name); - fprintf(Echo, "%s\tblif_model: %s\n", tabs, pb_type->blif_model); - fprintf(Echo, "%s\tclass_type: %d\n", tabs, pb_type->class_type); - fprintf(Echo, "%s\tnum_modes: %d\n", tabs, pb_type->num_modes); - fprintf(Echo, "%s\tnum_ports: %d\n", tabs, pb_type->num_ports); + fprintf(Echo, "%spb_type name: %s\n", tabs.c_str(), pb_type->name); + fprintf(Echo, "%s\tblif_model: %s\n", tabs.c_str(), pb_type->blif_model); + fprintf(Echo, "%s\tclass_type: %d\n", tabs.c_str(), pb_type->class_type); + fprintf(Echo, "%s\tnum_modes: %d\n", tabs.c_str(), pb_type->num_modes); + fprintf(Echo, "%s\tnum_ports: %d\n", tabs.c_str(), pb_type->num_ports); for (int i = 0; i < pb_type->num_ports; i++) { - fprintf(Echo, "%s\tport %s type %d num_pins %d\n", tabs, + fprintf(Echo, "%s\tport %s type %d num_pins %d\n", tabs.c_str(), pb_type->ports[i].name, pb_type->ports[i].type, pb_type->ports[i].num_pins); } if (pb_type->num_modes > 0) { /*one or more modes*/ for (int i = 0; i < pb_type->num_modes; i++) { - fprintf(Echo, "%s\tmode %s:\n", tabs, pb_type->modes[i].name); + fprintf(Echo, "%s\tmode %s:\n", tabs.c_str(), pb_type->modes[i].name); for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { PrintPb_types_rec(Echo, &pb_type->modes[i].pb_type_children[j], level + 2, models); } for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) { - fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs, + fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs.c_str(), pb_type->modes[i].interconnect[j].type, pb_type->modes[i].interconnect[j].input_string, pb_type->modes[i].interconnect[j].output_string); for (int k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; k++) { - fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs, + fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs.c_str(), pb_type->modes[i].interconnect[j].annotations[k].input_pins, pb_type->modes[i].interconnect[j].annotations[k].output_pins, pb_type->modes[i].interconnect[j].annotations[k].format, - pb_type->modes[i].interconnect[j].annotations[k].value[0]); + pb_type->modes[i].interconnect[j].annotations[k].annotation_entries[0].second.c_str()); } //Print power info for interconnects if (pb_type->modes[i].interconnect[j].interconnect_power) { if (pb_type->modes[i].interconnect[j].interconnect_power->power_usage.dynamic || pb_type->modes[i].interconnect[j].interconnect_power->power_usage.leakage) { - fprintf(Echo, "%s\t\t\tpower %e %e\n", tabs, + fprintf(Echo, "%s\t\t\tpower %e %e\n", tabs.c_str(), pb_type->modes[i].interconnect[j].interconnect_power->power_usage.dynamic, pb_type->modes[i].interconnect[j].interconnect_power->power_usage.leakage); } @@ -442,20 +436,19 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c && pb_type_model_name != LogicalModels::MODEL_INPUT && pb_type_model_name != LogicalModels::MODEL_OUTPUT) { for (int k = 0; k < pb_type->num_annotations; k++) { - fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs, + fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs.c_str(), pb_type->annotations[k].clock, pb_type->annotations[k].input_pins, pb_type->annotations[k].output_pins, pb_type->annotations[k].format, - pb_type->annotations[k].value[0]); + pb_type->annotations[k].annotation_entries[0].second.c_str()); } } } if (pb_type->pb_type_power) { - PrintPb_types_recPower(Echo, pb_type, tabs); + PrintPb_types_recPower(Echo, pb_type, tabs.c_str()); } - free(tabs); } //Added May 2013 Daniel Chen, help dump arch info after loading from XML diff --git a/libs/libarchfpga/src/logic_types.cpp b/libs/libarchfpga/src/logic_types.cpp index ba7391bf40..b878c1f202 100644 --- a/libs/libarchfpga/src/logic_types.cpp +++ b/libs/libarchfpga/src/logic_types.cpp @@ -148,7 +148,7 @@ void LogicalModels::free_model_data(t_model& model) { while (vptr) { vtr::t_linked_vptr* vptr_prev = vptr; vptr = vptr->next; - vtr::free(vptr_prev); + delete vptr_prev; } if (model.instances) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index cef4e506eb..ac089efa44 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -43,7 +43,6 @@ #include "clock_types.h" //Forward declarations -struct t_clock_arch; struct t_clock_network; struct t_power_arch; struct t_interconnect_pins; @@ -407,12 +406,6 @@ struct t_grid_def { /************************* POWER ***********************************/ -/* Global clock architecture */ -struct t_clock_arch { - int num_global_clocks; - t_clock_network* clock_inf; /* Details about each clock */ -}; - /* Architecture information for a single clock */ struct t_clock_network { bool autosize_buffer; /* autosize clock buffers */ @@ -422,6 +415,15 @@ struct t_clock_network { float prob; /* Static probability of net assigned to this clock */ float dens; /* Switching density of net assigned to this clock */ float period; /* Period of clock */ + + t_clock_network() { + autosize_buffer = false; + buffer_size = 0.0f; + C_wire = 0.0f; + prob = 0.0f; + dens = 0.0f; + period = 0.0f; + } }; /* Power-related architecture information */ @@ -434,12 +436,26 @@ struct t_power_arch { float mux_transistor_size; float FF_size; float LUT_transistor_size; + + t_power_arch() { + C_wire_local = 0.0f; + logical_effort_factor = 0.0f; + local_interc_factor = 0.0f; + transistors_per_SRAM_bit = 0.0f; + mux_transistor_size = 0.0f; + FF_size = 0.0f; + LUT_transistor_size = 0.0f; + } }; /* Power usage for an entity */ struct t_power_usage { float dynamic; float leakage; + t_power_usage() { + dynamic = 0.0f; + leakage = 0.0f; + } }; /*************************************************************************************************/ @@ -534,6 +550,18 @@ struct t_port_power { t_port* scaled_by_port; int scaled_by_port_pin_idx; bool reverse_scaled; /* Scale by (1-prob) */ + + t_port_power() { + wire_type = (e_power_wire_type)0; + wire = {0.0f}; // Default to C = 0.0f + buffer_type = (e_power_buffer_type)0; + buffer_size = 0.0f; + pin_toggle_initialized = false; + energy_per_toggle = 0.0f; + scaled_by_port = nullptr; + scaled_by_port_pin_idx = 0; + reverse_scaled = false; + } }; /** @@ -1150,24 +1178,39 @@ struct t_mode { */ struct t_interconnect { enum e_interconnect type; - char* name = nullptr; + char* name; - char* input_string = nullptr; - char* output_string = nullptr; + char* input_string; + char* output_string; - t_pin_to_pin_annotation* annotations = nullptr; /* [0..num_annotations-1] */ - int num_annotations = 0; - bool infer_annotations = false; + t_pin_to_pin_annotation* annotations; /* [0..num_annotations-1] */ + int num_annotations; + bool infer_annotations; - int line_num = 0; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */ + int line_num; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */ - int parent_mode_index = 0; + int parent_mode_index; /* Power related members */ - t_mode* parent_mode = nullptr; + t_mode* parent_mode; - t_interconnect_power* interconnect_power = nullptr; + t_interconnect_power* interconnect_power; t_metadata_dict meta; + + t_interconnect() { + type = (e_interconnect)0; + name = nullptr; + input_string = nullptr; + output_string = nullptr; + annotations = nullptr; + num_annotations = 0; + infer_annotations = false; + line_num = 0; + parent_mode_index = 0; + parent_mode = nullptr; + interconnect_power = nullptr; + meta = t_metadata_dict(); + } }; /** Describes I/O and clock ports @@ -1205,6 +1248,22 @@ struct t_port { int absolute_first_pin_index; t_port_power* port_power; + + t_port() { + name = nullptr; + model_port = nullptr; + type = (PORTS)0; + is_clock = false; + is_non_clock_global = false; + num_pins = 0; + equivalent = (PortEquivalence)0; + parent_pb_type = nullptr; + port_class = nullptr; + index = 0; + port_index_by_type = 0; + absolute_first_pin_index = 0; + port_power = nullptr; + } }; struct t_pb_type_power { @@ -1231,6 +1290,15 @@ struct t_interconnect_power { int num_output_ports; int num_pins_per_port; float transistor_cnt; + + t_interconnect_power() { + power_usage = t_power_usage(); + port_info_initialized = false; + num_input_ports = 0; + num_output_ports = 0; + num_pins_per_port = 0; + transistor_cnt = 0.0f; + } }; struct t_interconnect_pins { @@ -1249,8 +1317,7 @@ struct t_mode_power { * This is later for additional information. * * Data Members: - * value: value/property pair - * prop: value/property pair + * annotation_entries: pairs of annotation subtypes and the annotation values * type: type of annotation * format: formatting of data * input_pins: input pins as string affected by annotation @@ -1258,9 +1325,8 @@ struct t_mode_power { * clock_pin: clock as string affected by annotation */ struct t_pin_to_pin_annotation { - char** value; /* [0..num_value_prop_pairs - 1] */ - int* prop; /* [0..num_value_prop_pairs - 1] */ - int num_value_prop_pairs; + + std::vector> annotation_entries; enum e_pin_to_pin_annotation_type type; enum e_pin_to_pin_annotation_format format; @@ -1270,6 +1336,17 @@ struct t_pin_to_pin_annotation { char* clock; int line_num; /* used to report what line number this annotation is found in architecture file */ + + t_pin_to_pin_annotation() { + annotation_entries = std::vector>(); + input_pins = nullptr; + output_pins = nullptr; + clock = nullptr; + + line_num = 0; + type = (e_pin_to_pin_annotation_type)0; + format = (e_pin_to_pin_annotation_format)0; + } }; /************************************************************************************************* @@ -2207,7 +2284,8 @@ struct t_arch { LogicalModels models; t_power_arch* power = nullptr; - t_clock_arch* clocks = nullptr; + + std::shared_ptr> clocks; //determine which layers in multi-die FPGAs require to build global routing resources std::vector layer_global_routing; diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index c2e476e500..7fc334b74f 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -233,7 +233,7 @@ static t_port get_generic_port(t_arch* arch, port.is_non_clock_global = false; port.model_port = nullptr; port.port_class = vtr::strdup(nullptr); - port.port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power)); + port.port_power = new t_port_power(); if (!model.empty()) port.model_port = get_model_port(arch, model, name); @@ -257,16 +257,12 @@ static bool block_port_exists(t_pb_type* pb_type, std::string port_name) { static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) { t_pin_to_pin_annotation pp; - pp.prop = (int*)vtr::calloc(1, sizeof(int)); - pp.value = (char**)vtr::calloc(1, sizeof(char*)); - pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN; pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT; - pp.prop[0] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME; - pp.value[0] = vtr::strdup(pp_name.c_str()); + pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name}); pp.input_pins = vtr::strdup(input.c_str()); pp.output_pins = vtr::strdup(output.c_str()); - pp.num_value_prop_pairs = 1; + pp.clock = nullptr; return pp; @@ -1307,7 +1303,7 @@ struct ArchReader { lut->model_id = LogicalModels::MODEL_NAMES_ID; lut->num_ports = 2; - lut->ports = (t_port*)vtr::calloc(lut->num_ports, sizeof(t_port)); + lut->ports = new t_port[lut->num_ports](); lut->ports[0] = get_generic_port(arch_, lut, IN_PORT, "in", LogicalModels::MODEL_NAMES, width); lut->ports[1] = get_generic_port(arch_, lut, OUT_PORT, "out", LogicalModels::MODEL_NAMES); @@ -1391,7 +1387,7 @@ struct ArchReader { port->name = is_input ? vtr::strdup(ipin.c_str()) : vtr::strdup(opin.c_str()); port->model_port = nullptr; port->port_class = vtr::strdup(nullptr); - port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power)); + port->port_power = new t_port_power(); } // OPAD mode @@ -1409,7 +1405,7 @@ struct ArchReader { num_ports = 1; opad->num_ports = num_ports; - opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + opad->ports = new t_port[num_ports](); opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT); opad->model_id = LogicalModels::MODEL_OUTPUT_ID; @@ -1431,7 +1427,7 @@ struct ArchReader { num_ports = 1; ipad->num_ports = num_ports; - ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + ipad->ports = new t_port[num_ports](); ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT); ipad->model_id = LogicalModels::MODEL_INPUT_ID; @@ -1558,7 +1554,7 @@ struct ArchReader { int num_ports = ic_count; leaf->num_ports = num_ports; - leaf->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + leaf->ports = new t_port[num_ports](); leaf->blif_model = vtr::strdup((std::string(".subckt ") + name).c_str()); leaf->model_id = get_model(arch_, name); @@ -2096,7 +2092,7 @@ struct ArchReader { pb_type->modes = new t_mode[pb_type->num_modes]; pb_type->num_ports = 2; - pb_type->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port)); + pb_type->ports = new t_port[pb_type->num_ports](); pb_type->num_output_pins = 2; pb_type->num_input_pins = 0; @@ -2132,7 +2128,7 @@ struct ArchReader { int num_ports = 1; leaf_pb_type->num_ports = num_ports; - leaf_pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + leaf_pb_type->ports = new t_port[num_ports](); leaf_pb_type->blif_model = vtr::strdup(const_cell.first.c_str()); leaf_pb_type->model_id = get_model(arch_, const_cell.first); diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index b684a9e834..0d2c4ae852 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -357,7 +357,7 @@ static void ProcessPower(pugi::xml_node parent, t_power_arch* power_arch, const pugiutil::loc_data& loc_data); -static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data); +static void ProcessClocks(pugi::xml_node Parent, std::vector& clocks, const pugiutil::loc_data& loc_data); static void ProcessPb_TypePowerEstMethod(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data); static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const pugiutil::loc_data& loc_data); @@ -517,10 +517,9 @@ void XmlReadArch(const char* ArchFile, /* This information still needs to be read, even if it is just * thrown away. */ - t_power_arch* power_arch_fake = (t_power_arch*)vtr::calloc(1, - sizeof(t_power_arch)); + t_power_arch* power_arch_fake = new t_power_arch(); ProcessPower(Next, power_arch_fake, loc_data); - free(power_arch_fake); + delete power_arch_fake; } } @@ -528,16 +527,13 @@ void XmlReadArch(const char* ArchFile, Next = get_single_child(architecture, "clocks", loc_data, POWER_REQD); if (Next) { if (arch->clocks) { - ProcessClocks(Next, arch->clocks, loc_data); + ProcessClocks(Next, *arch->clocks, loc_data); } else { /* This information still needs to be read, even if it is just * thrown away. */ - t_clock_arch* clocks_fake = (t_clock_arch*)vtr::calloc(1, - sizeof(t_clock_arch)); + std::vector clocks_fake; ProcessClocks(Next, clocks_fake, loc_data); - free(clocks_fake->clock_inf); - free(clocks_fake); } } @@ -886,9 +882,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, i = 1; } - annotation->num_value_prop_pairs = i; - annotation->prop = (int*)vtr::calloc(i, sizeof(int)); - annotation->value = (char**)vtr::calloc(i, sizeof(char*)); + annotation->annotation_entries.resize(i); annotation->line_num = loc_data.line(Parent); /* Todo: This is slow, I should use a case lookup */ i = 0; @@ -897,14 +891,12 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MAX, Prop}; i++; } Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MIN, Prop}; i++; } Prop = get_attribute(Parent, "in_port", loc_data).value(); @@ -917,13 +909,13 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX; Prop = get_attribute(Parent, "type", loc_data).value(); - annotation->value[i] = vtr::strdup(Parent.child_value()); + annotation->annotation_entries[i].second = Parent.child_value(); if (0 == strcmp(Prop, "max")) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX; + annotation->annotation_entries[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX; } else { VTR_ASSERT(0 == strcmp(Prop, "min")); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN; + annotation->annotation_entries[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN; } i++; @@ -937,8 +929,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "C", loc_data).value(); - annotation->value[i] = vtr::strdup(Prop); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C; + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_CAPACITANCE_C, Prop}; i++; Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); @@ -951,8 +942,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, } else if (0 == strcmp(Parent.name(), "C_matrix")) { annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE; annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX; - annotation->value[i] = vtr::strdup(Parent.child_value()); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C; + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_CAPACITANCE_C, Parent.child_value()}; i++; Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); @@ -966,9 +956,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "value", loc_data).value(); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_TSETUP; - annotation->value[i] = vtr::strdup(Prop); - + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_TSETUP, Prop}; i++; Prop = get_attribute(Parent, "port", loc_data).value(); annotation->input_pins = vtr::strdup(Prop); @@ -985,15 +973,13 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, bool found_min_max_attrib = false; if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX, Prop}; i++; found_min_max_attrib = true; } Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN, Prop}; i++; found_min_max_attrib = true; } @@ -1016,8 +1002,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "value", loc_data).value(); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_THOLD; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_THOLD, Prop}; i++; Prop = get_attribute(Parent, "port", loc_data).value(); @@ -1032,8 +1017,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "name", loc_data).value(); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, Prop}; i++; Prop = get_attribute(Parent, "in_port", loc_data).value(); @@ -1047,7 +1031,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, "Unknown port type %s in %s in %s", Parent.name(), Parent.parent().name(), Parent.parent().parent().name()); } - VTR_ASSERT(i == annotation->num_value_prop_pairs); + VTR_ASSERT(i == static_cast(annotation->annotation_entries.size())); } static void ProcessPb_TypePowerPinToggle(pugi::xml_node parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) { @@ -1285,7 +1269,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, const int num_out_ports = count_children(Parent, "output", loc_data, ReqOpt::OPTIONAL); const int num_clock_ports = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); const int num_ports = num_in_ports + num_out_ports + num_clock_ports; - pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + pb_type->ports = new t_port[num_ports](); pb_type->num_ports = num_ports; /* Enforce VPR's definition of LUT/FF by checking number of ports */ @@ -1300,7 +1284,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, } /* Initialize Power Structure */ - pb_type->pb_type_power = (t_pb_type_power*)vtr::calloc(1, sizeof(t_pb_type_power)); + pb_type->pb_type_power = new t_pb_type_power(); ProcessPb_TypePowerEstMethod(Parent, pb_type, loc_data); /* process ports */ @@ -1377,7 +1361,8 @@ static void ProcessPb_Type(pugi::xml_node Parent, num_annotations += count_children(Parent, child_name, loc_data, ReqOpt::OPTIONAL); } - pb_type->annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, sizeof(t_pin_to_pin_annotation)); + pb_type->annotations = new t_pin_to_pin_annotation[num_annotations](); + pb_type->num_annotations = num_annotations; int annotation_idx = 0; @@ -1461,7 +1446,7 @@ static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_powe const char* prop; bool wire_defined = false; - port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power)); + port->port_power = new t_port_power(); //Defaults if (power_method == POWER_METHOD_AUTO_SIZES) { @@ -1747,8 +1732,7 @@ static void ProcessInterconnect(vtr::string_internment& strings, num_annotations += count_children(Cur, annot_child_name, loc_data, ReqOpt::OPTIONAL); } - mode->interconnect[interconnect_idx].annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, - sizeof(t_pin_to_pin_annotation)); + mode->interconnect[interconnect_idx].annotations = new t_pin_to_pin_annotation[num_annotations](); mode->interconnect[interconnect_idx].num_annotations = num_annotations; int annotation_idx = 0; @@ -1767,8 +1751,7 @@ static void ProcessInterconnect(vtr::string_internment& strings, VTR_ASSERT(annotation_idx == num_annotations); /* Power */ - mode->interconnect[interconnect_idx].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + mode->interconnect[interconnect_idx].interconnect_power = new t_interconnect_power(); mode->interconnect[interconnect_idx].interconnect_power->port_info_initialized = false; /* get next iteration */ @@ -1848,7 +1831,7 @@ static void ProcessMode(pugi::xml_node Parent, } /* Allocate power structure */ - mode->mode_power = (t_mode_power*)vtr::calloc(1, sizeof(t_mode_power)); + mode->mode_power = new t_mode_power(); if (!implied_mode) { // Implied mode metadata is attached to the pb_type, rather than @@ -4716,32 +4699,26 @@ static void ProcessPower(pugi::xml_node parent, } /* Get the clock architecture */ -static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data) { +static void ProcessClocks(pugi::xml_node Parent, std::vector& clocks, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; const char* tmp; - clocks->num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); + int num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); - /* Alloc the clockdetails */ - clocks->clock_inf = nullptr; - if (clocks->num_global_clocks > 0) { - clocks->clock_inf = (t_clock_network*)vtr::malloc(clocks->num_global_clocks * sizeof(t_clock_network)); - memset(clocks->clock_inf, 0, - clocks->num_global_clocks * sizeof(t_clock_network)); - } + clocks.resize(num_global_clocks, t_clock_network()); /* Load the clock info. */ Node = get_first_child(Parent, "clock", loc_data); - for (int i = 0; i < clocks->num_global_clocks; ++i) { + for (int i = 0; i < num_global_clocks; ++i) { tmp = get_attribute(Node, "buffer_size", loc_data).value(); if (strcmp(tmp, "auto") == 0) { - clocks->clock_inf[i].autosize_buffer = true; + clocks[i].autosize_buffer = true; } else { - clocks->clock_inf[i].autosize_buffer = false; - clocks->clock_inf[i].buffer_size = (float)atof(tmp); + clocks[i].autosize_buffer = false; + clocks[i].buffer_size = (float)atof(tmp); } - clocks->clock_inf[i].C_wire = get_attribute(Node, "C_wire", loc_data).as_float(0); + clocks[i].C_wire = get_attribute(Node, "C_wire", loc_data).as_float(0); /* get the next clock item */ Node = Node.next_sibling(Node.name()); diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 676f6378bd..a78a4e3440 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -731,14 +731,16 @@ static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t if (!Arch->power) Arch->power = new t_power_arch(); - if (!Arch->clocks) - Arch->clocks = new t_clock_arch(); + if (!Arch->clocks) { + Arch->clocks = std::make_shared>(); + } device_ctx.clock_arch = Arch->clocks; + } else { Arch->power = nullptr; - Arch->clocks = nullptr; - device_ctx.clock_arch = nullptr; + Arch->clocks.reset(); + device_ctx.clock_arch.reset(); } } diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 414e6cda3c..b975ae4768 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -268,7 +268,7 @@ struct DeviceContext : public Context { /******************************************************************* * Clock Network ********************************************************************/ - t_clock_arch* clock_arch; + std::shared_ptr> clock_arch; /// @brief Name of rrgraph file read (if any). /// Used to determine if the specified rr-graph file is already loaded, diff --git a/vpr/src/pack/pb_type_graph_annotations.cpp b/vpr/src/pack/pb_type_graph_annotations.cpp index 6ce0878e56..b3a10a32a0 100644 --- a/vpr/src/pack/pb_type_graph_annotations.cpp +++ b/vpr/src/pack/pb_type_graph_annotations.cpp @@ -18,7 +18,7 @@ #include "pb_type_graph.h" #include "pb_type_graph_annotations.h" -static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const char* value); +static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const std::string& value); static void load_delay_annotations(const int line_num, t_pb_graph_node* pb_graph_node, @@ -37,7 +37,6 @@ static void inferr_unspecified_pb_graph_edge_delays(t_pb_graph_edge* pb_graph_pi static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, const char* clock, int line_num); void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { - int i, j, k, m; const t_pb_type* pb_type; t_pin_to_pin_annotation* annotations; @@ -46,21 +45,21 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { /* Load primitive critical path delays */ if (pb_type->is_primitive()) { annotations = pb_type->annotations; - for (i = 0; i < pb_type->num_annotations; i++) { + for (int i = 0; i < pb_type->num_annotations; i++) { if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) { - for (j = 0; j < annotations[i].num_value_prop_pairs; j++) { - if (annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MIN - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { + for (const auto& [key, val] : annotations[i].annotation_entries) { + if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN + || key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN + || key == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP + || key == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { load_delay_annotations(annotations[i].line_num, pb_graph_node, OPEN, - annotations[i].format, (enum e_pin_to_pin_delay_annotations)annotations[i].prop[j], + annotations[i].format, (enum e_pin_to_pin_delay_annotations)key, annotations[i].input_pins, annotations[i].output_pins, annotations[i].clock, - annotations[i].value[j]); + val.c_str()); } else { VTR_ASSERT(false); } @@ -69,35 +68,35 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { } } else { /* Load interconnect delays */ - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_interconnect; j++) { + for (int i = 0; i < pb_type->num_modes; i++) { + for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) { annotations = pb_type->modes[i].interconnect[j].annotations; - for (k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; k++) { + for (int k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; k++) { if (annotations[k].type == E_ANNOT_PIN_TO_PIN_DELAY) { - for (m = 0; m < annotations[k].num_value_prop_pairs; m++) { - if (annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_MIN - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { + for (const auto& [key, val] : annotations[k].annotation_entries) { + if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN + || key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN + || key == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP + || key == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { load_delay_annotations(annotations[k].line_num, pb_graph_node, i, annotations[k].format, - (enum e_pin_to_pin_delay_annotations)annotations[k].prop[m], + (enum e_pin_to_pin_delay_annotations)key, annotations[k].input_pins, annotations[k].output_pins, annotations[k].clock, - annotations[k].value[m]); + val.c_str()); } else { VTR_ASSERT(false); } } } else if (annotations[k].type == E_ANNOT_PIN_TO_PIN_PACK_PATTERN) { - VTR_ASSERT(annotations[k].num_value_prop_pairs == 1); + VTR_ASSERT(annotations[k].annotation_entries.size() == 1); load_pack_pattern_annotations(annotations[k].line_num, pb_graph_node, i, annotations[k].input_pins, annotations[k].output_pins, - annotations[k].value[0]); + annotations[k].annotation_entries[0].second); } else { /* Todo: * load_power_annotations(pb_graph_node); @@ -111,9 +110,9 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { inferr_unspecified_pb_graph_node_delays(pb_graph_node); //Recursively annotate child pb's - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { + for (int i = 0; i < pb_type->num_modes; i++) { + for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + for (int k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { load_pb_graph_pin_to_pin_annotations(&pb_graph_node->child_pb_graph_nodes[i][j][k]); } } @@ -123,7 +122,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { /* * Add the pattern name to the pack_pattern field for each pb_graph_edge that is used in a pack pattern */ -static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const char* value) { +static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const std::string& value) { int i, j, k, m, n, p, iedge; t_pb_graph_pin ***in_port, ***out_port; int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets; @@ -152,7 +151,7 @@ static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* p if (iedge != in_port[i][j]->num_output_edges) { in_port[i][j]->output_edges[iedge]->num_pack_patterns++; in_port[i][j]->output_edges[iedge]->pack_pattern_names.resize(in_port[i][j]->output_edges[iedge]->num_pack_patterns); - in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - 1] = value; + in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - 1] = value.c_str(); // TODO: convert to std::string } p++; } diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index 1b88e2e831..493740f515 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -81,7 +81,7 @@ static void power_usage_local_buffers_and_wires(t_power_usage* power_usage, /* Clock */ static void power_usage_clock(t_power_usage* power_usage, - t_clock_arch* clock_arch); + std::vector& clock_arch); static void power_usage_clock_single(t_power_usage* power_usage, t_clock_network* clock_inf); @@ -192,8 +192,8 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra Q_dens = pin_dens(pb, Q_pin, iblk); Q_prob = pin_prob(pb, Q_pin, iblk); - clk_prob = device_ctx.clock_arch->clock_inf[0].prob; - clk_dens = device_ctx.clock_arch->clock_inf[0].dens; + clk_prob = (*device_ctx.clock_arch)[0].prob; + clk_dens = (*device_ctx.clock_arch)[0].dens; power_usage_ff(&sub_power_usage, power_ctx.arch->FF_size, D_prob, D_dens, Q_prob, Q_dens, clk_prob, clk_dens, power_ctx.solution_inf.T_crit); @@ -645,8 +645,7 @@ static void power_usage_blocks(t_power_usage* power_usage) { * Calculates the total power usage from the clock network */ static void power_usage_clock(t_power_usage* power_usage, - t_clock_arch* clock_arch) { - int clock_idx; + std::vector& clock_arch) { auto& power_ctx = g_vpr_ctx.power(); /* Initialization */ @@ -654,27 +653,25 @@ static void power_usage_clock(t_power_usage* power_usage, power_usage->leakage = 0.; /* if no global clock, then return */ - if (clock_arch->num_global_clocks == 0) { + if (clock_arch.empty()) { return; } - for (clock_idx = 0; clock_idx < clock_arch->num_global_clocks; - clock_idx++) { + for (auto& clock : clock_arch) { t_power_usage clock_power; /* Assume the global clock is active even for combinational circuits */ - if (clock_arch->num_global_clocks == 1) { - if (clock_arch->clock_inf[clock_idx].dens == 0) { - clock_arch->clock_inf[clock_idx].dens = 2; - clock_arch->clock_inf[clock_idx].prob = 0.5; + if (clock_arch.size() == 1) { + if (clock.dens == 0) { + clock.dens = 2; + clock.prob = 0.5; // This will need to change for multi-clock - clock_arch->clock_inf[clock_idx].period = power_ctx.solution_inf.T_crit; + clock.period = power_ctx.solution_inf.T_crit; } } /* find the power dissipated by each clock network */ - power_usage_clock_single(&clock_power, - &clock_arch->clock_inf[clock_idx]); + power_usage_clock_single(&clock_power, &clock); power_add_usage(power_usage, &clock_power); } @@ -1734,7 +1731,7 @@ e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, co power_component_add_usage(&sub_power_usage, POWER_COMPONENT_ROUTING); /* Clock */ - power_usage_clock(&sub_power_usage, arch->clocks); + power_usage_clock(&sub_power_usage, *arch->clocks); power_add_usage(&total_power, &sub_power_usage); power_component_add_usage(&sub_power_usage, POWER_COMPONENT_CLOCK);